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Staging: xgifb: fix lots of sparse warnings
[net-next-2.6.git] / drivers / staging / xgifb / vb_init.c
CommitLineData
d7636e0b 1#include "vgatypes.h"
2
d7636e0b 3#include <linux/version.h>
4#include <linux/types.h>
5#include <linux/delay.h> /* udelay */
6#include "XGIfb.h"
d7636e0b 7
8#include "vb_def.h"
9#include "vb_struct.h"
10#include "vb_util.h"
11#include "vb_setmode.h"
12#include "vb_init.h"
13#include "vb_ext.h"
14
d7636e0b 15
d7636e0b 16#include <asm/io.h>
d7636e0b 17
18
19
20
8922967e 21static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
d7636e0b 22
82d6eb5b
BP		 23unsigned short XGINew_DRAMType[17][5] = {
24 {0x0C, 0x0A, 0x02, 0x40, 0x39}, {0x0D, 0x0A, 0x01, 0x40, 0x48},
25 {0x0C, 0x09, 0x02, 0x20, 0x35}, {0x0D, 0x09, 0x01, 0x20, 0x44},
26 {0x0C, 0x08, 0x02, 0x10, 0x31}, {0x0D, 0x08, 0x01, 0x10, 0x40},
27 {0x0C, 0x0A, 0x01, 0x20, 0x34}, {0x0C, 0x09, 0x01, 0x08, 0x32},
28 {0x0B, 0x08, 0x02, 0x08, 0x21}, {0x0C, 0x08, 0x01, 0x08, 0x30},
29 {0x0A, 0x08, 0x02, 0x04, 0x11}, {0x0B, 0x0A, 0x01, 0x10, 0x28},
30 {0x09, 0x08, 0x02, 0x02, 0x01}, {0x0B, 0x09, 0x01, 0x08, 0x24},
31 {0x0B, 0x08, 0x01, 0x04, 0x20}, {0x0A, 0x08, 0x01, 0x02, 0x10},
32 {0x09, 0x08, 0x01, 0x01, 0x00} };
33
8922967e 34static unsigned short XGINew_SDRDRAM_TYPE[13][5] = {
82d6eb5b
BP		 35 { 2, 12, 9, 64, 0x35},
36 { 1, 13, 9, 64, 0x44},
37 { 2, 12, 8, 32, 0x31},
38 { 2, 11, 9, 32, 0x25},
39 { 1, 12, 9, 32, 0x34},
40 { 1, 13, 8, 32, 0x40},
41 { 2, 11, 8, 16, 0x21},
42 { 1, 12, 8, 16, 0x30},
43 { 1, 11, 9, 16, 0x24},
44 { 1, 11, 8, 8, 0x20},
45 { 2, 9, 8, 4, 0x01},
46 { 1, 10, 8, 4, 0x10},
47 { 1, 9, 8, 2, 0x00} };
48
8922967e 49static unsigned short XGINew_DDRDRAM_TYPE[4][5] = {
82d6eb5b
BP		 50 { 2, 12, 9, 64, 0x35},
51 { 2, 12, 8, 32, 0x31},
52 { 2, 11, 8, 16, 0x21},
53 { 2, 9, 8, 4, 0x01} };
54
8922967e 55static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
82d6eb5b
BP		 56 { 2, 13, 9, 64, 0x45},
57 { 2, 12, 9, 32, 0x35},
58 { 2, 12, 8, 16, 0x31},
59 { 2, 11, 8, 8, 0x21} };
60
8922967e 61static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
82d6eb5b
BP		 62 { 2, 14, 11, 128, 0x5D},
63 { 2, 14, 10, 64, 0x59},
64 { 2, 13, 11, 64, 0x4D},
65 { 2, 14, 9, 32, 0x55},
66 { 2, 13, 10, 32, 0x49},
67 { 2, 12, 11, 32, 0x3D},
68 { 2, 14, 8, 16, 0x51},
69 { 2, 13, 9, 16, 0x45},
70 { 2, 12, 10, 16, 0x39},
71 { 2, 13, 8, 8, 0x41},
72 { 2, 12, 9, 8, 0x35},
73 { 2, 12, 8, 4, 0x31} };
d7636e0b 74
80adad85
BP		 75void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *);
76void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *, struct vb_device_info *);
77void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
78void XGINew_SetDRAMModeRegister(struct vb_device_info *);
e4147abe
BP		 79void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension);
80void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 81 unsigned long, struct vb_device_info *);
e4147abe 82unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 83 struct vb_device_info *pVBInfo);
e4147abe 84unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension);
d7636e0b 85
80adad85
BP		 86int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
87void XGINew_DisableRefresh(struct xgi_hw_device_info *, struct vb_device_info *) ;
88void XGINew_CheckBusWidth_310(struct vb_device_info *) ;
89int XGINew_SDRSizing(struct vb_device_info *);
90int XGINew_DDRSizing(struct vb_device_info *);
91void XGINew_EnableRefresh(struct xgi_hw_device_info *, struct vb_device_info *);
8922967e
RD		 92static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
93#if 0
94static unsigned long UNIROM;
95#endif
80adad85 96unsigned char ChkLFB(struct vb_device_info *);
82d6eb5b 97void XGINew_Delay15us(unsigned long);
e4147abe 98void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
82d6eb5b 99 unsigned long XGI_P3d4Port);
80adad85
BP		 100void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
101void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
e4147abe
BP		 102void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension);
103void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension);
80adad85
BP		 104void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
105void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
106void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
107unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo);
108void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
109unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo);
d7636e0b 110
8922967e 111static void DelayUS(unsigned long MicroSeconds)
d7636e0b 112{
113 udelay(MicroSeconds);
114}
f2f58e14 115
d7636e0b 116
117/* --------------------------------------------------------------------- */
118/* Function : XGIInitNew */
119/* Input : */
120/* Output : */
121/* Description : */
122/* --------------------------------------------------------------------- */
e4147abe 123unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
d7636e0b 124{
125
80adad85
BP		 126 struct vb_device_info VBINF;
127 struct vb_device_info *pVBInfo = &VBINF;
108afbf8 128 unsigned char i, temp = 0, temp1 ;
d7636e0b 129 // VBIOSVersion[ 5 ] ;
274afb73 130 volatile unsigned char *pVideoMemory;
d7636e0b 131
82d6eb5b 132 /* unsigned long j, k ; */
d7636e0b 133
1d9f9a9b 134 struct XGI_DSReg *pSR ;
d7636e0b 135
82d6eb5b 136 unsigned long Temp ;
d7636e0b 137
138 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
139
140 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
141
82d6eb5b 142 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
d7636e0b 143
274afb73 144 pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
d7636e0b 145
146
147// Newdebugcode( 0x99 ) ;
148
149
150 /* if ( pVBInfo->ROMAddr == 0 ) */
dda08c59 151 /* return( 0 ) ; */
d7636e0b 152
8922967e 153 if (pVBInfo->FBAddr == NULL) {
d7636e0b 154 printk("\n pVBInfo->FBAddr == 0 ");
dda08c59
BP		 155 return 0;
156 }
d7636e0b 157printk("1");
dda08c59
BP		 158if (pVBInfo->BaseAddr == 0) {
159 printk("\npVBInfo->BaseAddr == 0 ");
160 return 0;
d7636e0b 161}
162printk("2");
163
164 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
165
166 pVBInfo->ISXPDOS = 0 ;
167printk("3");
168
169if ( !HwDeviceExtension->bIntegratedMMEnabled )
dda08c59
BP		 170 return 0; /* alan */
171
d7636e0b 172printk("4");
173
d7636e0b 174 // VBIOSVersion[ 4 ] = 0x0 ;
175
176 /* 09/07/99 modify by domao */
177
178 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
179 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
180 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
181 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
182 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
183 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
184 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
185 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
186 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
187 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
188 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
189 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
190 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
191 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
192 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
193 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
194 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
195printk("5");
196
197 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
198 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
199
200 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
201
202 /* ReadVBIOSData */
203 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
204
205 /* 1.Openkey */
206 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
207printk("6");
208
209 /* GetXG21Sense (GPIO) */
210 if ( HwDeviceExtension->jChipType == XG21 )
211 {
212 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
213 }
214 if ( HwDeviceExtension->jChipType == XG27 )
215 {
216 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
217 }
218printk("7");
219
220 /* 2.Reset Extended register */
221
222 for( i = 0x06 ; i < 0x20 ; i++ )
223 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
224
225 for( i = 0x21 ; i <= 0x27 ; i++ )
226 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
227
228 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
229 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
230
231printk("8");
232
233 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
234 {
235 for( i = 0x31 ; i <= 0x3B ; i++ )
236 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
237 }
238 else
239 {
240 for( i = 0x31 ; i <= 0x3D ; i++ )
241 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
242 }
243printk("9");
244
245 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
246 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
247
248 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
249 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
250
251 for( i = 0x79 ; i <= 0x7C ; i++ )
252 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
253
254printk("10");
255
256 if ( HwDeviceExtension->jChipType >= XG20 )
257 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
258
259 /* 3.SetMemoryClock
260
261 if ( HwDeviceExtension->jChipType >= XG40 )
262 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
263
264 if ( HwDeviceExtension->jChipType < XG40 )
265 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
266
267printk("11");
268
269 /* 4.SetDefExt1Regs begin */
270 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
271 if ( HwDeviceExtension->jChipType == XG27 )
272 {
273 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
274 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
275 }
276 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
277 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
278 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
279 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
281 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
282 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
283
284 /* SR11 = 0x0F ; */
285 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
286
287printk("12");
288
289 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
290 {
291// /* Set AGP Rate */
292// temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
293// temp1 &= 0x02 ;
294// if ( temp1 == 0x02 )
295// {
296// XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
297// ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
298// XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
299// VendorID = XGINew_GetReg3( 0x0cfc ) ;
300// VendorID &= 0x0000FFFF ;
301// XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
302// GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
303// GraphicVendorID &= 0x0000FFFF;
304//
305// if ( ChipsetID == 0x7301039 )
306/// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
307//
308// ChipsetID &= 0x0000FFFF ;
309///
310// if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
311// {
312// if ( ChipsetID == 0x1106 )
313// {
314// if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
315// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
316// else
317// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
318// }
319// else
320// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
321// }
322// }
323
324printk("13");
325
326 if ( HwDeviceExtension->jChipType >= XG40 )
327 {
328 /* Set AGP customize registers (in SetDefAGPRegs) Start */
329 for( i = 0x47 ; i <= 0x4C ; i++ )
330 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
331
332 for( i = 0x70 ; i <= 0x71 ; i++ )
333 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
334
335 for( i = 0x74 ; i <= 0x77 ; i++ )
336 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
337 /* Set AGP customize registers (in SetDefAGPRegs) End */
338 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
339// XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
340// ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
341// if ( ChipsetID == 0x25308086 )
342// XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
343
344 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
345 Temp >>= 20 ;
346 Temp &= 0xF ;
347
348 if ( Temp == 1 )
349 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
350 }
351printk("14");
352
353 if ( HwDeviceExtension->jChipType < XG40 )
354 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
355 } /* != XG20 */
356
357 /* Set PCI */
358 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
359 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
360 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
361printk("15");
362
363 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
364 {
365 /* Set VB */
366 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
367 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
368 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
108afbf8
BP		 369 temp1 = (unsigned char)XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
370 temp = (unsigned char)((temp1 >> 4) & 0x0F);
d7636e0b 371
372
373 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
374
375printk("16");
376
377 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
378 } /* != XG20 */
379
380
381 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
382
383 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
384 {
385 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
386 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
387 }
388 else
389 {
390 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
391 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
392 }
393 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
394printk("17");
395
396/*
397 if ( HwDeviceExtension->jChipType >= XG40 )
398 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
399
400 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
401 {
402 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
403 {
404 if ( pVBInfo->IF_DEF_LVDS == 0 )
405 {
406 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
407 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
408 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
409 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
410 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
411 }
412
413 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
414 }
415 } /* != XG20 */
416printk("18");
417
418 if ( HwDeviceExtension->jChipType < XG40 )
419 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
420printk("181");
421
dda08c59
BP		 422if (HwDeviceExtension->bSkipSense == 0) {
423 printk("182");
d7636e0b 424
425 XGI_SenseCRT1(pVBInfo) ;
426
dda08c59 427 printk("183");
d7636e0b 428 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
dda08c59 429 pVBInfo->IF_DEF_CH7007 = 0;
d7636e0b 430 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
431 {
432printk("184");
433 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
434printk("185");
435
436 }
437 if ( HwDeviceExtension->jChipType == XG21 )
438 {
439printk("186");
440
441 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
442 temp = GetXG21FPBits( pVBInfo ) ;
443 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
444printk("187");
445
446 }
447 if ( HwDeviceExtension->jChipType == XG27 )
448 {
449 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
450 temp = GetXG27FPBits( pVBInfo ) ;
451 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
452 }
453 }
454printk("19");
455
456 if ( HwDeviceExtension->jChipType >= XG40 )
457 {
458 if ( HwDeviceExtension->jChipType >= XG40 )
459 {
460 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
461 }
462
463 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
464
dda08c59 465 if (HwDeviceExtension->bSkipDramSizing == 1) {
d7636e0b 466 pSR = HwDeviceExtension->pSR ;
467 if ( pSR!=NULL )
468 {
469 while( pSR->jIdx != 0xFF )
470 {
471 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
472 pSR++ ;
473 }
474 }
475 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
476 } /* SkipDramSizing */
477 else
478 {
d7636e0b 479{
480printk("20");
481
482 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
483}
484printk("21");
485
486 }
487 } /* XG40 */
488
489printk("22");
490
491
492 /* SetDefExt2Regs begin */
493/*
494 AGP = 1 ;
108afbf8 495 temp =(unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x3A) ;
d7636e0b 496 temp &= 0x30 ;
497 if ( temp == 0x30 )
498 AGP = 0 ;
499
500 if ( AGP == 0 )
501 *pVBInfo->pSR21 &= 0xEF ;
502
503 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
504 if ( AGP == 1 )
505 *pVBInfo->pSR22 &= 0x20 ;
506 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
507*/
508
509// base = 0x80000000 ;
510// OutPortLong( 0xcf8 , base ) ;
511// Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
512// if ( Temp == 0x1039 )
513// {
108afbf8 514 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char)((*pVBInfo->pSR22) & 0xFE));
d7636e0b 515// }
516// else
517// {
518// XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
519// }
520
521 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
522
523printk("23");
524
525
526 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
527 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
528
529printk("24");
530
531
532XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
533XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
534printk("25");
535
dda08c59 536return 1;
d7636e0b 537} /* end of init */
538
539
540
541
542
543/* ============== alan ====================== */
544
545/* --------------------------------------------------------------------- */
546/* Function : XGINew_GetXG20DRAMType */
547/* Input : */
548/* Output : */
549/* Description : */
550/* --------------------------------------------------------------------- */
e4147abe 551unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 552 struct vb_device_info *pVBInfo)
d7636e0b 553{
108afbf8 554 unsigned char data, temp;
d7636e0b 555
556 if ( HwDeviceExtension->jChipType < XG20 )
557 {
558 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
559 {
560 data = *pVBInfo->pSoftSetting & 0x07 ;
561 return( data ) ;
562 }
563 else
564 {
565 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
566
567 if ( data == 0 )
568 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
569
570 return( data ) ;
571 }
572 }
573 else if ( HwDeviceExtension->jChipType == XG27 )
574 {
575 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
576 {
577 data = *pVBInfo->pSoftSetting & 0x07 ;
578 return( data ) ;
579 }
580 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
581
582 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
583 data = 0 ; /*DDR*/
584 else
585 data = 1 ; /*DDRII*/
586 return( data ) ;
587 }
588 else if ( HwDeviceExtension->jChipType == XG21 )
589 {
590 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
591 DelayUS(800);
592 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
593 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
594// HOTPLUG_SUPPORT
595// for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
596 if ( temp & 0x01 ) /* DVI read GPIOH */
597 data = 1 ; /*DDRII*/
598 else
599 data = 0 ; /*DDR*/
600//~HOTPLUG_SUPPORT
601 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
602 return( data ) ;
603 }
604 else
605 {
606 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
607
608 if ( data == 1 )
609 data ++ ;
610
611 return( data );
612 }
613}
614
615
616/* --------------------------------------------------------------------- */
617/* Function : XGINew_Get310DRAMType */
618/* Input : */
619/* Output : */
620/* Description : */
621/* --------------------------------------------------------------------- */
8922967e 622static unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo)
d7636e0b 623{
108afbf8 624 unsigned char data ;
d7636e0b 625
626 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
627 /* index &= 07 ; */
628
629 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
630 data = *pVBInfo->pSoftSetting & 0x03 ;
631 else
632 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
633
634 return( data ) ;
635}
636
637
638
639/* --------------------------------------------------------------------- */
640/* Function : XGINew_Delay15us */
641/* Input : */
642/* Output : */
643/* Description : */
644/* --------------------------------------------------------------------- */
645/*
82d6eb5b 646void XGINew_Delay15us(unsigned long ulMicrsoSec)
d7636e0b 647{
648}
649*/
650
651
652/* --------------------------------------------------------------------- */
653/* Function : XGINew_SDR_MRS */
654/* Input : */
655/* Output : */
656/* Description : */
657/* --------------------------------------------------------------------- */
8922967e 658static void XGINew_SDR_MRS(struct vb_device_info *pVBInfo)
d7636e0b 659{
82d6eb5b 660 unsigned short data ;
d7636e0b 661
662 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
663 data &= 0x3F ; /* SR16 D7=0,D6=0 */
664 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
665 /* XGINew_Delay15us( 0x100 ) ; */
666 data |= 0x80 ; /* SR16 D7=1,D6=0 */
667 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
668 /* XGINew_Delay15us( 0x100 ) ; */
669}
670
671
672/* --------------------------------------------------------------------- */
673/* Function : XGINew_DDR1x_MRS_340 */
674/* Input : */
675/* Output : */
676/* Description : */
677/* --------------------------------------------------------------------- */
8922967e 678static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
d7636e0b 679{
680 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
681 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
682 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
683 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
684
685 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
686 {
687 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
688 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
689 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
690 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
691 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
692 }
693
694 DelayUS( 60 ) ;
695 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
696 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
697 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
698 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
699 DelayUS( 1000 ) ;
700 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
701 DelayUS( 500 ) ;
702 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
703 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
704 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
705 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
706 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
707}
708
709
710/* --------------------------------------------------------------------- */
711/* Function : XGINew_DDR2x_MRS_340 */
712/* Input : */
713/* Output : */
714/* Description : */
715/* --------------------------------------------------------------------- */
8922967e
RD		 716static void XGINew_DDR2x_MRS_340(unsigned long P3c4,
717 struct vb_device_info *pVBInfo)
d7636e0b 718{
719 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
720 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
721 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
722 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
723 DelayUS( 60 ) ;
724 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
725 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
726 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
727 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
728 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
729 DelayUS( 1000 ) ;
730 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
731 DelayUS( 500 ) ;
732 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
733 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
734 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
735 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
736 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
737 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
738}
739
740/* --------------------------------------------------------------------- */
741/* Function : XGINew_DDRII_Bootup_XG27 */
742/* Input : */
743/* Output : */
744/* Description : */
745/* --------------------------------------------------------------------- */
8922967e
RD		 746static void XGINew_DDRII_Bootup_XG27(
747 struct xgi_hw_device_info *HwDeviceExtension,
748 unsigned long P3c4,
749 struct vb_device_info *pVBInfo)
d7636e0b 750{
82d6eb5b 751 unsigned long P3d4 = P3c4 + 0x10 ;
d7636e0b 752 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
753 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
754
755 /* Set Double Frequency */
756 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
757 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
758
759 DelayUS( 200 ) ;
760
761 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
762 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
763 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
764 DelayUS( 15 ) ;
765 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
766 DelayUS( 15 ) ;
767
768 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
769 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
770 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
771 DelayUS( 15 ) ;
772 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
773 DelayUS( 15) ;
774
775 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
776 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
777 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
778 DelayUS( 30 ) ;
779 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
780 DelayUS( 15 ) ;
781
782 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
783 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
784 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
785 DelayUS( 30 ) ;
786 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
787 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
788 /* DelayUS( 15 ) ; */
789
790 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
791 DelayUS( 60 ) ;
792 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
793
794 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
795 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
796 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
797
798 DelayUS( 30 ) ;
799 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
800 DelayUS( 15 ) ;
801
802 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
803 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
804 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
805 DelayUS( 30 ) ;
806 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
807 DelayUS( 15 ) ;
808
809 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
810 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
811 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
812 DelayUS( 30 ) ;
813 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
814 DelayUS( 15 ) ;
815
816 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
817 DelayUS( 200 ) ;
818
819
820}
821/* --------------------------------------------------------------------- */
822/* Function : XGINew_DDR2_MRS_XG20 */
823/* Input : */
824/* Output : */
825/* Description : */
826/* --------------------------------------------------------------------- */
8922967e 827static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 828 unsigned long P3c4, struct vb_device_info *pVBInfo)
d7636e0b 829{
82d6eb5b 830 unsigned long P3d4 = P3c4 + 0x10 ;
d7636e0b 831
832 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
833 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
834
835 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
836
837 DelayUS( 200 ) ;
838 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
839 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
840 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
841 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
842
843 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
844 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
845 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
846 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
847
848 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
849 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
850 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
851 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
852
853 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
854 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
855 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
856 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
857 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
858
859 DelayUS( 15 ) ;
860 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
861 DelayUS( 30 ) ;
862 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
863 DelayUS( 100 ) ;
864
865 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
866 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
867 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
868 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
869 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
870
871 DelayUS( 200 ) ;
872}
873
8922967e 874#if 0
d7636e0b 875/* --------------------------------------------------------------------- */
876/* Function : XGINew_DDR2_MRS_XG20 */
877/* Input : */
878/* Output : */
879/* Description : */
880/* --------------------------------------------------------------------- */
8922967e 881static void XGINew_DDR2_MRS_XG27(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 882 unsigned long P3c4, struct vb_device_info *pVBInfo)
d7636e0b 883{
82d6eb5b 884 unsigned long P3d4 = P3c4 + 0x10 ;
d7636e0b 885
886 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
887 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
888
889 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
890 DelayUS( 200 ) ;
891 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
892 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
893
894 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
895 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
896 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
897
898 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
899 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
900
901 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
902 DelayUS( 15 ) ; ////06/11/22 XG27 A0
903 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
904
905
906 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
907 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
908
909 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
910 DelayUS( 15 ) ; ////06/11/22 XG27 A0
911 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
912
913 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
914 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
915
916 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
917 DelayUS( 15 ) ; ////06/11/23 XG27 A0
918 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
919
920 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
921 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
922 DelayUS( 60 ) ;
923 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
924
925
926 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
927 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
928
929 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
930 DelayUS( 30 ) ;
931 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
932
933 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
934 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
935
936 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
937 DelayUS( 30 ) ;
938 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
939
940 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
941 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
942
943 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
944 DelayUS( 30 ) ;
945 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
946
947 DelayUS( 15 ) ; ////Start Auto-PreCharge
948 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
949 DelayUS( 200 ) ;
950 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
951
952}
8922967e 953#endif
d7636e0b 954
955/* --------------------------------------------------------------------- */
956/* Function : XGINew_DDR1x_DefaultRegister */
957/* Input : */
958/* Output : */
959/* Description : */
960/* --------------------------------------------------------------------- */
8922967e
RD		 961static void XGINew_DDR1x_DefaultRegister(
962 struct xgi_hw_device_info *HwDeviceExtension,
963 unsigned long Port,
964 struct vb_device_info *pVBInfo)
d7636e0b 965{
82d6eb5b 966 unsigned long P3d4 = Port ,
d7636e0b 967 P3c4 = Port - 0x10 ;
968
969 if ( HwDeviceExtension->jChipType >= XG20 )
970 {
971 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
972 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
973 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
974 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
975
976 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
977 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
978
979 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
980 }
981 else
982 {
983 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
984
985 switch( HwDeviceExtension->jChipType )
986 {
987 case XG41:
988 case XG42:
989 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
990 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
991 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
992 break ;
993 default:
994 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
995 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
996 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
997 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
998 XGINew_GetReg1( P3d4 , 0x86 ) ;
999 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1000 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1001 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1002 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1003 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1004 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1005 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1006 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1007 break ;
1008 }
1009
1010 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1011 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1012 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1013 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1014 }
1015}
1016
8922967e 1017#if 0
d7636e0b 1018/* --------------------------------------------------------------------- */
1019/* Function : XGINew_DDR2x_DefaultRegister */
1020/* Input : */
1021/* Output : */
1022/* Description : */
1023/* --------------------------------------------------------------------- */
8922967e
RD		 1024static void XGINew_DDR2x_DefaultRegister(
1025 struct xgi_hw_device_info *HwDeviceExtension,
1026 unsigned long Port,
1027 struct vb_device_info *pVBInfo)
d7636e0b 1028{
82d6eb5b 1029 unsigned long P3d4 = Port ,
d7636e0b 1030 P3c4 = Port - 0x10 ;
1031
1032 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1033
1034 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1035 switch( HwDeviceExtension->jChipType )
1036 {
1037 case XG41:
1038 case XG42:
1039 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1040 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1041 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1042 break ;
1043 default:
1044 /* keep following setting sequence, each setting in the same reg insert idle */
1045 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1046 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1047 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1048 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1049 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1050 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1051 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1052 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1053 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1054 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1055 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1056 }
1057 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1058 if ( HwDeviceExtension->jChipType == XG42 )
1059 {
1060 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1061 }
1062 else
1063 {
1064 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1065 }
1066 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1067
1068 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1069}
8922967e 1070#endif
d7636e0b 1071
1072/* --------------------------------------------------------------------- */
1073/* Function : XGINew_DDR2_DefaultRegister */
1074/* Input : */
1075/* Output : */
1076/* Description : */
1077/* --------------------------------------------------------------------- */
8922967e
RD		 1078static void XGINew_DDR2_DefaultRegister(
1079 struct xgi_hw_device_info *HwDeviceExtension,
1080 unsigned long Port,
1081 struct vb_device_info *pVBInfo)
d7636e0b 1082{
82d6eb5b 1083 unsigned long P3d4 = Port ,
d7636e0b 1084 P3c4 = Port - 0x10 ;
1085
1086 /* keep following setting sequence, each setting in the same reg insert idle */
1087 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1088 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1089 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1090 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1091 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1092 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1093 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1094 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1095 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1096 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1097 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1098 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1099 if ( HwDeviceExtension->jChipType == XG27 )
1100 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1101 else
1102 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1103
1104 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1105 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1106 if ( HwDeviceExtension->jChipType == XG27 )
1107 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1108 else
1109 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1110}
1111
1112
1113/* --------------------------------------------------------------------- */
1114/* Function : XGINew_SetDRAMDefaultRegister340 */
1115/* Input : */
1116/* Output : */
1117/* Description : */
1118/* --------------------------------------------------------------------- */
e4147abe 1119void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
80adad85 1120 unsigned long Port, struct vb_device_info *pVBInfo)
d7636e0b 1121{
108afbf8 1122 unsigned char temp, temp1, temp2, temp3 ,
d7636e0b 1123 i , j , k ;
1124
82d6eb5b 1125 unsigned long P3d4 = Port ,
d7636e0b 1126 P3c4 = Port - 0x10 ;
1127
1128 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1129 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1130 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1131 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1132
1133 temp2 = 0 ;
1134 for( i = 0 ; i < 4 ; i++ )
1135 {
1136 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1137 for( j = 0 ; j < 4 ; j++ )
1138 {
1139 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1140 temp2 |= temp1 ;
1141 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1142 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1143 temp2 &= 0xF0 ;
1144 temp2 += 0x10 ;
1145 }
1146 }
1147
1148 temp2 = 0 ;
1149 for( i = 0 ; i < 4 ; i++ )
1150 {
1151 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1152 for( j = 0 ; j < 4 ; j++ )
1153 {
1154 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1155 temp2 |= temp1 ;
1156 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1157 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1158 temp2 &= 0xF0 ;
1159 temp2 += 0x10 ;
1160 }
1161 }
1162
1163 temp3 = 0 ;
1164 for( k = 0 ; k < 4 ; k++ )
1165 {
1166 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1167 temp2 = 0 ;
1168 for( i = 0 ; i < 8 ; i++ )
1169 {
1170 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1171 for( j = 0 ; j < 4 ; j++ )
1172 {
1173 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1174 temp2 |= temp1 ;
1175 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1176 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1177 temp2 &= 0xF8 ;
1178 temp2 += 0x08 ;
1179 }
1180 }
1181 temp3 += 0x01 ;
1182 }
1183
1184 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1185 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1186
1187 temp2 = 0x80 ;
1188 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1189 for( j = 0 ; j < 4 ; j++ )
1190 {
1191 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1192 temp2 |= temp1 ;
1193 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1194 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1195 temp2 &= 0xF0 ;
1196 temp2 += 0x10 ;
1197 }
1198
1199 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1200 temp1 = temp & 0x03 ;
1201 temp2 |= temp1 ;
1202 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1203
1204 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1205 temp1 = temp & 0x0F ;
1206 temp2 = ( temp >> 4 ) & 0x07 ;
1207 temp3 = temp & 0x80 ;
1208 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1209 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1210 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1211 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1212
1213 if ( HwDeviceExtension->jChipType == XG27 )
1214 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1215
1216 for( j = 0 ; j <= 6 ; j++ )
1217 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1218
1219 for( j = 0 ; j <= 2 ; j++ )
1220 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1221
1222 for( j = 0 ; j < 2 ; j++ )
1223 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1224
1225 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1226 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1227
1228 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1229
1230 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1231 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1232 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1233 if ( XGINew_RAMType )
1234 {
1235 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1236 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1237 if ( HwDeviceExtension->jChipType == XG27 )
1238 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1239
1240 }
1241 else
1242 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1243 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1244
1245 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1246 if( temp == 0 )
1247 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1248 else
1249 {
1250 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1251 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1252 }
1253 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1254}
1255
1256
1257/* --------------------------------------------------------------------- */
1258/* Function : XGINew_DDR_MRS */
1259/* Input : */
1260/* Output : */
1261/* Description : */
1262/* --------------------------------------------------------------------- */
8922967e 1263static void XGINew_DDR_MRS(struct vb_device_info *pVBInfo)
d7636e0b 1264{
82d6eb5b 1265 unsigned short data ;
d7636e0b 1266
274afb73 1267 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
d7636e0b 1268
1269 /* SR16 <- 1F,DF,2F,AF */
1270 /* yriver modified SR16 <- 0F,DF,0F,AF */
1271 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1272 data = pVideoMemory[ 0xFB ] ;
1273 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1274
1275 data &= 0x0F ;
1276 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1277 data |= 0xC0 ;
1278 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1279 data &= 0x0F ;
1280 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1281 data |= 0x80 ;
1282 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1283 data &= 0x0F ;
1284 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1285 data |= 0xD0 ;
1286 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1287 data &= 0x0F ;
1288 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1289 data |= 0xA0 ;
1290 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1291/*
1292 else {
1293 data &= 0x0F;
1294 data |= 0x10;
1295 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1296
1297 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1298 {
1299 data &= 0x0F;
1300 }
1301
1302 data |= 0xC0;
1303 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1304
1305
1306 data &= 0x0F;
1307 data |= 0x20;
1308 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1309 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1310 {
1311 data &= 0x0F;
1312 }
1313
1314 data |= 0x80;
1315 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1316 }
1317*/
1318}
1319
1320
1321/* check if read cache pointer is correct */
1322
1323
1324
1325/* --------------------------------------------------------------------- */
1326/* Function : XGINew_VerifyMclk */
1327/* Input : */
1328/* Output : */
1329/* Description : */
1330/* --------------------------------------------------------------------- */
8922967e
RD		 1331static void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension,
1332 struct vb_device_info *pVBInfo)
d7636e0b 1333{
274afb73 1334 unsigned char *pVideoMemory = pVBInfo->FBAddr ;
108afbf8 1335 unsigned char i, j ;
82d6eb5b 1336 unsigned short Temp , SR21 ;
d7636e0b 1337
1338 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1339 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1340
1341 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1342 {
1343 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1344 {
1345 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1346 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1347 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1348
1349 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1350 Temp |= 0x01 ; /* MCLK reset */
1351
1352
1353 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1354 Temp &= 0xFE ; /* MCLK normal operation */
1355
1356 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1357
1358 pVideoMemory[ 16 + j ] = j ;
1359 if ( pVideoMemory[ 16 + j ] == j )
1360 {
1361 pVideoMemory[ j ] = j ;
1362 break ;
1363 }
1364 }
1365 }
1366}
1367
1368
1369
1370
1371
1372/* --------------------------------------------------------------------- */
1373/* Function : XGINew_SetDRAMSize_340 */
1374/* Input : */
1375/* Output : */
1376/* Description : */
1377/* --------------------------------------------------------------------- */
80adad85 1378void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 1379{
82d6eb5b 1380 unsigned short data ;
d7636e0b 1381
1382 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1383 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1384
1385 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1386
1387
1388 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
82d6eb5b 1389 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
d7636e0b 1390 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1391
1392 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1393 /*data |= 0x20 ;*/
1394 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1395 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1396 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
82d6eb5b 1397 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
d7636e0b 1398}
1399
1400
1401/* --------------------------------------------------------------------- */
1402/* Function : */
1403/* Input : */
1404/* Output : */
1405/* Description : */
1406/* --------------------------------------------------------------------- */
80adad85 1407void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 1408{
82d6eb5b 1409 unsigned short data ;
d7636e0b 1410 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1411 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1412#ifdef XGI301
1413 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1414#endif
1415
1416#ifdef XGI302 /* alan,should change value */
1417 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1418 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1419 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1420#endif
1421
1422 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1423
1424 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
82d6eb5b 1425 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
d7636e0b 1426
1427 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1428 data |= 0x20 ;
1429 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1430
1431 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1432
1433
82d6eb5b 1434 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short)(data | 0x0F)); /* assume lowest speed DRAM */
d7636e0b 1435
1436 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1437 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1438 XGINew_CheckBusWidth_310( pVBInfo) ;
1439 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1440
1441
1442
1443 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1444 {
1445 XGINew_SDRSizing( pVBInfo ) ;
1446 }
1447 else
1448 {
1449 XGINew_DDRSizing( pVBInfo) ;
1450 }
1451
1452
1453
1454
82d6eb5b 1455 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
d7636e0b 1456
1457 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1458 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
82d6eb5b 1459 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
d7636e0b 1460}
1461
1462
1463
1464/* --------------------------------------------------------------------- */
1465/* Function : XGINew_SetDRAMModeRegister340 */
1466/* Input : */
1467/* Output : */
1468/* Description : */
1469/* --------------------------------------------------------------------- */
1470
e4147abe 1471void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension)
d7636e0b 1472{
108afbf8 1473 unsigned char data ;
80adad85
BP		 1474 struct vb_device_info VBINF;
1475 struct vb_device_info *pVBInfo = &VBINF;
d7636e0b 1476 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1477 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
82d6eb5b 1478 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
d7636e0b 1479 pVBInfo->ISXPDOS = 0 ;
1480
1481 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1482 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1483 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1484 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1485 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1486 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1487 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1488 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1489 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1490 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1491 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1492 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1493 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1494 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1495 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1496 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1497 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1498 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1499 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1500
1501 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1502
1503 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1504
1505 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1506 {
1507 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1508 if ( data == 0x01 )
1509 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1510 else
1511 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1512 }
1513 else
1514 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1515
1516 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1517}
1518
1519/* --------------------------------------------------------------------- */
1520/* Function : XGINew_SetDRAMModeRegister */
1521/* Input : */
1522/* Output : */
1523/* Description : */
1524/* --------------------------------------------------------------------- */
80adad85 1525void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo)
d7636e0b 1526{
1527 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1528 {
1529 XGINew_SDR_MRS(pVBInfo ) ;
1530 }
1531 else
1532 {
1533 /* SR16 <- 0F,CF,0F,8F */
1534 XGINew_DDR_MRS( pVBInfo ) ;
1535 }
1536}
1537
1538
1539/* --------------------------------------------------------------------- */
1540/* Function : XGINew_DisableRefresh */
1541/* Input : */
1542/* Output : */
1543/* Description : */
1544/* --------------------------------------------------------------------- */
80adad85 1545void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 1546{
82d6eb5b 1547 unsigned short data ;
d7636e0b 1548
1549
1550 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1551 data &= 0xF8 ;
1552 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1553
1554}
1555
1556
1557/* --------------------------------------------------------------------- */
1558/* Function : XGINew_EnableRefresh */
1559/* Input : */
1560/* Output : */
1561/* Description : */
1562/* --------------------------------------------------------------------- */
80adad85 1563void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 1564{
1565
1566 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1567
1568
1569}
1570
1571
1572/* --------------------------------------------------------------------- */
1573/* Function : XGINew_DisableChannelInterleaving */
1574/* Input : */
1575/* Output : */
1576/* Description : */
1577/* --------------------------------------------------------------------- */
8922967e 1578static void XGINew_DisableChannelInterleaving(int index,
82d6eb5b 1579 unsigned short XGINew_DDRDRAM_TYPE[][5],
80adad85 1580 struct vb_device_info *pVBInfo)
d7636e0b 1581{
82d6eb5b 1582 unsigned short data ;
d7636e0b 1583
1584 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1585 data &= 0x1F ;
1586
1587 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1588 {
1589 case 64:
1590 data |= 0 ;
1591 break ;
1592 case 32:
1593 data |= 0x20 ;
1594 break ;
1595 case 16:
1596 data |= 0x40 ;
1597 break ;
1598 case 4:
1599 data |= 0x60 ;
1600 break ;
1601 default:
1602 break ;
1603 }
1604 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1605}
1606
1607
1608/* --------------------------------------------------------------------- */
1609/* Function : XGINew_SetDRAMSizingType */
1610/* Input : */
1611/* Output : */
1612/* Description : */
1613/* --------------------------------------------------------------------- */
8922967e 1614static void XGINew_SetDRAMSizingType(int index,
82d6eb5b 1615 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1616 struct vb_device_info *pVBInfo)
d7636e0b 1617{
82d6eb5b 1618 unsigned short data;
d7636e0b 1619
1620 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1621 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1622 DelayUS( 15 ) ;
1623 /* should delay 50 ns */
1624}
1625
1626
1627/* --------------------------------------------------------------------- */
1628/* Function : XGINew_CheckBusWidth_310 */
1629/* Input : */
1630/* Output : */
1631/* Description : */
1632/* --------------------------------------------------------------------- */
80adad85 1633void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo)
d7636e0b 1634{
82d6eb5b 1635 unsigned short data ;
fc3678a6 1636 volatile unsigned long *pVideoMemory ;
d7636e0b 1637
fc3678a6 1638 pVideoMemory = (unsigned long *) pVBInfo->FBAddr;
d7636e0b 1639
1640 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1641 {
1642 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1643 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1644 /* should delay */
1645 XGINew_SDR_MRS( pVBInfo ) ;
1646
1647 XGINew_ChannelAB = 0 ;
1648 XGINew_DataBusWidth = 128 ;
1649 pVideoMemory[ 0 ] = 0x01234567L ;
1650 pVideoMemory[ 1 ] = 0x456789ABL ;
1651 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1652 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1653 pVideoMemory[ 4 ] = 0x55555555L ;
1654 pVideoMemory[ 5 ] = 0x55555555L ;
1655 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1656 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1657
1658 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1659 {
1660 /* ChannelA64Bit */
1661 XGINew_DataBusWidth = 64 ;
1662 XGINew_ChannelAB = 0 ;
1663 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
82d6eb5b 1664 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (unsigned short)(data & 0xFD));
d7636e0b 1665 }
1666
1667 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1668 {
1669 /* ChannelB64Bit */
1670 XGINew_DataBusWidth = 64 ;
1671 XGINew_ChannelAB = 1 ;
1672 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
82d6eb5b
BP		 1673 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1674 (unsigned short)((data & 0xFD) | 0x01));
d7636e0b 1675 }
1676
1677 return ;
1678 }
1679 else
1680 {
1681 /* DDR Dual channel */
1682 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1683 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1684 /* should delay */
1685 XGINew_DDR_MRS( pVBInfo ) ;
1686
1687 XGINew_ChannelAB = 0 ;
1688 XGINew_DataBusWidth = 64 ;
1689 pVideoMemory[ 0 ] = 0x01234567L ;
1690 pVideoMemory[ 1 ] = 0x456789ABL ;
1691 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1692 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1693 pVideoMemory[ 4 ] = 0x55555555L ;
1694 pVideoMemory[ 5 ] = 0x55555555L ;
1695 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1696 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1697
1698 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1699 {
1700 if ( pVideoMemory[ 0 ] == 0x01234567L )
1701 {
1702 /* Channel A 64bit */
1703 return ;
1704 }
1705 }
1706 else
1707 {
1708 if ( pVideoMemory[ 0 ] == 0x01234567L )
1709 {
1710 /* Channel A 32bit */
1711 XGINew_DataBusWidth = 32 ;
1712 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1713 return ;
1714 }
1715 }
1716
1717 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1718 XGINew_DDR_MRS( pVBInfo);
1719
1720 XGINew_ChannelAB = 1 ;
1721 XGINew_DataBusWidth = 64 ;
1722 pVideoMemory[ 0 ] = 0x01234567L ;
1723 pVideoMemory[ 1 ] = 0x456789ABL ;
1724 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1725 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1726 pVideoMemory[ 4 ] = 0x55555555L ;
1727 pVideoMemory[ 5 ] = 0x55555555L ;
1728 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1729 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1730
1731 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1732 {
1733 /* Channel B 64 */
1734 if ( pVideoMemory[ 0 ] == 0x01234567L )
1735 {
1736 /* Channel B 64bit */
1737 return ;
1738 }
1739 else
1740 {
1741 /* error */
1742 }
1743 }
1744 else
1745 {
1746 if ( pVideoMemory[ 0 ] == 0x01234567L )
1747 {
1748 /* Channel B 32 */
1749 XGINew_DataBusWidth = 32 ;
1750 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1751 }
1752 else
1753 {
1754 /* error */
1755 }
1756 }
1757 }
1758}
1759
1760
1761/* --------------------------------------------------------------------- */
1762/* Function : XGINew_SetRank */
1763/* Input : */
1764/* Output : */
1765/* Description : */
1766/* --------------------------------------------------------------------- */
8922967e 1767static int XGINew_SetRank(int index,
108afbf8
BP		 1768 unsigned char RankNo,
1769 unsigned char XGINew_ChannelAB,
82d6eb5b 1770 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1771 struct vb_device_info *pVBInfo)
d7636e0b 1772{
82d6eb5b 1773 unsigned short data;
d7636e0b 1774 int RankSize ;
1775
1776 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1777 return 0 ;
1778
1779 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1780
1781 if ( ( RankNo * RankSize ) <= 128 )
1782 {
1783 data = 0 ;
1784
1785 while( ( RankSize >>= 1 ) > 0 )
1786 {
1787 data += 0x10 ;
1788 }
1789 data |= ( RankNo - 1 ) << 2 ;
1790 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1791 data |= XGINew_ChannelAB ;
1792 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1793 /* should delay */
1794 XGINew_SDR_MRS( pVBInfo ) ;
1795 return( 1 ) ;
1796 }
1797 else
1798 return( 0 ) ;
1799}
1800
1801
1802/* --------------------------------------------------------------------- */
1803/* Function : XGINew_SetDDRChannel */
1804/* Input : */
1805/* Output : */
1806/* Description : */
1807/* --------------------------------------------------------------------- */
8922967e 1808static int XGINew_SetDDRChannel(int index,
108afbf8
BP		 1809 unsigned char ChannelNo,
1810 unsigned char XGINew_ChannelAB,
82d6eb5b 1811 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1812 struct vb_device_info *pVBInfo)
d7636e0b 1813{
82d6eb5b 1814 unsigned short data;
d7636e0b 1815 int RankSize ;
1816
1817 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1818 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1819 if ( ChannelNo * RankSize <= 128 )
1820 {
1821 data = 0 ;
1822 while( ( RankSize >>= 1 ) > 0 )
1823 {
1824 data += 0x10 ;
1825 }
1826
1827 if ( ChannelNo == 2 )
1828 data |= 0x0C ;
1829
1830 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1831 data |= XGINew_ChannelAB ;
1832 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1833 /* should delay */
1834 XGINew_DDR_MRS( pVBInfo ) ;
1835 return( 1 ) ;
1836 }
1837 else
1838 return( 0 ) ;
1839}
1840
1841
1842/* --------------------------------------------------------------------- */
1843/* Function : XGINew_CheckColumn */
1844/* Input : */
1845/* Output : */
1846/* Description : */
1847/* --------------------------------------------------------------------- */
8922967e 1848static int XGINew_CheckColumn(int index,
82d6eb5b 1849 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1850 struct vb_device_info *pVBInfo)
d7636e0b 1851{
1852 int i ;
82d6eb5b 1853 unsigned long Increment , Position ;
d7636e0b 1854
1855 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1856 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1857
1858 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1859 {
fc3678a6
BP		 1860 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1861 Position += Increment ;
d7636e0b 1862 }
1863
d7636e0b 1864
1865 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1866 {
1867 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
fc3678a6
BP		 1868 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1869 return 0;
1870 Position += Increment;
d7636e0b 1871 }
1872 return( 1 ) ;
1873}
1874
1875
1876/* --------------------------------------------------------------------- */
1877/* Function : XGINew_CheckBanks */
1878/* Input : */
1879/* Output : */
1880/* Description : */
1881/* --------------------------------------------------------------------- */
8922967e 1882static int XGINew_CheckBanks(int index,
82d6eb5b 1883 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1884 struct vb_device_info *pVBInfo)
d7636e0b 1885{
1886 int i ;
82d6eb5b 1887 unsigned long Increment , Position ;
d7636e0b 1888
1889 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1890
1891 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1892 {
1893 /* pVBInfo->FBAddr[ Position ] = Position ; */
fc3678a6
BP		 1894 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1895 Position += Increment ;
d7636e0b 1896 }
1897
1898 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1899 {
1900 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
fc3678a6
BP		 1901 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1902 return 0;
1903 Position += Increment;
d7636e0b 1904 }
1905 return( 1 ) ;
1906}
1907
1908
1909/* --------------------------------------------------------------------- */
1910/* Function : XGINew_CheckRank */
1911/* Input : */
1912/* Output : */
1913/* Description : */
1914/* --------------------------------------------------------------------- */
8922967e 1915static int XGINew_CheckRank(int RankNo, int index,
82d6eb5b 1916 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1917 struct vb_device_info *pVBInfo)
d7636e0b 1918{
1919 int i ;
82d6eb5b 1920 unsigned long Increment , Position ;
d7636e0b 1921
1922 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1923 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1924
1925 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1926 {
1927 /* pVBInfo->FBAddr[ Position ] = Position ; */
fc3678a6
BP		 1928 /* *( (unsigned long *)( pVBInfo->FBAddr ) ) = Position ; */
1929 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1930 Position += Increment;
d7636e0b 1931 }
1932
1933 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1934 {
1935 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
fc3678a6
BP		 1936 /* if ( ( *(unsigned long *)( pVBInfo->FBAddr ) ) != Position ) */
1937 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1938 return 0;
1939 Position += Increment;
d7636e0b 1940 }
1941 return( 1 );
1942}
1943
1944
1945/* --------------------------------------------------------------------- */
1946/* Function : XGINew_CheckDDRRank */
1947/* Input : */
1948/* Output : */
1949/* Description : */
1950/* --------------------------------------------------------------------- */
8922967e 1951static int XGINew_CheckDDRRank(int RankNo, int index,
82d6eb5b 1952 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1953 struct vb_device_info *pVBInfo)
d7636e0b 1954{
82d6eb5b
BP		 1955 unsigned long Increment , Position ;
1956 unsigned short data ;
d7636e0b 1957
1958 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1959 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1960
1961 Increment += Increment / 2 ;
1962
1963 Position = 0;
fc3678a6
BP		 1964 *((unsigned long *)(pVBInfo->FBAddr + Position + 0)) = 0x01234567;
1965 *((unsigned long *)(pVBInfo->FBAddr + Position + 1)) = 0x456789AB;
1966 *((unsigned long *)(pVBInfo->FBAddr + Position + 2)) = 0x55555555;
1967 *((unsigned long *)(pVBInfo->FBAddr + Position + 3)) = 0x55555555;
1968 *((unsigned long *)(pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA;
1969 *((unsigned long *)(pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA;
d7636e0b 1970
fc3678a6
BP		 1971 if ((*(unsigned long *)(pVBInfo->FBAddr + 1)) == 0x456789AB)
1972 return 1;
1973
1974 if ((*(unsigned long *)(pVBInfo->FBAddr + 0)) == 0x01234567)
1975 return 0;
d7636e0b 1976
1977 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1978 data &= 0xF3 ;
1979 data |= 0x0E ;
1980 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1981 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1982 data += 0x20 ;
1983 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1984
1985 return( 1 ) ;
1986}
1987
1988
1989/* --------------------------------------------------------------------- */
1990/* Function : XGINew_CheckRanks */
1991/* Input : */
1992/* Output : */
1993/* Description : */
1994/* --------------------------------------------------------------------- */
8922967e 1995static int XGINew_CheckRanks(int RankNo, int index,
82d6eb5b 1996 unsigned short DRAMTYPE_TABLE[][5],
80adad85 1997 struct vb_device_info *pVBInfo)
d7636e0b 1998{
1999 int r ;
2000
2001 for( r = RankNo ; r >= 1 ; r-- )
2002 {
2003 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2004 return( 0 ) ;
2005 }
2006
2007 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2008 return( 0 ) ;
2009
2010 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2011 return( 0 ) ;
2012
2013 return( 1 ) ;
2014}
2015
2016
2017/* --------------------------------------------------------------------- */
2018/* Function : XGINew_CheckDDRRanks */
2019/* Input : */
2020/* Output : */
2021/* Description : */
2022/* --------------------------------------------------------------------- */
8922967e 2023static int XGINew_CheckDDRRanks(int RankNo, int index,
82d6eb5b 2024 unsigned short DRAMTYPE_TABLE[][5],
80adad85 2025 struct vb_device_info *pVBInfo)
d7636e0b 2026{
2027 int r ;
2028
2029 for( r = RankNo ; r >= 1 ; r-- )
2030 {
2031 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2032 return( 0 ) ;
2033 }
2034
2035 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2036 return( 0 ) ;
2037
2038 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2039 return( 0 ) ;
2040
2041 return( 1 ) ;
2042}
2043
2044
2045/* --------------------------------------------------------------------- */
2046/* Function : */
2047/* Input : */
2048/* Output : */
2049/* Description : */
2050/* --------------------------------------------------------------------- */
80adad85 2051int XGINew_SDRSizing(struct vb_device_info *pVBInfo)
d7636e0b 2052{
2053 int i ;
108afbf8 2054 unsigned char j ;
d7636e0b 2055
2056 for( i = 0 ; i < 13 ; i++ )
2057 {
2058 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2059
2060 for( j = 2 ; j > 0 ; j-- )
2061 {
108afbf8
BP		 2062 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB,
2063 XGINew_SDRDRAM_TYPE, pVBInfo))
d7636e0b 2064 continue ;
2065 else
2066 {
2067 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2068 return( 1 ) ;
2069 }
2070 }
2071 }
2072 return( 0 ) ;
2073}
2074
2075
2076/* --------------------------------------------------------------------- */
2077/* Function : XGINew_SetDRAMSizeReg */
2078/* Input : */
2079/* Output : */
2080/* Description : */
2081/* --------------------------------------------------------------------- */
8922967e 2082static unsigned short XGINew_SetDRAMSizeReg(int index,
82d6eb5b 2083 unsigned short DRAMTYPE_TABLE[][5],
80adad85 2084 struct vb_device_info *pVBInfo)
d7636e0b 2085{
82d6eb5b 2086 unsigned short data = 0 , memsize = 0;
d7636e0b 2087 int RankSize ;
108afbf8 2088 unsigned char ChannelNo ;
d7636e0b 2089
2090 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2091 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2092 data &= 0x80 ;
2093
2094 if ( data == 0x80 )
2095 RankSize *= 2 ;
2096
2097 data = 0 ;
2098
2099 if( XGINew_ChannelAB == 3 )
2100 ChannelNo = 4 ;
2101 else
2102 ChannelNo = XGINew_ChannelAB ;
2103
2104 if ( ChannelNo * RankSize <= 256 )
2105 {
2106 while( ( RankSize >>= 1 ) > 0 )
2107 {
2108 data += 0x10 ;
2109 }
2110
2111 memsize = data >> 4 ;
2112
2113 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2114 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2115
2116 /* data |= XGINew_ChannelAB << 2 ; */
2117 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2118 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2119
2120 /* should delay */
2121 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2122 }
2123 return( memsize ) ;
2124}
2125
2126
2127/* --------------------------------------------------------------------- */
2128/* Function : XGINew_SetDRAMSize20Reg */
2129/* Input : */
2130/* Output : */
2131/* Description : */
2132/* --------------------------------------------------------------------- */
8922967e 2133static unsigned short XGINew_SetDRAMSize20Reg(int index,
82d6eb5b 2134 unsigned short DRAMTYPE_TABLE[][5],
80adad85 2135 struct vb_device_info *pVBInfo)
d7636e0b 2136{
82d6eb5b 2137 unsigned short data = 0 , memsize = 0;
d7636e0b 2138 int RankSize ;
108afbf8 2139 unsigned char ChannelNo ;
d7636e0b 2140
2141 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2142 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2143 data &= 0x80 ;
2144
2145 if ( data == 0x80 )
2146 RankSize *= 2 ;
2147
2148 data = 0 ;
2149
2150 if( XGINew_ChannelAB == 3 )
2151 ChannelNo = 4 ;
2152 else
2153 ChannelNo = XGINew_ChannelAB ;
2154
2155 if ( ChannelNo * RankSize <= 256 )
2156 {
2157 while( ( RankSize >>= 1 ) > 0 )
2158 {
2159 data += 0x10 ;
2160 }
2161
2162 memsize = data >> 4 ;
2163
2164 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2165 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2166 DelayUS( 15 ) ;
2167
2168 /* data |= XGINew_ChannelAB << 2 ; */
2169 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2170 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2171
2172 /* should delay */
2173 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2174 }
2175 return( memsize ) ;
2176}
2177
2178
2179/* --------------------------------------------------------------------- */
2180/* Function : XGINew_ReadWriteRest */
2181/* Input : */
2182/* Output : */
2183/* Description : */
2184/* --------------------------------------------------------------------- */
8922967e
RD		 2185static int XGINew_ReadWriteRest(unsigned short StopAddr,
2186 unsigned short StartAddr,
2187 struct vb_device_info *pVBInfo)
d7636e0b 2188{
2189 int i ;
82d6eb5b 2190 unsigned long Position = 0 ;
d7636e0b 2191
fc3678a6 2192 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
d7636e0b 2193
2194 for( i = StartAddr ; i <= StopAddr ; i++ )
2195 {
2196 Position = 1 << i ;
fc3678a6 2197 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
d7636e0b 2198 }
2199
2200 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2201
2202 Position = 0 ;
2203
fc3678a6
BP		 2204 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2205 return 0;
d7636e0b 2206
2207 for( i = StartAddr ; i <= StopAddr ; i++ )
2208 {
2209 Position = 1 << i ;
fc3678a6
BP		 2210 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2211 return 0;
d7636e0b 2212 }
2213 return( 1 ) ;
2214}
2215
2216
2217/* --------------------------------------------------------------------- */
2218/* Function : XGINew_CheckFrequence */
2219/* Input : */
2220/* Output : */
2221/* Description : */
2222/* --------------------------------------------------------------------- */
8922967e 2223static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
d7636e0b 2224{
108afbf8 2225 unsigned char data ;
d7636e0b 2226
2227 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2228
2229 if ( ( data & 0x10 ) == 0 )
2230 {
2231 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2232 data = ( data & 0x02 ) >> 1 ;
2233 return( data ) ;
2234 }
2235 else
2236 return( data & 0x01 ) ;
2237}
2238
2239
2240/* --------------------------------------------------------------------- */
2241/* Function : XGINew_CheckChannel */
2242/* Input : */
2243/* Output : */
2244/* Description : */
2245/* --------------------------------------------------------------------- */
8922967e
RD		 2246static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
2247 struct vb_device_info *pVBInfo)
d7636e0b 2248{
108afbf8 2249 unsigned char data;
d7636e0b 2250
2251 switch( HwDeviceExtension->jChipType )
2252 {
2253 case XG20:
2254 case XG21:
2255 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2256 data = data & 0x01;
2257 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2258
2259 if ( data == 0 ) /* Single_32_16 */
2260 {
2261
2262 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2263 {
2264
2265 XGINew_DataBusWidth = 32 ; /* 32 bits */
2266 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2267 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2268 DelayUS( 15 ) ;
2269
2270 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2271 return ;
2272
2273 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2274 {
2275 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2276 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2277 DelayUS( 15 ) ;
2278
2279 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2280 return ;
2281 }
2282 }
2283
2284 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2285 {
2286 XGINew_DataBusWidth = 16 ; /* 16 bits */
2287 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2288 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2289 DelayUS( 15 ) ;
2290
2291 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2292 return ;
2293 else
2294 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2295 DelayUS( 15 ) ;
2296 }
2297
2298 }
2299 else /* Dual_16_8 */
2300 {
2301 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2302 {
2303
2304 XGINew_DataBusWidth = 16 ; /* 16 bits */
2305 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2306 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2307 DelayUS( 15 ) ;
2308
2309 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2310 return ;
2311
2312 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2313 {
2314 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2315 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2316 DelayUS( 15 ) ;
2317
2318 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2319 return ;
2320 }
2321 }
2322
2323
2324 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2325 {
2326 XGINew_DataBusWidth = 8 ; /* 8 bits */
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2328 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2329 DelayUS( 15 ) ;
2330
2331 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2332 return ;
2333 else
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2335 DelayUS( 15 ) ;
2336 }
2337 }
2338 break ;
2339
2340 case XG27:
2341 XGINew_DataBusWidth = 16 ; /* 16 bits */
2342 XGINew_ChannelAB = 1 ; /* Single channel */
2343 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2344 break ;
2345 case XG41:
2346 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2347 {
2348 XGINew_DataBusWidth = 32 ; /* 32 bits */
2349 XGINew_ChannelAB = 3 ; /* Quad Channel */
2350 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2351 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2352
2353 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2354 return ;
2355
2356 XGINew_ChannelAB = 2 ; /* Dual channels */
2357 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2358
2359 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2360 return ;
2361
2362 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2363
2364 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2365 return ;
2366
2367 XGINew_ChannelAB = 3 ;
2368 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2370
2371 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2372 return ;
2373
2374 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2375
2376 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2377 return ;
2378 else
2379 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2380 }
2381 else
2382 { /* DDR */
2383 XGINew_DataBusWidth = 64 ; /* 64 bits */
2384 XGINew_ChannelAB = 2 ; /* Dual channels */
2385 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2386 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2387
2388 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2389 return ;
2390
2391 XGINew_ChannelAB = 1 ; /* Single channels */
2392 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2393
2394 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2395 return ;
2396
2397 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2398
2399 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2400 return ;
2401
2402 XGINew_ChannelAB = 2 ; /* Dual channels */
2403 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2404 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2405
2406 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2407 return ;
2408
2409 XGINew_ChannelAB = 1 ; /* Single channels */
2410 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2411
2412 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2413 return ;
2414 else
2415 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2416 }
2417
2418 break ;
2419
2420 case XG42:
2421/*
2422 XG42 SR14 D[3] Reserve
2423 D[2] = 1, Dual Channel
2424 = 0, Single Channel
2425
2426 It's Different from Other XG40 Series.
2427*/
2428 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2429 {
2430 XGINew_DataBusWidth = 32 ; /* 32 bits */
2431 XGINew_ChannelAB = 2 ; /* 2 Channel */
2432 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2433 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2434
2435 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2436 return ;
2437
2438 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2439 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2440 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2441 return ;
2442
2443 XGINew_ChannelAB = 1 ; /* Single Channel */
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2445 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2446
2447 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2448 return ;
2449 else
2450 {
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2452 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2453 }
2454 }
2455 else
2456 { /* DDR */
2457 XGINew_DataBusWidth = 64 ; /* 64 bits */
2458 XGINew_ChannelAB = 1 ; /* 1 channels */
2459 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2460 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2461
2462 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2463 return ;
2464 else
2465 {
2466 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2467 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2468 }
2469 }
2470
2471 break ;
2472
2473 default: /* XG40 */
2474
2475 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2476 {
2477 XGINew_DataBusWidth = 32 ; /* 32 bits */
2478 XGINew_ChannelAB = 3 ;
2479 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2480 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2481
2482 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2483 return ;
2484
2485 XGINew_ChannelAB = 2 ; /* 2 channels */
2486 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2487
2488 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2489 return ;
2490
2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2492 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2493
2494 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2495 XGINew_ChannelAB = 3 ; /* 4 channels */
2496 else
2497 {
2498 XGINew_ChannelAB = 2 ; /* 2 channels */
2499 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2500 }
2501 }
2502 else
2503 { /* DDR */
2504 XGINew_DataBusWidth = 64 ; /* 64 bits */
2505 XGINew_ChannelAB = 2 ; /* 2 channels */
2506 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2507 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2508
2509 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2510 return ;
2511 else
2512 {
2513 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2514 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2515 }
2516 }
2517 break ;
2518 }
2519}
2520
2521
2522/* --------------------------------------------------------------------- */
2523/* Function : XGINew_DDRSizing340 */
2524/* Input : */
2525/* Output : */
2526/* Description : */
2527/* --------------------------------------------------------------------- */
80adad85 2528int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 2529{
2530 int i ;
82d6eb5b 2531 unsigned short memsize , addr ;
d7636e0b 2532
2533 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2534 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2535 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2536
2537
2538 if ( HwDeviceExtension->jChipType >= XG20 )
2539 {
2540 for( i = 0 ; i < 12 ; i++ )
2541 {
2542 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2543 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2544 if ( memsize == 0 )
2545 continue ;
2546
2547 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
82d6eb5b 2548 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr))
d7636e0b 2549 continue ;
2550
2551 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2552 return( 1 ) ;
2553 }
2554 }
2555 else
2556 {
2557 for( i = 0 ; i < 4 ; i++ )
2558 {
2559 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2560 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2561
2562 if ( memsize == 0 )
2563 continue ;
2564
2565 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
82d6eb5b 2566 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr))
d7636e0b 2567 continue ;
2568
2569 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2570 return( 1 ) ;
2571 }
2572 }
2573 return( 0 ) ;
2574}
2575
2576
2577/* --------------------------------------------------------------------- */
2578/* Function : XGINew_DDRSizing */
2579/* Input : */
2580/* Output : */
2581/* Description : */
2582/* --------------------------------------------------------------------- */
80adad85 2583int XGINew_DDRSizing(struct vb_device_info *pVBInfo)
d7636e0b 2584{
2585 int i ;
108afbf8 2586 unsigned char j ;
d7636e0b 2587
2588 for( i = 0 ; i < 4 ; i++ )
2589 {
2590 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2591 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2592 for( j = 2 ; j > 0 ; j-- )
2593 {
2594 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
108afbf8
BP		 2595 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB,
2596 XGINew_DDRDRAM_TYPE, pVBInfo))
d7636e0b 2597 continue ;
2598 else
2599 {
2600 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2601 return( 1 ) ;
2602 }
2603 }
2604 }
2605 return( 0 ) ;
2606}
2607
2608/* --------------------------------------------------------------------- */
2609/* Function : XGINew_SetMemoryClock */
2610/* Input : */
2611/* Output : */
2612/* Description : */
2613/* --------------------------------------------------------------------- */
80adad85 2614void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 2615{
2616
2617
2618 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2619 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2620 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2621
2622
2623
2624 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2625 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2626 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2627
2628 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2629 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2630 if ( HwDeviceExtension->jChipType == XG42 )
2631 {
2632 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2633 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2634 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
108afbf8 2635 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
d7636e0b 2636 }
2637}
2638
2639
2640/* --------------------------------------------------------------------- */
2641/* Function : ChkLFB */
2642/* Input : */
2643/* Output : */
2644/* Description : */
2645/* --------------------------------------------------------------------- */
80adad85 2646unsigned char ChkLFB(struct vb_device_info *pVBInfo)
d7636e0b 2647{
dda08c59
BP		 2648 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4 , 0x78))
2649 return 1;
2650 else
2651 return 0;
d7636e0b 2652}
2653
2654
2655/* --------------------------------------------------------------------- */
2656/* input : dx ,valid value : CR or second chip's CR */
2657/* */
2658/* SetPowerConsume : */
2659/* Description: reduce 40/43 power consumption in first chip or */
2660/* in second chip, assume CR A1 D[6]="1" in this case */
2661/* output : none */
2662/* --------------------------------------------------------------------- */
e4147abe 2663void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
82d6eb5b 2664 unsigned long XGI_P3d4Port)
d7636e0b 2665{
82d6eb5b 2666 unsigned long lTemp ;
108afbf8 2667 unsigned char bTemp;
d7636e0b 2668
2669 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2670 if ((lTemp&0xFF)==0)
2671 {
2672 /* set CR58 D[5]=0 D[3]=0 */
2673 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
108afbf8 2674 bTemp = (unsigned char) XGINew_GetReg1(XGI_P3d4Port, 0xCB);
d7636e0b 2675 if (bTemp&0x20)
2676 {
2677 if (!(bTemp&0x10))
2678 {
2679 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2680 }
2681 else
2682 {
2683 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2684 }
2685
2686 }
2687
2688 }
2689}
2690
8922967e
RD		 2691#if 0
2692static void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension,
2693 struct vb_device_info *pVBInfo)
d7636e0b 2694{
2695
82d6eb5b 2696 /* unsigned long ROMAddr = (unsigned long)HwDeviceExtension->pjVirtualRomBase; */
d7636e0b 2697 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2698 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
82d6eb5b 2699 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
d7636e0b 2700 pVBInfo->ISXPDOS = 0 ;
2701
2702 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2703 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2704 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2705 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2706 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2707 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2708 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2709 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2710 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2711 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2712 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2713 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2714 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2715 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2716 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2717 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2718 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2719 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2720 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2721
2722 switch(HwDeviceExtension->jChipType)
2723 {
2724 case XG40:
2725 case XG41:
2726 case XG42:
2727 case XG20:
2728 case XG21:
2729 default:
2730 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2731 return ;
2732 }
2733
2734}
8922967e 2735#endif
d7636e0b 2736
2737/* --------------------------------------------------------------------- */
2738/* Function : ReadVBIOSTablData */
2739/* Input : */
2740/* Output : */
2741/* Description : */
2742/* --------------------------------------------------------------------- */
80adad85 2743void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
d7636e0b 2744{
274afb73 2745 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
82d6eb5b 2746 unsigned long i ;
108afbf8 2747 unsigned char j, k ;
d7636e0b 2748 /* Volari customize data area end */
2749
2750 if ( ChipType == XG21 )
2751 {
2752 pVBInfo->IF_DEF_LVDS = 0 ;
2753 if (pVideoMemory[ 0x65 ] & 0x1)
2754 {
2755 pVBInfo->IF_DEF_LVDS = 1 ;
2756 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2757 j = pVideoMemory[ i-1 ] ;
2758 if ( j != 0xff )
2759 {
2760 k = 0;
2761 do
2762 {
2763 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2764 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2765 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2766 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2767 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2768 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2769 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2770 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2771 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2772 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2773 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2774 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2775 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2776 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2777 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2778 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2779 i += 25;
2780 j--;
2781 k++;
80adad85
BP		 2782 } while ((j > 0) &&
2783 (k < (sizeof(XGI21_LCDCapList)/sizeof(struct XGI21_LVDSCapStruct))));
d7636e0b 2784 }
2785 else
2786 {
2787 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2788 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2789 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2790 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2791 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2792 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2793 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2794 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2795 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2796 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2797 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2798 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2799 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2800 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2801 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2802 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2803 }
2804 }
2805 }
2806}
2807
2808/* --------------------------------------------------------------------- */
2809/* Function : XGINew_DDR1x_MRS_XG20 */
2810/* Input : */
2811/* Output : */
2812/* Description : */
2813/* --------------------------------------------------------------------- */
80adad85 2814void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
d7636e0b 2815{
2816
2817 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2818 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2819 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2820 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2821 DelayUS( 60 ) ;
2822
2823 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2824 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2825 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2826 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2827 DelayUS( 60 ) ;
2828 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2829 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2830 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
2831 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2832 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2833 DelayUS( 1000 ) ;
2834 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
2835 DelayUS( 500 ) ;
2836 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2837 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2838 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
2839 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2840 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2841 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
2842}
2843
2844/* --------------------------------------------------------------------- */
2845/* Function : XGINew_SetDRAMModeRegister_XG20 */
2846/* Input : */
2847/* Output : */
2848/* Description : */
2849/* --------------------------------------------------------------------- */
e4147abe 2850void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension)
d7636e0b 2851{
80adad85
BP		 2852 struct vb_device_info VBINF;
2853 struct vb_device_info *pVBInfo = &VBINF;
d7636e0b 2854 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2855 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
82d6eb5b 2856 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
d7636e0b 2857 pVBInfo->ISXPDOS = 0 ;
2858
2859 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2860 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2861 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2862 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2863 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2864 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2865 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2866 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2867 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2868 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2869 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2870 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2871 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2872 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2873 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2874 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2875 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2876
2877 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2878
2879 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2880
2881 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2882 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2883 else
2884 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2885
2886 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2887}
2888
e4147abe 2889void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
d7636e0b 2890{
80adad85
BP		 2891 struct vb_device_info VBINF;
2892 struct vb_device_info *pVBInfo = &VBINF;
d7636e0b 2893 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2894 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
82d6eb5b 2895 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
d7636e0b 2896 pVBInfo->ISXPDOS = 0 ;
2897
2898 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2899 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2900 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2901 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2902 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2903 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2904 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2905 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2906 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2907 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2908 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2909 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2910 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2911 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2912 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2913 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2914 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2915
2916 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2917
2918 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2919
2920 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2921 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2922 else
2923 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2924 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
2925
2926 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2927 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
2928
2929}
2930/*
e4147abe 2931void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
d7636e0b 2932{
84c7603c 2933
108afbf8 2934 unsigned char data ;
80adad85
BP		 2935 struct vb_device_info VBINF;
2936 struct vb_device_info *pVBInfo = &VBINF;
d7636e0b 2937 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2938 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2939 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
2940 pVBInfo->ISXPDOS = 0 ;
2941
2942 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2943 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2944 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2945 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2946 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2947 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2948 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2949 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2950 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2951 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2952 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2953 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2954 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2955 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2956 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2957 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2958 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2959
2960 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2961
2962 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2963
2964 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2965 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2966 else
2967 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2968
2969 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2970}
2971*/
2972/* -------------------------------------------------------- */
2973/* Function : XGINew_ChkSenseStatus */
2974/* Input : */
2975/* Output : */
2976/* Description : */
2977/* -------------------------------------------------------- */
80adad85 2978void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 2979{
82d6eb5b 2980 unsigned short tempbx = 0, temp, tempcx, CR3CData;
d7636e0b 2981
2982 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
2983
2984 if ( temp & Monitor1Sense )
2985 tempbx |= ActiveCRT1 ;
2986 if ( temp & LCDSense )
2987 tempbx |= ActiveLCD ;
2988 if ( temp & Monitor2Sense )
2989 tempbx |= ActiveCRT2 ;
2990 if ( temp & TVSense )
2991 {
2992 tempbx |= ActiveTV ;
2993 if ( temp & AVIDEOSense )
2994 tempbx |= ( ActiveAVideo << 8 );
2995 if ( temp & SVIDEOSense )
2996 tempbx |= ( ActiveSVideo << 8 );
2997 if ( temp & SCARTSense )
2998 tempbx |= ( ActiveSCART << 8 );
2999 if ( temp & HiTVSense )
3000 tempbx |= ( ActiveHiTV << 8 );
3001 if ( temp & YPbPrSense )
3002 tempbx |= ( ActiveYPbPr << 8 );
3003 }
3004
3005 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3006 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3007
3008 if ( tempbx & tempcx )
3009 {
3010 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3011 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3012 {
3013 tempcx = 0x1FF0 ;
3014 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3015 {
3016 tempbx = 0x1FF0 ;
3017 }
3018 }
3019 }
3020 else
3021 {
3022 tempcx = 0x1FF0 ;
3023 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3024 {
3025 tempbx = 0x1FF0 ;
3026 }
3027 }
3028
3029 tempbx &= tempcx ;
3030 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3031 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3032}
3033/* -------------------------------------------------------- */
3034/* Function : XGINew_SetModeScratch */
3035/* Input : */
3036/* Output : */
3037/* Description : */
3038/* -------------------------------------------------------- */
80adad85 3039void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 3040{
82d6eb5b 3041 unsigned short temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
d7636e0b 3042
3043 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3044 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3045 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3046
3047 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3048 {
3049 if ( temp & ActiveCRT2 )
3050 tempcl = SetCRT2ToRAMDAC ;
3051 }
3052
3053 if ( temp & ActiveLCD )
3054 {
3055 tempcl |= SetCRT2ToLCD ;
3056 if ( temp & DriverMode )
3057 {
3058 if ( temp & ActiveTV )
3059 {
3060 tempch = SetToLCDA | EnableDualEdge ;
3061 temp ^= SetCRT2ToLCD ;
3062
3063 if ( ( temp >> 8 ) & ActiveAVideo )
3064 tempcl |= SetCRT2ToAVIDEO ;
3065 if ( ( temp >> 8 ) & ActiveSVideo )
3066 tempcl |= SetCRT2ToSVIDEO ;
3067 if ( ( temp >> 8 ) & ActiveSCART )
3068 tempcl |= SetCRT2ToSCART ;
3069
3070 if ( pVBInfo->IF_DEF_HiVision == 1 )
3071 {
3072 if ( ( temp >> 8 ) & ActiveHiTV )
3073 tempcl |= SetCRT2ToHiVisionTV ;
3074 }
3075
3076 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3077 {
3078 if ( ( temp >> 8 ) & ActiveYPbPr )
3079 tempch |= SetYPbPr ;
3080 }
3081 }
3082 }
3083 }
3084 else
3085 {
3086 if ( ( temp >> 8 ) & ActiveAVideo )
3087 tempcl |= SetCRT2ToAVIDEO ;
3088 if ( ( temp >> 8 ) & ActiveSVideo )
3089 tempcl |= SetCRT2ToSVIDEO ;
3090 if ( ( temp >> 8 ) & ActiveSCART )
3091 tempcl |= SetCRT2ToSCART ;
3092
3093 if ( pVBInfo->IF_DEF_HiVision == 1 )
3094 {
3095 if ( ( temp >> 8 ) & ActiveHiTV )
3096 tempcl |= SetCRT2ToHiVisionTV ;
3097 }
3098
3099 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3100 {
3101 if ( ( temp >> 8 ) & ActiveYPbPr )
3102 tempch |= SetYPbPr ;
3103 }
3104 }
3105
3106
3107 tempcl |= SetSimuScanMode ;
3108 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3109 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3110 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3111 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3112 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3113
3114 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3115 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3116 if ( !( temp & ActiveCRT1 ) )
3117 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3118 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3119 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3120 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3121 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3122
3123 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3124 CR38Data &= ~SetYPbPr ;
3125 CR38Data |= tempch ;
3126 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3127
3128}
3129
3130/* -------------------------------------------------------- */
3131/* Function : XGINew_GetXG21Sense */
3132/* Input : */
3133/* Output : */
3134/* Description : */
3135/* -------------------------------------------------------- */
80adad85 3136void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 3137{
108afbf8 3138 unsigned char Temp;
274afb73 3139 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
d7636e0b 3140
3141 pVBInfo->IF_DEF_LVDS = 0 ;
3142
d7636e0b 3143#if 1
3144 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3145 {
3146 pVBInfo->IF_DEF_LVDS = 1 ;
3147 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3148 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3149 }
3150 else
3151 {
3152#endif
3153 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3154 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3155 if ( Temp == 0xC0 )
3156 { /* DVI & DVO GPIOA/B pull high */
3157 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3158 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3159 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3160 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3161 if ( !Temp )
3162 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3163 else
3164 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3165 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3166 }
3167#if 1
3168 }
3169#endif
3170}
3171
3172/* -------------------------------------------------------- */
3173/* Function : XGINew_GetXG27Sense */
3174/* Input : */
3175/* Output : */
3176/* Description : */
3177/* -------------------------------------------------------- */
80adad85 3178void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
d7636e0b 3179{
108afbf8 3180 unsigned char Temp, bCR4A;
d7636e0b 3181
3182 pVBInfo->IF_DEF_LVDS = 0 ;
3183 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3184 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3185 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3186 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3187
3188 if ( Temp <= 0x02 )
3189 {
3190 pVBInfo->IF_DEF_LVDS = 1 ;
3191 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3192 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3193 }
3194 else
3195 {
3196 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3197 }
3198 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3199
3200}
3201
80adad85 3202unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
d7636e0b 3203{
108afbf8 3204 unsigned char CR38, CR4A, temp;
d7636e0b 3205
3206 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3207 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3208 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3209 temp =0;
3210 if ( ( CR38 & 0xE0 ) > 0x80 )
3211 {
3212 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3213 temp &= 0x08;
3214 temp >>= 3;
3215 }
3216
3217 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3218
3219 return temp;
3220}
3221
80adad85 3222unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
d7636e0b 3223{
108afbf8 3224 unsigned char CR4A, temp;
d7636e0b 3225
3226 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3227 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3228 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3229 if ( temp <= 2 )
3230 {
3231 temp &= 0x03;
3232 }
3233 else
3234 {
3235 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3236 }
3237 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3238
3239 return temp;
3240}
3241
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