drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar5008_initvals.h"
  19 #include "ar9001_initvals.h"
  20 #include "ar9002_initvals.h"
  21 #include "ar9002_phy.h"
  22
  23 int modparam_force_new_ani;
  24 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
  25 MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
  26
  27 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  28
  29 static bool ar9002_hw_macversion_supported(u32 macversion)
  30 {
  31         switch (macversion) {
  32         case AR_SREV_VERSION_5416_PCI:
  33         case AR_SREV_VERSION_5416_PCIE:
  34         case AR_SREV_VERSION_9160:
  35         case AR_SREV_VERSION_9100:
  36         case AR_SREV_VERSION_9280:
  37         case AR_SREV_VERSION_9285:
  38         case AR_SREV_VERSION_9287:
  39         case AR_SREV_VERSION_9271:
  40                 return true;
  41         default:
  42                 break;
  43         }
  44         return false;
  45 }
  46
  47 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
  48 {
  49         if (AR_SREV_9271(ah)) {
  50                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  51                                ARRAY_SIZE(ar9271Modes_9271), 6);
  52                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  53                                ARRAY_SIZE(ar9271Common_9271), 2);
  54                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
  55                                ar9271Common_normal_cck_fir_coeff_9271,
  56                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
  57                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
  58                                ar9271Common_japan_2484_cck_fir_coeff_9271,
  59                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
  60                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  61                                ar9271Modes_9271_1_0_only,
  62                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
  63                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  64                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
  65                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  66                                ar9271Modes_high_power_tx_gain_9271,
  67                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
  68                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  69                                ar9271Modes_normal_power_tx_gain_9271,
  70                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
  71                 return;
  72         }
  73
  74         if (AR_SREV_9287_11_OR_LATER(ah)) {
  75                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  76                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
  77                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  78                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  79                 if (ah->config.pcie_clock_req)
  80                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  81                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
  82                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  83                 else
  84                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  85                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  86                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  87                                         2);
  88         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  89
  90
  91                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
  92                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
  93                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
  94                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
  95
  96                 if (ah->config.pcie_clock_req) {
  97                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  98                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
  99                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 100                 } else {
 101                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 102                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 103                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 104                                   2);
 105                 }
 106         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 107                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 108                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 109                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 110                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 111
 112                 if (ah->config.pcie_clock_req) {
 113                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 114                                ar9280PciePhy_clkreq_off_L1_9280,
 115                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
 116                 } else {
 117                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 118                                ar9280PciePhy_clkreq_always_on_L1_9280,
 119                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 120                 }
 121                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 122                                ar9280Modes_fast_clock_9280_2,
 123                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 124         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 125                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 126                                ARRAY_SIZE(ar5416Modes_9160), 6);
 127                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 128                                ARRAY_SIZE(ar5416Common_9160), 2);
 129                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 130                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 131                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 132                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 133                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 134                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 135                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 136                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 137                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 138                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 139                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 140                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 141                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 142                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 143                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 144                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 145                 if (AR_SREV_9160_11(ah)) {
 146                         INIT_INI_ARRAY(&ah->iniAddac,
 147                                        ar5416Addac_9160_1_1,
 148                                        ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
 149                 } else {
 150                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 151                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 152                 }
 153         } else if (AR_SREV_9100_OR_LATER(ah)) {
 154                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 155                                ARRAY_SIZE(ar5416Modes_9100), 6);
 156                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 157                                ARRAY_SIZE(ar5416Common_9100), 2);
 158                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 159                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 160                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 161                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 162                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 163                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 164                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 165                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 166                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 167                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 168                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 169                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 170                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 171                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 172                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 173                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 174                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 175                                ARRAY_SIZE(ar5416Addac_9100), 2);
 176         } else {
 177                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 178                                ARRAY_SIZE(ar5416Modes), 6);
 179                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 180                                ARRAY_SIZE(ar5416Common), 2);
 181                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 182                                ARRAY_SIZE(ar5416Bank0), 2);
 183                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 184                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 185                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 186                                ARRAY_SIZE(ar5416Bank1), 2);
 187                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 188                                ARRAY_SIZE(ar5416Bank2), 2);
 189                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 190                                ARRAY_SIZE(ar5416Bank3), 3);
 191                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 192                                ARRAY_SIZE(ar5416Bank6), 3);
 193                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 194                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 195                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 196                                ARRAY_SIZE(ar5416Bank7), 2);
 197                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 198                                ARRAY_SIZE(ar5416Addac), 2);
 199         }
 200 }
 201
 202 /* Support for Japan ch.14 (2484) spread */
 203 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
 204 {
 205         if (AR_SREV_9287_11_OR_LATER(ah)) {
 206                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 207                        ar9287Common_normal_cck_fir_coeff_9287_1_1,
 208                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
 209                        2);
 210                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 211                        ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
 212                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
 213                        2);
 214         }
 215 }
 216
 217 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 218 {
 219         u32 rxgain_type;
 220
 221         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 222             AR5416_EEP_MINOR_VER_17) {
 223                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 224
 225                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 226                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 227                         ar9280Modes_backoff_13db_rxgain_9280_2,
 228                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 229                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 230                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 231                         ar9280Modes_backoff_23db_rxgain_9280_2,
 232                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 233                 else
 234                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 235                         ar9280Modes_original_rxgain_9280_2,
 236                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 237         } else {
 238                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 239                         ar9280Modes_original_rxgain_9280_2,
 240                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 241         }
 242 }
 243
 244 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
 245 {
 246         u32 txgain_type;
 247
 248         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 249             AR5416_EEP_MINOR_VER_19) {
 250                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 251
 252                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 253                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 254                         ar9280Modes_high_power_tx_gain_9280_2,
 255                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 256                 else
 257                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 258                         ar9280Modes_original_tx_gain_9280_2,
 259                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 260         } else {
 261                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 262                 ar9280Modes_original_tx_gain_9280_2,
 263                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 264         }
 265 }
 266
 267 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 268 {
 269         if (AR_SREV_9287_11_OR_LATER(ah))
 270                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 271                 ar9287Modes_rx_gain_9287_1_1,
 272                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 273         else if (AR_SREV_9280_20(ah))
 274                 ar9280_20_hw_init_rxgain_ini(ah);
 275
 276         if (AR_SREV_9287_11_OR_LATER(ah)) {
 277                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 278                 ar9287Modes_tx_gain_9287_1_1,
 279                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 280         } else if (AR_SREV_9280_20(ah)) {
 281                 ar9280_20_hw_init_txgain_ini(ah);
 282         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 283                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 284
 285                 /* txgain table */
 286                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 287                         if (AR_SREV_9285E_20(ah)) {
 288                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                                 ar9285Modes_XE2_0_high_power,
 290                                 ARRAY_SIZE(
 291                                   ar9285Modes_XE2_0_high_power), 6);
 292                         } else {
 293                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 294                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 295                                 ARRAY_SIZE(
 296                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 297                         }
 298                 } else {
 299                         if (AR_SREV_9285E_20(ah)) {
 300                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 301                                 ar9285Modes_XE2_0_normal_power,
 302                                 ARRAY_SIZE(
 303                                   ar9285Modes_XE2_0_normal_power), 6);
 304                         } else {
 305                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 306                                 ar9285Modes_original_tx_gain_9285_1_2,
 307                                 ARRAY_SIZE(
 308                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 309                         }
 310                 }
 311         }
 312 }
 313
 314 /*
 315  * Helper for ASPM support.
 316  *
 317  * Disable PLL when in L0s as well as receiver clock when in L1.
 318  * This power saving option must be enabled through the SerDes.
 319  *
 320  * Programming the SerDes must go through the same 288 bit serial shift
 321  * register as the other analog registers.  Hence the 9 writes.
 322  */
 323 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 324                                          int restore,
 325                                          int power_off)
 326 {
 327         u8 i;
 328         u32 val;
 329
 330         if (ah->is_pciexpress != true)
 331                 return;
 332
 333         /* Do not touch SerDes registers */
 334         if (ah->config.pcie_powersave_enable == 2)
 335                 return;
 336
 337         /* Nothing to do on restore for 11N */
 338         if (!restore) {
 339                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 340                         /*
 341                          * AR9280 2.0 or later chips use SerDes values from the
 342                          * initvals.h initialized depending on chipset during
 343                          * __ath9k_hw_init()
 344                          */
 345                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 346                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 347                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 348                         }
 349                 } else {
 350                         ENABLE_REGWRITE_BUFFER(ah);
 351
 352                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 353                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 354
 355                         /* RX shut off when elecidle is asserted */
 356                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 357                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 358                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 359
 360                         /*
 361                          * Ignore ah->ah_config.pcie_clock_req setting for
 362                          * pre-AR9280 11n
 363                          */
 364                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 365
 366                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 367                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 368                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 369
 370                         /* Load the new settings */
 371                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 372
 373                         REGWRITE_BUFFER_FLUSH(ah);
 374                 }
 375
 376                 udelay(1000);
 377         }
 378
 379         if (power_off) {
 380                 /* clear bit 19 to disable L1 */
 381                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 382
 383                 val = REG_READ(ah, AR_WA);
 384
 385                 /*
 386                  * Set PCIe workaround bits
 387                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 388                  * should only  be set when device enters D3 and be
 389                  * cleared when device comes back to D0.
 390                  */
 391                 if (ah->config.pcie_waen) {
 392                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 393                                 val |= AR_WA_D3_L1_DISABLE;
 394                 } else {
 395                         if (((AR_SREV_9285(ah) ||
 396                               AR_SREV_9271(ah) ||
 397                               AR_SREV_9287(ah)) &&
 398                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 399                             (AR_SREV_9280(ah) &&
 400                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 401                                 val |= AR_WA_D3_L1_DISABLE;
 402                         }
 403                 }
 404
 405                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 406                         /*
 407                          * Disable bit 6 and 7 before entering D3 to
 408                          * prevent system hang.
 409                          */
 410                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 411                 }
 412
 413                 if (AR_SREV_9285E_20(ah))
 414                         val |= AR_WA_BIT23;
 415
 416                 REG_WRITE(ah, AR_WA, val);
 417         } else {
 418                 if (ah->config.pcie_waen) {
 419                         val = ah->config.pcie_waen;
 420                         if (!power_off)
 421                                 val &= (~AR_WA_D3_L1_DISABLE);
 422                 } else {
 423                         if (AR_SREV_9285(ah) ||
 424                             AR_SREV_9271(ah) ||
 425                             AR_SREV_9287(ah)) {
 426                                 val = AR9285_WA_DEFAULT;
 427                                 if (!power_off)
 428                                         val &= (~AR_WA_D3_L1_DISABLE);
 429                         }
 430                         else if (AR_SREV_9280(ah)) {
 431                                 /*
 432                                  * For AR9280 chips, bit 22 of 0x4004
 433                                  * needs to be set.
 434                                  */
 435                                 val = AR9280_WA_DEFAULT;
 436                                 if (!power_off)
 437                                         val &= (~AR_WA_D3_L1_DISABLE);
 438                         } else {
 439                                 val = AR_WA_DEFAULT;
 440                         }
 441                 }
 442
 443                 /* WAR for ASPM system hang */
 444                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 445                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 446                 }
 447
 448                 if (AR_SREV_9285E_20(ah))
 449                         val |= AR_WA_BIT23;
 450
 451                 REG_WRITE(ah, AR_WA, val);
 452
 453                 /* set bit 19 to allow forcing of pcie core into L1 state */
 454                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 455         }
 456 }
 457
 458 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 459 {
 460         u32 val;
 461         int i;
 462
 463         ENABLE_REGWRITE_BUFFER(ah);
 464
 465         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 466         for (i = 0; i < 8; i++)
 467                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 468
 469         REGWRITE_BUFFER_FLUSH(ah);
 470
 471         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 472         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 473
 474         return ath9k_hw_reverse_bits(val, 8);
 475 }
 476
 477 int ar9002_hw_rf_claim(struct ath_hw *ah)
 478 {
 479         u32 val;
 480
 481         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 482
 483         val = ar9002_hw_get_radiorev(ah);
 484         switch (val & AR_RADIO_SREV_MAJOR) {
 485         case 0:
 486                 val = AR_RAD5133_SREV_MAJOR;
 487                 break;
 488         case AR_RAD5133_SREV_MAJOR:
 489         case AR_RAD5122_SREV_MAJOR:
 490         case AR_RAD2133_SREV_MAJOR:
 491         case AR_RAD2122_SREV_MAJOR:
 492                 break;
 493         default:
 494                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 495                           "Radio Chip Rev 0x%02X not supported\n",
 496                           val & AR_RADIO_SREV_MAJOR);
 497                 return -EOPNOTSUPP;
 498         }
 499
 500         ah->hw_version.analog5GhzRev = val;
 501
 502         return 0;
 503 }
 504
 505 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 506 {
 507         if (AR_SREV_9287_13_OR_LATER(ah)) {
 508                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 509                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 510                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 511                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 512                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 513                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 514                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 515         }
 516 }
 517
 518 /*
 519  * If Async FIFO is enabled, the following counters change as MAC now runs
 520  * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
 521  *
 522  * The values below tested for ht40 2 chain.
 523  * Overwrite the delay/timeouts initialized in process ini.
 524  */
 525 void ar9002_hw_update_async_fifo(struct ath_hw *ah)
 526 {
 527         if (AR_SREV_9287_13_OR_LATER(ah)) {
 528                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
 529                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
 530                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
 531                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
 532                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
 533                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
 534
 535                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
 536                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
 537
 538                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
 539                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
 540                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
 541                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
 542         }
 543 }
 544
 545 /*
 546  * We don't enable WEP aggregation on mac80211 but we keep this
 547  * around for HAL unification purposes.
 548  */
 549 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
 550 {
 551         if (AR_SREV_9287_13_OR_LATER(ah)) {
 552                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
 553                             AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
 554         }
 555 }
 556
 557 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 558 void ar9002_hw_attach_ops(struct ath_hw *ah)
 559 {
 560         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 561         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 562
 563         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
 564         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 565         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 566
 567         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 568
 569         ar5008_hw_attach_phy_ops(ah);
 570         if (AR_SREV_9280_20_OR_LATER(ah))
 571                 ar9002_hw_attach_phy_ops(ah);
 572
 573         ar9002_hw_attach_calib_ops(ah);
 574         ar9002_hw_attach_mac_ops(ah);
 575 }
 576
 577 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
 578 {
 579         u32 modesIndex;
 580         int i;
 581
 582         switch (chan->chanmode) {
 583         case CHANNEL_A:
 584         case CHANNEL_A_HT20:
 585                 modesIndex = 1;
 586                 break;
 587         case CHANNEL_A_HT40PLUS:
 588         case CHANNEL_A_HT40MINUS:
 589                 modesIndex = 2;
 590                 break;
 591         case CHANNEL_G:
 592         case CHANNEL_G_HT20:
 593         case CHANNEL_B:
 594                 modesIndex = 4;
 595                 break;
 596         case CHANNEL_G_HT40PLUS:
 597         case CHANNEL_G_HT40MINUS:
 598                 modesIndex = 3;
 599                 break;
 600
 601         default:
 602                 return;
 603         }
 604
 605         ENABLE_REGWRITE_BUFFER(ah);
 606
 607         for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
 608                 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
 609                 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
 610                 u32 val_orig;
 611
 612                 if (reg == AR_PHY_CCK_DETECT) {
 613                         val_orig = REG_READ(ah, reg);
 614                         val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 615                         val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
 616
 617                         REG_WRITE(ah, reg, val|val_orig);
 618                 } else
 619                         REG_WRITE(ah, reg, val);
 620         }
 621
 622         REGWRITE_BUFFER_FLUSH(ah);
 623 }