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1 | /* | |
2 | * MUSB OTG driver - support for Mentor's DMA controller | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2007 by Texas Instruments | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
22 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
23 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
24 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
25 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
26 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
27 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
28 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
30 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
31 | * | |
32 | */ | |
33 | #include <linux/device.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/slab.h> | |
37 | #include "musb_core.h" | |
38 | #include "musbhsdma.h" | |
39 | ||
40 | static int dma_controller_start(struct dma_controller *c) | |
41 | { | |
42 | /* nothing to do */ | |
43 | return 0; | |
44 | } | |
45 | ||
46 | static void dma_channel_release(struct dma_channel *channel); | |
47 | ||
48 | static int dma_controller_stop(struct dma_controller *c) | |
49 | { | |
50 | struct musb_dma_controller *controller = container_of(c, | |
51 | struct musb_dma_controller, controller); | |
52 | struct musb *musb = controller->private_data; | |
53 | struct dma_channel *channel; | |
54 | u8 bit; | |
55 | ||
56 | if (controller->used_channels != 0) { | |
57 | dev_err(musb->controller, | |
58 | "Stopping DMA controller while channel active\n"); | |
59 | ||
60 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { | |
61 | if (controller->used_channels & (1 << bit)) { | |
62 | channel = &controller->channel[bit].channel; | |
63 | dma_channel_release(channel); | |
64 | ||
65 | if (!controller->used_channels) | |
66 | break; | |
67 | } | |
68 | } | |
69 | } | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
74 | static struct dma_channel *dma_channel_allocate(struct dma_controller *c, | |
75 | struct musb_hw_ep *hw_ep, u8 transmit) | |
76 | { | |
77 | struct musb_dma_controller *controller = container_of(c, | |
78 | struct musb_dma_controller, controller); | |
79 | struct musb_dma_channel *musb_channel = NULL; | |
80 | struct dma_channel *channel = NULL; | |
81 | u8 bit; | |
82 | ||
83 | for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { | |
84 | if (!(controller->used_channels & (1 << bit))) { | |
85 | controller->used_channels |= (1 << bit); | |
86 | musb_channel = &(controller->channel[bit]); | |
87 | musb_channel->controller = controller; | |
88 | musb_channel->idx = bit; | |
89 | musb_channel->epnum = hw_ep->epnum; | |
90 | musb_channel->transmit = transmit; | |
91 | channel = &(musb_channel->channel); | |
92 | channel->private_data = musb_channel; | |
93 | channel->status = MUSB_DMA_STATUS_FREE; | |
94 | channel->max_len = 0x10000; | |
95 | /* Tx => mode 1; Rx => mode 0 */ | |
96 | channel->desired_mode = transmit; | |
97 | channel->actual_len = 0; | |
98 | break; | |
99 | } | |
100 | } | |
101 | ||
102 | return channel; | |
103 | } | |
104 | ||
105 | static void dma_channel_release(struct dma_channel *channel) | |
106 | { | |
107 | struct musb_dma_channel *musb_channel = channel->private_data; | |
108 | ||
109 | channel->actual_len = 0; | |
110 | musb_channel->start_addr = 0; | |
111 | musb_channel->len = 0; | |
112 | ||
113 | musb_channel->controller->used_channels &= | |
114 | ~(1 << musb_channel->idx); | |
115 | ||
116 | channel->status = MUSB_DMA_STATUS_UNKNOWN; | |
117 | } | |
118 | ||
119 | static void configure_channel(struct dma_channel *channel, | |
120 | u16 packet_sz, u8 mode, | |
121 | dma_addr_t dma_addr, u32 len) | |
122 | { | |
123 | struct musb_dma_channel *musb_channel = channel->private_data; | |
124 | struct musb_dma_controller *controller = musb_channel->controller; | |
125 | void __iomem *mbase = controller->base; | |
126 | u8 bchannel = musb_channel->idx; | |
127 | u16 csr = 0; | |
128 | ||
129 | DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", | |
130 | channel, packet_sz, dma_addr, len, mode); | |
131 | ||
132 | if (mode) { | |
133 | csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; | |
134 | BUG_ON(len < packet_sz); | |
135 | } | |
136 | csr |= MUSB_HSDMA_BURSTMODE_INCR16 | |
137 | << MUSB_HSDMA_BURSTMODE_SHIFT; | |
138 | ||
139 | csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) | |
140 | | (1 << MUSB_HSDMA_ENABLE_SHIFT) | |
141 | | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) | |
142 | | (musb_channel->transmit | |
143 | ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) | |
144 | : 0); | |
145 | ||
146 | /* address/count */ | |
147 | musb_write_hsdma_addr(mbase, bchannel, dma_addr); | |
148 | musb_write_hsdma_count(mbase, bchannel, len); | |
149 | ||
150 | /* control (this should start things) */ | |
151 | musb_writew(mbase, | |
152 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), | |
153 | csr); | |
154 | } | |
155 | ||
156 | static int dma_channel_program(struct dma_channel *channel, | |
157 | u16 packet_sz, u8 mode, | |
158 | dma_addr_t dma_addr, u32 len) | |
159 | { | |
160 | struct musb_dma_channel *musb_channel = channel->private_data; | |
161 | ||
162 | DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", | |
163 | musb_channel->epnum, | |
164 | musb_channel->transmit ? "Tx" : "Rx", | |
165 | packet_sz, dma_addr, len, mode); | |
166 | ||
167 | BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || | |
168 | channel->status == MUSB_DMA_STATUS_BUSY); | |
169 | ||
170 | channel->actual_len = 0; | |
171 | musb_channel->start_addr = dma_addr; | |
172 | musb_channel->len = len; | |
173 | musb_channel->max_packet_sz = packet_sz; | |
174 | channel->status = MUSB_DMA_STATUS_BUSY; | |
175 | ||
176 | if ((mode == 1) && (len >= packet_sz)) | |
177 | configure_channel(channel, packet_sz, 1, dma_addr, len); | |
178 | else | |
179 | configure_channel(channel, packet_sz, 0, dma_addr, len); | |
180 | ||
181 | return true; | |
182 | } | |
183 | ||
184 | static int dma_channel_abort(struct dma_channel *channel) | |
185 | { | |
186 | struct musb_dma_channel *musb_channel = channel->private_data; | |
187 | void __iomem *mbase = musb_channel->controller->base; | |
188 | ||
189 | u8 bchannel = musb_channel->idx; | |
190 | int offset; | |
191 | u16 csr; | |
192 | ||
193 | if (channel->status == MUSB_DMA_STATUS_BUSY) { | |
194 | if (musb_channel->transmit) { | |
195 | offset = MUSB_EP_OFFSET(musb_channel->epnum, | |
196 | MUSB_TXCSR); | |
197 | ||
198 | /* | |
199 | * The programming guide says that we must clear | |
200 | * the DMAENAB bit before the DMAMODE bit... | |
201 | */ | |
202 | csr = musb_readw(mbase, offset); | |
203 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); | |
204 | musb_writew(mbase, offset, csr); | |
205 | csr &= ~MUSB_TXCSR_DMAMODE; | |
206 | musb_writew(mbase, offset, csr); | |
207 | } else { | |
208 | offset = MUSB_EP_OFFSET(musb_channel->epnum, | |
209 | MUSB_RXCSR); | |
210 | ||
211 | csr = musb_readw(mbase, offset); | |
212 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | | |
213 | MUSB_RXCSR_DMAENAB | | |
214 | MUSB_RXCSR_DMAMODE); | |
215 | musb_writew(mbase, offset, csr); | |
216 | } | |
217 | ||
218 | musb_writew(mbase, | |
219 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), | |
220 | 0); | |
221 | musb_write_hsdma_addr(mbase, bchannel, 0); | |
222 | musb_write_hsdma_count(mbase, bchannel, 0); | |
223 | channel->status = MUSB_DMA_STATUS_FREE; | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static irqreturn_t dma_controller_irq(int irq, void *private_data) | |
230 | { | |
231 | struct musb_dma_controller *controller = private_data; | |
232 | struct musb *musb = controller->private_data; | |
233 | struct musb_dma_channel *musb_channel; | |
234 | struct dma_channel *channel; | |
235 | ||
236 | void __iomem *mbase = controller->base; | |
237 | ||
238 | irqreturn_t retval = IRQ_NONE; | |
239 | ||
240 | unsigned long flags; | |
241 | ||
242 | u8 bchannel; | |
243 | u8 int_hsdma; | |
244 | ||
245 | u32 addr, count; | |
246 | u16 csr; | |
247 | ||
248 | spin_lock_irqsave(&musb->lock, flags); | |
249 | ||
250 | int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); | |
251 | ||
252 | #ifdef CONFIG_BLACKFIN | |
253 | /* Clear DMA interrupt flags */ | |
254 | musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); | |
255 | #endif | |
256 | ||
257 | if (!int_hsdma) { | |
258 | DBG(2, "spurious DMA irq\n"); | |
259 | ||
260 | for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { | |
261 | musb_channel = (struct musb_dma_channel *) | |
262 | &(controller->channel[bchannel]); | |
263 | channel = &musb_channel->channel; | |
264 | if (channel->status == MUSB_DMA_STATUS_BUSY) { | |
265 | count = musb_read_hsdma_count(mbase, bchannel); | |
266 | ||
267 | if (count == 0) | |
268 | int_hsdma |= (1 << bchannel); | |
269 | } | |
270 | } | |
271 | ||
272 | DBG(2, "int_hsdma = 0x%x\n", int_hsdma); | |
273 | ||
274 | if (!int_hsdma) | |
275 | goto done; | |
276 | } | |
277 | ||
278 | for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { | |
279 | if (int_hsdma & (1 << bchannel)) { | |
280 | musb_channel = (struct musb_dma_channel *) | |
281 | &(controller->channel[bchannel]); | |
282 | channel = &musb_channel->channel; | |
283 | ||
284 | csr = musb_readw(mbase, | |
285 | MUSB_HSDMA_CHANNEL_OFFSET(bchannel, | |
286 | MUSB_HSDMA_CONTROL)); | |
287 | ||
288 | if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { | |
289 | musb_channel->channel.status = | |
290 | MUSB_DMA_STATUS_BUS_ABORT; | |
291 | } else { | |
292 | u8 devctl; | |
293 | ||
294 | addr = musb_read_hsdma_addr(mbase, | |
295 | bchannel); | |
296 | channel->actual_len = addr | |
297 | - musb_channel->start_addr; | |
298 | ||
299 | DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", | |
300 | channel, musb_channel->start_addr, | |
301 | addr, channel->actual_len, | |
302 | musb_channel->len, | |
303 | (channel->actual_len | |
304 | < musb_channel->len) ? | |
305 | "=> reconfig 0" : "=> complete"); | |
306 | ||
307 | devctl = musb_readb(mbase, MUSB_DEVCTL); | |
308 | ||
309 | channel->status = MUSB_DMA_STATUS_FREE; | |
310 | ||
311 | /* completed */ | |
312 | if ((devctl & MUSB_DEVCTL_HM) | |
313 | && (musb_channel->transmit) | |
314 | && ((channel->desired_mode == 0) | |
315 | || (channel->actual_len & | |
316 | (musb_channel->max_packet_sz - 1))) | |
317 | ) { | |
318 | u8 epnum = musb_channel->epnum; | |
319 | int offset = MUSB_EP_OFFSET(epnum, | |
320 | MUSB_TXCSR); | |
321 | u16 txcsr; | |
322 | ||
323 | /* | |
324 | * The programming guide says that we | |
325 | * must clear DMAENAB before DMAMODE. | |
326 | */ | |
327 | musb_ep_select(mbase, epnum); | |
328 | txcsr = musb_readw(mbase, offset); | |
329 | txcsr &= ~(MUSB_TXCSR_DMAENAB | |
330 | | MUSB_TXCSR_AUTOSET); | |
331 | musb_writew(mbase, offset, txcsr); | |
332 | /* Send out the packet */ | |
333 | txcsr &= ~MUSB_TXCSR_DMAMODE; | |
334 | txcsr |= MUSB_TXCSR_TXPKTRDY; | |
335 | musb_writew(mbase, offset, txcsr); | |
336 | } | |
337 | musb_dma_completion(musb, musb_channel->epnum, | |
338 | musb_channel->transmit); | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
343 | retval = IRQ_HANDLED; | |
344 | done: | |
345 | spin_unlock_irqrestore(&musb->lock, flags); | |
346 | return retval; | |
347 | } | |
348 | ||
349 | void dma_controller_destroy(struct dma_controller *c) | |
350 | { | |
351 | struct musb_dma_controller *controller = container_of(c, | |
352 | struct musb_dma_controller, controller); | |
353 | ||
354 | if (!controller) | |
355 | return; | |
356 | ||
357 | if (controller->irq) | |
358 | free_irq(controller->irq, c); | |
359 | ||
360 | kfree(controller); | |
361 | } | |
362 | ||
363 | struct dma_controller *__init | |
364 | dma_controller_create(struct musb *musb, void __iomem *base) | |
365 | { | |
366 | struct musb_dma_controller *controller; | |
367 | struct device *dev = musb->controller; | |
368 | struct platform_device *pdev = to_platform_device(dev); | |
369 | int irq = platform_get_irq(pdev, 1); | |
370 | ||
371 | if (irq == 0) { | |
372 | dev_err(dev, "No DMA interrupt line!\n"); | |
373 | return NULL; | |
374 | } | |
375 | ||
376 | controller = kzalloc(sizeof(*controller), GFP_KERNEL); | |
377 | if (!controller) | |
378 | return NULL; | |
379 | ||
380 | controller->channel_count = MUSB_HSDMA_CHANNELS; | |
381 | controller->private_data = musb; | |
382 | controller->base = base; | |
383 | ||
384 | controller->controller.start = dma_controller_start; | |
385 | controller->controller.stop = dma_controller_stop; | |
386 | controller->controller.channel_alloc = dma_channel_allocate; | |
387 | controller->controller.channel_release = dma_channel_release; | |
388 | controller->controller.channel_program = dma_channel_program; | |
389 | controller->controller.channel_abort = dma_channel_abort; | |
390 | ||
391 | if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, | |
392 | dev_name(musb->controller), &controller->controller)) { | |
393 | dev_err(dev, "request_irq %d failed!\n", irq); | |
394 | dma_controller_destroy(&controller->controller); | |
395 | ||
396 | return NULL; | |
397 | } | |
398 | ||
399 | controller->irq = irq; | |
400 | ||
401 | return &controller->controller; | |
402 | } |