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staging: r8187se: Change to use common eeprom routines in EEPROM_93CX
[net-next-2.6.git] / drivers / staging / rtl8187se / r8180_core.c
CommitLineData
c8d86be3
GKH		 1/*
2 This is part of rtl818x pci OpenSource driver - v 0.1
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public License)
5
6 Parts of this driver are based on the GPL part of the official
7 Realtek driver.
8
9 Parts of this driver are based on the rtl8180 driver skeleton
10 from Patric Schenke & Andres Salomon.
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver.
13
14 Parts of BB/RF code are derived from David Young rtl8180 netbsd driver.
15
16 RSSI calc function from 'The Deuce'
17
18 Some ideas borrowed from the 8139too.c driver included in linux kernel.
19
20 We (I?) want to thanks the Authors of those projecs and also the
21 Ndiswrapper's project Authors.
22
23 A big big thanks goes also to Realtek corp. for their help in my attempt to
24 add RTL8185 and RTL8225 support, and to David Young also.
b6d11c07
BZ		 25
26 Power management interface routines.
27 Written by Mariusz Matuszek.
c8d86be3
GKH		 28*/
29
c8d86be3 30#undef RX_DONT_PASS_UL
c8d86be3 31#undef DUMMY_RX
c8d86be3 32
c8d86be3 33#include <linux/syscalls.h>
742821ce 34#include <linux/eeprom_93cx6.h>
fd882783 35
c8d86be3
GKH		 36#include "r8180_hw.h"
37#include "r8180.h"
c8d86be3 38#include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
c8d86be3
GKH		 39#include "r8180_93cx6.h" /* Card EEPROM */
40#include "r8180_wx.h"
41#include "r8180_dm.h"
42
fd9b8d6e 43#include "ieee80211/dot11d.h"
c8d86be3 44
c8d86be3
GKH		 45static struct pci_device_id rtl8180_pci_id_tbl[] __devinitdata = {
46 {
47 .vendor = PCI_VENDOR_ID_REALTEK,
c8d86be3
GKH		 48 .device = 0x8199,
49 .subvendor = PCI_ANY_ID,
50 .subdevice = PCI_ANY_ID,
51 .driver_data = 0,
52 },
c8d86be3
GKH		 53 {
54 .vendor = 0,
55 .device = 0,
56 .subvendor = 0,
57 .subdevice = 0,
58 .driver_data = 0,
59 }
60};
61
62
63static char* ifname = "wlan%d";
64static int hwseqnum = 0;
c8d86be3
GKH		 65static int hwwep = 0;
66static int channels = 0x3fff;
67
68#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
69#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
70MODULE_LICENSE("GPL");
71MODULE_DEVICE_TABLE(pci, rtl8180_pci_id_tbl);
72MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
73MODULE_DESCRIPTION("Linux driver for Realtek RTL8180 / RTL8185 WiFi cards");
74
75
c8d86be3
GKH		 76module_param(ifname, charp, S_IRUGO|S_IWUSR );
77module_param(hwseqnum,int, S_IRUGO|S_IWUSR);
78module_param(hwwep,int, S_IRUGO|S_IWUSR);
79module_param(channels,int, S_IRUGO|S_IWUSR);
c8d86be3
GKH		 80
81MODULE_PARM_DESC(devname," Net interface name, wlan%d=default");
c8d86be3
GKH		 82MODULE_PARM_DESC(hwseqnum," Try to use hardware 802.11 header sequence numbers. Zero=default");
83MODULE_PARM_DESC(hwwep," Try to use hardware WEP support. Still broken and not available on all cards");
84MODULE_PARM_DESC(channels," Channel bitmask for specific locales. NYI");
85
86
87static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
88 const struct pci_device_id *id);
89
90static void __devexit rtl8180_pci_remove(struct pci_dev *pdev);
91
92static void rtl8180_shutdown (struct pci_dev *pdev)
93{
94 struct net_device *dev = pci_get_drvdata(pdev);
727ae303
AB		 95 if (dev->netdev_ops->ndo_stop)
96 dev->netdev_ops->ndo_stop(dev);
c8d86be3
GKH		 97 pci_disable_device(pdev);
98}
99
b6d11c07
BZ		 100static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
101{
102 struct net_device *dev = pci_get_drvdata(pdev);
103
104 if (!netif_running(dev))
105 goto out_pci_suspend;
106
107 if (dev->netdev_ops->ndo_stop)
108 dev->netdev_ops->ndo_stop(dev);
109
110 netif_device_detach(dev);
111
112out_pci_suspend:
113 pci_save_state(pdev);
114 pci_disable_device(pdev);
115 pci_set_power_state(pdev, pci_choose_state(pdev, state));
116 return 0;
117}
118
119static int rtl8180_resume(struct pci_dev *pdev)
120{
121 struct net_device *dev = pci_get_drvdata(pdev);
122 int err;
123 u32 val;
124
125 pci_set_power_state(pdev, PCI_D0);
126
127 err = pci_enable_device(pdev);
128 if (err) {
129 printk(KERN_ERR "%s: pci_enable_device failed on resume\n",
130 dev->name);
131
132 return err;
133 }
134
135 pci_restore_state(pdev);
136
137 /*
138 * Suspend/Resume resets the PCI configuration space, so we have to
139 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
140 * from interfering with C3 CPU state. pci_restore_state won't help
141 * here since it only restores the first 64 bytes pci config header.
142 */
143 pci_read_config_dword(pdev, 0x40, &val);
144 if ((val & 0x0000ff00) != 0)
145 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
146
147 if (!netif_running(dev))
148 goto out;
149
150 if (dev->netdev_ops->ndo_open)
151 dev->netdev_ops->ndo_open(dev);
152
153 netif_device_attach(dev);
154out:
155 return 0;
156}
157
c8d86be3 158static struct pci_driver rtl8180_pci_driver = {
fd882783
BZ		 159 .name = RTL8180_MODULE_NAME,
160 .id_table = rtl8180_pci_id_tbl,
161 .probe = rtl8180_pci_probe,
162 .remove = __devexit_p(rtl8180_pci_remove),
163 .suspend = rtl8180_suspend,
164 .resume = rtl8180_resume,
c8d86be3
GKH		 165 .shutdown = rtl8180_shutdown,
166};
167
c8d86be3
GKH		 168u8 read_nic_byte(struct net_device *dev, int x)
169{
170 return 0xff&readb((u8*)dev->mem_start +x);
171}
172
173u32 read_nic_dword(struct net_device *dev, int x)
174{
175 return readl((u8*)dev->mem_start +x);
176}
177
178u16 read_nic_word(struct net_device *dev, int x)
179{
180 return readw((u8*)dev->mem_start +x);
181}
182
183void write_nic_byte(struct net_device *dev, int x,u8 y)
184{
185 writeb(y,(u8*)dev->mem_start +x);
186 udelay(20);
187}
188
189void write_nic_dword(struct net_device *dev, int x,u32 y)
190{
191 writel(y,(u8*)dev->mem_start +x);
192 udelay(20);
193}
194
195void write_nic_word(struct net_device *dev, int x,u16 y)
196{
197 writew(y,(u8*)dev->mem_start +x);
198 udelay(20);
199}
200
c8d86be3
GKH		 201inline void force_pci_posting(struct net_device *dev)
202{
203 read_nic_byte(dev,EPROM_CMD);
c8d86be3 204 mb();
c8d86be3
GKH		 205}
206
c8d86be3
GKH		 207irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs);
208void set_nic_rxring(struct net_device *dev);
209void set_nic_txring(struct net_device *dev);
210static struct net_device_stats *rtl8180_stats(struct net_device *dev);
211void rtl8180_commit(struct net_device *dev);
212void rtl8180_start_tx_beacon(struct net_device *dev);
213
c8d86be3
GKH		 214static struct proc_dir_entry *rtl8180_proc = NULL;
215
216static int proc_get_registers(char *page, char **start,
217 off_t offset, int count,
218 int *eof, void *data)
219{
220 struct net_device *dev = data;
c8d86be3
GKH		 221 int len = 0;
222 int i,n;
fd882783 223 int max = 0xff;
c8d86be3
GKH		 224
225 /* This dump the current register page */
fd882783
BZ		 226 for (n = 0; n <= max;) {
227 len += snprintf(page + len, count - len, "\nD: %2x > ", n);
c8d86be3 228
fd882783
BZ		 229 for (i = 0; i < 16 && n <= max; i++, n++)
230 len += snprintf(page + len, count - len, "%2x ",
231 read_nic_byte(dev, n));
c8d86be3
GKH		 232 }
233 len += snprintf(page + len, count - len,"\n");
234
c8d86be3
GKH		 235 *eof = 1;
236 return len;
c8d86be3
GKH		 237}
238
239int get_curr_tx_free_desc(struct net_device *dev, int priority);
240
241static int proc_get_stats_hw(char *page, char **start,
242 off_t offset, int count,
243 int *eof, void *data)
244{
c8d86be3 245 int len = 0;
c8d86be3 246
c8d86be3
GKH		 247 *eof = 1;
248 return len;
249}
250
c8d86be3
GKH		 251static int proc_get_stats_rx(char *page, char **start,
252 off_t offset, int count,
253 int *eof, void *data)
254{
255 struct net_device *dev = data;
256 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
257
258 int len = 0;
259
260 len += snprintf(page + len, count - len,
c8d86be3
GKH		 261 "RX OK: %lu\n"
262 "RX Retry: %lu\n"
263 "RX CRC Error(0-500): %lu\n"
264 "RX CRC Error(500-1000): %lu\n"
265 "RX CRC Error(>1000): %lu\n"
266 "RX ICV Error: %lu\n",
267 priv->stats.rxint,
268 priv->stats.rxerr,
269 priv->stats.rxcrcerrmin,
270 priv->stats.rxcrcerrmid,
271 priv->stats.rxcrcerrmax,
272 priv->stats.rxicverr
273 );
274
275 *eof = 1;
276 return len;
277}
278
c8d86be3
GKH		 279static int proc_get_stats_tx(char *page, char **start,
280 off_t offset, int count,
281 int *eof, void *data)
282{
283 struct net_device *dev = data;
284 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
285
286 int len = 0;
287 unsigned long totalOK;
288
289 totalOK=priv->stats.txnpokint+priv->stats.txhpokint+priv->stats.txlpokint;
290 len += snprintf(page + len, count - len,
c8d86be3
GKH		 291 "TX OK: %lu\n"
292 "TX Error: %lu\n"
293 "TX Retry: %lu\n"
294 "TX beacon OK: %lu\n"
295 "TX beacon error: %lu\n",
296 totalOK,
297 priv->stats.txnperr+priv->stats.txhperr+priv->stats.txlperr,
298 priv->stats.txretry,
299 priv->stats.txbeacon,
300 priv->stats.txbeaconerr
301 );
302
303 *eof = 1;
304 return len;
305}
306
c8d86be3
GKH		 307void rtl8180_proc_module_init(void)
308{
309 DMESG("Initializing proc filesystem");
c8d86be3 310 rtl8180_proc=create_proc_entry(RTL8180_MODULE_NAME, S_IFDIR, init_net.proc_net);
c8d86be3
GKH		 311}
312
c8d86be3
GKH		 313void rtl8180_proc_module_remove(void)
314{
c8d86be3 315 remove_proc_entry(RTL8180_MODULE_NAME, init_net.proc_net);
c8d86be3
GKH		 316}
317
c8d86be3
GKH		 318void rtl8180_proc_remove_one(struct net_device *dev)
319{
320 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
321 if (priv->dir_dev) {
322 remove_proc_entry("stats-hw", priv->dir_dev);
323 remove_proc_entry("stats-tx", priv->dir_dev);
324 remove_proc_entry("stats-rx", priv->dir_dev);
c8d86be3
GKH		 325 remove_proc_entry("registers", priv->dir_dev);
326 remove_proc_entry(dev->name, rtl8180_proc);
327 priv->dir_dev = NULL;
328 }
329}
330
c8d86be3
GKH		 331void rtl8180_proc_init_one(struct net_device *dev)
332{
333 struct proc_dir_entry *e;
334 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 335
be286fd2 336 priv->dir_dev = rtl8180_proc;
c8d86be3 337 if (!priv->dir_dev) {
be286fd2 338 DMESGE("Unable to initialize /proc/net/r8180/%s\n",
c8d86be3
GKH		 339 dev->name);
340 return;
341 }
342
343 e = create_proc_read_entry("stats-hw", S_IFREG | S_IRUGO,
344 priv->dir_dev, proc_get_stats_hw, dev);
c8d86be3
GKH		 345 if (!e) {
346 DMESGE("Unable to initialize "
be286fd2 347 "/proc/net/r8180/%s/stats-hw\n",
c8d86be3
GKH		 348 dev->name);
349 }
350
351 e = create_proc_read_entry("stats-rx", S_IFREG | S_IRUGO,
352 priv->dir_dev, proc_get_stats_rx, dev);
c8d86be3
GKH		 353 if (!e) {
354 DMESGE("Unable to initialize "
be286fd2 355 "/proc/net/r8180/%s/stats-rx\n",
c8d86be3
GKH		 356 dev->name);
357 }
358
359
360 e = create_proc_read_entry("stats-tx", S_IFREG | S_IRUGO,
361 priv->dir_dev, proc_get_stats_tx, dev);
c8d86be3
GKH		 362 if (!e) {
363 DMESGE("Unable to initialize "
be286fd2 364 "/proc/net/r8180/%s/stats-tx\n",
c8d86be3
GKH		 365 dev->name);
366 }
c8d86be3
GKH		 367
368 e = create_proc_read_entry("registers", S_IFREG | S_IRUGO,
369 priv->dir_dev, proc_get_registers, dev);
c8d86be3
GKH		 370 if (!e) {
371 DMESGE("Unable to initialize "
be286fd2 372 "/proc/net/r8180/%s/registers\n",
c8d86be3
GKH		 373 dev->name);
374 }
375}
fd882783 376
c8d86be3
GKH		 377/*
378 FIXME: check if we can use some standard already-existent
379 data type+functions in kernel
380*/
381
382short buffer_add(struct buffer **buffer, u32 *buf, dma_addr_t dma,
383 struct buffer **bufferhead)
384{
c8d86be3
GKH		 385 struct buffer *tmp;
386
387 if(! *buffer){
388
389 *buffer = kmalloc(sizeof(struct buffer),GFP_KERNEL);
390
391 if (*buffer == NULL) {
392 DMESGE("Failed to kmalloc head of TX/RX struct");
393 return -1;
394 }
395 (*buffer)->next=*buffer;
396 (*buffer)->buf=buf;
397 (*buffer)->dma=dma;
398 if(bufferhead !=NULL)
399 (*bufferhead) = (*buffer);
400 return 0;
401 }
402 tmp=*buffer;
403
404 while(tmp->next!=(*buffer)) tmp=tmp->next;
405 if ((tmp->next= kmalloc(sizeof(struct buffer),GFP_KERNEL)) == NULL){
406 DMESGE("Failed to kmalloc TX/RX struct");
407 return -1;
408 }
409 tmp->next->buf=buf;
410 tmp->next->dma=dma;
411 tmp->next->next=*buffer;
412
413 return 0;
414}
415
c8d86be3
GKH		 416void buffer_free(struct net_device *dev,struct buffer **buffer,int len,short
417consistent)
418{
419
420 struct buffer *tmp,*next;
421 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
422 struct pci_dev *pdev=priv->pdev;
c8d86be3 423
fd882783
BZ		 424 if (!*buffer)
425 return;
c8d86be3 426
fd882783 427 tmp = *buffer;
c8d86be3 428
c8d86be3
GKH		 429 do{
430 next=tmp->next;
431 if(consistent){
432 pci_free_consistent(pdev,len,
433 tmp->buf,tmp->dma);
434 }else{
435 pci_unmap_single(pdev, tmp->dma,
436 len,PCI_DMA_FROMDEVICE);
437 kfree(tmp->buf);
438 }
439 kfree(tmp);
440 tmp = next;
441 }
442 while(next != *buffer);
443
444 *buffer=NULL;
445}
446
c8d86be3
GKH		 447void print_buffer(u32 *buffer, int len)
448{
449 int i;
450 u8 *buf =(u8*)buffer;
451
452 printk("ASCII BUFFER DUMP (len: %x):\n",len);
453
454 for(i=0;i<len;i++)
455 printk("%c",buf[i]);
456
457 printk("\nBINARY BUFFER DUMP (len: %x):\n",len);
458
459 for(i=0;i<len;i++)
460 printk("%02x",buf[i]);
461
462 printk("\n");
463}
464
c8d86be3
GKH		 465int get_curr_tx_free_desc(struct net_device *dev, int priority)
466{
467 struct r8180_priv *priv = ieee80211_priv(dev);
468 u32* tail;
469 u32* head;
470 int ret;
471
472 switch (priority){
473 case MANAGE_PRIORITY:
474 head = priv->txmapringhead;
475 tail = priv->txmapringtail;
476 break;
477 case BK_PRIORITY:
478 head = priv->txbkpringhead;
479 tail = priv->txbkpringtail;
480 break;
481 case BE_PRIORITY:
482 head = priv->txbepringhead;
483 tail = priv->txbepringtail;
484 break;
485 case VI_PRIORITY:
486 head = priv->txvipringhead;
487 tail = priv->txvipringtail;
488 break;
489 case VO_PRIORITY:
490 head = priv->txvopringhead;
491 tail = priv->txvopringtail;
492 break;
493 case HI_PRIORITY:
494 head = priv->txhpringhead;
495 tail = priv->txhpringtail;
496 break;
497 default:
498 return -1;
499 }
500
fd882783 501 if (head <= tail)
c8d86be3
GKH		 502 ret = priv->txringcount - (tail - head)/8;
503 else
504 ret = (head - tail)/8;
505
fd882783
BZ		 506 if (ret > priv->txringcount)
507 DMESG("BUG");
508
c8d86be3 509 return ret;
c8d86be3
GKH		 510}
511
c8d86be3
GKH		 512short check_nic_enought_desc(struct net_device *dev, int priority)
513{
514 struct r8180_priv *priv = ieee80211_priv(dev);
515 struct ieee80211_device *ieee = netdev_priv(dev);
c8d86be3 516 int requiredbyte, required;
fd882783 517
c8d86be3
GKH		 518 requiredbyte = priv->ieee80211->fts + sizeof(struct ieee80211_header_data);
519
fd882783 520 if (ieee->current_network.QoS_Enable)
c8d86be3 521 requiredbyte += 2;
c8d86be3
GKH		 522
523 required = requiredbyte / (priv->txbuffsize-4);
fd882783
BZ		 524
525 if (requiredbyte % priv->txbuffsize)
526 required++;
527
c8d86be3
GKH		 528 /* for now we keep two free descriptor as a safety boundary
529 * between the tail and the head
530 */
531
532 return (required+2 < get_curr_tx_free_desc(dev,priority));
533}
534
c8d86be3
GKH		 535void fix_tx_fifo(struct net_device *dev)
536{
537 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
538 u32 *tmp;
539 int i;
ff954853 540
c8d86be3
GKH		 541 for (tmp=priv->txmapring, i=0;
542 i < priv->txringcount;
543 tmp+=8, i++){
544 *tmp = *tmp &~ (1<<31);
545 }
546
547 for (tmp=priv->txbkpring, i=0;
548 i < priv->txringcount;
549 tmp+=8, i++) {
550 *tmp = *tmp &~ (1<<31);
551 }
552
553 for (tmp=priv->txbepring, i=0;
554 i < priv->txringcount;
555 tmp+=8, i++){
556 *tmp = *tmp &~ (1<<31);
557 }
558 for (tmp=priv->txvipring, i=0;
559 i < priv->txringcount;
560 tmp+=8, i++) {
561 *tmp = *tmp &~ (1<<31);
562 }
563
564 for (tmp=priv->txvopring, i=0;
565 i < priv->txringcount;
566 tmp+=8, i++){
567 *tmp = *tmp &~ (1<<31);
568 }
569
570 for (tmp=priv->txhpring, i=0;
571 i < priv->txringcount;
572 tmp+=8,i++){
573 *tmp = *tmp &~ (1<<31);
574 }
575
576 for (tmp=priv->txbeaconring, i=0;
577 i < priv->txbeaconcount;
578 tmp+=8, i++){
579 *tmp = *tmp &~ (1<<31);
580 }
ff954853 581
c8d86be3
GKH		 582 priv->txmapringtail = priv->txmapring;
583 priv->txmapringhead = priv->txmapring;
584 priv->txmapbufstail = priv->txmapbufs;
585
586 priv->txbkpringtail = priv->txbkpring;
587 priv->txbkpringhead = priv->txbkpring;
588 priv->txbkpbufstail = priv->txbkpbufs;
589
590 priv->txbepringtail = priv->txbepring;
591 priv->txbepringhead = priv->txbepring;
592 priv->txbepbufstail = priv->txbepbufs;
593
594 priv->txvipringtail = priv->txvipring;
595 priv->txvipringhead = priv->txvipring;
596 priv->txvipbufstail = priv->txvipbufs;
597
598 priv->txvopringtail = priv->txvopring;
599 priv->txvopringhead = priv->txvopring;
600 priv->txvopbufstail = priv->txvopbufs;
601
602 priv->txhpringtail = priv->txhpring;
603 priv->txhpringhead = priv->txhpring;
604 priv->txhpbufstail = priv->txhpbufs;
605
606 priv->txbeaconringtail = priv->txbeaconring;
607 priv->txbeaconbufstail = priv->txbeaconbufs;
608 set_nic_txring(dev);
609
610 ieee80211_reset_queue(priv->ieee80211);
611 priv->ack_tx_to_ieee = 0;
612}
613
c8d86be3
GKH		 614void fix_rx_fifo(struct net_device *dev)
615{
616 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
617 u32 *tmp;
618 struct buffer *rxbuf;
619 u8 rx_desc_size;
620
c8d86be3 621 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3 622
c8d86be3
GKH		 623 for (tmp=priv->rxring, rxbuf=priv->rxbufferhead;
624 (tmp < (priv->rxring)+(priv->rxringcount)*rx_desc_size);
625 tmp+=rx_desc_size,rxbuf=rxbuf->next){
626 *(tmp+2) = rxbuf->dma;
627 *tmp=*tmp &~ 0xfff;
628 *tmp=*tmp | priv->rxbuffersize;
629 *tmp |= (1<<31);
630 }
631
c8d86be3
GKH		 632 priv->rxringtail=priv->rxring;
633 priv->rxbuffer=priv->rxbufferhead;
634 priv->rx_skb_complete=1;
635 set_nic_rxring(dev);
636}
637
c8d86be3 638unsigned char QUALITY_MAP[] = {
fd882783
BZ		 639 0x64, 0x64, 0x64, 0x63, 0x63, 0x62, 0x62, 0x61,
640 0x61, 0x60, 0x60, 0x5f, 0x5f, 0x5e, 0x5d, 0x5c,
641 0x5b, 0x5a, 0x59, 0x57, 0x56, 0x54, 0x52, 0x4f,
642 0x4c, 0x49, 0x45, 0x41, 0x3c, 0x37, 0x31, 0x29,
643 0x24, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22,
644 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x20,
645 0x20, 0x20, 0x20, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e,
646 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1a, 0x19, 0x19,
647 0x18, 0x17, 0x16, 0x15, 0x14, 0x12, 0x11, 0x0f,
648 0x0e, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x01, 0x00
c8d86be3
GKH		 649};
650
651unsigned char STRENGTH_MAP[] = {
fd882783
BZ		 652 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e,
653 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50,
654 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f,
655 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b,
656 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17,
657 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13,
658 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f,
659 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
660 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07,
661 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
c8d86be3
GKH		 662};
663
fd882783
BZ		 664void rtl8180_RSSI_calc(struct net_device *dev, u8 *rssi, u8 *qual)
665{
c8d86be3
GKH		 666 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
667 u32 temp;
668 u32 temp2;
669 u32 temp3;
670 u32 lsb;
671 u32 q;
672 u32 orig_qual;
673 u8 _rssi;
674
675 q = *qual;
676 orig_qual = *qual;
677 _rssi = 0; // avoid gcc complains..
678
679 if (q <= 0x4e) {
680 temp = QUALITY_MAP[q];
681 } else {
682 if( q & 0x80 ) {
683 temp = 0x32;
684 } else {
685 temp = 1;
686 }
687 }
688
689 *qual = temp;
690 temp2 = *rssi;
691
692 switch(priv->rf_chip){
693 case RFCHIPID_RFMD:
694 lsb = temp2 & 1;
695 temp2 &= 0x7e;
696 if ( !lsb || !(temp2 <= 0x3c) ) {
697 temp2 = 0x64;
698 } else {
699 temp2 = 100 * temp2 / 0x3c;
700 }
701 *rssi = temp2 & 0xff;
702 _rssi = temp2 & 0xff;
703 break;
704 case RFCHIPID_INTERSIL:
705 lsb = temp2;
706 temp2 &= 0xfffffffe;
707 temp2 *= 251;
708 temp3 = temp2;
709 temp2 <<= 6;
710 temp3 += temp2;
711 temp3 <<= 1;
712 temp2 = 0x4950df;
713 temp2 -= temp3;
714 lsb &= 1;
715 if ( temp2 <= 0x3e0000 ) {
716 if ( temp2 < 0xffef0000 )
717 temp2 = 0xffef0000;
718 } else {
719 temp2 = 0x3e0000;
720 }
721 if ( !lsb ) {
722 temp2 -= 0xf0000;
723 } else {
724 temp2 += 0xf0000;
725 }
726
727 temp3 = 0x4d0000;
728 temp3 -= temp2;
729 temp3 *= 100;
730 temp3 = temp3 / 0x6d;
731 temp3 >>= 0x10;
732 _rssi = temp3 & 0xff;
733 *rssi = temp3 & 0xff;
734 break;
735 case RFCHIPID_GCT:
736 lsb = temp2 & 1;
737 temp2 &= 0x7e;
738 if ( ! lsb || !(temp2 <= 0x3c) ){
739 temp2 = 0x64;
740 } else {
741 temp2 = (100 * temp2) / 0x3c;
742 }
743 *rssi = temp2 & 0xff;
744 _rssi = temp2 & 0xff;
745 break;
746 case RFCHIPID_PHILIPS:
747 if( orig_qual <= 0x4e ){
748 _rssi = STRENGTH_MAP[orig_qual];
749 *rssi = _rssi;
750 } else {
751 orig_qual -= 0x80;
752 if ( !orig_qual ){
753 _rssi = 1;
754 *rssi = 1;
755 } else {
756 _rssi = 0x32;
757 *rssi = 0x32;
758 }
759 }
760 break;
c8d86be3
GKH		 761 case RFCHIPID_MAXIM:
762 lsb = temp2 & 1;
763 temp2 &= 0x7e;
764 temp2 >>= 1;
765 temp2 += 0x42;
766 if( lsb != 0 ){
767 temp2 += 0xa;
768 }
769 *rssi = temp2 & 0xff;
770 _rssi = temp2 & 0xff;
771 break;
772 }
773
774 if ( _rssi < 0x64 ){
775 if ( _rssi == 0 ) {
776 *rssi = 1;
777 }
778 } else {
779 *rssi = 0x64;
780 }
781
782 return;
783}
784
c8d86be3
GKH		 785void rtl8180_irq_enable(struct net_device *dev)
786{
787 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
fd882783 788
c8d86be3 789 priv->irq_enabled = 1;
c8d86be3
GKH		 790 write_nic_word(dev,INTA_MASK, priv->irq_mask);
791}
792
c8d86be3
GKH		 793void rtl8180_irq_disable(struct net_device *dev)
794{
795 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
796
c8d86be3 797 write_nic_dword(dev,IMR,0);
c8d86be3
GKH		 798 force_pci_posting(dev);
799 priv->irq_enabled = 0;
800}
801
c8d86be3
GKH		 802void rtl8180_set_mode(struct net_device *dev,int mode)
803{
804 u8 ecmd;
fd882783 805
c8d86be3
GKH		 806 ecmd=read_nic_byte(dev, EPROM_CMD);
807 ecmd=ecmd &~ EPROM_CMD_OPERATING_MODE_MASK;
808 ecmd=ecmd | (mode<<EPROM_CMD_OPERATING_MODE_SHIFT);
809 ecmd=ecmd &~ (1<<EPROM_CS_SHIFT);
810 ecmd=ecmd &~ (1<<EPROM_CK_SHIFT);
811 write_nic_byte(dev, EPROM_CMD, ecmd);
812}
813
814void rtl8180_adapter_start(struct net_device *dev);
815void rtl8180_beacon_tx_enable(struct net_device *dev);
816
817void rtl8180_update_msr(struct net_device *dev)
818{
819 struct r8180_priv *priv = ieee80211_priv(dev);
820 u8 msr;
821 u32 rxconf;
822
823 msr = read_nic_byte(dev, MSR);
824 msr &= ~ MSR_LINK_MASK;
825
826 rxconf=read_nic_dword(dev,RX_CONF);
827
828 if(priv->ieee80211->state == IEEE80211_LINKED)
829 {
830 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
831 msr |= (MSR_LINK_ADHOC<<MSR_LINK_SHIFT);
832 else if (priv->ieee80211->iw_mode == IW_MODE_MASTER)
833 msr |= (MSR_LINK_MASTER<<MSR_LINK_SHIFT);
834 else if (priv->ieee80211->iw_mode == IW_MODE_INFRA)
835 msr |= (MSR_LINK_MANAGED<<MSR_LINK_SHIFT);
836 else
837 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
838 rxconf |= (1<<RX_CHECK_BSSID_SHIFT);
839
840 }else {
841 msr |= (MSR_LINK_NONE<<MSR_LINK_SHIFT);
842 rxconf &= ~(1<<RX_CHECK_BSSID_SHIFT);
843 }
844
845 write_nic_byte(dev, MSR, msr);
846 write_nic_dword(dev, RX_CONF, rxconf);
c8d86be3
GKH		 847}
848
c8d86be3
GKH		 849void rtl8180_set_chan(struct net_device *dev,short ch)
850{
851 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
852
fd882783 853 if ((ch > 14) || (ch < 1)) {
d599edca 854 printk("In %s: Invalid chnanel %d\n", __func__, ch);
c8d86be3
GKH		 855 return;
856 }
857
858 priv->chan=ch;
c8d86be3 859 priv->rf_set_chan(dev,priv->chan);
c8d86be3
GKH		 860}
861
c8d86be3
GKH		 862void rtl8180_rx_enable(struct net_device *dev)
863{
864 u8 cmd;
865 u32 rxconf;
866 /* for now we accept data, management & ctl frame*/
867 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
868
869 rxconf=read_nic_dword(dev,RX_CONF);
870 rxconf = rxconf &~ MAC_FILTER_MASK;
871 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
872 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
873 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
874 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
fd882783
BZ		 875 if (dev->flags & IFF_PROMISC)
876 DMESG("NIC in promisc mode");
c8d86be3
GKH		 877
878 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
879 dev->flags & IFF_PROMISC){
880 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
881 }else{
882 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
c8d86be3
GKH		 883 }
884
c8d86be3
GKH		 885 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
886 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
887 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
888 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
889 }
890
891 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
892 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
893
fd882783
BZ		 894 rxconf = rxconf & ~RX_FIFO_THRESHOLD_MASK;
895 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE << RX_FIFO_THRESHOLD_SHIFT);
c8d86be3
GKH		 896
897 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
898 rxconf = rxconf &~ MAX_RX_DMA_MASK;
899 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
900
fd882783 901 rxconf = rxconf | RCR_ONLYERLPKT;
c8d86be3
GKH		 902
903 rxconf = rxconf &~ RCR_CS_MASK;
fd882783 904
c8d86be3
GKH		 905 write_nic_dword(dev, RX_CONF, rxconf);
906
907 fix_rx_fifo(dev);
908
c8d86be3
GKH		 909 cmd=read_nic_byte(dev,CMD);
910 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
c8d86be3
GKH		 911}
912
c8d86be3
GKH		 913void set_nic_txring(struct net_device *dev)
914{
915 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 916
917 write_nic_dword(dev, TX_MANAGEPRIORITY_RING_ADDR, priv->txmapringdma);
c8d86be3 918 write_nic_dword(dev, TX_BKPRIORITY_RING_ADDR, priv->txbkpringdma);
c8d86be3 919 write_nic_dword(dev, TX_BEPRIORITY_RING_ADDR, priv->txbepringdma);
c8d86be3 920 write_nic_dword(dev, TX_VIPRIORITY_RING_ADDR, priv->txvipringdma);
c8d86be3 921 write_nic_dword(dev, TX_VOPRIORITY_RING_ADDR, priv->txvopringdma);
c8d86be3 922 write_nic_dword(dev, TX_HIGHPRIORITY_RING_ADDR, priv->txhpringdma);
c8d86be3
GKH		 923 write_nic_dword(dev, TX_BEACON_RING_ADDR, priv->txbeaconringdma);
924}
925
c8d86be3
GKH		 926void rtl8180_conttx_enable(struct net_device *dev)
927{
928 u32 txconf;
fd882783 929
c8d86be3
GKH		 930 txconf = read_nic_dword(dev,TX_CONF);
931 txconf = txconf &~ TX_LOOPBACK_MASK;
932 txconf = txconf | (TX_LOOPBACK_CONTINUE <<TX_LOOPBACK_SHIFT);
933 write_nic_dword(dev,TX_CONF,txconf);
934}
935
c8d86be3
GKH		 936void rtl8180_conttx_disable(struct net_device *dev)
937{
938 u32 txconf;
fd882783 939
c8d86be3
GKH		 940 txconf = read_nic_dword(dev,TX_CONF);
941 txconf = txconf &~ TX_LOOPBACK_MASK;
942 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
943 write_nic_dword(dev,TX_CONF,txconf);
944}
945
c8d86be3
GKH		 946void rtl8180_tx_enable(struct net_device *dev)
947{
948 u8 cmd;
949 u8 tx_agc_ctl;
950 u8 byte;
951 u32 txconf;
952 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 953
fd882783 954 txconf = read_nic_dword(dev, TX_CONF);
c8d86be3 955
d44eb889
LF		 956 byte = read_nic_byte(dev, CW_CONF);
957 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
958 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
959 write_nic_byte(dev, CW_CONF, byte);
c8d86be3 960
d44eb889
LF		 961 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
962 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
963 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
964 tx_agc_ctl |= (1<<TX_AGC_CTL_FEEDBACK_ANT);
965 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
966 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
967
968 txconf = txconf & ~(1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
c8d86be3
GKH		 969
970 txconf = txconf &~ TX_LOOPBACK_MASK;
971 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
972 txconf = txconf &~ TCR_DPRETRY_MASK;
973 txconf = txconf &~ TCR_RTSRETRY_MASK;
974 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
975 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
976 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
977
d44eb889
LF		 978 if (priv->hw_plcp_len)
979 txconf = txconf & ~TCR_PLCP_LEN;
980 else
981 txconf = txconf | TCR_PLCP_LEN;
fd882783 982
c8d86be3
GKH		 983 txconf = txconf &~ TCR_MXDMA_MASK;
984 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
985 txconf = txconf | TCR_CWMIN;
986 txconf = txconf | TCR_DISCW;
987
fd882783 988 txconf = txconf | (1 << TX_NOICV_SHIFT);
c8d86be3
GKH		 989
990 write_nic_dword(dev,TX_CONF,txconf);
991
c8d86be3
GKH		 992 fix_tx_fifo(dev);
993
c8d86be3
GKH		 994 cmd=read_nic_byte(dev,CMD);
995 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
996
c8d86be3 997 write_nic_dword(dev,TX_CONF,txconf);
c8d86be3
GKH		 998}
999
c8d86be3
GKH		 1000void rtl8180_beacon_tx_enable(struct net_device *dev)
1001{
1002 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1003
1004 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1005 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_BQ);
1006 write_nic_byte(dev,TPPollStop, priv->dma_poll_mask);
c8d86be3
GKH		 1007 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1008}
1009
c8d86be3
GKH		 1010void rtl8180_beacon_tx_disable(struct net_device *dev)
1011{
1012 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1013
1014 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1015 priv->dma_poll_stop_mask |= TPPOLLSTOP_BQ;
1016 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1017 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1018
1019}
1020
c8d86be3
GKH		 1021void rtl8180_rtx_disable(struct net_device *dev)
1022{
1023 u8 cmd;
1024 struct r8180_priv *priv = ieee80211_priv(dev);
1025
1026 cmd=read_nic_byte(dev,CMD);
1027 write_nic_byte(dev, CMD, cmd &~ \
1028 ((1<<CMD_RX_ENABLE_SHIFT)|(1<<CMD_TX_ENABLE_SHIFT)));
1029 force_pci_posting(dev);
1030 mdelay(10);
c8d86be3
GKH		 1031
1032 if(!priv->rx_skb_complete)
1033 dev_kfree_skb_any(priv->rx_skb);
1034}
1035
c8d86be3
GKH		 1036short alloc_tx_desc_ring(struct net_device *dev, int bufsize, int count,
1037 int addr)
1038{
1039 int i;
1040 u32 *desc;
1041 u32 *tmp;
1042 dma_addr_t dma_desc, dma_tmp;
1043 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1044 struct pci_dev *pdev = priv->pdev;
1045 void *buf;
1046
1047 if((bufsize & 0xfff) != bufsize) {
1048 DMESGE ("TX buffer allocation too large");
1049 return 0;
1050 }
1051 desc = (u32*)pci_alloc_consistent(pdev,
1052 sizeof(u32)*8*count+256, &dma_desc);
fd882783
BZ		 1053 if (desc == NULL)
1054 return -1;
c8d86be3 1055
fd882783 1056 if (dma_desc & 0xff)
c8d86be3
GKH		 1057 /*
1058 * descriptor's buffer must be 256 byte aligned
1059 * we shouldn't be here, since we set DMA mask !
1060 */
be286fd2 1061 WARN(1, "DMA buffer is not aligned\n");
fd882783
BZ		 1062
1063 tmp = desc;
1064
1065 for (i = 0; i < count; i++) {
1066 buf = (void *)pci_alloc_consistent(pdev, bufsize, &dma_tmp);
1067 if (buf == NULL)
1068 return -ENOMEM;
c8d86be3
GKH		 1069
1070 switch(addr) {
c8d86be3
GKH		 1071 case TX_MANAGEPRIORITY_RING_ADDR:
1072 if(-1 == buffer_add(&(priv->txmapbufs),buf,dma_tmp,NULL)){
1073 DMESGE("Unable to allocate mem for buffer NP");
1074 return -ENOMEM;
1075 }
1076 break;
c8d86be3
GKH		 1077 case TX_BKPRIORITY_RING_ADDR:
1078 if(-1 == buffer_add(&(priv->txbkpbufs),buf,dma_tmp,NULL)){
1079 DMESGE("Unable to allocate mem for buffer LP");
1080 return -ENOMEM;
1081 }
1082 break;
1083 case TX_BEPRIORITY_RING_ADDR:
1084 if(-1 == buffer_add(&(priv->txbepbufs),buf,dma_tmp,NULL)){
1085 DMESGE("Unable to allocate mem for buffer NP");
1086 return -ENOMEM;
1087 }
1088 break;
c8d86be3
GKH		 1089 case TX_VIPRIORITY_RING_ADDR:
1090 if(-1 == buffer_add(&(priv->txvipbufs),buf,dma_tmp,NULL)){
1091 DMESGE("Unable to allocate mem for buffer LP");
1092 return -ENOMEM;
1093 }
1094 break;
1095 case TX_VOPRIORITY_RING_ADDR:
1096 if(-1 == buffer_add(&(priv->txvopbufs),buf,dma_tmp,NULL)){
1097 DMESGE("Unable to allocate mem for buffer NP");
1098 return -ENOMEM;
1099 }
1100 break;
c8d86be3
GKH		 1101 case TX_HIGHPRIORITY_RING_ADDR:
1102 if(-1 == buffer_add(&(priv->txhpbufs),buf,dma_tmp,NULL)){
1103 DMESGE("Unable to allocate mem for buffer HP");
1104 return -ENOMEM;
1105 }
1106 break;
1107 case TX_BEACON_RING_ADDR:
1108 if(-1 == buffer_add(&(priv->txbeaconbufs),buf,dma_tmp,NULL)){
1109 DMESGE("Unable to allocate mem for buffer BP");
1110 return -ENOMEM;
1111 }
1112 break;
1113 }
1114 *tmp = *tmp &~ (1<<31); // descriptor empty, owned by the drv
1115 *(tmp+2) = (u32)dma_tmp;
1116 *(tmp+3) = bufsize;
1117
1118 if(i+1<count)
1119 *(tmp+4) = (u32)dma_desc+((i+1)*8*4);
1120 else
1121 *(tmp+4) = (u32)dma_desc;
1122
1123 tmp=tmp+8;
1124 }
1125
1126 switch(addr) {
1127 case TX_MANAGEPRIORITY_RING_ADDR:
1128 priv->txmapringdma=dma_desc;
1129 priv->txmapring=desc;
1130 break;
c8d86be3
GKH		 1131 case TX_BKPRIORITY_RING_ADDR:
1132 priv->txbkpringdma=dma_desc;
1133 priv->txbkpring=desc;
1134 break;
c8d86be3
GKH		 1135 case TX_BEPRIORITY_RING_ADDR:
1136 priv->txbepringdma=dma_desc;
1137 priv->txbepring=desc;
1138 break;
c8d86be3
GKH		 1139 case TX_VIPRIORITY_RING_ADDR:
1140 priv->txvipringdma=dma_desc;
1141 priv->txvipring=desc;
1142 break;
c8d86be3
GKH		 1143 case TX_VOPRIORITY_RING_ADDR:
1144 priv->txvopringdma=dma_desc;
1145 priv->txvopring=desc;
1146 break;
c8d86be3
GKH		 1147 case TX_HIGHPRIORITY_RING_ADDR:
1148 priv->txhpringdma=dma_desc;
1149 priv->txhpring=desc;
1150 break;
c8d86be3
GKH		 1151 case TX_BEACON_RING_ADDR:
1152 priv->txbeaconringdma=dma_desc;
1153 priv->txbeaconring=desc;
1154 break;
1155
1156 }
1157
c8d86be3
GKH		 1158 return 0;
1159}
1160
c8d86be3
GKH		 1161void free_tx_desc_rings(struct net_device *dev)
1162{
c8d86be3
GKH		 1163 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1164 struct pci_dev *pdev=priv->pdev;
1165 int count = priv->txringcount;
1166
1167 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1168 priv->txmapring, priv->txmapringdma);
1169 buffer_free(dev,&(priv->txmapbufs),priv->txbuffsize,1);
1170
1171 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1172 priv->txbkpring, priv->txbkpringdma);
1173 buffer_free(dev,&(priv->txbkpbufs),priv->txbuffsize,1);
1174
1175 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1176 priv->txbepring, priv->txbepringdma);
1177 buffer_free(dev,&(priv->txbepbufs),priv->txbuffsize,1);
1178
1179 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1180 priv->txvipring, priv->txvipringdma);
1181 buffer_free(dev,&(priv->txvipbufs),priv->txbuffsize,1);
1182
1183 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1184 priv->txvopring, priv->txvopringdma);
1185 buffer_free(dev,&(priv->txvopbufs),priv->txbuffsize,1);
1186
1187 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1188 priv->txhpring, priv->txhpringdma);
1189 buffer_free(dev,&(priv->txhpbufs),priv->txbuffsize,1);
1190
1191 count = priv->txbeaconcount;
1192 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1193 priv->txbeaconring, priv->txbeaconringdma);
1194 buffer_free(dev,&(priv->txbeaconbufs),priv->txbuffsize,1);
1195}
1196
c8d86be3
GKH		 1197void free_rx_desc_ring(struct net_device *dev)
1198{
1199 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1200 struct pci_dev *pdev = priv->pdev;
c8d86be3
GKH		 1201 int count = priv->rxringcount;
1202
c8d86be3
GKH		 1203 pci_free_consistent(pdev, sizeof(u32)*8*count+256,
1204 priv->rxring, priv->rxringdma);
c8d86be3
GKH		 1205
1206 buffer_free(dev,&(priv->rxbuffer),priv->rxbuffersize,0);
1207}
1208
c8d86be3
GKH		 1209short alloc_rx_desc_ring(struct net_device *dev, u16 bufsize, int count)
1210{
1211 int i;
1212 u32 *desc;
1213 u32 *tmp;
1214 dma_addr_t dma_desc,dma_tmp;
1215 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1216 struct pci_dev *pdev=priv->pdev;
1217 void *buf;
1218 u8 rx_desc_size;
1219
c8d86be3 1220 rx_desc_size = 8; // 4*8 = 32 bytes
c8d86be3
GKH		 1221
1222 if((bufsize & 0xfff) != bufsize){
1223 DMESGE ("RX buffer allocation too large");
1224 return -1;
1225 }
1226
1227 desc = (u32*)pci_alloc_consistent(pdev,sizeof(u32)*rx_desc_size*count+256,
1228 &dma_desc);
1229
fd882783 1230 if (dma_desc & 0xff)
c8d86be3
GKH		 1231 /*
1232 * descriptor's buffer must be 256 byte aligned
1233 * should never happen since we specify the DMA mask
1234 */
be286fd2 1235 WARN(1, "DMA buffer is not aligned\n");
c8d86be3
GKH		 1236
1237 priv->rxring=desc;
1238 priv->rxringdma=dma_desc;
1239 tmp=desc;
1240
fd882783 1241 for (i = 0; i < count; i++) {
c8d86be3
GKH		 1242 if ((buf= kmalloc(bufsize * sizeof(u8),GFP_ATOMIC)) == NULL){
1243 DMESGE("Failed to kmalloc RX buffer");
1244 return -1;
1245 }
1246
1247 dma_tmp = pci_map_single(pdev,buf,bufsize * sizeof(u8),
1248 PCI_DMA_FROMDEVICE);
1249
c8d86be3
GKH		 1250 if(-1 == buffer_add(&(priv->rxbuffer), buf,dma_tmp,
1251 &(priv->rxbufferhead))){
1252 DMESGE("Unable to allocate mem RX buf");
1253 return -1;
1254 }
1255 *tmp = 0; //zero pads the header of the descriptor
1256 *tmp = *tmp |( bufsize&0xfff);
1257 *(tmp+2) = (u32)dma_tmp;
1258 *tmp = *tmp |(1<<31); // descriptor void, owned by the NIC
1259
c8d86be3
GKH		 1260 tmp=tmp+rx_desc_size;
1261 }
1262
1263 *(tmp-rx_desc_size) = *(tmp-rx_desc_size) | (1<<30); // this is the last descriptor
1264
c8d86be3
GKH		 1265 return 0;
1266}
1267
1268
1269void set_nic_rxring(struct net_device *dev)
1270{
1271 u8 pgreg;
1272 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1273
c8d86be3
GKH		 1274 pgreg=read_nic_byte(dev, PGSELECT);
1275 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
1276
c8d86be3
GKH		 1277 write_nic_dword(dev, RXRING_ADDR,priv->rxringdma);
1278}
1279
c8d86be3
GKH		 1280void rtl8180_reset(struct net_device *dev)
1281{
c8d86be3
GKH		 1282 u8 cr;
1283
c8d86be3
GKH		 1284 rtl8180_irq_disable(dev);
1285
1286 cr=read_nic_byte(dev,CMD);
1287 cr = cr & 2;
1288 cr = cr | (1<<CMD_RST_SHIFT);
1289 write_nic_byte(dev,CMD,cr);
1290
1291 force_pci_posting(dev);
1292
1293 mdelay(200);
1294
1295 if(read_nic_byte(dev,CMD) & (1<<CMD_RST_SHIFT))
1296 DMESGW("Card reset timeout!");
1297 else
1298 DMESG("Card successfully reset");
1299
c8d86be3
GKH		 1300 rtl8180_set_mode(dev,EPROM_CMD_LOAD);
1301 force_pci_posting(dev);
1302 mdelay(200);
c8d86be3
GKH		 1303}
1304
1305inline u16 ieeerate2rtlrate(int rate)
1306{
1307 switch(rate){
1308 case 10:
fd882783 1309 return 0;
c8d86be3 1310 case 20:
fd882783 1311 return 1;
c8d86be3 1312 case 55:
fd882783 1313 return 2;
c8d86be3 1314 case 110:
fd882783 1315 return 3;
c8d86be3 1316 case 60:
fd882783 1317 return 4;
c8d86be3 1318 case 90:
fd882783 1319 return 5;
c8d86be3 1320 case 120:
fd882783 1321 return 6;
c8d86be3 1322 case 180:
fd882783 1323 return 7;
c8d86be3 1324 case 240:
fd882783 1325 return 8;
c8d86be3 1326 case 360:
fd882783 1327 return 9;
c8d86be3 1328 case 480:
fd882783 1329 return 10;
c8d86be3 1330 case 540:
fd882783 1331 return 11;
c8d86be3 1332 default:
fd882783 1333 return 3;
c8d86be3
GKH		 1334 }
1335}
1336
1337static u16 rtl_rate[] = {10,20,55,110,60,90,120,180,240,360,480,540,720};
fd882783 1338
c8d86be3
GKH		 1339inline u16 rtl8180_rate2rate(short rate)
1340{
fd882783
BZ		 1341 if (rate > 12)
1342 return 10;
c8d86be3
GKH		 1343 return rtl_rate[rate];
1344}
fd882783 1345
c8d86be3
GKH		 1346inline u8 rtl8180_IsWirelessBMode(u16 rate)
1347{
1348 if( ((rate <= 110) && (rate != 60) && (rate != 90)) || (rate == 220) )
1349 return 1;
fd882783
BZ		 1350 else
1351 return 0;
c8d86be3 1352}
fd882783 1353
c8d86be3 1354u16 N_DBPSOfRate(u16 DataRate);
fd882783
BZ		 1355
1356u16 ComputeTxTime(u16 FrameLength, u16 DataRate, u8 bManagementFrame,
1357 u8 bShortPreamble)
c8d86be3
GKH		 1358{
1359 u16 FrameTime;
1360 u16 N_DBPS;
1361 u16 Ceiling;
1362
fd882783
BZ		 1363 if (rtl8180_IsWirelessBMode(DataRate)) {
1364 if (bManagementFrame || !bShortPreamble || DataRate == 10)
1365 /* long preamble */
c8d86be3 1366 FrameTime = (u16)(144+48+(FrameLength*8/(DataRate/10)));
c8d86be3 1367 else
fd882783 1368 /* short preamble */
c8d86be3 1369 FrameTime = (u16)(72+24+(FrameLength*8/(DataRate/10)));
fd882783
BZ		 1370
1371 if ((FrameLength*8 % (DataRate/10)) != 0) /* get the ceilling */
1372 FrameTime++;
1373 } else { /* 802.11g DSSS-OFDM PLCP length field calculation. */
c8d86be3
GKH		 1374 N_DBPS = N_DBPSOfRate(DataRate);
1375 Ceiling = (16 + 8*FrameLength + 6) / N_DBPS
1376 + (((16 + 8*FrameLength + 6) % N_DBPS) ? 1 : 0);
1377 FrameTime = (u16)(16 + 4 + 4*Ceiling + 6);
1378 }
1379 return FrameTime;
1380}
fd882783 1381
c8d86be3
GKH		 1382u16 N_DBPSOfRate(u16 DataRate)
1383{
1384 u16 N_DBPS = 24;
1385
fd882783
BZ		 1386 switch (DataRate) {
1387 case 60:
1388 N_DBPS = 24;
1389 break;
1390 case 90:
1391 N_DBPS = 36;
1392 break;
1393 case 120:
1394 N_DBPS = 48;
1395 break;
1396 case 180:
1397 N_DBPS = 72;
1398 break;
1399 case 240:
1400 N_DBPS = 96;
1401 break;
1402 case 360:
1403 N_DBPS = 144;
1404 break;
1405 case 480:
1406 N_DBPS = 192;
1407 break;
1408 case 540:
1409 N_DBPS = 216;
1410 break;
1411 default:
1412 break;
1413 }
c8d86be3 1414
fd882783 1415 return N_DBPS;
c8d86be3
GKH		 1416}
1417
c8d86be3
GKH		 1418//
1419// Description:
1420// For Netgear case, they want good-looking singal strength.
c8d86be3 1421//
fd882783 1422long NetgearSignalStrengthTranslate(long LastSS, long CurrSS)
c8d86be3
GKH		 1423{
1424 long RetSS;
1425
1426 // Step 1. Scale mapping.
fd882783 1427 if (CurrSS >= 71 && CurrSS <= 100)
c8d86be3 1428 RetSS = 90 + ((CurrSS - 70) / 3);
fd882783 1429 else if (CurrSS >= 41 && CurrSS <= 70)
c8d86be3 1430 RetSS = 78 + ((CurrSS - 40) / 3);
fd882783 1431 else if (CurrSS >= 31 && CurrSS <= 40)
c8d86be3 1432 RetSS = 66 + (CurrSS - 30);
fd882783 1433 else if (CurrSS >= 21 && CurrSS <= 30)
c8d86be3 1434 RetSS = 54 + (CurrSS - 20);
fd882783 1435 else if (CurrSS >= 5 && CurrSS <= 20)
c8d86be3 1436 RetSS = 42 + (((CurrSS - 5) * 2) / 3);
fd882783 1437 else if (CurrSS == 4)
c8d86be3 1438 RetSS = 36;
fd882783 1439 else if (CurrSS == 3)
c8d86be3 1440 RetSS = 27;
fd882783 1441 else if (CurrSS == 2)
c8d86be3 1442 RetSS = 18;
fd882783 1443 else if (CurrSS == 1)
c8d86be3 1444 RetSS = 9;
c8d86be3 1445 else
c8d86be3 1446 RetSS = CurrSS;
c8d86be3
GKH		 1447
1448 // Step 2. Smoothing.
1449 if(LastSS > 0)
c8d86be3 1450 RetSS = ((LastSS * 5) + (RetSS)+ 5) / 6;
c8d86be3
GKH		 1451
1452 return RetSS;
1453}
fd882783 1454
c8d86be3
GKH		 1455//
1456// Description:
1457// Translate 0-100 signal strength index into dBm.
1458//
fd882783 1459long TranslateToDbm8185(u8 SignalStrengthIndex)
c8d86be3 1460{
fd882783 1461 long SignalPower;
c8d86be3
GKH		 1462
1463 // Translate to dBm (x=0.5y-95).
1464 SignalPower = (long)((SignalStrengthIndex + 1) >> 1);
1465 SignalPower -= 95;
1466
1467 return SignalPower;
1468}
fd882783 1469
c8d86be3
GKH		 1470//
1471// Description:
1472// Perform signal smoothing for dynamic mechanism.
1473// This is different with PerformSignalSmoothing8185 in smoothing fomula.
1474// No dramatic adjustion is apply because dynamic mechanism need some degree
1475// of correctness. Ported from 8187B.
c8d86be3 1476//
fd882783
BZ		 1477void PerformUndecoratedSignalSmoothing8185(struct r8180_priv *priv,
1478 bool bCckRate)
c8d86be3 1479{
c8d86be3
GKH		 1480 // Determin the current packet is CCK rate.
1481 priv->bCurCCKPkt = bCckRate;
1482
fd882783 1483 if (priv->UndecoratedSmoothedSS >= 0)
c8d86be3 1484 priv->UndecoratedSmoothedSS = ( (priv->UndecoratedSmoothedSS * 5) + (priv->SignalStrength * 10) ) / 6;
c8d86be3 1485 else
c8d86be3 1486 priv->UndecoratedSmoothedSS = priv->SignalStrength * 10;
c8d86be3
GKH		 1487
1488 priv->UndercorateSmoothedRxPower = ( (priv->UndercorateSmoothedRxPower * 50) + (priv->RxPower* 11)) / 60;
1489
fd882783 1490 if (bCckRate)
c8d86be3 1491 priv->CurCCKRSSI = priv->RSSI;
c8d86be3 1492 else
c8d86be3 1493 priv->CurCCKRSSI = 0;
c8d86be3
GKH		 1494}
1495
c8d86be3
GKH		 1496
1497/* This is rough RX isr handling routine*/
1498void rtl8180_rx(struct net_device *dev)
1499{
1500 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1501 struct sk_buff *tmp_skb;
c8d86be3
GKH		 1502 short first,last;
1503 u32 len;
1504 int lastlen;
1505 unsigned char quality, signal;
1506 u8 rate;
c8d86be3
GKH		 1507 u32 *tmp,*tmp2;
1508 u8 rx_desc_size;
1509 u8 padding;
c8d86be3
GKH		 1510 char rxpower = 0;
1511 u32 RXAGC = 0;
1512 long RxAGC_dBm = 0;
1513 u8 LNA=0, BB=0;
1514 u8 LNA_gain[4]={02, 17, 29, 39};
1515 u8 Antenna = 0;
0604384d 1516 struct ieee80211_hdr_4addr *hdr;
c8d86be3
GKH		 1517 u16 fc,type;
1518 u8 bHwError = 0,bCRC = 0,bICV = 0;
c8d86be3
GKH		 1519 bool bCckRate = false;
1520 u8 RSSI = 0;
fd882783 1521 long SignalStrengthIndex = 0;
c8d86be3
GKH		 1522 struct ieee80211_rx_stats stats = {
1523 .signal = 0,
1524 .noise = -98,
1525 .rate = 0,
c8d86be3
GKH		 1526 .freq = IEEE80211_24GHZ_BAND,
1527 };
1528
c8d86be3
GKH		 1529 stats.nic_type = NIC_8185B;
1530 rx_desc_size = 8;
1531
c8d86be3 1532 if ((*(priv->rxringtail)) & (1<<31)) {
c8d86be3
GKH		 1533 /* we have got an RX int, but the descriptor
1534 * we are pointing is empty*/
1535
1536 priv->stats.rxnodata++;
1537 priv->ieee80211->stats.rx_errors++;
1538
c8d86be3
GKH		 1539 tmp2 = NULL;
1540 tmp = priv->rxringtail;
1541 do{
1542 if(tmp == priv->rxring)
c8d86be3
GKH		 1543 tmp = priv->rxring + (priv->rxringcount - 1)*rx_desc_size;
1544 else
1545 tmp -= rx_desc_size;
1546
1547 if(! (*tmp & (1<<31)))
1548 tmp2 = tmp;
1549 }while(tmp != priv->rxring);
1550
1551 if(tmp2) priv->rxringtail = tmp2;
c8d86be3
GKH		 1552 }
1553
1554 /* while there are filled descriptors */
1555 while(!(*(priv->rxringtail) & (1<<31))){
1556 if(*(priv->rxringtail) & (1<<26))
1557 DMESGW("RX buffer overflow");
1558 if(*(priv->rxringtail) & (1<<12))
1559 priv->stats.rxicverr++;
1560
1561 if(*(priv->rxringtail) & (1<<27)){
1562 priv->stats.rxdmafail++;
1563 //DMESG("EE: RX DMA FAILED at buffer pointed by descriptor %x",(u32)priv->rxringtail);
1564 goto drop;
1565 }
1566
1567 pci_dma_sync_single_for_cpu(priv->pdev,
1568 priv->rxbuffer->dma,
1569 priv->rxbuffersize * \
1570 sizeof(u8),
1571 PCI_DMA_FROMDEVICE);
1572
1573 first = *(priv->rxringtail) & (1<<29) ? 1:0;
1574 if(first) priv->rx_prevlen=0;
1575
1576 last = *(priv->rxringtail) & (1<<28) ? 1:0;
1577 if(last){
1578 lastlen=((*priv->rxringtail) &0xfff);
1579
1580 /* if the last descriptor (that should
1581 * tell us the total packet len) tell
1582 * us something less than the descriptors
1583 * len we had until now, then there is some
1584 * problem..
1585 * workaround to prevent kernel panic
1586 */
1587 if(lastlen < priv->rx_prevlen)
1588 len=0;
1589 else
1590 len=lastlen-priv->rx_prevlen;
1591
1592 if(*(priv->rxringtail) & (1<<13)) {
c8d86be3
GKH		 1593 if ((*(priv->rxringtail) & 0xfff) <500)
1594 priv->stats.rxcrcerrmin++;
1595 else if ((*(priv->rxringtail) & 0x0fff) >1000)
1596 priv->stats.rxcrcerrmax++;
1597 else
1598 priv->stats.rxcrcerrmid++;
1599
1600 }
1601
1602 }else{
1603 len = priv->rxbuffersize;
1604 }
1605
c8d86be3
GKH		 1606 if(first && last) {
1607 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1608 }else if(first) {
1609 padding = ((*(priv->rxringtail+3))&(0x04000000))>>26;
1610 if(padding) {
1611 len -= 2;
1612 }
1613 }else {
1614 padding = 0;
1615 }
c8d86be3 1616 padding = 0;
c8d86be3
GKH		 1617 priv->rx_prevlen+=len;
1618
1619 if(priv->rx_prevlen > MAX_FRAG_THRESHOLD + 100){
1620 /* HW is probably passing several buggy frames
1621 * without FD or LD flag set.
1622 * Throw this garbage away to prevent skb
1623 * memory exausting
1624 */
1625 if(!priv->rx_skb_complete)
1626 dev_kfree_skb_any(priv->rx_skb);
1627 priv->rx_skb_complete = 1;
1628 }
1629
c8d86be3 1630 signal=(unsigned char)(((*(priv->rxringtail+3))& (0x00ff0000))>>16);
1994130e 1631 signal = (signal & 0xfe) >> 1;
c8d86be3
GKH		 1632
1633 quality=(unsigned char)((*(priv->rxringtail+3)) & (0xff));
1634
1635 stats.mac_time[0] = *(priv->rxringtail+1);
1636 stats.mac_time[1] = *(priv->rxringtail+2);
1637 rxpower =((char)(((*(priv->rxringtail+4))& (0x00ff0000))>>16))/2 - 42;
1638 RSSI = ((u8)(((*(priv->rxringtail+3)) & (0x0000ff00))>> 8)) & (0x7f);
1639
c8d86be3
GKH		 1640 rate=((*(priv->rxringtail)) &
1641 ((1<<23)|(1<<22)|(1<<21)|(1<<20)))>>20;
1642
1643 stats.rate = rtl8180_rate2rate(rate);
c8d86be3 1644 Antenna = (((*(priv->rxringtail +3))& (0x00008000)) == 0 )? 0:1 ;
c8d86be3
GKH		 1645 if(!rtl8180_IsWirelessBMode(stats.rate))
1646 { // OFDM rate.
1647
1648 RxAGC_dBm = rxpower+1; //bias
1649 }
1650 else
1651 { // CCK rate.
1652 RxAGC_dBm = signal;//bit 0 discard
1653
1654 LNA = (u8) (RxAGC_dBm & 0x60 ) >> 5 ; //bit 6~ bit 5
1655 BB = (u8) (RxAGC_dBm & 0x1F); // bit 4 ~ bit 0
1656
1657 RxAGC_dBm = -( LNA_gain[LNA] + (BB *2) ); //Pin_11b=-(LNA_gain+BB_gain) (dBm)
1658
1659 RxAGC_dBm +=4; //bias
1660 }
1661
1662 if(RxAGC_dBm & 0x80) //absolute value
1663 RXAGC= ~(RxAGC_dBm)+1;
1664 bCckRate = rtl8180_IsWirelessBMode(stats.rate);
1665 // Translate RXAGC into 1-100.
1666 if(!rtl8180_IsWirelessBMode(stats.rate))
1667 { // OFDM rate.
1668 if(RXAGC>90)
1669 RXAGC=90;
1670 else if(RXAGC<25)
1671 RXAGC=25;
1672 RXAGC=(90-RXAGC)*100/65;
1673 }
1674 else
1675 { // CCK rate.
1676 if(RXAGC>95)
1677 RXAGC=95;
1678 else if(RXAGC<30)
1679 RXAGC=30;
1680 RXAGC=(95-RXAGC)*100/65;
1681 }
1682 priv->SignalStrength = (u8)RXAGC;
1994130e 1683 priv->RecvSignalPower = RxAGC_dBm;
c8d86be3
GKH		 1684 priv->RxPower = rxpower;
1685 priv->RSSI = RSSI;
1994130e 1686 /* SQ translation formula is provided by SD3 DZ. 2006.06.27 */
c8d86be3
GKH		 1687 if(quality >= 127)
1688 quality = 1;//0; //0 will cause epc to show signal zero , walk aroud now;
1689 else if(quality < 27)
1690 quality = 100;
1691 else
1692 quality = 127 - quality;
1693 priv->SignalQuality = quality;
c8d86be3
GKH		 1694
1695 stats.signal = (u8)quality;//priv->wstats.qual.level = priv->SignalStrength;
1696 stats.signalstrength = RXAGC;
1697 if(stats.signalstrength > 100)
1698 stats.signalstrength = 100;
1699 stats.signalstrength = (stats.signalstrength * 70)/100 + 30;
1700 // printk("==========================>rx : RXAGC is %d,signalstrength is %d\n",RXAGC,stats.signalstrength);
1701 stats.rssi = priv->wstats.qual.qual = priv->SignalQuality;
1702 stats.noise = priv->wstats.qual.noise = 100 - priv ->wstats.qual.qual;
c8d86be3
GKH		 1703 bHwError = (((*(priv->rxringtail))& (0x00000fff)) == 4080)| (((*(priv->rxringtail))& (0x04000000)) != 0 )
1704 | (((*(priv->rxringtail))& (0x08000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x10000000)) != 0 )| (((~(*(priv->rxringtail)))& (0x20000000)) != 0 );
1705 bCRC = ((*(priv->rxringtail)) & (0x00002000)) >> 13;
1706 bICV = ((*(priv->rxringtail)) & (0x00001000)) >> 12;
0604384d 1707 hdr = (struct ieee80211_hdr_4addr *)priv->rxbuffer->buf;
c8d86be3
GKH		 1708 fc = le16_to_cpu(hdr->frame_ctl);
1709 type = WLAN_FC_GET_TYPE(fc);
1710
1711 if((IEEE80211_FTYPE_CTL != type) &&
1712 (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS)? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS )? hdr->addr2 : hdr->addr3))
1713 && (!bHwError) && (!bCRC)&& (!bICV))
1714 {
1994130e
LF		 1715 /* Perform signal smoothing for dynamic
1716 * mechanism on demand. This is different
1717 * with PerformSignalSmoothing8185 in smoothing
1718 * fomula. No dramatic adjustion is apply
1719 * because dynamic mechanism need some degree
1720 * of correctness. */
c8d86be3
GKH		 1721 PerformUndecoratedSignalSmoothing8185(priv,bCckRate);
1722 //
1723 // For good-looking singal strength.
1724 //
1725 SignalStrengthIndex = NetgearSignalStrengthTranslate(
1726 priv->LastSignalStrengthInPercent,
1727 priv->SignalStrength);
1728
1729 priv->LastSignalStrengthInPercent = SignalStrengthIndex;
1730 priv->Stats_SignalStrength = TranslateToDbm8185((u8)SignalStrengthIndex);
1731 //
1732 // We need more correct power of received packets and the "SignalStrength" of RxStats is beautified,
1733 // so we record the correct power here.
1734 //
1735 priv->Stats_SignalQuality =(long) (priv->Stats_SignalQuality * 5 + (long)priv->SignalQuality + 5) / 6;
1736 priv->Stats_RecvSignalPower = (long)(priv->Stats_RecvSignalPower * 5 + priv->RecvSignalPower -1) / 6;
1737
1738 // Figure out which antenna that received the lasted packet.
1739 priv->LastRxPktAntenna = Antenna ? 1 : 0; // 0: aux, 1: main.
c8d86be3
GKH		 1740 SwAntennaDiversityRxOk8185(dev, priv->SignalStrength);
1741 }
1742
c8d86be3
GKH		 1743 if(first){
1744 if(!priv->rx_skb_complete){
1745 /* seems that HW sometimes fails to reiceve and
1746 doesn't provide the last descriptor */
c8d86be3
GKH		 1747 dev_kfree_skb_any(priv->rx_skb);
1748 priv->stats.rxnolast++;
c8d86be3
GKH		 1749 }
1750 /* support for prism header has been originally added by Christian */
1751 if(priv->prism_hdr && priv->ieee80211->iw_mode == IW_MODE_MONITOR){
1752
c8d86be3
GKH		 1753 }else{
1754 priv->rx_skb = dev_alloc_skb(len+2);
1755 if( !priv->rx_skb) goto drop;
c8d86be3
GKH		 1756 }
1757
1758 priv->rx_skb_complete=0;
1759 priv->rx_skb->dev=dev;
1760 }else{
1761 /* if we are here we should have already RXed
1762 * the first frame.
1763 * If we get here and the skb is not allocated then
1764 * we have just throw out garbage (skb not allocated)
1765 * and we are still rxing garbage....
1766 */
1767 if(!priv->rx_skb_complete){
1768
1769 tmp_skb= dev_alloc_skb(priv->rx_skb->len +len+2);
1770
1771 if(!tmp_skb) goto drop;
1772
1773 tmp_skb->dev=dev;
c8d86be3 1774
c8d86be3
GKH		 1775 memcpy(skb_put(tmp_skb,priv->rx_skb->len),
1776 priv->rx_skb->data,
1777 priv->rx_skb->len);
c8d86be3
GKH		 1778
1779 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH		 1780
1781 priv->rx_skb=tmp_skb;
1782 }
1783 }
ff954853 1784
c8d86be3 1785 if(!priv->rx_skb_complete) {
c8d86be3
GKH		 1786 if(padding) {
1787 memcpy(skb_put(priv->rx_skb,len),
1788 (((unsigned char *)priv->rxbuffer->buf) + 2),len);
1789 } else {
c8d86be3
GKH		 1790 memcpy(skb_put(priv->rx_skb,len),
1791 priv->rxbuffer->buf,len);
c8d86be3 1792 }
c8d86be3 1793 }
c8d86be3
GKH		 1794
1795 if(last && !priv->rx_skb_complete){
c8d86be3
GKH		 1796 if(priv->rx_skb->len > 4)
1797 skb_trim(priv->rx_skb,priv->rx_skb->len-4);
df574b8e 1798 if(!ieee80211_rtl_rx(priv->ieee80211,
1994130e 1799 priv->rx_skb, &stats))
c8d86be3 1800 dev_kfree_skb_any(priv->rx_skb);
c8d86be3
GKH		 1801 priv->rx_skb_complete=1;
1802 }
1803
c8d86be3
GKH		 1804 pci_dma_sync_single_for_device(priv->pdev,
1805 priv->rxbuffer->dma,
1806 priv->rxbuffersize * \
1807 sizeof(u8),
1808 PCI_DMA_FROMDEVICE);
1809
bbc9a991 1810drop: // this is used when we have not enough mem
c8d86be3
GKH		 1811 /* restore the descriptor */
1812 *(priv->rxringtail+2)=priv->rxbuffer->dma;
1813 *(priv->rxringtail)=*(priv->rxringtail) &~ 0xfff;
1814 *(priv->rxringtail)=
1815 *(priv->rxringtail) | priv->rxbuffersize;
1816
1817 *(priv->rxringtail)=
1818 *(priv->rxringtail) | (1<<31);
c8d86be3
GKH		 1819
1820 priv->rxringtail+=rx_desc_size;
1821 if(priv->rxringtail >=
1822 (priv->rxring)+(priv->rxringcount )*rx_desc_size)
1823 priv->rxringtail=priv->rxring;
1824
c8d86be3 1825 priv->rxbuffer=(priv->rxbuffer->next);
c8d86be3 1826 }
c8d86be3
GKH		 1827}
1828
1829
1830void rtl8180_dma_kick(struct net_device *dev, int priority)
1831{
1832 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1833
1834 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1835 write_nic_byte(dev, TX_DMA_POLLING,
1836 (1 << (priority + 1)) | priv->dma_poll_mask);
1837 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1838
1839 force_pci_posting(dev);
1840}
1841
c8d86be3
GKH		 1842void rtl8180_data_hard_stop(struct net_device *dev)
1843{
1844 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1845
1846 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1847 priv->dma_poll_stop_mask |= TPPOLLSTOP_AC_VIQ;
1848 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1849 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1850}
1851
c8d86be3
GKH		 1852void rtl8180_data_hard_resume(struct net_device *dev)
1853{
1854 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1855
1856 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
c8d86be3
GKH		 1857 priv->dma_poll_stop_mask &= ~(TPPOLLSTOP_AC_VIQ);
1858 write_nic_byte(dev,TPPollStop, priv->dma_poll_stop_mask);
c8d86be3
GKH		 1859 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
1860}
1861
c8d86be3
GKH		 1862/* this function TX data frames when the ieee80211 stack requires this.
1863 * It checks also if we need to stop the ieee tx queue, eventually do it
1864 */
1865void rtl8180_hard_data_xmit(struct sk_buff *skb,struct net_device *dev, int
1866rate)
1867{
1868 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1869 int mode;
1870 struct ieee80211_hdr_3addr *h = (struct ieee80211_hdr_3addr *) skb->data;
1871 short morefrag = (h->frame_ctl) & IEEE80211_FCTL_MOREFRAGS;
1872 unsigned long flags;
1873 int priority;
c8d86be3
GKH		 1874
1875 mode = priv->ieee80211->iw_mode;
1876
1877 rate = ieeerate2rtlrate(rate);
1878 /*
1879 * This function doesn't require lock because we make
1880 * sure it's called with the tx_lock already acquired.
bbc9a991
AGR		 1881 * this come from the kernel's hard_xmit callback (through
1882 * the ieee stack, or from the try_wake_queue (again through
c8d86be3
GKH		 1883 * the ieee stack.
1884 */
c8d86be3 1885 priority = AC2Q(skb->priority);
c8d86be3
GKH		 1886 spin_lock_irqsave(&priv->tx_lock,flags);
1887
1888 if(priv->ieee80211->bHwRadioOff)
1889 {
1890 spin_unlock_irqrestore(&priv->tx_lock,flags);
1891
1892 return;
1893 }
1894
c8d86be3 1895 if (!check_nic_enought_desc(dev, priority)){
c8d86be3
GKH		 1896 DMESGW("Error: no descriptor left by previous TX (avail %d) ",
1897 get_curr_tx_free_desc(dev, priority));
df574b8e 1898 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3
GKH		 1899 }
1900 rtl8180_tx(dev, skb->data, skb->len, priority, morefrag,0,rate);
1901 if (!check_nic_enought_desc(dev, priority))
df574b8e 1902 ieee80211_rtl_stop_queue(priv->ieee80211);
c8d86be3 1903
c8d86be3 1904 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3
GKH		 1905}
1906
1907/* This is a rough attempt to TX a frame
1908 * This is called by the ieee 80211 stack to TX management frames.
1909 * If the ring is full packet are dropped (for data frame the queue
1910 * is stopped before this can happen). For this reason it is better
1911 * if the descriptors are larger than the largest management frame
1912 * we intend to TX: i'm unsure what the HW does if it will not found
1913 * the last fragment of a frame because it has been dropped...
1914 * Since queues for Management and Data frames are different we
1915 * might use a different lock than tx_lock (for example mgmt_tx_lock)
1916 */
1917/* these function may loops if invoked with 0 descriptors or 0 len buffer*/
1918int rtl8180_hard_start_xmit(struct sk_buff *skb,struct net_device *dev)
1919{
1920 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3 1921 unsigned long flags;
c8d86be3
GKH		 1922 int priority;
1923
c8d86be3 1924 priority = MANAGE_PRIORITY;
c8d86be3
GKH		 1925
1926 spin_lock_irqsave(&priv->tx_lock,flags);
1927
fd882783 1928 if (priv->ieee80211->bHwRadioOff) {
c8d86be3 1929 spin_unlock_irqrestore(&priv->tx_lock,flags);
c8d86be3 1930 dev_kfree_skb_any(skb);
ec634fe3 1931 return NETDEV_TX_OK;
c8d86be3
GKH		 1932 }
1933
1934 rtl8180_tx(dev, skb->data, skb->len, priority,
1935 0, 0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
1936
1937 priv->ieee80211->stats.tx_bytes+=skb->len;
1938 priv->ieee80211->stats.tx_packets++;
1939 spin_unlock_irqrestore(&priv->tx_lock,flags);
1940
1941 dev_kfree_skb_any(skb);
ec634fe3 1942 return NETDEV_TX_OK;
c8d86be3
GKH		 1943}
1944
1945// longpre 144+48 shortpre 72+24
1946u16 rtl8180_len2duration(u32 len, short rate,short* ext)
1947{
1948 u16 duration;
1949 u16 drift;
1950 *ext=0;
1951
1952 switch(rate){
1953 case 0://1mbps
1954 *ext=0;
1955 duration = ((len+4)<<4) /0x2;
1956 drift = ((len+4)<<4) % 0x2;
1957 if(drift ==0 ) break;
1958 duration++;
1959 break;
c8d86be3
GKH		 1960 case 1://2mbps
1961 *ext=0;
1962 duration = ((len+4)<<4) /0x4;
1963 drift = ((len+4)<<4) % 0x4;
1964 if(drift ==0 ) break;
1965 duration++;
1966 break;
c8d86be3
GKH		 1967 case 2: //5.5mbps
1968 *ext=0;
1969 duration = ((len+4)<<4) /0xb;
1970 drift = ((len+4)<<4) % 0xb;
1971 if(drift ==0 )
1972 break;
1973 duration++;
1974 break;
c8d86be3
GKH		 1975 default:
1976 case 3://11mbps
1977 *ext=0;
1978 duration = ((len+4)<<4) /0x16;
1979 drift = ((len+4)<<4) % 0x16;
1980 if(drift ==0 )
1981 break;
1982 duration++;
1983 if(drift > 6)
1984 break;
1985 *ext=1;
1986 break;
1987 }
1988
1989 return duration;
1990}
1991
c8d86be3
GKH		 1992void rtl8180_prepare_beacon(struct net_device *dev)
1993{
c8d86be3 1994 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 1995 struct sk_buff *skb;
1996
1997 u16 word = read_nic_word(dev, BcnItv);
1998 word &= ~BcnItv_BcnItv; // clear Bcn_Itv
1999 word |= cpu_to_le16(priv->ieee80211->current_network.beacon_interval);//0x64;
2000 write_nic_word(dev, BcnItv, word);
2001
c8d86be3
GKH		 2002 skb = ieee80211_get_beacon(priv->ieee80211);
2003 if(skb){
2004 rtl8180_tx(dev,skb->data,skb->len,BEACON_PRIORITY,
2005 0,0,ieeerate2rtlrate(priv->ieee80211->basic_rate));
2006 dev_kfree_skb_any(skb);
2007 }
c8d86be3
GKH		 2008}
2009
2010/* This function do the real dirty work: it enqueues a TX command
2011 * descriptor in the ring buffer, copyes the frame in a TX buffer
2012 * and kicks the NIC to ensure it does the DMA transfer.
2013 */
2014short rtl8180_tx(struct net_device *dev, u8* txbuf, int len, int priority,
2015 short morefrag, short descfrag, int rate)
2016{
2017 struct r8180_priv *priv = ieee80211_priv(dev);
2018 u32 *tail,*temp_tail;
2019 u32 *begin;
2020 u32 *buf;
2021 int i;
2022 int remain;
2023 int buflen;
2024 int count;
c8d86be3
GKH		 2025 u16 duration;
2026 short ext;
2027 struct buffer* buflist;
c8d86be3
GKH		 2028 struct ieee80211_hdr_3addr *frag_hdr = (struct ieee80211_hdr_3addr *)txbuf;
2029 u8 dest[ETH_ALEN];
2030 u8 bUseShortPreamble = 0;
2031 u8 bCTSEnable = 0;
2032 u8 bRTSEnable = 0;
c8d86be3
GKH		 2033 u16 Duration = 0;
2034 u16 RtsDur = 0;
2035 u16 ThisFrameTime = 0;
2036 u16 TxDescDuration = 0;
1994130e 2037 u8 ownbit_flag = false;
c8d86be3
GKH		 2038
2039 switch(priority) {
2040 case MANAGE_PRIORITY:
2041 tail=priv->txmapringtail;
2042 begin=priv->txmapring;
2043 buflist = priv->txmapbufstail;
2044 count = priv->txringcount;
2045 break;
c8d86be3
GKH		 2046 case BK_PRIORITY:
2047 tail=priv->txbkpringtail;
2048 begin=priv->txbkpring;
2049 buflist = priv->txbkpbufstail;
2050 count = priv->txringcount;
2051 break;
c8d86be3
GKH		 2052 case BE_PRIORITY:
2053 tail=priv->txbepringtail;
2054 begin=priv->txbepring;
2055 buflist = priv->txbepbufstail;
2056 count = priv->txringcount;
2057 break;
c8d86be3
GKH		 2058 case VI_PRIORITY:
2059 tail=priv->txvipringtail;
2060 begin=priv->txvipring;
2061 buflist = priv->txvipbufstail;
2062 count = priv->txringcount;
2063 break;
c8d86be3
GKH		 2064 case VO_PRIORITY:
2065 tail=priv->txvopringtail;
2066 begin=priv->txvopring;
2067 buflist = priv->txvopbufstail;
2068 count = priv->txringcount;
2069 break;
c8d86be3
GKH		 2070 case HI_PRIORITY:
2071 tail=priv->txhpringtail;
2072 begin=priv->txhpring;
2073 buflist = priv->txhpbufstail;
2074 count = priv->txringcount;
2075 break;
c8d86be3
GKH		 2076 case BEACON_PRIORITY:
2077 tail=priv->txbeaconringtail;
2078 begin=priv->txbeaconring;
2079 buflist = priv->txbeaconbufstail;
2080 count = priv->txbeaconcount;
2081 break;
c8d86be3
GKH		 2082 default:
2083 return -1;
2084 break;
2085 }
2086
c8d86be3
GKH		 2087 memcpy(&dest, frag_hdr->addr1, ETH_ALEN);
2088 if (is_multicast_ether_addr(dest) ||
2089 is_broadcast_ether_addr(dest))
2090 {
2091 Duration = 0;
2092 RtsDur = 0;
2093 bRTSEnable = 0;
2094 bCTSEnable = 0;
2095
2096 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2097 TxDescDuration = ThisFrameTime;
2098 } else {// Unicast packet
c8d86be3
GKH		 2099 u16 AckTime;
2100
2101 //YJ,add,080828,for Keep alive
2102 priv->NumTxUnicast++;
2103
1994130e
LF		 2104 /* Figure out ACK rate according to BSS basic rate
2105 * and Tx rate. */
c8d86be3 2106 AckTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
c8d86be3
GKH		 2107
2108 if ( ((len + sCrcLng) > priv->rts) && priv->rts )
2109 { // RTS/CTS.
2110 u16 RtsTime, CtsTime;
2111 //u16 CtsRate;
2112 bRTSEnable = 1;
2113 bCTSEnable = 0;
2114
2115 // Rate and time required for RTS.
2116 RtsTime = ComputeTxTime( sAckCtsLng/8,priv->ieee80211->basic_rate, 0, 0);
2117 // Rate and time required for CTS.
2118 CtsTime = ComputeTxTime(14, 10,0, 0); // AckCTSLng = 14 use 1M bps send
2119
2120 // Figure out time required to transmit this frame.
2121 ThisFrameTime = ComputeTxTime(len + sCrcLng,
2122 rtl8180_rate2rate(rate),
2123 0,
2124 bUseShortPreamble);
2125
2126 // RTS-CTS-ThisFrame-ACK.
2127 RtsDur = CtsTime + ThisFrameTime + AckTime + 3*aSifsTime;
2128
2129 TxDescDuration = RtsTime + RtsDur;
2130 }
2131 else {// Normal case.
2132 bCTSEnable = 0;
2133 bRTSEnable = 0;
2134 RtsDur = 0;
2135
2136 ThisFrameTime = ComputeTxTime(len + sCrcLng, rtl8180_rate2rate(rate), 0, bUseShortPreamble);
2137 TxDescDuration = ThisFrameTime + aSifsTime + AckTime;
2138 }
2139
2140 if(!(frag_hdr->frame_ctl & IEEE80211_FCTL_MOREFRAGS)) { //no more fragment
2141 // ThisFrame-ACK.
2142 Duration = aSifsTime + AckTime;
2143 } else { // One or more fragments remained.
2144 u16 NextFragTime;
2145 NextFragTime = ComputeTxTime( len + sCrcLng, //pretend following packet length equal current packet
2146 rtl8180_rate2rate(rate),
2147 0,
2148 bUseShortPreamble );
2149
2150 //ThisFrag-ACk-NextFrag-ACK.
2151 Duration = NextFragTime + 3*aSifsTime + 2*AckTime;
2152 }
2153
2154 } // End of Unicast packet
2155
2156 frag_hdr->duration_id = Duration;
c8d86be3
GKH		 2157
2158 buflen=priv->txbuffsize;
2159 remain=len;
2160 temp_tail = tail;
fd882783 2161
c8d86be3 2162 while(remain!=0){
c8d86be3
GKH		 2163 mb();
2164 if(!buflist){
2165 DMESGE("TX buffer error, cannot TX frames. pri %d.", priority);
c8d86be3
GKH		 2166 return -1;
2167 }
2168 buf=buflist->buf;
2169
fd882783
BZ		 2170 if ((*tail & (1 << 31)) && (priority != BEACON_PRIORITY)) {
2171 DMESGW("No more TX desc, returning %x of %x",
2172 remain, len);
2173 priv->stats.txrdu++;
c8d86be3 2174 return remain;
c8d86be3
GKH		 2175 }
2176
2177 *tail= 0; // zeroes header
2178 *(tail+1) = 0;
2179 *(tail+3) = 0;
2180 *(tail+5) = 0;
2181 *(tail+6) = 0;
2182 *(tail+7) = 0;
2183
d44eb889
LF		 2184 /*FIXME: this should be triggered by HW encryption parameters.*/
2185 *tail |= (1<<15); /* no encrypt */
fd882783 2186
c8d86be3 2187 if(remain==len && !descfrag) {
1994130e 2188 ownbit_flag = false;
c8d86be3
GKH		 2189 *tail = *tail| (1<<29) ; //fist segment of the packet
2190 *tail = *tail |(len);
2191 } else {
2192 ownbit_flag = true;
2193 }
2194
2195 for(i=0;i<buflen&& remain >0;i++,remain--){
2196 ((u8*)buf)[i]=txbuf[i]; //copy data into descriptor pointed DMAble buffer
2197 if(remain == 4 && i+4 >= buflen) break;
2198 /* ensure the last desc has at least 4 bytes payload */
2199
2200 }
2201 txbuf = txbuf + i;
2202 *(tail+3)=*(tail+3) &~ 0xfff;
2203 *(tail+3)=*(tail+3) | i; // buffer lenght
2204 // Use short preamble or not
2205 if (priv->ieee80211->current_network.capability&WLAN_CAPABILITY_SHORT_PREAMBLE)
2206 if (priv->plcp_preamble_mode==1 && rate!=0) // short mode now, not long!
b3184e1e 2207 ;// *tail |= (1<<16); // enable short preamble mode.
c8d86be3 2208
c8d86be3
GKH		 2209 if(bCTSEnable) {
2210 *tail |= (1<<18);
2211 }
2212
2213 if(bRTSEnable) //rts enable
2214 {
2215 *tail |= ((ieeerate2rtlrate(priv->ieee80211->basic_rate))<<19);//RTS RATE
2216 *tail |= (1<<23);//rts enable
2217 *(tail+1) |=(RtsDur&0xffff);//RTS Duration
2218 }
2219 *(tail+3) |= ((TxDescDuration&0xffff)<<16); //DURATION
2220// *(tail+3) |= (0xe6<<16);
2221 *(tail+5) |= (11<<8);//(priv->retry_data<<8); //retry lim ;
c8d86be3
GKH		 2222
2223 *tail = *tail | ((rate&0xf) << 24);
c8d86be3
GKH		 2224
2225 /* hw_plcp_len is not used for rtl8180 chip */
2226 /* FIXME */
d44eb889 2227 if (!priv->hw_plcp_len) {
fd882783 2228 duration = rtl8180_len2duration(len, rate, &ext);
c8d86be3
GKH		 2229 *(tail+1) = *(tail+1) | ((duration & 0x7fff)<<16);
2230 if(ext) *(tail+1) = *(tail+1) |(1<<31); //plcp length extension
2231 }
2232
2233 if(morefrag) *tail = (*tail) | (1<<17); // more fragment
2234 if(!remain) *tail = (*tail) | (1<<28); // last segment of frame
2235
c8d86be3
GKH		 2236 *(tail+5) = *(tail+5)|(2<<27);
2237 *(tail+7) = *(tail+7)|(1<<4);
2238
2239 wmb();
2240 if(ownbit_flag)
2241 {
2242 *tail = *tail | (1<<31); // descriptor ready to be txed
2243 }
2244
c8d86be3
GKH		 2245 if((tail - begin)/8 == count-1)
2246 tail=begin;
c8d86be3
GKH		 2247 else
2248 tail=tail+8;
2249
2250 buflist=buflist->next;
2251
2252 mb();
2253
2254 switch(priority) {
2255 case MANAGE_PRIORITY:
2256 priv->txmapringtail=tail;
2257 priv->txmapbufstail=buflist;
2258 break;
c8d86be3
GKH		 2259 case BK_PRIORITY:
2260 priv->txbkpringtail=tail;
2261 priv->txbkpbufstail=buflist;
2262 break;
c8d86be3
GKH		 2263 case BE_PRIORITY:
2264 priv->txbepringtail=tail;
2265 priv->txbepbufstail=buflist;
2266 break;
c8d86be3
GKH		 2267 case VI_PRIORITY:
2268 priv->txvipringtail=tail;
2269 priv->txvipbufstail=buflist;
2270 break;
c8d86be3
GKH		 2271 case VO_PRIORITY:
2272 priv->txvopringtail=tail;
2273 priv->txvopbufstail=buflist;
2274 break;
c8d86be3
GKH		 2275 case HI_PRIORITY:
2276 priv->txhpringtail=tail;
2277 priv->txhpbufstail = buflist;
2278 break;
c8d86be3
GKH		 2279 case BEACON_PRIORITY:
2280 /* the HW seems to be happy with the 1st
2281 * descriptor filled and the 2nd empty...
2282 * So always update descriptor 1 and never
2283 * touch 2nd
2284 */
c8d86be3 2285 break;
c8d86be3 2286 }
c8d86be3
GKH		 2287 }
2288 *temp_tail = *temp_tail | (1<<31); // descriptor ready to be txed
2289 rtl8180_dma_kick(dev,priority);
c8d86be3
GKH		 2290
2291 return 0;
c8d86be3
GKH		 2292}
2293
c8d86be3
GKH		 2294void rtl8180_irq_rx_tasklet(struct r8180_priv * priv);
2295
c8d86be3
GKH		 2296void rtl8180_link_change(struct net_device *dev)
2297{
2298 struct r8180_priv *priv = ieee80211_priv(dev);
2299 u16 beacon_interval;
c8d86be3 2300 struct ieee80211_network *net = &priv->ieee80211->current_network;
c8d86be3 2301
fd882783 2302 rtl8180_update_msr(dev);
c8d86be3
GKH		 2303
2304 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2305
2306 write_nic_dword(dev,BSSID,((u32*)net->bssid)[0]);
2307 write_nic_word(dev,BSSID+4,((u16*)net->bssid)[2]);
2308
c8d86be3
GKH		 2309 beacon_interval = read_nic_dword(dev,BEACON_INTERVAL);
2310 beacon_interval &= ~ BEACON_INTERVAL_MASK;
2311 beacon_interval |= net->beacon_interval;
2312 write_nic_dword(dev, BEACON_INTERVAL, beacon_interval);
2313
2314 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
2315
d44eb889 2316 rtl8180_set_chan(dev, priv->chan);
c8d86be3
GKH		 2317}
2318
2319void rtl8180_rq_tx_ack(struct net_device *dev){
2320
2321 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 2322
c8d86be3
GKH		 2323 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)|CONFIG4_PWRMGT);
2324 priv->ack_tx_to_ieee = 1;
2325}
2326
2327short rtl8180_is_tx_queue_empty(struct net_device *dev){
2328
2329 struct r8180_priv *priv = ieee80211_priv(dev);
2330 u32* d;
2331
2332 for (d = priv->txmapring;
2333 d < priv->txmapring + priv->txringcount;d+=8)
2334 if(*d & (1<<31)) return 0;
2335
2336 for (d = priv->txbkpring;
2337 d < priv->txbkpring + priv->txringcount;d+=8)
2338 if(*d & (1<<31)) return 0;
2339
2340 for (d = priv->txbepring;
2341 d < priv->txbepring + priv->txringcount;d+=8)
2342 if(*d & (1<<31)) return 0;
2343
2344 for (d = priv->txvipring;
2345 d < priv->txvipring + priv->txringcount;d+=8)
2346 if(*d & (1<<31)) return 0;
2347
2348 for (d = priv->txvopring;
2349 d < priv->txvopring + priv->txringcount;d+=8)
2350 if(*d & (1<<31)) return 0;
2351
2352 for (d = priv->txhpring;
2353 d < priv->txhpring + priv->txringcount;d+=8)
2354 if(*d & (1<<31)) return 0;
2355 return 1;
2356}
2357/* FIXME FIXME 5msecs is random */
2358#define HW_WAKE_DELAY 5
2359
2360void rtl8180_hw_wakeup(struct net_device *dev)
2361{
2362 unsigned long flags;
c8d86be3
GKH		 2363 struct r8180_priv *priv = ieee80211_priv(dev);
2364
2365 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3 2366 write_nic_byte(dev,CONFIG4,read_nic_byte(dev,CONFIG4)&~CONFIG4_PWRMGT);
fd882783 2367 if (priv->rf_wakeup)
c8d86be3 2368 priv->rf_wakeup(dev);
c8d86be3
GKH		 2369 spin_unlock_irqrestore(&priv->ps_lock,flags);
2370}
2371
2372void rtl8180_hw_sleep_down(struct net_device *dev)
2373{
2374 unsigned long flags;
c8d86be3
GKH		 2375 struct r8180_priv *priv = ieee80211_priv(dev);
2376
2377 spin_lock_irqsave(&priv->ps_lock,flags);
c8d86be3
GKH		 2378 if(priv->rf_sleep)
2379 priv->rf_sleep(dev);
2380 spin_unlock_irqrestore(&priv->ps_lock,flags);
2381}
2382
c8d86be3
GKH		 2383void rtl8180_hw_sleep(struct net_device *dev, u32 th, u32 tl)
2384{
c8d86be3 2385 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 2386 u32 rb = jiffies;
2387 unsigned long flags;
2388
2389 spin_lock_irqsave(&priv->ps_lock,flags);
2390
2391 /* Writing HW register with 0 equals to disable
2392 * the timer, that is not really what we want
2393 */
2394 tl -= MSECS(4+16+7);
2395
c8d86be3
GKH		 2396 /* If the interval in witch we are requested to sleep is too
2397 * short then give up and remain awake
2398 */
2399 if(((tl>=rb)&& (tl-rb) <= MSECS(MIN_SLEEP_TIME))
2400 ||((rb>tl)&& (rb-tl) < MSECS(MIN_SLEEP_TIME))) {
2401 spin_unlock_irqrestore(&priv->ps_lock,flags);
2402 printk("too short to sleep\n");
2403 return;
2404 }
2405
c8d86be3
GKH		 2406 {
2407 u32 tmp = (tl>rb)?(tl-rb):(rb-tl);
c8d86be3 2408
c8d86be3
GKH		 2409 priv->DozePeriodInPast2Sec += jiffies_to_msecs(tmp);
2410
2411 queue_delayed_work(priv->ieee80211->wq, &priv->ieee80211->hw_wakeup_wq, tmp); //as tl may be less than rb
2412 }
2413 /* if we suspect the TimerInt is gone beyond tl
2414 * while setting it, then give up
2415 */
fd882783 2416
c8d86be3
GKH		 2417 if(((tl > rb) && ((tl-rb) > MSECS(MAX_SLEEP_TIME)))||
2418 ((tl < rb) && ((rb-tl) > MSECS(MAX_SLEEP_TIME)))) {
2419 spin_unlock_irqrestore(&priv->ps_lock,flags);
2420 return;
2421 }
c8d86be3
GKH		 2422
2423 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_sleep_wq);
2424 spin_unlock_irqrestore(&priv->ps_lock,flags);
2425}
2426
c8d86be3
GKH		 2427void rtl8180_wmm_param_update(struct work_struct * work)
2428{
2429 struct ieee80211_device * ieee = container_of(work, struct ieee80211_device,wmm_param_update_wq);
c8d86be3 2430 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 2431 u8 *ac_param = (u8 *)(ieee->current_network.wmm_param);
2432 u8 mode = ieee->current_network.mode;
2433 AC_CODING eACI;
2434 AC_PARAM AcParam;
2435 PAC_PARAM pAcParam;
2436 u8 i;
2437
c8d86be3
GKH		 2438 if(!ieee->current_network.QoS_Enable){
2439 //legacy ac_xx_param update
2440 AcParam.longData = 0;
2441 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2442 AcParam.f.AciAifsn.f.ACM = 0;
2443 AcParam.f.Ecw.f.ECWmin = 3; // Follow 802.11 CWmin.
2444 AcParam.f.Ecw.f.ECWmax = 7; // Follow 802.11 CWmax.
2445 AcParam.f.TXOPLimit = 0;
2446 for(eACI = 0; eACI < AC_MAX; eACI++){
2447 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2448 {
2449 u8 u1bAIFS;
2450 u32 u4bAcParam;
2451 pAcParam = (PAC_PARAM)(&AcParam);
2452 // Retrive paramters to udpate.
2453 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN *(((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2454 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit))<<AC_PARAM_TXOP_LIMIT_OFFSET)|
2455 (((u32)(pAcParam->f.Ecw.f.ECWmax))<<AC_PARAM_ECW_MAX_OFFSET)|
2456 (((u32)(pAcParam->f.Ecw.f.ECWmin))<<AC_PARAM_ECW_MIN_OFFSET)|
2457 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2458 switch(eACI){
2459 case AC1_BK:
2460 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2461 break;
c8d86be3
GKH		 2462 case AC0_BE:
2463 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2464 break;
c8d86be3
GKH		 2465 case AC2_VI:
2466 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2467 break;
c8d86be3
GKH		 2468 case AC3_VO:
2469 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2470 break;
c8d86be3
GKH		 2471 default:
2472 printk(KERN_WARNING "SetHwReg8185():invalid ACI: %d!\n", eACI);
2473 break;
2474 }
2475 }
2476 }
2477 return;
2478 }
2479
2480 for(i = 0; i < AC_MAX; i++){
2481 //AcParam.longData = 0;
2482 pAcParam = (AC_PARAM * )ac_param;
2483 {
2484 AC_CODING eACI;
2485 u8 u1bAIFS;
2486 u32 u4bAcParam;
2487
2488 // Retrive paramters to udpate.
2489 eACI = pAcParam->f.AciAifsn.f.ACI;
2490 //Mode G/A: slotTimeTimer = 9; Mode B: 20
2491 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * (((mode&IEEE_G) == IEEE_G)?9:20) + aSifsTime;
2492 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2493 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2494 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2495 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2496
2497 switch(eACI){
2498 case AC1_BK:
2499 write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2500 break;
c8d86be3
GKH		 2501 case AC0_BE:
2502 write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2503 break;
c8d86be3
GKH		 2504 case AC2_VI:
2505 write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2506 break;
c8d86be3
GKH		 2507 case AC3_VO:
2508 write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2509 break;
c8d86be3
GKH		 2510 default:
2511 printk(KERN_WARNING "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2512 break;
2513 }
2514 }
2515 ac_param += (sizeof(AC_PARAM));
2516 }
c8d86be3
GKH		 2517}
2518
c8d86be3 2519void rtl8180_tx_irq_wq(struct work_struct *work);
c8d86be3
GKH		 2520void rtl8180_restart_wq(struct work_struct *work);
2521//void rtl8180_rq_tx_ack(struct work_struct *work);
c8d86be3 2522void rtl8180_watch_dog_wq(struct work_struct *work);
c8d86be3 2523void rtl8180_hw_wakeup_wq(struct work_struct *work);
c8d86be3 2524void rtl8180_hw_sleep_wq(struct work_struct *work);
c8d86be3 2525void rtl8180_sw_antenna_wq(struct work_struct *work);
0370453f
BZ		 2526void rtl8180_watch_dog(struct net_device *dev);
2527
c8d86be3
GKH		 2528void watch_dog_adaptive(unsigned long data)
2529{
fd882783
BZ		 2530 struct r8180_priv* priv = ieee80211_priv((struct net_device *)data);
2531
2532 if (!priv->up) {
c8d86be3
GKH		 2533 DMESG("<----watch_dog_adaptive():driver is not up!\n");
2534 return;
2535 }
2536
c8d86be3 2537 // Tx High Power Mechanism.
c8d86be3 2538 if(CheckHighPower((struct net_device *)data))
c8d86be3 2539 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->tx_pw_wq);
c8d86be3 2540
c8d86be3 2541 // Tx Power Tracking on 87SE.
cffd4e16 2542 if (CheckTxPwrTracking((struct net_device *)data))
c8d86be3 2543 TxPwrTracking87SE((struct net_device *)data);
c8d86be3
GKH		 2544
2545 // Perform DIG immediately.
c8d86be3 2546 if(CheckDig((struct net_device *)data) == true)
c8d86be3 2547 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->hw_dig_wq);
c8d86be3
GKH		 2548 rtl8180_watch_dog((struct net_device *)data);
2549
c8d86be3
GKH		 2550 queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->GPIOChangeRFWorkItem);
2551
2552 priv->watch_dog_timer.expires = jiffies + MSECS(IEEE80211_WATCH_DOG_TIME);
2553 add_timer(&priv->watch_dog_timer);
c8d86be3
GKH		 2554}
2555
c8d86be3
GKH		 2556static CHANNEL_LIST ChannelPlan[] = {
2557 {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, //FCC
2558 {{1,2,3,4,5,6,7,8,9,10,11},11}, //IC
2559 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //ETSI
2560 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Spain. Change to ETSI.
2561 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //France. Change to ETSI.
2562 {{14,36,40,44,48,52,56,60,64},9}, //MKK
2563 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14, 36,40,44,48,52,56,60,64},22},//MKK1
2564 {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, //Israel.
2565 {{1,2,3,4,5,6,7,8,9,10,11,12,13,34,38,42,46},17}, // For 11a , TELEC
2566 {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, //For Global Domain. 1-11:active scan, 12-14 passive scan. //+YJ, 080626
2567 {{1,2,3,4,5,6,7,8,9,10,11,12,13},13} //world wide 13: ch1~ch11 active scan, ch12~13 passive //lzm add 080826
2568};
2569
2570static void rtl8180_set_channel_map(u8 channel_plan, struct ieee80211_device *ieee)
2571{
2572 int i;
2573
2574 //lzm add 080826
2575 ieee->MinPassiveChnlNum=MAX_CHANNEL_NUMBER+1;
2576 ieee->IbssStartChnl=0;
2577
2578 switch (channel_plan)
2579 {
2580 case COUNTRY_CODE_FCC:
2581 case COUNTRY_CODE_IC:
2582 case COUNTRY_CODE_ETSI:
2583 case COUNTRY_CODE_SPAIN:
2584 case COUNTRY_CODE_FRANCE:
2585 case COUNTRY_CODE_MKK:
2586 case COUNTRY_CODE_MKK1:
2587 case COUNTRY_CODE_ISRAEL:
2588 case COUNTRY_CODE_TELEC:
2589 {
2590 Dot11d_Init(ieee);
2591 ieee->bGlobalDomain = false;
2592 if (ChannelPlan[channel_plan].Len != 0){
2593 // Clear old channel map
2594 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2595 // Set new channel map
2596 for (i=0;i<ChannelPlan[channel_plan].Len;i++)
2597 {
2598 if(ChannelPlan[channel_plan].Channel[i] <= 14)
2599 GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan[channel_plan].Channel[i]] = 1;
2600 }
2601 }
2602 break;
2603 }
2604 case COUNTRY_CODE_GLOBAL_DOMAIN:
2605 {
2606 GET_DOT11D_INFO(ieee)->bEnabled = 0;
2607 Dot11d_Reset(ieee);
2608 ieee->bGlobalDomain = true;
2609 break;
2610 }
2611 case COUNTRY_CODE_WORLD_WIDE_13_INDEX://lzm add 080826
2612 {
2613 ieee->MinPassiveChnlNum=12;
2614 ieee->IbssStartChnl= 10;
2615 break;
2616 }
2617 default:
2618 {
2619 Dot11d_Init(ieee);
2620 ieee->bGlobalDomain = false;
2621 memset(GET_DOT11D_INFO(ieee)->channel_map, 0, sizeof(GET_DOT11D_INFO(ieee)->channel_map));
2622 for (i=1;i<=14;i++)
2623 {
2624 GET_DOT11D_INFO(ieee)->channel_map[i] = 1;
2625 }
2626 break;
2627 }
2628 }
2629}
c8d86be3 2630
c8d86be3 2631void GPIOChangeRFWorkItemCallBack(struct work_struct *work);
c8d86be3
GKH		 2632
2633//YJ,add,080828
2634static void rtl8180_statistics_init(struct Stats *pstats)
2635{
2636 memset(pstats, 0, sizeof(struct Stats));
2637}
fd882783 2638
c8d86be3
GKH		 2639static void rtl8180_link_detect_init(plink_detect_t plink_detect)
2640{
2641 memset(plink_detect, 0, sizeof(link_detect_t));
2642 plink_detect->SlotNum = DEFAULT_SLOT_NUM;
2643}
2644//YJ,add,080828,end
2645
742821ce
LF		 2646static void rtl8187se_eeprom_register_read(struct eeprom_93cx6 *eeprom)
2647{
2648 struct net_device *dev = eeprom->data;
2649 u8 reg = read_nic_byte(dev, EPROM_CMD);
2650
2651 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
2652 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
2653 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
2654 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
2655}
2656
2657static void rtl8187se_eeprom_register_write(struct eeprom_93cx6 *eeprom)
2658{
2659 struct net_device *dev = eeprom->data;
2660 u8 reg = 2 << 6;
2661
2662 if (eeprom->reg_data_in)
2663 reg |= RTL818X_EEPROM_CMD_WRITE;
2664 if (eeprom->reg_data_out)
2665 reg |= RTL818X_EEPROM_CMD_READ;
2666 if (eeprom->reg_data_clock)
2667 reg |= RTL818X_EEPROM_CMD_CK;
2668 if (eeprom->reg_chip_select)
2669 reg |= RTL818X_EEPROM_CMD_CS;
2670
2671 write_nic_byte(dev, EPROM_CMD, reg);
2672 read_nic_byte(dev, EPROM_CMD);
2673 udelay(10);
2674}
2675
c8d86be3
GKH		 2676short rtl8180_init(struct net_device *dev)
2677{
2678 struct r8180_priv *priv = ieee80211_priv(dev);
2679 u16 word;
2680 u16 version;
c8d86be3
GKH		 2681 u32 usValue;
2682 u16 tmpu16;
2683 int i, j;
742821ce
LF		 2684 struct eeprom_93cx6 eeprom;
2685 u16 eeprom_val;
2686
2687 eeprom.data = dev;
2688 eeprom.register_read = rtl8187se_eeprom_register_read;
2689 eeprom.register_write = rtl8187se_eeprom_register_write;
2690 eeprom.width = PCI_EEPROM_WIDTH_93C46;
c8d86be3 2691
742821ce
LF		 2692 eeprom_93cx6_read(&eeprom, EEPROM_COUNTRY_CODE>>1, &eeprom_val);
2693 priv->channel_plan = eeprom_val & 0xFF;
c8d86be3
GKH		 2694 if(priv->channel_plan > COUNTRY_CODE_GLOBAL_DOMAIN){
2695 printk("rtl8180_init:Error channel plan! Set to default.\n");
2696 priv->channel_plan = 0;
2697 }
c8d86be3
GKH		 2698
2699 DMESG("Channel plan is %d\n",priv->channel_plan);
2700 rtl8180_set_channel_map(priv->channel_plan, priv->ieee80211);
c8d86be3 2701
c8d86be3
GKH		 2702 //FIXME: these constants are placed in a bad pleace.
2703 priv->txbuffsize = 2048;//1024;
2704 priv->txringcount = 32;//32;
2705 priv->rxbuffersize = 2048;//1024;
2706 priv->rxringcount = 64;//32;
2707 priv->txbeaconcount = 2;
2708 priv->rx_skb_complete = 1;
c8d86be3 2709
c8d86be3 2710 priv->RegThreeWireMode = HW_THREE_WIRE_SI;
c8d86be3 2711
c8d86be3
GKH		 2712 priv->RFChangeInProgress = false;
2713 priv->SetRFPowerStateInProgress = false;
2714 priv->RFProgType = 0;
2715 priv->bInHctTest = false;
2716
2717 priv->irq_enabled=0;
2718
c8d86be3
GKH		 2719 rtl8180_statistics_init(&priv->stats);
2720 rtl8180_link_detect_init(&priv->link_detect);
c8d86be3
GKH		 2721
2722 priv->ack_tx_to_ieee = 0;
2723 priv->ieee80211->current_network.beacon_interval = DEFAULT_BEACONINTERVAL;
2724 priv->ieee80211->iw_mode = IW_MODE_INFRA;
2725 priv->ieee80211->softmac_features = IEEE_SOFTMAC_SCAN |
2726 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2727 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2728 priv->ieee80211->active_scan = 1;
2729 priv->ieee80211->rate = 110; //11 mbps
2730 priv->ieee80211->modulation = IEEE80211_CCK_MODULATION;
2731 priv->ieee80211->host_encrypt = 1;
2732 priv->ieee80211->host_decrypt = 1;
2733 priv->ieee80211->sta_wake_up = rtl8180_hw_wakeup;
2734 priv->ieee80211->ps_request_tx_ack = rtl8180_rq_tx_ack;
2735 priv->ieee80211->enter_sleep_state = rtl8180_hw_sleep;
2736 priv->ieee80211->ps_is_queue_empty = rtl8180_is_tx_queue_empty;
2737
2738 priv->hw_wep = hwwep;
2739 priv->prism_hdr=0;
2740 priv->dev=dev;
2741 priv->retry_rts = DEFAULT_RETRY_RTS;
2742 priv->retry_data = DEFAULT_RETRY_DATA;
2743 priv->RFChangeInProgress = false;
2744 priv->SetRFPowerStateInProgress = false;
2745 priv->RFProgType = 0;
2746 priv->bInHctTest = false;
2747 priv->bInactivePs = true;//false;
2748 priv->ieee80211->bInactivePs = priv->bInactivePs;
2749 priv->bSwRfProcessing = false;
2750 priv->eRFPowerState = eRfOff;
2751 priv->RfOffReason = 0;
2752 priv->LedStrategy = SW_LED_MODE0;
c8d86be3
GKH		 2753 priv->TxPollingTimes = 0;//lzm add 080826
2754 priv->bLeisurePs = true;
2755 priv->dot11PowerSaveMode = eActive;
c8d86be3
GKH		 2756 priv->AdMinCheckPeriod = 5;
2757 priv->AdMaxCheckPeriod = 10;
c8d86be3
GKH		 2758 priv->AdMaxRxSsThreshold = 30;//60->30
2759 priv->AdRxSsThreshold = 20;//50->20
2760 priv->AdCheckPeriod = priv->AdMinCheckPeriod;
2761 priv->AdTickCount = 0;
2762 priv->AdRxSignalStrength = -1;
2763 priv->RegSwAntennaDiversityMechanism = 0;
2764 priv->RegDefaultAntenna = 0;
2765 priv->SignalStrength = 0;
2766 priv->AdRxOkCnt = 0;
2767 priv->CurrAntennaIndex = 0;
2768 priv->AdRxSsBeforeSwitched = 0;
2769 init_timer(&priv->SwAntennaDiversityTimer);
2770 priv->SwAntennaDiversityTimer.data = (unsigned long)dev;
2771 priv->SwAntennaDiversityTimer.function = (void *)SwAntennaDiversityTimerCallback;
c8d86be3
GKH		 2772 priv->bDigMechanism = 1;
2773 priv->InitialGain = 6;
2774 priv->bXtalCalibration = false;
2775 priv->XtalCal_Xin = 0;
2776 priv->XtalCal_Xout = 0;
2777 priv->bTxPowerTrack = false;
2778 priv->ThermalMeter = 0;
2779 priv->FalseAlarmRegValue = 0;
2780 priv->RegDigOfdmFaUpTh = 0xc; // Upper threhold of OFDM false alarm, which is used in DIG.
2781 priv->DIG_NumberFallbackVote = 0;
2782 priv->DIG_NumberUpgradeVote = 0;
2783 priv->LastSignalStrengthInPercent = 0;
2784 priv->Stats_SignalStrength = 0;
2785 priv->LastRxPktAntenna = 0;
2786 priv->SignalQuality = 0; // in 0-100 index.
2787 priv->Stats_SignalQuality = 0;
2788 priv->RecvSignalPower = 0; // in dBm.
2789 priv->Stats_RecvSignalPower = 0;
2790 priv->AdMainAntennaRxOkCnt = 0;
2791 priv->AdAuxAntennaRxOkCnt = 0;
2792 priv->bHWAdSwitched = false;
2793 priv->bRegHighPowerMechanism = true;
2794 priv->RegHiPwrUpperTh = 77;
2795 priv->RegHiPwrLowerTh = 75;
2796 priv->RegRSSIHiPwrUpperTh = 70;
2797 priv->RegRSSIHiPwrLowerTh = 20;
2798 priv->bCurCCKPkt = false;
2799 priv->UndecoratedSmoothedSS = -1;
2800 priv->bToUpdateTxPwr = false;
2801 priv->CurCCKRSSI = 0;
2802 priv->RxPower = 0;
2803 priv->RSSI = 0;
c8d86be3
GKH		 2804 priv->NumTxOkTotal = 0;
2805 priv->NumTxUnicast = 0;
2806 priv->keepAliveLevel = DEFAULT_KEEP_ALIVE_LEVEL;
2807 priv->PowerProfile = POWER_PROFILE_AC;
1994130e
LF		 2808 priv->CurrRetryCnt = 0;
2809 priv->LastRetryCnt = 0;
2810 priv->LastTxokCnt = 0;
2811 priv->LastRxokCnt = 0;
2812 priv->LastRetryRate = 0;
2813 priv->bTryuping = 0;
2814 priv->CurrTxRate = 0;
2815 priv->CurrRetryRate = 0;
2816 priv->TryupingCount = 0;
2817 priv->TryupingCountNoData = 0;
2818 priv->TryDownCountLowData = 0;
2819 priv->LastTxOKBytes = 0;
2820 priv->LastFailTxRate = 0;
2821 priv->LastFailTxRateSS = 0;
2822 priv->FailTxRateCount = 0;
2823 priv->LastTxThroughput = 0;
2824 priv->NumTxOkBytesTotal = 0;
c8d86be3
GKH		 2825 priv->ForcedDataRate = 0;
2826 priv->RegBModeGainStage = 1;
2827
1994130e 2828 priv->promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
c8d86be3
GKH		 2829 spin_lock_init(&priv->irq_lock);
2830 spin_lock_init(&priv->irq_th_lock);
2831 spin_lock_init(&priv->tx_lock);
2832 spin_lock_init(&priv->ps_lock);
2833 spin_lock_init(&priv->rf_ps_lock);
1994130e
LF		 2834 sema_init(&priv->wx_sem, 1);
2835 sema_init(&priv->rf_state, 1);
2836 INIT_WORK(&priv->reset_wq, (void *)rtl8180_restart_wq);
2837 INIT_WORK(&priv->tx_irq_wq, (void *)rtl8180_tx_irq_wq);
2838 INIT_DELAYED_WORK(&priv->ieee80211->hw_wakeup_wq,
2839 (void *)rtl8180_hw_wakeup_wq);
2840 INIT_DELAYED_WORK(&priv->ieee80211->hw_sleep_wq,
2841 (void *)rtl8180_hw_sleep_wq);
2842 INIT_WORK(&priv->ieee80211->wmm_param_update_wq,
2843 (void *)rtl8180_wmm_param_update);
2844 INIT_DELAYED_WORK(&priv->ieee80211->rate_adapter_wq,
2845 (void *)rtl8180_rate_adapter);
2846 INIT_DELAYED_WORK(&priv->ieee80211->hw_dig_wq,
2847 (void *)rtl8180_hw_dig_wq);
2848 INIT_DELAYED_WORK(&priv->ieee80211->tx_pw_wq,
2849 (void *)rtl8180_tx_pw_wq);
2850 INIT_DELAYED_WORK(&priv->ieee80211->GPIOChangeRFWorkItem,
2851 (void *) GPIOChangeRFWorkItemCallBack);
c8d86be3
GKH		 2852 tasklet_init(&priv->irq_rx_tasklet,
2853 (void(*)(unsigned long)) rtl8180_irq_rx_tasklet,
2854 (unsigned long)priv);
fd882783 2855
1994130e 2856 init_timer(&priv->watch_dog_timer);
c8d86be3
GKH		 2857 priv->watch_dog_timer.data = (unsigned long)dev;
2858 priv->watch_dog_timer.function = watch_dog_adaptive;
c8d86be3 2859
1994130e
LF		 2860 init_timer(&priv->rateadapter_timer);
2861 priv->rateadapter_timer.data = (unsigned long)dev;
2862 priv->rateadapter_timer.function = timer_rate_adaptive;
2863 priv->RateAdaptivePeriod = RATE_ADAPTIVE_TIMER_PERIOD;
2864 priv->bEnhanceTxPwr = false;
c8d86be3
GKH		 2865
2866 priv->ieee80211->softmac_hard_start_xmit = rtl8180_hard_start_xmit;
2867 priv->ieee80211->set_chan = rtl8180_set_chan;
2868 priv->ieee80211->link_change = rtl8180_link_change;
2869 priv->ieee80211->softmac_data_hard_start_xmit = rtl8180_hard_data_xmit;
2870 priv->ieee80211->data_hard_stop = rtl8180_data_hard_stop;
2871 priv->ieee80211->data_hard_resume = rtl8180_data_hard_resume;
2872
2873 priv->ieee80211->init_wmmparam_flag = 0;
2874
2875 priv->ieee80211->start_send_beacons = rtl8180_start_tx_beacon;
2876 priv->ieee80211->stop_send_beacons = rtl8180_beacon_tx_disable;
2877 priv->ieee80211->fts = DEFAULT_FRAG_THRESHOLD;
2878
c8d86be3
GKH		 2879 priv->MWIEnable = 0;
2880
2881 priv->ShortRetryLimit = 7;
2882 priv->LongRetryLimit = 7;
2883 priv->EarlyRxThreshold = 7;
2884
2885 priv->CSMethod = (0x01 << 29);
2886
1994130e
LF		 2887 priv->TransmitConfig = TCR_DurProcMode_OFFSET |
2888 (7<<TCR_MXDMA_OFFSET) |
2889 (priv->ShortRetryLimit<<TCR_SRL_OFFSET) |
2890 (priv->LongRetryLimit<<TCR_LRL_OFFSET) |
2891 (0 ? TCR_SAT : 0);
2892
2893 priv->ReceiveConfig = RCR_AMF | RCR_ADF | RCR_ACF |
2894 RCR_AB | RCR_AM | RCR_APM |
2895 (7<<RCR_MXDMA_OFFSET) |
2896 (priv->EarlyRxThreshold<<RCR_FIFO_OFFSET) |
2897 (priv->EarlyRxThreshold == 7 ?
2898 RCR_ONLYERLPKT : 0);
c8d86be3
GKH		 2899
2900 priv->IntrMask = IMR_TMGDOK | IMR_TBDER | IMR_THPDER |
1994130e
LF		 2901 IMR_THPDER | IMR_THPDOK |
2902 IMR_TVODER | IMR_TVODOK |
2903 IMR_TVIDER | IMR_TVIDOK |
2904 IMR_TBEDER | IMR_TBEDOK |
2905 IMR_TBKDER | IMR_TBKDOK |
2906 IMR_RDU |
2907 IMR_RER | IMR_ROK |
2908 IMR_RQoSOK;
c8d86be3
GKH		 2909
2910 priv->InitialGain = 6;
c8d86be3 2911
d44eb889
LF		 2912 DMESG("MAC controller is a RTL8187SE b/g");
2913 priv->phy_ver = 2;
c8d86be3 2914
d44eb889
LF		 2915 priv->ieee80211->modulation |= IEEE80211_OFDM_MODULATION;
2916 priv->ieee80211->short_slot = 1;
c8d86be3 2917
c8d86be3 2918 // just for sync 85
c8d86be3
GKH		 2919 priv->enable_gpio0 = 0;
2920
742821ce
LF		 2921 eeprom_93cx6_read(&eeprom, EEPROM_SW_REVD_OFFSET, &eeprom_val);
2922 usValue = eeprom_val;
c8d86be3 2923 DMESG("usValue is 0x%x\n",usValue);
c8d86be3 2924 //3Read AntennaDiversity
fd882783 2925
c8d86be3 2926 // SW Antenna Diversity.
fd882783 2927 if ((usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE)
c8d86be3 2928 priv->EEPROMSwAntennaDiversity = false;
c8d86be3 2929 else
c8d86be3 2930 priv->EEPROMSwAntennaDiversity = true;
fd882783 2931
c8d86be3 2932 // Default Antenna to use.
fd882783 2933 if ((usValue & EEPROM_DEF_ANT_MASK) != EEPROM_DEF_ANT_1)
c8d86be3 2934 priv->EEPROMDefaultAntenna1 = false;
c8d86be3 2935 else
c8d86be3 2936 priv->EEPROMDefaultAntenna1 = true;
c8d86be3 2937
c8d86be3 2938 if( priv->RegSwAntennaDiversityMechanism == 0 ) // Auto
fd882783 2939 /* 0: default from EEPROM. */
c8d86be3 2940 priv->bSwAntennaDiverity = priv->EEPROMSwAntennaDiversity;
c8d86be3 2941 else
fd882783 2942 /* 1:disable antenna diversity, 2: enable antenna diversity. */
c8d86be3 2943 priv->bSwAntennaDiverity = ((priv->RegSwAntennaDiversityMechanism == 1)? false : true);
c8d86be3 2944
fd882783
BZ		 2945 if (priv->RegDefaultAntenna == 0)
2946 /* 0: default from EEPROM. */
c8d86be3 2947 priv->bDefaultAntenna1 = priv->EEPROMDefaultAntenna1;
c8d86be3 2948 else
fd882783 2949 /* 1: main, 2: aux. */
c8d86be3 2950 priv->bDefaultAntenna1 = ((priv->RegDefaultAntenna== 2) ? true : false);
fd882783 2951
c8d86be3
GKH		 2952 /* rtl8185 can calc plcp len in HW.*/
2953 priv->hw_plcp_len = 1;
2954
2955 priv->plcp_preamble_mode = 2;
2956 /*the eeprom type is stored in RCR register bit #6 */
fd882783 2957 if (RCR_9356SEL & read_nic_dword(dev, RCR))
c8d86be3 2958 priv->epromtype=EPROM_93c56;
fd882783 2959 else
c8d86be3 2960 priv->epromtype=EPROM_93c46;
c8d86be3 2961
742821ce
LF		 2962 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)
2963 dev->dev_addr, 3);
c8d86be3
GKH		 2964
2965 for(i=1,j=0; i<14; i+=2,j++){
742821ce 2966 eeprom_93cx6_read(&eeprom, EPROM_TXPW_CH1_2 + j, &word);
c8d86be3
GKH		 2967 priv->chtxpwr[i]=word & 0xff;
2968 priv->chtxpwr[i+1]=(word & 0xff00)>>8;
c8d86be3 2969 }
d44eb889 2970 for (i = 1, j = 0; i < 14; i += 2, j++) {
742821ce 2971 eeprom_93cx6_read(&eeprom, EPROM_TXPW_OFDM_CH1_2 + j, &word);
d44eb889 2972 priv->chtxpwr_ofdm[i] = word & 0xff;
1994130e 2973 priv->chtxpwr_ofdm[i+1] = (word & 0xff00) >> 8;
c8d86be3 2974 }
fd882783 2975
1994130e 2976 /* 3Read crystal calibtration and thermal meter indication on 87SE. */
742821ce 2977 eeprom_93cx6_read(&eeprom, EEPROM_RSV>>1, &tmpu16);
c8d86be3 2978
1994130e
LF		 2979 /* Crystal calibration for Xin and Xout resp. */
2980 priv->XtalCal_Xout = tmpu16 & EEPROM_XTAL_CAL_XOUT_MASK;
2981 priv->XtalCal_Xin = (tmpu16 & EEPROM_XTAL_CAL_XIN_MASK) >> 4;
2982 if ((tmpu16 & EEPROM_XTAL_CAL_ENABLE) >> 12)
2983 priv->bXtalCalibration = true;
c8d86be3 2984
1994130e
LF		 2985 /* Thermal meter reference indication. */
2986 priv->ThermalMeter = (u8)((tmpu16 & EEPROM_THERMAL_METER_MASK) >> 8);
2987 if ((tmpu16 & EEPROM_THERMAL_METER_ENABLE) >> 13)
2988 priv->bTxPowerTrack = true;
c8d86be3 2989
742821ce 2990 eeprom_93cx6_read(&eeprom, EPROM_TXPW_BASE, &word);
c8d86be3
GKH		 2991 priv->cck_txpwr_base = word & 0xf;
2992 priv->ofdm_txpwr_base = (word>>4) & 0xf;
c8d86be3 2993
742821ce 2994 eeprom_93cx6_read(&eeprom, EPROM_VERSION, &version);
c8d86be3 2995 DMESG("EEPROM version %x",version);
d44eb889 2996 priv->rcr_csense = 3;
c8d86be3 2997
742821ce
LF		 2998 eeprom_93cx6_read(&eeprom, ENERGY_TRESHOLD, &eeprom_val);
2999 priv->cs_treshold = (eeprom_val & 0xff00) >> 8;
c8d86be3 3000
742821ce
LF		 3001 eeprom_93cx6_read(&eeprom, RFCHIPID, &eeprom_val);
3002 priv->rf_chip = 0xff & eeprom_val;
c8d86be3 3003
c8d86be3
GKH		 3004 priv->rf_chip = RF_ZEBRA4;
3005 priv->rf_sleep = rtl8225z4_rf_sleep;
3006 priv->rf_wakeup = rtl8225z4_rf_wakeup;
c8d86be3
GKH		 3007 DMESGW("**PLEASE** REPORT SUCCESSFUL/UNSUCCESSFUL TO Realtek!");
3008
3009 priv->rf_close = rtl8225z2_rf_close;
3010 priv->rf_init = rtl8225z2_rf_init;
3011 priv->rf_set_chan = rtl8225z2_rf_set_chan;
3012 priv->rf_set_sens = NULL;
c8d86be3 3013
c8d86be3
GKH		 3014 if (0!=alloc_rx_desc_ring(dev, priv->rxbuffersize, priv->rxringcount))
3015 return -ENOMEM;
3016
3017 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3018 TX_MANAGEPRIORITY_RING_ADDR))
3019 return -ENOMEM;
3020
3021 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3022 TX_BKPRIORITY_RING_ADDR))
3023 return -ENOMEM;
3024
3025 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3026 TX_BEPRIORITY_RING_ADDR))
3027 return -ENOMEM;
3028
3029 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3030 TX_VIPRIORITY_RING_ADDR))
3031 return -ENOMEM;
3032
3033 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3034 TX_VOPRIORITY_RING_ADDR))
3035 return -ENOMEM;
3036
3037 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txringcount,
3038 TX_HIGHPRIORITY_RING_ADDR))
3039 return -ENOMEM;
3040
3041 if (0!=alloc_tx_desc_ring(dev, priv->txbuffsize, priv->txbeaconcount,
3042 TX_BEACON_RING_ADDR))
3043 return -ENOMEM;
3044
c8d86be3 3045 if(request_irq(dev->irq, (void *)rtl8180_interrupt, IRQF_SHARED, dev->name, dev)){
c8d86be3
GKH		 3046 DMESGE("Error allocating IRQ %d",dev->irq);
3047 return -1;
3048 }else{
3049 priv->irq=dev->irq;
3050 DMESG("IRQ %d",dev->irq);
3051 }
3052
c8d86be3 3053 return 0;
c8d86be3
GKH		 3054}
3055
c8d86be3
GKH		 3056void rtl8180_no_hw_wep(struct net_device *dev)
3057{
c8d86be3
GKH		 3058}
3059
c8d86be3
GKH		 3060void rtl8180_set_hw_wep(struct net_device *dev)
3061{
3062 struct r8180_priv *priv = ieee80211_priv(dev);
3063 u8 pgreg;
3064 u8 security;
3065 u32 key0_word4;
3066
3067 pgreg=read_nic_byte(dev, PGSELECT);
3068 write_nic_byte(dev, PGSELECT, pgreg &~ (1<<PGSELECT_PG_SHIFT));
3069
3070 key0_word4 = read_nic_dword(dev, KEY0+4+4+4);
3071 key0_word4 &= ~ 0xff;
3072 key0_word4 |= priv->key0[3]& 0xff;
3073 write_nic_dword(dev,KEY0,(priv->key0[0]));
3074 write_nic_dword(dev,KEY0+4,(priv->key0[1]));
3075 write_nic_dword(dev,KEY0+4+4,(priv->key0[2]));
3076 write_nic_dword(dev,KEY0+4+4+4,(key0_word4));
3077
c8d86be3
GKH		 3078 security = read_nic_byte(dev,SECURITY);
3079 security |= (1<<SECURITY_WEP_TX_ENABLE_SHIFT);
3080 security |= (1<<SECURITY_WEP_RX_ENABLE_SHIFT);
3081 security &= ~ SECURITY_ENCRYP_MASK;
3082 security |= (SECURITY_ENCRYP_104<<SECURITY_ENCRYP_SHIFT);
3083
3084 write_nic_byte(dev, SECURITY, security);
3085
3086 DMESG("key %x %x %x %x",read_nic_dword(dev,KEY0+4+4+4),
3087 read_nic_dword(dev,KEY0+4+4),read_nic_dword(dev,KEY0+4),
3088 read_nic_dword(dev,KEY0));
c8d86be3
GKH		 3089}
3090
3091
3092void rtl8185_rf_pins_enable(struct net_device *dev)
3093{
3094// u16 tmp;
3095// tmp = read_nic_word(dev, RFPinsEnable);
3096 write_nic_word(dev, RFPinsEnable, 0x1fff);// | tmp);
c8d86be3
GKH		 3097}
3098
c8d86be3
GKH		 3099void rtl8185_set_anaparam2(struct net_device *dev, u32 a)
3100{
3101 u8 conf3;
3102
3103 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3104
3105 conf3 = read_nic_byte(dev, CONFIG3);
3106 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3107 write_nic_dword(dev, ANAPARAM2, a);
3108
3109 conf3 = read_nic_byte(dev, CONFIG3);
3110 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3111 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH		 3112}
3113
c8d86be3
GKH		 3114void rtl8180_set_anaparam(struct net_device *dev, u32 a)
3115{
3116 u8 conf3;
3117
3118 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3119
3120 conf3 = read_nic_byte(dev, CONFIG3);
3121 write_nic_byte(dev, CONFIG3, conf3 | (1<<CONFIG3_ANAPARAM_W_SHIFT));
3122 write_nic_dword(dev, ANAPARAM, a);
3123
3124 conf3 = read_nic_byte(dev, CONFIG3);
3125 write_nic_byte(dev, CONFIG3, conf3 &~(1<<CONFIG3_ANAPARAM_W_SHIFT));
3126 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3127}
3128
c8d86be3
GKH		 3129void rtl8185_tx_antenna(struct net_device *dev, u8 ant)
3130{
3131 write_nic_byte(dev, TX_ANTENNA, ant);
3132 force_pci_posting(dev);
3133 mdelay(1);
3134}
3135
c8d86be3
GKH		 3136void rtl8185_write_phy(struct net_device *dev, u8 adr, u32 data)
3137{
c8d86be3 3138 u32 phyw;
c8d86be3
GKH		 3139
3140 adr |= 0x80;
3141
3142 phyw= ((data<<8) | adr);
c8d86be3 3143
c8d86be3
GKH		 3144 // Note that, we must write 0xff7c after 0x7d-0x7f to write BB register.
3145 write_nic_byte(dev, 0x7f, ((phyw & 0xff000000) >> 24));
3146 write_nic_byte(dev, 0x7e, ((phyw & 0x00ff0000) >> 16));
3147 write_nic_byte(dev, 0x7d, ((phyw & 0x0000ff00) >> 8));
3148 write_nic_byte(dev, 0x7c, ((phyw & 0x000000ff) ));
5521a513 3149
c8d86be3
GKH		 3150 /* this is ok to fail when we write AGC table. check for AGC table might be
3151 * done by masking with 0x7f instead of 0xff
3152 */
3153 //if(phyr != (data&0xff)) DMESGW("Phy write timeout %x %x %x", phyr, data,adr);
3154}
3155
c8d86be3
GKH		 3156inline void write_phy_ofdm (struct net_device *dev, u8 adr, u32 data)
3157{
3158 data = data & 0xff;
3159 rtl8185_write_phy(dev, adr, data);
3160}
3161
c8d86be3
GKH		 3162void write_phy_cck (struct net_device *dev, u8 adr, u32 data)
3163{
3164 data = data & 0xff;
3165 rtl8185_write_phy(dev, adr, data | 0x10000);
3166}
3167
c8d86be3
GKH		 3168/* 70*3 = 210 ms
3169 * I hope this is enougth
3170 */
3171#define MAX_PHY 70
3172void write_phy(struct net_device *dev, u8 adr, u8 data)
3173{
3174 u32 phy;
3175 int i;
3176
3177 phy = 0xff0000;
3178 phy |= adr;
3179 phy |= 0x80; /* this should enable writing */
3180 phy |= (data<<8);
3181
3182 //PHY_ADR, PHY_R and PHY_W are contig and treated as one dword
3183 write_nic_dword(dev,PHY_ADR, phy);
3184
3185 phy= 0xffff00;
3186 phy |= adr;
3187
3188 write_nic_dword(dev,PHY_ADR, phy);
3189 for(i=0;i<MAX_PHY;i++){
3190 phy=read_nic_dword(dev,PHY_ADR);
3191 phy= phy & 0xff0000;
3192 phy= phy >> 16;
3193 if(phy == data){ //SUCCESS!
3194 force_pci_posting(dev);
3195 mdelay(3); //random value
c8d86be3
GKH		 3196 return;
3197 }else{
3198 force_pci_posting(dev);
3199 mdelay(3); //random value
3200 }
3201 }
3202 DMESGW ("Phy writing %x %x failed!", adr,data);
3203}
3204
3205void rtl8185_set_rate(struct net_device *dev)
3206{
3207 int i;
3208 u16 word;
3209 int basic_rate,min_rr_rate,max_rr_rate;
3210
c8d86be3
GKH		 3211 basic_rate = ieeerate2rtlrate(240);
3212 min_rr_rate = ieeerate2rtlrate(60);
3213 max_rr_rate = ieeerate2rtlrate(240);
3214
c8d86be3
GKH		 3215 write_nic_byte(dev, RESP_RATE,
3216 max_rr_rate<<MAX_RESP_RATE_SHIFT| min_rr_rate<<MIN_RESP_RATE_SHIFT);
3217
3218 word = read_nic_word(dev, BRSR);
3219 word &= ~BRSR_MBR_8185;
3220
c8d86be3
GKH		 3221 for(i=0;i<=basic_rate;i++)
3222 word |= (1<<i);
3223
3224 write_nic_word(dev, BRSR, word);
c8d86be3
GKH		 3225}
3226
c8d86be3
GKH		 3227void rtl8180_adapter_start(struct net_device *dev)
3228{
3229 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 3230
3231 rtl8180_rtx_disable(dev);
3232 rtl8180_reset(dev);
3233
c8d86be3
GKH		 3234 /* enable beacon timeout, beacon TX ok and err
3235 * LP tx ok and err, HP TX ok and err, NP TX ok and err,
3236 * RX ok and ERR, and GP timer */
3237 priv->irq_mask = 0x6fcf;
3238
3239 priv->dma_poll_mask = 0;
3240
3241 rtl8180_beacon_tx_disable(dev);
3242
c8d86be3
GKH		 3243 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3244 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
3245 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
3246 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3247
3248 rtl8180_update_msr(dev);
3249
c8d86be3
GKH		 3250 /* These might be unnecessary since we do in rx_enable / tx_enable */
3251 fix_rx_fifo(dev);
3252 fix_tx_fifo(dev);
c8d86be3
GKH		 3253
3254 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3255
3256 /*
3257 The following is very strange. seems to be that 1 means test mode,
3258 but we need to acknolwledges the nic when a packet is ready
bbc9a991 3259 although we set it to 0
c8d86be3
GKH		 3260 */
3261
3262 write_nic_byte(dev,
3263 CONFIG2, read_nic_byte(dev,CONFIG2) &~\
3264 (1<<CONFIG2_DMA_POLLING_MODE_SHIFT));
3265 //^the nic isn't in test mode
d44eb889 3266 write_nic_byte(dev,
c8d86be3
GKH		 3267 CONFIG2, read_nic_byte(dev,CONFIG2)|(1<<4));
3268
3269 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3270
3271 write_nic_dword(dev,INT_TIMEOUT,0);
c8d86be3 3272
d44eb889 3273 write_nic_byte(dev, WPA_CONFIG, 0);
c8d86be3
GKH		 3274
3275 rtl8180_no_hw_wep(dev);
3276
d44eb889
LF		 3277 rtl8185_set_rate(dev);
3278 write_nic_byte(dev, RATE_FALLBACK, 0x81);
c8d86be3 3279
d44eb889 3280 write_nic_byte(dev, GP_ENABLE, read_nic_byte(dev, GP_ENABLE) & ~(1<<6));
c8d86be3 3281
d44eb889
LF		 3282 /*FIXME cfg 3 ClkRun enable - isn't it ReadOnly ? */
3283 rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
3284 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3)
3285 | (1 << CONFIG3_CLKRUN_SHIFT));
3286 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
c8d86be3
GKH		 3287
3288 priv->rf_init(dev);
3289
3290 if(priv->rf_set_sens != NULL)
3291 priv->rf_set_sens(dev,priv->sens);
3292 rtl8180_irq_enable(dev);
3293
3294 netif_start_queue(dev);
c8d86be3
GKH		 3295}
3296
c8d86be3
GKH		 3297/* this configures registers for beacon tx and enables it via
3298 * rtl8180_beacon_tx_enable(). rtl8180_beacon_tx_disable() might
3299 * be used to stop beacon transmission
3300 */
3301void rtl8180_start_tx_beacon(struct net_device *dev)
3302{
c8d86be3 3303 u16 word;
c8d86be3
GKH		 3304
3305 DMESG("Enabling beacon TX");
c8d86be3
GKH		 3306 rtl8180_prepare_beacon(dev);
3307 rtl8180_irq_disable(dev);
3308 rtl8180_beacon_tx_enable(dev);
c8d86be3 3309
c8d86be3
GKH		 3310 word = read_nic_word(dev, AtimWnd) &~ AtimWnd_AtimWnd;
3311 write_nic_word(dev, AtimWnd,word);// word |=
c8d86be3
GKH		 3312
3313 word = read_nic_word(dev, BintrItv);
3314 word &= ~BintrItv_BintrItv;
3315 word |= 1000;/*priv->ieee80211->current_network.beacon_interval *
3316 ((priv->txbeaconcount > 1)?(priv->txbeaconcount-1):1);
3317 // FIXME: check if correct ^^ worked with 0x3e8;
3318 */
3319 write_nic_word(dev, BintrItv, word);
3320
c8d86be3
GKH		 3321 rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
3322
c8d86be3 3323 rtl8185b_irq_enable(dev);
c8d86be3
GKH		 3324}
3325
c8d86be3
GKH		 3326static struct net_device_stats *rtl8180_stats(struct net_device *dev)
3327{
3328 struct r8180_priv *priv = ieee80211_priv(dev);
3329
3330 return &priv->ieee80211->stats;
3331}
3332//
3333// Change current and default preamble mode.
c8d86be3
GKH		 3334//
3335bool
3336MgntActSet_802_11_PowerSaveMode(
3337 struct r8180_priv *priv,
3338 RT_PS_MODE rtPsMode
3339)
3340{
c8d86be3
GKH		 3341 // Currently, we do not change power save mode on IBSS mode.
3342 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
c8d86be3 3343 return false;
c8d86be3 3344
c8d86be3 3345 priv->ieee80211->ps = rtPsMode;
5521a513 3346
c8d86be3
GKH		 3347 return true;
3348}
3349
fd882783 3350void LeisurePSEnter(struct r8180_priv *priv)
c8d86be3 3351{
fd882783 3352 if (priv->bLeisurePs) {
c8d86be3 3353 if (priv->ieee80211->ps == IEEE80211_PS_DISABLED)
c8d86be3 3354 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_MBCAST|IEEE80211_PS_UNICAST);//IEEE80211_PS_ENABLE
c8d86be3
GKH		 3355 }
3356}
3357
fd882783 3358void LeisurePSLeave(struct r8180_priv *priv)
c8d86be3 3359{
fd882783 3360 if (priv->bLeisurePs) {
c8d86be3 3361 if (priv->ieee80211->ps != IEEE80211_PS_DISABLED)
c8d86be3 3362 MgntActSet_802_11_PowerSaveMode(priv, IEEE80211_PS_DISABLED);
c8d86be3
GKH		 3363 }
3364}
0370453f 3365
c8d86be3
GKH		 3366void rtl8180_hw_wakeup_wq (struct work_struct *work)
3367{
bf6aede7 3368 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 3369 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_wakeup_wq);
3370 struct net_device *dev = ieee->dev;
c8d86be3 3371
c8d86be3 3372 rtl8180_hw_wakeup(dev);
c8d86be3
GKH		 3373}
3374
c8d86be3
GKH		 3375void rtl8180_hw_sleep_wq (struct work_struct *work)
3376{
bf6aede7 3377 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 3378 struct ieee80211_device *ieee = container_of(dwork,struct ieee80211_device,hw_sleep_wq);
3379 struct net_device *dev = ieee->dev;
c8d86be3
GKH		 3380
3381 rtl8180_hw_sleep_down(dev);
3382}
3383
c8d86be3
GKH		 3384static void MgntLinkKeepAlive(struct r8180_priv *priv )
3385{
3386 if (priv->keepAliveLevel == 0)
3387 return;
3388
3389 if(priv->ieee80211->state == IEEE80211_LINKED)
3390 {
3391 //
3392 // Keep-Alive.
3393 //
c8d86be3
GKH		 3394
3395 if ( (priv->keepAliveLevel== 2) ||
3396 (priv->link_detect.LastNumTxUnicast == priv->NumTxUnicast &&
3397 priv->link_detect.LastNumRxUnicast == priv->ieee80211->NumRxUnicast )
3398 )
3399 {
3400 priv->link_detect.IdleCount++;
3401
3402 //
3403 // Send a Keep-Alive packet packet to AP if we had been idle for a while.
3404 //
3405 if(priv->link_detect.IdleCount >= ((KEEP_ALIVE_INTERVAL / CHECK_FOR_HANG_PERIOD)-1) )
3406 {
3407 priv->link_detect.IdleCount = 0;
3408 ieee80211_sta_ps_send_null_frame(priv->ieee80211, false);
3409 }
3410 }
3411 else
3412 {
3413 priv->link_detect.IdleCount = 0;
3414 }
3415 priv->link_detect.LastNumTxUnicast = priv->NumTxUnicast;
3416 priv->link_detect.LastNumRxUnicast = priv->ieee80211->NumRxUnicast;
3417 }
3418}
c8d86be3
GKH		 3419
3420static u8 read_acadapter_file(char *filename);
fd882783 3421
c8d86be3
GKH		 3422void rtl8180_watch_dog(struct net_device *dev)
3423{
3424 struct r8180_priv *priv = ieee80211_priv(dev);
3425 bool bEnterPS = false;
3426 bool bBusyTraffic = false;
3427 u32 TotalRxNum = 0;
3428 u16 SlotIndex = 0;
3429 u16 i = 0;
c8d86be3
GKH		 3430 if(priv->ieee80211->actscanning == false){
3431 if((priv->ieee80211->iw_mode != IW_MODE_ADHOC) && (priv->ieee80211->state == IEEE80211_NOLINK) && (priv->ieee80211->beinretry == false) && (priv->eRFPowerState == eRfOn)){
3432 IPSEnter(dev);
3433 }
3434 }
c8d86be3
GKH		 3435 //YJ,add,080828,for link state check
3436 if((priv->ieee80211->state == IEEE80211_LINKED) && (priv->ieee80211->iw_mode == IW_MODE_INFRA)){
3437 SlotIndex = (priv->link_detect.SlotIndex++) % priv->link_detect.SlotNum;
3438 priv->link_detect.RxFrameNum[SlotIndex] = priv->ieee80211->NumRxDataInPeriod + priv->ieee80211->NumRxBcnInPeriod;
3439 for( i=0; i<priv->link_detect.SlotNum; i++ )
3440 TotalRxNum+= priv->link_detect.RxFrameNum[i];
fd882783 3441
c8d86be3
GKH		 3442 if(TotalRxNum == 0){
3443 priv->ieee80211->state = IEEE80211_ASSOCIATING;
3444 queue_work(priv->ieee80211->wq, &priv->ieee80211->associate_procedure_wq);
3445 }
3446 }
3447
3448 //YJ,add,080828,for KeepAlive
3449 MgntLinkKeepAlive(priv);
3450
3451 //YJ,add,080828,for LPS
fd882783 3452 if (priv->PowerProfile == POWER_PROFILE_BATTERY)
c8d86be3 3453 priv->bLeisurePs = true;
fd882783 3454 else if (priv->PowerProfile == POWER_PROFILE_AC) {
c8d86be3
GKH		 3455 LeisurePSLeave(priv);
3456 priv->bLeisurePs= false;
3457 }
c8d86be3 3458
c8d86be3
GKH		 3459 if(priv->ieee80211->state == IEEE80211_LINKED){
3460 priv->link_detect.NumRxOkInPeriod = priv->ieee80211->NumRxDataInPeriod;
c8d86be3
GKH		 3461 if( priv->link_detect.NumRxOkInPeriod> 666 ||
3462 priv->link_detect.NumTxOkInPeriod> 666 ) {
3463 bBusyTraffic = true;
3464 }
3465 if(((priv->link_detect.NumRxOkInPeriod + priv->link_detect.NumTxOkInPeriod) > 8)
3466 || (priv->link_detect.NumRxOkInPeriod > 2)) {
3467 bEnterPS= false;
fd882783 3468 } else
c8d86be3 3469 bEnterPS= true;
c8d86be3 3470
fd882783 3471 if (bEnterPS)
c8d86be3 3472 LeisurePSEnter(priv);
fd882783 3473 else
c8d86be3 3474 LeisurePSLeave(priv);
fd882783 3475 } else
c8d86be3 3476 LeisurePSLeave(priv);
c8d86be3
GKH		 3477 priv->link_detect.bBusyTraffic = bBusyTraffic;
3478 priv->link_detect.NumRxOkInPeriod = 0;
3479 priv->link_detect.NumTxOkInPeriod = 0;
3480 priv->ieee80211->NumRxDataInPeriod = 0;
3481 priv->ieee80211->NumRxBcnInPeriod = 0;
c8d86be3 3482}
fd882783 3483
c8d86be3
GKH		 3484int _rtl8180_up(struct net_device *dev)
3485{
3486 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 3487
3488 priv->up=1;
3489
3490 DMESG("Bringing up iface");
c8d86be3
GKH		 3491 rtl8185b_adapter_start(dev);
3492 rtl8185b_rx_enable(dev);
3493 rtl8185b_tx_enable(dev);
c8d86be3
GKH		 3494 if(priv->bInactivePs){
3495 if(priv->ieee80211->iw_mode == IW_MODE_ADHOC)
3496 IPSLeave(dev);
3497 }
c8d86be3 3498 timer_rate_adaptive((unsigned long)dev);
c8d86be3 3499 watch_dog_adaptive((unsigned long)dev);
c8d86be3
GKH		 3500 if(priv->bSwAntennaDiverity)
3501 SwAntennaDiversityTimerCallback(dev);
c8d86be3 3502 ieee80211_softmac_start_protocol(priv->ieee80211);
c8d86be3
GKH		 3503 return 0;
3504}
3505
c8d86be3
GKH		 3506int rtl8180_open(struct net_device *dev)
3507{
3508 struct r8180_priv *priv = ieee80211_priv(dev);
3509 int ret;
3510
3511 down(&priv->wx_sem);
3512 ret = rtl8180_up(dev);
3513 up(&priv->wx_sem);
3514 return ret;
c8d86be3
GKH		 3515}
3516
c8d86be3
GKH		 3517int rtl8180_up(struct net_device *dev)
3518{
3519 struct r8180_priv *priv = ieee80211_priv(dev);
3520
3521 if (priv->up == 1) return -1;
3522
3523 return _rtl8180_up(dev);
3524}
3525
c8d86be3
GKH		 3526int rtl8180_close(struct net_device *dev)
3527{
3528 struct r8180_priv *priv = ieee80211_priv(dev);
3529 int ret;
3530
3531 down(&priv->wx_sem);
3532 ret = rtl8180_down(dev);
3533 up(&priv->wx_sem);
3534
3535 return ret;
c8d86be3
GKH		 3536}
3537
3538int rtl8180_down(struct net_device *dev)
3539{
3540 struct r8180_priv *priv = ieee80211_priv(dev);
3541
fd882783
BZ		 3542 if (priv->up == 0)
3543 return -1;
c8d86be3
GKH		 3544
3545 priv->up=0;
3546
3547 ieee80211_softmac_stop_protocol(priv->ieee80211);
3548 /* FIXME */
3549 if (!netif_queue_stopped(dev))
3550 netif_stop_queue(dev);
3551 rtl8180_rtx_disable(dev);
3552 rtl8180_irq_disable(dev);
3553 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ		 3554 del_timer_sync(&priv->rateadapter_timer);
3555 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH		 3556 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3557 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3558 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3559 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3560 del_timer_sync(&priv->SwAntennaDiversityTimer);
3561 SetZebraRFPowerState8185(dev,eRfOff);
c8d86be3
GKH		 3562 memset(&(priv->ieee80211->current_network),0,sizeof(struct ieee80211_network));
3563 priv->ieee80211->state = IEEE80211_NOLINK;
3564 return 0;
3565}
3566
c8d86be3
GKH		 3567void rtl8180_restart_wq(struct work_struct *work)
3568{
3569 struct r8180_priv *priv = container_of(work, struct r8180_priv, reset_wq);
3570 struct net_device *dev = priv->dev;
0370453f 3571
c8d86be3
GKH		 3572 down(&priv->wx_sem);
3573
3574 rtl8180_commit(dev);
3575
3576 up(&priv->wx_sem);
3577}
3578
3579void rtl8180_restart(struct net_device *dev)
3580{
3581 struct r8180_priv *priv = ieee80211_priv(dev);
fd882783 3582
c8d86be3 3583 schedule_work(&priv->reset_wq);
c8d86be3
GKH		 3584}
3585
c8d86be3
GKH		 3586void rtl8180_commit(struct net_device *dev)
3587{
3588 struct r8180_priv *priv = ieee80211_priv(dev);
3589
fd882783
BZ		 3590 if (priv->up == 0)
3591 return ;
3592
c8d86be3 3593 del_timer_sync(&priv->watch_dog_timer);
fd882783
BZ		 3594 del_timer_sync(&priv->rateadapter_timer);
3595 cancel_delayed_work(&priv->ieee80211->rate_adapter_wq);
c8d86be3
GKH		 3596 cancel_delayed_work(&priv->ieee80211->hw_wakeup_wq);
3597 cancel_delayed_work(&priv->ieee80211->hw_sleep_wq);
3598 cancel_delayed_work(&priv->ieee80211->hw_dig_wq);
3599 cancel_delayed_work(&priv->ieee80211->tx_pw_wq);
3600 del_timer_sync(&priv->SwAntennaDiversityTimer);
3601 ieee80211_softmac_stop_protocol(priv->ieee80211);
3602 rtl8180_irq_disable(dev);
3603 rtl8180_rtx_disable(dev);
3604 _rtl8180_up(dev);
3605}
3606
c8d86be3
GKH		 3607static void r8180_set_multicast(struct net_device *dev)
3608{
3609 struct r8180_priv *priv = ieee80211_priv(dev);
3610 short promisc;
3611
c8d86be3
GKH		 3612 promisc = (dev->flags & IFF_PROMISC) ? 1:0;
3613
3614 if (promisc != priv->promisc)
3615 rtl8180_restart(dev);
3616
3617 priv->promisc = promisc;
c8d86be3
GKH		 3618}
3619
c8d86be3
GKH		 3620int r8180_set_mac_adr(struct net_device *dev, void *mac)
3621{
3622 struct r8180_priv *priv = ieee80211_priv(dev);
3623 struct sockaddr *addr = mac;
3624
3625 down(&priv->wx_sem);
3626
3627 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3628
3629 if(priv->ieee80211->iw_mode == IW_MODE_MASTER)
3630 memcpy(priv->ieee80211->current_network.bssid, dev->dev_addr, ETH_ALEN);
3631
3632 if (priv->up) {
3633 rtl8180_down(dev);
3634 rtl8180_up(dev);
3635 }
3636
3637 up(&priv->wx_sem);
3638
3639 return 0;
3640}
3641
3642/* based on ipw2200 driver */
3643int rtl8180_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3644{
3645 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 3646 struct iwreq *wrq = (struct iwreq *) rq;
3647 int ret=-1;
fd882783 3648
c8d86be3 3649 switch (cmd) {
fd882783 3650 case RTL_IOCTL_WPA_SUPPLICANT:
c8d86be3
GKH		 3651 ret = ieee80211_wpa_supplicant_ioctl(priv->ieee80211, &wrq->u.data);
3652 return ret;
fd882783 3653 default:
c8d86be3
GKH		 3654 return -EOPNOTSUPP;
3655 }
3656
3657 return -EOPNOTSUPP;
3658}
3659
727ae303
AB		 3660static const struct net_device_ops rtl8180_netdev_ops = {
3661 .ndo_open = rtl8180_open,
3662 .ndo_stop = rtl8180_close,
3663 .ndo_get_stats = rtl8180_stats,
3664 .ndo_tx_timeout = rtl8180_restart,
3665 .ndo_do_ioctl = rtl8180_ioctl,
3666 .ndo_set_multicast_list = r8180_set_multicast,
3667 .ndo_set_mac_address = r8180_set_mac_adr,
3668 .ndo_validate_addr = eth_validate_addr,
3669 .ndo_change_mtu = eth_change_mtu,
df574b8e 3670 .ndo_start_xmit = ieee80211_rtl_xmit,
727ae303 3671};
c8d86be3
GKH		 3672
3673static int __devinit rtl8180_pci_probe(struct pci_dev *pdev,
3674 const struct pci_device_id *id)
3675{
3676 unsigned long ioaddr = 0;
3677 struct net_device *dev = NULL;
3678 struct r8180_priv *priv= NULL;
c8d86be3
GKH		 3679 u8 unit = 0;
3680
c8d86be3 3681 unsigned long pmem_start, pmem_len, pmem_flags;
c8d86be3
GKH		 3682
3683 DMESG("Configuring chip resources");
3684
3685 if( pci_enable_device (pdev) ){
3686 DMESG("Failed to enable PCI device");
3687 return -EIO;
3688 }
3689
3690 pci_set_master(pdev);
c8d86be3
GKH		 3691 pci_set_dma_mask(pdev, 0xffffff00ULL);
3692 pci_set_consistent_dma_mask(pdev,0xffffff00ULL);
3693 dev = alloc_ieee80211(sizeof(struct r8180_priv));
3694 if (!dev)
3695 return -ENOMEM;
3696 priv = ieee80211_priv(dev);
3697 priv->ieee80211 = netdev_priv(dev);
3698
c8d86be3
GKH		 3699 pci_set_drvdata(pdev, dev);
3700 SET_NETDEV_DEV(dev, &pdev->dev);
3701
3702 priv = ieee80211_priv(dev);
fd882783 3703 priv->pdev = pdev;
c8d86be3
GKH		 3704
3705 pmem_start = pci_resource_start(pdev, 1);
3706 pmem_len = pci_resource_len(pdev, 1);
3707 pmem_flags = pci_resource_flags (pdev, 1);
3708
3709 if (!(pmem_flags & IORESOURCE_MEM)) {
3710 DMESG("region #1 not a MMIO resource, aborting");
3711 goto fail;
3712 }
3713
c8d86be3
GKH		 3714 if( ! request_mem_region(pmem_start, pmem_len, RTL8180_MODULE_NAME)) {
3715 DMESG("request_mem_region failed!");
3716 goto fail;
3717 }
3718
c8d86be3
GKH		 3719 ioaddr = (unsigned long)ioremap_nocache( pmem_start, pmem_len);
3720 if( ioaddr == (unsigned long)NULL ){
3721 DMESG("ioremap failed!");
c8d86be3
GKH		 3722 goto fail1;
3723 }
3724
3725 dev->mem_start = ioaddr; // shared mem start
3726 dev->mem_end = ioaddr + pci_resource_len(pdev, 0); // shared mem end
3727
c8d86be3
GKH		 3728 pci_read_config_byte(pdev, 0x05, &unit);
3729 pci_write_config_byte(pdev, 0x05, unit & (~0x04));
c8d86be3
GKH		 3730
3731 dev->irq = pdev->irq;
3732 priv->irq = 0;
3733
727ae303 3734 dev->netdev_ops = &rtl8180_netdev_ops;
c8d86be3 3735 dev->wireless_handlers = &r8180_wx_handlers_def;
c8d86be3 3736
c8d86be3 3737 dev->type=ARPHRD_ETHER;
1994130e 3738 dev->watchdog_timeo = HZ*3;
c8d86be3
GKH		 3739
3740 if (dev_alloc_name(dev, ifname) < 0){
3741 DMESG("Oops: devname already taken! Trying wlan%%d...\n");
3742 ifname = "wlan%d";
c8d86be3
GKH		 3743 dev_alloc_name(dev, ifname);
3744 }
3745
c8d86be3
GKH		 3746 if(rtl8180_init(dev)!=0){
3747 DMESG("Initialization failed");
3748 goto fail1;
3749 }
3750
3751 netif_carrier_off(dev);
3752
3753 register_netdev(dev);
3754
3755 rtl8180_proc_init_one(dev);
3756
3757 DMESG("Driver probe completed\n");
3758 return 0;
c8d86be3 3759fail1:
c8d86be3
GKH		 3760 if( dev->mem_start != (unsigned long)NULL ){
3761 iounmap( (void *)dev->mem_start );
3762 release_mem_region( pci_resource_start(pdev, 1),
3763 pci_resource_len(pdev, 1) );
3764 }
c8d86be3
GKH		 3765fail:
3766 if(dev){
c8d86be3
GKH		 3767 if (priv->irq) {
3768 free_irq(dev->irq, dev);
3769 dev->irq=0;
3770 }
3771 free_ieee80211(dev);
3772 }
3773
3774 pci_disable_device(pdev);
3775
3776 DMESG("wlan driver load failed\n");
3777 pci_set_drvdata(pdev, NULL);
3778 return -ENODEV;
c8d86be3
GKH		 3779}
3780
c8d86be3
GKH		 3781static void __devexit rtl8180_pci_remove(struct pci_dev *pdev)
3782{
3783 struct r8180_priv *priv;
3784 struct net_device *dev = pci_get_drvdata(pdev);
c8d86be3 3785
fd882783 3786 if (dev) {
c8d86be3
GKH		 3787 unregister_netdev(dev);
3788
fd882783 3789 priv = ieee80211_priv(dev);
c8d86be3
GKH		 3790
3791 rtl8180_proc_remove_one(dev);
3792 rtl8180_down(dev);
3793 priv->rf_close(dev);
3794 rtl8180_reset(dev);
c8d86be3 3795 mdelay(10);
c8d86be3
GKH		 3796
3797 if(priv->irq){
c8d86be3
GKH		 3798 DMESG("Freeing irq %d",dev->irq);
3799 free_irq(dev->irq, dev);
3800 priv->irq=0;
c8d86be3
GKH		 3801 }
3802
3803 free_rx_desc_ring(dev);
3804 free_tx_desc_rings(dev);
c8d86be3 3805
c8d86be3
GKH		 3806 if( dev->mem_start != (unsigned long)NULL ){
3807 iounmap( (void *)dev->mem_start );
3808 release_mem_region( pci_resource_start(pdev, 1),
3809 pci_resource_len(pdev, 1) );
3810 }
c8d86be3
GKH		 3811
3812 free_ieee80211(dev);
3813 }
3814 pci_disable_device(pdev);
3815
3816 DMESG("wlan driver removed\n");
3817}
3818
c8d86be3
GKH		 3819/* fun with the built-in ieee80211 stack... */
3820extern int ieee80211_crypto_init(void);
3821extern void ieee80211_crypto_deinit(void);
3822extern int ieee80211_crypto_tkip_init(void);
3823extern void ieee80211_crypto_tkip_exit(void);
3824extern int ieee80211_crypto_ccmp_init(void);
3825extern void ieee80211_crypto_ccmp_exit(void);
3826extern int ieee80211_crypto_wep_init(void);
3827extern void ieee80211_crypto_wep_exit(void);
3828
3829static int __init rtl8180_pci_module_init(void)
3830{
3831 int ret;
3832
3833 ret = ieee80211_crypto_init();
3834 if (ret) {
3835 printk(KERN_ERR "ieee80211_crypto_init() failed %d\n", ret);
3836 return ret;
3837 }
3838 ret = ieee80211_crypto_tkip_init();
3839 if (ret) {
3840 printk(KERN_ERR "ieee80211_crypto_tkip_init() failed %d\n", ret);
3841 return ret;
3842 }
3843 ret = ieee80211_crypto_ccmp_init();
3844 if (ret) {
3845 printk(KERN_ERR "ieee80211_crypto_ccmp_init() failed %d\n", ret);
3846 return ret;
3847 }
3848 ret = ieee80211_crypto_wep_init();
3849 if (ret) {
3850 printk(KERN_ERR "ieee80211_crypto_wep_init() failed %d\n", ret);
3851 return ret;
3852 }
3853
bc568942 3854 printk(KERN_INFO "\nLinux kernel driver for RTL8180 / RTL8185 based WLAN cards\n");
c8d86be3
GKH		 3855 printk(KERN_INFO "Copyright (c) 2004-2005, Andrea Merello\n");
3856 DMESG("Initializing module");
3857 DMESG("Wireless extensions version %d", WIRELESS_EXT);
3858 rtl8180_proc_module_init();
3859
fd882783 3860 if (pci_register_driver(&rtl8180_pci_driver)) {
c8d86be3 3861 DMESG("No device found");
c8d86be3
GKH		 3862 return -ENODEV;
3863 }
3864 return 0;
3865}
3866
c8d86be3
GKH		 3867static void __exit rtl8180_pci_module_exit(void)
3868{
3869 pci_unregister_driver (&rtl8180_pci_driver);
3870 rtl8180_proc_module_remove();
c8d86be3
GKH		 3871 ieee80211_crypto_tkip_exit();
3872 ieee80211_crypto_ccmp_exit();
3873 ieee80211_crypto_wep_exit();
096c55d1 3874 ieee80211_crypto_deinit();
c8d86be3
GKH		 3875 DMESG("Exiting");
3876}
3877
c8d86be3
GKH		 3878void rtl8180_try_wake_queue(struct net_device *dev, int pri)
3879{
3880 unsigned long flags;
3881 short enough_desc;
3882 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3883
3884 spin_lock_irqsave(&priv->tx_lock,flags);
3885 enough_desc = check_nic_enought_desc(dev,pri);
3886 spin_unlock_irqrestore(&priv->tx_lock,flags);
3887
3888 if(enough_desc)
df574b8e 3889 ieee80211_rtl_wake_queue(priv->ieee80211);
c8d86be3
GKH		 3890}
3891
c8d86be3
GKH		 3892void rtl8180_tx_isr(struct net_device *dev, int pri,short error)
3893{
3894 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
c8d86be3
GKH		 3895 u32 *tail; //tail virtual addr
3896 u32 *head; //head virtual addr
3897 u32 *begin;//start of ring virtual addr
3898 u32 *nicv; //nic pointer virtual addr
c8d86be3
GKH		 3899 u32 nic; //nic pointer physical addr
3900 u32 nicbegin;// start of ring physical addr
c8d86be3
GKH		 3901 unsigned long flag;
3902 /* physical addr are ok on 32 bits since we set DMA mask*/
c8d86be3
GKH		 3903 int offs;
3904 int j,i;
3905 int hd;
3906 if (error) priv->stats.txretry++; //tony 20060601
3907 spin_lock_irqsave(&priv->tx_lock,flag);
3908 switch(pri) {
3909 case MANAGE_PRIORITY:
3910 tail = priv->txmapringtail;
3911 begin = priv->txmapring;
3912 head = priv->txmapringhead;
3913 nic = read_nic_dword(dev,TX_MANAGEPRIORITY_RING_ADDR);
3914 nicbegin = priv->txmapringdma;
3915 break;
c8d86be3
GKH		 3916 case BK_PRIORITY:
3917 tail = priv->txbkpringtail;
3918 begin = priv->txbkpring;
3919 head = priv->txbkpringhead;
3920 nic = read_nic_dword(dev,TX_BKPRIORITY_RING_ADDR);
3921 nicbegin = priv->txbkpringdma;
3922 break;
c8d86be3
GKH		 3923 case BE_PRIORITY:
3924 tail = priv->txbepringtail;
3925 begin = priv->txbepring;
3926 head = priv->txbepringhead;
3927 nic = read_nic_dword(dev,TX_BEPRIORITY_RING_ADDR);
3928 nicbegin = priv->txbepringdma;
3929 break;
c8d86be3
GKH		 3930 case VI_PRIORITY:
3931 tail = priv->txvipringtail;
3932 begin = priv->txvipring;
3933 head = priv->txvipringhead;
3934 nic = read_nic_dword(dev,TX_VIPRIORITY_RING_ADDR);
3935 nicbegin = priv->txvipringdma;
3936 break;
c8d86be3
GKH		 3937 case VO_PRIORITY:
3938 tail = priv->txvopringtail;
3939 begin = priv->txvopring;
3940 head = priv->txvopringhead;
3941 nic = read_nic_dword(dev,TX_VOPRIORITY_RING_ADDR);
3942 nicbegin = priv->txvopringdma;
3943 break;
c8d86be3
GKH		 3944 case HI_PRIORITY:
3945 tail = priv->txhpringtail;
3946 begin = priv->txhpring;
3947 head = priv->txhpringhead;
3948 nic = read_nic_dword(dev,TX_HIGHPRIORITY_RING_ADDR);
3949 nicbegin = priv->txhpringdma;
3950 break;
3951
3952 default:
3953 spin_unlock_irqrestore(&priv->tx_lock,flag);
3954 return ;
3955 }
fd882783 3956
c8d86be3
GKH		 3957 nicv = (u32*) ((nic - nicbegin) + (u8*)begin);
3958 if((head <= tail && (nicv > tail || nicv < head)) ||
3959 (head > tail && (nicv > tail && nicv < head))){
c8d86be3 3960 DMESGW("nic has lost pointer");
c8d86be3
GKH		 3961 spin_unlock_irqrestore(&priv->tx_lock,flag);
3962 rtl8180_restart(dev);
3963 return;
3964 }
3965
3966 /* we check all the descriptors between the head and the nic,
bbc9a991 3967 * but not the currently pointed by the nic (the next to be txed)
c8d86be3
GKH		 3968 * and the previous of the pointed (might be in process ??)
3969 */
c8d86be3 3970 offs = (nic - nicbegin);
c8d86be3 3971 offs = offs / 8 /4;
c8d86be3
GKH		 3972 hd = (head - begin) /8;
3973
3974 if(offs >= hd)
3975 j = offs - hd;
3976 else
3977 j = offs + (priv->txringcount -1 -hd);
c8d86be3
GKH		 3978
3979 j-=2;
3980 if(j<0) j=0;
3981
c8d86be3
GKH		 3982 for(i=0;i<j;i++)
3983 {
c8d86be3
GKH		 3984 if((*head) & (1<<31))
3985 break;
3986 if(((*head)&(0x10000000)) != 0){
c8d86be3 3987 priv->CurrRetryCnt += (u16)((*head) & (0x000000ff));
fd882783 3988 if (!error)
c8d86be3 3989 priv->NumTxOkTotal++;
c8d86be3 3990 }
fd882783
BZ		 3991
3992 if (!error)
c8d86be3 3993 priv->NumTxOkBytesTotal += (*(head+3)) & (0x00000fff);
fd882783 3994
c8d86be3
GKH		 3995 *head = *head &~ (1<<31);
3996
3997 if((head - begin)/8 == priv->txringcount-1)
3998 head=begin;
c8d86be3
GKH		 3999 else
4000 head+=8;
4001 }
c8d86be3 4002
c8d86be3
GKH		 4003 /* the head has been moved to the last certainly TXed
4004 * (or at least processed by the nic) packet.
4005 * The driver take forcefully owning of all these packets
4006 * If the packet previous of the nic pointer has been
4007 * processed this doesn't matter: it will be checked
4008 * here at the next round. Anyway if no more packet are
4009 * TXed no memory leak occour at all.
4010 */
4011
4012 switch(pri) {
4013 case MANAGE_PRIORITY:
4014 priv->txmapringhead = head;
fd882783 4015
c8d86be3 4016 if(priv->ack_tx_to_ieee){
c8d86be3 4017 if(rtl8180_is_tx_queue_empty(dev)){
c8d86be3
GKH		 4018 priv->ack_tx_to_ieee = 0;
4019 ieee80211_ps_tx_ack(priv->ieee80211,!error);
4020 }
c8d86be3
GKH		 4021 }
4022 break;
c8d86be3
GKH		 4023 case BK_PRIORITY:
4024 priv->txbkpringhead = head;
4025 break;
c8d86be3
GKH		 4026 case BE_PRIORITY:
4027 priv->txbepringhead = head;
4028 break;
c8d86be3
GKH		 4029 case VI_PRIORITY:
4030 priv->txvipringhead = head;
4031 break;
c8d86be3
GKH		 4032 case VO_PRIORITY:
4033 priv->txvopringhead = head;
4034 break;
c8d86be3
GKH		 4035 case HI_PRIORITY:
4036 priv->txhpringhead = head;
4037 break;
4038 }
4039
c8d86be3 4040 spin_unlock_irqrestore(&priv->tx_lock,flag);
c8d86be3
GKH		 4041}
4042
c8d86be3
GKH		 4043void rtl8180_tx_irq_wq(struct work_struct *work)
4044{
bf6aede7 4045 struct delayed_work *dwork = to_delayed_work(work);
c8d86be3
GKH		 4046 struct ieee80211_device * ieee = (struct ieee80211_device*)
4047 container_of(dwork, struct ieee80211_device, watch_dog_wq);
4048 struct net_device *dev = ieee->dev;
0370453f 4049
c8d86be3
GKH		 4050 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
4051}
4052irqreturn_t rtl8180_interrupt(int irq, void *netdev, struct pt_regs *regs)
4053{
4054 struct net_device *dev = (struct net_device *) netdev;
4055 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
4056 unsigned long flags;
4057 u32 inta;
4058
4059 /* We should return IRQ_NONE, but for now let me keep this */
4060 if(priv->irq_enabled == 0) return IRQ_HANDLED;
4061
4062 spin_lock_irqsave(&priv->irq_th_lock,flags);
4063
c8d86be3
GKH		 4064 //ISR: 4bytes
4065 inta = read_nic_dword(dev, ISR);// & priv->IntrMask;
4066 write_nic_dword(dev,ISR,inta); // reset int situation
c8d86be3
GKH		 4067
4068 priv->stats.shints++;
4069
c8d86be3
GKH		 4070 if(!inta){
4071 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4072 return IRQ_HANDLED;
4073 /*
4074 most probably we can safely return IRQ_NONE,
4075 but for now is better to avoid problems
4076 */
4077 }
4078
fd882783
BZ		 4079 if (inta == 0xffff) {
4080 /* HW disappared */
4081 spin_unlock_irqrestore(&priv->irq_th_lock, flags);
4082 return IRQ_HANDLED;
c8d86be3
GKH		 4083 }
4084
4085 priv->stats.ints++;
c8d86be3
GKH		 4086
4087 if(!netif_running(dev)) {
4088 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4089 return IRQ_HANDLED;
4090 }
4091
fd882783 4092 if (inta & ISR_TimeOut)
c8d86be3 4093 write_nic_dword(dev, TimerInt, 0);
c8d86be3 4094
fd882783 4095 if (inta & ISR_TBDOK)
c8d86be3 4096 priv->stats.txbeacon++;
c8d86be3 4097
fd882783 4098 if (inta & ISR_TBDER)
c8d86be3 4099 priv->stats.txbeaconerr++;
c8d86be3 4100
fd882783 4101 if (inta & IMR_TMGDOK)
c8d86be3 4102 rtl8180_tx_isr(dev,MANAGE_PRIORITY,0);
c8d86be3
GKH		 4103
4104 if(inta & ISR_THPDER){
c8d86be3
GKH		 4105 priv->stats.txhperr++;
4106 rtl8180_tx_isr(dev,HI_PRIORITY,1);
4107 priv->ieee80211->stats.tx_errors++;
4108 }
4109
4110 if(inta & ISR_THPDOK){ //High priority tx ok
c8d86be3
GKH		 4111 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4112 priv->stats.txhpokint++;
4113 rtl8180_tx_isr(dev,HI_PRIORITY,0);
4114 }
4115
4116 if(inta & ISR_RER) {
4117 priv->stats.rxerr++;
c8d86be3 4118 }
c8d86be3
GKH		 4119 if(inta & ISR_TBKDER){ //corresponding to BK_PRIORITY
4120 priv->stats.txbkperr++;
4121 priv->ieee80211->stats.tx_errors++;
c8d86be3
GKH		 4122 rtl8180_tx_isr(dev,BK_PRIORITY,1);
4123 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4124 }
4125
4126 if(inta & ISR_TBEDER){ //corresponding to BE_PRIORITY
4127 priv->stats.txbeperr++;
4128 priv->ieee80211->stats.tx_errors++;
c8d86be3 4129 rtl8180_tx_isr(dev,BE_PRIORITY,1);
c8d86be3
GKH		 4130 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4131 }
c8d86be3
GKH		 4132 if(inta & ISR_TNPDER){ //corresponding to VO_PRIORITY
4133 priv->stats.txnperr++;
4134 priv->ieee80211->stats.tx_errors++;
c8d86be3 4135 rtl8180_tx_isr(dev,NORM_PRIORITY,1);
c8d86be3 4136 rtl8180_try_wake_queue(dev, NORM_PRIORITY);
c8d86be3
GKH		 4137 }
4138
4139 if(inta & ISR_TLPDER){ //corresponding to VI_PRIORITY
4140 priv->stats.txlperr++;
4141 priv->ieee80211->stats.tx_errors++;
c8d86be3 4142 rtl8180_tx_isr(dev,LOW_PRIORITY,1);
c8d86be3
GKH		 4143 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4144 }
4145
4146 if(inta & ISR_ROK){
c8d86be3
GKH		 4147 priv->stats.rxint++;
4148 tasklet_schedule(&priv->irq_rx_tasklet);
4149 }
4150
4151 if(inta & ISR_RQoSOK ){
c8d86be3
GKH		 4152 priv->stats.rxint++;
4153 tasklet_schedule(&priv->irq_rx_tasklet);
4154 }
4155 if(inta & ISR_BcnInt) {
c8d86be3
GKH		 4156 rtl8180_prepare_beacon(dev);
4157 }
4158
4159 if(inta & ISR_RDU){
c8d86be3
GKH		 4160 DMESGW("No RX descriptor available");
4161 priv->stats.rxrdu++;
c8d86be3 4162 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3 4163 }
fd882783 4164
c8d86be3 4165 if(inta & ISR_RXFOVW){
c8d86be3
GKH		 4166 priv->stats.rxoverflow++;
4167 tasklet_schedule(&priv->irq_rx_tasklet);
c8d86be3
GKH		 4168 }
4169
fd882783
BZ		 4170 if (inta & ISR_TXFOVW)
4171 priv->stats.txoverflow++;
c8d86be3
GKH		 4172
4173 if(inta & ISR_TNPDOK){ //Normal priority tx ok
c8d86be3 4174 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH		 4175 priv->stats.txnpokint++;
4176 rtl8180_tx_isr(dev,NORM_PRIORITY,0);
4177 }
4178
4179 if(inta & ISR_TLPDOK){ //Low priority tx ok
c8d86be3 4180 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
c8d86be3
GKH		 4181 priv->stats.txlpokint++;
4182 rtl8180_tx_isr(dev,LOW_PRIORITY,0);
4183 rtl8180_try_wake_queue(dev, LOW_PRIORITY);
4184 }
4185
c8d86be3
GKH		 4186 if(inta & ISR_TBKDOK){ //corresponding to BK_PRIORITY
4187 priv->stats.txbkpokint++;
c8d86be3
GKH		 4188 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4189 rtl8180_tx_isr(dev,BK_PRIORITY,0);
4190 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4191 }
4192
4193 if(inta & ISR_TBEDOK){ //corresponding to BE_PRIORITY
4194 priv->stats.txbeperr++;
c8d86be3
GKH		 4195 priv->link_detect.NumTxOkInPeriod++; //YJ,add,080828
4196 rtl8180_tx_isr(dev,BE_PRIORITY,0);
4197 rtl8180_try_wake_queue(dev, BE_PRIORITY);
4198 }
c8d86be3
GKH		 4199 force_pci_posting(dev);
4200 spin_unlock_irqrestore(&priv->irq_th_lock,flags);
4201
4202 return IRQ_HANDLED;
4203}
4204
c8d86be3
GKH		 4205void rtl8180_irq_rx_tasklet(struct r8180_priv* priv)
4206{
c8d86be3 4207 rtl8180_rx(priv->dev);
c8d86be3
GKH		 4208}
4209
c8d86be3
GKH		 4210void GPIOChangeRFWorkItemCallBack(struct work_struct *work)
4211{
c8d86be3
GKH		 4212 struct ieee80211_device *ieee = container_of(work, struct ieee80211_device, GPIOChangeRFWorkItem.work);
4213 struct net_device *dev = ieee->dev;
4214 struct r8180_priv *priv = ieee80211_priv(dev);
c8d86be3
GKH		 4215 u8 btPSR;
4216 u8 btConfig0;
4217 RT_RF_POWER_STATE eRfPowerStateToSet;
4218 bool bActuallySet=false;
4219
4220 char *argv[3];
4221 static char *RadioPowerPath = "/etc/acpi/events/RadioPower.sh";
4222 static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL};
4223 static int readf_count = 0;
c8d86be3 4224
c8d86be3
GKH		 4225 if(readf_count % 10 == 0)
4226 priv->PowerProfile = read_acadapter_file("/proc/acpi/ac_adapter/AC0/state");
4227
4228 readf_count = (readf_count+1)%0xffff;
1994130e 4229 /* We should turn off LED before polling FF51[4]. */
c8d86be3 4230
1994130e
LF		 4231 /* Turn off LED. */
4232 btPSR = read_nic_byte(dev, PSR);
4233 write_nic_byte(dev, PSR, (btPSR & ~BIT3));
c8d86be3 4234
1994130e
LF		 4235 /* It need to delay 4us suggested by Jong, 2008-01-16 */
4236 udelay(4);
c8d86be3 4237
1994130e
LF		 4238 /* HW radio On/Off according to the value of FF51[4](config0) */
4239 btConfig0 = btPSR = read_nic_byte(dev, CONFIG0);
c8d86be3 4240
1994130e
LF		 4241 /* Turn on LED. */
4242 write_nic_byte(dev, PSR, btPSR | BIT3);
c8d86be3 4243
1994130e 4244 eRfPowerStateToSet = (btConfig0 & BIT4) ? eRfOn : eRfOff;
c8d86be3 4245
1994130e
LF		 4246 if ((priv->ieee80211->bHwRadioOff == true) &&
4247 (eRfPowerStateToSet == eRfOn)) {
4248 priv->ieee80211->bHwRadioOff = false;
4249 bActuallySet = true;
4250 } else if ((priv->ieee80211->bHwRadioOff == false) &&
4251 (eRfPowerStateToSet == eRfOff)) {
4252 priv->ieee80211->bHwRadioOff = true;
4253 bActuallySet = true;
4254 }
c8d86be3 4255
1994130e
LF		 4256 if (bActuallySet) {
4257 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
4258
4259 /* To update the UI status for Power status changed */
4260 if (priv->ieee80211->bHwRadioOff == true)
4261 argv[1] = "RFOFF";
4262 else
4263 argv[1] = "RFON";
4264 argv[0] = RadioPowerPath;
4265 argv[2] = NULL;
4266
4267 call_usermodehelper(RadioPowerPath, argv, envp, 1);
4268 }
c8d86be3
GKH		 4269}
4270
4271static u8 read_acadapter_file(char *filename)
4272{
c8d86be3
GKH		 4273 return 0;
4274}
4275
c8d86be3
GKH		 4276module_init(rtl8180_pci_module_init);
4277module_exit(rtl8180_pci_module_exit);
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