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[SCSI] qla2xxx: Add QoS support.
[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
01e58d8e 3 * Copyright (c) 2003-2008 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
2c96d8d0 10#include <linux/vmalloc.h>
1da177e4
LT		 11#include <asm/uaccess.h>
12
1da177e4
LT		 13/*
14 * NVRAM support routines
15 */
16
17/**
fa2a1ce5 18 * qla2x00_lock_nvram_access() -
1da177e4
LT		 19 * @ha: HA context
20 */
a824ebb3 21static void
7b867cf7 22qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 23{
24 uint16_t data;
3d71644c 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48}
49
50/**
fa2a1ce5 51 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 52 * @ha: HA context
53 */
a824ebb3 54static void
7b867cf7 55qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 56{
3d71644c 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63}
64
7b867cf7
AC		 65/**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70static void
71qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72{
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85}
86
87/**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102static uint16_t
103qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104{
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140}
141
142
1da177e4
LT		 143/**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
a824ebb3 151static uint16_t
7b867cf7 152qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 153{
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162}
163
7b867cf7
AC		 164/**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168static void
169qla2x00_nv_deselect(struct qla_hw_data *ha)
170{
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176}
177
1da177e4
LT		 178/**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
a824ebb3 184static void
7b867cf7 185qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 186{
187 int count;
188 uint16_t word;
45aeaf1e 189 uint32_t nv_cmd, wait_cnt;
3d71644c 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 219 wait_cnt = NVR_WAIT_CNT;
1da177e4 220 do {
45aeaf1e 221 if (!--wait_cnt) {
7640335e
AV		 222 DEBUG9_10(qla_printk(KERN_WARNING, ha,
223 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 224 break;
225 }
1da177e4
LT		 226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238}
239
459c5378 240static int
7b867cf7
AC		 241qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
459c5378
AV		 243{
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297}
298
459c5378
AV		 299/**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303static int
7b867cf7 304qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 305{
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 308 uint32_t word, wait_cnt;
459c5378
AV		 309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 316 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 349 wait_cnt = NVR_WAIT_CNT;
459c5378 350 do {
45aeaf1e 351 if (!--wait_cnt) {
7640335e 352 DEBUG9_10(qla_printk(KERN_WARNING, ha,
7b867cf7 353 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 354 break;
355 }
459c5378
AV		 356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
45aeaf1e
RA		 360 if (wait_cnt)
361 ret = QLA_SUCCESS;
459c5378 362 } else
45aeaf1e 363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 364
365 return ret;
366}
367
368static void
7b867cf7 369qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 370{
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 372 uint32_t word, wait_cnt;
459c5378
AV		 373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 408 wait_cnt = NVR_WAIT_CNT;
459c5378 409 do {
45aeaf1e 410 if (!--wait_cnt) {
7640335e
AV		 411 DEBUG9_10(qla_printk(KERN_WARNING, ha,
412 "NVRAM didn't go ready...\n"));
45aeaf1e
RA		 413 break;
414 }
459c5378
AV		 415 NVRAM_DELAY();
416 word = RD_REG_WORD(&reg->nvram);
417 } while ((word & NVR_DATA_IN) == 0);
418}
419
420
421/*****************************************************************************/
422/* Flash Manipulation Routines */
423/*****************************************************************************/
424
338c9161
AV		 425#define OPTROM_BURST_SIZE 0x1000
426#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
427
459c5378 428static inline uint32_t
3a03eb79 429flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 430{
3a03eb79 431 return ha->flash_conf_off | faddr;
459c5378
AV		 432}
433
434static inline uint32_t
3a03eb79 435flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 436{
3a03eb79 437 return ha->flash_data_off | faddr;
459c5378
AV		 438}
439
440static inline uint32_t
3a03eb79 441nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 442{
3a03eb79 443 return ha->nvram_conf_off | naddr;
459c5378
AV		 444}
445
446static inline uint32_t
3a03eb79 447nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 448{
3a03eb79 449 return ha->nvram_data_off | naddr;
459c5378
AV		 450}
451
e5f82ab8 452static uint32_t
7b867cf7 453qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 454{
455 int rval;
456 uint32_t cnt, data;
457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458
459 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
460 /* Wait for READ cycle to complete. */
461 rval = QLA_SUCCESS;
462 for (cnt = 3000;
463 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
464 rval == QLA_SUCCESS; cnt--) {
465 if (cnt)
466 udelay(10);
467 else
468 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 469 cond_resched();
459c5378
AV		 470 }
471
472 /* TODO: What happens if we time out? */
473 data = 0xDEADDEAD;
474 if (rval == QLA_SUCCESS)
475 data = RD_REG_DWORD(&reg->flash_data);
476
477 return data;
478}
479
480uint32_t *
7b867cf7 481qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 482 uint32_t dwords)
483{
484 uint32_t i;
3a03eb79
AV		 485 struct qla_hw_data *ha = vha->hw;
486
459c5378
AV		 487 /* Dword reads to flash. */
488 for (i = 0; i < dwords; i++, faddr++)
3a03eb79
AV		 489 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
490 flash_data_addr(ha, faddr)));
459c5378 491
459c5378
AV		 492 return dwptr;
493}
494
e5f82ab8 495static int
7b867cf7 496qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 497{
498 int rval;
499 uint32_t cnt;
500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
501
502 WRT_REG_DWORD(&reg->flash_data, data);
503 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
504 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
505 /* Wait for Write cycle to complete. */
506 rval = QLA_SUCCESS;
507 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
508 rval == QLA_SUCCESS; cnt--) {
509 if (cnt)
510 udelay(10);
511 else
512 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 513 cond_resched();
459c5378
AV		 514 }
515 return rval;
516}
517
e5f82ab8 518static void
7b867cf7 519qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 520 uint8_t *flash_id)
521{
522 uint32_t ids;
523
3a03eb79 524 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
459c5378
AV		 525 *man_id = LSB(ids);
526 *flash_id = MSB(ids);
45aeaf1e
RA		 527
528 /* Check if man_id and flash_id are valid. */
529 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
530 /* Read information using 0x9f opcode
531 * Device ID, Mfg ID would be read in the format:
532 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
533 * Example: ATMEL 0x00 01 45 1F
534 * Extract MFG and Dev ID from last two bytes.
535 */
3a03eb79 536 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
45aeaf1e
RA		 537 *man_id = LSB(ids);
538 *flash_id = MSB(ids);
539 }
459c5378
AV		 540}
541
c00d8994 542static int
7b867cf7 543qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 544{
545 const char *loc, *locations[] = { "DEF", "PCI" };
546 uint32_t pcihdr, pcids;
547 uint32_t *dcode;
548 uint8_t *buf, *bcode, last_image;
549 uint16_t cnt, chksum, *wptr;
550 struct qla_flt_location *fltl;
7b867cf7 551 struct qla_hw_data *ha = vha->hw;
73208dfd 552 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 553
554 /*
555 * FLT-location structure resides after the last PCI region.
556 */
557
558 /* Begin with sane defaults. */
559 loc = locations[0];
3a03eb79
AV		 560 *start = 0;
561 if (IS_QLA24XX_TYPE(ha))
562 *start = FA_FLASH_LAYOUT_ADDR_24;
563 else if (IS_QLA25XX(ha))
564 *start = FA_FLASH_LAYOUT_ADDR;
565 else if (IS_QLA81XX(ha))
566 *start = FA_FLASH_LAYOUT_ADDR_81;
c00d8994 567 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 568 buf = (uint8_t *)req->ring;
569 dcode = (uint32_t *)req->ring;
c00d8994
AV		 570 pcihdr = 0;
571 last_image = 1;
572 do {
573 /* Verify PCI expansion ROM header. */
7b867cf7 574 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 575 bcode = buf + (pcihdr % 4);
576 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
577 goto end;
578
579 /* Locate PCI data structure. */
580 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 581 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 582 bcode = buf + (pcihdr % 4);
583
584 /* Validate signature of PCI data structure. */
585 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
586 bcode[0x2] != 'I' || bcode[0x3] != 'R')
587 goto end;
588
589 last_image = bcode[0x15] & BIT_7;
590
591 /* Locate next PCI expansion ROM. */
592 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
593 } while (!last_image);
594
595 /* Now verify FLT-location structure. */
7b867cf7
AC		 596 fltl = (struct qla_flt_location *)req->ring;
597 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 598 sizeof(struct qla_flt_location) >> 2);
599 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
600 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
601 goto end;
602
7b867cf7 603 wptr = (uint16_t *)req->ring;
c00d8994
AV		 604 cnt = sizeof(struct qla_flt_location) >> 1;
605 for (chksum = 0; cnt; cnt--)
606 chksum += le16_to_cpu(*wptr++);
607 if (chksum) {
608 qla_printk(KERN_ERR, ha,
609 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
610 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
611 return QLA_FUNCTION_FAILED;
612 }
613
614 /* Good data. Use specified location. */
615 loc = locations[1];
79c13a74
HZ		 616 *start = (le16_to_cpu(fltl->start_hi) << 16 |
617 le16_to_cpu(fltl->start_lo)) >> 2;
c00d8994
AV		 618end:
619 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
620 return QLA_SUCCESS;
621}
622
623static void
7b867cf7 624qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 625{
626 const char *loc, *locations[] = { "DEF", "FLT" };
3a03eb79
AV		 627 const uint32_t def_fw[] =
628 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
629 const uint32_t def_boot[] =
630 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
631 const uint32_t def_vpd_nvram[] =
632 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
3d79038f
AV		 633 const uint32_t def_vpd0[] =
634 { 0, 0, FA_VPD0_ADDR_81 };
635 const uint32_t def_vpd1[] =
636 { 0, 0, FA_VPD1_ADDR_81 };
637 const uint32_t def_nvram0[] =
638 { 0, 0, FA_NVRAM0_ADDR_81 };
639 const uint32_t def_nvram1[] =
640 { 0, 0, FA_NVRAM1_ADDR_81 };
3a03eb79
AV		 641 const uint32_t def_fdt[] =
642 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
643 FA_FLASH_DESCR_ADDR_81 };
644 const uint32_t def_npiv_conf0[] =
645 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
646 FA_NPIV_CONF0_ADDR_81 };
647 const uint32_t def_npiv_conf1[] =
648 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
649 FA_NPIV_CONF1_ADDR_81 };
650 uint32_t def;
c00d8994
AV		 651 uint16_t *wptr;
652 uint16_t cnt, chksum;
653 uint32_t start;
654 struct qla_flt_header *flt;
655 struct qla_flt_region *region;
7b867cf7 656 struct qla_hw_data *ha = vha->hw;
73208dfd 657 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 658
659 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 660 wptr = (uint16_t *)req->ring;
661 flt = (struct qla_flt_header *)req->ring;
c00d8994 662 region = (struct qla_flt_region *)&flt[1];
7b867cf7 663 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 664 flt_addr << 2, OPTROM_BURST_SIZE);
665 if (*wptr == __constant_cpu_to_le16(0xffff))
666 goto no_flash_data;
667 if (flt->version != __constant_cpu_to_le16(1)) {
668 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
669 "version=0x%x length=0x%x checksum=0x%x.\n",
670 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
671 le16_to_cpu(flt->checksum)));
672 goto no_flash_data;
673 }
674
675 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
676 for (chksum = 0; cnt; cnt--)
677 chksum += le16_to_cpu(*wptr++);
678 if (chksum) {
679 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
680 "version=0x%x length=0x%x checksum=0x%x.\n",
681 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
682 chksum));
683 goto no_flash_data;
684 }
685
686 loc = locations[1];
687 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
688 for ( ; cnt; cnt--, region++) {
689 /* Store addresses as DWORD offsets. */
690 start = le32_to_cpu(region->start) >> 2;
691
692 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
693 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
694 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
695
9088608e 696 switch (le32_to_cpu(region->code) & 0xff) {
c00d8994
AV		 697 case FLT_REG_FW:
698 ha->flt_region_fw = start;
699 break;
700 case FLT_REG_BOOT_CODE:
701 ha->flt_region_boot = start;
702 break;
703 case FLT_REG_VPD_0:
704 ha->flt_region_vpd_nvram = start;
3d79038f
AV		 705 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
706 ha->flt_region_vpd = start;
707 break;
708 case FLT_REG_VPD_1:
709 if (PCI_FUNC(ha->pdev->devfn) & 1)
710 ha->flt_region_vpd = start;
711 break;
712 case FLT_REG_NVRAM_0:
713 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
714 ha->flt_region_nvram = start;
715 break;
716 case FLT_REG_NVRAM_1:
717 if (PCI_FUNC(ha->pdev->devfn) & 1)
718 ha->flt_region_nvram = start;
c00d8994
AV		 719 break;
720 case FLT_REG_FDT:
721 ha->flt_region_fdt = start;
722 break;
272976ca 723 case FLT_REG_NPIV_CONF_0:
3a03eb79 724 if (!(PCI_FUNC(ha->pdev->devfn) & 1))
272976ca
AV		 725 ha->flt_region_npiv_conf = start;
726 break;
727 case FLT_REG_NPIV_CONF_1:
3a03eb79 728 if (PCI_FUNC(ha->pdev->devfn) & 1)
272976ca
AV		 729 ha->flt_region_npiv_conf = start;
730 break;
c00d8994
AV		 731 }
732 }
733 goto done;
734
735no_flash_data:
736 /* Use hardcoded defaults. */
737 loc = locations[0];
3a03eb79
AV		 738 def = 0;
739 if (IS_QLA24XX_TYPE(ha))
740 def = 0;
741 else if (IS_QLA25XX(ha))
742 def = 1;
743 else if (IS_QLA81XX(ha))
744 def = 2;
745 ha->flt_region_fw = def_fw[def];
746 ha->flt_region_boot = def_boot[def];
747 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
3d79038f
AV		 748 ha->flt_region_vpd = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
749 def_vpd0[def]: def_vpd1[def];
750 ha->flt_region_nvram = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
751 def_nvram0[def]: def_nvram1[def];
3a03eb79
AV		 752 ha->flt_region_fdt = def_fdt[def];
753 ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
754 def_npiv_conf0[def]: def_npiv_conf1[def];
c00d8994
AV		 755done:
756 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
3d79038f
AV		 757 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
758 "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
759 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
1ded85e2 760 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
c00d8994
AV		 761}
762
763static void
7b867cf7 764qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 765{
821b3996 766#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 767#define FLASH_BLK_SIZE_32K 0x8000
768#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 769 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 770 uint16_t cnt, chksum;
771 uint16_t *wptr;
772 struct qla_fdt_layout *fdt;
773 uint8_t man_id, flash_id;
c00d8994 774 uint16_t mid, fid;
7b867cf7 775 struct qla_hw_data *ha = vha->hw;
73208dfd 776 struct req_que *req = ha->req_q_map[0];
7d232c74 777
7b867cf7
AC		 778 wptr = (uint16_t *)req->ring;
779 fdt = (struct qla_fdt_layout *)req->ring;
780 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 781 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 782 if (*wptr == __constant_cpu_to_le16(0xffff))
783 goto no_flash_data;
784 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
785 fdt->sig[3] != 'D')
786 goto no_flash_data;
787
788 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
789 cnt++)
790 chksum += le16_to_cpu(*wptr++);
791 if (chksum) {
792 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
793 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
794 le16_to_cpu(fdt->version)));
795 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
796 goto no_flash_data;
797 }
798
c00d8994
AV		 799 loc = locations[1];
800 mid = le16_to_cpu(fdt->man_id);
801 fid = le16_to_cpu(fdt->id);
7d232c74 802 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
3a03eb79 803 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
7d232c74
AV		 804 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
805 if (fdt->unprotect_sec_cmd) {
3a03eb79 806 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
7d232c74
AV		 807 fdt->unprotect_sec_cmd);
808 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3a03eb79
AV		 809 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
810 flash_conf_addr(ha, 0x0336);
7d232c74 811 }
c00d8994 812 goto done;
7d232c74 813no_flash_data:
c00d8994 814 loc = locations[0];
7d232c74 815 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 816 mid = man_id;
817 fid = flash_id;
7d232c74 818 ha->fdt_wrt_disable = 0x9c;
3a03eb79 819 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
7d232c74
AV		 820 switch (man_id) {
821 case 0xbf: /* STT flash. */
822 if (flash_id == 0x8e)
823 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
824 else
825 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
826
827 if (flash_id == 0x80)
3a03eb79 828 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
7d232c74
AV		 829 break;
830 case 0x13: /* ST M25P80. */
831 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
832 break;
833 case 0x1f: /* Atmel 26DF081A. */
821b3996 834 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
3a03eb79
AV		 835 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
836 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
837 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
7d232c74
AV		 838 break;
839 default:
840 /* Default to 64 kb sector size. */
841 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
842 break;
843 }
c00d8994
AV		 844done:
845 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
821b3996 846 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
7d232c74 847 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
821b3996 848 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
7d232c74
AV		 849 ha->fdt_block_size));
850}
851
c00d8994 852int
7b867cf7 853qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 854{
855 int ret;
856 uint32_t flt_addr;
7b867cf7 857 struct qla_hw_data *ha = vha->hw;
c00d8994 858
3a03eb79 859 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
c00d8994
AV		 860 return QLA_SUCCESS;
861
7b867cf7 862 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 863 if (ret != QLA_SUCCESS)
864 return ret;
865
7b867cf7
AC		 866 qla2xxx_get_flt_info(vha, flt_addr);
867 qla2xxx_get_fdt_info(vha);
c00d8994
AV		 868
869 return QLA_SUCCESS;
870}
871
272976ca 872void
7b867cf7 873qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 874{
875#define NPIV_CONFIG_SIZE (16*1024)
876 void *data;
877 uint16_t *wptr;
878 uint16_t cnt, chksum;
73208dfd 879 int i;
272976ca
AV		 880 struct qla_npiv_header hdr;
881 struct qla_npiv_entry *entry;
7b867cf7 882 struct qla_hw_data *ha = vha->hw;
272976ca 883
3a03eb79 884 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
272976ca
AV		 885 return;
886
7b867cf7 887 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 888 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
889 if (hdr.version == __constant_cpu_to_le16(0xffff))
890 return;
891 if (hdr.version != __constant_cpu_to_le16(1)) {
892 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
893 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
894 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
895 le16_to_cpu(hdr.checksum)));
896 return;
897 }
898
899 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
900 if (!data) {
901 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
902 "allocate memory.\n"));
903 return;
904 }
905
7b867cf7 906 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 907 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
908
909 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
910 sizeof(struct qla_npiv_entry)) >> 1;
911 for (wptr = data, chksum = 0; cnt; cnt--)
912 chksum += le16_to_cpu(*wptr++);
913 if (chksum) {
914 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
915 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
916 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
917 chksum));
918 goto done;
919 }
920
921 entry = data + sizeof(struct qla_npiv_header);
922 cnt = le16_to_cpu(hdr.entries);
2afa19a9 923 ha->flex_port_count = cnt;
73208dfd 924 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 925 uint16_t flags;
926 struct fc_vport_identifiers vid;
927 struct fc_vport *vport;
928
929 flags = le16_to_cpu(entry->flags);
930 if (flags == 0xffff)
931 continue;
932 if ((flags & BIT_0) == 0)
933 continue;
934
935 memset(&vid, 0, sizeof(vid));
936 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
937 vid.vport_type = FC_PORTTYPE_NPIV;
938 vid.disable = false;
939 vid.port_name = wwn_to_u64(entry->port_name);
940 vid.node_name = wwn_to_u64(entry->node_name);
941
73208dfd
AC		 942 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
943
272976ca 944 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
73208dfd
AC		 945 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
946 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
947 entry->q_qos, entry->f_qos));
948
949 if (i < QLA_PRECONFIG_VPORTS) {
950 vport = fc_vport_create(vha->host, 0, &vid);
951 if (!vport)
952 qla_printk(KERN_INFO, ha,
953 "NPIV-Config: Failed to create vport [%02x]: "
954 "wwpn=%llx wwnn=%llx.\n", cnt,
955 vid.port_name, vid.node_name);
956 }
272976ca
AV		 957 }
958done:
959 kfree(data);
73208dfd 960 ha->npiv_info = NULL;
272976ca
AV		 961}
962
1d2874de
JC		 963static int
964qla24xx_unprotect_flash(scsi_qla_host_t *vha)
cb8dacbf 965{
1d2874de 966 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 967 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
968
1d2874de
JC		 969 if (ha->flags.fac_supported)
970 return qla81xx_fac_do_write_enable(vha, 1);
971
cb8dacbf
AV		 972 /* Enable flash write. */
973 WRT_REG_DWORD(&reg->ctrl_status,
974 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
975 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
976
7d232c74 977 if (!ha->fdt_wrt_disable)
1d2874de 978 goto done;
7d232c74 979
b872ca40 980 /* Disable flash write-protection, first clear SR protection bit */
3a03eb79 981 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
b872ca40 982 /* Then write zero again to clear remaining SR bits.*/
3a03eb79 983 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1d2874de
JC		 984done:
985 return QLA_SUCCESS;
cb8dacbf
AV		 986}
987
1d2874de
JC		 988static int
989qla24xx_protect_flash(scsi_qla_host_t *vha)
cb8dacbf
AV		 990{
991 uint32_t cnt;
1d2874de 992 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 993 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
994
1d2874de
JC		 995 if (ha->flags.fac_supported)
996 return qla81xx_fac_do_write_enable(vha, 0);
997
7d232c74
AV		 998 if (!ha->fdt_wrt_disable)
999 goto skip_wrt_protect;
1000
cb8dacbf 1001 /* Enable flash write-protection and wait for completion. */
3a03eb79 1002 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
7d232c74 1003 ha->fdt_wrt_disable);
cb8dacbf 1004 for (cnt = 300; cnt &&
3a03eb79 1005 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
cb8dacbf
AV		 1006 cnt--) {
1007 udelay(10);
1008 }
1009
7d232c74 1010skip_wrt_protect:
cb8dacbf
AV		 1011 /* Disable flash write. */
1012 WRT_REG_DWORD(&reg->ctrl_status,
1013 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1014 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1d2874de
JC		 1015
1016 return QLA_SUCCESS;
1017}
1018
1019static int
1020qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1021{
1022 struct qla_hw_data *ha = vha->hw;
1023 uint32_t start, finish;
1024
1025 if (ha->flags.fac_supported) {
1026 start = fdata >> 2;
1027 finish = start + (ha->fdt_block_size >> 2) - 1;
1028 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1029 start), flash_data_addr(ha, finish));
1030 }
1031
1032 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1033 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1034 ((fdata >> 16) & 0xff));
cb8dacbf
AV		 1035}
1036
e5f82ab8 1037static int
7b867cf7 1038qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 1039 uint32_t dwords)
1040{
1041 int ret;
7c283177 1042 uint32_t liter;
7d232c74 1043 uint32_t sec_mask, rest_addr;
85d0acbb 1044 uint32_t fdata;
338c9161
AV		 1045 dma_addr_t optrom_dma;
1046 void *optrom = NULL;
7b867cf7 1047 struct qla_hw_data *ha = vha->hw;
459c5378 1048
338c9161 1049 /* Prepare burst-capable write on supported ISPs. */
3a03eb79 1050 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
338c9161
AV		 1051 dwords > OPTROM_BURST_DWORDS) {
1052 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1053 &optrom_dma, GFP_KERNEL);
1054 if (!optrom) {
1055 qla_printk(KERN_DEBUG, ha,
1056 "Unable to allocate memory for optrom burst write "
1057 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1058 }
1059 }
1060
7d232c74 1061 rest_addr = (ha->fdt_block_size >> 2) - 1;
85d0acbb 1062 sec_mask = ~rest_addr;
459c5378 1063
1d2874de
JC		 1064 ret = qla24xx_unprotect_flash(vha);
1065 if (ret != QLA_SUCCESS) {
1066 qla_printk(KERN_WARNING, ha,
1067 "Unable to unprotect flash for update.\n");
1068 goto done;
1069 }
459c5378 1070
338c9161 1071 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
85d0acbb 1072 fdata = (faddr & sec_mask) << 2;
45aeaf1e 1073
338c9161 1074 /* Are we at the beginning of a sector? */
85d0acbb 1075 if ((faddr & rest_addr) == 0) {
7d232c74
AV		 1076 /* Do sector unprotect. */
1077 if (ha->fdt_unprotect_sec_cmd)
338c9161 1078 qla24xx_write_flash_dword(ha,
7d232c74 1079 ha->fdt_unprotect_sec_cmd,
338c9161 1080 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1081 0xff0000) | ((fdata >> 16) & 0xff));
1d2874de 1082 ret = qla24xx_erase_sector(vha, fdata);
338c9161 1083 if (ret != QLA_SUCCESS) {
7640335e
AV		 1084 DEBUG9(qla_printk(KERN_WARNING, ha,
1085 "Unable to erase sector: address=%x.\n",
1086 faddr));
338c9161 1087 break;
459c5378 1088 }
338c9161
AV		 1089 }
1090
1091 /* Go with burst-write. */
94d6a2b3 1092 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161 1093 /* Copy data to DMA'ble buffer. */
7c283177 1094 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
338c9161 1095
7b867cf7 1096 ret = qla2x00_load_ram(vha, optrom_dma,
3a03eb79 1097 flash_data_addr(ha, faddr),
338c9161 1098 OPTROM_BURST_DWORDS);
459c5378 1099 if (ret != QLA_SUCCESS) {
338c9161
AV		 1100 qla_printk(KERN_WARNING, ha,
1101 "Unable to burst-write optrom segment "
1102 "(%x/%x/%llx).\n", ret,
3a03eb79 1103 flash_data_addr(ha, faddr),
875baf3c 1104 (unsigned long long)optrom_dma);
338c9161
AV		 1105 qla_printk(KERN_WARNING, ha,
1106 "Reverting to slow-write.\n");
1107
1108 dma_free_coherent(&ha->pdev->dev,
1109 OPTROM_BURST_SIZE, optrom, optrom_dma);
1110 optrom = NULL;
1111 } else {
1112 liter += OPTROM_BURST_DWORDS - 1;
1113 faddr += OPTROM_BURST_DWORDS - 1;
1114 dwptr += OPTROM_BURST_DWORDS - 1;
1115 continue;
459c5378 1116 }
338c9161 1117 }
45aeaf1e 1118
338c9161 1119 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1120 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
338c9161
AV		 1121 if (ret != QLA_SUCCESS) {
1122 DEBUG9(printk("%s(%ld) Unable to program flash "
1123 "address=%x data=%x.\n", __func__,
7b867cf7 1124 vha->host_no, faddr, *dwptr));
338c9161 1125 break;
459c5378 1126 }
338c9161 1127
7d232c74
AV		 1128 /* Do sector protect. */
1129 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1130 ((faddr & rest_addr) == rest_addr))
1131 qla24xx_write_flash_dword(ha,
7d232c74 1132 ha->fdt_protect_sec_cmd,
338c9161
AV		 1133 (fdata & 0xff00) | ((fdata << 16) &
1134 0xff0000) | ((fdata >> 16) & 0xff));
1135 }
459c5378 1136
1d2874de
JC		 1137 ret = qla24xx_protect_flash(vha);
1138 if (ret != QLA_SUCCESS)
1139 qla_printk(KERN_WARNING, ha,
1140 "Unable to protect flash after update.\n");
1141done:
338c9161
AV		 1142 if (optrom)
1143 dma_free_coherent(&ha->pdev->dev,
1144 OPTROM_BURST_SIZE, optrom, optrom_dma);
1145
459c5378
AV		 1146 return ret;
1147}
1148
1149uint8_t *
7b867cf7 1150qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1151 uint32_t bytes)
1152{
1153 uint32_t i;
1154 uint16_t *wptr;
7b867cf7 1155 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1156
1157 /* Word reads to NVRAM via registers. */
1158 wptr = (uint16_t *)buf;
1159 qla2x00_lock_nvram_access(ha);
1160 for (i = 0; i < bytes >> 1; i++, naddr++)
1161 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1162 naddr));
1163 qla2x00_unlock_nvram_access(ha);
1164
1165 return buf;
1166}
1167
1168uint8_t *
7b867cf7 1169qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1170 uint32_t bytes)
1171{
1172 uint32_t i;
1173 uint32_t *dwptr;
3a03eb79 1174 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1175
1176 /* Dword reads to flash. */
1177 dwptr = (uint32_t *)buf;
1178 for (i = 0; i < bytes >> 2; i++, naddr++)
3a03eb79
AV		 1179 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1180 nvram_data_addr(ha, naddr)));
459c5378 1181
459c5378
AV		 1182 return buf;
1183}
1184
1185int
7b867cf7 1186qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1187 uint32_t bytes)
1188{
1189 int ret, stat;
1190 uint32_t i;
1191 uint16_t *wptr;
2c96d8d0 1192 unsigned long flags;
7b867cf7 1193 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1194
1195 ret = QLA_SUCCESS;
1196
2c96d8d0 1197 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1198 qla2x00_lock_nvram_access(ha);
1199
1200 /* Disable NVRAM write-protection. */
1201 stat = qla2x00_clear_nvram_protection(ha);
1202
1203 wptr = (uint16_t *)buf;
1204 for (i = 0; i < bytes >> 1; i++, naddr++) {
1205 qla2x00_write_nvram_word(ha, naddr,
1206 cpu_to_le16(*wptr));
1207 wptr++;
1208 }
1209
1210 /* Enable NVRAM write-protection. */
1211 qla2x00_set_nvram_protection(ha, stat);
1212
1213 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1214 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1215
1216 return ret;
1217}
1218
1219int
7b867cf7 1220qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1221 uint32_t bytes)
1222{
1223 int ret;
1224 uint32_t i;
1225 uint32_t *dwptr;
7b867cf7 1226 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1227 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1228
1229 ret = QLA_SUCCESS;
1230
459c5378
AV		 1231 /* Enable flash write. */
1232 WRT_REG_DWORD(&reg->ctrl_status,
1233 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1234 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1235
1236 /* Disable NVRAM write-protection. */
3a03eb79
AV		 1237 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1238 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
459c5378
AV		 1239
1240 /* Dword writes to flash. */
1241 dwptr = (uint32_t *)buf;
1242 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1243 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1244 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
459c5378 1245 if (ret != QLA_SUCCESS) {
7640335e
AV		 1246 DEBUG9(qla_printk(KERN_WARNING, ha,
1247 "Unable to program nvram address=%x data=%x.\n",
1248 naddr, *dwptr));
459c5378
AV		 1249 break;
1250 }
1251 }
1252
1253 /* Enable NVRAM write-protection. */
3a03eb79 1254 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
459c5378
AV		 1255
1256 /* Disable flash write. */
1257 WRT_REG_DWORD(&reg->ctrl_status,
1258 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1259 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1260
459c5378
AV		 1261 return ret;
1262}
f6df144c 1263
c3a2f0df 1264uint8_t *
7b867cf7 1265qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1266 uint32_t bytes)
1267{
1268 uint32_t i;
1269 uint32_t *dwptr;
7b867cf7 1270 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1271
1272 /* Dword reads to flash. */
1273 dwptr = (uint32_t *)buf;
1274 for (i = 0; i < bytes >> 2; i++, naddr++)
1275 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
3a03eb79 1276 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
c3a2f0df
AV		 1277
1278 return buf;
1279}
1280
1281int
7b867cf7 1282qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1283 uint32_t bytes)
1284{
7b867cf7 1285 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1286#define RMW_BUFFER_SIZE (64 * 1024)
1287 uint8_t *dbuf;
1288
1289 dbuf = vmalloc(RMW_BUFFER_SIZE);
1290 if (!dbuf)
1291 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1292 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1293 RMW_BUFFER_SIZE);
1294 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1295 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1296 RMW_BUFFER_SIZE);
1297 vfree(dbuf);
1298
1299 return QLA_SUCCESS;
c3a2f0df 1300}
f6df144c
AV		 1301
1302static inline void
7b867cf7 1303qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c
AV		 1304{
1305 if (IS_QLA2322(ha)) {
1306 /* Flip all colors. */
1307 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1308 /* Turn off. */
1309 ha->beacon_color_state = 0;
1310 *pflags = GPIO_LED_ALL_OFF;
1311 } else {
1312 /* Turn on. */
1313 ha->beacon_color_state = QLA_LED_ALL_ON;
1314 *pflags = GPIO_LED_RGA_ON;
1315 }
1316 } else {
1317 /* Flip green led only. */
1318 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1319 /* Turn off. */
1320 ha->beacon_color_state = 0;
1321 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1322 } else {
1323 /* Turn on. */
1324 ha->beacon_color_state = QLA_LED_GRN_ON;
1325 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1326 }
1327 }
1328}
1329
948882f6
AV		 1330#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1331
f6df144c 1332void
7b867cf7 1333qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c
AV		 1334{
1335 uint16_t gpio_enable;
1336 uint16_t gpio_data;
1337 uint16_t led_color = 0;
1338 unsigned long flags;
7b867cf7 1339 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1340 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1341
f6df144c
AV		 1342 spin_lock_irqsave(&ha->hardware_lock, flags);
1343
1344 /* Save the Original GPIOE. */
1345 if (ha->pio_address) {
948882f6
AV		 1346 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1347 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c
AV		 1348 } else {
1349 gpio_enable = RD_REG_WORD(&reg->gpioe);
1350 gpio_data = RD_REG_WORD(&reg->gpiod);
1351 }
1352
1353 /* Set the modified gpio_enable values */
1354 gpio_enable |= GPIO_LED_MASK;
1355
1356 if (ha->pio_address) {
948882f6 1357 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c
AV		 1358 } else {
1359 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1360 RD_REG_WORD(&reg->gpioe);
1361 }
1362
1363 qla2x00_flip_colors(ha, &led_color);
1364
1365 /* Clear out any previously set LED color. */
1366 gpio_data &= ~GPIO_LED_MASK;
1367
1368 /* Set the new input LED color to GPIOD. */
1369 gpio_data |= led_color;
1370
1371 /* Set the modified gpio_data values */
1372 if (ha->pio_address) {
948882f6 1373 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c
AV		 1374 } else {
1375 WRT_REG_WORD(&reg->gpiod, gpio_data);
1376 RD_REG_WORD(&reg->gpiod);
1377 }
1378
1379 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1380}
1381
1382int
7b867cf7 1383qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c
AV		 1384{
1385 uint16_t gpio_enable;
1386 uint16_t gpio_data;
1387 unsigned long flags;
7b867cf7 1388 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1389 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1390
1391 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1392 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1393
7b867cf7 1394 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c
AV		 1395 qla_printk(KERN_WARNING, ha,
1396 "Unable to update fw options (beacon on).\n");
1397 return QLA_FUNCTION_FAILED;
1398 }
1399
f6df144c
AV		 1400 /* Turn off LEDs. */
1401 spin_lock_irqsave(&ha->hardware_lock, flags);
1402 if (ha->pio_address) {
948882f6
AV		 1403 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1404 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c
AV		 1405 } else {
1406 gpio_enable = RD_REG_WORD(&reg->gpioe);
1407 gpio_data = RD_REG_WORD(&reg->gpiod);
1408 }
1409 gpio_enable |= GPIO_LED_MASK;
1410
1411 /* Set the modified gpio_enable values. */
1412 if (ha->pio_address) {
948882f6 1413 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c
AV		 1414 } else {
1415 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1416 RD_REG_WORD(&reg->gpioe);
1417 }
1418
1419 /* Clear out previously set LED colour. */
1420 gpio_data &= ~GPIO_LED_MASK;
1421 if (ha->pio_address) {
948882f6 1422 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c
AV		 1423 } else {
1424 WRT_REG_WORD(&reg->gpiod, gpio_data);
1425 RD_REG_WORD(&reg->gpiod);
1426 }
1427 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1428
1429 /*
1430 * Let the per HBA timer kick off the blinking process based on
1431 * the following flags. No need to do anything else now.
1432 */
1433 ha->beacon_blink_led = 1;
1434 ha->beacon_color_state = 0;
1435
1436 return QLA_SUCCESS;
1437}
1438
1439int
7b867cf7 1440qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c
AV		 1441{
1442 int rval = QLA_SUCCESS;
7b867cf7 1443 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1444
1445 ha->beacon_blink_led = 0;
1446
1447 /* Set the on flag so when it gets flipped it will be off. */
1448 if (IS_QLA2322(ha))
1449 ha->beacon_color_state = QLA_LED_ALL_ON;
1450 else
1451 ha->beacon_color_state = QLA_LED_GRN_ON;
1452
7b867cf7 1453 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c
AV		 1454
1455 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1456 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1457
7b867cf7 1458 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c
AV		 1459 if (rval != QLA_SUCCESS)
1460 qla_printk(KERN_WARNING, ha,
1461 "Unable to update fw options (beacon off).\n");
1462 return rval;
1463}
1464
1465
1466static inline void
7b867cf7 1467qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c
AV		 1468{
1469 /* Flip all colors. */
1470 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1471 /* Turn off. */
1472 ha->beacon_color_state = 0;
1473 *pflags = 0;
1474 } else {
1475 /* Turn on. */
1476 ha->beacon_color_state = QLA_LED_ALL_ON;
1477 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1478 }
1479}
1480
1481void
7b867cf7 1482qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c
AV		 1483{
1484 uint16_t led_color = 0;
1485 uint32_t gpio_data;
1486 unsigned long flags;
7b867cf7 1487 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1488 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1489
1490 /* Save the Original GPIOD. */
1491 spin_lock_irqsave(&ha->hardware_lock, flags);
1492 gpio_data = RD_REG_DWORD(&reg->gpiod);
1493
1494 /* Enable the gpio_data reg for update. */
1495 gpio_data |= GPDX_LED_UPDATE_MASK;
1496
1497 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1498 gpio_data = RD_REG_DWORD(&reg->gpiod);
1499
1500 /* Set the color bits. */
1501 qla24xx_flip_colors(ha, &led_color);
1502
1503 /* Clear out any previously set LED color. */
1504 gpio_data &= ~GPDX_LED_COLOR_MASK;
1505
1506 /* Set the new input LED color to GPIOD. */
1507 gpio_data |= led_color;
1508
1509 /* Set the modified gpio_data values. */
1510 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1511 gpio_data = RD_REG_DWORD(&reg->gpiod);
1512 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1513}
1514
1515int
7b867cf7 1516qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c
AV		 1517{
1518 uint32_t gpio_data;
1519 unsigned long flags;
7b867cf7 1520 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1521 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1522
1523 if (ha->beacon_blink_led == 0) {
1524 /* Enable firmware for update */
1525 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1526
7b867cf7 1527 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c
AV		 1528 return QLA_FUNCTION_FAILED;
1529
7b867cf7 1530 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c
AV		 1531 QLA_SUCCESS) {
1532 qla_printk(KERN_WARNING, ha,
1533 "Unable to update fw options (beacon on).\n");
1534 return QLA_FUNCTION_FAILED;
1535 }
1536
1537 spin_lock_irqsave(&ha->hardware_lock, flags);
1538 gpio_data = RD_REG_DWORD(&reg->gpiod);
1539
1540 /* Enable the gpio_data reg for update. */
1541 gpio_data |= GPDX_LED_UPDATE_MASK;
1542 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1543 RD_REG_DWORD(&reg->gpiod);
1544
1545 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1546 }
1547
1548 /* So all colors blink together. */
1549 ha->beacon_color_state = 0;
1550
1551 /* Let the per HBA timer kick off the blinking process. */
1552 ha->beacon_blink_led = 1;
1553
1554 return QLA_SUCCESS;
1555}
1556
1557int
7b867cf7 1558qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c
AV		 1559{
1560 uint32_t gpio_data;
1561 unsigned long flags;
7b867cf7 1562 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1563 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1564
1565 ha->beacon_blink_led = 0;
1566 ha->beacon_color_state = QLA_LED_ALL_ON;
1567
7b867cf7 1568 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c
AV		 1569
1570 /* Give control back to firmware. */
1571 spin_lock_irqsave(&ha->hardware_lock, flags);
1572 gpio_data = RD_REG_DWORD(&reg->gpiod);
1573
1574 /* Disable the gpio_data reg for update. */
1575 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1576 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1577 RD_REG_DWORD(&reg->gpiod);
1578 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1579
1580 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1581
7b867cf7 1582 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c
AV		 1583 qla_printk(KERN_WARNING, ha,
1584 "Unable to update fw options (beacon off).\n");
1585 return QLA_FUNCTION_FAILED;
1586 }
1587
7b867cf7 1588 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
f6df144c
AV		 1589 qla_printk(KERN_WARNING, ha,
1590 "Unable to get fw options (beacon off).\n");
1591 return QLA_FUNCTION_FAILED;
1592 }
1593
1594 return QLA_SUCCESS;
1595}
854165f4
AV		 1596
1597
1598/*
1599 * Flash support routines
1600 */
1601
1602/**
1603 * qla2x00_flash_enable() - Setup flash for reading and writing.
1604 * @ha: HA context
1605 */
1606static void
7b867cf7 1607qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4
AV		 1608{
1609 uint16_t data;
1610 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1611
1612 data = RD_REG_WORD(&reg->ctrl_status);
1613 data |= CSR_FLASH_ENABLE;
1614 WRT_REG_WORD(&reg->ctrl_status, data);
1615 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1616}
1617
1618/**
1619 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1620 * @ha: HA context
1621 */
1622static void
7b867cf7 1623qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4
AV		 1624{
1625 uint16_t data;
1626 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1627
1628 data = RD_REG_WORD(&reg->ctrl_status);
1629 data &= ~(CSR_FLASH_ENABLE);
1630 WRT_REG_WORD(&reg->ctrl_status, data);
1631 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1632}
1633
1634/**
1635 * qla2x00_read_flash_byte() - Reads a byte from flash
1636 * @ha: HA context
1637 * @addr: Address in flash to read
1638 *
1639 * A word is read from the chip, but, only the lower byte is valid.
1640 *
1641 * Returns the byte read from flash @addr.
1642 */
1643static uint8_t
7b867cf7 1644qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4
AV		 1645{
1646 uint16_t data;
1647 uint16_t bank_select;
1648 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1649
1650 bank_select = RD_REG_WORD(&reg->ctrl_status);
1651
1652 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1653 /* Specify 64K address range: */
1654 /* clear out Module Select and Flash Address bits [19:16]. */
1655 bank_select &= ~0xf8;
1656 bank_select |= addr >> 12 & 0xf0;
1657 bank_select |= CSR_FLASH_64K_BANK;
1658 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1659 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1660
1661 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1662 data = RD_REG_WORD(&reg->flash_data);
1663
1664 return (uint8_t)data;
1665 }
1666
1667 /* Setup bit 16 of flash address. */
1668 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1669 bank_select |= CSR_FLASH_64K_BANK;
1670 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1671 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1672 } else if (((addr & BIT_16) == 0) &&
1673 (bank_select & CSR_FLASH_64K_BANK)) {
1674 bank_select &= ~(CSR_FLASH_64K_BANK);
1675 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1676 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1677 }
1678
1679 /* Always perform IO mapped accesses to the FLASH registers. */
1680 if (ha->pio_address) {
1681 uint16_t data2;
1682
948882f6 1683 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1684 do {
948882f6 1685 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4
AV		 1686 barrier();
1687 cpu_relax();
948882f6 1688 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4
AV		 1689 } while (data != data2);
1690 } else {
1691 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1692 data = qla2x00_debounce_register(&reg->flash_data);
1693 }
1694
1695 return (uint8_t)data;
1696}
1697
1698/**
1699 * qla2x00_write_flash_byte() - Write a byte to flash
1700 * @ha: HA context
1701 * @addr: Address in flash to write
1702 * @data: Data to write
1703 */
1704static void
7b867cf7 1705qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4
AV		 1706{
1707 uint16_t bank_select;
1708 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1709
1710 bank_select = RD_REG_WORD(&reg->ctrl_status);
1711 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1712 /* Specify 64K address range: */
1713 /* clear out Module Select and Flash Address bits [19:16]. */
1714 bank_select &= ~0xf8;
1715 bank_select |= addr >> 12 & 0xf0;
1716 bank_select |= CSR_FLASH_64K_BANK;
1717 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1718 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1719
1720 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1721 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1722 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1723 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1724
1725 return;
1726 }
1727
1728 /* Setup bit 16 of flash address. */
1729 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1730 bank_select |= CSR_FLASH_64K_BANK;
1731 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1732 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1733 } else if (((addr & BIT_16) == 0) &&
1734 (bank_select & CSR_FLASH_64K_BANK)) {
1735 bank_select &= ~(CSR_FLASH_64K_BANK);
1736 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1737 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1738 }
1739
1740 /* Always perform IO mapped accesses to the FLASH registers. */
1741 if (ha->pio_address) {
948882f6
AV		 1742 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1743 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4
AV		 1744 } else {
1745 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1746 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1747 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1748 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1749 }
1750}
1751
1752/**
1753 * qla2x00_poll_flash() - Polls flash for completion.
1754 * @ha: HA context
1755 * @addr: Address in flash to poll
1756 * @poll_data: Data to be polled
1757 * @man_id: Flash manufacturer ID
1758 * @flash_id: Flash ID
1759 *
1760 * This function polls the device until bit 7 of what is read matches data
1761 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1762 * out (a fatal error). The flash book recommeds reading bit 7 again after
1763 * reading bit 5 as a 1.
1764 *
1765 * Returns 0 on success, else non-zero.
1766 */
1767static int
7b867cf7 1768qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4
AV		 1769 uint8_t man_id, uint8_t flash_id)
1770{
1771 int status;
1772 uint8_t flash_data;
1773 uint32_t cnt;
1774
1775 status = 1;
1776
1777 /* Wait for 30 seconds for command to finish. */
1778 poll_data &= BIT_7;
1779 for (cnt = 3000000; cnt; cnt--) {
1780 flash_data = qla2x00_read_flash_byte(ha, addr);
1781 if ((flash_data & BIT_7) == poll_data) {
1782 status = 0;
1783 break;
1784 }
1785
1786 if (man_id != 0x40 && man_id != 0xda) {
1787 if ((flash_data & BIT_5) && cnt > 2)
1788 cnt = 2;
1789 }
1790 udelay(10);
1791 barrier();
40a2e34a 1792 cond_resched();
854165f4
AV		 1793 }
1794 return status;
1795}
1796
854165f4
AV		 1797/**
1798 * qla2x00_program_flash_address() - Programs a flash address
1799 * @ha: HA context
1800 * @addr: Address in flash to program
1801 * @data: Data to be written in flash
1802 * @man_id: Flash manufacturer ID
1803 * @flash_id: Flash ID
1804 *
1805 * Returns 0 on success, else non-zero.
1806 */
1807static int
7b867cf7
AC		 1808qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1809 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4
AV		 1810{
1811 /* Write Program Command Sequence. */
1812 if (IS_OEM_001(ha)) {
1813 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1814 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1815 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1816 qla2x00_write_flash_byte(ha, addr, data);
1817 } else {
1818 if (man_id == 0xda && flash_id == 0xc1) {
1819 qla2x00_write_flash_byte(ha, addr, data);
1820 if (addr & 0x7e)
1821 return 0;
1822 } else {
1823 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1824 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1825 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1826 qla2x00_write_flash_byte(ha, addr, data);
1827 }
1828 }
1829
1830 udelay(150);
1831
1832 /* Wait for write to complete. */
1833 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1834}
1835
1836/**
1837 * qla2x00_erase_flash() - Erase the flash.
1838 * @ha: HA context
1839 * @man_id: Flash manufacturer ID
1840 * @flash_id: Flash ID
1841 *
1842 * Returns 0 on success, else non-zero.
1843 */
1844static int
7b867cf7 1845qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4
AV		 1846{
1847 /* Individual Sector Erase Command Sequence */
1848 if (IS_OEM_001(ha)) {
1849 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1850 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1851 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1852 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1853 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1854 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1855 } else {
1856 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1857 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1858 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1859 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1860 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1861 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1862 }
1863
1864 udelay(150);
1865
1866 /* Wait for erase to complete. */
1867 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1868}
1869
1870/**
1871 * qla2x00_erase_flash_sector() - Erase a flash sector.
1872 * @ha: HA context
1873 * @addr: Flash sector to erase
1874 * @sec_mask: Sector address mask
1875 * @man_id: Flash manufacturer ID
1876 * @flash_id: Flash ID
1877 *
1878 * Returns 0 on success, else non-zero.
1879 */
1880static int
7b867cf7 1881qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4
AV		 1882 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1883{
1884 /* Individual Sector Erase Command Sequence */
1885 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1886 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1887 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1888 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1889 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1890 if (man_id == 0x1f && flash_id == 0x13)
1891 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1892 else
1893 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1894
1895 udelay(150);
1896
1897 /* Wait for erase to complete. */
1898 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1899}
1900
1901/**
1902 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1903 * @man_id: Flash manufacturer ID
1904 * @flash_id: Flash ID
1905 */
1906static void
7b867cf7 1907qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4
AV		 1908 uint8_t *flash_id)
1909{
1910 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1911 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1912 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1913 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1914 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1915 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1916 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1917 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1918}
1919
30c47662 1920static void
7b867cf7
AC		 1921qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1922 uint32_t saddr, uint32_t length)
30c47662
AV		 1923{
1924 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1925 uint32_t midpoint, ilength;
1926 uint8_t data;
1927
1928 midpoint = length / 2;
1929
1930 WRT_REG_WORD(&reg->nvram, 0);
1931 RD_REG_WORD(&reg->nvram);
1932 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1933 if (ilength == midpoint) {
1934 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1935 RD_REG_WORD(&reg->nvram);
1936 }
1937 data = qla2x00_read_flash_byte(ha, saddr);
1938 if (saddr % 100)
1939 udelay(10);
1940 *tmp_buf = data;
40a2e34a 1941 cond_resched();
30c47662
AV		 1942 }
1943}
854165f4
AV		 1944
1945static inline void
7b867cf7 1946qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4
AV		 1947{
1948 int cnt;
1949 unsigned long flags;
7b867cf7 1950 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 1951 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1952
1953 /* Suspend HBA. */
7b867cf7 1954 scsi_block_requests(vha->host);
fd34f556 1955 ha->isp_ops->disable_intrs(ha);
854165f4
AV		 1956 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1957
1958 /* Pause RISC. */
1959 spin_lock_irqsave(&ha->hardware_lock, flags);
1960 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1961 RD_REG_WORD(&reg->hccr);
1962 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1963 for (cnt = 0; cnt < 30000; cnt++) {
1964 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1965 break;
1966 udelay(100);
1967 }
1968 } else {
1969 udelay(10);
1970 }
1971 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1972}
1973
1974static inline void
7b867cf7 1975qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 1976{
7b867cf7
AC		 1977 struct qla_hw_data *ha = vha->hw;
1978
854165f4
AV		 1979 /* Resume HBA. */
1980 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 1981 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1982 qla2xxx_wake_dpc(vha);
2533cf67 1983 qla2x00_wait_for_chip_reset(vha);
7b867cf7 1984 scsi_unblock_requests(vha->host);
854165f4
AV		 1985}
1986
1987uint8_t *
7b867cf7 1988qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 1989 uint32_t offset, uint32_t length)
1990{
854165f4
AV		 1991 uint32_t addr, midpoint;
1992 uint8_t *data;
7b867cf7 1993 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 1994 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1995
1996 /* Suspend HBA. */
7b867cf7 1997 qla2x00_suspend_hba(vha);
854165f4
AV		 1998
1999 /* Go with read. */
854165f4
AV		 2000 midpoint = ha->optrom_size / 2;
2001
2002 qla2x00_flash_enable(ha);
2003 WRT_REG_WORD(&reg->nvram, 0);
2004 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2005 for (addr = offset, data = buf; addr < length; addr++, data++) {
2006 if (addr == midpoint) {
2007 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2008 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2009 }
2010
2011 *data = qla2x00_read_flash_byte(ha, addr);
2012 }
2013 qla2x00_flash_disable(ha);
854165f4
AV		 2014
2015 /* Resume HBA. */
7b867cf7 2016 qla2x00_resume_hba(vha);
854165f4
AV		 2017
2018 return buf;
2019}
2020
2021int
7b867cf7 2022qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2023 uint32_t offset, uint32_t length)
2024{
2025
2026 int rval;
854165f4
AV		 2027 uint8_t man_id, flash_id, sec_number, data;
2028 uint16_t wd;
2029 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 2030 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2031 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2032
2033 /* Suspend HBA. */
7b867cf7 2034 qla2x00_suspend_hba(vha);
854165f4
AV		 2035
2036 rval = QLA_SUCCESS;
2037 sec_number = 0;
2038
2039 /* Reset ISP chip. */
854165f4
AV		 2040 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2041 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2042
2043 /* Go with write. */
2044 qla2x00_flash_enable(ha);
2045 do { /* Loop once to provide quick error exit */
2046 /* Structure of flash memory based on manufacturer */
2047 if (IS_OEM_001(ha)) {
2048 /* OEM variant with special flash part. */
2049 man_id = flash_id = 0;
2050 rest_addr = 0xffff;
2051 sec_mask = 0x10000;
2052 goto update_flash;
2053 }
2054 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2055 switch (man_id) {
2056 case 0x20: /* ST flash. */
2057 if (flash_id == 0xd2 || flash_id == 0xe3) {
2058 /*
2059 * ST m29w008at part - 64kb sector size with
2060 * 32kb,8kb,8kb,16kb sectors at memory address
2061 * 0xf0000.
2062 */
2063 rest_addr = 0xffff;
2064 sec_mask = 0x10000;
2065 break;
2066 }
2067 /*
2068 * ST m29w010b part - 16kb sector size
2069 * Default to 16kb sectors
2070 */
2071 rest_addr = 0x3fff;
2072 sec_mask = 0x1c000;
2073 break;
2074 case 0x40: /* Mostel flash. */
2075 /* Mostel v29c51001 part - 512 byte sector size. */
2076 rest_addr = 0x1ff;
2077 sec_mask = 0x1fe00;
2078 break;
2079 case 0xbf: /* SST flash. */
2080 /* SST39sf10 part - 4kb sector size. */
2081 rest_addr = 0xfff;
2082 sec_mask = 0x1f000;
2083 break;
2084 case 0xda: /* Winbond flash. */
2085 /* Winbond W29EE011 part - 256 byte sector size. */
2086 rest_addr = 0x7f;
2087 sec_mask = 0x1ff80;
2088 break;
2089 case 0xc2: /* Macronix flash. */
2090 /* 64k sector size. */
2091 if (flash_id == 0x38 || flash_id == 0x4f) {
2092 rest_addr = 0xffff;
2093 sec_mask = 0x10000;
2094 break;
2095 }
2096 /* Fall through... */
2097
2098 case 0x1f: /* Atmel flash. */
2099 /* 512k sector size. */
2100 if (flash_id == 0x13) {
2101 rest_addr = 0x7fffffff;
2102 sec_mask = 0x80000000;
2103 break;
2104 }
2105 /* Fall through... */
2106
2107 case 0x01: /* AMD flash. */
2108 if (flash_id == 0x38 || flash_id == 0x40 ||
2109 flash_id == 0x4f) {
2110 /* Am29LV081 part - 64kb sector size. */
2111 /* Am29LV002BT part - 64kb sector size. */
2112 rest_addr = 0xffff;
2113 sec_mask = 0x10000;
2114 break;
2115 } else if (flash_id == 0x3e) {
2116 /*
2117 * Am29LV008b part - 64kb sector size with
2118 * 32kb,8kb,8kb,16kb sector at memory address
2119 * h0xf0000.
2120 */
2121 rest_addr = 0xffff;
2122 sec_mask = 0x10000;
2123 break;
2124 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2125 /*
2126 * Am29LV010 part or AM29f010 - 16kb sector
2127 * size.
2128 */
2129 rest_addr = 0x3fff;
2130 sec_mask = 0x1c000;
2131 break;
2132 } else if (flash_id == 0x6d) {
2133 /* Am29LV001 part - 8kb sector size. */
2134 rest_addr = 0x1fff;
2135 sec_mask = 0x1e000;
2136 break;
2137 }
2138 default:
2139 /* Default to 16 kb sector size. */
2140 rest_addr = 0x3fff;
2141 sec_mask = 0x1c000;
2142 break;
2143 }
2144
2145update_flash:
2146 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2147 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2148 rval = QLA_FUNCTION_FAILED;
2149 break;
2150 }
2151 }
2152
2153 for (addr = offset, liter = 0; liter < length; liter++,
2154 addr++) {
2155 data = buf[liter];
2156 /* Are we at the beginning of a sector? */
2157 if ((addr & rest_addr) == 0) {
2158 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2159 if (addr >= 0x10000UL) {
2160 if (((addr >> 12) & 0xf0) &&
2161 ((man_id == 0x01 &&
2162 flash_id == 0x3e) ||
2163 (man_id == 0x20 &&
2164 flash_id == 0xd2))) {
2165 sec_number++;
2166 if (sec_number == 1) {
2167 rest_addr =
2168 0x7fff;
2169 sec_mask =
2170 0x18000;
2171 } else if (
2172 sec_number == 2 ||
2173 sec_number == 3) {
2174 rest_addr =
2175 0x1fff;
2176 sec_mask =
2177 0x1e000;
2178 } else if (
2179 sec_number == 4) {
2180 rest_addr =
2181 0x3fff;
2182 sec_mask =
2183 0x1c000;
2184 }
2185 }
2186 }
2187 } else if (addr == ha->optrom_size / 2) {
2188 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2189 RD_REG_WORD(&reg->nvram);
2190 }
2191
2192 if (flash_id == 0xda && man_id == 0xc1) {
2193 qla2x00_write_flash_byte(ha, 0x5555,
2194 0xaa);
2195 qla2x00_write_flash_byte(ha, 0x2aaa,
2196 0x55);
2197 qla2x00_write_flash_byte(ha, 0x5555,
2198 0xa0);
2199 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2200 /* Then erase it */
2201 if (qla2x00_erase_flash_sector(ha,
2202 addr, sec_mask, man_id,
2203 flash_id)) {
2204 rval = QLA_FUNCTION_FAILED;
2205 break;
2206 }
2207 if (man_id == 0x01 && flash_id == 0x6d)
2208 sec_number++;
2209 }
2210 }
2211
2212 if (man_id == 0x01 && flash_id == 0x6d) {
2213 if (sec_number == 1 &&
2214 addr == (rest_addr - 1)) {
2215 rest_addr = 0x0fff;
2216 sec_mask = 0x1f000;
2217 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2218 rest_addr = 0x3fff;
2219 sec_mask = 0x1c000;
2220 }
2221 }
2222
2223 if (qla2x00_program_flash_address(ha, addr, data,
2224 man_id, flash_id)) {
2225 rval = QLA_FUNCTION_FAILED;
2226 break;
2227 }
40a2e34a 2228 cond_resched();
854165f4
AV		 2229 }
2230 } while (0);
2231 qla2x00_flash_disable(ha);
854165f4
AV		 2232
2233 /* Resume HBA. */
7b867cf7 2234 qla2x00_resume_hba(vha);
854165f4
AV		 2235
2236 return rval;
2237}
2238
2239uint8_t *
7b867cf7 2240qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2241 uint32_t offset, uint32_t length)
2242{
7b867cf7
AC		 2243 struct qla_hw_data *ha = vha->hw;
2244
854165f4 2245 /* Suspend HBA. */
7b867cf7 2246 scsi_block_requests(vha->host);
854165f4
AV		 2247 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2248
2249 /* Go with read. */
7b867cf7 2250 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4
AV		 2251
2252 /* Resume HBA. */
2253 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2254 scsi_unblock_requests(vha->host);
854165f4
AV		 2255
2256 return buf;
2257}
2258
2259int
7b867cf7 2260qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2261 uint32_t offset, uint32_t length)
2262{
2263 int rval;
7b867cf7 2264 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2265
2266 /* Suspend HBA. */
7b867cf7 2267 scsi_block_requests(vha->host);
854165f4
AV		 2268 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2269
2270 /* Go with write. */
7b867cf7 2271 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4
AV		 2272 length >> 2);
2273
854165f4 2274 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2275 scsi_unblock_requests(vha->host);
854165f4
AV		 2276
2277 return rval;
2278}
30c47662 2279
338c9161 2280uint8_t *
7b867cf7 2281qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2282 uint32_t offset, uint32_t length)
2283{
2284 int rval;
2285 dma_addr_t optrom_dma;
2286 void *optrom;
2287 uint8_t *pbuf;
2288 uint32_t faddr, left, burst;
7b867cf7 2289 struct qla_hw_data *ha = vha->hw;
338c9161 2290
b7cc176c 2291 if (offset & 0xfff)
338c9161
AV		 2292 goto slow_read;
2293 if (length < OPTROM_BURST_SIZE)
2294 goto slow_read;
2295
2296 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2297 &optrom_dma, GFP_KERNEL);
2298 if (!optrom) {
2299 qla_printk(KERN_DEBUG, ha,
2300 "Unable to allocate memory for optrom burst read "
2301 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2302
2303 goto slow_read;
2304 }
2305
2306 pbuf = buf;
2307 faddr = offset >> 2;
2308 left = length >> 2;
2309 burst = OPTROM_BURST_DWORDS;
2310 while (left != 0) {
2311 if (burst > left)
2312 burst = left;
2313
7b867cf7 2314 rval = qla2x00_dump_ram(vha, optrom_dma,
3a03eb79 2315 flash_data_addr(ha, faddr), burst);
338c9161
AV		 2316 if (rval) {
2317 qla_printk(KERN_WARNING, ha,
2318 "Unable to burst-read optrom segment "
2319 "(%x/%x/%llx).\n", rval,
3a03eb79 2320 flash_data_addr(ha, faddr),
875baf3c 2321 (unsigned long long)optrom_dma);
338c9161
AV		 2322 qla_printk(KERN_WARNING, ha,
2323 "Reverting to slow-read.\n");
2324
2325 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2326 optrom, optrom_dma);
2327 goto slow_read;
2328 }
2329
2330 memcpy(pbuf, optrom, burst * 4);
2331
2332 left -= burst;
2333 faddr += burst;
2334 pbuf += burst * 4;
2335 }
2336
2337 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2338 optrom_dma);
2339
2340 return buf;
2341
2342slow_read:
7b867cf7 2343 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2344}
2345
30c47662
AV		 2346/**
2347 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2348 * @ha: HA context
2349 * @pcids: Pointer to the FCODE PCI data structure
2350 *
2351 * The process of retrieving the FCODE version information is at best
2352 * described as interesting.
2353 *
2354 * Within the first 100h bytes of the image an ASCII string is present
2355 * which contains several pieces of information including the FCODE
2356 * version. Unfortunately it seems the only reliable way to retrieve
2357 * the version is by scanning for another sentinel within the string,
2358 * the FCODE build date:
2359 *
2360 * ... 2.00.02 10/17/02 ...
2361 *
2362 * Returns QLA_SUCCESS on successful retrieval of version.
2363 */
2364static void
7b867cf7 2365qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2366{
2367 int ret = QLA_FUNCTION_FAILED;
2368 uint32_t istart, iend, iter, vend;
2369 uint8_t do_next, rbyte, *vbyte;
2370
2371 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2372
2373 /* Skip the PCI data structure. */
2374 istart = pcids +
2375 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2376 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2377 iend = istart + 0x100;
2378 do {
2379 /* Scan for the sentinel date string...eeewww. */
2380 do_next = 0;
2381 iter = istart;
2382 while ((iter < iend) && !do_next) {
2383 iter++;
2384 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2385 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2386 '/')
2387 do_next++;
2388 else if (qla2x00_read_flash_byte(ha,
2389 iter + 3) == '/')
2390 do_next++;
2391 }
2392 }
2393 if (!do_next)
2394 break;
2395
2396 /* Backtrack to previous ' ' (space). */
2397 do_next = 0;
2398 while ((iter > istart) && !do_next) {
2399 iter--;
2400 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2401 do_next++;
2402 }
2403 if (!do_next)
2404 break;
2405
2406 /*
2407 * Mark end of version tag, and find previous ' ' (space) or
2408 * string length (recent FCODE images -- major hack ahead!!!).
2409 */
2410 vend = iter - 1;
2411 do_next = 0;
2412 while ((iter > istart) && !do_next) {
2413 iter--;
2414 rbyte = qla2x00_read_flash_byte(ha, iter);
2415 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2416 do_next++;
2417 }
2418 if (!do_next)
2419 break;
2420
2421 /* Mark beginning of version tag, and copy data. */
2422 iter++;
2423 if ((vend - iter) &&
2424 ((vend - iter) < sizeof(ha->fcode_revision))) {
2425 vbyte = ha->fcode_revision;
2426 while (iter <= vend) {
2427 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2428 iter++;
2429 }
2430 ret = QLA_SUCCESS;
2431 }
2432 } while (0);
2433
2434 if (ret != QLA_SUCCESS)
2435 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2436}
2437
2438int
7b867cf7 2439qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2440{
2441 int ret = QLA_SUCCESS;
2442 uint8_t code_type, last_image;
2443 uint32_t pcihdr, pcids;
2444 uint8_t *dbyte;
2445 uint16_t *dcode;
7b867cf7 2446 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2447
2448 if (!ha->pio_address || !mbuf)
2449 return QLA_FUNCTION_FAILED;
2450
2451 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2452 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2453 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2454 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2455
2456 qla2x00_flash_enable(ha);
2457
2458 /* Begin with first PCI expansion ROM header. */
2459 pcihdr = 0;
2460 last_image = 1;
2461 do {
2462 /* Verify PCI expansion ROM header. */
2463 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2464 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2465 /* No signature */
7b867cf7
AC		 2466 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2467 "signature.\n"));
30c47662
AV		 2468 ret = QLA_FUNCTION_FAILED;
2469 break;
2470 }
2471
2472 /* Locate PCI data structure. */
2473 pcids = pcihdr +
2474 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2475 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2476
2477 /* Validate signature of PCI data structure. */
2478 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2479 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2480 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2481 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2482 /* Incorrect header. */
7b867cf7
AC		 2483 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2484 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2485 ret = QLA_FUNCTION_FAILED;
2486 break;
2487 }
2488
2489 /* Read version */
2490 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2491 switch (code_type) {
2492 case ROM_CODE_TYPE_BIOS:
2493 /* Intel x86, PC-AT compatible. */
2494 ha->bios_revision[0] =
2495 qla2x00_read_flash_byte(ha, pcids + 0x12);
2496 ha->bios_revision[1] =
2497 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2498 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2499 ha->bios_revision[1], ha->bios_revision[0]));
2500 break;
2501 case ROM_CODE_TYPE_FCODE:
2502 /* Open Firmware standard for PCI (FCode). */
2503 /* Eeeewww... */
2504 qla2x00_get_fcode_version(ha, pcids);
2505 break;
2506 case ROM_CODE_TYPE_EFI:
2507 /* Extensible Firmware Interface (EFI). */
2508 ha->efi_revision[0] =
2509 qla2x00_read_flash_byte(ha, pcids + 0x12);
2510 ha->efi_revision[1] =
2511 qla2x00_read_flash_byte(ha, pcids + 0x13);
7b867cf7 2512 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2513 ha->efi_revision[1], ha->efi_revision[0]));
2514 break;
2515 default:
7b867cf7
AC		 2516 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2517 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2518 break;
2519 }
2520
2521 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2522
2523 /* Locate next PCI expansion ROM. */
2524 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2525 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2526 } while (!last_image);
2527
2528 if (IS_QLA2322(ha)) {
2529 /* Read firmware image information. */
2530 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2531 dbyte = mbuf;
2532 memset(dbyte, 0, 8);
2533 dcode = (uint16_t *)dbyte;
2534
c00d8994 2535 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2536 8);
7b867cf7
AC		 2537 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2538 "flash:\n"));
30c47662
AV		 2539 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2540
2541 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2542 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2543 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2544 dcode[3] == 0)) {
7b867cf7
AC		 2545 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2546 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2547 } else {
2548 /* values are in big endian */
2549 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2550 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2551 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2552 }
2553 }
2554
2555 qla2x00_flash_disable(ha);
2556
2557 return ret;
2558}
2559
2560int
7b867cf7 2561qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2562{
2563 int ret = QLA_SUCCESS;
2564 uint32_t pcihdr, pcids;
2565 uint32_t *dcode;
2566 uint8_t *bcode;
2567 uint8_t code_type, last_image;
2568 int i;
7b867cf7 2569 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2570
2571 if (!mbuf)
2572 return QLA_FUNCTION_FAILED;
2573
2574 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2575 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2576 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2577 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2578
2579 dcode = mbuf;
2580
2581 /* Begin with first PCI expansion ROM header. */
6315a5f8 2582 pcihdr = ha->flt_region_boot << 2;
30c47662
AV		 2583 last_image = 1;
2584 do {
2585 /* Verify PCI expansion ROM header. */
7b867cf7 2586 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2587 bcode = mbuf + (pcihdr % 4);
2588 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2589 /* No signature */
7b867cf7
AC		 2590 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2591 "signature.\n"));
30c47662
AV		 2592 ret = QLA_FUNCTION_FAILED;
2593 break;
2594 }
2595
2596 /* Locate PCI data structure. */
2597 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2598
7b867cf7 2599 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2600 bcode = mbuf + (pcihdr % 4);
2601
2602 /* Validate signature of PCI data structure. */
2603 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2604 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2605 /* Incorrect header. */
7b867cf7
AC		 2606 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2607 "found pcir_adr=%x.\n", pcids));
30c47662
AV		 2608 ret = QLA_FUNCTION_FAILED;
2609 break;
2610 }
2611
2612 /* Read version */
2613 code_type = bcode[0x14];
2614 switch (code_type) {
2615 case ROM_CODE_TYPE_BIOS:
2616 /* Intel x86, PC-AT compatible. */
2617 ha->bios_revision[0] = bcode[0x12];
2618 ha->bios_revision[1] = bcode[0x13];
7b867cf7 2619 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
30c47662
AV		 2620 ha->bios_revision[1], ha->bios_revision[0]));
2621 break;
2622 case ROM_CODE_TYPE_FCODE:
2623 /* Open Firmware standard for PCI (FCode). */
2624 ha->fcode_revision[0] = bcode[0x12];
2625 ha->fcode_revision[1] = bcode[0x13];
7b867cf7 2626 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
30c47662
AV		 2627 ha->fcode_revision[1], ha->fcode_revision[0]));
2628 break;
2629 case ROM_CODE_TYPE_EFI:
2630 /* Extensible Firmware Interface (EFI). */
2631 ha->efi_revision[0] = bcode[0x12];
2632 ha->efi_revision[1] = bcode[0x13];
7b867cf7 2633 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
30c47662
AV		 2634 ha->efi_revision[1], ha->efi_revision[0]));
2635 break;
2636 default:
7b867cf7
AC		 2637 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2638 "type %x at pcids %x.\n", code_type, pcids));
30c47662
AV		 2639 break;
2640 }
2641
2642 last_image = bcode[0x15] & BIT_7;
2643
2644 /* Locate next PCI expansion ROM. */
2645 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2646 } while (!last_image);
2647
2648 /* Read firmware image information. */
2649 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2650 dcode = mbuf;
2651
7b867cf7 2652 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2653 for (i = 0; i < 4; i++)
2654 dcode[i] = be32_to_cpu(dcode[i]);
2655
2656 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2657 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2658 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2659 dcode[3] == 0)) {
7b867cf7
AC		 2660 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2661 "revision at %x.\n", ha->flt_region_fw * 4));
30c47662
AV		 2662 } else {
2663 ha->fw_revision[0] = dcode[0];
2664 ha->fw_revision[1] = dcode[1];
2665 ha->fw_revision[2] = dcode[2];
2666 ha->fw_revision[3] = dcode[3];
2667 }
2668
2669 return ret;
2670}
cb8dacbf 2671
1ee27146
JC		 2672static int
2673qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2674{
2675 if (pos >= end || *pos != 0x82)
2676 return 0;
2677
2678 pos += 3 + pos[1];
2679 if (pos >= end || *pos != 0x90)
2680 return 0;
2681
2682 pos += 3 + pos[1];
2683 if (pos >= end || *pos != 0x78)
2684 return 0;
2685
2686 return 1;
2687}
2688
2689int
7b867cf7 2690qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2691{
7b867cf7 2692 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2693 uint8_t *pos = ha->vpd;
2694 uint8_t *end = pos + ha->vpd_size;
2695 int len = 0;
2696
2697 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2698 return 0;
2699
2700 while (pos < end && *pos != 0x78) {
2701 len = (*pos == 0x82) ? pos[1] : pos[2];
2702
2703 if (!strncmp(pos, key, strlen(key)))
2704 break;
2705
2706 if (*pos != 0x90 && *pos != 0x91)
2707 pos += len;
2708
2709 pos += 3;
2710 }
2711
2712 if (pos < end - len && *pos != 0x78)
2713 return snprintf(str, size, "%.*s", len, pos + 3);
2714
2715 return 0;
2716}
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