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iwlwifi: trigger scan synchronously
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
d43c36dc 33#include <linux/sched.h>
b481de9c
ZY		 34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
dbb6654c 42#include "iwl-fh.h"
bddadf86 43#include "iwl-3945-fh.h"
600c0e11 44#include "iwl-commands.h"
17f841cd 45#include "iwl-sta.h"
b481de9c 46#include "iwl-3945.h"
e6148917 47#include "iwl-eeprom.h"
5747d47f 48#include "iwl-core.h"
4a6547c7 49#include "iwl-helpers.h"
e932a609
JB		 50#include "iwl-led.h"
51#include "iwl-3945-led.h"
b481de9c
ZY		 52
53#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 64
65/*
66 * Parameter order:
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
68 *
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
71 *
72 */
d9829a67 73const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 74 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 86};
87
bb8c093b 88/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 89#define IWL_EVT_DISABLE (0)
90#define IWL_EVT_DISABLE_SIZE (1532/32)
91
92/**
bb8c093b 93 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 94 *
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 101void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 102{
b481de9c
ZY		 103 int i;
104 u32 base; /* SRAM address of event log header */
105 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
106 u32 array_size; /* # of u32 entries in array */
107 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
155 };
156
157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 158 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 159 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 160 return;
161 }
162
5d49f498
AK		 163 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 165
166 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 167 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 168 disable_ptr);
b481de9c 169 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 170 iwl_write_targ_mem(priv,
af7cca2a
TW		 171 disable_ptr + (i * sizeof(u32)),
172 evt_disable[i]);
b481de9c 173
b481de9c 174 } else {
e1623446
TW		 175 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 178 disable_ptr, array_size);
179 }
180
181}
182
17744ff6
TW		 183static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184{
185 int idx;
186
1d79e53c 187 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
17744ff6
TW		 188 if (iwl3945_rates[idx].plcp == plcp)
189 return idx;
190 return -1;
191}
192
d08853a3 193#ifdef CONFIG_IWLWIFI_DEBUG
04569cbe 194#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2
TW		 195
196static const char *iwl3945_get_tx_fail_reason(u32 status)
197{
198 switch (status & TX_STATUS_MSK) {
04569cbe 199 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 200 return "SUCCESS";
201 TX_STATUS_ENTRY(SHORT_LIMIT);
202 TX_STATUS_ENTRY(LONG_LIMIT);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204 TX_STATUS_ENTRY(MGMNT_ABORT);
205 TX_STATUS_ENTRY(NEXT_FRAG);
206 TX_STATUS_ENTRY(LIFE_EXPIRE);
207 TX_STATUS_ENTRY(DEST_PS);
208 TX_STATUS_ENTRY(ABORTED);
209 TX_STATUS_ENTRY(BT_RETRY);
210 TX_STATUS_ENTRY(STA_INVALID);
211 TX_STATUS_ENTRY(FRAG_DROPPED);
212 TX_STATUS_ENTRY(TID_DISABLE);
213 TX_STATUS_ENTRY(FRAME_FLUSHED);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215 TX_STATUS_ENTRY(TX_LOCKED);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217 }
218
219 return "UNKNOWN";
220}
221#else
222static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223{
224 return "";
225}
226#endif
227
e6a9854b
JB		 228/*
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
231 * value
232 */
4a8a4322 233int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 234{
235 int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237 switch (priv->band) {
238 case IEEE80211_BAND_5GHZ:
239 if (rate == IWL_RATE_12M_INDEX)
240 next_rate = IWL_RATE_9M_INDEX;
241 else if (rate == IWL_RATE_6M_INDEX)
242 next_rate = IWL_RATE_6M_INDEX;
243 break;
7262796a 244 case IEEE80211_BAND_2GHZ:
ee525d13 245 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 246 iwl_is_associated(priv)) {
7262796a
AM		 247 if (rate == IWL_RATE_11M_INDEX)
248 next_rate = IWL_RATE_5M_INDEX;
249 }
e6a9854b 250 break;
7262796a 251
e6a9854b
JB		 252 default:
253 break;
254 }
255
256 return next_rate;
257}
258
91c066f2
TW		 259
260/**
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262 *
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
266 */
4a8a4322 267static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 268 int txq_id, int index)
269{
188cf6c7 270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 271 struct iwl_queue *q = &txq->q;
dbb6654c 272 struct iwl_tx_info *tx_info;
91c066f2
TW		 273
274 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 280 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 281 tx_info->skb[0] = NULL;
7aaa1d79 282 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 283 }
284
d20b3c65 285 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 286 (txq_id != IWL_CMD_QUEUE_NUM) &&
287 priv->mac80211_registered)
e4e72fb4 288 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 289}
290
291/**
292 * iwl3945_rx_reply_tx - Handle Tx response
293 */
4a8a4322 294static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 295 struct iwl_rx_mem_buffer *rxb)
91c066f2 296{
2f301227 297 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 298 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299 int txq_id = SEQ_TO_QUEUE(sequence);
300 int index = SEQ_TO_INDEX(sequence);
188cf6c7 301 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 302 struct ieee80211_tx_info *info;
91c066f2
TW		 303 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304 u32 status = le32_to_cpu(tx_resp->status);
305 int rate_idx;
74221d07 306 int fail;
91c066f2 307
625a381a 308 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 309 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 310 "is out of range [0-%d] %d %d\n", txq_id,
311 index, txq->q.n_bd, txq->q.write_ptr,
312 txq->q.read_ptr);
313 return;
314 }
315
e039fa4a 316 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 317 ieee80211_tx_info_clear_status(info);
318
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321 if (info->band == IEEE80211_BAND_5GHZ)
322 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324 fail = tx_resp->failure_frame;
74221d07
AM		 325
326 info->status.rates[0].idx = rate_idx;
327 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 328
91c066f2 329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 330 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331 IEEE80211_TX_STAT_ACK : 0;
91c066f2 332
e1623446 333 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 334 txq_id, iwl3945_get_tx_fail_reason(status), status,
335 tx_resp->rate, tx_resp->failure_frame);
336
e1623446 337 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 341 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 342}
343
344
345
b481de9c
ZY		 346/*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
b481de9c
ZY		 352 *****************************************************************************/
353
396887a2
DH		 354void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355 struct iwl_rx_mem_buffer *rxb)
b481de9c 356{
2f301227 357 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e1623446 358 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 359 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 360 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 361
ee525d13 362 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 363}
364
17744ff6
TW		 365/******************************************************************************
366 *
367 * Misc. internal state and helper functions
368 *
369 ******************************************************************************/
d08853a3 370#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 371
372/**
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
374 *
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
378 */
d08853a3 379static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 380 struct iwl_rx_packet *pkt,
17744ff6
TW		 381 struct ieee80211_hdr *header, int group100)
382{
383 u32 to_us;
384 u32 print_summary = 0;
385 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
386 u32 hundred = 0;
387 u32 dataframe = 0;
fd7c8a40 388 __le16 fc;
17744ff6
TW		 389 u16 seq_ctl;
390 u16 channel;
391 u16 phy_flags;
392 u16 length;
393 u16 status;
394 u16 bcn_tmr;
395 u32 tsf_low;
396 u64 tsf;
397 u8 rssi;
398 u8 agc;
399 u16 sig_avg;
400 u16 noise_diff;
401 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
402 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
403 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
404 u8 *data = IWL_RX_DATA(pkt);
405
406 /* MAC header */
fd7c8a40 407 fc = header->frame_control;
17744ff6
TW		 408 seq_ctl = le16_to_cpu(header->seq_ctrl);
409
410 /* metadata */
411 channel = le16_to_cpu(rx_hdr->channel);
412 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
413 length = le16_to_cpu(rx_hdr->len);
414
415 /* end-of-frame status and timestamp */
416 status = le32_to_cpu(rx_end->status);
417 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
418 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
419 tsf = le64_to_cpu(rx_end->timestamp);
420
421 /* signal statistics */
422 rssi = rx_stats->rssi;
423 agc = rx_stats->agc;
424 sig_avg = le16_to_cpu(rx_stats->sig_avg);
425 noise_diff = le16_to_cpu(rx_stats->noise_diff);
426
427 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
428
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 431 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 433 dataframe = 1;
434 if (!group100)
435 print_summary = 1; /* print each frame */
436 else if (priv->framecnt_to_us < 100) {
437 priv->framecnt_to_us++;
438 print_summary = 0;
439 } else {
440 priv->framecnt_to_us = 0;
441 print_summary = 1;
442 hundred = 1;
443 }
444 } else {
445 /* print summary for all other frames */
446 print_summary = 1;
447 }
448
449 if (print_summary) {
450 char *title;
0ff1cca0 451 int rate;
17744ff6
TW		 452
453 if (hundred)
454 title = "100Frames";
fd7c8a40 455 else if (ieee80211_has_retry(fc))
17744ff6 456 title = "Retry";
fd7c8a40 457 else if (ieee80211_is_assoc_resp(fc))
17744ff6 458 title = "AscRsp";
fd7c8a40 459 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 460 title = "RasRsp";
fd7c8a40 461 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 462 title = "PrbRsp";
463 print_dump = 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc)) {
465 title = "Beacon";
466 print_dump = 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc))
468 title = "ATIM";
469 else if (ieee80211_is_auth(fc))
470 title = "Auth";
471 else if (ieee80211_is_deauth(fc))
472 title = "DeAuth";
473 else if (ieee80211_is_disassoc(fc))
474 title = "DisAssoc";
475 else
476 title = "Frame";
477
478 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
479 if (rate == -1)
480 rate = 0;
481 else
482 rate = iwl3945_rates[rate].ieee / 2;
483
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
487 if (dataframe)
e1623446 488 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
91dd6c27 489 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
fd7c8a40 490 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 491 length, rssi, channel, rate);
492 else {
493 /* src/dst addresses assume managed mode */
e1623446 494 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
fd7c8a40 497 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 498 header->addr3[5], rssi,
499 tsf_low - priv->scan_start_tsf,
500 phy_flags, channel);
501 }
502 }
503 if (print_dump)
3d816c77 504 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 505}
d08853a3
SO		 506
507static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
508 struct iwl_rx_packet *pkt,
509 struct ieee80211_hdr *header, int group100)
510{
3d816c77 511 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 512 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
513}
514
17744ff6 515#else
4a8a4322 516static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 517 struct iwl_rx_packet *pkt,
17744ff6
TW		 518 struct ieee80211_hdr *header, int group100)
519{
520}
521#endif
522
4bd9b4f3 523/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 524static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 525 struct ieee80211_hdr *header)
526{
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv->iw_mode) {
05c914fe 530 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 533 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header->addr2, priv->bssid);
536 default:
537 return 1;
538 }
539}
17744ff6 540
4a8a4322 541static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 542 struct iwl_rx_mem_buffer *rxb,
12342c47 543 struct ieee80211_rx_status *stats)
b481de9c 544{
2f301227 545 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 546 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 547 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
548 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 549 u16 len = le16_to_cpu(rx_hdr->len);
550 struct sk_buff *skb;
29b1b268 551 __le16 fc = hdr->frame_control;
b481de9c
ZY		 552
553 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 554 if (unlikely(len + IWL39_RX_FRAME_SIZE >
555 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 556 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 557 return;
558 }
559
560 /* We only process data packets if the interface is open */
561 if (unlikely(!priv->is_open)) {
e1623446
TW		 562 IWL_DEBUG_DROP_LIMIT(priv,
563 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 564 return;
565 }
b481de9c 566
ecdf94b8 567 skb = dev_alloc_skb(128);
2f301227 568 if (!skb) {
ecdf94b8 569 IWL_ERR(priv, "dev_alloc_skb failed\n");
2f301227
ZY		 570 return;
571 }
b481de9c 572
9c74d9fb 573 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 574 iwl_set_decrypted_flag(priv,
2f301227 575 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 576 le32_to_cpu(rx_end->status), stats);
577
2f301227
ZY		 578 skb_add_rx_frag(skb, 0, rxb->page,
579 (void *)rx_hdr->payload - (void *)pkt, len);
580
29b1b268 581 iwl_update_stats(priv, false, fc, len);
2f301227 582 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 583
29b1b268 584 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 585 priv->alloc_rxb_page--;
586 rxb->page = NULL;
b481de9c
ZY		 587}
588
7878a5a4
MA		 589#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
590
4a8a4322 591static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 592 struct iwl_rx_mem_buffer *rxb)
b481de9c 593{
17744ff6
TW		 594 struct ieee80211_hdr *header;
595 struct ieee80211_rx_status rx_status;
2f301227 596 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 597 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
598 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
599 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
f875f518
RC		 600 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
601 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
b481de9c 602 u8 network_packet;
17744ff6 603
17744ff6
TW		 604 rx_status.flag = 0;
605 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 606 rx_status.freq =
c0186078 607 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 608 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
609 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
610
611 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 612 if (rx_status.band == IEEE80211_BAND_5GHZ)
613 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 614
9024adf5 615 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 616 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
617
618 /* set the preamble flag if appropriate */
619 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
620 rx_status.flag |= RX_FLAG_SHORTPRE;
621
b481de9c 622 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 623 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
624 rx_stats->phy_count);
b481de9c
ZY		 625 return;
626 }
627
628 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
629 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 630 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 631 return;
632 }
633
56decd3c 634
b481de9c
ZY		 635
636 /* Convert 3945's rssi indicator to dBm */
250bdd21 637 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c 638
ed1b6e99
JB		 639 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
640 rx_status.signal, rx_stats_sig_avg,
641 rx_stats_noise_diff);
b481de9c 642
b481de9c
ZY		 643 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
644
bb8c093b 645 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 646
ed1b6e99 647 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
17744ff6
TW		 648 network_packet ? '*' : ' ',
649 le16_to_cpu(rx_hdr->channel),
566bfe5a 650 rx_status.signal, rx_status.signal,
ed1b6e99 651 rx_status.rate_idx);
b481de9c 652
d08853a3
SO		 653 /* Set "1" to report good data frames in groups of 100 */
654 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 655 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 656
657 if (network_packet) {
e99f168c
JB		 658 priv->_3945.last_beacon_time =
659 le32_to_cpu(rx_end->beacon_timestamp);
660 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
661 priv->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 662 }
663
12e5e22d 664 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 665}
666
7aaa1d79
SO		 667int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
668 struct iwl_tx_queue *txq,
669 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 670{
671 int count;
7aaa1d79 672 struct iwl_queue *q;
59606ffa 673 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 674
675 q = &txq->q;
59606ffa
SO		 676 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
677 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 678
679 if (reset)
680 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 681
682 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 683
684 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 685 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 686 NUM_TFD_CHUNKS);
687 return -EINVAL;
688 }
689
dbb6654c
WT		 690 tfd->tbs[count].addr = cpu_to_le32(addr);
691 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 692
693 count++;
694
695 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
696 TFD_CTL_PAD_SET(pad));
697
698 return 0;
699}
700
701/**
bb8c093b 702 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 703 *
704 * Does NOT advance any indexes
705 */
7aaa1d79 706void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 707{
59606ffa 708 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 709 int index = txq->q.read_ptr;
710 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 711 struct pci_dev *dev = priv->pci_dev;
712 int i;
713 int counter;
714
b481de9c 715 /* sanity check */
dbb6654c 716 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 717 if (counter > NUM_TFD_CHUNKS) {
15b1687c 718 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 719 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 720 return;
b481de9c
ZY		 721 }
722
fd9377ee
RC		 723 /* Unmap tx_cmd */
724 if (counter)
725 pci_unmap_single(dev,
c2acea8e
JB		 726 pci_unmap_addr(&txq->meta[index], mapping),
727 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 728 PCI_DMA_TODEVICE);
729
b481de9c
ZY		 730 /* unmap chunks if any */
731
732 for (i = 1; i < counter; i++) {
dbb6654c
WT		 733 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
734 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 735 if (txq->txb[txq->q.read_ptr].skb[0]) {
736 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
737 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 738 /* Can be called from interrupt context */
739 dev_kfree_skb_any(skb);
fc4b6853 740 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 741 }
742 }
743 }
7aaa1d79 744 return ;
b481de9c
ZY		 745}
746
b481de9c 747/**
bb8c093b 748 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 749 *
750*/
c2acea8e
JB		 751void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
752 struct iwl_device_cmd *cmd,
753 struct ieee80211_tx_info *info,
754 struct ieee80211_hdr *hdr,
755 int sta_id, int tx_id)
b481de9c 756{
e039fa4a 757 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
1d79e53c 758 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
b481de9c
ZY		 759 u16 rate_mask;
760 int rate;
761 u8 rts_retry_limit;
762 u8 data_retry_limit;
763 __le32 tx_flags;
fd7c8a40 764 __le16 fc = hdr->frame_control;
9744c91f 765 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 766
bb8c093b 767 rate = iwl3945_rates[rate_index].plcp;
9744c91f 768 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 769
770 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 771 * in this running context */
b481de9c
ZY		 772 rate_mask = IWL_RATES_MASK;
773
768db982
AK		 774
775 /* Set retry limit on DATA packets and Probe Responses*/
776 if (ieee80211_is_probe_resp(fc))
777 data_retry_limit = 3;
778 else
779 data_retry_limit = IWL_DEFAULT_TX_RETRY;
780 tx_cmd->data_retry_limit = data_retry_limit;
781
b481de9c
ZY		 782 if (tx_id >= IWL_CMD_QUEUE_NUM)
783 rts_retry_limit = 3;
784 else
785 rts_retry_limit = 7;
786
768db982
AK		 787 if (data_retry_limit < rts_retry_limit)
788 rts_retry_limit = data_retry_limit;
789 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 790
fd7c8a40
HH		 791 if (ieee80211_is_mgmt(fc)) {
792 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
793 case cpu_to_le16(IEEE80211_STYPE_AUTH):
794 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
795 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
796 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 797 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
798 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
799 tx_flags |= TX_CMD_FLG_CTS_MSK;
800 }
801 break;
802 default:
803 break;
804 }
805 }
806
9744c91f
AK		 807 tx_cmd->rate = rate;
808 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 809
810 /* OFDM */
9744c91f 811 tx_cmd->supp_rates[0] =
14577f23 812 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 813
814 /* CCK */
9744c91f 815 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 816
e1623446 817 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 818 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 819 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
820 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 821}
822
4a8a4322 823u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 824{
825 unsigned long flags_spin;
c587de0b 826 struct iwl_station_entry *station;
b481de9c
ZY		 827
828 if (sta_id == IWL_INVALID_STATION)
829 return IWL_INVALID_STATION;
830
831 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 832 station = &priv->stations[sta_id];
b481de9c
ZY		 833
834 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
835 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 836 station->sta.mode = STA_CONTROL_MODIFY_MSK;
837
838 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
839
c587de0b 840 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 841 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 842 sta_id, tx_rate);
843 return sta_id;
844}
845
854682ed 846static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 847{
854682ed 848 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 849 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 850 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 851 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
852 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 853
5d49f498 854 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 855 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
856 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 857 }
b481de9c 858 } else {
5d49f498 859 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 860 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
861 ~APMG_PS_CTRL_MSK_PWR_SRC);
862
5d49f498 863 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 864 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
865 }
b481de9c 866
a8b50a0a 867 return 0;
b481de9c
ZY		 868}
869
4a8a4322 870static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 871{
5d49f498 872 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 873 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 874 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
875 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 876 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
877 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
878 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
879 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
880 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
881 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
882 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
883 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 884
885 /* fake read to flush all prev I/O */
5d49f498 886 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 887
b481de9c
ZY		 888 return 0;
889}
890
4a8a4322 891static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 892{
b481de9c
ZY		 893
894 /* bypass mode */
5d49f498 895 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 896
897 /* RA 0 is active */
5d49f498 898 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 899
900 /* all 6 fifo are active */
5d49f498 901 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 902
5d49f498
AK		 903 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
904 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
905 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
906 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 907
5d49f498 908 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 909 priv->_3945.shared_phys);
b481de9c 910
5d49f498 911 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 912 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
913 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
914 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
915 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
916 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
917 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
918 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 919
b481de9c
ZY		 920
921 return 0;
922}
923
924/**
925 * iwl3945_txq_ctx_reset - Reset TX queue context
926 *
927 * Destroys all DMA structures and initialize them again
928 */
4a8a4322 929static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 930{
931 int rc;
932 int txq_id, slots_num;
933
bb8c093b 934 iwl3945_hw_txq_ctx_free(priv);
b481de9c 935
88804e2b
WYG		 936 /* allocate tx queue structure */
937 rc = iwl_alloc_txq_mem(priv);
938 if (rc)
939 return rc;
940
b481de9c
ZY		 941 /* Tx CMD queue */
942 rc = iwl3945_tx_reset(priv);
943 if (rc)
944 goto error;
945
946 /* Tx queue(s) */
5905a1aa 947 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 948 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
949 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 950 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
951 txq_id);
b481de9c 952 if (rc) {
15b1687c 953 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 954 goto error;
955 }
956 }
957
958 return rc;
959
960 error:
bb8c093b 961 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 962 return rc;
963}
964
fadb3582 965
f33269b8 966/*
fadb3582
BC		 967 * Start up 3945's basic functionality after it has been reset
968 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 969 * NOTE: This does not load uCode nor start the embedded processor
970 */
01ec616d 971static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 972{
fadb3582 973 int ret = iwl_apm_init(priv);
01ec616d 974
f33269b8
BC		 975 /* Clear APMG (NIC's internal power management) interrupts */
976 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
977 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
978
979 /* Reset radio chip */
980 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
981 udelay(5);
982 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
983
01ec616d
KA		 984 return ret;
985}
b481de9c 986
01ec616d
KA		 987static void iwl3945_nic_config(struct iwl_priv *priv)
988{
e6148917 989 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 990 unsigned long flags;
991 u8 rev_id = 0;
b481de9c 992
b481de9c
ZY		 993 spin_lock_irqsave(&priv->lock, flags);
994
43121432
AK		 995 /* Determine HW type */
996 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
997
998 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
999
b481de9c 1000 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
91dd6c27 1001 IWL_DEBUG_INFO(priv, "RTP type\n");
b481de9c 1002 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1003 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1004 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1005 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1006 } else {
e1623446 1007 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1008 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1009 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1010 }
1011
e6148917 1012 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1013 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1014 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1015 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1016 } else
e1623446 1017 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1018
e6148917 1019 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1020 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1021 eeprom->board_revision);
5d49f498 1022 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1023 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1024 } else {
e1623446 1025 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1026 eeprom->board_revision);
5d49f498 1027 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1028 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1029 }
1030
e6148917 1031 if (eeprom->almgor_m_version <= 1) {
5d49f498 1032 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1033 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1034 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1035 eeprom->almgor_m_version);
b481de9c 1036 } else {
e1623446 1037 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1038 eeprom->almgor_m_version);
5d49f498 1039 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1040 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1041 }
1042 spin_unlock_irqrestore(&priv->lock, flags);
1043
e6148917 1044 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1045 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1046
e6148917 1047 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1048 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1049}
1050
1051int iwl3945_hw_nic_init(struct iwl_priv *priv)
1052{
01ec616d
KA		 1053 int rc;
1054 unsigned long flags;
1055 struct iwl_rx_queue *rxq = &priv->rxq;
1056
1057 spin_lock_irqsave(&priv->lock, flags);
1058 priv->cfg->ops->lib->apm_ops.init(priv);
1059 spin_unlock_irqrestore(&priv->lock, flags);
1060
854682ed 1061 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1062 if (rc)
854682ed
KA		 1063 return rc;
1064
01ec616d 1065 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1066
1067 /* Allocate the RX queue, or reset if it is already allocated */
1068 if (!rxq->bd) {
51af3d3f 1069 rc = iwl_rx_queue_alloc(priv);
b481de9c 1070 if (rc) {
15b1687c 1071 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1072 return -ENOMEM;
1073 }
1074 } else
df833b1d 1075 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1076
bb8c093b 1077 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1078
1079 iwl3945_rx_init(priv, rxq);
1080
b481de9c
ZY		 1081
1082 /* Look at using this instead:
1083 rxq->need_update = 1;
141c43a3 1084 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1085 */
1086
5d49f498 1087 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1088
1089 rc = iwl3945_txq_ctx_reset(priv);
1090 if (rc)
1091 return rc;
1092
1093 set_bit(STATUS_INIT, &priv->status);
1094
1095 return 0;
1096}
1097
1098/**
bb8c093b 1099 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1100 *
1101 * Destroy all TX DMA queues and structures
1102 */
4a8a4322 1103void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1104{
1105 int txq_id;
1106
1107 /* Tx queues */
88804e2b
WYG		 1108 if (priv->txq)
1109 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1110 txq_id++)
1111 if (txq_id == IWL_CMD_QUEUE_NUM)
1112 iwl_cmd_queue_free(priv);
1113 else
1114 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1115
88804e2b
WYG		 1116 /* free tx queue structure */
1117 iwl_free_txq_mem(priv);
b481de9c
ZY		 1118}
1119
4a8a4322 1120void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1121{
bddadf86 1122 int txq_id;
b481de9c
ZY		 1123
1124 /* stop SCD */
5d49f498 1125 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1126 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1127
1128 /* reset TFD queues */
5905a1aa 1129 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1130 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1131 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1132 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1133 1000);
1134 }
1135
bb8c093b 1136 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1137}
1138
b481de9c 1139/**
bb8c093b 1140 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1141 * return index delta into power gain settings table
1142*/
bb8c093b 1143static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1144{
1145 return (new_reading - old_reading) * (-11) / 100;
1146}
1147
1148/**
bb8c093b 1149 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1150 */
bb8c093b 1151static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1152{
3ac7f146 1153 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1154}
1155
4a8a4322 1156int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1157{
5d49f498 1158 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1159}
1160
1161/**
bb8c093b 1162 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1163 * get the current temperature by reading from NIC
1164*/
4a8a4322 1165static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1166{
e6148917 1167 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1168 int temperature;
1169
bb8c093b 1170 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1171
1172 /* driver's okay range is -260 to +25.
1173 * human readable okay range is 0 to +285 */
e1623446 1174 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1175
1176 /* handle insane temp reading */
bb8c093b 1177 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1178 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1179
1180 /* if really really hot(?),
1181 * substitute the 3rd band/group's temp measured at factory */
1182 if (priv->last_temperature > 100)
e6148917 1183 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1184 else /* else use most recent "sane" value from driver */
1185 temperature = priv->last_temperature;
1186 }
1187
1188 return temperature; /* raw, not "human readable" */
1189}
1190
1191/* Adjust Txpower only if temperature variance is greater than threshold.
1192 *
1193 * Both are lower than older versions' 9 degrees */
1194#define IWL_TEMPERATURE_LIMIT_TIMER 6
1195
1196/**
1197 * is_temp_calib_needed - determines if new calibration is needed
1198 *
1199 * records new temperature in tx_mgr->temperature.
1200 * replaces tx_mgr->last_temperature *only* if calib needed
1201 * (assumes caller will actually do the calibration!). */
4a8a4322 1202static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1203{
1204 int temp_diff;
1205
bb8c093b 1206 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1207 temp_diff = priv->temperature - priv->last_temperature;
1208
1209 /* get absolute value */
1210 if (temp_diff < 0) {
e1623446 1211 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1212 temp_diff = -temp_diff;
1213 } else if (temp_diff == 0)
e1623446 1214 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1215 else
e1623446 1216 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1217
1218 /* if we don't need calibration, *don't* update last_temperature */
1219 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1220 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1221 return 0;
1222 }
1223
e1623446 1224 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1225
1226 /* assume that caller will actually do calib ...
1227 * update the "last temperature" value */
1228 priv->last_temperature = priv->temperature;
1229 return 1;
1230}
1231
1232#define IWL_MAX_GAIN_ENTRIES 78
1233#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1234#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1235
1236/* radio and DSP power table, each step is 1/2 dB.
1237 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1238static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1239 {
1240 {251, 127}, /* 2.4 GHz, highest power */
1241 {251, 127},
1242 {251, 127},
1243 {251, 127},
1244 {251, 125},
1245 {251, 110},
1246 {251, 105},
1247 {251, 98},
1248 {187, 125},
1249 {187, 115},
1250 {187, 108},
1251 {187, 99},
1252 {243, 119},
1253 {243, 111},
1254 {243, 105},
1255 {243, 97},
1256 {243, 92},
1257 {211, 106},
1258 {211, 100},
1259 {179, 120},
1260 {179, 113},
1261 {179, 107},
1262 {147, 125},
1263 {147, 119},
1264 {147, 112},
1265 {147, 106},
1266 {147, 101},
1267 {147, 97},
1268 {147, 91},
1269 {115, 107},
1270 {235, 121},
1271 {235, 115},
1272 {235, 109},
1273 {203, 127},
1274 {203, 121},
1275 {203, 115},
1276 {203, 108},
1277 {203, 102},
1278 {203, 96},
1279 {203, 92},
1280 {171, 110},
1281 {171, 104},
1282 {171, 98},
1283 {139, 116},
1284 {227, 125},
1285 {227, 119},
1286 {227, 113},
1287 {227, 107},
1288 {227, 101},
1289 {227, 96},
1290 {195, 113},
1291 {195, 106},
1292 {195, 102},
1293 {195, 95},
1294 {163, 113},
1295 {163, 106},
1296 {163, 102},
1297 {163, 95},
1298 {131, 113},
1299 {131, 106},
1300 {131, 102},
1301 {131, 95},
1302 {99, 113},
1303 {99, 106},
1304 {99, 102},
1305 {99, 95},
1306 {67, 113},
1307 {67, 106},
1308 {67, 102},
1309 {67, 95},
1310 {35, 113},
1311 {35, 106},
1312 {35, 102},
1313 {35, 95},
1314 {3, 113},
1315 {3, 106},
1316 {3, 102},
1317 {3, 95} }, /* 2.4 GHz, lowest power */
1318 {
1319 {251, 127}, /* 5.x GHz, highest power */
1320 {251, 120},
1321 {251, 114},
1322 {219, 119},
1323 {219, 101},
1324 {187, 113},
1325 {187, 102},
1326 {155, 114},
1327 {155, 103},
1328 {123, 117},
1329 {123, 107},
1330 {123, 99},
1331 {123, 92},
1332 {91, 108},
1333 {59, 125},
1334 {59, 118},
1335 {59, 109},
1336 {59, 102},
1337 {59, 96},
1338 {59, 90},
1339 {27, 104},
1340 {27, 98},
1341 {27, 92},
1342 {115, 118},
1343 {115, 111},
1344 {115, 104},
1345 {83, 126},
1346 {83, 121},
1347 {83, 113},
1348 {83, 105},
1349 {83, 99},
1350 {51, 118},
1351 {51, 111},
1352 {51, 104},
1353 {51, 98},
1354 {19, 116},
1355 {19, 109},
1356 {19, 102},
1357 {19, 98},
1358 {19, 93},
1359 {171, 113},
1360 {171, 107},
1361 {171, 99},
1362 {139, 120},
1363 {139, 113},
1364 {139, 107},
1365 {139, 99},
1366 {107, 120},
1367 {107, 113},
1368 {107, 107},
1369 {107, 99},
1370 {75, 120},
1371 {75, 113},
1372 {75, 107},
1373 {75, 99},
1374 {43, 120},
1375 {43, 113},
1376 {43, 107},
1377 {43, 99},
1378 {11, 120},
1379 {11, 113},
1380 {11, 107},
1381 {11, 99},
1382 {131, 107},
1383 {131, 99},
1384 {99, 120},
1385 {99, 113},
1386 {99, 107},
1387 {99, 99},
1388 {67, 120},
1389 {67, 113},
1390 {67, 107},
1391 {67, 99},
1392 {35, 120},
1393 {35, 113},
1394 {35, 107},
1395 {35, 99},
1396 {3, 120} } /* 5.x GHz, lowest power */
1397};
1398
bb8c093b 1399static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1400{
1401 if (index < 0)
1402 return 0;
1403 if (index >= IWL_MAX_GAIN_ENTRIES)
1404 return IWL_MAX_GAIN_ENTRIES - 1;
1405 return (u8) index;
1406}
1407
1408/* Kick off thermal recalibration check every 60 seconds */
1409#define REG_RECALIB_PERIOD (60)
1410
1411/**
bb8c093b 1412 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1413 *
1414 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1415 * or 6 Mbit (OFDM) rates.
1416 */
4a8a4322 1417static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1418 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1419 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1420 int band_index)
1421{
bb8c093b 1422 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1423 s8 power;
1424 u8 power_index;
1425
1426 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1427
1428 /* use this channel group's 6Mbit clipping/saturation pwr,
1429 * but cap at regulatory scan power restriction (set during init
1430 * based on eeprom channel data) for this channel. */
14577f23 1431 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1432
1433 /* further limit to user's max power preference.
1434 * FIXME: Other spectrum management power limitations do not
1435 * seem to apply?? */
62ea9c5b 1436 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1437 scan_power_info->requested_power = power;
1438
1439 /* find difference between new scan *power* and current "normal"
1440 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1441 * current "normal" temperature-compensated Tx power *index* for
1442 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1443 * *index*. */
1444 power_index = ch_info->power_info[rate_index].power_table_index
1445 - (power - ch_info->power_info
14577f23 1446 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1447
1448 /* store reference index that we use when adjusting *all* scan
1449 * powers. So we can accommodate user (all channel) or spectrum
1450 * management (single channel) power changes "between" temperature
1451 * feedback compensation procedures.
1452 * don't force fit this reference index into gain table; it may be a
1453 * negative number. This will help avoid errors when we're at
1454 * the lower bounds (highest gains, for warmest temperatures)
1455 * of the table. */
1456
1457 /* don't exceed table bounds for "real" setting */
bb8c093b 1458 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1459
1460 scan_power_info->power_table_index = power_index;
1461 scan_power_info->tpc.tx_gain =
1462 power_gain_table[band_index][power_index].tx_gain;
1463 scan_power_info->tpc.dsp_atten =
1464 power_gain_table[band_index][power_index].dsp_atten;
1465}
1466
1467/**
75bcfae9 1468 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1469 *
1470 * Configures power settings for all rates for the current channel,
1471 * using values from channel info struct, and send to NIC
1472 */
dfb39e82 1473static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1474{
14577f23 1475 int rate_idx, i;
d20b3c65 1476 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1477 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1478 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1479 };
1480
8318d78a 1481 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1482 ch_info = iwl_get_channel_info(priv,
8318d78a 1483 priv->band,
8ccde88a 1484 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1485 if (!ch_info) {
15b1687c
WT		 1486 IWL_ERR(priv,
1487 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1488 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1489 return -EINVAL;
1490 }
1491
1492 if (!is_channel_valid(ch_info)) {
e1623446 1493 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1494 "non-Tx channel.\n");
1495 return 0;
1496 }
1497
1498 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1499 /* Fill OFDM rate */
1500 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1501 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1502
1503 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1504 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1505
e1623446 1506 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1507 le16_to_cpu(txpower.channel),
1508 txpower.band,
14577f23
MA		 1509 txpower.power[i].tpc.tx_gain,
1510 txpower.power[i].tpc.dsp_atten,
1511 txpower.power[i].rate);
1512 }
1513 /* Fill CCK rates */
1514 for (rate_idx = IWL_FIRST_CCK_RATE;
1515 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1516 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1517 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1518
e1623446 1519 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1520 le16_to_cpu(txpower.channel),
1521 txpower.band,
1522 txpower.power[i].tpc.tx_gain,
1523 txpower.power[i].tpc.dsp_atten,
1524 txpower.power[i].rate);
b481de9c
ZY		 1525 }
1526
518099a8
SO		 1527 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1528 sizeof(struct iwl3945_txpowertable_cmd),
1529 &txpower);
b481de9c
ZY		 1530
1531}
1532
1533/**
bb8c093b 1534 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1535 * @ch_info: Channel to update. Uses power_info.requested_power.
1536 *
1537 * Replace requested_power and base_power_index ch_info fields for
1538 * one channel.
1539 *
1540 * Called if user or spectrum management changes power preferences.
1541 * Takes into account h/w and modulation limitations (clip power).
1542 *
1543 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1544 *
1545 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1546 * properly fill out the scan powers, and actual h/w gain settings,
1547 * and send changes to NIC
1548 */
4a8a4322 1549static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1550 struct iwl_channel_info *ch_info)
b481de9c 1551{
bb8c093b 1552 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1553 int power_changed = 0;
1554 int i;
1555 const s8 *clip_pwrs;
1556 int power;
1557
1558 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1559 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1560
1561 /* Get this channel's rate-to-current-power settings table */
1562 power_info = ch_info->power_info;
1563
1564 /* update OFDM Txpower settings */
14577f23 1565 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1566 i++, ++power_info) {
1567 int delta_idx;
1568
1569 /* limit new power to be no more than h/w capability */
1570 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1571 if (power == power_info->requested_power)
1572 continue;
1573
1574 /* find difference between old and new requested powers,
1575 * update base (non-temp-compensated) power index */
1576 delta_idx = (power - power_info->requested_power) * 2;
1577 power_info->base_power_index -= delta_idx;
1578
1579 /* save new requested power value */
1580 power_info->requested_power = power;
1581
1582 power_changed = 1;
1583 }
1584
1585 /* update CCK Txpower settings, based on OFDM 12M setting ...
1586 * ... all CCK power settings for a given channel are the *same*. */
1587 if (power_changed) {
1588 power =
14577f23 1589 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1590 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1591
bb8c093b 1592 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1593 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1594 power_info->requested_power = power;
1595 power_info->base_power_index =
14577f23 1596 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1597 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1598 ++power_info;
1599 }
1600 }
1601
1602 return 0;
1603}
1604
1605/**
bb8c093b 1606 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1607 *
1608 * NOTE: Returned power limit may be less (but not more) than requested,
1609 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1610 * (no consideration for h/w clipping limitations).
1611 */
d20b3c65 1612static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1613{
1614 s8 max_power;
1615
1616#if 0
1617 /* if we're using TGd limits, use lower of TGd or EEPROM */
1618 if (ch_info->tgd_data.max_power != 0)
1619 max_power = min(ch_info->tgd_data.max_power,
1620 ch_info->eeprom.max_power_avg);
1621
1622 /* else just use EEPROM limits */
1623 else
1624#endif
1625 max_power = ch_info->eeprom.max_power_avg;
1626
1627 return min(max_power, ch_info->max_power_avg);
1628}
1629
1630/**
bb8c093b 1631 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1632 *
1633 * Compensate txpower settings of *all* channels for temperature.
1634 * This only accounts for the difference between current temperature
1635 * and the factory calibration temperatures, and bases the new settings
1636 * on the channel's base_power_index.
1637 *
1638 * If RxOn is "associated", this sends the new Txpower to NIC!
1639 */
4a8a4322 1640static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1641{
d20b3c65 1642 struct iwl_channel_info *ch_info = NULL;
e6148917 1643 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1644 int delta_index;
1645 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1646 u8 a_band;
1647 u8 rate_index;
1648 u8 scan_tbl_index;
1649 u8 i;
1650 int ref_temp;
1651 int temperature = priv->temperature;
1652
1653 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1654 for (i = 0; i < priv->channel_count; i++) {
1655 ch_info = &priv->channel_info[i];
1656 a_band = is_channel_a_band(ch_info);
1657
1658 /* Get this chnlgrp's factory calibration temperature */
e6148917 1659 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1660 temperature;
1661
a96a27f9 1662 /* get power index adjustment based on current and factory
b481de9c 1663 * temps */
bb8c093b 1664 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1665 ref_temp);
1666
1667 /* set tx power value for all rates, OFDM and CCK */
1668 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1669 rate_index++) {
1670 int power_idx =
1671 ch_info->power_info[rate_index].base_power_index;
1672
1673 /* temperature compensate */
1674 power_idx += delta_index;
1675
1676 /* stay within table range */
bb8c093b 1677 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1678 ch_info->power_info[rate_index].
1679 power_table_index = (u8) power_idx;
1680 ch_info->power_info[rate_index].tpc =
1681 power_gain_table[a_band][power_idx];
1682 }
1683
1684 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1685 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1686
1687 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1688 for (scan_tbl_index = 0;
1689 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1690 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1691 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1692 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1693 actual_index, clip_pwrs,
1694 ch_info, a_band);
1695 }
1696 }
1697
1698 /* send Txpower command for current channel to ucode */
75bcfae9 1699 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1700}
1701
4a8a4322 1702int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1703{
d20b3c65 1704 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1705 s8 max_power;
1706 u8 a_band;
1707 u8 i;
1708
62ea9c5b 1709 if (priv->tx_power_user_lmt == power) {
e1623446 1710 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1711 "limit: %ddBm.\n", power);
1712 return 0;
1713 }
1714
e1623446 1715 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1716 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1717
1718 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1719
1720 for (i = 0; i < priv->channel_count; i++) {
1721 ch_info = &priv->channel_info[i];
1722 a_band = is_channel_a_band(ch_info);
1723
1724 /* find minimum power of all user and regulatory constraints
1725 * (does not consider h/w clipping limitations) */
bb8c093b 1726 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1727 max_power = min(power, max_power);
1728 if (max_power != ch_info->curr_txpow) {
1729 ch_info->curr_txpow = max_power;
1730
1731 /* this considers the h/w clipping limitations */
bb8c093b 1732 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1733 }
1734 }
1735
1736 /* update txpower settings for all channels,
1737 * send to NIC if associated. */
1738 is_temp_calib_needed(priv);
bb8c093b 1739 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1740
1741 return 0;
1742}
1743
5bbe233b
AK		 1744static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1745{
1746 int rc = 0;
2f301227 1747 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1748 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1749 struct iwl_host_cmd cmd = {
1750 .id = REPLY_RXON_ASSOC,
1751 .len = sizeof(rxon_assoc),
c2acea8e 1752 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1753 .data = &rxon_assoc,
1754 };
1755 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1756 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1757
1758 if ((rxon1->flags == rxon2->flags) &&
1759 (rxon1->filter_flags == rxon2->filter_flags) &&
1760 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1761 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1762 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1763 return 0;
1764 }
1765
1766 rxon_assoc.flags = priv->staging_rxon.flags;
1767 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1768 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1769 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1770 rxon_assoc.reserved = 0;
1771
1772 rc = iwl_send_cmd_sync(priv, &cmd);
1773 if (rc)
1774 return rc;
1775
2f301227
ZY		 1776 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1777 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1778 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1779 rc = -EIO;
1780 }
1781
64a76b50 1782 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1783
1784 return rc;
1785}
1786
e0158e61
AK		 1787/**
1788 * iwl3945_commit_rxon - commit staging_rxon to hardware
1789 *
1790 * The RXON command in staging_rxon is committed to the hardware and
1791 * the active_rxon structure is updated with the new data. This
1792 * function correctly transitions out of the RXON_ASSOC_MSK state if
1793 * a HW tune is required based on the RXON structure changes.
1794 */
1795static int iwl3945_commit_rxon(struct iwl_priv *priv)
1796{
1797 /* cast away the const for active_rxon in this function */
1798 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1799 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1800 int rc = 0;
1801 bool new_assoc =
1802 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1803
1804 if (!iwl_is_alive(priv))
1805 return -1;
1806
1807 /* always get timestamp with Rx frame */
1808 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1809
1810 /* select antenna */
1811 staging_rxon->flags &=
1812 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1813 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1814
1815 rc = iwl_check_rxon_cmd(priv);
1816 if (rc) {
1817 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1818 return -EINVAL;
1819 }
1820
1821 /* If we don't need to send a full RXON, we can use
1822 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1823 * and other flags for the current radio configuration. */
1824 if (!iwl_full_rxon_required(priv)) {
1825 rc = iwl_send_rxon_assoc(priv);
1826 if (rc) {
1827 IWL_ERR(priv, "Error setting RXON_ASSOC "
1828 "configuration (%d).\n", rc);
1829 return rc;
1830 }
1831
1832 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1833
1834 return 0;
1835 }
1836
1837 /* If we are currently associated and the new config requires
1838 * an RXON_ASSOC and the new config wants the associated mask enabled,
1839 * we must clear the associated from the active configuration
1840 * before we apply the new config */
1841 if (iwl_is_associated(priv) && new_assoc) {
1842 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1843 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1844
1845 /*
1846 * reserved4 and 5 could have been filled by the iwlcore code.
1847 * Let's clear them before pushing to the 3945.
1848 */
1849 active_rxon->reserved4 = 0;
1850 active_rxon->reserved5 = 0;
1851 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1852 sizeof(struct iwl3945_rxon_cmd),
1853 &priv->active_rxon);
1854
1855 /* If the mask clearing failed then we set
1856 * active_rxon back to what it was previously */
1857 if (rc) {
1858 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1859 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1860 "configuration (%d).\n", rc);
1861 return rc;
1862 }
7e246191
RC		 1863 iwl_clear_ucode_stations(priv, false);
1864 iwl_restore_stations(priv);
e0158e61
AK		 1865 }
1866
1867 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1868 "* with%s RXON_FILTER_ASSOC_MSK\n"
1869 "* channel = %d\n"
1870 "* bssid = %pM\n",
1871 (new_assoc ? "" : "out"),
1872 le16_to_cpu(staging_rxon->channel),
1873 staging_rxon->bssid_addr);
1874
1875 /*
1876 * reserved4 and 5 could have been filled by the iwlcore code.
1877 * Let's clear them before pushing to the 3945.
1878 */
1879 staging_rxon->reserved4 = 0;
1880 staging_rxon->reserved5 = 0;
1881
90e8e424 1882 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1883
1884 /* Apply the new configuration */
1885 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1886 sizeof(struct iwl3945_rxon_cmd),
1887 staging_rxon);
1888 if (rc) {
1889 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1890 return rc;
1891 }
1892
1893 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1894
7e246191
RC		 1895 if (!new_assoc) {
1896 iwl_clear_ucode_stations(priv, false);
1897 iwl_restore_stations(priv);
1898 }
e0158e61
AK		 1899
1900 /* If we issue a new RXON command which required a tune then we must
1901 * send a new TXPOWER command or we won't be able to Tx any frames */
1902 rc = priv->cfg->ops->lib->send_tx_power(priv);
1903 if (rc) {
1904 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1905 return rc;
1906 }
1907
e0158e61
AK		 1908 /* Init the hardware's rate fallback order based on the band */
1909 rc = iwl3945_init_hw_rate_table(priv);
1910 if (rc) {
1911 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1912 return -EIO;
1913 }
1914
1915 return 0;
1916}
1917
b481de9c
ZY		 1918/**
1919 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1920 *
1921 * -- reset periodic timer
1922 * -- see if temp has changed enough to warrant re-calibration ... if so:
1923 * -- correct coeffs for temp (can reset temp timer)
1924 * -- save this temp as "last",
1925 * -- send new set of gain settings to NIC
1926 * NOTE: This should continue working, even when we're not associated,
1927 * so we can keep our internal table of scan powers current. */
4a8a4322 1928void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1929{
1930 /* This will kick in the "brute force"
bb8c093b 1931 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1932 if (!is_temp_calib_needed(priv))
1933 goto reschedule;
1934
1935 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1936 * This is based *only* on current temperature,
1937 * ignoring any previous power measurements */
bb8c093b 1938 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1939
1940 reschedule:
1941 queue_delayed_work(priv->workqueue,
ee525d13 1942 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 1943}
1944
416e1438 1945static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1946{
4a8a4322 1947 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 1948 _3945.thermal_periodic.work);
b481de9c
ZY		 1949
1950 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1951 return;
1952
1953 mutex_lock(&priv->mutex);
1954 iwl3945_reg_txpower_periodic(priv);
1955 mutex_unlock(&priv->mutex);
1956}
1957
1958/**
bb8c093b 1959 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1960 * for the channel.
1961 *
1962 * This function is used when initializing channel-info structs.
1963 *
1964 * NOTE: These channel groups do *NOT* match the bands above!
1965 * These channel groups are based on factory-tested channels;
1966 * on A-band, EEPROM's "group frequency" entries represent the top
1967 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1968 */
4a8a4322 1969static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 1970 const struct iwl_channel_info *ch_info)
b481de9c 1971{
e6148917
SO		 1972 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1973 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 1974 u8 group;
1975 u16 group_index = 0; /* based on factory calib frequencies */
1976 u8 grp_channel;
1977
1978 /* Find the group index for the channel ... don't use index 1(?) */
1979 if (is_channel_a_band(ch_info)) {
1980 for (group = 1; group < 5; group++) {
1981 grp_channel = ch_grp[group].group_channel;
1982 if (ch_info->channel <= grp_channel) {
1983 group_index = group;
1984 break;
1985 }
1986 }
1987 /* group 4 has a few channels *above* its factory cal freq */
1988 if (group == 5)
1989 group_index = 4;
1990 } else
1991 group_index = 0; /* 2.4 GHz, group 0 */
1992
e1623446 1993 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 1994 group_index);
1995 return group_index;
1996}
1997
1998/**
bb8c093b 1999 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2000 *
2001 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2002 * into radio/DSP gain settings table for requested power.
2003 */
4a8a4322 2004static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2005 s8 requested_power,
2006 s32 setting_index, s32 *new_index)
2007{
bb8c093b 2008 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2009 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2010 s32 index0, index1;
2011 s32 power = 2 * requested_power;
2012 s32 i;
bb8c093b 2013 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2014 s32 gains0, gains1;
2015 s32 res;
2016 s32 denominator;
2017
e6148917 2018 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2019 samples = chnl_grp->samples;
2020 for (i = 0; i < 5; i++) {
2021 if (power == samples[i].power) {
2022 *new_index = samples[i].gain_index;
2023 return 0;
2024 }
2025 }
2026
2027 if (power > samples[1].power) {
2028 index0 = 0;
2029 index1 = 1;
2030 } else if (power > samples[2].power) {
2031 index0 = 1;
2032 index1 = 2;
2033 } else if (power > samples[3].power) {
2034 index0 = 2;
2035 index1 = 3;
2036 } else {
2037 index0 = 3;
2038 index1 = 4;
2039 }
2040
2041 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2042 if (denominator == 0)
2043 return -EINVAL;
2044 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2045 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2046 res = gains0 + (gains1 - gains0) *
2047 ((s32) power - (s32) samples[index0].power) / denominator +
2048 (1 << 18);
2049 *new_index = res >> 19;
2050 return 0;
2051}
2052
4a8a4322 2053static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2054{
2055 u32 i;
2056 s32 rate_index;
e6148917 2057 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2058 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2059
e1623446 2060 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2061
2062 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2063 s8 *clip_pwrs; /* table of power levels for each rate */
2064 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2065 group = &eeprom->groups[i];
b481de9c
ZY		 2066
2067 /* sanity check on factory saturation power value */
2068 if (group->saturation_power < 40) {
39aadf8c 2069 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2070 "less than minimum expected 40\n",
2071 group->saturation_power);
2072 return;
2073 }
2074
2075 /*
2076 * Derive requested power levels for each rate, based on
2077 * hardware capabilities (saturation power for band).
2078 * Basic value is 3dB down from saturation, with further
2079 * power reductions for highest 3 data rates. These
2080 * backoffs provide headroom for high rate modulation
2081 * power peaks, without too much distortion (clipping).
2082 */
2083 /* we'll fill in this array with h/w max power levels */
67d613ae 2084 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2085
2086 /* divide factory saturation power by 2 to find -3dB level */
2087 satur_pwr = (s8) (group->saturation_power >> 1);
2088
2089 /* fill in channel group's nominal powers for each rate */
2090 for (rate_index = 0;
1d79e53c 2091 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
b481de9c 2092 switch (rate_index) {
14577f23 2093 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2094 if (i == 0) /* B/G */
2095 *clip_pwrs = satur_pwr;
2096 else /* A */
2097 *clip_pwrs = satur_pwr - 5;
2098 break;
14577f23 2099 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2100 if (i == 0)
2101 *clip_pwrs = satur_pwr - 7;
2102 else
2103 *clip_pwrs = satur_pwr - 10;
2104 break;
14577f23 2105 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2106 if (i == 0)
2107 *clip_pwrs = satur_pwr - 9;
2108 else
2109 *clip_pwrs = satur_pwr - 12;
2110 break;
2111 default:
2112 *clip_pwrs = satur_pwr;
2113 break;
2114 }
2115 }
2116 }
2117}
2118
2119/**
2120 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2121 *
2122 * Second pass (during init) to set up priv->channel_info
2123 *
2124 * Set up Tx-power settings in our channel info database for each VALID
2125 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2126 * and current temperature.
2127 *
2128 * Since this is based on current temperature (at init time), these values may
2129 * not be valid for very long, but it gives us a starting/default point,
2130 * and allows us to active (i.e. using Tx) scan.
2131 *
2132 * This does *not* write values to NIC, just sets up our internal table.
2133 */
4a8a4322 2134int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2135{
d20b3c65 2136 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2137 struct iwl3945_channel_power_info *pwr_info;
e6148917 2138 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2139 int delta_index;
2140 u8 rate_index;
2141 u8 scan_tbl_index;
2142 const s8 *clip_pwrs; /* array of power levels for each rate */
2143 u8 gain, dsp_atten;
2144 s8 power;
2145 u8 pwr_index, base_pwr_index, a_band;
2146 u8 i;
2147 int temperature;
2148
2149 /* save temperature reference,
2150 * so we can determine next time to calibrate */
bb8c093b 2151 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2152 priv->last_temperature = temperature;
2153
bb8c093b 2154 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2155
2156 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2157 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2158 i++, ch_info++) {
2159 a_band = is_channel_a_band(ch_info);
2160 if (!is_channel_valid(ch_info))
2161 continue;
2162
2163 /* find this channel's channel group (*not* "band") index */
2164 ch_info->group_index =
bb8c093b 2165 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2166
2167 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2168 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2169
2170 /* calculate power index *adjustment* value according to
2171 * diff between current temperature and factory temperature */
bb8c093b 2172 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2173 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2174 temperature);
2175
e1623446 2176 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2177 ch_info->channel, delta_index, temperature +
2178 IWL_TEMP_CONVERT);
2179
2180 /* set tx power value for all OFDM rates */
2181 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2182 rate_index++) {
25a4ccea 2183 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2184 int rc;
2185
2186 /* use channel group's clip-power table,
2187 * but don't exceed channel's max power */
2188 s8 pwr = min(ch_info->max_power_avg,
2189 clip_pwrs[rate_index]);
2190
2191 pwr_info = &ch_info->power_info[rate_index];
2192
2193 /* get base (i.e. at factory-measured temperature)
2194 * power table index for this rate's power */
bb8c093b 2195 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2196 ch_info->group_index,
2197 &power_idx);
2198 if (rc) {
15b1687c 2199 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2200 return rc;
2201 }
2202 pwr_info->base_power_index = (u8) power_idx;
2203
2204 /* temperature compensate */
2205 power_idx += delta_index;
2206
2207 /* stay within range of gain table */
bb8c093b 2208 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2209
bb8c093b 2210 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2211 pwr_info->requested_power = pwr;
2212 pwr_info->power_table_index = (u8) power_idx;
2213 pwr_info->tpc.tx_gain =
2214 power_gain_table[a_band][power_idx].tx_gain;
2215 pwr_info->tpc.dsp_atten =
2216 power_gain_table[a_band][power_idx].dsp_atten;
2217 }
2218
2219 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2220 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2221 power = pwr_info->requested_power +
2222 IWL_CCK_FROM_OFDM_POWER_DIFF;
2223 pwr_index = pwr_info->power_table_index +
2224 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2225 base_pwr_index = pwr_info->base_power_index +
2226 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2227
2228 /* stay within table range */
bb8c093b 2229 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2230 gain = power_gain_table[a_band][pwr_index].tx_gain;
2231 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2232
bb8c093b 2233 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2234 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2235 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2236 for (rate_index = 0;
2237 rate_index < IWL_CCK_RATES; rate_index++) {
2238 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2239 pwr_info->requested_power = power;
2240 pwr_info->power_table_index = pwr_index;
2241 pwr_info->base_power_index = base_pwr_index;
2242 pwr_info->tpc.tx_gain = gain;
2243 pwr_info->tpc.dsp_atten = dsp_atten;
2244 }
2245
2246 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2247 for (scan_tbl_index = 0;
2248 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2249 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2250 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2251 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2252 actual_index, clip_pwrs, ch_info, a_band);
2253 }
2254 }
2255
2256 return 0;
2257}
2258
4a8a4322 2259int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2260{
2261 int rc;
b481de9c 2262
5d49f498
AK		 2263 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2264 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2265 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2266 if (rc < 0)
15b1687c 2267 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2268
b481de9c
ZY		 2269 return 0;
2270}
2271
188cf6c7 2272int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2273{
b481de9c
ZY		 2274 int txq_id = txq->q.id;
2275
ee525d13 2276 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2277
2278 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2279
5d49f498
AK		 2280 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2281 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2282
5d49f498 2283 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2284 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2285 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2286 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2287 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2288 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2289
2290 /* fake read to flush all prev. writes */
5d49f498 2291 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2292
2293 return 0;
2294}
2295
42427b4e
KA		 2296/*
2297 * HCMD utils
2298 */
2299static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2300{
2301 switch (cmd_id) {
2302 case REPLY_RXON:
d25aabb0
WT		 2303 return sizeof(struct iwl3945_rxon_cmd);
2304 case POWER_TABLE_CMD:
2305 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2306 default:
2307 return len;
2308 }
2309}
2310
c587de0b 2311
17f841cd
SO		 2312static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2313{
c587de0b
TW		 2314 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2315 addsta->mode = cmd->mode;
2316 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2317 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2318 addsta->station_flags = cmd->station_flags;
2319 addsta->station_flags_msk = cmd->station_flags_msk;
2320 addsta->tid_disable_tx = cpu_to_le16(0);
2321 addsta->rate_n_flags = cmd->rate_n_flags;
2322 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2323 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2324 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2325
2326 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2327}
2328
c587de0b 2329
b481de9c
ZY		 2330/**
2331 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2332 */
4a8a4322 2333int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2334{
14577f23 2335 int rc, i, index, prev_index;
bb8c093b 2336 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2337 .reserved = {0, 0, 0},
2338 };
bb8c093b 2339 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2340
bb8c093b
CH		 2341 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2342 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2343
2344 table[index].rate_n_flags =
bb8c093b 2345 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2346 table[index].try_cnt = priv->retry_rate;
bb8c093b 2347 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2348 table[index].next_rate_index =
2349 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2350 }
2351
8318d78a
JB		 2352 switch (priv->band) {
2353 case IEEE80211_BAND_5GHZ:
e1623446 2354 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2355 /* If one of the following CCK rates is used,
2356 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2357 for (i = IWL_RATE_1M_INDEX_TABLE;
2358 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2359 table[i].next_rate_index =
2360 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2361
2362 /* Don't fall back to CCK rates */
7262796a
AM		 2363 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2364 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2365
2366 /* Don't drop out of OFDM rates */
14577f23 2367 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2368 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2369 break;
2370
8318d78a 2371 case IEEE80211_BAND_2GHZ:
e1623446 2372 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2373 /* If an OFDM rate is used, have it fall back to the
2374 * 1M CCK rates */
b481de9c 2375
ee525d13 2376 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2377 iwl_is_associated(priv)) {
7262796a
AM		 2378
2379 index = IWL_FIRST_CCK_RATE;
2380 for (i = IWL_RATE_6M_INDEX_TABLE;
2381 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2382 table[i].next_rate_index =
2383 iwl3945_rates[index].table_rs_index;
2384
2385 index = IWL_RATE_11M_INDEX_TABLE;
2386 /* CCK shouldn't fall back to OFDM... */
2387 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2388 }
b481de9c
ZY		 2389 break;
2390
2391 default:
8318d78a 2392 WARN_ON(1);
b481de9c
ZY		 2393 break;
2394 }
2395
2396 /* Update the rate scaling for control frame Tx */
2397 rate_cmd.table_id = 0;
518099a8 2398 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2399 &rate_cmd);
2400 if (rc)
2401 return rc;
2402
2403 /* Update the rate scaling for data frame Tx */
2404 rate_cmd.table_id = 1;
518099a8 2405 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2406 &rate_cmd);
2407}
2408
796083cb 2409/* Called when initializing driver */
4a8a4322 2410int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2411{
3832ec9d
AK		 2412 memset((void *)&priv->hw_params, 0,
2413 sizeof(struct iwl_hw_params));
b481de9c 2414
ee525d13
JB		 2415 priv->_3945.shared_virt =
2416 dma_alloc_coherent(&priv->pci_dev->dev,
2417 sizeof(struct iwl3945_shared),
2418 &priv->_3945.shared_phys, GFP_KERNEL);
2419 if (!priv->_3945.shared_virt) {
15b1687c 2420 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2421 mutex_unlock(&priv->mutex);
2422 return -ENOMEM;
2423 }
2424
21c02a1a 2425 /* Assign number of Usable TX queues */
88804e2b 2426 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2427
a8e74e27 2428 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2429 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2430 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2431 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2432 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2433 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2434
141c43a3 2435 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2436 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2437
b481de9c
ZY		 2438 return 0;
2439}
2440
4a8a4322 2441unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2442 struct iwl3945_frame *frame, u8 rate)
b481de9c 2443{
bb8c093b 2444 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2445 unsigned int frame_size;
2446
bb8c093b 2447 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2448 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2449
3832ec9d 2450 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2451 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2452
bb8c093b 2453 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2454 tx_beacon_cmd->frame,
b481de9c
ZY		 2455 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2456
2457 BUG_ON(frame_size > MAX_MPDU_SIZE);
2458 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2459
2460 tx_beacon_cmd->tx.rate = rate;
2461 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2462 TX_CMD_FLG_TSF_MSK);
2463
14577f23
MA		 2464 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2465 tx_beacon_cmd->tx.supp_rates[0] =
2466 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2467
b481de9c 2468 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2469 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2470
3ac7f146 2471 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2472}
2473
4a8a4322 2474void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2475{
91c066f2 2476 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2477 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2478}
2479
4a8a4322 2480void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2481{
ee525d13 2482 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2483 iwl3945_bg_reg_txpower_periodic);
2484}
2485
4a8a4322 2486void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2487{
ee525d13 2488 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2489}
2490
0164b9b4
KA		 2491/* check contents of special bootstrap uCode SRAM */
2492static int iwl3945_verify_bsm(struct iwl_priv *priv)
2493 {
2494 __le32 *image = priv->ucode_boot.v_addr;
2495 u32 len = priv->ucode_boot.len;
2496 u32 reg;
2497 u32 val;
2498
e1623446 2499 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2500
2501 /* verify BSM SRAM contents */
2502 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2503 for (reg = BSM_SRAM_LOWER_BOUND;
2504 reg < BSM_SRAM_LOWER_BOUND + len;
2505 reg += sizeof(u32), image++) {
2506 val = iwl_read_prph(priv, reg);
2507 if (val != le32_to_cpu(*image)) {
2508 IWL_ERR(priv, "BSM uCode verification failed at "
2509 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2510 BSM_SRAM_LOWER_BOUND,
2511 reg - BSM_SRAM_LOWER_BOUND, len,
2512 val, le32_to_cpu(*image));
2513 return -EIO;
2514 }
2515 }
2516
e1623446 2517 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2518
2519 return 0;
2520}
2521
e6148917
SO		 2522
2523/******************************************************************************
2524 *
2525 * EEPROM related functions
2526 *
2527 ******************************************************************************/
2528
2529/*
2530 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2531 * embedded controller) as EEPROM reader; each read is a series of pulses
2532 * to/from the EEPROM chip, not a single event, so even reads could conflict
2533 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2534 * simply claims ownership, which should be safe when this function is called
2535 * (i.e. before loading uCode!).
2536 */
2537static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2538{
2539 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2540 return 0;
2541}
2542
2543
2544static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2545{
2546 return;
2547}
2548
0164b9b4
KA		 2549 /**
2550 * iwl3945_load_bsm - Load bootstrap instructions
2551 *
2552 * BSM operation:
2553 *
2554 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2555 * in special SRAM that does not power down during RFKILL. When powering back
2556 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2557 * the bootstrap program into the on-board processor, and starts it.
2558 *
2559 * The bootstrap program loads (via DMA) instructions and data for a new
2560 * program from host DRAM locations indicated by the host driver in the
2561 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2562 * automatically.
2563 *
2564 * When initializing the NIC, the host driver points the BSM to the
2565 * "initialize" uCode image. This uCode sets up some internal data, then
2566 * notifies host via "initialize alive" that it is complete.
2567 *
2568 * The host then replaces the BSM_DRAM_* pointer values to point to the
2569 * normal runtime uCode instructions and a backup uCode data cache buffer
2570 * (filled initially with starting data values for the on-board processor),
2571 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2572 * which begins normal operation.
2573 *
2574 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2575 * the backup data cache in DRAM before SRAM is powered down.
2576 *
2577 * When powering back up, the BSM loads the bootstrap program. This reloads
2578 * the runtime uCode instructions and the backup data cache into SRAM,
2579 * and re-launches the runtime uCode from where it left off.
2580 */
2581static int iwl3945_load_bsm(struct iwl_priv *priv)
2582{
2583 __le32 *image = priv->ucode_boot.v_addr;
2584 u32 len = priv->ucode_boot.len;
2585 dma_addr_t pinst;
2586 dma_addr_t pdata;
2587 u32 inst_len;
2588 u32 data_len;
2589 int rc;
2590 int i;
2591 u32 done;
2592 u32 reg_offset;
2593
e1623446 2594 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2595
2596 /* make sure bootstrap program is no larger than BSM's SRAM size */
2597 if (len > IWL39_MAX_BSM_SIZE)
2598 return -EINVAL;
2599
2600 /* Tell bootstrap uCode where to find the "Initialize" uCode
2601 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2602 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2603 * after the "initialize" uCode has run, to point to
2604 * runtime/protocol instructions and backup data cache. */
2605 pinst = priv->ucode_init.p_addr;
2606 pdata = priv->ucode_init_data.p_addr;
2607 inst_len = priv->ucode_init.len;
2608 data_len = priv->ucode_init_data.len;
2609
0164b9b4
KA		 2610 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2611 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2612 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2613 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2614
2615 /* Fill BSM memory with bootstrap instructions */
2616 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2617 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2618 reg_offset += sizeof(u32), image++)
2619 _iwl_write_prph(priv, reg_offset,
2620 le32_to_cpu(*image));
2621
2622 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2623 if (rc)
0164b9b4 2624 return rc;
0164b9b4
KA		 2625
2626 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2627 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2628 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2629 IWL39_RTC_INST_LOWER_BOUND);
2630 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2631
2632 /* Load bootstrap code into instruction SRAM now,
2633 * to prepare to load "initialize" uCode */
2634 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2635 BSM_WR_CTRL_REG_BIT_START);
2636
2637 /* Wait for load of bootstrap uCode to finish */
2638 for (i = 0; i < 100; i++) {
2639 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2640 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2641 break;
2642 udelay(10);
2643 }
2644 if (i < 100)
e1623446 2645 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2646 else {
2647 IWL_ERR(priv, "BSM write did not complete!\n");
2648 return -EIO;
2649 }
2650
2651 /* Enable future boot loads whenever power management unit triggers it
2652 * (e.g. when powering back up after power-save shutdown) */
2653 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2654 BSM_WR_CTRL_REG_BIT_START_EN);
2655
0164b9b4
KA		 2656 return 0;
2657}
2658
cc0f555d
JS		 2659#define IWL3945_UCODE_GET(item) \
2660static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2661 u32 api_ver) \
2662{ \
2663 return le32_to_cpu(ucode->u.v1.item); \
2664}
2665
2666static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2667{
2668 return UCODE_HEADER_SIZE(1);
2669}
2670static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2671 u32 api_ver)
2672{
2673 return 0;
2674}
2675static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2676 u32 api_ver)
2677{
2678 return (u8 *) ucode->u.v1.data;
2679}
2680
2681IWL3945_UCODE_GET(inst_size);
2682IWL3945_UCODE_GET(data_size);
2683IWL3945_UCODE_GET(init_size);
2684IWL3945_UCODE_GET(init_data_size);
2685IWL3945_UCODE_GET(boot_size);
2686
5bbe233b
AK		 2687static struct iwl_hcmd_ops iwl3945_hcmd = {
2688 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2689 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2690};
2691
cc0f555d
JS		 2692static struct iwl_ucode_ops iwl3945_ucode = {
2693 .get_header_size = iwl3945_ucode_get_header_size,
2694 .get_build = iwl3945_ucode_get_build,
2695 .get_inst_size = iwl3945_ucode_get_inst_size,
2696 .get_data_size = iwl3945_ucode_get_data_size,
2697 .get_init_size = iwl3945_ucode_get_init_size,
2698 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2699 .get_boot_size = iwl3945_ucode_get_boot_size,
2700 .get_data = iwl3945_ucode_get_data,
2701};
2702
0164b9b4 2703static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2704 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2705 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2706 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2707 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2708 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2709 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2710 .apm_ops = {
2711 .init = iwl3945_apm_init,
d68b603c 2712 .stop = iwl_apm_stop,
01ec616d 2713 .config = iwl3945_nic_config,
854682ed 2714 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2715 },
e6148917
SO		 2716 .eeprom_ops = {
2717 .regulatory_bands = {
2718 EEPROM_REGULATORY_BAND_1_CHANNELS,
2719 EEPROM_REGULATORY_BAND_2_CHANNELS,
2720 EEPROM_REGULATORY_BAND_3_CHANNELS,
2721 EEPROM_REGULATORY_BAND_4_CHANNELS,
2722 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2723 EEPROM_REGULATORY_BAND_NO_HT40,
2724 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2725 },
2726 .verify_signature = iwlcore_eeprom_verify_signature,
2727 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2728 .release_semaphore = iwl3945_eeprom_release_semaphore,
2729 .query_addr = iwlcore_eeprom_query_addr,
2730 },
75bcfae9 2731 .send_tx_power = iwl3945_send_tx_power,
c2436980 2732 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2733 .post_associate = iwl3945_post_associate,
ef850d7c 2734 .isr = iwl_isr_legacy,
60690a6a 2735 .config_ap = iwl3945_config_ap,
3459ab5a 2736 .add_bcast_station = iwl3945_add_bcast_station,
0164b9b4
KA		 2737};
2738
42427b4e
KA		 2739static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2740 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2741 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2742 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
b6e4c55a 2743 .request_scan = iwl3945_request_scan,
42427b4e
KA		 2744};
2745
45d5d805 2746static const struct iwl_ops iwl3945_ops = {
cc0f555d 2747 .ucode = &iwl3945_ucode,
0164b9b4 2748 .lib = &iwl3945_lib,
5bbe233b 2749 .hcmd = &iwl3945_hcmd,
42427b4e 2750 .utils = &iwl3945_hcmd_utils,
e932a609 2751 .led = &iwl3945_led_ops,
0164b9b4
KA		 2752};
2753
c0f20d91 2754static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2755 .name = "3945BG",
a0987a8d
RC		 2756 .fw_name_pre = IWL3945_FW_PRE,
2757 .ucode_api_max = IWL3945_UCODE_API_MAX,
2758 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2759 .sku = IWL_SKU_G,
e6148917
SO		 2760 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2761 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2762 .ops = &iwl3945_ops,
88804e2b 2763 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2764 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2765 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2766 .set_l0s = false,
2767 .use_bsm = true,
b261793d
DH		 2768 .use_isr_legacy = true,
2769 .ht_greenfield_support = false,
f2d0d0e2 2770 .led_compensation = 64,
bc45a670 2771 .broken_powersave = true,
3e4fb5fa 2772 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
b74e31a9 2773 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2774 .max_event_log_size = 512,
82b9a121
TW		 2775};
2776
c0f20d91 2777static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2778 .name = "3945ABG",
a0987a8d
RC		 2779 .fw_name_pre = IWL3945_FW_PRE,
2780 .ucode_api_max = IWL3945_UCODE_API_MAX,
2781 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2782 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2783 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2784 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2785 .ops = &iwl3945_ops,
88804e2b 2786 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2787 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2788 .use_isr_legacy = true,
2789 .ht_greenfield_support = false,
f2d0d0e2 2790 .led_compensation = 64,
bc45a670 2791 .broken_powersave = true,
3e4fb5fa 2792 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
b74e31a9 2793 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2794 .max_event_log_size = 512,
82b9a121
TW		 2795};
2796
a3aa1884 2797DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2798 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2799 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2800 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2801 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2802 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2803 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2804 {0}
2805};
2806
bb8c093b 2807MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
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