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enc28j60: don't specify (wrong) IRQ type
[net-next-2.6.git] / drivers / net / s2io.c
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1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
66#include <linux/skbuff.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/stddef.h>
70#include <linux/ioctl.h>
71#include <linux/timex.h>
1da177e4 72#include <linux/ethtool.h>
1da177e4 73#include <linux/workqueue.h>
be3a6b02 74#include <linux/if_vlan.h>
7d3d0439
RA		 75#include <linux/ip.h>
76#include <linux/tcp.h>
77#include <net/tcp.h>
1da177e4 78
1da177e4
LT		 79#include <asm/system.h>
80#include <asm/uaccess.h>
20346722 81#include <asm/io.h>
fe931395 82#include <asm/div64.h>
330ce0de 83#include <asm/irq.h>
1da177e4
LT		 84
85/* local include */
86#include "s2io.h"
87#include "s2io-regs.h"
88
29d0a2b0 89#define DRV_VERSION "2.0.26.25"
6c1792f4 90
1da177e4 91/* S2io Driver name & version. */
20346722 92static char s2io_driver_name[] = "Neterion";
6c1792f4 93static char s2io_driver_version[] = DRV_VERSION;
1da177e4 94
6d517a27
VP		 95static int rxd_size[2] = {32,48};
96static int rxd_count[2] = {127,85};
da6971d8 97
1ee6dd77 98static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 99{
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106}
107
20346722 108/*
1da177e4
LT		 109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
541ae68f
K		 113#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 117
118#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 120
92b84437
SS		 121static inline int is_s2io_card_up(const struct s2io_nic * sp)
122{
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
124}
125
1da177e4
LT		 126/* Ethtool related variables and Macros. */
127static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133};
134
fa1f0cb3 135static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
1da177e4 145 {"tmac_any_err_frms"},
bd1034f0 146 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
bd1034f0 161 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
1da177e4 168 {"rmac_discarded_frms"},
bd1034f0
AR		 169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
1da177e4
LT		 172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
bd1034f0
AR		 176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
bd1034f0
AR		 190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
1da177e4 207 {"rmac_pause_cnt"},
bd1034f0
AR		 208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
bd1034f0
AR		 212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
fa1f0cb3
SS		 229 {"rxf_wr_cnt"}
230};
231
232static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
240 {"rmac_vlan_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
243 {"rmac_pf_discard"},
244 {"rmac_da_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 248 {"link_fault_cnt"}
249};
250
251static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
bd1034f0
AR		 255 {"parity_err_cnt"},
256 {"serious_err_cnt"},
257 {"soft_reset_cnt"},
258 {"fifo_full_cnt"},
8116f3cf
SS		 259 {"ring_0_full_cnt"},
260 {"ring_1_full_cnt"},
261 {"ring_2_full_cnt"},
262 {"ring_3_full_cnt"},
263 {"ring_4_full_cnt"},
264 {"ring_5_full_cnt"},
265 {"ring_6_full_cnt"},
266 {"ring_7_full_cnt"},
43b7c451
SH		 267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
287 {"mem_allocated"},
288 {"mem_freed"},
289 {"link_up_cnt"},
290 {"link_down_cnt"},
291 {"link_up_time"},
292 {"link_down_time"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 307 {"tda_err_cnt"},
308 {"pfc_err_cnt"},
309 {"pcc_err_cnt"},
310 {"tti_err_cnt"},
311 {"tpa_err_cnt"},
312 {"sm_err_cnt"},
313 {"lso_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
318 {"rc_err_cnt"},
319 {"prc_pcix_err_cnt"},
320 {"rpa_err_cnt"},
321 {"rda_err_cnt"},
322 {"rti_err_cnt"},
323 {"mc_err_cnt"}
1da177e4
LT		 324};
325
4c3616cd
AMR		 326#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 329
330#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
332
333#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 335
4c3616cd 336#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 337#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
338
25fff88e
K		 339#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
344
2fd37688
SS		 345/* copy mac addr to def_mac_addr array */
346static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
347{
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
354}
be3a6b02
K		 355/* Add the vlan */
356static void s2io_vlan_rx_register(struct net_device *dev,
357 struct vlan_group *grp)
358{
2fda096d 359 int i;
1ee6dd77 360 struct s2io_nic *nic = dev->priv;
2fda096d
SR		 361 unsigned long flags[MAX_TX_FIFOS];
362 struct mac_info *mac_control = &nic->mac_control;
363 struct config_param *config = &nic->config;
364
365 for (i = 0; i < config->tx_fifo_num; i++)
366 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 367
be3a6b02 368 nic->vlgrp = grp;
2fda096d
SR		 369 for (i = config->tx_fifo_num - 1; i >= 0; i--)
370 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
371 flags[i]);
be3a6b02
K		 372}
373
926930b2 374/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 375static int vlan_strip_flag;
926930b2 376
cdb5bf02
SH		 377/* Unregister the vlan */
378static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
379{
380 int i;
381 struct s2io_nic *nic = dev->priv;
382 unsigned long flags[MAX_TX_FIFOS];
383 struct mac_info *mac_control = &nic->mac_control;
384 struct config_param *config = &nic->config;
385
386 for (i = 0; i < config->tx_fifo_num; i++)
387 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
388
389 if (nic->vlgrp)
390 vlan_group_set_device(nic->vlgrp, vid, NULL);
391
392 for (i = config->tx_fifo_num - 1; i >= 0; i--)
393 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
394 flags[i]);
395}
396
20346722 397/*
1da177e4
LT		 398 * Constants to be programmed into the Xena's registers, to configure
399 * the XAUI.
400 */
401
1da177e4 402#define END_SIGN 0x0
f71e1309 403static const u64 herc_act_dtx_cfg[] = {
541ae68f 404 /* Set address */
e960fc5c 405 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 406 /* Write data */
e960fc5c 407 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 408 /* Set address */
409 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
410 /* Write data */
411 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
412 /* Set address */
e960fc5c 413 0x801205150D440000ULL, 0x801205150D4400E0ULL,
414 /* Write data */
415 0x801205150D440004ULL, 0x801205150D4400E4ULL,
416 /* Set address */
541ae68f
K		 417 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
418 /* Write data */
419 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
420 /* Done */
421 END_SIGN
422};
423
f71e1309 424static const u64 xena_dtx_cfg[] = {
c92ca04b 425 /* Set address */
1da177e4 426 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 427 /* Write data */
428 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
429 /* Set address */
430 0x8001051500000000ULL, 0x80010515000000E0ULL,
431 /* Write data */
432 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
433 /* Set address */
1da177e4 434 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 435 /* Write data */
436 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 437 END_SIGN
438};
439
20346722 440/*
1da177e4
LT		 441 * Constants for Fixing the MacAddress problem seen mostly on
442 * Alpha machines.
443 */
f71e1309 444static const u64 fix_mac[] = {
1da177e4
LT		 445 0x0060000000000000ULL, 0x0060600000000000ULL,
446 0x0040600000000000ULL, 0x0000600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0060600000000000ULL,
457 0x0020600000000000ULL, 0x0000600000000000ULL,
458 0x0040600000000000ULL, 0x0060600000000000ULL,
459 END_SIGN
460};
461
b41477f3
AR		 462MODULE_LICENSE("GPL");
463MODULE_VERSION(DRV_VERSION);
464
465
1da177e4 466/* Module Loadable parameters. */
6cfc482b 467S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 468S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 469S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 470S2IO_PARM_INT(rx_ring_mode, 1);
471S2IO_PARM_INT(use_continuous_tx_intrs, 1);
472S2IO_PARM_INT(rmac_pause_time, 0x100);
473S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
474S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
475S2IO_PARM_INT(shared_splits, 0);
476S2IO_PARM_INT(tmac_util_period, 5);
477S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 478S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 479/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
480S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 481/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 482S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 483/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 484S2IO_PARM_INT(intr_type, 2);
7d3d0439 485/* Large receive offload feature */
43b7c451
SH		 486static unsigned int lro_enable;
487module_param_named(lro, lro_enable, uint, 0);
488
7d3d0439
RA		 489/* Max pkts to be aggregated by LRO at one time. If not specified,
490 * aggregation happens until we hit max IP pkt size(64K)
491 */
b41477f3 492S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 493S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 494
495S2IO_PARM_INT(napi, 1);
496S2IO_PARM_INT(ufo, 0);
926930b2 497S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 498
499static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
500 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
501static unsigned int rx_ring_sz[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
503static unsigned int rts_frm_len[MAX_RX_RINGS] =
504 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
505
506module_param_array(tx_fifo_len, uint, NULL, 0);
507module_param_array(rx_ring_sz, uint, NULL, 0);
508module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 509
20346722 510/*
1da177e4 511 * S2IO device table.
20346722 512 * This table lists all the devices that this driver supports.
1da177e4
LT		 513 */
514static struct pci_device_id s2io_tbl[] __devinitdata = {
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 520 PCI_ANY_ID, PCI_ANY_ID},
521 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
522 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 523 {0,}
524};
525
526MODULE_DEVICE_TABLE(pci, s2io_tbl);
527
d796fdb7
LV		 528static struct pci_error_handlers s2io_err_handler = {
529 .error_detected = s2io_io_error_detected,
530 .slot_reset = s2io_io_slot_reset,
531 .resume = s2io_io_resume,
532};
533
1da177e4
LT		 534static struct pci_driver s2io_driver = {
535 .name = "S2IO",
536 .id_table = s2io_tbl,
537 .probe = s2io_init_nic,
538 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 539 .err_handler = &s2io_err_handler,
1da177e4
LT		 540};
541
542/* A simplifier macro used both by init and free shared_mem Fns(). */
543#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
544
3a3d5756
SH		 545/* netqueue manipulation helper functions */
546static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
547{
fd2ea0a7
DM		 548 if (!sp->config.multiq) {
549 int i;
550
3a3d5756
SH		 551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 553 }
fd2ea0a7 554 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 555}
556
557static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
558{
fd2ea0a7 559 if (!sp->config.multiq)
3a3d5756
SH		 560 sp->mac_control.fifos[fifo_no].queue_state =
561 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 562
563 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 564}
565
566static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
567{
fd2ea0a7
DM		 568 if (!sp->config.multiq) {
569 int i;
570
3a3d5756
SH		 571 for (i = 0; i < sp->config.tx_fifo_num; i++)
572 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 573 }
fd2ea0a7 574 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 575}
576
577static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
578{
fd2ea0a7 579 if (!sp->config.multiq)
3a3d5756
SH		 580 sp->mac_control.fifos[fifo_no].queue_state =
581 FIFO_QUEUE_START;
fd2ea0a7
DM		 582
583 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 584}
585
586static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
587{
fd2ea0a7
DM		 588 if (!sp->config.multiq) {
589 int i;
590
3a3d5756
SH		 591 for (i = 0; i < sp->config.tx_fifo_num; i++)
592 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 593 }
fd2ea0a7 594 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 595}
596
597static inline void s2io_wake_tx_queue(
598 struct fifo_info *fifo, int cnt, u8 multiq)
599{
600
3a3d5756
SH		 601 if (multiq) {
602 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
603 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 604 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 605 if (netif_queue_stopped(fifo->dev)) {
606 fifo->queue_state = FIFO_QUEUE_START;
607 netif_wake_queue(fifo->dev);
608 }
609 }
610}
611
1da177e4
LT		 612/**
613 * init_shared_mem - Allocation and Initialization of Memory
614 * @nic: Device private variable.
20346722
K		 615 * Description: The function allocates all the memory areas shared
616 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 617 * Rx descriptors and the statistics block.
618 */
619
620static int init_shared_mem(struct s2io_nic *nic)
621{
622 u32 size;
623 void *tmp_v_addr, *tmp_v_addr_next;
624 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 625 struct RxD_block *pre_rxd_blk = NULL;
372cc597 626 int i, j, blk_cnt;
1da177e4
LT		 627 int lst_size, lst_per_page;
628 struct net_device *dev = nic->dev;
8ae418cf 629 unsigned long tmp;
1ee6dd77 630 struct buffAdd *ba;
1da177e4 631
1ee6dd77 632 struct mac_info *mac_control;
1da177e4 633 struct config_param *config;
491976b2 634 unsigned long long mem_allocated = 0;
1da177e4
LT		 635
636 mac_control = &nic->mac_control;
637 config = &nic->config;
638
639
640 /* Allocation and initialization of TXDLs in FIOFs */
641 size = 0;
642 for (i = 0; i < config->tx_fifo_num; i++) {
643 size += config->tx_cfg[i].fifo_len;
644 }
645 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 646 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 647 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 648 return -EINVAL;
1da177e4
LT		 649 }
650
2fda096d
SR		 651 size = 0;
652 for (i = 0; i < config->tx_fifo_num; i++) {
653 size = config->tx_cfg[i].fifo_len;
654 /*
655 * Legal values are from 2 to 8192
656 */
657 if (size < 2) {
658 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
659 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
660 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
661 "are 2 to 8192\n");
662 return -EINVAL;
663 }
664 }
665
1ee6dd77 666 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 667 lst_per_page = PAGE_SIZE / lst_size;
668
669 for (i = 0; i < config->tx_fifo_num; i++) {
670 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 671 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 672 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722
K		 673 GFP_KERNEL);
674 if (!mac_control->fifos[i].list_info) {
0c61ed5f 675 DBG_PRINT(INFO_DBG,
1da177e4
LT		 676 "Malloc failed for list_info\n");
677 return -ENOMEM;
678 }
491976b2 679 mem_allocated += list_holder_size;
1da177e4
LT		 680 }
681 for (i = 0; i < config->tx_fifo_num; i++) {
682 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
683 lst_per_page);
20346722
K		 684 mac_control->fifos[i].tx_curr_put_info.offset = 0;
685 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 686 config->tx_cfg[i].fifo_len - 1;
20346722
K		 687 mac_control->fifos[i].tx_curr_get_info.offset = 0;
688 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 689 config->tx_cfg[i].fifo_len - 1;
20346722
K		 690 mac_control->fifos[i].fifo_no = i;
691 mac_control->fifos[i].nic = nic;
fed5eccd 692 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
3a3d5756 693 mac_control->fifos[i].dev = dev;
20346722 694
1da177e4
LT		 695 for (j = 0; j < page_num; j++) {
696 int k = 0;
697 dma_addr_t tmp_p;
698 void *tmp_v;
699 tmp_v = pci_alloc_consistent(nic->pdev,
700 PAGE_SIZE, &tmp_p);
701 if (!tmp_v) {
0c61ed5f 702 DBG_PRINT(INFO_DBG,
1da177e4 703 "pci_alloc_consistent ");
0c61ed5f 704 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 705 return -ENOMEM;
706 }
776bd20f 707 /* If we got a zero DMA address(can happen on
708 * certain platforms like PPC), reallocate.
709 * Store virtual address of page we don't want,
710 * to be freed later.
711 */
712 if (!tmp_p) {
713 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 714 DBG_PRINT(INIT_DBG,
776bd20f 715 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 716 DBG_PRINT(INIT_DBG,
6b4d617d 717 "Virtual address %p\n", tmp_v);
776bd20f 718 tmp_v = pci_alloc_consistent(nic->pdev,
719 PAGE_SIZE, &tmp_p);
720 if (!tmp_v) {
0c61ed5f 721 DBG_PRINT(INFO_DBG,
776bd20f 722 "pci_alloc_consistent ");
0c61ed5f 723 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 724 return -ENOMEM;
725 }
491976b2 726 mem_allocated += PAGE_SIZE;
776bd20f 727 }
1da177e4
LT		 728 while (k < lst_per_page) {
729 int l = (j * lst_per_page) + k;
730 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 731 break;
732 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 733 tmp_v + (k * lst_size);
20346722 734 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 735 tmp_p + (k * lst_size);
736 k++;
737 }
738 }
739 }
1da177e4 740
2fda096d
SR		 741 for (i = 0; i < config->tx_fifo_num; i++) {
742 size = config->tx_cfg[i].fifo_len;
743 mac_control->fifos[i].ufo_in_band_v
744 = kcalloc(size, sizeof(u64), GFP_KERNEL);
745 if (!mac_control->fifos[i].ufo_in_band_v)
746 return -ENOMEM;
747 mem_allocated += (size * sizeof(u64));
748 }
fed5eccd 749
1da177e4
LT		 750 /* Allocation and initialization of RXDs in Rings */
751 size = 0;
752 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 753 if (config->rx_cfg[i].num_rxd %
754 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 755 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
756 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
757 i);
758 DBG_PRINT(ERR_DBG, "RxDs per Block");
759 return FAILURE;
760 }
761 size += config->rx_cfg[i].num_rxd;
20346722 762 mac_control->rings[i].block_count =
da6971d8
AR		 763 config->rx_cfg[i].num_rxd /
764 (rxd_count[nic->rxd_mode] + 1 );
765 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
766 mac_control->rings[i].block_count;
1da177e4 767 }
da6971d8 768 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 769 size = (size * (sizeof(struct RxD1)));
da6971d8 770 else
1ee6dd77 771 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 772
773 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 774 mac_control->rings[i].rx_curr_get_info.block_index = 0;
775 mac_control->rings[i].rx_curr_get_info.offset = 0;
776 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 777 config->rx_cfg[i].num_rxd - 1;
20346722
K		 778 mac_control->rings[i].rx_curr_put_info.block_index = 0;
779 mac_control->rings[i].rx_curr_put_info.offset = 0;
780 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 781 config->rx_cfg[i].num_rxd - 1;
20346722
K		 782 mac_control->rings[i].nic = nic;
783 mac_control->rings[i].ring_no = i;
0425b46a 784 mac_control->rings[i].lro = lro_enable;
20346722 785
da6971d8
AR		 786 blk_cnt = config->rx_cfg[i].num_rxd /
787 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 788 /* Allocating all the Rx blocks */
789 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 790 struct rx_block_info *rx_blocks;
da6971d8
AR		 791 int l;
792
793 rx_blocks = &mac_control->rings[i].rx_blocks[j];
794 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 795 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
796 &tmp_p_addr);
797 if (tmp_v_addr == NULL) {
798 /*
20346722
K		 799 * In case of failure, free_shared_mem()
800 * is called, which should free any
801 * memory that was alloced till the
1da177e4
LT		 802 * failure happened.
803 */
da6971d8 804 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 805 return -ENOMEM;
806 }
491976b2 807 mem_allocated += size;
1da177e4 808 memset(tmp_v_addr, 0, size);
da6971d8
AR		 809 rx_blocks->block_virt_addr = tmp_v_addr;
810 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 811 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 812 rxd_count[nic->rxd_mode],
813 GFP_KERNEL);
372cc597
SS		 814 if (!rx_blocks->rxds)
815 return -ENOMEM;
8a4bdbaa 816 mem_allocated +=
491976b2 817 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 818 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
819 rx_blocks->rxds[l].virt_addr =
820 rx_blocks->block_virt_addr +
821 (rxd_size[nic->rxd_mode] * l);
822 rx_blocks->rxds[l].dma_addr =
823 rx_blocks->block_dma_addr +
824 (rxd_size[nic->rxd_mode] * l);
825 }
1da177e4
LT		 826 }
827 /* Interlinking all Rx Blocks */
828 for (j = 0; j < blk_cnt; j++) {
20346722
K		 829 tmp_v_addr =
830 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 831 tmp_v_addr_next =
20346722 832 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 833 blk_cnt].block_virt_addr;
20346722
K		 834 tmp_p_addr =
835 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 836 tmp_p_addr_next =
20346722 837 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 838 blk_cnt].block_dma_addr;
839
1ee6dd77 840 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 841 pre_rxd_blk->reserved_2_pNext_RxD_block =
842 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 843 pre_rxd_blk->pNext_RxD_Blk_physical =
844 (u64) tmp_p_addr_next;
845 }
846 }
6d517a27 847 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 848 /*
849 * Allocation of Storages for buffer addresses in 2BUFF mode
850 * and the buffers as well.
851 */
852 for (i = 0; i < config->rx_ring_num; i++) {
853 blk_cnt = config->rx_cfg[i].num_rxd /
854 (rxd_count[nic->rxd_mode]+ 1);
855 mac_control->rings[i].ba =
1ee6dd77 856 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 857 GFP_KERNEL);
da6971d8 858 if (!mac_control->rings[i].ba)
1da177e4 859 return -ENOMEM;
491976b2 860 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 861 for (j = 0; j < blk_cnt; j++) {
862 int k = 0;
863 mac_control->rings[i].ba[j] =
1ee6dd77 864 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 865 (rxd_count[nic->rxd_mode] + 1)),
866 GFP_KERNEL);
867 if (!mac_control->rings[i].ba[j])
1da177e4 868 return -ENOMEM;
491976b2
SH		 869 mem_allocated += (sizeof(struct buffAdd) * \
870 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 871 while (k != rxd_count[nic->rxd_mode]) {
872 ba = &mac_control->rings[i].ba[j][k];
873
874 ba->ba_0_org = (void *) kmalloc
875 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
876 if (!ba->ba_0_org)
877 return -ENOMEM;
8a4bdbaa 878 mem_allocated +=
491976b2 879 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 880 tmp = (unsigned long)ba->ba_0_org;
881 tmp += ALIGN_SIZE;
882 tmp &= ~((unsigned long) ALIGN_SIZE);
883 ba->ba_0 = (void *) tmp;
884
885 ba->ba_1_org = (void *) kmalloc
886 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
887 if (!ba->ba_1_org)
888 return -ENOMEM;
8a4bdbaa 889 mem_allocated
491976b2 890 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 891 tmp = (unsigned long) ba->ba_1_org;
892 tmp += ALIGN_SIZE;
893 tmp &= ~((unsigned long) ALIGN_SIZE);
894 ba->ba_1 = (void *) tmp;
895 k++;
896 }
1da177e4
LT		 897 }
898 }
899 }
1da177e4
LT		 900
901 /* Allocation and initialization of Statistics block */
1ee6dd77 902 size = sizeof(struct stat_block);
1da177e4
LT		 903 mac_control->stats_mem = pci_alloc_consistent
904 (nic->pdev, size, &mac_control->stats_mem_phy);
905
906 if (!mac_control->stats_mem) {
20346722
K		 907 /*
908 * In case of failure, free_shared_mem() is called, which
909 * should free any memory that was alloced till the
1da177e4
LT		 910 * failure happened.
911 */
912 return -ENOMEM;
913 }
491976b2 914 mem_allocated += size;
1da177e4
LT		 915 mac_control->stats_mem_sz = size;
916
917 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 918 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 919 memset(tmp_v_addr, 0, size);
1da177e4
LT		 920 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
921 (unsigned long long) tmp_p_addr);
491976b2 922 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 923 return SUCCESS;
924}
925
20346722
K		 926/**
927 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 928 * @nic: Device private variable.
929 * Description: This function is to free all memory locations allocated by
930 * the init_shared_mem() function and return it to the kernel.
931 */
932
933static void free_shared_mem(struct s2io_nic *nic)
934{
935 int i, j, blk_cnt, size;
936 void *tmp_v_addr;
937 dma_addr_t tmp_p_addr;
1ee6dd77 938 struct mac_info *mac_control;
1da177e4
LT		 939 struct config_param *config;
940 int lst_size, lst_per_page;
8910b49f 941 struct net_device *dev;
491976b2 942 int page_num = 0;
1da177e4
LT		 943
944 if (!nic)
945 return;
946
8910b49f
MG		 947 dev = nic->dev;
948
1da177e4
LT		 949 mac_control = &nic->mac_control;
950 config = &nic->config;
951
1ee6dd77 952 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 953 lst_per_page = PAGE_SIZE / lst_size;
954
955 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 956 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
957 lst_per_page);
1da177e4
LT		 958 for (j = 0; j < page_num; j++) {
959 int mem_blks = (j * lst_per_page);
776bd20f 960 if (!mac_control->fifos[i].list_info)
6aa20a22 961 return;
776bd20f 962 if (!mac_control->fifos[i].list_info[mem_blks].
963 list_virt_addr)
1da177e4
LT		 964 break;
965 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 966 mac_control->fifos[i].
967 list_info[mem_blks].
1da177e4 968 list_virt_addr,
20346722
K		 969 mac_control->fifos[i].
970 list_info[mem_blks].
1da177e4 971 list_phy_addr);
8a4bdbaa 972 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 973 += PAGE_SIZE;
1da177e4 974 }
776bd20f 975 /* If we got a zero DMA address during allocation,
976 * free the page now
977 */
978 if (mac_control->zerodma_virt_addr) {
979 pci_free_consistent(nic->pdev, PAGE_SIZE,
980 mac_control->zerodma_virt_addr,
981 (dma_addr_t)0);
6aa20a22 982 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 983 "%s: Freeing TxDL with zero DMA addr. ",
984 dev->name);
985 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
986 mac_control->zerodma_virt_addr);
8a4bdbaa 987 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 988 += PAGE_SIZE;
776bd20f 989 }
20346722 990 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 991 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 992 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 993 }
994
1da177e4 995 size = SIZE_OF_BLOCK;
1da177e4 996 for (i = 0; i < config->rx_ring_num; i++) {
20346722 997 blk_cnt = mac_control->rings[i].block_count;
1da177e4 998 for (j = 0; j < blk_cnt; j++) {
20346722
K		 999 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1000 block_virt_addr;
1001 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1002 block_dma_addr;
1da177e4
LT		 1003 if (tmp_v_addr == NULL)
1004 break;
1005 pci_free_consistent(nic->pdev, size,
1006 tmp_v_addr, tmp_p_addr);
491976b2 1007 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 1008 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 1009 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1010 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1011 }
1012 }
1013
6d517a27 1014 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1015 /* Freeing buffer storage addresses in 2BUFF mode. */
1016 for (i = 0; i < config->rx_ring_num; i++) {
1017 blk_cnt = config->rx_cfg[i].num_rxd /
1018 (rxd_count[nic->rxd_mode] + 1);
1019 for (j = 0; j < blk_cnt; j++) {
1020 int k = 0;
1021 if (!mac_control->rings[i].ba[j])
1022 continue;
1023 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 1024 struct buffAdd *ba =
da6971d8
AR		 1025 &mac_control->rings[i].ba[j][k];
1026 kfree(ba->ba_0_org);
491976b2
SH		 1027 nic->mac_control.stats_info->sw_stat.\
1028 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1029 kfree(ba->ba_1_org);
491976b2
SH		 1030 nic->mac_control.stats_info->sw_stat.\
1031 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1032 k++;
1033 }
1034 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 1035 nic->mac_control.stats_info->sw_stat.mem_freed +=
1036 (sizeof(struct buffAdd) *
1037 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1038 }
da6971d8 1039 kfree(mac_control->rings[i].ba);
8a4bdbaa 1040 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1041 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1042 }
1da177e4 1043 }
1da177e4 1044
2fda096d
SR		 1045 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1046 if (mac_control->fifos[i].ufo_in_band_v) {
1047 nic->mac_control.stats_info->sw_stat.mem_freed
1048 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1049 kfree(mac_control->fifos[i].ufo_in_band_v);
1050 }
1051 }
1052
1da177e4 1053 if (mac_control->stats_mem) {
2fda096d
SR		 1054 nic->mac_control.stats_info->sw_stat.mem_freed +=
1055 mac_control->stats_mem_sz;
1da177e4
LT		 1056 pci_free_consistent(nic->pdev,
1057 mac_control->stats_mem_sz,
1058 mac_control->stats_mem,
1059 mac_control->stats_mem_phy);
491976b2 1060 }
1da177e4
LT		 1061}
1062
541ae68f
K		 1063/**
1064 * s2io_verify_pci_mode -
1065 */
1066
1ee6dd77 1067static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1068{
1ee6dd77 1069 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1070 register u64 val64 = 0;
1071 int mode;
1072
1073 val64 = readq(&bar0->pci_mode);
1074 mode = (u8)GET_PCI_MODE(val64);
1075
1076 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1077 return -1; /* Unknown PCI mode */
1078 return mode;
1079}
1080
c92ca04b
AR		 1081#define NEC_VENID 0x1033
1082#define NEC_DEVID 0x0125
1083static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1084{
1085 struct pci_dev *tdev = NULL;
26d36b64
AC		 1086 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1087 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1088 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1089 pci_dev_put(tdev);
c92ca04b 1090 return 1;
7ad62dbc 1091 }
c92ca04b
AR		 1092 }
1093 }
1094 return 0;
1095}
541ae68f 1096
7b32a312 1097static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1098/**
1099 * s2io_print_pci_mode -
1100 */
1ee6dd77 1101static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1102{
1ee6dd77 1103 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1104 register u64 val64 = 0;
1105 int mode;
1106 struct config_param *config = &nic->config;
1107
1108 val64 = readq(&bar0->pci_mode);
1109 mode = (u8)GET_PCI_MODE(val64);
1110
1111 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1112 return -1; /* Unknown PCI mode */
1113
c92ca04b
AR		 1114 config->bus_speed = bus_speed[mode];
1115
1116 if (s2io_on_nec_bridge(nic->pdev)) {
1117 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1118 nic->dev->name);
1119 return mode;
1120 }
1121
541ae68f
K		 1122 if (val64 & PCI_MODE_32_BITS) {
1123 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1124 } else {
1125 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1126 }
1127
1128 switch(mode) {
1129 case PCI_MODE_PCI_33:
1130 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 1131 break;
1132 case PCI_MODE_PCI_66:
1133 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 1134 break;
1135 case PCI_MODE_PCIX_M1_66:
1136 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 1137 break;
1138 case PCI_MODE_PCIX_M1_100:
1139 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 1140 break;
1141 case PCI_MODE_PCIX_M1_133:
1142 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 1143 break;
1144 case PCI_MODE_PCIX_M2_66:
1145 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1146 break;
1147 case PCI_MODE_PCIX_M2_100:
1148 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1149 break;
1150 case PCI_MODE_PCIX_M2_133:
1151 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1152 break;
1153 default:
1154 return -1; /* Unsupported bus speed */
1155 }
1156
1157 return mode;
1158}
1159
b7c5678f
RV		 1160/**
1161 * init_tti - Initialization transmit traffic interrupt scheme
1162 * @nic: device private variable
1163 * @link: link status (UP/DOWN) used to enable/disable continuous
1164 * transmit interrupts
1165 * Description: The function configures transmit traffic interrupts
1166 * Return Value: SUCCESS on success and
1167 * '-1' on failure
1168 */
1169
0d66afe7 1170static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1171{
1172 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1173 register u64 val64 = 0;
1174 int i;
1175 struct config_param *config;
1176
1177 config = &nic->config;
1178
1179 for (i = 0; i < config->tx_fifo_num; i++) {
1180 /*
1181 * TTI Initialization. Default Tx timer gets us about
1182 * 250 interrupts per sec. Continuous interrupts are enabled
1183 * by default.
1184 */
1185 if (nic->device_type == XFRAME_II_DEVICE) {
1186 int count = (nic->config.bus_speed * 125)/2;
1187 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1188 } else
1189 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1190
1191 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1192 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1193 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1194 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1195 if (i == 0)
1196 if (use_continuous_tx_intrs && (link == LINK_UP))
1197 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1198 writeq(val64, &bar0->tti_data1_mem);
1199
ac731ab6
SH		 1200 if (nic->config.intr_type == MSI_X) {
1201 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1202 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1203 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1204 TTI_DATA2_MEM_TX_UFC_D(0x300);
1205 } else {
1206 if ((nic->config.tx_steering_type ==
1207 TX_DEFAULT_STEERING) &&
1208 (config->tx_fifo_num > 1) &&
1209 (i >= nic->udp_fifo_idx) &&
1210 (i < (nic->udp_fifo_idx +
1211 nic->total_udp_fifos)))
1212 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1213 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1214 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1215 TTI_DATA2_MEM_TX_UFC_D(0x120);
1216 else
1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x80);
1221 }
b7c5678f
RV		 1222
1223 writeq(val64, &bar0->tti_data2_mem);
1224
1225 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1226 TTI_CMD_MEM_OFFSET(i);
1227 writeq(val64, &bar0->tti_command_mem);
1228
1229 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1230 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1231 return FAILURE;
1232 }
1233
1234 return SUCCESS;
1235}
1236
20346722
K		 1237/**
1238 * init_nic - Initialization of hardware
b7c5678f 1239 * @nic: device private variable
20346722
K		 1240 * Description: The function sequentially configures every block
1241 * of the H/W from their reset values.
1242 * Return Value: SUCCESS on success and
1da177e4
LT		 1243 * '-1' on failure (endian settings incorrect).
1244 */
1245
1246static int init_nic(struct s2io_nic *nic)
1247{
1ee6dd77 1248 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1249 struct net_device *dev = nic->dev;
1250 register u64 val64 = 0;
1251 void __iomem *add;
1252 u32 time;
1253 int i, j;
1ee6dd77 1254 struct mac_info *mac_control;
1da177e4 1255 struct config_param *config;
c92ca04b 1256 int dtx_cnt = 0;
1da177e4 1257 unsigned long long mem_share;
20346722 1258 int mem_size;
1da177e4
LT		 1259
1260 mac_control = &nic->mac_control;
1261 config = &nic->config;
1262
5e25b9dd 1263 /* to set the swapper controle on the card */
20346722 1264 if(s2io_set_swapper(nic)) {
1da177e4 1265 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1266 return -EIO;
1da177e4
LT		 1267 }
1268
541ae68f
K		 1269 /*
1270 * Herc requires EOI to be removed from reset before XGXS, so..
1271 */
1272 if (nic->device_type & XFRAME_II_DEVICE) {
1273 val64 = 0xA500000000ULL;
1274 writeq(val64, &bar0->sw_reset);
1275 msleep(500);
1276 val64 = readq(&bar0->sw_reset);
1277 }
1278
1da177e4
LT		 1279 /* Remove XGXS from reset state */
1280 val64 = 0;
1281 writeq(val64, &bar0->sw_reset);
1da177e4 1282 msleep(500);
20346722 1283 val64 = readq(&bar0->sw_reset);
1da177e4 1284
7962024e
SH		 1285 /* Ensure that it's safe to access registers by checking
1286 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1287 */
1288 if (nic->device_type == XFRAME_II_DEVICE) {
1289 for (i = 0; i < 50; i++) {
1290 val64 = readq(&bar0->adapter_status);
1291 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1292 break;
1293 msleep(10);
1294 }
1295 if (i == 50)
1296 return -ENODEV;
1297 }
1298
1da177e4
LT		 1299 /* Enable Receiving broadcasts */
1300 add = &bar0->mac_cfg;
1301 val64 = readq(&bar0->mac_cfg);
1302 val64 |= MAC_RMAC_BCAST_ENABLE;
1303 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1304 writel((u32) val64, add);
1305 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1306 writel((u32) (val64 >> 32), (add + 4));
1307
1308 /* Read registers in all blocks */
1309 val64 = readq(&bar0->mac_int_mask);
1310 val64 = readq(&bar0->mc_int_mask);
1311 val64 = readq(&bar0->xgxs_int_mask);
1312
1313 /* Set MTU */
1314 val64 = dev->mtu;
1315 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1316
541ae68f
K		 1317 if (nic->device_type & XFRAME_II_DEVICE) {
1318 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1319 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1320 &bar0->dtx_control, UF);
541ae68f
K		 1321 if (dtx_cnt & 0x1)
1322 msleep(1); /* Necessary!! */
1da177e4
LT		 1323 dtx_cnt++;
1324 }
541ae68f 1325 } else {
c92ca04b
AR		 1326 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1327 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1328 &bar0->dtx_control, UF);
1329 val64 = readq(&bar0->dtx_control);
1330 dtx_cnt++;
1da177e4
LT		 1331 }
1332 }
1333
1334 /* Tx DMA Initialization */
1335 val64 = 0;
1336 writeq(val64, &bar0->tx_fifo_partition_0);
1337 writeq(val64, &bar0->tx_fifo_partition_1);
1338 writeq(val64, &bar0->tx_fifo_partition_2);
1339 writeq(val64, &bar0->tx_fifo_partition_3);
1340
1341
1342 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1343 val64 |=
b7c5678f 1344 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1345 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1346 ((j * 32) + 5), 3);
1da177e4
LT		 1347
1348 if (i == (config->tx_fifo_num - 1)) {
1349 if (i % 2 == 0)
1350 i++;
1351 }
1352
1353 switch (i) {
1354 case 1:
1355 writeq(val64, &bar0->tx_fifo_partition_0);
1356 val64 = 0;
b7c5678f 1357 j = 0;
1da177e4
LT		 1358 break;
1359 case 3:
1360 writeq(val64, &bar0->tx_fifo_partition_1);
1361 val64 = 0;
b7c5678f 1362 j = 0;
1da177e4
LT		 1363 break;
1364 case 5:
1365 writeq(val64, &bar0->tx_fifo_partition_2);
1366 val64 = 0;
b7c5678f 1367 j = 0;
1da177e4
LT		 1368 break;
1369 case 7:
1370 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1371 val64 = 0;
1372 j = 0;
1373 break;
1374 default:
1375 j++;
1da177e4
LT		 1376 break;
1377 }
1378 }
1379
5e25b9dd
K		 1380 /*
1381 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1382 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1383 */
541ae68f 1384 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1385 (nic->pdev->revision < 4))
5e25b9dd
K		 1386 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1387
1da177e4
LT		 1388 val64 = readq(&bar0->tx_fifo_partition_0);
1389 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1390 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1391
20346722
K		 1392 /*
1393 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1394 * integrity checking.
1395 */
1396 val64 = readq(&bar0->tx_pa_cfg);
1397 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1398 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1399 writeq(val64, &bar0->tx_pa_cfg);
1400
1401 /* Rx DMA intialization. */
1402 val64 = 0;
1403 for (i = 0; i < config->rx_ring_num; i++) {
1404 val64 |=
1405 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1406 3);
1407 }
1408 writeq(val64, &bar0->rx_queue_priority);
1409
20346722
K		 1410 /*
1411 * Allocating equal share of memory to all the
1da177e4
LT		 1412 * configured Rings.
1413 */
1414 val64 = 0;
541ae68f
K		 1415 if (nic->device_type & XFRAME_II_DEVICE)
1416 mem_size = 32;
1417 else
1418 mem_size = 64;
1419
1da177e4
LT		 1420 for (i = 0; i < config->rx_ring_num; i++) {
1421 switch (i) {
1422 case 0:
20346722
K		 1423 mem_share = (mem_size / config->rx_ring_num +
1424 mem_size % config->rx_ring_num);
1da177e4
LT		 1425 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1426 continue;
1427 case 1:
20346722 1428 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1429 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1430 continue;
1431 case 2:
20346722 1432 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1434 continue;
1435 case 3:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1438 continue;
1439 case 4:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1442 continue;
1443 case 5:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1446 continue;
1447 case 6:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1450 continue;
1451 case 7:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1454 continue;
1455 }
1456 }
1457 writeq(val64, &bar0->rx_queue_cfg);
1458
20346722 1459 /*
5e25b9dd 1460 * Filling Tx round robin registers
b7c5678f 1461 * as per the number of FIFOs for equal scheduling priority
1da177e4 1462 */
5e25b9dd
K		 1463 switch (config->tx_fifo_num) {
1464 case 1:
b7c5678f 1465 val64 = 0x0;
5e25b9dd
K		 1466 writeq(val64, &bar0->tx_w_round_robin_0);
1467 writeq(val64, &bar0->tx_w_round_robin_1);
1468 writeq(val64, &bar0->tx_w_round_robin_2);
1469 writeq(val64, &bar0->tx_w_round_robin_3);
1470 writeq(val64, &bar0->tx_w_round_robin_4);
1471 break;
1472 case 2:
b7c5678f 1473 val64 = 0x0001000100010001ULL;
5e25b9dd 1474 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1475 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1476 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1477 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1478 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1479 writeq(val64, &bar0->tx_w_round_robin_4);
1480 break;
1481 case 3:
b7c5678f 1482 val64 = 0x0001020001020001ULL;
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1484 val64 = 0x0200010200010200ULL;
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1486 val64 = 0x0102000102000102ULL;
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1488 val64 = 0x0001020001020001ULL;
5e25b9dd 1489 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1490 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1491 writeq(val64, &bar0->tx_w_round_robin_4);
1492 break;
1493 case 4:
b7c5678f 1494 val64 = 0x0001020300010203ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1498 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1499 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1500 writeq(val64, &bar0->tx_w_round_robin_4);
1501 break;
1502 case 5:
b7c5678f 1503 val64 = 0x0001020304000102ULL;
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1505 val64 = 0x0304000102030400ULL;
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1507 val64 = 0x0102030400010203ULL;
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1509 val64 = 0x0400010203040001ULL;
5e25b9dd 1510 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1511 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1512 writeq(val64, &bar0->tx_w_round_robin_4);
1513 break;
1514 case 6:
b7c5678f 1515 val64 = 0x0001020304050001ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1517 val64 = 0x0203040500010203ULL;
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1519 val64 = 0x0405000102030405ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1521 val64 = 0x0001020304050001ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1523 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1524 writeq(val64, &bar0->tx_w_round_robin_4);
1525 break;
1526 case 7:
b7c5678f 1527 val64 = 0x0001020304050600ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1529 val64 = 0x0102030405060001ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1531 val64 = 0x0203040506000102ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1533 val64 = 0x0304050600010203ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1535 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1536 writeq(val64, &bar0->tx_w_round_robin_4);
1537 break;
1538 case 8:
b7c5678f 1539 val64 = 0x0001020304050607ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1543 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1544 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1545 writeq(val64, &bar0->tx_w_round_robin_4);
1546 break;
1547 }
1548
b41477f3 1549 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1550 val64 = readq(&bar0->tx_fifo_partition_0);
1551 val64 |= (TX_FIFO_PARTITION_EN);
1552 writeq(val64, &bar0->tx_fifo_partition_0);
1553
5e25b9dd 1554 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1555 * number of Rings and steering based on QoS with
1556 * equal priority.
1557 */
5e25b9dd
K		 1558 switch (config->rx_ring_num) {
1559 case 1:
0425b46a
SH		 1560 val64 = 0x0;
1561 writeq(val64, &bar0->rx_w_round_robin_0);
1562 writeq(val64, &bar0->rx_w_round_robin_1);
1563 writeq(val64, &bar0->rx_w_round_robin_2);
1564 writeq(val64, &bar0->rx_w_round_robin_3);
1565 writeq(val64, &bar0->rx_w_round_robin_4);
1566
5e25b9dd
K		 1567 val64 = 0x8080808080808080ULL;
1568 writeq(val64, &bar0->rts_qos_steering);
1569 break;
1570 case 2:
0425b46a 1571 val64 = 0x0001000100010001ULL;
5e25b9dd 1572 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1573 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1574 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1575 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1576 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1577 writeq(val64, &bar0->rx_w_round_robin_4);
1578
1579 val64 = 0x8080808040404040ULL;
1580 writeq(val64, &bar0->rts_qos_steering);
1581 break;
1582 case 3:
0425b46a 1583 val64 = 0x0001020001020001ULL;
5e25b9dd 1584 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1585 val64 = 0x0200010200010200ULL;
5e25b9dd 1586 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1587 val64 = 0x0102000102000102ULL;
5e25b9dd 1588 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1589 val64 = 0x0001020001020001ULL;
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1591 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1592 writeq(val64, &bar0->rx_w_round_robin_4);
1593
1594 val64 = 0x8080804040402020ULL;
1595 writeq(val64, &bar0->rts_qos_steering);
1596 break;
1597 case 4:
0425b46a 1598 val64 = 0x0001020300010203ULL;
5e25b9dd 1599 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1601 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1602 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1603 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1604 writeq(val64, &bar0->rx_w_round_robin_4);
1605
1606 val64 = 0x8080404020201010ULL;
1607 writeq(val64, &bar0->rts_qos_steering);
1608 break;
1609 case 5:
0425b46a 1610 val64 = 0x0001020304000102ULL;
5e25b9dd 1611 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1612 val64 = 0x0304000102030400ULL;
5e25b9dd 1613 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1614 val64 = 0x0102030400010203ULL;
5e25b9dd 1615 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1616 val64 = 0x0400010203040001ULL;
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1618 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1619 writeq(val64, &bar0->rx_w_round_robin_4);
1620
1621 val64 = 0x8080404020201008ULL;
1622 writeq(val64, &bar0->rts_qos_steering);
1623 break;
1624 case 6:
0425b46a 1625 val64 = 0x0001020304050001ULL;
5e25b9dd 1626 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1627 val64 = 0x0203040500010203ULL;
5e25b9dd 1628 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1629 val64 = 0x0405000102030405ULL;
5e25b9dd 1630 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1631 val64 = 0x0001020304050001ULL;
5e25b9dd 1632 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1633 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1634 writeq(val64, &bar0->rx_w_round_robin_4);
1635
1636 val64 = 0x8080404020100804ULL;
1637 writeq(val64, &bar0->rts_qos_steering);
1638 break;
1639 case 7:
0425b46a 1640 val64 = 0x0001020304050600ULL;
5e25b9dd 1641 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1642 val64 = 0x0102030405060001ULL;
5e25b9dd 1643 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1644 val64 = 0x0203040506000102ULL;
5e25b9dd 1645 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1646 val64 = 0x0304050600010203ULL;
5e25b9dd 1647 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1648 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1649 writeq(val64, &bar0->rx_w_round_robin_4);
1650
1651 val64 = 0x8080402010080402ULL;
1652 writeq(val64, &bar0->rts_qos_steering);
1653 break;
1654 case 8:
0425b46a 1655 val64 = 0x0001020304050607ULL;
5e25b9dd 1656 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1658 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1659 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1660 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1661 writeq(val64, &bar0->rx_w_round_robin_4);
1662
1663 val64 = 0x8040201008040201ULL;
1664 writeq(val64, &bar0->rts_qos_steering);
1665 break;
1666 }
1da177e4
LT		 1667
1668 /* UDP Fix */
1669 val64 = 0;
20346722 1670 for (i = 0; i < 8; i++)
1da177e4
LT		 1671 writeq(val64, &bar0->rts_frm_len_n[i]);
1672
5e25b9dd
K		 1673 /* Set the default rts frame length for the rings configured */
1674 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1675 for (i = 0 ; i < config->rx_ring_num ; i++)
1676 writeq(val64, &bar0->rts_frm_len_n[i]);
1677
1678 /* Set the frame length for the configured rings
1679 * desired by the user
1680 */
1681 for (i = 0; i < config->rx_ring_num; i++) {
1682 /* If rts_frm_len[i] == 0 then it is assumed that user not
1683 * specified frame length steering.
1684 * If the user provides the frame length then program
1685 * the rts_frm_len register for those values or else
1686 * leave it as it is.
1687 */
1688 if (rts_frm_len[i] != 0) {
1689 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1690 &bar0->rts_frm_len_n[i]);
1691 }
1692 }
8a4bdbaa 1693
9fc93a41
SS		 1694 /* Disable differentiated services steering logic */
1695 for (i = 0; i < 64; i++) {
1696 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1697 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1698 dev->name);
1699 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1700 return -ENODEV;
9fc93a41
SS		 1701 }
1702 }
1703
20346722 1704 /* Program statistics memory */
1da177e4 1705 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1706
541ae68f
K		 1707 if (nic->device_type == XFRAME_II_DEVICE) {
1708 val64 = STAT_BC(0x320);
1709 writeq(val64, &bar0->stat_byte_cnt);
1710 }
1711
20346722 1712 /*
1da177e4
LT		 1713 * Initializing the sampling rate for the device to calculate the
1714 * bandwidth utilization.
1715 */
1716 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1717 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1718 writeq(val64, &bar0->mac_link_util);
1719
20346722
K		 1720 /*
1721 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1722 * Scheme.
1723 */
1da177e4 1724
b7c5678f
RV		 1725 /* Initialize TTI */
1726 if (SUCCESS != init_tti(nic, nic->last_link_state))
1727 return -ENODEV;
1da177e4 1728
8a4bdbaa
SS		 1729 /* RTI Initialization */
1730 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1731 /*
8a4bdbaa
SS		 1732 * Programmed to generate Apprx 500 Intrs per
1733 * second
1734 */
1735 int count = (nic->config.bus_speed * 125)/4;
1736 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1737 } else
1738 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1739 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1740 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1741 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1742
1743 writeq(val64, &bar0->rti_data1_mem);
1744
1745 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1746 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1747 if (nic->config.intr_type == MSI_X)
1748 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1749 RTI_DATA2_MEM_RX_UFC_D(0x40));
1750 else
1751 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1752 RTI_DATA2_MEM_RX_UFC_D(0x80));
1753 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1754
8a4bdbaa
SS		 1755 for (i = 0; i < config->rx_ring_num; i++) {
1756 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1757 | RTI_CMD_MEM_OFFSET(i);
1758 writeq(val64, &bar0->rti_command_mem);
1da177e4 1759
8a4bdbaa
SS		 1760 /*
1761 * Once the operation completes, the Strobe bit of the
1762 * command register will be reset. We poll for this
1763 * particular condition. We wait for a maximum of 500ms
1764 * for the operation to complete, if it's not complete
1765 * by then we return error.
1766 */
1767 time = 0;
1768 while (TRUE) {
1769 val64 = readq(&bar0->rti_command_mem);
1770 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1771 break;
b6e3f982 1772
8a4bdbaa
SS		 1773 if (time > 10) {
1774 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1775 dev->name);
9f74ffde 1776 return -ENODEV;
b6e3f982 1777 }
8a4bdbaa
SS		 1778 time++;
1779 msleep(50);
1da177e4 1780 }
1da177e4
LT		 1781 }
1782
20346722
K		 1783 /*
1784 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1785 * the 8 Queues on Rx side.
1786 */
1787 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1788 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1789
1790 /* Disable RMAC PAD STRIPPING */
509a2671 1791 add = &bar0->mac_cfg;
1da177e4
LT		 1792 val64 = readq(&bar0->mac_cfg);
1793 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1794 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1795 writel((u32) (val64), add);
1796 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1797 writel((u32) (val64 >> 32), (add + 4));
1798 val64 = readq(&bar0->mac_cfg);
1799
7d3d0439
RA		 1800 /* Enable FCS stripping by adapter */
1801 add = &bar0->mac_cfg;
1802 val64 = readq(&bar0->mac_cfg);
1803 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1804 if (nic->device_type == XFRAME_II_DEVICE)
1805 writeq(val64, &bar0->mac_cfg);
1806 else {
1807 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1808 writel((u32) (val64), add);
1809 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1810 writel((u32) (val64 >> 32), (add + 4));
1811 }
1812
20346722
K		 1813 /*
1814 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1815 * generated by xena.
1816 */
1817 val64 = readq(&bar0->rmac_pause_cfg);
1818 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1819 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1820 writeq(val64, &bar0->rmac_pause_cfg);
1821
20346722 1822 /*
1da177e4
LT		 1823 * Set the Threshold Limit for Generating the pause frame
1824 * If the amount of data in any Queue exceeds ratio of
1825 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1826 * pause frame is generated
1827 */
1828 val64 = 0;
1829 for (i = 0; i < 4; i++) {
1830 val64 |=
1831 (((u64) 0xFF00 | nic->mac_control.
1832 mc_pause_threshold_q0q3)
1833 << (i * 2 * 8));
1834 }
1835 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1836
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
1839 val64 |=
1840 (((u64) 0xFF00 | nic->mac_control.
1841 mc_pause_threshold_q4q7)
1842 << (i * 2 * 8));
1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1845
20346722
K		 1846 /*
1847 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1848 * exceeded the limit pointed by shared_splits
1849 */
1850 val64 = readq(&bar0->pic_control);
1851 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1852 writeq(val64, &bar0->pic_control);
1853
863c11a9
AR		 1854 if (nic->config.bus_speed == 266) {
1855 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1856 writeq(0x0, &bar0->read_retry_delay);
1857 writeq(0x0, &bar0->write_retry_delay);
1858 }
1859
541ae68f
K		 1860 /*
1861 * Programming the Herc to split every write transaction
1862 * that does not start on an ADB to reduce disconnects.
1863 */
1864 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1865 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1866 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1867 writeq(val64, &bar0->misc_control);
1868 val64 = readq(&bar0->pic_control2);
b7b5a128 1869 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1870 writeq(val64, &bar0->pic_control2);
541ae68f 1871 }
c92ca04b
AR		 1872 if (strstr(nic->product_name, "CX4")) {
1873 val64 = TMAC_AVG_IPG(0x17);
1874 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1875 }
1876
1da177e4
LT		 1877 return SUCCESS;
1878}
a371a07d
K		 1879#define LINK_UP_DOWN_INTERRUPT 1
1880#define MAC_RMAC_ERR_TIMER 2
1881
1ee6dd77 1882static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1883{
1884 if (nic->device_type == XFRAME_II_DEVICE)
1885 return LINK_UP_DOWN_INTERRUPT;
1886 else
1887 return MAC_RMAC_ERR_TIMER;
1888}
8116f3cf 1889
9caab458
SS		 1890/**
1891 * do_s2io_write_bits - update alarm bits in alarm register
1892 * @value: alarm bits
1893 * @flag: interrupt status
1894 * @addr: address value
1895 * Description: update alarm bits in alarm register
1896 * Return Value:
1897 * NONE.
1898 */
1899static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1900{
1901 u64 temp64;
1902
1903 temp64 = readq(addr);
1904
1905 if(flag == ENABLE_INTRS)
1906 temp64 &= ~((u64) value);
1907 else
1908 temp64 |= ((u64) value);
1909 writeq(temp64, addr);
1910}
1da177e4 1911
43b7c451 1912static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1913{
1914 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1915 register u64 gen_int_mask = 0;
01e16faa 1916 u64 interruptible;
9caab458 1917
01e16faa 1918 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458
SS		 1919 if (mask & TX_DMA_INTR) {
1920
1921 gen_int_mask |= TXDMA_INT_M;
1922
1923 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1924 TXDMA_PCC_INT | TXDMA_TTI_INT |
1925 TXDMA_LSO_INT | TXDMA_TPA_INT |
1926 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1927
1928 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1929 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1930 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1931 &bar0->pfc_err_mask);
1932
1933 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1934 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1935 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1936
1937 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1938 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1939 PCC_N_SERR | PCC_6_COF_OV_ERR |
1940 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1941 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1942 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1943
1944 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1945 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1946
1947 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1948 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1949 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1950 flag, &bar0->lso_err_mask);
1951
1952 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1953 flag, &bar0->tpa_err_mask);
1954
1955 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1956
1957 }
1958
1959 if (mask & TX_MAC_INTR) {
1960 gen_int_mask |= TXMAC_INT_M;
1961 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1962 &bar0->mac_int_mask);
1963 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1964 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1965 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1966 flag, &bar0->mac_tmac_err_mask);
1967 }
1968
1969 if (mask & TX_XGXS_INTR) {
1970 gen_int_mask |= TXXGXS_INT_M;
1971 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1972 &bar0->xgxs_int_mask);
1973 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1974 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1975 flag, &bar0->xgxs_txgxs_err_mask);
1976 }
1977
1978 if (mask & RX_DMA_INTR) {
1979 gen_int_mask |= RXDMA_INT_M;
1980 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1981 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1982 flag, &bar0->rxdma_int_mask);
1983 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1984 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1985 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1986 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1987 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1988 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1989 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1990 &bar0->prc_pcix_err_mask);
1991 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1992 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1993 &bar0->rpa_err_mask);
1994 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1995 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1996 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1997 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1998 flag, &bar0->rda_err_mask);
1999 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2000 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2001 flag, &bar0->rti_err_mask);
2002 }
2003
2004 if (mask & RX_MAC_INTR) {
2005 gen_int_mask |= RXMAC_INT_M;
2006 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2007 &bar0->mac_int_mask);
01e16faa 2008 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
9caab458 2009 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
01e16faa
SH		 2010 RMAC_DOUBLE_ECC_ERR;
2011 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2012 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2013 do_s2io_write_bits(interruptible,
9caab458
SS		 2014 flag, &bar0->mac_rmac_err_mask);
2015 }
2016
2017 if (mask & RX_XGXS_INTR)
2018 {
2019 gen_int_mask |= RXXGXS_INT_M;
2020 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2021 &bar0->xgxs_int_mask);
2022 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2023 &bar0->xgxs_rxgxs_err_mask);
2024 }
2025
2026 if (mask & MC_INTR) {
2027 gen_int_mask |= MC_INT_M;
2028 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2029 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2030 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2031 &bar0->mc_err_mask);
2032 }
2033 nic->general_int_mask = gen_int_mask;
2034
2035 /* Remove this line when alarm interrupts are enabled */
2036 nic->general_int_mask = 0;
2037}
20346722
K		 2038/**
2039 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2040 * @nic: device private variable,
2041 * @mask: A mask indicating which Intr block must be modified and,
2042 * @flag: A flag indicating whether to enable or disable the Intrs.
2043 * Description: This function will either disable or enable the interrupts
20346722
K		 2044 * depending on the flag argument. The mask argument can be used to
2045 * enable/disable any Intr block.
1da177e4
LT		 2046 * Return Value: NONE.
2047 */
2048
2049static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2050{
1ee6dd77 2051 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2052 register u64 temp64 = 0, intr_mask = 0;
2053
2054 intr_mask = nic->general_int_mask;
1da177e4
LT		 2055
2056 /* Top level interrupt classification */
2057 /* PIC Interrupts */
9caab458 2058 if (mask & TX_PIC_INTR) {
1da177e4 2059 /* Enable PIC Intrs in the general intr mask register */
9caab458 2060 intr_mask |= TXPIC_INT_M;
1da177e4 2061 if (flag == ENABLE_INTRS) {
20346722 2062 /*
a371a07d 2063 * If Hercules adapter enable GPIO otherwise
b41477f3 2064 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2065 * interrupts for now.
2066 * TODO
1da177e4 2067 */
a371a07d
K		 2068 if (s2io_link_fault_indication(nic) ==
2069 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2070 do_s2io_write_bits(PIC_INT_GPIO, flag,
2071 &bar0->pic_int_mask);
2072 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2073 &bar0->gpio_int_mask);
2074 } else
a371a07d 2075 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2076 } else if (flag == DISABLE_INTRS) {
20346722
K		 2077 /*
2078 * Disable PIC Intrs in the general
2079 * intr mask register
1da177e4
LT		 2080 */
2081 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2082 }
2083 }
2084
1da177e4
LT		 2085 /* Tx traffic interrupts */
2086 if (mask & TX_TRAFFIC_INTR) {
9caab458 2087 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2088 if (flag == ENABLE_INTRS) {
20346722 2089 /*
1da177e4 2090 * Enable all the Tx side interrupts
20346722 2091 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2092 */
2093 writeq(0x0, &bar0->tx_traffic_mask);
2094 } else if (flag == DISABLE_INTRS) {
20346722
K		 2095 /*
2096 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2097 * register.
2098 */
2099 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2100 }
2101 }
2102
2103 /* Rx traffic interrupts */
2104 if (mask & RX_TRAFFIC_INTR) {
9caab458 2105 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2106 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2107 /* writing 0 Enables all 8 RX interrupt levels */
2108 writeq(0x0, &bar0->rx_traffic_mask);
2109 } else if (flag == DISABLE_INTRS) {
20346722
K		 2110 /*
2111 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2112 * register.
2113 */
2114 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2115 }
2116 }
9caab458
SS		 2117
2118 temp64 = readq(&bar0->general_int_mask);
2119 if (flag == ENABLE_INTRS)
2120 temp64 &= ~((u64) intr_mask);
2121 else
2122 temp64 = DISABLE_ALL_INTRS;
2123 writeq(temp64, &bar0->general_int_mask);
2124
2125 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2126}
2127
19a60522
SS		 2128/**
2129 * verify_pcc_quiescent- Checks for PCC quiescent state
2130 * Return: 1 If PCC is quiescence
2131 * 0 If PCC is not quiescence
2132 */
1ee6dd77 2133static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2134{
19a60522 2135 int ret = 0, herc;
1ee6dd77 2136 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2137 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2138
19a60522 2139 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 2140
2141 if (flag == FALSE) {
44c10138 2142 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2143 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2144 ret = 1;
19a60522
SS		 2145 } else {
2146 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2147 ret = 1;
20346722
K		 2148 }
2149 } else {
44c10138 2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2151 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2152 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2153 ret = 1;
5e25b9dd
K		 2154 } else {
2155 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2156 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2157 ret = 1;
20346722
K		 2158 }
2159 }
2160
2161 return ret;
2162}
2163/**
2164 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2165 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2166 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2167 * differs and the calling function passes the input argument flag to
2168 * indicate this.
20346722 2169 * Return: 1 If xena is quiescence
1da177e4
LT		 2170 * 0 If Xena is not quiescence
2171 */
2172
1ee6dd77 2173static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2174{
19a60522 2175 int mode;
1ee6dd77 2176 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2177 u64 val64 = readq(&bar0->adapter_status);
2178 mode = s2io_verify_pci_mode(sp);
1da177e4 2179
19a60522
SS		 2180 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2181 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2182 return 0;
2183 }
2184 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2185 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2186 return 0;
2187 }
2188 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2189 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2193 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2197 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2201 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2205 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2209 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2210 return 0;
1da177e4
LT		 2211 }
2212
19a60522
SS		 2213 /*
2214 * In PCI 33 mode, the P_PLL is not used, and therefore,
2215 * the the P_PLL_LOCK bit in the adapter_status register will
2216 * not be asserted.
2217 */
2218 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2219 sp->device_type == XFRAME_II_DEVICE && mode !=
2220 PCI_MODE_PCI_33) {
2221 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2222 return 0;
2223 }
2224 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2225 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2226 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2227 return 0;
2228 }
2229 return 1;
1da177e4
LT		 2230}
2231
2232/**
2233 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2234 * @sp: Pointer to device specifc structure
20346722 2235 * Description :
1da177e4
LT		 2236 * New procedure to clear mac address reading problems on Alpha platforms
2237 *
2238 */
2239
1ee6dd77 2240static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2241{
1ee6dd77 2242 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2243 u64 val64;
2244 int i = 0;
2245
2246 while (fix_mac[i] != END_SIGN) {
2247 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2248 udelay(10);
1da177e4
LT		 2249 val64 = readq(&bar0->gpio_control);
2250 }
2251}
2252
2253/**
20346722 2254 * start_nic - Turns the device on
1da177e4 2255 * @nic : device private variable.
20346722
K		 2256 * Description:
2257 * This function actually turns the device on. Before this function is
2258 * called,all Registers are configured from their reset states
2259 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2260 * calling this function, the device interrupts are cleared and the NIC is
2261 * literally switched on by writing into the adapter control register.
20346722 2262 * Return Value:
1da177e4
LT		 2263 * SUCCESS on success and -1 on failure.
2264 */
2265
2266static int start_nic(struct s2io_nic *nic)
2267{
1ee6dd77 2268 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2269 struct net_device *dev = nic->dev;
2270 register u64 val64 = 0;
20346722 2271 u16 subid, i;
1ee6dd77 2272 struct mac_info *mac_control;
1da177e4
LT		 2273 struct config_param *config;
2274
2275 mac_control = &nic->mac_control;
2276 config = &nic->config;
2277
2278 /* PRC Initialization and configuration */
2279 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2280 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2281 &bar0->prc_rxd0_n[i]);
2282
2283 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2284 if (nic->rxd_mode == RXD_MODE_1)
2285 val64 |= PRC_CTRL_RC_ENABLED;
2286 else
2287 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2288 if (nic->device_type == XFRAME_II_DEVICE)
2289 val64 |= PRC_CTRL_GROUP_READS;
2290 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2291 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2292 writeq(val64, &bar0->prc_ctrl_n[i]);
2293 }
2294
da6971d8
AR		 2295 if (nic->rxd_mode == RXD_MODE_3B) {
2296 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2297 val64 = readq(&bar0->rx_pa_cfg);
2298 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2299 writeq(val64, &bar0->rx_pa_cfg);
2300 }
1da177e4 2301
926930b2
SS		 2302 if (vlan_tag_strip == 0) {
2303 val64 = readq(&bar0->rx_pa_cfg);
2304 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2305 writeq(val64, &bar0->rx_pa_cfg);
2306 vlan_strip_flag = 0;
2307 }
2308
20346722 2309 /*
1da177e4
LT		 2310 * Enabling MC-RLDRAM. After enabling the device, we timeout
2311 * for around 100ms, which is approximately the time required
2312 * for the device to be ready for operation.
2313 */
2314 val64 = readq(&bar0->mc_rldram_mrs);
2315 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2316 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2317 val64 = readq(&bar0->mc_rldram_mrs);
2318
20346722 2319 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2320
2321 /* Enabling ECC Protection. */
2322 val64 = readq(&bar0->adapter_control);
2323 val64 &= ~ADAPTER_ECC_EN;
2324 writeq(val64, &bar0->adapter_control);
2325
20346722
K		 2326 /*
2327 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2328 * it.
2329 */
2330 val64 = readq(&bar0->adapter_status);
19a60522 2331 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2332 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2333 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2334 (unsigned long long) val64);
2335 return FAILURE;
2336 }
2337
20346722 2338 /*
1da177e4 2339 * With some switches, link might be already up at this point.
20346722
K		 2340 * Because of this weird behavior, when we enable laser,
2341 * we may not get link. We need to handle this. We cannot
2342 * figure out which switch is misbehaving. So we are forced to
2343 * make a global change.
1da177e4
LT		 2344 */
2345
2346 /* Enabling Laser. */
2347 val64 = readq(&bar0->adapter_control);
2348 val64 |= ADAPTER_EOI_TX_ON;
2349 writeq(val64, &bar0->adapter_control);
2350
c92ca04b
AR		 2351 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2352 /*
2353 * Dont see link state interrupts initally on some switches,
2354 * so directly scheduling the link state task here.
2355 */
2356 schedule_work(&nic->set_link_task);
2357 }
1da177e4
LT		 2358 /* SXE-002: Initialize link and activity LED */
2359 subid = nic->pdev->subsystem_device;
541ae68f
K		 2360 if (((subid & 0xFF) >= 0x07) &&
2361 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2362 val64 = readq(&bar0->gpio_control);
2363 val64 |= 0x0000800000000000ULL;
2364 writeq(val64, &bar0->gpio_control);
2365 val64 = 0x0411040400000000ULL;
509a2671 2366 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2367 }
2368
1da177e4
LT		 2369 return SUCCESS;
2370}
fed5eccd
AR		 2371/**
2372 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2373 */
1ee6dd77
RB		 2374static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2375 TxD *txdlp, int get_off)
fed5eccd 2376{
1ee6dd77 2377 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2378 struct sk_buff *skb;
1ee6dd77 2379 struct TxD *txds;
fed5eccd
AR		 2380 u16 j, frg_cnt;
2381
2382 txds = txdlp;
2fda096d 2383 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2384 pci_unmap_single(nic->pdev, (dma_addr_t)
2385 txds->Buffer_Pointer, sizeof(u64),
2386 PCI_DMA_TODEVICE);
2387 txds++;
2388 }
2389
2390 skb = (struct sk_buff *) ((unsigned long)
2391 txds->Host_Control);
2392 if (!skb) {
1ee6dd77 2393 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2394 return NULL;
2395 }
2396 pci_unmap_single(nic->pdev, (dma_addr_t)
2397 txds->Buffer_Pointer,
2398 skb->len - skb->data_len,
2399 PCI_DMA_TODEVICE);
2400 frg_cnt = skb_shinfo(skb)->nr_frags;
2401 if (frg_cnt) {
2402 txds++;
2403 for (j = 0; j < frg_cnt; j++, txds++) {
2404 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2405 if (!txds->Buffer_Pointer)
2406 break;
6aa20a22 2407 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2408 txds->Buffer_Pointer,
2409 frag->size, PCI_DMA_TODEVICE);
2410 }
2411 }
1ee6dd77 2412 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2413 return(skb);
2414}
1da177e4 2415
20346722
K		 2416/**
2417 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2418 * @nic : device private variable.
20346722 2419 * Description:
1da177e4 2420 * Free all queued Tx buffers.
20346722 2421 * Return Value: void
1da177e4
LT		 2422*/
2423
2424static void free_tx_buffers(struct s2io_nic *nic)
2425{
2426 struct net_device *dev = nic->dev;
2427 struct sk_buff *skb;
1ee6dd77 2428 struct TxD *txdp;
1da177e4 2429 int i, j;
1ee6dd77 2430 struct mac_info *mac_control;
1da177e4 2431 struct config_param *config;
fed5eccd 2432 int cnt = 0;
1da177e4
LT		 2433
2434 mac_control = &nic->mac_control;
2435 config = &nic->config;
2436
2437 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2438 unsigned long flags;
2439 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
b35b3b49 2440 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
491976b2
SH		 2441 txdp = (struct TxD *) \
2442 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2443 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2444 if (skb) {
8a4bdbaa 2445 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2446 += skb->truesize;
fed5eccd
AR		 2447 dev_kfree_skb(skb);
2448 cnt++;
1da177e4 2449 }
1da177e4
LT		 2450 }
2451 DBG_PRINT(INTR_DBG,
2452 "%s:forcibly freeing %d skbs on FIFO%d\n",
2453 dev->name, cnt, i);
20346722
K		 2454 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2455 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2456 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2457 }
2458}
2459
20346722
K		 2460/**
2461 * stop_nic - To stop the nic
1da177e4 2462 * @nic ; device private variable.
20346722
K		 2463 * Description:
2464 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2465 * function does. This function is called to stop the device.
2466 * Return Value:
2467 * void.
2468 */
2469
2470static void stop_nic(struct s2io_nic *nic)
2471{
1ee6dd77 2472 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2473 register u64 val64 = 0;
5d3213cc 2474 u16 interruptible;
1ee6dd77 2475 struct mac_info *mac_control;
1da177e4
LT		 2476 struct config_param *config;
2477
2478 mac_control = &nic->mac_control;
2479 config = &nic->config;
2480
2481 /* Disable all interrupts */
9caab458 2482 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2483 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2484 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2485 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2486
5d3213cc
AR		 2487 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2488 val64 = readq(&bar0->adapter_control);
2489 val64 &= ~(ADAPTER_CNTL_EN);
2490 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2491}
2492
20346722
K		 2493/**
2494 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2495 * @ring_info: per ring structure
3f78d885
SH		 2496 * @from_card_up: If this is true, we will map the buffer to get
2497 * the dma address for buf0 and buf1 to give it to the card.
2498 * Else we will sync the already mapped buffer to give it to the card.
20346722 2499 * Description:
1da177e4
LT		 2500 * The function allocates Rx side skbs and puts the physical
2501 * address of these buffers into the RxD buffer pointers, so that the NIC
2502 * can DMA the received frame into these locations.
2503 * The NIC supports 3 receive modes, viz
2504 * 1. single buffer,
2505 * 2. three buffer and
2506 * 3. Five buffer modes.
20346722
K		 2507 * Each mode defines how many fragments the received frame will be split
2508 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2509 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2510 * is split into 3 fragments. As of now only single buffer mode is
2511 * supported.
2512 * Return Value:
2513 * SUCCESS on success or an appropriate -ve value on failure.
2514 */
8d8bb39b
FT		 2515static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2516 int from_card_up)
1da177e4 2517{
1da177e4 2518 struct sk_buff *skb;
1ee6dd77 2519 struct RxD_t *rxdp;
0425b46a 2520 int off, size, block_no, block_no1;
1da177e4 2521 u32 alloc_tab = 0;
20346722 2522 u32 alloc_cnt;
20346722 2523 u64 tmp;
1ee6dd77 2524 struct buffAdd *ba;
1ee6dd77 2525 struct RxD_t *first_rxdp = NULL;
363dc367 2526 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2527 int rxd_index = 0;
6d517a27
VP		 2528 struct RxD1 *rxdp1;
2529 struct RxD3 *rxdp3;
0425b46a 2530 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2531
0425b46a 2532 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2533
0425b46a 2534 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2535 while (alloc_tab < alloc_cnt) {
0425b46a 2536 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2537
0425b46a
SH		 2538 off = ring->rx_curr_put_info.offset;
2539
2540 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2541
2542 rxd_index = off + 1;
2543 if (block_no)
2544 rxd_index += (block_no * ring->rxd_count);
da6971d8 2545
7d2e3cb7 2546 if ((block_no == block_no1) &&
0425b46a
SH		 2547 (off == ring->rx_curr_get_info.offset) &&
2548 (rxdp->Host_Control)) {
da6971d8 2549 DBG_PRINT(INTR_DBG, "%s: Get and Put",
0425b46a 2550 ring->dev->name);
1da177e4
LT		 2551 DBG_PRINT(INTR_DBG, " info equated\n");
2552 goto end;
2553 }
0425b46a
SH		 2554 if (off && (off == ring->rxd_count)) {
2555 ring->rx_curr_put_info.block_index++;
2556 if (ring->rx_curr_put_info.block_index ==
2557 ring->block_count)
2558 ring->rx_curr_put_info.block_index = 0;
2559 block_no = ring->rx_curr_put_info.block_index;
2560 off = 0;
2561 ring->rx_curr_put_info.offset = off;
2562 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2563 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2564 ring->dev->name, rxdp);
2565
1da177e4 2566 }
c9fcbf47 2567
da6971d8 2568 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
0425b46a 2569 ((ring->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2570 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2571 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2572 goto end;
2573 }
da6971d8 2574 /* calculate size of skb based on ring mode */
0425b46a 2575 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
da6971d8 2576 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2577 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2578 size += NET_IP_ALIGN;
da6971d8 2579 else
0425b46a 2580 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2581
da6971d8
AR		 2582 /* allocate skb */
2583 skb = dev_alloc_skb(size);
2584 if(!skb) {
0425b46a 2585 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2586 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2587 if (first_rxdp) {
2588 wmb();
2589 first_rxdp->Control_1 |= RXD_OWN_XENA;
2590 }
0425b46a 2591 stats->mem_alloc_fail_cnt++;
7d2e3cb7 2592
da6971d8
AR		 2593 return -ENOMEM ;
2594 }
0425b46a
SH		 2595 stats->mem_allocated += skb->truesize;
2596
2597 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2598 /* 1 buffer mode - normal operation mode */
6d517a27 2599 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2600 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2601 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2602 rxdp1->Buffer0_ptr = pci_map_single
0425b46a 2603 (ring->pdev, skb->data, size - NET_IP_ALIGN,
863c11a9 2604 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2605 if (pci_dma_mapping_error(nic->pdev,
2606 rxdp1->Buffer0_ptr))
491abf25
VP		 2607 goto pci_map_failed;
2608
8a4bdbaa 2609 rxdp->Control_2 =
491976b2 2610 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
0425b46a
SH		 2611 rxdp->Host_Control = (unsigned long) (skb);
2612 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2613 /*
6d517a27
VP		 2614 * 2 buffer mode -
2615 * 2 buffer mode provides 128
da6971d8 2616 * byte aligned receive buffers.
da6971d8
AR		 2617 */
2618
6d517a27 2619 rxdp3 = (struct RxD3*)rxdp;
491976b2 2620 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2621 Buffer0_ptr = rxdp3->Buffer0_ptr;
2622 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2623 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2624 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2625 rxdp3->Buffer0_ptr = Buffer0_ptr;
2626 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2627
0425b46a 2628 ba = &ring->ba[block_no][off];
da6971d8
AR		 2629 skb_reserve(skb, BUF0_LEN);
2630 tmp = (u64)(unsigned long) skb->data;
2631 tmp += ALIGN_SIZE;
2632 tmp &= ~ALIGN_SIZE;
2633 skb->data = (void *) (unsigned long)tmp;
27a884dc 2634 skb_reset_tail_pointer(skb);
da6971d8 2635
3f78d885 2636 if (from_card_up) {
6d517a27 2637 rxdp3->Buffer0_ptr =
0425b46a
SH		 2638 pci_map_single(ring->pdev, ba->ba_0,
2639 BUF0_LEN, PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
3f78d885
SH		 2642 goto pci_map_failed;
2643 } else
0425b46a 2644 pci_dma_sync_single_for_device(ring->pdev,
6d517a27 2645 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2646 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25 2647
da6971d8 2648 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2649 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2650 /* Two buffer mode */
2651
2652 /*
6aa20a22 2653 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2654 * L4 payload
2655 */
6d517a27 2656 rxdp3->Buffer2_ptr = pci_map_single
0425b46a 2657 (ring->pdev, skb->data, ring->mtu + 4,
da6971d8
AR		 2658 PCI_DMA_FROMDEVICE);
2659
8d8bb39b
FT		 2660 if (pci_dma_mapping_error(nic->pdev,
2661 rxdp3->Buffer2_ptr))
491abf25
VP		 2662 goto pci_map_failed;
2663
3f78d885 2664 if (from_card_up) {
0425b46a
SH		 2665 rxdp3->Buffer1_ptr =
2666 pci_map_single(ring->pdev,
75c30b13
AR		 2667 ba->ba_1, BUF1_LEN,
2668 PCI_DMA_FROMDEVICE);
0425b46a 2669
8d8bb39b
FT		 2670 if (pci_dma_mapping_error(nic->pdev,
2671 rxdp3->Buffer1_ptr)) {
3f78d885
SH		 2672 pci_unmap_single
2673 (ring->pdev,
2674 (dma_addr_t)(unsigned long)
2675 skb->data,
2676 ring->mtu + 4,
2677 PCI_DMA_FROMDEVICE);
2678 goto pci_map_failed;
2679 }
75c30b13 2680 }
da6971d8
AR		 2681 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2682 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
0425b46a 2683 (ring->mtu + 4);
da6971d8 2684 }
b7b5a128 2685 rxdp->Control_2 |= s2BIT(0);
0425b46a 2686 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2687 }
303bcb4b
K		 2688 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2689 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2690 off++;
0425b46a 2691 if (off == (ring->rxd_count + 1))
da6971d8 2692 off = 0;
0425b46a 2693 ring->rx_curr_put_info.offset = off;
20346722 2694
da6971d8 2695 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2696 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2697 if (first_rxdp) {
2698 wmb();
2699 first_rxdp->Control_1 |= RXD_OWN_XENA;
2700 }
2701 first_rxdp = rxdp;
2702 }
0425b46a 2703 ring->rx_bufs_left += 1;
1da177e4
LT		 2704 alloc_tab++;
2705 }
2706
2707 end:
303bcb4b
K		 2708 /* Transfer ownership of first descriptor to adapter just before
2709 * exiting. Before that, use memory barrier so that ownership
2710 * and other fields are seen by adapter correctly.
2711 */
2712 if (first_rxdp) {
2713 wmb();
2714 first_rxdp->Control_1 |= RXD_OWN_XENA;
2715 }
2716
1da177e4 2717 return SUCCESS;
491abf25
VP		 2718pci_map_failed:
2719 stats->pci_map_fail_cnt++;
2720 stats->mem_freed += skb->truesize;
2721 dev_kfree_skb_irq(skb);
2722 return -ENOMEM;
1da177e4
LT		 2723}
2724
da6971d8
AR		 2725static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2726{
2727 struct net_device *dev = sp->dev;
2728 int j;
2729 struct sk_buff *skb;
1ee6dd77
RB		 2730 struct RxD_t *rxdp;
2731 struct mac_info *mac_control;
2732 struct buffAdd *ba;
6d517a27
VP		 2733 struct RxD1 *rxdp1;
2734 struct RxD3 *rxdp3;
da6971d8
AR		 2735
2736 mac_control = &sp->mac_control;
2737 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2738 rxdp = mac_control->rings[ring_no].
2739 rx_blocks[blk].rxds[j].virt_addr;
2740 skb = (struct sk_buff *)
2741 ((unsigned long) rxdp->Host_Control);
2742 if (!skb) {
2743 continue;
2744 }
2745 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2746 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2747 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2748 rxdp1->Buffer0_ptr,
2749 dev->mtu +
2750 HEADER_ETHERNET_II_802_3_SIZE
2751 + HEADER_802_2_SIZE +
2752 HEADER_SNAP_SIZE,
2753 PCI_DMA_FROMDEVICE);
1ee6dd77 2754 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2755 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2756 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2757 ba = &mac_control->rings[ring_no].
2758 ba[blk][j];
2759 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2760 rxdp3->Buffer0_ptr,
2761 BUF0_LEN,
da6971d8
AR		 2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2764 rxdp3->Buffer1_ptr,
2765 BUF1_LEN,
da6971d8
AR		 2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2768 rxdp3->Buffer2_ptr,
2769 dev->mtu + 4,
da6971d8 2770 PCI_DMA_FROMDEVICE);
1ee6dd77 2771 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2772 }
491976b2 2773 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2774 dev_kfree_skb(skb);
0425b46a 2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2776 }
2777}
2778
1da177e4 2779/**
20346722 2780 * free_rx_buffers - Frees all Rx buffers
1da177e4 2781 * @sp: device private variable.
20346722 2782 * Description:
1da177e4
LT		 2783 * This function will free all Rx buffers allocated by host.
2784 * Return Value:
2785 * NONE.
2786 */
2787
2788static void free_rx_buffers(struct s2io_nic *sp)
2789{
2790 struct net_device *dev = sp->dev;
da6971d8 2791 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2792 struct mac_info *mac_control;
1da177e4 2793 struct config_param *config;
1da177e4
LT		 2794
2795 mac_control = &sp->mac_control;
2796 config = &sp->config;
2797
2798 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2799 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2800 free_rxd_blk(sp,i,blk);
1da177e4 2801
20346722
K		 2802 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2803 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2804 mac_control->rings[i].rx_curr_put_info.offset = 0;
2805 mac_control->rings[i].rx_curr_get_info.offset = 0;
0425b46a 2806 mac_control->rings[i].rx_bufs_left = 0;
1da177e4
LT		 2807 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2808 dev->name, buf_cnt, i);
2809 }
2810}
2811
8d8bb39b 2812static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2813{
8d8bb39b 2814 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2815 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2816 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2817 }
2818 return 0;
2819}
2820
1da177e4
LT		 2821/**
2822 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2823 * @napi : pointer to the napi structure.
20346722 2824 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2825 * during one pass through the 'Poll" function.
2826 * Description:
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2830 * Return value:
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2832 */
2833
f61e0a35 2834static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2835{
f61e0a35
SH		 2836 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2837 struct net_device *dev = ring->dev;
1da177e4 2838 struct config_param *config;
f61e0a35
SH		 2839 struct mac_info *mac_control;
2840 int pkts_processed = 0;
1a79d1c3
AV		 2841 u8 __iomem *addr = NULL;
2842 u8 val8 = 0;
f61e0a35 2843 struct s2io_nic *nic = dev->priv;
1ee6dd77 2844 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2845 int budget_org = budget;
1da177e4 2846
1da177e4 2847 config = &nic->config;
f61e0a35 2848 mac_control = &nic->mac_control;
1da177e4 2849
f61e0a35
SH		 2850 if (unlikely(!is_s2io_card_up(nic)))
2851 return 0;
1da177e4 2852
f61e0a35 2853 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2854 s2io_chk_rx_buffers(nic, ring);
1da177e4 2855
f61e0a35
SH		 2856 if (pkts_processed < budget_org) {
2857 netif_rx_complete(dev, napi);
2858 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2859 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2860 addr += 7 - ring->ring_no;
2861 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2862 writeb(val8, addr);
2863 val8 = readb(addr);
1da177e4 2864 }
f61e0a35
SH		 2865 return pkts_processed;
2866}
2867static int s2io_poll_inta(struct napi_struct *napi, int budget)
2868{
2869 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2870 struct ring_info *ring;
2871 struct net_device *dev = nic->dev;
2872 struct config_param *config;
2873 struct mac_info *mac_control;
2874 int pkts_processed = 0;
2875 int ring_pkts_processed, i;
2876 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2877 int budget_org = budget;
1da177e4 2878
f61e0a35
SH		 2879 config = &nic->config;
2880 mac_control = &nic->mac_control;
1da177e4 2881
f61e0a35
SH		 2882 if (unlikely(!is_s2io_card_up(nic)))
2883 return 0;
1da177e4 2884
1da177e4 2885 for (i = 0; i < config->rx_ring_num; i++) {
f61e0a35
SH		 2886 ring = &mac_control->rings[i];
2887 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2888 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2889 pkts_processed += ring_pkts_processed;
2890 budget -= ring_pkts_processed;
2891 if (budget <= 0)
1da177e4 2892 break;
1da177e4 2893 }
f61e0a35
SH		 2894 if (pkts_processed < budget_org) {
2895 netif_rx_complete(dev, napi);
2896 /* Re enable the Rx interrupts for the ring */
2897 writeq(0, &bar0->rx_traffic_mask);
2898 readl(&bar0->rx_traffic_mask);
2899 }
2900 return pkts_processed;
1da177e4 2901}
20346722 2902
b41477f3 2903#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2904/**
b41477f3 2905 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2906 * @dev : pointer to the device structure.
2907 * Description:
b41477f3
AR		 2908 * This function will be called by upper layer to check for events on the
2909 * interface in situations where interrupts are disabled. It is used for
2910 * specific in-kernel networking tasks, such as remote consoles and kernel
2911 * debugging over the network (example netdump in RedHat).
612eff0e 2912 */
612eff0e
BH		 2913static void s2io_netpoll(struct net_device *dev)
2914{
1ee6dd77
RB		 2915 struct s2io_nic *nic = dev->priv;
2916 struct mac_info *mac_control;
612eff0e 2917 struct config_param *config;
1ee6dd77 2918 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2919 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2920 int i;
2921
d796fdb7
LV		 2922 if (pci_channel_offline(nic->pdev))
2923 return;
2924
612eff0e
BH		 2925 disable_irq(dev->irq);
2926
612eff0e
BH		 2927 mac_control = &nic->mac_control;
2928 config = &nic->config;
2929
612eff0e 2930 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2931 writeq(val64, &bar0->tx_traffic_int);
2932
6aa20a22 2933 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2934 * run out of skbs and will fail and eventually netpoll application such
2935 * as netdump will fail.
2936 */
2937 for (i = 0; i < config->tx_fifo_num; i++)
2938 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2939
b41477f3 2940 /* check for received packet and indicate up to network */
612eff0e 2941 for (i = 0; i < config->rx_ring_num; i++)
f61e0a35 2942 rx_intr_handler(&mac_control->rings[i], 0);
612eff0e
BH		 2943
2944 for (i = 0; i < config->rx_ring_num; i++) {
8d8bb39b
FT		 2945 if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
2946 -ENOMEM) {
0c61ed5f
RV		 2947 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2948 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2949 break;
2950 }
2951 }
612eff0e
BH		 2952 enable_irq(dev->irq);
2953 return;
2954}
2955#endif
2956
20346722 2957/**
1da177e4 2958 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2959 * @ring_info: per ring structure.
2960 * @budget: budget for napi processing.
20346722
K		 2961 * Description:
2962 * If the interrupt is because of a received frame or if the
1da177e4 2963 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2964 * called. It picks out the RxD at which place the last Rx processing had
2965 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2966 * the offset.
2967 * Return Value:
f61e0a35 2968 * No. of napi packets processed.
1da177e4 2969 */
f61e0a35 2970static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2971{
c9fcbf47 2972 int get_block, put_block;
1ee6dd77
RB		 2973 struct rx_curr_get_info get_info, put_info;
2974 struct RxD_t *rxdp;
1da177e4 2975 struct sk_buff *skb;
f61e0a35 2976 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2977 int i;
6d517a27
VP		 2978 struct RxD1* rxdp1;
2979 struct RxD3* rxdp3;
7d3d0439 2980
20346722
K		 2981 get_info = ring_data->rx_curr_get_info;
2982 get_block = get_info.block_index;
1ee6dd77 2983 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2984 put_block = put_info.block_index;
da6971d8 2985 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2986
da6971d8 2987 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2988 /*
2989 * If your are next to put index then it's
2990 * FIFO full condition
2991 */
da6971d8
AR		 2992 if ((get_block == put_block) &&
2993 (get_info.offset + 1) == put_info.offset) {
0425b46a
SH		 2994 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2995 ring_data->dev->name);
da6971d8
AR		 2996 break;
2997 }
20346722
K		 2998 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2999 if (skb == NULL) {
3000 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 3001 ring_data->dev->name);
20346722 3002 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 3003 return 0;
1da177e4 3004 }
0425b46a 3005 if (ring_data->rxd_mode == RXD_MODE_1) {
6d517a27 3006 rxdp1 = (struct RxD1*)rxdp;
0425b46a 3007 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3008 rxdp1->Buffer0_ptr,
0425b46a 3009 ring_data->mtu +
6d517a27
VP		 3010 HEADER_ETHERNET_II_802_3_SIZE +
3011 HEADER_802_2_SIZE +
3012 HEADER_SNAP_SIZE,
3013 PCI_DMA_FROMDEVICE);
0425b46a 3014 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
6d517a27 3015 rxdp3 = (struct RxD3*)rxdp;
0425b46a 3016 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
6d517a27
VP		 3017 rxdp3->Buffer0_ptr,
3018 BUF0_LEN, PCI_DMA_FROMDEVICE);
0425b46a 3019 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3020 rxdp3->Buffer2_ptr,
0425b46a 3021 ring_data->mtu + 4,
6d517a27 3022 PCI_DMA_FROMDEVICE);
da6971d8 3023 }
863c11a9 3024 prefetch(skb->data);
20346722
K		 3025 rx_osm_handler(ring_data, rxdp);
3026 get_info.offset++;
da6971d8
AR		 3027 ring_data->rx_curr_get_info.offset = get_info.offset;
3028 rxdp = ring_data->rx_blocks[get_block].
3029 rxds[get_info.offset].virt_addr;
0425b46a 3030 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3031 get_info.offset = 0;
da6971d8 3032 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3033 get_block++;
da6971d8
AR		 3034 if (get_block == ring_data->block_count)
3035 get_block = 0;
3036 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3037 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3038 }
1da177e4 3039
f61e0a35
SH		 3040 if (ring_data->nic->config.napi) {
3041 budget--;
3042 napi_pkts++;
3043 if (!budget)
0425b46a
SH		 3044 break;
3045 }
20346722 3046 pkt_cnt++;
1da177e4
LT		 3047 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3048 break;
3049 }
0425b46a 3050 if (ring_data->lro) {
7d3d0439
RA		 3051 /* Clear all LRO sessions before exiting */
3052 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 3053 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3054 if (lro->in_use) {
0425b46a 3055 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3056 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3057 clear_lro_session(lro);
3058 }
3059 }
3060 }
f61e0a35 3061 return(napi_pkts);
1da177e4 3062}
20346722
K		 3063
3064/**
1da177e4
LT		 3065 * tx_intr_handler - Transmit interrupt handler
3066 * @nic : device private variable
20346722
K		 3067 * Description:
3068 * If an interrupt was raised to indicate DMA complete of the
3069 * Tx packet, this function is called. It identifies the last TxD
3070 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3071 * DMA'ed into the NICs internal memory.
3072 * Return Value:
3073 * NONE
3074 */
3075
1ee6dd77 3076static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3077{
1ee6dd77 3078 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3079 struct tx_curr_get_info get_info, put_info;
3a3d5756 3080 struct sk_buff *skb = NULL;
1ee6dd77 3081 struct TxD *txdlp;
3a3d5756 3082 int pkt_cnt = 0;
2fda096d 3083 unsigned long flags = 0;
f9046eb3 3084 u8 err_mask;
1da177e4 3085
2fda096d
SR		 3086 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3087 return;
3088
20346722 3089 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3090 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3091 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 3092 list_virt_addr;
3093 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3094 (get_info.offset != put_info.offset) &&
3095 (txdlp->Host_Control)) {
3096 /* Check for TxD errors */
3097 if (txdlp->Control_1 & TXD_T_CODE) {
3098 unsigned long long err;
3099 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3100 if (err & 0x1) {
3101 nic->mac_control.stats_info->sw_stat.
3102 parity_err_cnt++;
3103 }
491976b2
SH		 3104
3105 /* update t_code statistics */
f9046eb3
OH		 3106 err_mask = err >> 48;
3107 switch(err_mask) {
491976b2
SH		 3108 case 2:
3109 nic->mac_control.stats_info->sw_stat.
3110 tx_buf_abort_cnt++;
3111 break;
3112
3113 case 3:
3114 nic->mac_control.stats_info->sw_stat.
3115 tx_desc_abort_cnt++;
3116 break;
3117
3118 case 7:
3119 nic->mac_control.stats_info->sw_stat.
3120 tx_parity_err_cnt++;
3121 break;
3122
3123 case 10:
3124 nic->mac_control.stats_info->sw_stat.
3125 tx_link_loss_cnt++;
3126 break;
3127
3128 case 15:
3129 nic->mac_control.stats_info->sw_stat.
3130 tx_list_proc_err_cnt++;
3131 break;
3132 }
20346722 3133 }
1da177e4 3134
fed5eccd 3135 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3136 if (skb == NULL) {
2fda096d 3137 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722
K		 3138 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3139 __FUNCTION__);
3140 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3141 return;
3142 }
3a3d5756 3143 pkt_cnt++;
20346722 3144
20346722 3145 /* Updating the statistics block */
20346722 3146 nic->stats.tx_bytes += skb->len;
491976b2 3147 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 3148 dev_kfree_skb_irq(skb);
3149
3150 get_info.offset++;
863c11a9
AR		 3151 if (get_info.offset == get_info.fifo_len + 1)
3152 get_info.offset = 0;
1ee6dd77 3153 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 3154 [get_info.offset].list_virt_addr;
3155 fifo_data->tx_curr_get_info.offset =
3156 get_info.offset;
1da177e4
LT		 3157 }
3158
3a3d5756 3159 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3160
3161 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3162}
3163
bd1034f0
AR		 3164/**
3165 * s2io_mdio_write - Function to write in to MDIO registers
3166 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3167 * @addr : address value
3168 * @value : data value
3169 * @dev : pointer to net_device structure
3170 * Description:
3171 * This function is used to write values to the MDIO registers
3172 * NONE
3173 */
3174static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3175{
3176 u64 val64 = 0x0;
1ee6dd77
RB		 3177 struct s2io_nic *sp = dev->priv;
3178 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3179
3180 //address transaction
3181 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3182 | MDIO_MMD_DEV_ADDR(mmd_type)
3183 | MDIO_MMS_PRT_ADDR(0x0);
3184 writeq(val64, &bar0->mdio_control);
3185 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3186 writeq(val64, &bar0->mdio_control);
3187 udelay(100);
3188
3189 //Data transaction
3190 val64 = 0x0;
3191 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3192 | MDIO_MMD_DEV_ADDR(mmd_type)
3193 | MDIO_MMS_PRT_ADDR(0x0)
3194 | MDIO_MDIO_DATA(value)
3195 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3196 writeq(val64, &bar0->mdio_control);
3197 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3198 writeq(val64, &bar0->mdio_control);
3199 udelay(100);
3200
3201 val64 = 0x0;
3202 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3203 | MDIO_MMD_DEV_ADDR(mmd_type)
3204 | MDIO_MMS_PRT_ADDR(0x0)
3205 | MDIO_OP(MDIO_OP_READ_TRANS);
3206 writeq(val64, &bar0->mdio_control);
3207 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3208 writeq(val64, &bar0->mdio_control);
3209 udelay(100);
3210
3211}
3212
3213/**
3214 * s2io_mdio_read - Function to write in to MDIO registers
3215 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3216 * @addr : address value
3217 * @dev : pointer to net_device structure
3218 * Description:
3219 * This function is used to read values to the MDIO registers
3220 * NONE
3221 */
3222static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3223{
3224 u64 val64 = 0x0;
3225 u64 rval64 = 0x0;
1ee6dd77
RB		 3226 struct s2io_nic *sp = dev->priv;
3227 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3228
3229 /* address transaction */
3230 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3231 | MDIO_MMD_DEV_ADDR(mmd_type)
3232 | MDIO_MMS_PRT_ADDR(0x0);
3233 writeq(val64, &bar0->mdio_control);
3234 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3235 writeq(val64, &bar0->mdio_control);
3236 udelay(100);
3237
3238 /* Data transaction */
3239 val64 = 0x0;
3240 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3241 | MDIO_MMD_DEV_ADDR(mmd_type)
3242 | MDIO_MMS_PRT_ADDR(0x0)
3243 | MDIO_OP(MDIO_OP_READ_TRANS);
3244 writeq(val64, &bar0->mdio_control);
3245 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3246 writeq(val64, &bar0->mdio_control);
3247 udelay(100);
3248
3249 /* Read the value from regs */
3250 rval64 = readq(&bar0->mdio_control);
3251 rval64 = rval64 & 0xFFFF0000;
3252 rval64 = rval64 >> 16;
3253 return rval64;
3254}
3255/**
3256 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3257 * @counter : couter value to be updated
3258 * @flag : flag to indicate the status
3259 * @type : counter type
3260 * Description:
3261 * This function is to check the status of the xpak counters value
3262 * NONE
3263 */
3264
3265static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3266{
3267 u64 mask = 0x3;
3268 u64 val64;
3269 int i;
3270 for(i = 0; i <index; i++)
3271 mask = mask << 0x2;
3272
3273 if(flag > 0)
3274 {
3275 *counter = *counter + 1;
3276 val64 = *regs_stat & mask;
3277 val64 = val64 >> (index * 0x2);
3278 val64 = val64 + 1;
3279 if(val64 == 3)
3280 {
3281 switch(type)
3282 {
3283 case 1:
3284 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3285 "service. Excessive temperatures may "
3286 "result in premature transceiver "
3287 "failure \n");
3288 break;
3289 case 2:
3290 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3291 "service Excessive bias currents may "
3292 "indicate imminent laser diode "
3293 "failure \n");
3294 break;
3295 case 3:
3296 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3297 "service Excessive laser output "
3298 "power may saturate far-end "
3299 "receiver\n");
3300 break;
3301 default:
3302 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3303 "type \n");
3304 }
3305 val64 = 0x0;
3306 }
3307 val64 = val64 << (index * 0x2);
3308 *regs_stat = (*regs_stat & (~mask)) | (val64);
3309
3310 } else {
3311 *regs_stat = *regs_stat & (~mask);
3312 }
3313}
3314
3315/**
3316 * s2io_updt_xpak_counter - Function to update the xpak counters
3317 * @dev : pointer to net_device struct
3318 * Description:
3319 * This function is to upate the status of the xpak counters value
3320 * NONE
3321 */
3322static void s2io_updt_xpak_counter(struct net_device *dev)
3323{
3324 u16 flag = 0x0;
3325 u16 type = 0x0;
3326 u16 val16 = 0x0;
3327 u64 val64 = 0x0;
3328 u64 addr = 0x0;
3329
1ee6dd77
RB		 3330 struct s2io_nic *sp = dev->priv;
3331 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3332
3333 /* Check the communication with the MDIO slave */
3334 addr = 0x0000;
3335 val64 = 0x0;
3336 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3337 if((val64 == 0xFFFF) || (val64 == 0x0000))
3338 {
3339 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3340 "Returned %llx\n", (unsigned long long)val64);
3341 return;
3342 }
3343
3344 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3345 if(val64 != 0x2040)
3346 {
3347 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3348 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3349 (unsigned long long)val64);
3350 return;
3351 }
3352
3353 /* Loading the DOM register to MDIO register */
3354 addr = 0xA100;
3355 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3356 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3357
3358 /* Reading the Alarm flags */
3359 addr = 0xA070;
3360 val64 = 0x0;
3361 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3362
3363 flag = CHECKBIT(val64, 0x7);
3364 type = 1;
3365 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3366 &stat_info->xpak_stat.xpak_regs_stat,
3367 0x0, flag, type);
3368
3369 if(CHECKBIT(val64, 0x6))
3370 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3371
3372 flag = CHECKBIT(val64, 0x3);
3373 type = 2;
3374 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3375 &stat_info->xpak_stat.xpak_regs_stat,
3376 0x2, flag, type);
3377
3378 if(CHECKBIT(val64, 0x2))
3379 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3380
3381 flag = CHECKBIT(val64, 0x1);
3382 type = 3;
3383 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3384 &stat_info->xpak_stat.xpak_regs_stat,
3385 0x4, flag, type);
3386
3387 if(CHECKBIT(val64, 0x0))
3388 stat_info->xpak_stat.alarm_laser_output_power_low++;
3389
3390 /* Reading the Warning flags */
3391 addr = 0xA074;
3392 val64 = 0x0;
3393 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3394
3395 if(CHECKBIT(val64, 0x7))
3396 stat_info->xpak_stat.warn_transceiver_temp_high++;
3397
3398 if(CHECKBIT(val64, 0x6))
3399 stat_info->xpak_stat.warn_transceiver_temp_low++;
3400
3401 if(CHECKBIT(val64, 0x3))
3402 stat_info->xpak_stat.warn_laser_bias_current_high++;
3403
3404 if(CHECKBIT(val64, 0x2))
3405 stat_info->xpak_stat.warn_laser_bias_current_low++;
3406
3407 if(CHECKBIT(val64, 0x1))
3408 stat_info->xpak_stat.warn_laser_output_power_high++;
3409
3410 if(CHECKBIT(val64, 0x0))
3411 stat_info->xpak_stat.warn_laser_output_power_low++;
3412}
3413
20346722 3414/**
1da177e4 3415 * wait_for_cmd_complete - waits for a command to complete.
20346722 3416 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3417 * s2io_nic structure.
20346722
K		 3418 * Description: Function that waits for a command to Write into RMAC
3419 * ADDR DATA registers to be completed and returns either success or
3420 * error depending on whether the command was complete or not.
1da177e4
LT		 3421 * Return value:
3422 * SUCCESS on success and FAILURE on failure.
3423 */
3424
9fc93a41
SS		 3425static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3426 int bit_state)
1da177e4 3427{
9fc93a41 3428 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3429 u64 val64;
3430
9fc93a41
SS		 3431 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3432 return FAILURE;
3433
3434 do {
c92ca04b 3435 val64 = readq(addr);
9fc93a41
SS		 3436 if (bit_state == S2IO_BIT_RESET) {
3437 if (!(val64 & busy_bit)) {
3438 ret = SUCCESS;
3439 break;
3440 }
3441 } else {
3442 if (!(val64 & busy_bit)) {
3443 ret = SUCCESS;
3444 break;
3445 }
1da177e4 3446 }
c92ca04b
AR		 3447
3448 if(in_interrupt())
9fc93a41 3449 mdelay(delay);
c92ca04b 3450 else
9fc93a41 3451 msleep(delay);
c92ca04b 3452
9fc93a41
SS		 3453 if (++cnt >= 10)
3454 delay = 50;
3455 } while (cnt < 20);
1da177e4
LT		 3456 return ret;
3457}
19a60522
SS		 3458/*
3459 * check_pci_device_id - Checks if the device id is supported
3460 * @id : device id
3461 * Description: Function to check if the pci device id is supported by driver.
3462 * Return value: Actual device id if supported else PCI_ANY_ID
3463 */
3464static u16 check_pci_device_id(u16 id)
3465{
3466 switch (id) {
3467 case PCI_DEVICE_ID_HERC_WIN:
3468 case PCI_DEVICE_ID_HERC_UNI:
3469 return XFRAME_II_DEVICE;
3470 case PCI_DEVICE_ID_S2IO_UNI:
3471 case PCI_DEVICE_ID_S2IO_WIN:
3472 return XFRAME_I_DEVICE;
3473 default:
3474 return PCI_ANY_ID;
3475 }
3476}
1da177e4 3477
20346722
K		 3478/**
3479 * s2io_reset - Resets the card.
1da177e4
LT		 3480 * @sp : private member of the device structure.
3481 * Description: Function to Reset the card. This function then also
20346722 3482 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3483 * the card reset also resets the configuration space.
3484 * Return value:
3485 * void.
3486 */
3487
1ee6dd77 3488static void s2io_reset(struct s2io_nic * sp)
1da177e4 3489{
1ee6dd77 3490 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3491 u64 val64;
5e25b9dd 3492 u16 subid, pci_cmd;
19a60522
SS		 3493 int i;
3494 u16 val16;
491976b2
SH		 3495 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3496 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3497
19a60522
SS		 3498 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3499 __FUNCTION__, sp->dev->name);
1da177e4 3500
0b1f7ebe 3501 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3502 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3503
1da177e4
LT		 3504 val64 = SW_RESET_ALL;
3505 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3506 if (strstr(sp->product_name, "CX4")) {
3507 msleep(750);
3508 }
19a60522
SS		 3509 msleep(250);
3510 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3511
19a60522
SS		 3512 /* Restore the PCI state saved during initialization. */
3513 pci_restore_state(sp->pdev);
3514 pci_read_config_word(sp->pdev, 0x2, &val16);
3515 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3516 break;
3517 msleep(200);
3518 }
1da177e4 3519
19a60522
SS		 3520 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3521 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3522 }
3523
3524 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3525
3526 s2io_init_pci(sp);
1da177e4 3527
20346722
K		 3528 /* Set swapper to enable I/O register access */
3529 s2io_set_swapper(sp);
3530
faa4f796
SH		 3531 /* restore mac_addr entries */
3532 do_s2io_restore_unicast_mc(sp);
3533
cc6e7c44
RA		 3534 /* Restore the MSIX table entries from local variables */
3535 restore_xmsi_data(sp);
3536
5e25b9dd 3537 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3538 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3539 /* Clear "detected parity error" bit */
303bcb4b 3540 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3541
303bcb4b
K		 3542 /* Clearing PCIX Ecc status register */
3543 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3544
303bcb4b 3545 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3546 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3547 }
5e25b9dd 3548
20346722
K		 3549 /* Reset device statistics maintained by OS */
3550 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3551
491976b2
SH		 3552 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3553 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3554 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3555 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3556 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3557 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3558 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3559 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3560 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3561 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3562 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3563 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3564 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3565 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3566 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3567 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3568 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3569 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3570 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3571
1da177e4
LT		 3572 /* SXE-002: Configure link and activity LED to turn it off */
3573 subid = sp->pdev->subsystem_device;
541ae68f
K		 3574 if (((subid & 0xFF) >= 0x07) &&
3575 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3576 val64 = readq(&bar0->gpio_control);
3577 val64 |= 0x0000800000000000ULL;
3578 writeq(val64, &bar0->gpio_control);
3579 val64 = 0x0411040400000000ULL;
509a2671 3580 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3581 }
3582
541ae68f
K		 3583 /*
3584 * Clear spurious ECC interrupts that would have occured on
3585 * XFRAME II cards after reset.
3586 */
3587 if (sp->device_type == XFRAME_II_DEVICE) {
3588 val64 = readq(&bar0->pcc_err_reg);
3589 writeq(val64, &bar0->pcc_err_reg);
3590 }
3591
1da177e4
LT		 3592 sp->device_enabled_once = FALSE;
3593}
3594
3595/**
20346722
K		 3596 * s2io_set_swapper - to set the swapper controle on the card
3597 * @sp : private member of the device structure,
1da177e4 3598 * pointer to the s2io_nic structure.
20346722 3599 * Description: Function to set the swapper control on the card
1da177e4
LT		 3600 * correctly depending on the 'endianness' of the system.
3601 * Return value:
3602 * SUCCESS on success and FAILURE on failure.
3603 */
3604
1ee6dd77 3605static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3606{
3607 struct net_device *dev = sp->dev;
1ee6dd77 3608 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3609 u64 val64, valt, valr;
3610
20346722 3611 /*
1da177e4
LT		 3612 * Set proper endian settings and verify the same by reading
3613 * the PIF Feed-back register.
3614 */
3615
3616 val64 = readq(&bar0->pif_rd_swapper_fb);
3617 if (val64 != 0x0123456789ABCDEFULL) {
3618 int i = 0;
3619 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3620 0x8100008181000081ULL, /* FE=1, SE=0 */
3621 0x4200004242000042ULL, /* FE=0, SE=1 */
3622 0}; /* FE=0, SE=0 */
3623
3624 while(i<4) {
3625 writeq(value[i], &bar0->swapper_ctrl);
3626 val64 = readq(&bar0->pif_rd_swapper_fb);
3627 if (val64 == 0x0123456789ABCDEFULL)
3628 break;
3629 i++;
3630 }
3631 if (i == 4) {
3632 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3633 dev->name);
3634 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3635 (unsigned long long) val64);
3636 return FAILURE;
3637 }
3638 valr = value[i];
3639 } else {
3640 valr = readq(&bar0->swapper_ctrl);
3641 }
3642
3643 valt = 0x0123456789ABCDEFULL;
3644 writeq(valt, &bar0->xmsi_address);
3645 val64 = readq(&bar0->xmsi_address);
3646
3647 if(val64 != valt) {
3648 int i = 0;
3649 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3650 0x0081810000818100ULL, /* FE=1, SE=0 */
3651 0x0042420000424200ULL, /* FE=0, SE=1 */
3652 0}; /* FE=0, SE=0 */
3653
3654 while(i<4) {
3655 writeq((value[i] | valr), &bar0->swapper_ctrl);
3656 writeq(valt, &bar0->xmsi_address);
3657 val64 = readq(&bar0->xmsi_address);
3658 if(val64 == valt)
3659 break;
3660 i++;
3661 }
3662 if(i == 4) {
20346722 3663 unsigned long long x = val64;
1da177e4 3664 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3665 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3666 return FAILURE;
3667 }
3668 }
3669 val64 = readq(&bar0->swapper_ctrl);
3670 val64 &= 0xFFFF000000000000ULL;
3671
3672#ifdef __BIG_ENDIAN
20346722
K		 3673 /*
3674 * The device by default set to a big endian format, so a
1da177e4
LT		 3675 * big endian driver need not set anything.
3676 */
3677 val64 |= (SWAPPER_CTRL_TXP_FE |
3678 SWAPPER_CTRL_TXP_SE |
3679 SWAPPER_CTRL_TXD_R_FE |
3680 SWAPPER_CTRL_TXD_W_FE |
3681 SWAPPER_CTRL_TXF_R_FE |
3682 SWAPPER_CTRL_RXD_R_FE |
3683 SWAPPER_CTRL_RXD_W_FE |
3684 SWAPPER_CTRL_RXF_W_FE |
3685 SWAPPER_CTRL_XMSI_FE |
1da177e4 3686 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3687 if (sp->config.intr_type == INTA)
cc6e7c44 3688 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3689 writeq(val64, &bar0->swapper_ctrl);
3690#else
20346722 3691 /*
1da177e4 3692 * Initially we enable all bits to make it accessible by the
20346722 3693 * driver, then we selectively enable only those bits that
1da177e4
LT		 3694 * we want to set.
3695 */
3696 val64 |= (SWAPPER_CTRL_TXP_FE |
3697 SWAPPER_CTRL_TXP_SE |
3698 SWAPPER_CTRL_TXD_R_FE |
3699 SWAPPER_CTRL_TXD_R_SE |
3700 SWAPPER_CTRL_TXD_W_FE |
3701 SWAPPER_CTRL_TXD_W_SE |
3702 SWAPPER_CTRL_TXF_R_FE |
3703 SWAPPER_CTRL_RXD_R_FE |
3704 SWAPPER_CTRL_RXD_R_SE |
3705 SWAPPER_CTRL_RXD_W_FE |
3706 SWAPPER_CTRL_RXD_W_SE |
3707 SWAPPER_CTRL_RXF_W_FE |
3708 SWAPPER_CTRL_XMSI_FE |
1da177e4 3709 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3710 if (sp->config.intr_type == INTA)
cc6e7c44 3711 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3712 writeq(val64, &bar0->swapper_ctrl);
3713#endif
3714 val64 = readq(&bar0->swapper_ctrl);
3715
20346722
K		 3716 /*
3717 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3718 * feedback register.
3719 */
3720 val64 = readq(&bar0->pif_rd_swapper_fb);
3721 if (val64 != 0x0123456789ABCDEFULL) {
3722 /* Endian settings are incorrect, calls for another dekko. */
3723 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3724 dev->name);
3725 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3726 (unsigned long long) val64);
3727 return FAILURE;
3728 }
3729
3730 return SUCCESS;
3731}
3732
1ee6dd77 3733static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3734{
1ee6dd77 3735 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3736 u64 val64;
3737 int ret = 0, cnt = 0;
3738
3739 do {
3740 val64 = readq(&bar0->xmsi_access);
b7b5a128 3741 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3742 break;
3743 mdelay(1);
3744 cnt++;
3745 } while(cnt < 5);
3746 if (cnt == 5) {
3747 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3748 ret = 1;
3749 }
3750
3751 return ret;
3752}
3753
1ee6dd77 3754static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3755{
1ee6dd77 3756 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3757 u64 val64;
f61e0a35
SH		 3758 int i, msix_index;
3759
3760
3761 if (nic->device_type == XFRAME_I_DEVICE)
3762 return;
cc6e7c44 3763
75c30b13 3764 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35 3765 msix_index = (i) ? ((i-1) * 8 + 1): 0;
cc6e7c44
RA		 3766 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3767 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3768 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3769 writeq(val64, &bar0->xmsi_access);
f61e0a35 3770 if (wait_for_msix_trans(nic, msix_index)) {
cc6e7c44
RA		 3771 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3772 continue;
3773 }
3774 }
3775}
3776
1ee6dd77 3777static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3778{
1ee6dd77 3779 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3780 u64 val64, addr, data;
f61e0a35
SH		 3781 int i, msix_index;
3782
3783 if (nic->device_type == XFRAME_I_DEVICE)
3784 return;
cc6e7c44
RA		 3785
3786 /* Store and display */
75c30b13 3787 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35
SH		 3788 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3789 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3790 writeq(val64, &bar0->xmsi_access);
f61e0a35 3791 if (wait_for_msix_trans(nic, msix_index)) {
cc6e7c44
RA		 3792 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3793 continue;
3794 }
3795 addr = readq(&bar0->xmsi_address);
3796 data = readq(&bar0->xmsi_data);
3797 if (addr && data) {
3798 nic->msix_info[i].addr = addr;
3799 nic->msix_info[i].data = data;
3800 }
3801 }
3802}
3803
1ee6dd77 3804static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3805{
1ee6dd77 3806 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3807 u64 rx_mat;
cc6e7c44
RA		 3808 u16 msi_control; /* Temp variable */
3809 int ret, i, j, msix_indx = 1;
3810
f61e0a35 3811 nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
cc6e7c44 3812 GFP_KERNEL);
bd684e43 3813 if (!nic->entries) {
491976b2
SH		 3814 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3815 __FUNCTION__);
c53d4945 3816 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3817 return -ENOMEM;
3818 }
8a4bdbaa 3819 nic->mac_control.stats_info->sw_stat.mem_allocated
f61e0a35
SH		 3820 += (nic->num_entries * sizeof(struct msix_entry));
3821
3822 memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3823
3824 nic->s2io_entries =
f61e0a35 3825 kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
cc6e7c44 3826 GFP_KERNEL);
bd684e43 3827 if (!nic->s2io_entries) {
8a4bdbaa 3828 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3829 __FUNCTION__);
c53d4945 3830 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3831 kfree(nic->entries);
8a4bdbaa 3832 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3833 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3834 return -ENOMEM;
3835 }
8a4bdbaa 3836 nic->mac_control.stats_info->sw_stat.mem_allocated
f61e0a35
SH		 3837 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3838 memset(nic->s2io_entries, 0,
3839 nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44 3840
ac731ab6
SH		 3841 nic->entries[0].entry = 0;
3842 nic->s2io_entries[0].entry = 0;
3843 nic->s2io_entries[0].in_use = MSIX_FLG;
3844 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3845 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3846
f61e0a35
SH		 3847 for (i = 1; i < nic->num_entries; i++) {
3848 nic->entries[i].entry = ((i - 1) * 8) + 1;
3849 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3850 nic->s2io_entries[i].arg = NULL;
3851 nic->s2io_entries[i].in_use = 0;
3852 }
3853
8a4bdbaa 3854 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3855 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3856 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3857 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3858 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3859 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3860 msix_indx += 8;
cc6e7c44 3861 }
8a4bdbaa 3862 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3863 readq(&bar0->rx_mat);
cc6e7c44 3864
f61e0a35 3865 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3866 /* We fail init if error or we get less vectors than min required */
cc6e7c44
RA		 3867 if (ret) {
3868 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3869 kfree(nic->entries);
8a4bdbaa 3870 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3871 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44 3872 kfree(nic->s2io_entries);
8a4bdbaa 3873 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3874 += (nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3875 nic->entries = NULL;
3876 nic->s2io_entries = NULL;
3877 return -ENOMEM;
3878 }
3879
3880 /*
3881 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3882 * in the herc NIC. (Temp change, needs to be removed later)
3883 */
3884 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3885 msi_control |= 0x1; /* Enable MSI */
3886 pci_write_config_word(nic->pdev, 0x42, msi_control);
3887
3888 return 0;
3889}
3890
8abc4d5b 3891/* Handle software interrupt used during MSI(X) test */
33390a70 3892static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3893{
3894 struct s2io_nic *sp = dev_id;
3895
3896 sp->msi_detected = 1;
3897 wake_up(&sp->msi_wait);
3898
3899 return IRQ_HANDLED;
3900}
3901
3902/* Test interrupt path by forcing a a software IRQ */
33390a70 3903static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3904{
3905 struct pci_dev *pdev = sp->pdev;
3906 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3907 int err;
3908 u64 val64, saved64;
3909
3910 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3911 sp->name, sp);
3912 if (err) {
3913 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3914 sp->dev->name, pci_name(pdev), pdev->irq);
3915 return err;
3916 }
3917
3918 init_waitqueue_head (&sp->msi_wait);
3919 sp->msi_detected = 0;
3920
3921 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3922 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3923 val64 |= SCHED_INT_CTRL_TIMER_EN;
3924 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3925 writeq(val64, &bar0->scheduled_int_ctrl);
3926
3927 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3928
3929 if (!sp->msi_detected) {
3930 /* MSI(X) test failed, go back to INTx mode */
2450022a 3931 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3932 "using MSI(X) during test\n", sp->dev->name,
3933 pci_name(pdev));
3934
3935 err = -EOPNOTSUPP;
3936 }
3937
3938 free_irq(sp->entries[1].vector, sp);
3939
3940 writeq(saved64, &bar0->scheduled_int_ctrl);
3941
3942 return err;
3943}
18b2b7bd
SH		 3944
3945static void remove_msix_isr(struct s2io_nic *sp)
3946{
3947 int i;
3948 u16 msi_control;
3949
f61e0a35 3950 for (i = 0; i < sp->num_entries; i++) {
18b2b7bd
SH		 3951 if (sp->s2io_entries[i].in_use ==
3952 MSIX_REGISTERED_SUCCESS) {
3953 int vector = sp->entries[i].vector;
3954 void *arg = sp->s2io_entries[i].arg;
3955 free_irq(vector, arg);
3956 }
3957 }
3958
3959 kfree(sp->entries);
3960 kfree(sp->s2io_entries);
3961 sp->entries = NULL;
3962 sp->s2io_entries = NULL;
3963
3964 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3965 msi_control &= 0xFFFE; /* Disable MSI */
3966 pci_write_config_word(sp->pdev, 0x42, msi_control);
3967
3968 pci_disable_msix(sp->pdev);
3969}
3970
3971static void remove_inta_isr(struct s2io_nic *sp)
3972{
3973 struct net_device *dev = sp->dev;
3974
3975 free_irq(sp->pdev->irq, dev);
3976}
3977
1da177e4
LT		 3978/* ********************************************************* *
3979 * Functions defined below concern the OS part of the driver *
3980 * ********************************************************* */
3981
20346722 3982/**
1da177e4
LT		 3983 * s2io_open - open entry point of the driver
3984 * @dev : pointer to the device structure.
3985 * Description:
3986 * This function is the open entry point of the driver. It mainly calls a
3987 * function to allocate Rx buffers and inserts them into the buffer
20346722 3988 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3989 * Return value:
3990 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3991 * file on failure.
3992 */
3993
ac1f60db 3994static int s2io_open(struct net_device *dev)
1da177e4 3995{
1ee6dd77 3996 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3997 int err = 0;
3998
20346722
K		 3999 /*
4000 * Make sure you have link off by default every time
1da177e4
LT		 4001 * Nic is initialized
4002 */
4003 netif_carrier_off(dev);
0b1f7ebe 4004 sp->last_link_state = 0;
1da177e4
LT		 4005
4006 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4007 err = s2io_card_up(sp);
4008 if (err) {
1da177e4
LT		 4009 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4010 dev->name);
e6a8fee2 4011 goto hw_init_failed;
1da177e4
LT		 4012 }
4013
2fd37688 4014 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4015 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4016 s2io_card_down(sp);
20346722 4017 err = -ENODEV;
e6a8fee2 4018 goto hw_init_failed;
1da177e4 4019 }
3a3d5756 4020 s2io_start_all_tx_queue(sp);
1da177e4 4021 return 0;
20346722 4022
20346722 4023hw_init_failed:
eaae7f72 4024 if (sp->config.intr_type == MSI_X) {
491976b2 4025 if (sp->entries) {
cc6e7c44 4026 kfree(sp->entries);
8a4bdbaa 4027 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4028 += (sp->num_entries * sizeof(struct msix_entry));
491976b2
SH		 4029 }
4030 if (sp->s2io_entries) {
cc6e7c44 4031 kfree(sp->s2io_entries);
8a4bdbaa 4032 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4033 += (sp->num_entries * sizeof(struct s2io_msix_entry));
491976b2 4034 }
cc6e7c44 4035 }
20346722 4036 return err;
1da177e4
LT		 4037}
4038
4039/**
4040 * s2io_close -close entry point of the driver
4041 * @dev : device pointer.
4042 * Description:
4043 * This is the stop entry point of the driver. It needs to undo exactly
4044 * whatever was done by the open entry point,thus it's usually referred to
4045 * as the close function.Among other things this function mainly stops the
4046 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4047 * Return value:
4048 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4049 * file on failure.
4050 */
4051
ac1f60db 4052static int s2io_close(struct net_device *dev)
1da177e4 4053{
1ee6dd77 4054 struct s2io_nic *sp = dev->priv;
faa4f796
SH		 4055 struct config_param *config = &sp->config;
4056 u64 tmp64;
4057 int offset;
cc6e7c44 4058
9f74ffde
SH		 4059 /* Return if the device is already closed *
4060 * Can happen when s2io_card_up failed in change_mtu *
4061 */
4062 if (!is_s2io_card_up(sp))
4063 return 0;
4064
3a3d5756 4065 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4066 /* delete all populated mac entries */
4067 for (offset = 1; offset < config->max_mc_addr; offset++) {
4068 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4069 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4070 do_s2io_delete_unicast_mc(sp, tmp64);
4071 }
4072
e6a8fee2 4073 s2io_card_down(sp);
cc6e7c44 4074
1da177e4
LT		 4075 return 0;
4076}
4077
4078/**
4079 * s2io_xmit - Tx entry point of te driver
4080 * @skb : the socket buffer containing the Tx data.
4081 * @dev : device pointer.
4082 * Description :
4083 * This function is the Tx entry point of the driver. S2IO NIC supports
4084 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4085 * NOTE: when device cant queue the pkt,just the trans_start variable will
4086 * not be upadted.
4087 * Return value:
4088 * 0 on success & 1 on failure.
4089 */
4090
ac1f60db 4091static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4092{
1ee6dd77 4093 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4094 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4095 register u64 val64;
1ee6dd77
RB		 4096 struct TxD *txdp;
4097 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4098 unsigned long flags = 0;
be3a6b02 4099 u16 vlan_tag = 0;
2fda096d 4100 struct fifo_info *fifo = NULL;
1ee6dd77 4101 struct mac_info *mac_control;
1da177e4 4102 struct config_param *config;
6cfc482b 4103 int do_spin_lock = 1;
75c30b13 4104 int offload_type;
6cfc482b 4105 int enable_per_list_interrupt = 0;
491abf25 4106 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4107
4108 mac_control = &sp->mac_control;
4109 config = &sp->config;
4110
20346722 4111 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4112
4113 if (unlikely(skb->len <= 0)) {
4114 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4115 dev_kfree_skb_any(skb);
4116 return 0;
2fda096d 4117 }
491976b2 4118
92b84437 4119 if (!is_s2io_card_up(sp)) {
20346722 4120 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4121 dev->name);
20346722
K		 4122 dev_kfree_skb(skb);
4123 return 0;
1da177e4
LT		 4124 }
4125
4126 queue = 0;
3a3d5756 4127 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4128 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4129 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4130 if (skb->protocol == htons(ETH_P_IP)) {
4131 struct iphdr *ip;
4132 struct tcphdr *th;
4133 ip = ip_hdr(skb);
4134
4135 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4136 th = (struct tcphdr *)(((unsigned char *)ip) +
4137 ip->ihl*4);
4138
4139 if (ip->protocol == IPPROTO_TCP) {
4140 queue_len = sp->total_tcp_fifos;
4141 queue = (ntohs(th->source) +
4142 ntohs(th->dest)) &
4143 sp->fifo_selector[queue_len - 1];
4144 if (queue >= queue_len)
4145 queue = queue_len - 1;
4146 } else if (ip->protocol == IPPROTO_UDP) {
4147 queue_len = sp->total_udp_fifos;
4148 queue = (ntohs(th->source) +
4149 ntohs(th->dest)) &
4150 sp->fifo_selector[queue_len - 1];
4151 if (queue >= queue_len)
4152 queue = queue_len - 1;
4153 queue += sp->udp_fifo_idx;
4154 if (skb->len > 1024)
4155 enable_per_list_interrupt = 1;
4156 do_spin_lock = 0;
4157 }
4158 }
4159 }
4160 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4161 /* get fifo number based on skb->priority value */
4162 queue = config->fifo_mapping
4163 [skb->priority & (MAX_TX_FIFOS - 1)];
4164 fifo = &mac_control->fifos[queue];
3a3d5756 4165
6cfc482b
SH		 4166 if (do_spin_lock)
4167 spin_lock_irqsave(&fifo->tx_lock, flags);
4168 else {
4169 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4170 return NETDEV_TX_LOCKED;
4171 }
be3a6b02 4172
3a3d5756
SH		 4173 if (sp->config.multiq) {
4174 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4175 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4176 return NETDEV_TX_BUSY;
4177 }
b19fa1fa 4178 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4179 if (netif_queue_stopped(dev)) {
4180 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4181 return NETDEV_TX_BUSY;
4182 }
4183 }
4184
2fda096d
SR		 4185 put_off = (u16) fifo->tx_curr_put_info.offset;
4186 get_off = (u16) fifo->tx_curr_get_info.offset;
4187 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4188
2fda096d 4189 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4190 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4191 if (txdp->Host_Control ||
4192 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4193 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4194 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4195 dev_kfree_skb(skb);
2fda096d 4196 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4197 return 0;
4198 }
0b1f7ebe 4199
75c30b13 4200 offload_type = s2io_offload_type(skb);
75c30b13 4201 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4202 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4203 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4204 }
84fa7933 4205 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4206 txdp->Control_2 |=
4207 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4208 TXD_TX_CKO_UDP_EN);
4209 }
fed5eccd
AR		 4210 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4211 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4212 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4213 if (enable_per_list_interrupt)
4214 if (put_off & (queue_len >> 5))
4215 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4216 if (vlan_tag) {
be3a6b02
K		 4217 txdp->Control_2 |= TXD_VLAN_ENABLE;
4218 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4219 }
4220
fed5eccd 4221 frg_len = skb->len - skb->data_len;
75c30b13 4222 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4223 int ufo_size;
4224
75c30b13 4225 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4226 ufo_size &= ~7;
4227 txdp->Control_1 |= TXD_UFO_EN;
4228 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4229 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4230#ifdef __BIG_ENDIAN
3459feb8 4231 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4232 fifo->ufo_in_band_v[put_off] =
3459feb8 4233 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4234#else
2fda096d 4235 fifo->ufo_in_band_v[put_off] =
3459feb8 4236 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4237#endif
2fda096d 4238 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4239 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4240 fifo->ufo_in_band_v,
fed5eccd 4241 sizeof(u64), PCI_DMA_TODEVICE);
8d8bb39b 4242 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4243 goto pci_map_failed;
fed5eccd 4244 txdp++;
fed5eccd 4245 }
1da177e4 4246
fed5eccd
AR		 4247 txdp->Buffer_Pointer = pci_map_single
4248 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4249 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4250 goto pci_map_failed;
4251
fed5eccd
AR		 4252 txdp->Host_Control = (unsigned long) skb;
4253 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4254 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4255 txdp->Control_1 |= TXD_UFO_EN;
4256
4257 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4258 /* For fragmented SKB. */
4259 for (i = 0; i < frg_cnt; i++) {
4260 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4261 /* A '0' length fragment will be ignored */
4262 if (!frag->size)
4263 continue;
1da177e4
LT		 4264 txdp++;
4265 txdp->Buffer_Pointer = (u64) pci_map_page
4266 (sp->pdev, frag->page, frag->page_offset,
4267 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4268 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4269 if (offload_type == SKB_GSO_UDP)
fed5eccd 4270 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4271 }
4272 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4273
75c30b13 4274 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4275 frg_cnt++; /* as Txd0 was used for inband header */
4276
1da177e4 4277 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4278 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4279 writeq(val64, &tx_fifo->TxDL_Pointer);
4280
4281 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4282 TX_FIFO_LAST_LIST);
75c30b13 4283 if (offload_type)
fed5eccd 4284 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4285
1da177e4
LT		 4286 writeq(val64, &tx_fifo->List_Control);
4287
303bcb4b
K		 4288 mmiowb();
4289
1da177e4 4290 put_off++;
2fda096d 4291 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4292 put_off = 0;
2fda096d 4293 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4294
4295 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4296 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4297 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4298 DBG_PRINT(TX_DBG,
4299 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4300 put_off, get_off);
3a3d5756 4301 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4302 }
491976b2 4303 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4 4304 dev->trans_start = jiffies;
2fda096d 4305 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4306
f6f4bfa3
SH		 4307 if (sp->config.intr_type == MSI_X)
4308 tx_intr_handler(fifo);
4309
491abf25
VP		 4310 return 0;
4311pci_map_failed:
4312 stats->pci_map_fail_cnt++;
3a3d5756 4313 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4314 stats->mem_freed += skb->truesize;
4315 dev_kfree_skb(skb);
2fda096d 4316 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4317 return 0;
4318}
4319
25fff88e
K		 4320static void
4321s2io_alarm_handle(unsigned long data)
4322{
1ee6dd77 4323 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4324 struct net_device *dev = sp->dev;
25fff88e 4325
8116f3cf 4326 s2io_handle_errors(dev);
25fff88e
K		 4327 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4328}
4329
7d12e780 4330static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4331{
1ee6dd77
RB		 4332 struct ring_info *ring = (struct ring_info *)dev_id;
4333 struct s2io_nic *sp = ring->nic;
f61e0a35
SH		 4334 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4335 struct net_device *dev = sp->dev;
cc6e7c44 4336
f61e0a35 4337 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4338 return IRQ_HANDLED;
92b84437 4339
f61e0a35 4340 if (sp->config.napi) {
1a79d1c3
AV		 4341 u8 __iomem *addr = NULL;
4342 u8 val8 = 0;
f61e0a35 4343
1a79d1c3 4344 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4345 addr += (7 - ring->ring_no);
4346 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4347 writeb(val8, addr);
4348 val8 = readb(addr);
4349 netif_rx_schedule(dev, &ring->napi);
4350 } else {
4351 rx_intr_handler(ring, 0);
8d8bb39b 4352 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4353 }
7d3d0439 4354
cc6e7c44
RA		 4355 return IRQ_HANDLED;
4356}
4357
7d12e780 4358static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4359{
ac731ab6
SH		 4360 int i;
4361 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4362 struct s2io_nic *sp = fifos->nic;
4363 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4364 struct config_param *config = &sp->config;
4365 u64 reason;
cc6e7c44 4366
ac731ab6
SH		 4367 if (unlikely(!is_s2io_card_up(sp)))
4368 return IRQ_NONE;
4369
4370 reason = readq(&bar0->general_int_status);
4371 if (unlikely(reason == S2IO_MINUS_ONE))
4372 /* Nothing much can be done. Get out */
92b84437 4373 return IRQ_HANDLED;
92b84437 4374
01e16faa
SH		 4375 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4376 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4377
01e16faa
SH		 4378 if (reason & GEN_INTR_TXPIC)
4379 s2io_txpic_intr_handle(sp);
ac731ab6 4380
01e16faa
SH		 4381 if (reason & GEN_INTR_TXTRAFFIC)
4382 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4383
01e16faa
SH		 4384 for (i = 0; i < config->tx_fifo_num; i++)
4385 tx_intr_handler(&fifos[i]);
ac731ab6 4386
01e16faa
SH		 4387 writeq(sp->general_int_mask, &bar0->general_int_mask);
4388 readl(&bar0->general_int_status);
4389 return IRQ_HANDLED;
4390 }
4391 /* The interrupt was not raised by us */
4392 return IRQ_NONE;
cc6e7c44 4393}
ac731ab6 4394
1ee6dd77 4395static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4396{
1ee6dd77 4397 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4398 u64 val64;
4399
4400 val64 = readq(&bar0->pic_int_status);
4401 if (val64 & PIC_INT_GPIO) {
4402 val64 = readq(&bar0->gpio_int_reg);
4403 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4404 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4405 /*
4406 * This is unstable state so clear both up/down
4407 * interrupt and adapter to re-evaluate the link state.
4408 */
a371a07d
K		 4409 val64 |= GPIO_INT_REG_LINK_DOWN;
4410 val64 |= GPIO_INT_REG_LINK_UP;
4411 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4412 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4413 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4414 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4415 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4416 }
c92ca04b
AR		 4417 else if (val64 & GPIO_INT_REG_LINK_UP) {
4418 val64 = readq(&bar0->adapter_status);
c92ca04b 4419 /* Enable Adapter */
19a60522
SS		 4420 val64 = readq(&bar0->adapter_control);
4421 val64 |= ADAPTER_CNTL_EN;
4422 writeq(val64, &bar0->adapter_control);
4423 val64 |= ADAPTER_LED_ON;
4424 writeq(val64, &bar0->adapter_control);
4425 if (!sp->device_enabled_once)
4426 sp->device_enabled_once = 1;
c92ca04b 4427
19a60522
SS		 4428 s2io_link(sp, LINK_UP);
4429 /*
4430 * unmask link down interrupt and mask link-up
4431 * intr
4432 */
4433 val64 = readq(&bar0->gpio_int_mask);
4434 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4435 val64 |= GPIO_INT_MASK_LINK_UP;
4436 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4437
c92ca04b
AR		 4438 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4439 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4440 s2io_link(sp, LINK_DOWN);
4441 /* Link is down so unmaks link up interrupt */
4442 val64 = readq(&bar0->gpio_int_mask);
4443 val64 &= ~GPIO_INT_MASK_LINK_UP;
4444 val64 |= GPIO_INT_MASK_LINK_DOWN;
4445 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4446
4447 /* turn off LED */
4448 val64 = readq(&bar0->adapter_control);
4449 val64 = val64 &(~ADAPTER_LED_ON);
4450 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4451 }
4452 }
c92ca04b 4453 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4454}
4455
8116f3cf
SS		 4456/**
4457 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4458 * @value: alarm bits
4459 * @addr: address value
4460 * @cnt: counter variable
4461 * Description: Check for alarm and increment the counter
4462 * Return Value:
4463 * 1 - if alarm bit set
4464 * 0 - if alarm bit is not set
4465 */
43b7c451 4466static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4467 unsigned long long *cnt)
4468{
4469 u64 val64;
4470 val64 = readq(addr);
4471 if ( val64 & value ) {
4472 writeq(val64, addr);
4473 (*cnt)++;
4474 return 1;
4475 }
4476 return 0;
4477
4478}
4479
4480/**
4481 * s2io_handle_errors - Xframe error indication handler
4482 * @nic: device private variable
4483 * Description: Handle alarms such as loss of link, single or
4484 * double ECC errors, critical and serious errors.
4485 * Return Value:
4486 * NONE
4487 */
4488static void s2io_handle_errors(void * dev_id)
4489{
4490 struct net_device *dev = (struct net_device *) dev_id;
4491 struct s2io_nic *sp = dev->priv;
4492 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4493 u64 temp64 = 0,val64=0;
4494 int i = 0;
4495
4496 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4497 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4498
92b84437 4499 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4500 return;
4501
4502 if (pci_channel_offline(sp->pdev))
4503 return;
4504
4505 memset(&sw_stat->ring_full_cnt, 0,
4506 sizeof(sw_stat->ring_full_cnt));
4507
4508 /* Handling the XPAK counters update */
4509 if(stats->xpak_timer_count < 72000) {
4510 /* waiting for an hour */
4511 stats->xpak_timer_count++;
4512 } else {
4513 s2io_updt_xpak_counter(dev);
4514 /* reset the count to zero */
4515 stats->xpak_timer_count = 0;
4516 }
4517
4518 /* Handling link status change error Intr */
4519 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4520 val64 = readq(&bar0->mac_rmac_err_reg);
4521 writeq(val64, &bar0->mac_rmac_err_reg);
4522 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4523 schedule_work(&sp->set_link_task);
4524 }
4525
4526 /* In case of a serious error, the device will be Reset. */
4527 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4528 &sw_stat->serious_err_cnt))
4529 goto reset;
4530
4531 /* Check for data parity error */
4532 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4533 &sw_stat->parity_err_cnt))
4534 goto reset;
4535
4536 /* Check for ring full counter */
4537 if (sp->device_type == XFRAME_II_DEVICE) {
4538 val64 = readq(&bar0->ring_bump_counter1);
4539 for (i=0; i<4; i++) {
4540 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4541 temp64 >>= 64 - ((i+1)*16);
4542 sw_stat->ring_full_cnt[i] += temp64;
4543 }
4544
4545 val64 = readq(&bar0->ring_bump_counter2);
4546 for (i=0; i<4; i++) {
4547 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4548 temp64 >>= 64 - ((i+1)*16);
4549 sw_stat->ring_full_cnt[i+4] += temp64;
4550 }
4551 }
4552
4553 val64 = readq(&bar0->txdma_int_status);
4554 /*check for pfc_err*/
4555 if (val64 & TXDMA_PFC_INT) {
4556 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4557 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4558 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4559 &sw_stat->pfc_err_cnt))
4560 goto reset;
4561 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4562 &sw_stat->pfc_err_cnt);
4563 }
4564
4565 /*check for tda_err*/
4566 if (val64 & TXDMA_TDA_INT) {
4567 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4568 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4569 &sw_stat->tda_err_cnt))
4570 goto reset;
4571 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4572 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4573 }
4574 /*check for pcc_err*/
4575 if (val64 & TXDMA_PCC_INT) {
4576 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4577 | PCC_N_SERR | PCC_6_COF_OV_ERR
4578 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4579 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4580 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4581 &sw_stat->pcc_err_cnt))
4582 goto reset;
4583 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4584 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4585 }
4586
4587 /*check for tti_err*/
4588 if (val64 & TXDMA_TTI_INT) {
4589 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4590 &sw_stat->tti_err_cnt))
4591 goto reset;
4592 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4593 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4594 }
4595
4596 /*check for lso_err*/
4597 if (val64 & TXDMA_LSO_INT) {
4598 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4599 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4600 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4601 goto reset;
4602 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4603 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4604 }
4605
4606 /*check for tpa_err*/
4607 if (val64 & TXDMA_TPA_INT) {
4608 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4609 &sw_stat->tpa_err_cnt))
4610 goto reset;
4611 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4612 &sw_stat->tpa_err_cnt);
4613 }
4614
4615 /*check for sm_err*/
4616 if (val64 & TXDMA_SM_INT) {
4617 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4618 &sw_stat->sm_err_cnt))
4619 goto reset;
4620 }
4621
4622 val64 = readq(&bar0->mac_int_status);
4623 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4624 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4625 &bar0->mac_tmac_err_reg,
4626 &sw_stat->mac_tmac_err_cnt))
4627 goto reset;
4628 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4629 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4630 &bar0->mac_tmac_err_reg,
4631 &sw_stat->mac_tmac_err_cnt);
4632 }
4633
4634 val64 = readq(&bar0->xgxs_int_status);
4635 if (val64 & XGXS_INT_STATUS_TXGXS) {
4636 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt))
4639 goto reset;
4640 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4641 &bar0->xgxs_txgxs_err_reg,
4642 &sw_stat->xgxs_txgxs_err_cnt);
4643 }
4644
4645 val64 = readq(&bar0->rxdma_int_status);
4646 if (val64 & RXDMA_INT_RC_INT_M) {
4647 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4648 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4649 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4650 goto reset;
4651 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4652 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653 &sw_stat->rc_err_cnt);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4655 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4656 &sw_stat->prc_pcix_err_cnt))
4657 goto reset;
4658 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4659 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4660 &sw_stat->prc_pcix_err_cnt);
4661 }
4662
4663 if (val64 & RXDMA_INT_RPA_INT_M) {
4664 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4665 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4666 goto reset;
4667 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4668 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4669 }
4670
4671 if (val64 & RXDMA_INT_RDA_INT_M) {
4672 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4673 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4674 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4675 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4676 goto reset;
4677 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4678 | RDA_MISC_ERR | RDA_PCIX_ERR,
4679 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4680 }
4681
4682 if (val64 & RXDMA_INT_RTI_INT_M) {
4683 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4684 &sw_stat->rti_err_cnt))
4685 goto reset;
4686 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4687 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4688 }
4689
4690 val64 = readq(&bar0->mac_int_status);
4691 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4692 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4693 &bar0->mac_rmac_err_reg,
4694 &sw_stat->mac_rmac_err_cnt))
4695 goto reset;
4696 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4697 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4698 &sw_stat->mac_rmac_err_cnt);
4699 }
4700
4701 val64 = readq(&bar0->xgxs_int_status);
4702 if (val64 & XGXS_INT_STATUS_RXGXS) {
4703 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4704 &bar0->xgxs_rxgxs_err_reg,
4705 &sw_stat->xgxs_rxgxs_err_cnt))
4706 goto reset;
4707 }
4708
4709 val64 = readq(&bar0->mc_int_status);
4710 if(val64 & MC_INT_STATUS_MC_INT) {
4711 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4712 &sw_stat->mc_err_cnt))
4713 goto reset;
4714
4715 /* Handling Ecc errors */
4716 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4717 writeq(val64, &bar0->mc_err_reg);
4718 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4719 sw_stat->double_ecc_errs++;
4720 if (sp->device_type != XFRAME_II_DEVICE) {
4721 /*
4722 * Reset XframeI only if critical error
4723 */
4724 if (val64 &
4725 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4726 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4727 goto reset;
4728 }
4729 } else
4730 sw_stat->single_ecc_errs++;
4731 }
4732 }
4733 return;
4734
4735reset:
3a3d5756 4736 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4737 schedule_work(&sp->rst_timer_task);
4738 sw_stat->soft_reset_cnt++;
4739 return;
4740}
4741
1da177e4
LT		 4742/**
4743 * s2io_isr - ISR handler of the device .
4744 * @irq: the irq of the device.
4745 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4746 * Description: This function is the ISR handler of the device. It
4747 * identifies the reason for the interrupt and calls the relevant
4748 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4749 * recv buffers, if their numbers are below the panic value which is
4750 * presently set to 25% of the original number of rcv buffers allocated.
4751 * Return value:
20346722 4752 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4753 * IRQ_NONE: will be returned if interrupt is not from our device
4754 */
7d12e780 4755static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4756{
4757 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4758 struct s2io_nic *sp = dev->priv;
4759 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4760 int i;
19a60522 4761 u64 reason = 0;
1ee6dd77 4762 struct mac_info *mac_control;
1da177e4
LT		 4763 struct config_param *config;
4764
d796fdb7
LV		 4765 /* Pretend we handled any irq's from a disconnected card */
4766 if (pci_channel_offline(sp->pdev))
4767 return IRQ_NONE;
4768
596c5c97 4769 if (!is_s2io_card_up(sp))
92b84437 4770 return IRQ_NONE;
92b84437 4771
1da177e4
LT		 4772 mac_control = &sp->mac_control;
4773 config = &sp->config;
4774
20346722 4775 /*
1da177e4
LT		 4776 * Identify the cause for interrupt and call the appropriate
4777 * interrupt handler. Causes for the interrupt could be;
4778 * 1. Rx of packet.
4779 * 2. Tx complete.
4780 * 3. Link down.
1da177e4
LT		 4781 */
4782 reason = readq(&bar0->general_int_status);
4783
596c5c97
SS		 4784 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4785 /* Nothing much can be done. Get out */
4786 return IRQ_HANDLED;
1da177e4 4787 }
5d3213cc 4788
596c5c97
SS		 4789 if (reason & (GEN_INTR_RXTRAFFIC |
4790 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4791 {
4792 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4793
4794 if (config->napi) {
4795 if (reason & GEN_INTR_RXTRAFFIC) {
f61e0a35
SH		 4796 netif_rx_schedule(dev, &sp->napi);
4797 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4798 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4799 readl(&bar0->rx_traffic_int);
db874e65 4800 }
596c5c97
SS		 4801 } else {
4802 /*
4803 * rx_traffic_int reg is an R1 register, writing all 1's
4804 * will ensure that the actual interrupt causing bit
4805 * get's cleared and hence a read can be avoided.
4806 */
4807 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4808 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4809
4810 for (i = 0; i < config->rx_ring_num; i++)
f61e0a35 4811 rx_intr_handler(&mac_control->rings[i], 0);
db874e65 4812 }
596c5c97 4813
db874e65 4814 /*
596c5c97 4815 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4816 * will ensure that the actual interrupt causing bit get's
4817 * cleared and hence a read can be avoided.
4818 */
596c5c97
SS		 4819 if (reason & GEN_INTR_TXTRAFFIC)
4820 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4821
596c5c97
SS		 4822 for (i = 0; i < config->tx_fifo_num; i++)
4823 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4824
596c5c97
SS		 4825 if (reason & GEN_INTR_TXPIC)
4826 s2io_txpic_intr_handle(sp);
fe113638 4827
596c5c97
SS		 4828 /*
4829 * Reallocate the buffers from the interrupt handler itself.
4830 */
4831 if (!config->napi) {
4832 for (i = 0; i < config->rx_ring_num; i++)
8d8bb39b 4833 s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
596c5c97
SS		 4834 }
4835 writeq(sp->general_int_mask, &bar0->general_int_mask);
4836 readl(&bar0->general_int_status);
20346722 4837
596c5c97 4838 return IRQ_HANDLED;
db874e65 4839
596c5c97
SS		 4840 }
4841 else if (!reason) {
4842 /* The interrupt was not raised by us */
4843 return IRQ_NONE;
4844 }
db874e65 4845
1da177e4
LT		 4846 return IRQ_HANDLED;
4847}
4848
7ba013ac
K		 4849/**
4850 * s2io_updt_stats -
4851 */
1ee6dd77 4852static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4853{
1ee6dd77 4854 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4855 u64 val64;
4856 int cnt = 0;
4857
92b84437 4858 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4859 /* Apprx 30us on a 133 MHz bus */
4860 val64 = SET_UPDT_CLICKS(10) |
4861 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4862 writeq(val64, &bar0->stat_cfg);
4863 do {
4864 udelay(100);
4865 val64 = readq(&bar0->stat_cfg);
b7b5a128 4866 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4867 break;
4868 cnt++;
4869 if (cnt == 5)
4870 break; /* Updt failed */
4871 } while(1);
8a4bdbaa 4872 }
7ba013ac
K		 4873}
4874
1da177e4 4875/**
20346722 4876 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4877 * @dev : pointer to the device structure.
4878 * Description:
20346722 4879 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4880 * structure and returns a pointer to the same.
4881 * Return value:
4882 * pointer to the updated net_device_stats structure.
4883 */
4884
ac1f60db 4885static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4886{
1ee6dd77
RB		 4887 struct s2io_nic *sp = dev->priv;
4888 struct mac_info *mac_control;
1da177e4 4889 struct config_param *config;
0425b46a 4890 int i;
1da177e4 4891
20346722 4892
1da177e4
LT		 4893 mac_control = &sp->mac_control;
4894 config = &sp->config;
4895
7ba013ac
K		 4896 /* Configure Stats for immediate updt */
4897 s2io_updt_stats(sp);
4898
4899 sp->stats.tx_packets =
4900 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4901 sp->stats.tx_errors =
4902 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4903 sp->stats.rx_errors =
ee705dba 4904 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4905 sp->stats.multicast =
4906 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4907 sp->stats.rx_length_errors =
ee705dba 4908 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4909
0425b46a
SH		 4910 /* collect per-ring rx_packets and rx_bytes */
4911 sp->stats.rx_packets = sp->stats.rx_bytes = 0;
4912 for (i = 0; i < config->rx_ring_num; i++) {
4913 sp->stats.rx_packets += mac_control->rings[i].rx_packets;
4914 sp->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4915 }
4916
1da177e4
LT		 4917 return (&sp->stats);
4918}
4919
4920/**
4921 * s2io_set_multicast - entry point for multicast address enable/disable.
4922 * @dev : pointer to the device structure
4923 * Description:
20346722
K		 4924 * This function is a driver entry point which gets called by the kernel
4925 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4926 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4927 * determine, if multicast address must be enabled or if promiscuous mode
4928 * is to be disabled etc.
4929 * Return value:
4930 * void.
4931 */
4932
4933static void s2io_set_multicast(struct net_device *dev)
4934{
4935 int i, j, prev_cnt;
4936 struct dev_mc_list *mclist;
1ee6dd77
RB		 4937 struct s2io_nic *sp = dev->priv;
4938 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4939 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4940 0xfeffffffffffULL;
faa4f796 4941 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4942 void __iomem *add;
faa4f796 4943 struct config_param *config = &sp->config;
1da177e4
LT		 4944
4945 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4946 /* Enable all Multicast addresses */
4947 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4948 &bar0->rmac_addr_data0_mem);
4949 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4950 &bar0->rmac_addr_data1_mem);
4951 val64 = RMAC_ADDR_CMD_MEM_WE |
4952 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4953 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4954 writeq(val64, &bar0->rmac_addr_cmd_mem);
4955 /* Wait till command completes */
c92ca04b 4956 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4957 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4958 S2IO_BIT_RESET);
1da177e4
LT		 4959
4960 sp->m_cast_flg = 1;
faa4f796 4961 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4962 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4963 /* Disable all Multicast addresses */
4964 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4965 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4966 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4967 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4968 val64 = RMAC_ADDR_CMD_MEM_WE |
4969 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4970 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4971 writeq(val64, &bar0->rmac_addr_cmd_mem);
4972 /* Wait till command completes */
c92ca04b 4973 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4974 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4975 S2IO_BIT_RESET);
1da177e4
LT		 4976
4977 sp->m_cast_flg = 0;
4978 sp->all_multi_pos = 0;
4979 }
4980
4981 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4982 /* Put the NIC into promiscuous mode */
4983 add = &bar0->mac_cfg;
4984 val64 = readq(&bar0->mac_cfg);
4985 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4986
4987 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4988 writel((u32) val64, add);
4989 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4990 writel((u32) (val64 >> 32), (add + 4));
4991
926930b2
SS		 4992 if (vlan_tag_strip != 1) {
4993 val64 = readq(&bar0->rx_pa_cfg);
4994 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4995 writeq(val64, &bar0->rx_pa_cfg);
4996 vlan_strip_flag = 0;
4997 }
4998
1da177e4
LT		 4999 val64 = readq(&bar0->mac_cfg);
5000 sp->promisc_flg = 1;
776bd20f 5001 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5002 dev->name);
5003 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5004 /* Remove the NIC from promiscuous mode */
5005 add = &bar0->mac_cfg;
5006 val64 = readq(&bar0->mac_cfg);
5007 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5008
5009 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5010 writel((u32) val64, add);
5011 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5012 writel((u32) (val64 >> 32), (add + 4));
5013
926930b2
SS		 5014 if (vlan_tag_strip != 0) {
5015 val64 = readq(&bar0->rx_pa_cfg);
5016 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5017 writeq(val64, &bar0->rx_pa_cfg);
5018 vlan_strip_flag = 1;
5019 }
5020
1da177e4
LT		 5021 val64 = readq(&bar0->mac_cfg);
5022 sp->promisc_flg = 0;
776bd20f 5023 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5024 dev->name);
5025 }
5026
5027 /* Update individual M_CAST address list */
5028 if ((!sp->m_cast_flg) && dev->mc_count) {
5029 if (dev->mc_count >
faa4f796 5030 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5031 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5032 dev->name);
5033 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5034 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5035 return;
5036 }
5037
5038 prev_cnt = sp->mc_addr_count;
5039 sp->mc_addr_count = dev->mc_count;
5040
5041 /* Clear out the previous list of Mc in the H/W. */
5042 for (i = 0; i < prev_cnt; i++) {
5043 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5044 &bar0->rmac_addr_data0_mem);
5045 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5046 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5047 val64 = RMAC_ADDR_CMD_MEM_WE |
5048 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5049 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5050 (config->mc_start_offset + i);
1da177e4
LT		 5051 writeq(val64, &bar0->rmac_addr_cmd_mem);
5052
5053 /* Wait for command completes */
c92ca04b 5054 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5055 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5056 S2IO_BIT_RESET)) {
1da177e4
LT		 5057 DBG_PRINT(ERR_DBG, "%s: Adding ",
5058 dev->name);
5059 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5060 return;
5061 }
5062 }
5063
5064 /* Create the new Rx filter list and update the same in H/W. */
5065 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5066 i++, mclist = mclist->next) {
5067 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5068 ETH_ALEN);
a7a80d5a 5069 mac_addr = 0;
1da177e4
LT		 5070 for (j = 0; j < ETH_ALEN; j++) {
5071 mac_addr |= mclist->dmi_addr[j];
5072 mac_addr <<= 8;
5073 }
5074 mac_addr >>= 8;
5075 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5076 &bar0->rmac_addr_data0_mem);
5077 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5078 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5079 val64 = RMAC_ADDR_CMD_MEM_WE |
5080 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5081 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5082 (i + config->mc_start_offset);
1da177e4
LT		 5083 writeq(val64, &bar0->rmac_addr_cmd_mem);
5084
5085 /* Wait for command completes */
c92ca04b 5086 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5087 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5088 S2IO_BIT_RESET)) {
1da177e4
LT		 5089 DBG_PRINT(ERR_DBG, "%s: Adding ",
5090 dev->name);
5091 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5092 return;
5093 }
5094 }
5095 }
5096}
5097
faa4f796
SH		 5098/* read from CAM unicast & multicast addresses and store it in
5099 * def_mac_addr structure
5100 */
5101void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5102{
5103 int offset;
5104 u64 mac_addr = 0x0;
5105 struct config_param *config = &sp->config;
5106
5107 /* store unicast & multicast mac addresses */
5108 for (offset = 0; offset < config->max_mc_addr; offset++) {
5109 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5110 /* if read fails disable the entry */
5111 if (mac_addr == FAILURE)
5112 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5113 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5114 }
5115}
5116
5117/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5118static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5119{
5120 int offset;
5121 struct config_param *config = &sp->config;
5122 /* restore unicast mac address */
5123 for (offset = 0; offset < config->max_mac_addr; offset++)
5124 do_s2io_prog_unicast(sp->dev,
5125 sp->def_mac_addr[offset].mac_addr);
5126
5127 /* restore multicast mac address */
5128 for (offset = config->mc_start_offset;
5129 offset < config->max_mc_addr; offset++)
5130 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5131}
5132
5133/* add a multicast MAC address to CAM */
5134static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5135{
5136 int i;
5137 u64 mac_addr = 0;
5138 struct config_param *config = &sp->config;
5139
5140 for (i = 0; i < ETH_ALEN; i++) {
5141 mac_addr <<= 8;
5142 mac_addr |= addr[i];
5143 }
5144 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5145 return SUCCESS;
5146
5147 /* check if the multicast mac already preset in CAM */
5148 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5149 u64 tmp64;
5150 tmp64 = do_s2io_read_unicast_mc(sp, i);
5151 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5152 break;
5153
5154 if (tmp64 == mac_addr)
5155 return SUCCESS;
5156 }
5157 if (i == config->max_mc_addr) {
5158 DBG_PRINT(ERR_DBG,
5159 "CAM full no space left for multicast MAC\n");
5160 return FAILURE;
5161 }
5162 /* Update the internal structure with this new mac address */
5163 do_s2io_copy_mac_addr(sp, i, mac_addr);
5164
5165 return (do_s2io_add_mac(sp, mac_addr, i));
5166}
5167
5168/* add MAC address to CAM */
5169static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5170{
5171 u64 val64;
5172 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5173
5174 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5175 &bar0->rmac_addr_data0_mem);
5176
5177 val64 =
5178 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5179 RMAC_ADDR_CMD_MEM_OFFSET(off);
5180 writeq(val64, &bar0->rmac_addr_cmd_mem);
5181
5182 /* Wait till command completes */
5183 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5184 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5185 S2IO_BIT_RESET)) {
faa4f796 5186 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5187 return FAILURE;
5188 }
5189 return SUCCESS;
5190}
faa4f796
SH		 5191/* deletes a specified unicast/multicast mac entry from CAM */
5192static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5193{
5194 int offset;
5195 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5196 struct config_param *config = &sp->config;
5197
5198 for (offset = 1;
5199 offset < config->max_mc_addr; offset++) {
5200 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5201 if (tmp64 == addr) {
5202 /* disable the entry by writing 0xffffffffffffULL */
5203 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5204 return FAILURE;
5205 /* store the new mac list from CAM */
5206 do_s2io_store_unicast_mc(sp);
5207 return SUCCESS;
5208 }
5209 }
5210 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5211 (unsigned long long)addr);
5212 return FAILURE;
5213}
5214
5215/* read mac entries from CAM */
5216static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5217{
5218 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5219 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5220
5221 /* read mac addr */
5222 val64 =
5223 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5224 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5225 writeq(val64, &bar0->rmac_addr_cmd_mem);
5226
5227 /* Wait till command completes */
5228 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5229 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5230 S2IO_BIT_RESET)) {
5231 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5232 return FAILURE;
5233 }
5234 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5235 return (tmp64 >> 16);
5236}
2fd37688
SS		 5237
5238/**
5239 * s2io_set_mac_addr driver entry point
5240 */
faa4f796 5241
2fd37688
SS		 5242static int s2io_set_mac_addr(struct net_device *dev, void *p)
5243{
5244 struct sockaddr *addr = p;
5245
5246 if (!is_valid_ether_addr(addr->sa_data))
5247 return -EINVAL;
5248
5249 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5250
5251 /* store the MAC address in CAM */
5252 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5253}
1da177e4 5254/**
2fd37688 5255 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5256 * @dev : pointer to the device structure.
5257 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5258 * Description : This procedure will program the Xframe to receive
1da177e4 5259 * frames with new Mac Address
20346722 5260 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5261 * as defined in errno.h file on failure.
5262 */
faa4f796 5263
2fd37688 5264static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5265{
1ee6dd77 5266 struct s2io_nic *sp = dev->priv;
2fd37688 5267 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5268 int i;
faa4f796
SH		 5269 u64 tmp64;
5270 struct config_param *config = &sp->config;
1da177e4 5271
20346722 5272 /*
2fd37688
SS		 5273 * Set the new MAC address as the new unicast filter and reflect this
5274 * change on the device address registered with the OS. It will be
5275 * at offset 0.
5276 */
1da177e4
LT		 5277 for (i = 0; i < ETH_ALEN; i++) {
5278 mac_addr <<= 8;
5279 mac_addr |= addr[i];
2fd37688
SS		 5280 perm_addr <<= 8;
5281 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5282 }
5283
2fd37688
SS		 5284 /* check if the dev_addr is different than perm_addr */
5285 if (mac_addr == perm_addr)
d8d70caf
SS		 5286 return SUCCESS;
5287
faa4f796
SH		 5288 /* check if the mac already preset in CAM */
5289 for (i = 1; i < config->max_mac_addr; i++) {
5290 tmp64 = do_s2io_read_unicast_mc(sp, i);
5291 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5292 break;
5293
5294 if (tmp64 == mac_addr) {
5295 DBG_PRINT(INFO_DBG,
5296 "MAC addr:0x%llx already present in CAM\n",
5297 (unsigned long long)mac_addr);
5298 return SUCCESS;
5299 }
5300 }
5301 if (i == config->max_mac_addr) {
5302 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5303 return FAILURE;
5304 }
d8d70caf 5305 /* Update the internal structure with this new mac address */
faa4f796
SH		 5306 do_s2io_copy_mac_addr(sp, i, mac_addr);
5307 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5308}
5309
5310/**
20346722 5311 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5312 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5313 * @info: pointer to the structure with parameters given by ethtool to set
5314 * link information.
5315 * Description:
20346722 5316 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5317 * the NIC.
5318 * Return value:
5319 * 0 on success.
5320*/
5321
5322static int s2io_ethtool_sset(struct net_device *dev,
5323 struct ethtool_cmd *info)
5324{
1ee6dd77 5325 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5326 if ((info->autoneg == AUTONEG_ENABLE) ||
5327 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5328 return -EINVAL;
5329 else {
5330 s2io_close(sp->dev);
5331 s2io_open(sp->dev);
5332 }
5333
5334 return 0;
5335}
5336
5337/**
20346722 5338 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5339 * @sp : private member of the device structure, pointer to the
5340 * s2io_nic structure.
5341 * @info : pointer to the structure with parameters given by ethtool
5342 * to return link information.
5343 * Description:
5344 * Returns link specific information like speed, duplex etc.. to ethtool.
5345 * Return value :
5346 * return 0 on success.
5347 */
5348
5349static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5350{
1ee6dd77 5351 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5352 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5353 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5354 info->port = PORT_FIBRE;
1a7eb72b
SS		 5355
5356 /* info->transceiver */
5357 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5358
5359 if (netif_carrier_ok(sp->dev)) {
5360 info->speed = 10000;
5361 info->duplex = DUPLEX_FULL;
5362 } else {
5363 info->speed = -1;
5364 info->duplex = -1;
5365 }
5366
5367 info->autoneg = AUTONEG_DISABLE;
5368 return 0;
5369}
5370
5371/**
20346722
K		 5372 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5373 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5374 * s2io_nic structure.
5375 * @info : pointer to the structure with parameters given by ethtool to
5376 * return driver information.
5377 * Description:
5378 * Returns driver specefic information like name, version etc.. to ethtool.
5379 * Return value:
5380 * void
5381 */
5382
5383static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5384 struct ethtool_drvinfo *info)
5385{
1ee6dd77 5386 struct s2io_nic *sp = dev->priv;
1da177e4 5387
dbc2309d
JL		 5388 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5389 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5390 strncpy(info->fw_version, "", sizeof(info->fw_version));
5391 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5392 info->regdump_len = XENA_REG_SPACE;
5393 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5394}
5395
5396/**
5397 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5398 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5399 * s2io_nic structure.
20346722 5400 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5401 * dumping the registers.
5402 * @reg_space: The input argumnet into which all the registers are dumped.
5403 * Description:
5404 * Dumps the entire register space of xFrame NIC into the user given
5405 * buffer area.
5406 * Return value :
5407 * void .
5408*/
5409
5410static void s2io_ethtool_gregs(struct net_device *dev,
5411 struct ethtool_regs *regs, void *space)
5412{
5413 int i;
5414 u64 reg;
5415 u8 *reg_space = (u8 *) space;
1ee6dd77 5416 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5417
5418 regs->len = XENA_REG_SPACE;
5419 regs->version = sp->pdev->subsystem_device;
5420
5421 for (i = 0; i < regs->len; i += 8) {
5422 reg = readq(sp->bar0 + i);
5423 memcpy((reg_space + i), &reg, 8);
5424 }
5425}
5426
5427/**
5428 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5429 * @data : address of the private member of the device structure, which
1da177e4 5430 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5431 * Description: This is actually the timer function that alternates the
5432 * adapter LED bit of the adapter control bit to set/reset every time on
5433 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5434 * once every second.
5435*/
5436static void s2io_phy_id(unsigned long data)
5437{
1ee6dd77
RB		 5438 struct s2io_nic *sp = (struct s2io_nic *) data;
5439 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5440 u64 val64 = 0;
5441 u16 subid;
5442
5443 subid = sp->pdev->subsystem_device;
541ae68f
K		 5444 if ((sp->device_type == XFRAME_II_DEVICE) ||
5445 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5446 val64 = readq(&bar0->gpio_control);
5447 val64 ^= GPIO_CTRL_GPIO_0;
5448 writeq(val64, &bar0->gpio_control);
5449 } else {
5450 val64 = readq(&bar0->adapter_control);
5451 val64 ^= ADAPTER_LED_ON;
5452 writeq(val64, &bar0->adapter_control);
5453 }
5454
5455 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5456}
5457
5458/**
5459 * s2io_ethtool_idnic - To physically identify the nic on the system.
5460 * @sp : private member of the device structure, which is a pointer to the
5461 * s2io_nic structure.
20346722 5462 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5463 * ethtool.
5464 * Description: Used to physically identify the NIC on the system.
20346722 5465 * The Link LED will blink for a time specified by the user for
1da177e4 5466 * identification.
20346722 5467 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5468 * identification is possible only if it's link is up.
5469 * Return value:
5470 * int , returns 0 on success
5471 */
5472
5473static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5474{
5475 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5476 struct s2io_nic *sp = dev->priv;
5477 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5478 u16 subid;
5479
5480 subid = sp->pdev->subsystem_device;
5481 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 5482 if ((sp->device_type == XFRAME_I_DEVICE) &&
5483 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5484 val64 = readq(&bar0->adapter_control);
5485 if (!(val64 & ADAPTER_CNTL_EN)) {
5486 printk(KERN_ERR
5487 "Adapter Link down, cannot blink LED\n");
5488 return -EFAULT;
5489 }
5490 }
5491 if (sp->id_timer.function == NULL) {
5492 init_timer(&sp->id_timer);
5493 sp->id_timer.function = s2io_phy_id;
5494 sp->id_timer.data = (unsigned long) sp;
5495 }
5496 mod_timer(&sp->id_timer, jiffies);
5497 if (data)
20346722 5498 msleep_interruptible(data * HZ);
1da177e4 5499 else
20346722 5500 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5501 del_timer_sync(&sp->id_timer);
5502
541ae68f 5503 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5504 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5505 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5506 }
5507
5508 return 0;
5509}
5510
0cec35eb
SH		 5511static void s2io_ethtool_gringparam(struct net_device *dev,
5512 struct ethtool_ringparam *ering)
5513{
5514 struct s2io_nic *sp = dev->priv;
5515 int i,tx_desc_count=0,rx_desc_count=0;
5516
5517 if (sp->rxd_mode == RXD_MODE_1)
5518 ering->rx_max_pending = MAX_RX_DESC_1;
5519 else if (sp->rxd_mode == RXD_MODE_3B)
5520 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5521
5522 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5523 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5524 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5525
0cec35eb
SH		 5526 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5527 ering->tx_pending = tx_desc_count;
5528 rx_desc_count = 0;
8a4bdbaa 5529 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5530 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5531
0cec35eb
SH		 5532 ering->rx_pending = rx_desc_count;
5533
5534 ering->rx_mini_max_pending = 0;
5535 ering->rx_mini_pending = 0;
5536 if(sp->rxd_mode == RXD_MODE_1)
5537 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5538 else if (sp->rxd_mode == RXD_MODE_3B)
5539 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5540 ering->rx_jumbo_pending = rx_desc_count;
5541}
5542
1da177e4
LT		 5543/**
5544 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5545 * @sp : private member of the device structure, which is a pointer to the
5546 * s2io_nic structure.
1da177e4
LT		 5547 * @ep : pointer to the structure with pause parameters given by ethtool.
5548 * Description:
5549 * Returns the Pause frame generation and reception capability of the NIC.
5550 * Return value:
5551 * void
5552 */
5553static void s2io_ethtool_getpause_data(struct net_device *dev,
5554 struct ethtool_pauseparam *ep)
5555{
5556 u64 val64;
1ee6dd77
RB		 5557 struct s2io_nic *sp = dev->priv;
5558 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5559
5560 val64 = readq(&bar0->rmac_pause_cfg);
5561 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5562 ep->tx_pause = TRUE;
5563 if (val64 & RMAC_PAUSE_RX_ENABLE)
5564 ep->rx_pause = TRUE;
5565 ep->autoneg = FALSE;
5566}
5567
5568/**
5569 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5570 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5571 * s2io_nic structure.
5572 * @ep : pointer to the structure with pause parameters given by ethtool.
5573 * Description:
5574 * It can be used to set or reset Pause frame generation or reception
5575 * support of the NIC.
5576 * Return value:
5577 * int, returns 0 on Success
5578 */
5579
5580static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5581 struct ethtool_pauseparam *ep)
1da177e4
LT		 5582{
5583 u64 val64;
1ee6dd77
RB		 5584 struct s2io_nic *sp = dev->priv;
5585 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5586
5587 val64 = readq(&bar0->rmac_pause_cfg);
5588 if (ep->tx_pause)
5589 val64 |= RMAC_PAUSE_GEN_ENABLE;
5590 else
5591 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5592 if (ep->rx_pause)
5593 val64 |= RMAC_PAUSE_RX_ENABLE;
5594 else
5595 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5596 writeq(val64, &bar0->rmac_pause_cfg);
5597 return 0;
5598}
5599
5600/**
5601 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5602 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5603 * s2io_nic structure.
5604 * @off : offset at which the data must be written
5605 * @data : Its an output parameter where the data read at the given
20346722 5606 * offset is stored.
1da177e4 5607 * Description:
20346722 5608 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5609 * read data.
5610 * NOTE: Will allow to read only part of the EEPROM visible through the
5611 * I2C bus.
5612 * Return value:
5613 * -1 on failure and 0 on success.
5614 */
5615
5616#define S2IO_DEV_ID 5
1ee6dd77 5617static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5618{
5619 int ret = -1;
5620 u32 exit_cnt = 0;
5621 u64 val64;
1ee6dd77 5622 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5623
ad4ebed0 5624 if (sp->device_type == XFRAME_I_DEVICE) {
5625 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5626 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5627 I2C_CONTROL_CNTL_START;
5628 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5629
ad4ebed0 5630 while (exit_cnt < 5) {
5631 val64 = readq(&bar0->i2c_control);
5632 if (I2C_CONTROL_CNTL_END(val64)) {
5633 *data = I2C_CONTROL_GET_DATA(val64);
5634 ret = 0;
5635 break;
5636 }
5637 msleep(50);
5638 exit_cnt++;
1da177e4 5639 }
1da177e4
LT		 5640 }
5641
ad4ebed0 5642 if (sp->device_type == XFRAME_II_DEVICE) {
5643 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5644 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5645 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5646 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5647 val64 |= SPI_CONTROL_REQ;
5648 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5649 while (exit_cnt < 5) {
5650 val64 = readq(&bar0->spi_control);
5651 if (val64 & SPI_CONTROL_NACK) {
5652 ret = 1;
5653 break;
5654 } else if (val64 & SPI_CONTROL_DONE) {
5655 *data = readq(&bar0->spi_data);
5656 *data &= 0xffffff;
5657 ret = 0;
5658 break;
5659 }
5660 msleep(50);
5661 exit_cnt++;
5662 }
5663 }
1da177e4
LT		 5664 return ret;
5665}
5666
5667/**
5668 * write_eeprom - actually writes the relevant part of the data value.
5669 * @sp : private member of the device structure, which is a pointer to the
5670 * s2io_nic structure.
5671 * @off : offset at which the data must be written
5672 * @data : The data that is to be written
20346722 5673 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5674 * the Eeprom. (max of 3)
5675 * Description:
5676 * Actually writes the relevant part of the data value into the Eeprom
5677 * through the I2C bus.
5678 * Return value:
5679 * 0 on success, -1 on failure.
5680 */
5681
1ee6dd77 5682static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5683{
5684 int exit_cnt = 0, ret = -1;
5685 u64 val64;
1ee6dd77 5686 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5687
ad4ebed0 5688 if (sp->device_type == XFRAME_I_DEVICE) {
5689 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5690 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5691 I2C_CONTROL_CNTL_START;
5692 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5693
5694 while (exit_cnt < 5) {
5695 val64 = readq(&bar0->i2c_control);
5696 if (I2C_CONTROL_CNTL_END(val64)) {
5697 if (!(val64 & I2C_CONTROL_NACK))
5698 ret = 0;
5699 break;
5700 }
5701 msleep(50);
5702 exit_cnt++;
5703 }
5704 }
1da177e4 5705
ad4ebed0 5706 if (sp->device_type == XFRAME_II_DEVICE) {
5707 int write_cnt = (cnt == 8) ? 0 : cnt;
5708 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5709
5710 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5711 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5712 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5713 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5714 val64 |= SPI_CONTROL_REQ;
5715 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5716 while (exit_cnt < 5) {
5717 val64 = readq(&bar0->spi_control);
5718 if (val64 & SPI_CONTROL_NACK) {
5719 ret = 1;
5720 break;
5721 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5722 ret = 0;
ad4ebed0 5723 break;
5724 }
5725 msleep(50);
5726 exit_cnt++;
1da177e4 5727 }
1da177e4 5728 }
1da177e4
LT		 5729 return ret;
5730}
1ee6dd77 5731static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5732{
b41477f3
AR		 5733 u8 *vpd_data;
5734 u8 data;
9dc737a7
AR		 5735 int i=0, cnt, fail = 0;
5736 int vpd_addr = 0x80;
5737
5738 if (nic->device_type == XFRAME_II_DEVICE) {
5739 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5740 vpd_addr = 0x80;
5741 }
5742 else {
5743 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5744 vpd_addr = 0x50;
5745 }
19a60522 5746 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5747
b41477f3 5748 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5749 if (!vpd_data) {
5750 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5751 return;
c53d4945 5752 }
491976b2 5753 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5754
9dc737a7
AR		 5755 for (i = 0; i < 256; i +=4 ) {
5756 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5757 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5758 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5759 for (cnt = 0; cnt <5; cnt++) {
5760 msleep(2);
5761 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5762 if (data == 0x80)
5763 break;
5764 }
5765 if (cnt >= 5) {
5766 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5767 fail = 1;
5768 break;
5769 }
5770 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5771 (u32 *)&vpd_data[i]);
5772 }
19a60522
SS		 5773
5774 if(!fail) {
5775 /* read serial number of adapter */
5776 for (cnt = 0; cnt < 256; cnt++) {
5777 if ((vpd_data[cnt] == 'S') &&
5778 (vpd_data[cnt+1] == 'N') &&
5779 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5780 memset(nic->serial_num, 0, VPD_STRING_LEN);
5781 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5782 vpd_data[cnt+2]);
5783 break;
5784 }
5785 }
5786 }
5787
5788 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5789 memset(nic->product_name, 0, vpd_data[1]);
5790 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5791 }
b41477f3 5792 kfree(vpd_data);
491976b2 5793 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5794}
5795
1da177e4
LT		 5796/**
5797 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5798 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5799 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5800 * containing all relevant information.
5801 * @data_buf : user defined value to be written into Eeprom.
5802 * Description: Reads the values stored in the Eeprom at given offset
5803 * for a given length. Stores these values int the input argument data
5804 * buffer 'data_buf' and returns these to the caller (ethtool.)
5805 * Return value:
5806 * int 0 on success
5807 */
5808
5809static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5810 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5811{
ad4ebed0 5812 u32 i, valid;
5813 u64 data;
1ee6dd77 5814 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5815
5816 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5817
5818 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5819 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5820
5821 for (i = 0; i < eeprom->len; i += 4) {
5822 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5823 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5824 return -EFAULT;
5825 }
5826 valid = INV(data);
5827 memcpy((data_buf + i), &valid, 4);
5828 }
5829 return 0;
5830}
5831
5832/**
5833 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5834 * @sp : private member of the device structure, which is a pointer to the
5835 * s2io_nic structure.
20346722 5836 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5837 * containing all relevant information.
5838 * @data_buf ; user defined value to be written into Eeprom.
5839 * Description:
5840 * Tries to write the user provided value in the Eeprom, at the offset
5841 * given by the user.
5842 * Return value:
5843 * 0 on success, -EFAULT on failure.
5844 */
5845
5846static int s2io_ethtool_seeprom(struct net_device *dev,
5847 struct ethtool_eeprom *eeprom,
5848 u8 * data_buf)
5849{
5850 int len = eeprom->len, cnt = 0;
ad4ebed0 5851 u64 valid = 0, data;
1ee6dd77 5852 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5853
5854 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5855 DBG_PRINT(ERR_DBG,
5856 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5857 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5858 eeprom->magic);
5859 return -EFAULT;
5860 }
5861
5862 while (len) {
5863 data = (u32) data_buf[cnt] & 0x000000FF;
5864 if (data) {
5865 valid = (u32) (data << 24);
5866 } else
5867 valid = data;
5868
5869 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5870 DBG_PRINT(ERR_DBG,
5871 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5872 DBG_PRINT(ERR_DBG,
5873 "write into the specified offset\n");
5874 return -EFAULT;
5875 }
5876 cnt++;
5877 len--;
5878 }
5879
5880 return 0;
5881}
5882
5883/**
20346722
K		 5884 * s2io_register_test - reads and writes into all clock domains.
5885 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5886 * s2io_nic structure.
5887 * @data : variable that returns the result of each of the test conducted b
5888 * by the driver.
5889 * Description:
5890 * Read and write into all clock domains. The NIC has 3 clock domains,
5891 * see that registers in all the three regions are accessible.
5892 * Return value:
5893 * 0 on success.
5894 */
5895
1ee6dd77 5896static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5897{
1ee6dd77 5898 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5899 u64 val64 = 0, exp_val;
1da177e4
LT		 5900 int fail = 0;
5901
20346722
K		 5902 val64 = readq(&bar0->pif_rd_swapper_fb);
5903 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5904 fail = 1;
5905 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5906 }
5907
5908 val64 = readq(&bar0->rmac_pause_cfg);
5909 if (val64 != 0xc000ffff00000000ULL) {
5910 fail = 1;
5911 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5912 }
5913
5914 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5915 if (sp->device_type == XFRAME_II_DEVICE)
5916 exp_val = 0x0404040404040404ULL;
5917 else
5918 exp_val = 0x0808080808080808ULL;
5919 if (val64 != exp_val) {
1da177e4
LT		 5920 fail = 1;
5921 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5922 }
5923
5924 val64 = readq(&bar0->xgxs_efifo_cfg);
5925 if (val64 != 0x000000001923141EULL) {
5926 fail = 1;
5927 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5928 }
5929
5930 val64 = 0x5A5A5A5A5A5A5A5AULL;
5931 writeq(val64, &bar0->xmsi_data);
5932 val64 = readq(&bar0->xmsi_data);
5933 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5934 fail = 1;
5935 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5936 }
5937
5938 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5939 writeq(val64, &bar0->xmsi_data);
5940 val64 = readq(&bar0->xmsi_data);
5941 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5942 fail = 1;
5943 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5944 }
5945
5946 *data = fail;
ad4ebed0 5947 return fail;
1da177e4
LT		 5948}
5949
5950/**
20346722 5951 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5952 * @sp : private member of the device structure, which is a pointer to the
5953 * s2io_nic structure.
5954 * @data:variable that returns the result of each of the test conducted by
5955 * the driver.
5956 * Description:
20346722 5957 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5958 * register.
5959 * Return value:
5960 * 0 on success.
5961 */
5962
1ee6dd77 5963static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5964{
5965 int fail = 0;
ad4ebed0 5966 u64 ret_data, org_4F0, org_7F0;
5967 u8 saved_4F0 = 0, saved_7F0 = 0;
5968 struct net_device *dev = sp->dev;
1da177e4
LT		 5969
5970 /* Test Write Error at offset 0 */
ad4ebed0 5971 /* Note that SPI interface allows write access to all areas
5972 * of EEPROM. Hence doing all negative testing only for Xframe I.
5973 */
5974 if (sp->device_type == XFRAME_I_DEVICE)
5975 if (!write_eeprom(sp, 0, 0, 3))
5976 fail = 1;
5977
5978 /* Save current values at offsets 0x4F0 and 0x7F0 */
5979 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5980 saved_4F0 = 1;
5981 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5982 saved_7F0 = 1;
1da177e4
LT		 5983
5984 /* Test Write at offset 4f0 */
ad4ebed0 5985 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5986 fail = 1;
5987 if (read_eeprom(sp, 0x4F0, &ret_data))
5988 fail = 1;
5989
ad4ebed0 5990 if (ret_data != 0x012345) {
26b7625c
AM		 5991 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5992 "Data written %llx Data read %llx\n",
5993 dev->name, (unsigned long long)0x12345,
5994 (unsigned long long)ret_data);
1da177e4 5995 fail = 1;
ad4ebed0 5996 }
1da177e4
LT		 5997
5998 /* Reset the EEPROM data go FFFF */
ad4ebed0 5999 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6000
6001 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6002 if (sp->device_type == XFRAME_I_DEVICE)
6003 if (!write_eeprom(sp, 0x07C, 0, 3))
6004 fail = 1;
1da177e4 6005
ad4ebed0 6006 /* Test Write Request at offset 0x7f0 */
6007 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6008 fail = 1;
ad4ebed0 6009 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6010 fail = 1;
6011
ad4ebed0 6012 if (ret_data != 0x012345) {
26b7625c
AM		 6013 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6014 "Data written %llx Data read %llx\n",
6015 dev->name, (unsigned long long)0x12345,
6016 (unsigned long long)ret_data);
1da177e4 6017 fail = 1;
ad4ebed0 6018 }
1da177e4
LT		 6019
6020 /* Reset the EEPROM data go FFFF */
ad4ebed0 6021 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6022
ad4ebed0 6023 if (sp->device_type == XFRAME_I_DEVICE) {
6024 /* Test Write Error at offset 0x80 */
6025 if (!write_eeprom(sp, 0x080, 0, 3))
6026 fail = 1;
1da177e4 6027
ad4ebed0 6028 /* Test Write Error at offset 0xfc */
6029 if (!write_eeprom(sp, 0x0FC, 0, 3))
6030 fail = 1;
1da177e4 6031
ad4ebed0 6032 /* Test Write Error at offset 0x100 */
6033 if (!write_eeprom(sp, 0x100, 0, 3))
6034 fail = 1;
1da177e4 6035
ad4ebed0 6036 /* Test Write Error at offset 4ec */
6037 if (!write_eeprom(sp, 0x4EC, 0, 3))
6038 fail = 1;
6039 }
6040
6041 /* Restore values at offsets 0x4F0 and 0x7F0 */
6042 if (saved_4F0)
6043 write_eeprom(sp, 0x4F0, org_4F0, 3);
6044 if (saved_7F0)
6045 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6046
6047 *data = fail;
ad4ebed0 6048 return fail;
1da177e4
LT		 6049}
6050
6051/**
6052 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6053 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6054 * s2io_nic structure.
20346722 6055 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6056 * the driver.
6057 * Description:
6058 * This invokes the MemBist test of the card. We give around
6059 * 2 secs time for the Test to complete. If it's still not complete
20346722 6060 * within this peiod, we consider that the test failed.
1da177e4
LT		 6061 * Return value:
6062 * 0 on success and -1 on failure.
6063 */
6064
1ee6dd77 6065static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6066{
6067 u8 bist = 0;
6068 int cnt = 0, ret = -1;
6069
6070 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6071 bist |= PCI_BIST_START;
6072 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6073
6074 while (cnt < 20) {
6075 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6076 if (!(bist & PCI_BIST_START)) {
6077 *data = (bist & PCI_BIST_CODE_MASK);
6078 ret = 0;
6079 break;
6080 }
6081 msleep(100);
6082 cnt++;
6083 }
6084
6085 return ret;
6086}
6087
6088/**
20346722
K		 6089 * s2io-link_test - verifies the link state of the nic
6090 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6091 * s2io_nic structure.
6092 * @data: variable that returns the result of each of the test conducted by
6093 * the driver.
6094 * Description:
20346722 6095 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6096 * argument 'data' appropriately.
6097 * Return value:
6098 * 0 on success.
6099 */
6100
1ee6dd77 6101static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6102{
1ee6dd77 6103 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6104 u64 val64;
6105
6106 val64 = readq(&bar0->adapter_status);
c92ca04b 6107 if(!(LINK_IS_UP(val64)))
1da177e4 6108 *data = 1;
c92ca04b
AR		 6109 else
6110 *data = 0;
1da177e4 6111
b41477f3 6112 return *data;
1da177e4
LT		 6113}
6114
6115/**
20346722
K		 6116 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6117 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6118 * s2io_nic structure.
20346722 6119 * @data - variable that returns the result of each of the test
1da177e4
LT		 6120 * conducted by the driver.
6121 * Description:
20346722 6122 * This is one of the offline test that tests the read and write
1da177e4
LT		 6123 * access to the RldRam chip on the NIC.
6124 * Return value:
6125 * 0 on success.
6126 */
6127
1ee6dd77 6128static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6129{
1ee6dd77 6130 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6131 u64 val64;
ad4ebed0 6132 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6133
6134 val64 = readq(&bar0->adapter_control);
6135 val64 &= ~ADAPTER_ECC_EN;
6136 writeq(val64, &bar0->adapter_control);
6137
6138 val64 = readq(&bar0->mc_rldram_test_ctrl);
6139 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6140 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6141
6142 val64 = readq(&bar0->mc_rldram_mrs);
6143 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6144 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6145
6146 val64 |= MC_RLDRAM_MRS_ENABLE;
6147 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6148
6149 while (iteration < 2) {
6150 val64 = 0x55555555aaaa0000ULL;
6151 if (iteration == 1) {
6152 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6153 }
6154 writeq(val64, &bar0->mc_rldram_test_d0);
6155
6156 val64 = 0xaaaa5a5555550000ULL;
6157 if (iteration == 1) {
6158 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6159 }
6160 writeq(val64, &bar0->mc_rldram_test_d1);
6161
6162 val64 = 0x55aaaaaaaa5a0000ULL;
6163 if (iteration == 1) {
6164 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6165 }
6166 writeq(val64, &bar0->mc_rldram_test_d2);
6167
ad4ebed0 6168 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6169 writeq(val64, &bar0->mc_rldram_test_add);
6170
ad4ebed0 6171 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6172 MC_RLDRAM_TEST_GO;
6173 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6174
6175 for (cnt = 0; cnt < 5; cnt++) {
6176 val64 = readq(&bar0->mc_rldram_test_ctrl);
6177 if (val64 & MC_RLDRAM_TEST_DONE)
6178 break;
6179 msleep(200);
6180 }
6181
6182 if (cnt == 5)
6183 break;
6184
ad4ebed0 6185 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6186 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6187
6188 for (cnt = 0; cnt < 5; cnt++) {
6189 val64 = readq(&bar0->mc_rldram_test_ctrl);
6190 if (val64 & MC_RLDRAM_TEST_DONE)
6191 break;
6192 msleep(500);
6193 }
6194
6195 if (cnt == 5)
6196 break;
6197
6198 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6199 if (!(val64 & MC_RLDRAM_TEST_PASS))
6200 test_fail = 1;
1da177e4
LT		 6201
6202 iteration++;
6203 }
6204
ad4ebed0 6205 *data = test_fail;
1da177e4 6206
ad4ebed0 6207 /* Bring the adapter out of test mode */
6208 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6209
6210 return test_fail;
1da177e4
LT		 6211}
6212
6213/**
6214 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6215 * @sp : private member of the device structure, which is a pointer to the
6216 * s2io_nic structure.
6217 * @ethtest : pointer to a ethtool command specific structure that will be
6218 * returned to the user.
20346722 6219 * @data : variable that returns the result of each of the test
1da177e4
LT		 6220 * conducted by the driver.
6221 * Description:
6222 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6223 * the health of the card.
6224 * Return value:
6225 * void
6226 */
6227
6228static void s2io_ethtool_test(struct net_device *dev,
6229 struct ethtool_test *ethtest,
6230 uint64_t * data)
6231{
1ee6dd77 6232 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6233 int orig_state = netif_running(sp->dev);
6234
6235 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6236 /* Offline Tests. */
20346722 6237 if (orig_state)
1da177e4 6238 s2io_close(sp->dev);
1da177e4
LT		 6239
6240 if (s2io_register_test(sp, &data[0]))
6241 ethtest->flags |= ETH_TEST_FL_FAILED;
6242
6243 s2io_reset(sp);
1da177e4
LT		 6244
6245 if (s2io_rldram_test(sp, &data[3]))
6246 ethtest->flags |= ETH_TEST_FL_FAILED;
6247
6248 s2io_reset(sp);
1da177e4
LT		 6249
6250 if (s2io_eeprom_test(sp, &data[1]))
6251 ethtest->flags |= ETH_TEST_FL_FAILED;
6252
6253 if (s2io_bist_test(sp, &data[4]))
6254 ethtest->flags |= ETH_TEST_FL_FAILED;
6255
6256 if (orig_state)
6257 s2io_open(sp->dev);
6258
6259 data[2] = 0;
6260 } else {
6261 /* Online Tests. */
6262 if (!orig_state) {
6263 DBG_PRINT(ERR_DBG,
6264 "%s: is not up, cannot run test\n",
6265 dev->name);
6266 data[0] = -1;
6267 data[1] = -1;
6268 data[2] = -1;
6269 data[3] = -1;
6270 data[4] = -1;
6271 }
6272
6273 if (s2io_link_test(sp, &data[2]))
6274 ethtest->flags |= ETH_TEST_FL_FAILED;
6275
6276 data[0] = 0;
6277 data[1] = 0;
6278 data[3] = 0;
6279 data[4] = 0;
6280 }
6281}
6282
6283static void s2io_get_ethtool_stats(struct net_device *dev,
6284 struct ethtool_stats *estats,
6285 u64 * tmp_stats)
6286{
8116f3cf 6287 int i = 0, k;
1ee6dd77
RB		 6288 struct s2io_nic *sp = dev->priv;
6289 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6290
7ba013ac 6291 s2io_updt_stats(sp);
541ae68f
K		 6292 tmp_stats[i++] =
6293 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6294 le32_to_cpu(stat_info->tmac_frms);
6295 tmp_stats[i++] =
6296 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6297 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6298 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 6299 tmp_stats[i++] =
6300 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6301 le32_to_cpu(stat_info->tmac_mcst_frms);
6302 tmp_stats[i++] =
6303 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6304 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6305 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6306 tmp_stats[i++] =
6307 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6308 le32_to_cpu(stat_info->tmac_ttl_octets);
6309 tmp_stats[i++] =
6310 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6311 le32_to_cpu(stat_info->tmac_ucst_frms);
6312 tmp_stats[i++] =
6313 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6314 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 6315 tmp_stats[i++] =
6316 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6317 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6318 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6319 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 6320 tmp_stats[i++] =
6321 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6322 le32_to_cpu(stat_info->tmac_vld_ip);
6323 tmp_stats[i++] =
6324 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6325 le32_to_cpu(stat_info->tmac_drop_ip);
6326 tmp_stats[i++] =
6327 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6328 le32_to_cpu(stat_info->tmac_icmp);
6329 tmp_stats[i++] =
6330 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6331 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6332 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 6333 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6334 le32_to_cpu(stat_info->tmac_udp);
6335 tmp_stats[i++] =
6336 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6337 le32_to_cpu(stat_info->rmac_vld_frms);
6338 tmp_stats[i++] =
6339 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6340 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6341 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6342 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 6343 tmp_stats[i++] =
6344 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6345 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6346 tmp_stats[i++] =
6347 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6348 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6349 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6350 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6351 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6352 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6353 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6354 tmp_stats[i++] =
6355 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6356 le32_to_cpu(stat_info->rmac_ttl_octets);
6357 tmp_stats[i++] =
6358 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6359 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6360 tmp_stats[i++] =
6361 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6362 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6363 tmp_stats[i++] =
6364 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6365 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6366 tmp_stats[i++] =
6367 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6368 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6369 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6370 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6371 tmp_stats[i++] =
6372 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6373 le32_to_cpu(stat_info->rmac_usized_frms);
6374 tmp_stats[i++] =
6375 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6376 le32_to_cpu(stat_info->rmac_osized_frms);
6377 tmp_stats[i++] =
6378 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6379 le32_to_cpu(stat_info->rmac_frag_frms);
6380 tmp_stats[i++] =
6381 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6382 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6384 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6386 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6387 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6388 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6389 tmp_stats[i++] =
6390 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6391 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6392 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6393 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6394 tmp_stats[i++] =
6395 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6396 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6397 tmp_stats[i++] =
6398 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6399 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6401 tmp_stats[i++] =
6402 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6403 le32_to_cpu(stat_info->rmac_udp);
6404 tmp_stats[i++] =
6405 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6406 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6407 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6408 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6409 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6410 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6411 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6412 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6413 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6414 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6415 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6416 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6417 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6418 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6419 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6420 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6421 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6422 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6423 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6424 tmp_stats[i++] =
6425 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6426 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6429 tmp_stats[i++] =
6430 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6431 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6432 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6433 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6434 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6435 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6436 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6437 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6438 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6439 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6440 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6441 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6442 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6443 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6444 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6445 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6446 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6447 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6448 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6451
6452 /* Enhanced statistics exist only for Hercules */
6453 if(sp->device_type == XFRAME_II_DEVICE) {
6454 tmp_stats[i++] =
6455 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6456 tmp_stats[i++] =
6457 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6458 tmp_stats[i++] =
6459 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6460 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6461 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6462 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6463 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6464 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6465 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6466 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6467 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6468 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6469 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6470 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6471 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6472 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6473 }
6474
7ba013ac
K		 6475 tmp_stats[i++] = 0;
6476 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6477 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6478 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6479 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6480 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6481 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6482 for (k = 0; k < MAX_RX_RINGS; k++)
6483 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6484 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6485 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6486 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6487 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6488 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6489 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6490 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6491 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6492 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6493 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6494 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6495 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6496 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6497 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6498 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6499 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6500 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6501 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6502 int count = 0;
6aa20a22 6503 /*
bd1034f0
AR		 6504 * Since 64-bit divide does not work on all platforms,
6505 * do repeated subtraction.
6506 */
6507 while (tmp >= stat_info->sw_stat.num_aggregations) {
6508 tmp -= stat_info->sw_stat.num_aggregations;
6509 count++;
6510 }
6511 tmp_stats[i++] = count;
fe931395 6512 }
bd1034f0
AR		 6513 else
6514 tmp_stats[i++] = 0;
c53d4945 6515 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6516 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6517 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6518 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6519 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6520 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6521 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6522 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6523 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6524
6525 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6526 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6527 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6528 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6529 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6530
6531 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6532 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6533 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6534 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6535 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6536 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6537 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6538 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6539 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6540 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6541 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6543 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6544 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6545 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6546 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6547 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6549 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6550 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6551 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6553 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6556 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6557}
6558
ac1f60db 6559static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6560{
6561 return (XENA_REG_SPACE);
6562}
6563
6564
ac1f60db 6565static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6566{
1ee6dd77 6567 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6568
6569 return (sp->rx_csum);
6570}
ac1f60db
AB		 6571
6572static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6573{
1ee6dd77 6574 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6575
6576 if (data)
6577 sp->rx_csum = 1;
6578 else
6579 sp->rx_csum = 0;
6580
6581 return 0;
6582}
ac1f60db
AB		 6583
6584static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6585{
6586 return (XENA_EEPROM_SPACE);
6587}
6588
b9f2c044 6589static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6590{
b9f2c044
JG		 6591 struct s2io_nic *sp = dev->priv;
6592
6593 switch (sset) {
6594 case ETH_SS_TEST:
6595 return S2IO_TEST_LEN;
6596 case ETH_SS_STATS:
6597 switch(sp->device_type) {
6598 case XFRAME_I_DEVICE:
6599 return XFRAME_I_STAT_LEN;
6600 case XFRAME_II_DEVICE:
6601 return XFRAME_II_STAT_LEN;
6602 default:
6603 return 0;
6604 }
6605 default:
6606 return -EOPNOTSUPP;
6607 }
1da177e4 6608}
ac1f60db
AB		 6609
6610static void s2io_ethtool_get_strings(struct net_device *dev,
6611 u32 stringset, u8 * data)
1da177e4 6612{
fa1f0cb3
SS		 6613 int stat_size = 0;
6614 struct s2io_nic *sp = dev->priv;
6615
1da177e4
LT		 6616 switch (stringset) {
6617 case ETH_SS_TEST:
6618 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6619 break;
6620 case ETH_SS_STATS:
fa1f0cb3
SS		 6621 stat_size = sizeof(ethtool_xena_stats_keys);
6622 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6623 if(sp->device_type == XFRAME_II_DEVICE) {
6624 memcpy(data + stat_size,
6625 &ethtool_enhanced_stats_keys,
6626 sizeof(ethtool_enhanced_stats_keys));
6627 stat_size += sizeof(ethtool_enhanced_stats_keys);
6628 }
6629
6630 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6631 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6632 }
6633}
1da177e4 6634
ac1f60db 6635static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6636{
6637 if (data)
6638 dev->features |= NETIF_F_IP_CSUM;
6639 else
6640 dev->features &= ~NETIF_F_IP_CSUM;
6641
6642 return 0;
6643}
6644
75c30b13
AR		 6645static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6646{
6647 return (dev->features & NETIF_F_TSO) != 0;
6648}
6649static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6650{
6651 if (data)
6652 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6653 else
6654 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6655
6656 return 0;
6657}
1da177e4 6658
7282d491 6659static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6660 .get_settings = s2io_ethtool_gset,
6661 .set_settings = s2io_ethtool_sset,
6662 .get_drvinfo = s2io_ethtool_gdrvinfo,
6663 .get_regs_len = s2io_ethtool_get_regs_len,
6664 .get_regs = s2io_ethtool_gregs,
6665 .get_link = ethtool_op_get_link,
6666 .get_eeprom_len = s2io_get_eeprom_len,
6667 .get_eeprom = s2io_ethtool_geeprom,
6668 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6669 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6670 .get_pauseparam = s2io_ethtool_getpause_data,
6671 .set_pauseparam = s2io_ethtool_setpause_data,
6672 .get_rx_csum = s2io_ethtool_get_rx_csum,
6673 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6674 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6675 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6676 .get_tso = s2io_ethtool_op_get_tso,
6677 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6678 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6679 .self_test = s2io_ethtool_test,
6680 .get_strings = s2io_ethtool_get_strings,
6681 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6682 .get_ethtool_stats = s2io_get_ethtool_stats,
6683 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6684};
6685
6686/**
20346722 6687 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6688 * @dev : Device pointer.
6689 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6690 * a proprietary structure used to pass information to the driver.
6691 * @cmd : This is used to distinguish between the different commands that
6692 * can be passed to the IOCTL functions.
6693 * Description:
20346722
K		 6694 * Currently there are no special functionality supported in IOCTL, hence
6695 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6696 */
6697
ac1f60db 6698static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6699{
6700 return -EOPNOTSUPP;
6701}
6702
6703/**
6704 * s2io_change_mtu - entry point to change MTU size for the device.
6705 * @dev : device pointer.
6706 * @new_mtu : the new MTU size for the device.
6707 * Description: A driver entry point to change MTU size for the device.
6708 * Before changing the MTU the device must be stopped.
6709 * Return value:
6710 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6711 * file on failure.
6712 */
6713
ac1f60db 6714static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6715{
1ee6dd77 6716 struct s2io_nic *sp = dev->priv;
9f74ffde 6717 int ret = 0;
1da177e4
LT		 6718
6719 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6720 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6721 dev->name);
6722 return -EPERM;
6723 }
6724
1da177e4 6725 dev->mtu = new_mtu;
d8892c6e 6726 if (netif_running(dev)) {
3a3d5756 6727 s2io_stop_all_tx_queue(sp);
e6a8fee2 6728 s2io_card_down(sp);
9f74ffde
SH		 6729 ret = s2io_card_up(sp);
6730 if (ret) {
d8892c6e
K		 6731 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6732 __FUNCTION__);
9f74ffde 6733 return ret;
d8892c6e 6734 }
3a3d5756 6735 s2io_wake_all_tx_queue(sp);
d8892c6e 6736 } else { /* Device is down */
1ee6dd77 6737 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6738 u64 val64 = new_mtu;
6739
6740 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6741 }
1da177e4 6742
9f74ffde 6743 return ret;
1da177e4
LT		 6744}
6745
1da177e4
LT		 6746/**
6747 * s2io_set_link - Set the LInk status
6748 * @data: long pointer to device private structue
6749 * Description: Sets the link status for the adapter
6750 */
6751
c4028958 6752static void s2io_set_link(struct work_struct *work)
1da177e4 6753{
1ee6dd77 6754 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6755 struct net_device *dev = nic->dev;
1ee6dd77 6756 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6757 register u64 val64;
6758 u16 subid;
6759
22747d6b
FR		 6760 rtnl_lock();
6761
6762 if (!netif_running(dev))
6763 goto out_unlock;
6764
92b84437 6765 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6766 /* The card is being reset, no point doing anything */
22747d6b 6767 goto out_unlock;
1da177e4
LT		 6768 }
6769
6770 subid = nic->pdev->subsystem_device;
a371a07d
K		 6771 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6772 /*
6773 * Allow a small delay for the NICs self initiated
6774 * cleanup to complete.
6775 */
6776 msleep(100);
6777 }
1da177e4
LT		 6778
6779 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6780 if (LINK_IS_UP(val64)) {
6781 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6782 if (verify_xena_quiescence(nic)) {
6783 val64 = readq(&bar0->adapter_control);
6784 val64 |= ADAPTER_CNTL_EN;
1da177e4 6785 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6786 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6787 nic->device_type, subid)) {
6788 val64 = readq(&bar0->gpio_control);
6789 val64 |= GPIO_CTRL_GPIO_0;
6790 writeq(val64, &bar0->gpio_control);
6791 val64 = readq(&bar0->gpio_control);
6792 } else {
6793 val64 |= ADAPTER_LED_ON;
6794 writeq(val64, &bar0->adapter_control);
a371a07d 6795 }
1da177e4 6796 nic->device_enabled_once = TRUE;
19a60522
SS		 6797 } else {
6798 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6799 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6800 s2io_stop_all_tx_queue(nic);
1da177e4 6801 }
19a60522 6802 }
92c48799
SS		 6803 val64 = readq(&bar0->adapter_control);
6804 val64 |= ADAPTER_LED_ON;
6805 writeq(val64, &bar0->adapter_control);
6806 s2io_link(nic, LINK_UP);
19a60522
SS		 6807 } else {
6808 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6809 subid)) {
6810 val64 = readq(&bar0->gpio_control);
6811 val64 &= ~GPIO_CTRL_GPIO_0;
6812 writeq(val64, &bar0->gpio_control);
6813 val64 = readq(&bar0->gpio_control);
1da177e4 6814 }
92c48799
SS		 6815 /* turn off LED */
6816 val64 = readq(&bar0->adapter_control);
6817 val64 = val64 &(~ADAPTER_LED_ON);
6818 writeq(val64, &bar0->adapter_control);
19a60522 6819 s2io_link(nic, LINK_DOWN);
1da177e4 6820 }
92b84437 6821 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6822
6823out_unlock:
d8d70caf 6824 rtnl_unlock();
1da177e4
LT		 6825}
6826
1ee6dd77
RB		 6827static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6828 struct buffAdd *ba,
6829 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6830 u64 *temp2, int size)
5d3213cc
AR		 6831{
6832 struct net_device *dev = sp->dev;
491abf25 6833 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6834
6835 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6836 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6837 /* allocate skb */
6838 if (*skb) {
6839 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6840 /*
6841 * As Rx frame are not going to be processed,
6842 * using same mapped address for the Rxd
6843 * buffer pointer
6844 */
6d517a27 6845 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6846 } else {
6847 *skb = dev_alloc_skb(size);
6848 if (!(*skb)) {
0c61ed5f 6849 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6850 DBG_PRINT(INFO_DBG, "memory to allocate ");
6851 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6852 sp->mac_control.stats_info->sw_stat. \
6853 mem_alloc_fail_cnt++;
5d3213cc
AR		 6854 return -ENOMEM ;
6855 }
8a4bdbaa 6856 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6857 += (*skb)->truesize;
5d3213cc
AR		 6858 /* storing the mapped addr in a temp variable
6859 * such it will be used for next rxd whose
6860 * Host Control is NULL
6861 */
6d517a27 6862 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6863 pci_map_single( sp->pdev, (*skb)->data,
6864 size - NET_IP_ALIGN,
6865 PCI_DMA_FROMDEVICE);
8d8bb39b 6866 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6867 goto memalloc_failed;
5d3213cc
AR		 6868 rxdp->Host_Control = (unsigned long) (*skb);
6869 }
6870 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6871 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6872 /* Two buffer Mode */
6873 if (*skb) {
6d517a27
VP		 6874 rxdp3->Buffer2_ptr = *temp2;
6875 rxdp3->Buffer0_ptr = *temp0;
6876 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6877 } else {
6878 *skb = dev_alloc_skb(size);
2ceaac75 6879 if (!(*skb)) {
c53d4945
SH		 6880 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6881 DBG_PRINT(INFO_DBG, "memory to allocate ");
6882 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6883 sp->mac_control.stats_info->sw_stat. \
6884 mem_alloc_fail_cnt++;
2ceaac75
DR		 6885 return -ENOMEM;
6886 }
8a4bdbaa 6887 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6888 += (*skb)->truesize;
6d517a27 6889 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6890 pci_map_single(sp->pdev, (*skb)->data,
6891 dev->mtu + 4,
6892 PCI_DMA_FROMDEVICE);
8d8bb39b 6893 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6894 goto memalloc_failed;
6d517a27 6895 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6896 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6897 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6898 if (pci_dma_mapping_error(sp->pdev,
6899 rxdp3->Buffer0_ptr)) {
491abf25 6900 pci_unmap_single (sp->pdev,
3e847423 6901 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6902 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6903 goto memalloc_failed;
6904 }
5d3213cc
AR		 6905 rxdp->Host_Control = (unsigned long) (*skb);
6906
6907 /* Buffer-1 will be dummy buffer not used */
6d517a27 6908 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6909 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6910 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6911 if (pci_dma_mapping_error(sp->pdev,
6912 rxdp3->Buffer1_ptr)) {
491abf25 6913 pci_unmap_single (sp->pdev,
3e847423
AV		 6914 (dma_addr_t)rxdp3->Buffer0_ptr,
6915 BUF0_LEN, PCI_DMA_FROMDEVICE);
6916 pci_unmap_single (sp->pdev,
6917 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6918 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6919 goto memalloc_failed;
6920 }
5d3213cc
AR		 6921 }
6922 }
6923 return 0;
491abf25
VP		 6924 memalloc_failed:
6925 stats->pci_map_fail_cnt++;
6926 stats->mem_freed += (*skb)->truesize;
6927 dev_kfree_skb(*skb);
6928 return -ENOMEM;
5d3213cc 6929}
491abf25 6930
1ee6dd77
RB		 6931static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6932 int size)
5d3213cc
AR		 6933{
6934 struct net_device *dev = sp->dev;
6935 if (sp->rxd_mode == RXD_MODE_1) {
6936 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6937 } else if (sp->rxd_mode == RXD_MODE_3B) {
6938 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6939 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6940 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6941 }
6942}
6943
1ee6dd77 6944static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6945{
6946 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6947 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6948 struct config_param *config = &sp->config;
6949 struct net_device *dev = sp->dev;
1ee6dd77 6950 struct RxD_t *rxdp = NULL;
5d3213cc 6951 struct sk_buff *skb = NULL;
1ee6dd77 6952 struct buffAdd *ba = NULL;
5d3213cc
AR		 6953 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6954
6955 /* Calculate the size based on ring mode */
6956 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6957 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6958 if (sp->rxd_mode == RXD_MODE_1)
6959 size += NET_IP_ALIGN;
6960 else if (sp->rxd_mode == RXD_MODE_3B)
6961 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6962
6963 for (i = 0; i < config->rx_ring_num; i++) {
6964 blk_cnt = config->rx_cfg[i].num_rxd /
6965 (rxd_count[sp->rxd_mode] +1);
6966
6967 for (j = 0; j < blk_cnt; j++) {
6968 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6969 rxdp = mac_control->rings[i].
6970 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6971 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6972 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6973 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6974 &skb,(u64 *)&temp0_64,
6975 (u64 *)&temp1_64,
ac1f90d6 6976 (u64 *)&temp2_64,
20cbe73c 6977 size) == -ENOMEM) {
ac1f90d6
SS		 6978 return 0;
6979 }
5d3213cc
AR		 6980
6981 set_rxd_buffer_size(sp, rxdp, size);
6982 wmb();
6983 /* flip the Ownership bit to Hardware */
6984 rxdp->Control_1 |= RXD_OWN_XENA;
6985 }
6986 }
6987 }
6988 return 0;
6989
6990}
6991
1ee6dd77 6992static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6993{
e6a8fee2 6994 int ret = 0;
c92ca04b 6995 struct net_device *dev = sp->dev;
e6a8fee2 6996 int err = 0;
1da177e4 6997
eaae7f72 6998 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6999 ret = s2io_enable_msi_x(sp);
7000 if (ret) {
7001 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7002 sp->config.intr_type = INTA;
20346722 7003 }
1da177e4 7004
1ee6dd77 7005 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 7006 store_xmsi_data(sp);
c92ca04b 7007
e6a8fee2 7008 /* After proper initialization of H/W, register ISR */
eaae7f72 7009 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7010 int i, msix_rx_cnt = 0;
7011
f61e0a35
SH		 7012 for (i = 0; i < sp->num_entries; i++) {
7013 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7014 if (sp->s2io_entries[i].type ==
ac731ab6
SH		 7015 MSIX_RING_TYPE) {
7016 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7017 dev->name, i);
7018 err = request_irq(sp->entries[i].vector,
7019 s2io_msix_ring_handle, 0,
7020 sp->desc[i],
7021 sp->s2io_entries[i].arg);
7022 } else if (sp->s2io_entries[i].type ==
7023 MSIX_ALARM_TYPE) {
7024 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
e6a8fee2 7025 dev->name, i);
ac731ab6
SH		 7026 err = request_irq(sp->entries[i].vector,
7027 s2io_msix_fifo_handle, 0,
7028 sp->desc[i],
7029 sp->s2io_entries[i].arg);
7030
fb6a825b 7031 }
ac731ab6
SH		 7032 /* if either data or addr is zero print it. */
7033 if (!(sp->msix_info[i].addr &&
fb6a825b 7034 sp->msix_info[i].data)) {
ac731ab6
SH		 7035 DBG_PRINT(ERR_DBG,
7036 "%s @Addr:0x%llx Data:0x%llx\n",
7037 sp->desc[i],
fb6a825b
SS		 7038 (unsigned long long)
7039 sp->msix_info[i].addr,
3459feb8 7040 (unsigned long long)
ac731ab6
SH		 7041 ntohl(sp->msix_info[i].data));
7042 } else
fb6a825b 7043 msix_rx_cnt++;
ac731ab6
SH		 7044 if (err) {
7045 remove_msix_isr(sp);
7046
7047 DBG_PRINT(ERR_DBG,
7048 "%s:MSI-X-%d registration "
7049 "failed\n", dev->name, i);
7050
7051 DBG_PRINT(ERR_DBG,
7052 "%s: Defaulting to INTA\n",
7053 dev->name);
7054 sp->config.intr_type = INTA;
7055 break;
fb6a825b 7056 }
ac731ab6
SH		 7057 sp->s2io_entries[i].in_use =
7058 MSIX_REGISTERED_SUCCESS;
c92ca04b 7059 }
e6a8fee2 7060 }
18b2b7bd 7061 if (!err) {
18b2b7bd 7062 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
ac731ab6
SH		 7063 --msix_rx_cnt);
7064 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7065 " through alarm vector\n");
18b2b7bd 7066 }
e6a8fee2 7067 }
eaae7f72 7068 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7069 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7070 sp->name, dev);
7071 if (err) {
7072 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7073 dev->name);
7074 return -1;
7075 }
7076 }
7077 return 0;
7078}
1ee6dd77 7079static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7080{
18b2b7bd
SH		 7081 if (sp->config.intr_type == MSI_X)
7082 remove_msix_isr(sp);
7083 else
7084 remove_inta_isr(sp);
e6a8fee2
AR		 7085}
7086
d796fdb7 7087static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7088{
7089 int cnt = 0;
1ee6dd77 7090 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7091 register u64 val64 = 0;
5f490c96
SH		 7092 struct config_param *config;
7093 config = &sp->config;
e6a8fee2 7094
9f74ffde
SH		 7095 if (!is_s2io_card_up(sp))
7096 return;
7097
e6a8fee2
AR		 7098 del_timer_sync(&sp->alarm_timer);
7099 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7100 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7101 msleep(50);
7102 }
92b84437 7103 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7104
5f490c96 7105 /* Disable napi */
f61e0a35
SH		 7106 if (sp->config.napi) {
7107 int off = 0;
7108 if (config->intr_type == MSI_X) {
7109 for (; off < sp->config.rx_ring_num; off++)
7110 napi_disable(&sp->mac_control.rings[off].napi);
7111 }
7112 else
7113 napi_disable(&sp->napi);
7114 }
5f490c96 7115
e6a8fee2 7116 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7117 if (do_io)
7118 stop_nic(sp);
e6a8fee2
AR		 7119
7120 s2io_rem_isr(sp);
1da177e4 7121
01e16faa
SH		 7122 /* stop the tx queue, indicate link down */
7123 s2io_link(sp, LINK_DOWN);
7124
1da177e4 7125 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7126 while(do_io) {
5d3213cc
AR		 7127 /* As per the HW requirement we need to replenish the
7128 * receive buffer to avoid the ring bump. Since there is
7129 * no intention of processing the Rx frame at this pointwe are
7130 * just settting the ownership bit of rxd in Each Rx
7131 * ring to HW and set the appropriate buffer size
7132 * based on the ring mode
7133 */
7134 rxd_owner_bit_reset(sp);
7135
1da177e4 7136 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7137 if (verify_xena_quiescence(sp)) {
7138 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7139 break;
7140 }
7141
7142 msleep(50);
7143 cnt++;
7144 if (cnt == 10) {
7145 DBG_PRINT(ERR_DBG,
7146 "s2io_close:Device not Quiescent ");
7147 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7148 (unsigned long long) val64);
7149 break;
7150 }
d796fdb7
LV		 7151 }
7152 if (do_io)
7153 s2io_reset(sp);
1da177e4 7154
7ba013ac 7155 /* Free all Tx buffers */
1da177e4 7156 free_tx_buffers(sp);
7ba013ac
K		 7157
7158 /* Free all Rx buffers */
1da177e4
LT		 7159 free_rx_buffers(sp);
7160
92b84437 7161 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7162}
7163
d796fdb7
LV		 7164static void s2io_card_down(struct s2io_nic * sp)
7165{
7166 do_s2io_card_down(sp, 1);
7167}
7168
1ee6dd77 7169static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7170{
cc6e7c44 7171 int i, ret = 0;
1ee6dd77 7172 struct mac_info *mac_control;
1da177e4
LT		 7173 struct config_param *config;
7174 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7175 u16 interruptible;
1da177e4
LT		 7176
7177 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7178 ret = init_nic(sp);
7179 if (ret != 0) {
1da177e4
LT		 7180 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7181 dev->name);
9f74ffde
SH		 7182 if (ret != -EIO)
7183 s2io_reset(sp);
7184 return ret;
1da177e4
LT		 7185 }
7186
20346722
K		 7187 /*
7188 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7189 * Rx ring and initializing buffers into 30 Rx blocks
7190 */
7191 mac_control = &sp->mac_control;
7192 config = &sp->config;
7193
7194 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a 7195 mac_control->rings[i].mtu = dev->mtu;
8d8bb39b 7196 ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
0425b46a 7197 if (ret) {
1da177e4
LT		 7198 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7199 dev->name);
7200 s2io_reset(sp);
7201 free_rx_buffers(sp);
7202 return -ENOMEM;
7203 }
7204 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
0425b46a 7205 mac_control->rings[i].rx_bufs_left);
1da177e4 7206 }
5f490c96
SH		 7207
7208 /* Initialise napi */
f61e0a35
SH		 7209 if (config->napi) {
7210 int i;
7211 if (config->intr_type == MSI_X) {
7212 for (i = 0; i < sp->config.rx_ring_num; i++)
7213 napi_enable(&sp->mac_control.rings[i].napi);
7214 } else {
7215 napi_enable(&sp->napi);
7216 }
7217 }
5f490c96 7218
19a60522
SS		 7219 /* Maintain the state prior to the open */
7220 if (sp->promisc_flg)
7221 sp->promisc_flg = 0;
7222 if (sp->m_cast_flg) {
7223 sp->m_cast_flg = 0;
7224 sp->all_multi_pos= 0;
7225 }
1da177e4
LT		 7226
7227 /* Setting its receive mode */
7228 s2io_set_multicast(dev);
7229
7d3d0439 7230 if (sp->lro) {
b41477f3 7231 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7232 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7233 /* Check if we can use(if specified) user provided value */
7234 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7235 sp->lro_max_aggr_per_sess = lro_max_pkts;
7236 }
7237
1da177e4
LT		 7238 /* Enable Rx Traffic and interrupts on the NIC */
7239 if (start_nic(sp)) {
7240 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7241 s2io_reset(sp);
e6a8fee2
AR		 7242 free_rx_buffers(sp);
7243 return -ENODEV;
7244 }
7245
7246 /* Add interrupt service routine */
7247 if (s2io_add_isr(sp) != 0) {
eaae7f72 7248 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7249 s2io_rem_isr(sp);
7250 s2io_reset(sp);
1da177e4
LT		 7251 free_rx_buffers(sp);
7252 return -ENODEV;
7253 }
7254
25fff88e
K		 7255 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7256
01e16faa
SH		 7257 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7258
e6a8fee2 7259 /* Enable select interrupts */
9caab458 7260 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7261 if (sp->config.intr_type != INTA) {
7262 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7263 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7264 } else {
e6a8fee2 7265 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7266 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7267 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7268 }
7269
1da177e4
LT		 7270 return 0;
7271}
7272
20346722 7273/**
1da177e4
LT		 7274 * s2io_restart_nic - Resets the NIC.
7275 * @data : long pointer to the device private structure
7276 * Description:
7277 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7278 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7279 * the run time of the watch dog routine which is run holding a
7280 * spin lock.
7281 */
7282
c4028958 7283static void s2io_restart_nic(struct work_struct *work)
1da177e4 7284{
1ee6dd77 7285 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7286 struct net_device *dev = sp->dev;
1da177e4 7287
22747d6b
FR		 7288 rtnl_lock();
7289
7290 if (!netif_running(dev))
7291 goto out_unlock;
7292
e6a8fee2 7293 s2io_card_down(sp);
1da177e4
LT		 7294 if (s2io_card_up(sp)) {
7295 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7296 dev->name);
7297 }
3a3d5756 7298 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7299 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7300 dev->name);
22747d6b
FR		 7301out_unlock:
7302 rtnl_unlock();
1da177e4
LT		 7303}
7304
20346722
K		 7305/**
7306 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7307 * @dev : Pointer to net device structure
7308 * Description:
7309 * This function is triggered if the Tx Queue is stopped
7310 * for a pre-defined amount of time when the Interface is still up.
7311 * If the Interface is jammed in such a situation, the hardware is
7312 * reset (by s2io_close) and restarted again (by s2io_open) to
7313 * overcome any problem that might have been caused in the hardware.
7314 * Return value:
7315 * void
7316 */
7317
7318static void s2io_tx_watchdog(struct net_device *dev)
7319{
1ee6dd77 7320 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 7321
7322 if (netif_carrier_ok(dev)) {
c53d4945 7323 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7324 schedule_work(&sp->rst_timer_task);
bd1034f0 7325 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7326 }
7327}
7328
7329/**
7330 * rx_osm_handler - To perform some OS related operations on SKB.
7331 * @sp: private member of the device structure,pointer to s2io_nic structure.
7332 * @skb : the socket buffer pointer.
7333 * @len : length of the packet
7334 * @cksum : FCS checksum of the frame.
7335 * @ring_no : the ring from which this RxD was extracted.
20346722 7336 * Description:
b41477f3 7337 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7338 * some OS related operations on the SKB before passing it to the upper
7339 * layers. It mainly checks if the checksum is OK, if so adds it to the
7340 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7341 * to the upper layer. If the checksum is wrong, it increments the Rx
7342 * packet error count, frees the SKB and returns error.
7343 * Return value:
7344 * SUCCESS on success and -1 on failure.
7345 */
1ee6dd77 7346static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7347{
1ee6dd77 7348 struct s2io_nic *sp = ring_data->nic;
0425b46a 7349 struct net_device *dev = (struct net_device *) ring_data->dev;
20346722
K		 7350 struct sk_buff *skb = (struct sk_buff *)
7351 ((unsigned long) rxdp->Host_Control);
7352 int ring_no = ring_data->ring_no;
1da177e4 7353 u16 l3_csum, l4_csum;
863c11a9 7354 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7355 struct lro *lro;
f9046eb3 7356 u8 err_mask;
da6971d8 7357
20346722 7358 skb->dev = dev;
c92ca04b 7359
863c11a9 7360 if (err) {
bd1034f0
AR		 7361 /* Check for parity error */
7362 if (err & 0x1) {
7363 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7364 }
f9046eb3
OH		 7365 err_mask = err >> 48;
7366 switch(err_mask) {
491976b2
SH		 7367 case 1:
7368 sp->mac_control.stats_info->sw_stat.
7369 rx_parity_err_cnt++;
7370 break;
7371
7372 case 2:
7373 sp->mac_control.stats_info->sw_stat.
7374 rx_abort_cnt++;
7375 break;
7376
7377 case 3:
7378 sp->mac_control.stats_info->sw_stat.
7379 rx_parity_abort_cnt++;
7380 break;
7381
7382 case 4:
7383 sp->mac_control.stats_info->sw_stat.
7384 rx_rda_fail_cnt++;
7385 break;
7386
7387 case 5:
7388 sp->mac_control.stats_info->sw_stat.
7389 rx_unkn_prot_cnt++;
7390 break;
7391
7392 case 6:
7393 sp->mac_control.stats_info->sw_stat.
7394 rx_fcs_err_cnt++;
7395 break;
bd1034f0 7396
491976b2
SH		 7397 case 7:
7398 sp->mac_control.stats_info->sw_stat.
7399 rx_buf_size_err_cnt++;
7400 break;
7401
7402 case 8:
7403 sp->mac_control.stats_info->sw_stat.
7404 rx_rxd_corrupt_cnt++;
7405 break;
7406
7407 case 15:
7408 sp->mac_control.stats_info->sw_stat.
7409 rx_unkn_err_cnt++;
7410 break;
7411 }
863c11a9
AR		 7412 /*
7413 * Drop the packet if bad transfer code. Exception being
7414 * 0x5, which could be due to unsupported IPv6 extension header.
7415 * In this case, we let stack handle the packet.
7416 * Note that in this case, since checksum will be incorrect,
7417 * stack will validate the same.
7418 */
f9046eb3
OH		 7419 if (err_mask != 0x5) {
7420 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7421 dev->name, err_mask);
863c11a9 7422 sp->stats.rx_crc_errors++;
8a4bdbaa 7423 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7424 += skb->truesize;
863c11a9 7425 dev_kfree_skb(skb);
0425b46a 7426 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7427 rxdp->Host_Control = 0;
7428 return 0;
7429 }
20346722 7430 }
1da177e4 7431
20346722 7432 /* Updating statistics */
0425b46a 7433 ring_data->rx_packets++;
20346722 7434 rxdp->Host_Control = 0;
da6971d8
AR		 7435 if (sp->rxd_mode == RXD_MODE_1) {
7436 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7437
0425b46a 7438 ring_data->rx_bytes += len;
da6971d8
AR		 7439 skb_put(skb, len);
7440
6d517a27 7441 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7442 int get_block = ring_data->rx_curr_get_info.block_index;
7443 int get_off = ring_data->rx_curr_get_info.offset;
7444 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7445 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7446 unsigned char *buff = skb_push(skb, buf0_len);
7447
1ee6dd77 7448 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7449 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7450 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7451 skb_put(skb, buf2_len);
da6971d8 7452 }
20346722 7453
0425b46a
SH		 7454 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7455 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7456 (sp->rx_csum)) {
7457 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7458 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7459 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7460 /*
1da177e4
LT		 7461 * NIC verifies if the Checksum of the received
7462 * frame is Ok or not and accordingly returns
7463 * a flag in the RxD.
7464 */
7465 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7466 if (ring_data->lro) {
7d3d0439
RA		 7467 u32 tcp_len;
7468 u8 *tcp;
7469 int ret = 0;
7470
0425b46a
SH		 7471 ret = s2io_club_tcp_session(ring_data,
7472 skb->data, &tcp, &tcp_len, &lro,
7473 rxdp, sp);
7d3d0439
RA		 7474 switch (ret) {
7475 case 3: /* Begin anew */
7476 lro->parent = skb;
7477 goto aggregate;
7478 case 1: /* Aggregate */
7479 {
7480 lro_append_pkt(sp, lro,
7481 skb, tcp_len);
7482 goto aggregate;
7483 }
7484 case 4: /* Flush session */
7485 {
7486 lro_append_pkt(sp, lro,
7487 skb, tcp_len);
cdb5bf02
SH		 7488 queue_rx_frame(lro->parent,
7489 lro->vlan_tag);
7d3d0439
RA		 7490 clear_lro_session(lro);
7491 sp->mac_control.stats_info->
7492 sw_stat.flush_max_pkts++;
7493 goto aggregate;
7494 }
7495 case 2: /* Flush both */
7496 lro->parent->data_len =
7497 lro->frags_len;
7498 sp->mac_control.stats_info->
7499 sw_stat.sending_both++;
cdb5bf02
SH		 7500 queue_rx_frame(lro->parent,
7501 lro->vlan_tag);
7d3d0439
RA		 7502 clear_lro_session(lro);
7503 goto send_up;
7504 case 0: /* sessions exceeded */
c92ca04b
AR		 7505 case -1: /* non-TCP or not
7506 * L2 aggregatable
7507 */
7d3d0439
RA		 7508 case 5: /*
7509 * First pkt in session not
7510 * L3/L4 aggregatable
7511 */
7512 break;
7513 default:
7514 DBG_PRINT(ERR_DBG,
7515 "%s: Samadhana!!\n",
7516 __FUNCTION__);
7517 BUG();
7518 }
7519 }
1da177e4 7520 } else {
20346722
K		 7521 /*
7522 * Packet with erroneous checksum, let the
1da177e4
LT		 7523 * upper layers deal with it.
7524 */
7525 skb->ip_summed = CHECKSUM_NONE;
7526 }
cdb5bf02 7527 } else
1da177e4 7528 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7529
491976b2 7530 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7531send_up:
cdb5bf02 7532 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
1da177e4 7533 dev->last_rx = jiffies;
7d3d0439 7534aggregate:
0425b46a 7535 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7536 return SUCCESS;
7537}
7538
7539/**
7540 * s2io_link - stops/starts the Tx queue.
7541 * @sp : private member of the device structure, which is a pointer to the
7542 * s2io_nic structure.
7543 * @link : inidicates whether link is UP/DOWN.
7544 * Description:
7545 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7546 * status of the NIC is is down or up. This is called by the Alarm
7547 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7548 * Return value:
7549 * void.
7550 */
7551
1ee6dd77 7552static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7553{
7554 struct net_device *dev = (struct net_device *) sp->dev;
7555
7556 if (link != sp->last_link_state) {
b7c5678f 7557 init_tti(sp, link);
1da177e4
LT		 7558 if (link == LINK_DOWN) {
7559 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7560 s2io_stop_all_tx_queue(sp);
1da177e4 7561 netif_carrier_off(dev);
491976b2 7562 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7563 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7564 jiffies - sp->start_time;
7565 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7566 } else {
7567 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7568 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7569 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7570 jiffies - sp->start_time;
7571 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7572 netif_carrier_on(dev);
3a3d5756 7573 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7574 }
7575 }
7576 sp->last_link_state = link;
491976b2 7577 sp->start_time = jiffies;
1da177e4
LT		 7578}
7579
20346722
K		 7580/**
7581 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7582 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7583 * s2io_nic structure.
7584 * Description:
7585 * This function initializes a few of the PCI and PCI-X configuration registers
7586 * with recommended values.
7587 * Return value:
7588 * void
7589 */
7590
1ee6dd77 7591static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7592{
20346722 7593 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7594
7595 /* Enable Data Parity Error Recovery in PCI-X command register. */
7596 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7597 &(pcix_cmd));
1da177e4 7598 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7599 (pcix_cmd | 1));
1da177e4 7600 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7601 &(pcix_cmd));
1da177e4
LT		 7602
7603 /* Set the PErr Response bit in PCI command register. */
7604 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7605 pci_write_config_word(sp->pdev, PCI_COMMAND,
7606 (pci_cmd | PCI_COMMAND_PARITY));
7607 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7608}
7609
3a3d5756
SH		 7610static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7611 u8 *dev_multiq)
9dc737a7 7612{
2fda096d 7613 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7614 (tx_fifo_num < 1)) {
2fda096d
SR		 7615 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7616 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7617
7618 if (tx_fifo_num < 1)
7619 tx_fifo_num = 1;
7620 else
7621 tx_fifo_num = MAX_TX_FIFOS;
7622
2fda096d
SR		 7623 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7624 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7625 }
2fda096d 7626
6cfc482b 7627 if (multiq)
3a3d5756 7628 *dev_multiq = multiq;
6cfc482b
SH		 7629
7630 if (tx_steering_type && (1 == tx_fifo_num)) {
7631 if (tx_steering_type != TX_DEFAULT_STEERING)
7632 DBG_PRINT(ERR_DBG,
7633 "s2io: Tx steering is not supported with "
7634 "one fifo. Disabling Tx steering.\n");
7635 tx_steering_type = NO_STEERING;
7636 }
7637
7638 if ((tx_steering_type < NO_STEERING) ||
7639 (tx_steering_type > TX_DEFAULT_STEERING)) {
7640 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7641 "supported\n");
7642 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7643 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7644 }
7645
0425b46a
SH		 7646 if (rx_ring_num > MAX_RX_RINGS) {
7647 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
9dc737a7 7648 "supported\n");
0425b46a
SH		 7649 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7650 MAX_RX_RINGS);
7651 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7652 }
0425b46a 7653
eccb8628 7654 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7655 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7656 "Defaulting to INTA\n");
7657 *dev_intr_type = INTA;
7658 }
596c5c97 7659
9dc737a7
AR		 7660 if ((*dev_intr_type == MSI_X) &&
7661 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7662 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7663 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7664 "Defaulting to INTA\n");
7665 *dev_intr_type = INTA;
7666 }
fb6a825b 7667
6d517a27 7668 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7669 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7670 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7671 rx_ring_mode = 1;
9dc737a7
AR		 7672 }
7673 return SUCCESS;
7674}
7675
9fc93a41
SS		 7676/**
7677 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7678 * or Traffic class respectively.
b7c5678f 7679 * @nic: device private variable
9fc93a41
SS		 7680 * Description: The function configures the receive steering to
7681 * desired receive ring.
7682 * Return Value: SUCCESS on success and
7683 * '-1' on failure (endian settings incorrect).
7684 */
7685static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7686{
7687 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7688 register u64 val64 = 0;
7689
7690 if (ds_codepoint > 63)
7691 return FAILURE;
7692
7693 val64 = RTS_DS_MEM_DATA(ring);
7694 writeq(val64, &bar0->rts_ds_mem_data);
7695
7696 val64 = RTS_DS_MEM_CTRL_WE |
7697 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7698 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7699
7700 writeq(val64, &bar0->rts_ds_mem_ctrl);
7701
7702 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7703 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7704 S2IO_BIT_RESET);
7705}
7706
1da177e4 7707/**
20346722 7708 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7709 * @pdev : structure containing the PCI related information of the device.
7710 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7711 * Description:
7712 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7713 * All OS related initialization including memory and device structure and
7714 * initlaization of the device private variable is done. Also the swapper
7715 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7716 * registers of the device.
7717 * Return value:
7718 * returns 0 on success and negative on failure.
7719 */
7720
7721static int __devinit
7722s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7723{
1ee6dd77 7724 struct s2io_nic *sp;
1da177e4 7725 struct net_device *dev;
1da177e4
LT		 7726 int i, j, ret;
7727 int dma_flag = FALSE;
7728 u32 mac_up, mac_down;
7729 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7730 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7731 u16 subid;
1ee6dd77 7732 struct mac_info *mac_control;
1da177e4 7733 struct config_param *config;
541ae68f 7734 int mode;
cc6e7c44 7735 u8 dev_intr_type = intr_type;
3a3d5756 7736 u8 dev_multiq = 0;
0795af57 7737 DECLARE_MAC_BUF(mac);
1da177e4 7738
3a3d5756
SH		 7739 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7740 if (ret)
9dc737a7 7741 return ret;
1da177e4
LT		 7742
7743 if ((ret = pci_enable_device(pdev))) {
7744 DBG_PRINT(ERR_DBG,
7745 "s2io_init_nic: pci_enable_device failed\n");
7746 return ret;
7747 }
7748
1e7f0bd8 7749 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7750 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7751 dma_flag = TRUE;
1da177e4 7752 if (pci_set_consistent_dma_mask
1e7f0bd8 7753 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7754 DBG_PRINT(ERR_DBG,
7755 "Unable to obtain 64bit DMA for \
7756 consistent allocations\n");
7757 pci_disable_device(pdev);
7758 return -ENOMEM;
7759 }
1e7f0bd8 7760 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7761 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7762 } else {
7763 pci_disable_device(pdev);
7764 return -ENOMEM;
7765 }
eccb8628
VP		 7766 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7767 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7768 pci_disable_device(pdev);
7769 return -ENODEV;
1da177e4 7770 }
3a3d5756 7771 if (dev_multiq)
6cfc482b 7772 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7773 else
b19fa1fa 7774 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7775 if (dev == NULL) {
7776 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7777 pci_disable_device(pdev);
7778 pci_release_regions(pdev);
7779 return -ENODEV;
7780 }
7781
7782 pci_set_master(pdev);
7783 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7784 SET_NETDEV_DEV(dev, &pdev->dev);
7785
7786 /* Private member variable initialized to s2io NIC structure */
7787 sp = dev->priv;
1ee6dd77 7788 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7789 sp->dev = dev;
7790 sp->pdev = pdev;
1da177e4 7791 sp->high_dma_flag = dma_flag;
1da177e4 7792 sp->device_enabled_once = FALSE;
da6971d8
AR		 7793 if (rx_ring_mode == 1)
7794 sp->rxd_mode = RXD_MODE_1;
7795 if (rx_ring_mode == 2)
7796 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7797
eaae7f72 7798 sp->config.intr_type = dev_intr_type;
1da177e4 7799
541ae68f
K		 7800 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7801 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7802 sp->device_type = XFRAME_II_DEVICE;
7803 else
7804 sp->device_type = XFRAME_I_DEVICE;
7805
43b7c451 7806 sp->lro = lro_enable;
6aa20a22 7807
1da177e4
LT		 7808 /* Initialize some PCI/PCI-X fields of the NIC. */
7809 s2io_init_pci(sp);
7810
20346722 7811 /*
1da177e4 7812 * Setting the device configuration parameters.
20346722
K		 7813 * Most of these parameters can be specified by the user during
7814 * module insertion as they are module loadable parameters. If
7815 * these parameters are not not specified during load time, they
1da177e4
LT		 7816 * are initialized with default values.
7817 */
7818 mac_control = &sp->mac_control;
7819 config = &sp->config;
7820
596c5c97 7821 config->napi = napi;
6cfc482b 7822 config->tx_steering_type = tx_steering_type;
596c5c97 7823
1da177e4 7824 /* Tx side parameters. */
6cfc482b
SH		 7825 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7826 config->tx_fifo_num = MAX_TX_FIFOS;
7827 else
7828 config->tx_fifo_num = tx_fifo_num;
7829
7830 /* Initialize the fifos used for tx steering */
7831 if (config->tx_fifo_num < 5) {
7832 if (config->tx_fifo_num == 1)
7833 sp->total_tcp_fifos = 1;
7834 else
7835 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7836 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7837 sp->total_udp_fifos = 1;
7838 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7839 } else {
7840 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7841 FIFO_OTHER_MAX_NUM);
7842 sp->udp_fifo_idx = sp->total_tcp_fifos;
7843 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7844 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7845 }
7846
3a3d5756 7847 config->multiq = dev_multiq;
6cfc482b 7848 for (i = 0; i < config->tx_fifo_num; i++) {
1da177e4
LT		 7849 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7850 config->tx_cfg[i].fifo_priority = i;
7851 }
7852
20346722
K		 7853 /* mapping the QoS priority to the configured fifos */
7854 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7855 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7856
6cfc482b
SH		 7857 /* map the hashing selector table to the configured fifos */
7858 for (i = 0; i < config->tx_fifo_num; i++)
7859 sp->fifo_selector[i] = fifo_selector[i];
7860
7861
1da177e4
LT		 7862 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7863 for (i = 0; i < config->tx_fifo_num; i++) {
7864 config->tx_cfg[i].f_no_snoop =
7865 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7866 if (config->tx_cfg[i].fifo_len < 65) {
7867 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7868 break;
7869 }
7870 }
fed5eccd
AR		 7871 /* + 2 because one Txd for skb->data and one Txd for UFO */
7872 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7873
7874 /* Rx side parameters. */
1da177e4 7875 config->rx_ring_num = rx_ring_num;
0425b46a 7876 for (i = 0; i < config->rx_ring_num; i++) {
1da177e4 7877 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7878 (rxd_count[sp->rxd_mode] + 1);
1da177e4 7879 config->rx_cfg[i].ring_priority = i;
0425b46a
SH		 7880 mac_control->rings[i].rx_bufs_left = 0;
7881 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7882 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7883 mac_control->rings[i].pdev = sp->pdev;
7884 mac_control->rings[i].dev = sp->dev;
1da177e4
LT		 7885 }
7886
7887 for (i = 0; i < rx_ring_num; i++) {
7888 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7889 config->rx_cfg[i].f_no_snoop =
7890 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7891 }
7892
7893 /* Setting Mac Control parameters */
7894 mac_control->rmac_pause_time = rmac_pause_time;
7895 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7896 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7897
7898
1da177e4
LT		 7899 /* initialize the shared memory used by the NIC and the host */
7900 if (init_shared_mem(sp)) {
7901 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7902 dev->name);
1da177e4
LT		 7903 ret = -ENOMEM;
7904 goto mem_alloc_failed;
7905 }
7906
7907 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7908 pci_resource_len(pdev, 0));
7909 if (!sp->bar0) {
19a60522 7910 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7911 dev->name);
7912 ret = -ENOMEM;
7913 goto bar0_remap_failed;
7914 }
7915
7916 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7917 pci_resource_len(pdev, 2));
7918 if (!sp->bar1) {
19a60522 7919 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7920 dev->name);
7921 ret = -ENOMEM;
7922 goto bar1_remap_failed;
7923 }
7924
7925 dev->irq = pdev->irq;
7926 dev->base_addr = (unsigned long) sp->bar0;
7927
7928 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7929 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7930 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7931 (sp->bar1 + (j * 0x00020000));
7932 }
7933
7934 /* Driver entry points */
7935 dev->open = &s2io_open;
7936 dev->stop = &s2io_close;
7937 dev->hard_start_xmit = &s2io_xmit;
7938 dev->get_stats = &s2io_get_stats;
7939 dev->set_multicast_list = &s2io_set_multicast;
7940 dev->do_ioctl = &s2io_ioctl;
2fd37688 7941 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 7942 dev->change_mtu = &s2io_change_mtu;
7943 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7944 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7945 dev->vlan_rx_register = s2io_vlan_rx_register;
cdb5bf02 7946 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 7947
1da177e4
LT		 7948 /*
7949 * will use eth_mac_addr() for dev->set_mac_address
7950 * mac address will be set every time dev->open() is called
7951 */
612eff0e
BH		 7952#ifdef CONFIG_NET_POLL_CONTROLLER
7953 dev->poll_controller = s2io_netpoll;
7954#endif
7955
1da177e4
LT		 7956 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7957 if (sp->high_dma_flag == TRUE)
7958 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7959 dev->features |= NETIF_F_TSO;
f83ef8c0 7960 dev->features |= NETIF_F_TSO6;
db874e65 7961 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7962 dev->features |= NETIF_F_UFO;
7963 dev->features |= NETIF_F_HW_CSUM;
7964 }
1da177e4
LT		 7965 dev->tx_timeout = &s2io_tx_watchdog;
7966 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7967 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7968 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7969
e960fc5c 7970 pci_save_state(sp->pdev);
1da177e4
LT		 7971
7972 /* Setting swapper control on the NIC, for proper reset operation */
7973 if (s2io_set_swapper(sp)) {
7974 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7975 dev->name);
7976 ret = -EAGAIN;
7977 goto set_swap_failed;
7978 }
7979
541ae68f
K		 7980 /* Verify if the Herc works on the slot its placed into */
7981 if (sp->device_type & XFRAME_II_DEVICE) {
7982 mode = s2io_verify_pci_mode(sp);
7983 if (mode < 0) {
7984 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7985 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7986 ret = -EBADSLT;
7987 goto set_swap_failed;
7988 }
7989 }
7990
f61e0a35
SH		 7991 if (sp->config.intr_type == MSI_X) {
7992 sp->num_entries = config->rx_ring_num + 1;
7993 ret = s2io_enable_msi_x(sp);
7994
7995 if (!ret) {
7996 ret = s2io_test_msi(sp);
7997 /* rollback MSI-X, will re-enable during add_isr() */
7998 remove_msix_isr(sp);
7999 }
8000 if (ret) {
8001
8002 DBG_PRINT(ERR_DBG,
8003 "%s: MSI-X requested but failed to enable\n",
8004 dev->name);
8005 sp->config.intr_type = INTA;
8006 }
8007 }
8008
8009 if (config->intr_type == MSI_X) {
8010 for (i = 0; i < config->rx_ring_num ; i++)
8011 netif_napi_add(dev, &mac_control->rings[i].napi,
8012 s2io_poll_msix, 64);
8013 } else {
8014 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8015 }
8016
541ae68f
K		 8017 /* Not needed for Herc */
8018 if (sp->device_type & XFRAME_I_DEVICE) {
8019 /*
8020 * Fix for all "FFs" MAC address problems observed on
8021 * Alpha platforms
8022 */
8023 fix_mac_address(sp);
8024 s2io_reset(sp);
8025 }
1da177e4
LT		 8026
8027 /*
1da177e4
LT		 8028 * MAC address initialization.
8029 * For now only one mac address will be read and used.
8030 */
8031 bar0 = sp->bar0;
8032 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 8033 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8034 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8035 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 8036 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 8037 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8038 mac_down = (u32) tmp64;
8039 mac_up = (u32) (tmp64 >> 32);
8040
1da177e4
LT		 8041 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8042 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8043 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8044 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8045 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8046 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8047
1da177e4
LT		 8048 /* Set the factory defined MAC address initially */
8049 dev->addr_len = ETH_ALEN;
8050 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8051 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8052
faa4f796
SH		 8053 /* initialize number of multicast & unicast MAC entries variables */
8054 if (sp->device_type == XFRAME_I_DEVICE) {
8055 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8056 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8057 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8058 } else if (sp->device_type == XFRAME_II_DEVICE) {
8059 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8060 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8061 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8062 }
8063
8064 /* store mac addresses from CAM to s2io_nic structure */
8065 do_s2io_store_unicast_mc(sp);
8066
f61e0a35
SH		 8067 /* Configure MSIX vector for number of rings configured plus one */
8068 if ((sp->device_type == XFRAME_II_DEVICE) &&
8069 (config->intr_type == MSI_X))
8070 sp->num_entries = config->rx_ring_num + 1;
8071
c77dd43e
SS		 8072 /* Store the values of the MSIX table in the s2io_nic structure */
8073 store_xmsi_data(sp);
b41477f3
AR		 8074 /* reset Nic and bring it to known state */
8075 s2io_reset(sp);
8076
1da177e4 8077 /*
99993af6 8078 * Initialize link state flags
541ae68f 8079 * and the card state parameter
1da177e4 8080 */
92b84437 8081 sp->state = 0;
1da177e4 8082
1da177e4 8083 /* Initialize spinlocks */
2fda096d
SR		 8084 for (i = 0; i < sp->config.tx_fifo_num; i++)
8085 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65 8086
20346722
K		 8087 /*
8088 * SXE-002: Configure link and activity LED to init state
8089 * on driver load.
1da177e4
LT		 8090 */
8091 subid = sp->pdev->subsystem_device;
8092 if ((subid & 0xFF) >= 0x07) {
8093 val64 = readq(&bar0->gpio_control);
8094 val64 |= 0x0000800000000000ULL;
8095 writeq(val64, &bar0->gpio_control);
8096 val64 = 0x0411040400000000ULL;
8097 writeq(val64, (void __iomem *) bar0 + 0x2700);
8098 val64 = readq(&bar0->gpio_control);
8099 }
8100
8101 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8102
8103 if (register_netdev(dev)) {
8104 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8105 ret = -ENODEV;
8106 goto register_failed;
8107 }
9dc737a7 8108 s2io_vpd_read(sp);
0c61ed5f 8109 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8110 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8111 sp->product_name, pdev->revision);
b41477f3
AR		 8112 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8113 s2io_driver_version);
0795af57
JP		 8114 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8115 dev->name, print_mac(mac, dev->dev_addr));
19a60522 8116 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8117 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8118 mode = s2io_print_pci_mode(sp);
541ae68f 8119 if (mode < 0) {
9dc737a7 8120 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8121 ret = -EBADSLT;
9dc737a7 8122 unregister_netdev(dev);
541ae68f
K		 8123 goto set_swap_failed;
8124 }
541ae68f 8125 }
9dc737a7
AR		 8126 switch(sp->rxd_mode) {
8127 case RXD_MODE_1:
8128 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8129 dev->name);
8130 break;
8131 case RXD_MODE_3B:
8132 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8133 dev->name);
8134 break;
9dc737a7 8135 }
db874e65 8136
f61e0a35
SH		 8137 switch (sp->config.napi) {
8138 case 0:
8139 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8140 break;
8141 case 1:
db874e65 8142 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8143 break;
8144 }
3a3d5756
SH		 8145
8146 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8147 sp->config.tx_fifo_num);
8148
0425b46a
SH		 8149 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8150 sp->config.rx_ring_num);
8151
eaae7f72 8152 switch(sp->config.intr_type) {
9dc737a7
AR		 8153 case INTA:
8154 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8155 break;
9dc737a7
AR		 8156 case MSI_X:
8157 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8158 break;
8159 }
3a3d5756
SH		 8160 if (sp->config.multiq) {
8161 for (i = 0; i < sp->config.tx_fifo_num; i++)
8162 mac_control->fifos[i].multiq = config->multiq;
8163 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8164 dev->name);
8165 } else
8166 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8167 dev->name);
8168
6cfc482b
SH		 8169 switch (sp->config.tx_steering_type) {
8170 case NO_STEERING:
8171 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8172 " transmit\n", dev->name);
8173 break;
8174 case TX_PRIORITY_STEERING:
8175 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8176 " transmit\n", dev->name);
8177 break;
8178 case TX_DEFAULT_STEERING:
8179 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8180 " transmit\n", dev->name);
8181 }
8182
7d3d0439
RA		 8183 if (sp->lro)
8184 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8185 dev->name);
db874e65
SS		 8186 if (ufo)
8187 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8188 " enabled\n", dev->name);
7ba013ac 8189 /* Initialize device name */
9dc737a7 8190 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8191
20346722
K		 8192 /*
8193 * Make Link state as off at this point, when the Link change
8194 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8195 * the right state.
8196 */
8197 netif_carrier_off(dev);
1da177e4
LT		 8198
8199 return 0;
8200
8201 register_failed:
8202 set_swap_failed:
8203 iounmap(sp->bar1);
8204 bar1_remap_failed:
8205 iounmap(sp->bar0);
8206 bar0_remap_failed:
8207 mem_alloc_failed:
8208 free_shared_mem(sp);
8209 pci_disable_device(pdev);
eccb8628 8210 pci_release_regions(pdev);
1da177e4
LT		 8211 pci_set_drvdata(pdev, NULL);
8212 free_netdev(dev);
8213
8214 return ret;
8215}
8216
8217/**
20346722 8218 * s2io_rem_nic - Free the PCI device
1da177e4 8219 * @pdev: structure containing the PCI related information of the device.
20346722 8220 * Description: This function is called by the Pci subsystem to release a
1da177e4 8221 * PCI device and free up all resource held up by the device. This could
20346722 8222 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8223 * from memory.
8224 */
8225
8226static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8227{
8228 struct net_device *dev =
8229 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8230 struct s2io_nic *sp;
1da177e4
LT		 8231
8232 if (dev == NULL) {
8233 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8234 return;
8235 }
8236
22747d6b
FR		 8237 flush_scheduled_work();
8238
1da177e4
LT		 8239 sp = dev->priv;
8240 unregister_netdev(dev);
8241
8242 free_shared_mem(sp);
8243 iounmap(sp->bar0);
8244 iounmap(sp->bar1);
eccb8628 8245 pci_release_regions(pdev);
1da177e4 8246 pci_set_drvdata(pdev, NULL);
1da177e4 8247 free_netdev(dev);
19a60522 8248 pci_disable_device(pdev);
1da177e4
LT		 8249}
8250
8251/**
8252 * s2io_starter - Entry point for the driver
8253 * Description: This function is the entry point for the driver. It verifies
8254 * the module loadable parameters and initializes PCI configuration space.
8255 */
8256
43b7c451 8257static int __init s2io_starter(void)
1da177e4 8258{
29917620 8259 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8260}
8261
8262/**
20346722 8263 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8264 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8265 */
8266
372cc597 8267static __exit void s2io_closer(void)
1da177e4
LT		 8268{
8269 pci_unregister_driver(&s2io_driver);
8270 DBG_PRINT(INIT_DBG, "cleanup done\n");
8271}
8272
8273module_init(s2io_starter);
8274module_exit(s2io_closer);
7d3d0439 8275
6aa20a22 8276static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8277 struct tcphdr **tcp, struct RxD_t *rxdp,
8278 struct s2io_nic *sp)
7d3d0439
RA		 8279{
8280 int ip_off;
8281 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8282
8283 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8284 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8285 __FUNCTION__);
8286 return -1;
8287 }
8288
cdb5bf02
SH		 8289 /* Checking for DIX type or DIX type with VLAN */
8290 if ((l2_type == 0)
8291 || (l2_type == 4)) {
8292 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8293 /*
8294 * If vlan stripping is disabled and the frame is VLAN tagged,
8295 * shift the offset by the VLAN header size bytes.
8296 */
8297 if ((!vlan_strip_flag) &&
8298 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8299 ip_off += HEADER_VLAN_SIZE;
8300 } else {
7d3d0439 8301 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8302 return -1;
7d3d0439
RA		 8303 }
8304
8305 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8306 ip_len = (u8)((*ip)->ihl);
8307 ip_len <<= 2;
8308 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8309
8310 return 0;
8311}
8312
1ee6dd77 8313static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8314 struct tcphdr *tcp)
8315{
8316 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8317 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8318 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8319 return -1;
8320 return 0;
8321}
8322
8323static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8324{
8325 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8326}
8327
1ee6dd77 8328static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8329 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439
RA		 8330{
8331 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8332 lro->l2h = l2h;
8333 lro->iph = ip;
8334 lro->tcph = tcp;
8335 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8336 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8337 lro->sg_num = 1;
8338 lro->total_len = ntohs(ip->tot_len);
8339 lro->frags_len = 0;
cdb5bf02 8340 lro->vlan_tag = vlan_tag;
6aa20a22 8341 /*
7d3d0439
RA		 8342 * check if we saw TCP timestamp. Other consistency checks have
8343 * already been done.
8344 */
8345 if (tcp->doff == 8) {
c8855953
SR		 8346 __be32 *ptr;
8347 ptr = (__be32 *)(tcp+1);
7d3d0439 8348 lro->saw_ts = 1;
c8855953 8349 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8350 lro->cur_tsecr = *(ptr+2);
8351 }
8352 lro->in_use = 1;
8353}
8354
1ee6dd77 8355static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8356{
8357 struct iphdr *ip = lro->iph;
8358 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8359 __sum16 nchk;
1ee6dd77 8360 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 8361 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8362
8363 /* Update L3 header */
8364 ip->tot_len = htons(lro->total_len);
8365 ip->check = 0;
8366 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8367 ip->check = nchk;
8368
8369 /* Update L4 header */
8370 tcp->ack_seq = lro->tcp_ack;
8371 tcp->window = lro->window;
8372
8373 /* Update tsecr field if this session has timestamps enabled */
8374 if (lro->saw_ts) {
c8855953 8375 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8376 *(ptr+2) = lro->cur_tsecr;
8377 }
8378
8379 /* Update counters required for calculation of
8380 * average no. of packets aggregated.
8381 */
8382 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8383 statinfo->sw_stat.num_aggregations++;
8384}
8385
1ee6dd77 8386static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8387 struct tcphdr *tcp, u32 l4_pyld)
8388{
8389 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8390 lro->total_len += l4_pyld;
8391 lro->frags_len += l4_pyld;
8392 lro->tcp_next_seq += l4_pyld;
8393 lro->sg_num++;
8394
8395 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8396 lro->tcp_ack = tcp->ack_seq;
8397 lro->window = tcp->window;
6aa20a22 8398
7d3d0439 8399 if (lro->saw_ts) {
c8855953 8400 __be32 *ptr;
7d3d0439 8401 /* Update tsecr and tsval from this packet */
c8855953
SR		 8402 ptr = (__be32 *)(tcp+1);
8403 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8404 lro->cur_tsecr = *(ptr + 2);
8405 }
8406}
8407
1ee6dd77 8408static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8409 struct tcphdr *tcp, u32 tcp_pyld_len)
8410{
7d3d0439
RA		 8411 u8 *ptr;
8412
79dc1901
AM		 8413 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8414
7d3d0439
RA		 8415 if (!tcp_pyld_len) {
8416 /* Runt frame or a pure ack */
8417 return -1;
8418 }
8419
8420 if (ip->ihl != 5) /* IP has options */
8421 return -1;
8422
75c30b13
AR		 8423 /* If we see CE codepoint in IP header, packet is not mergeable */
8424 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8425 return -1;
8426
8427 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8428 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8429 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8430 /*
8431 * Currently recognize only the ack control word and
8432 * any other control field being set would result in
8433 * flushing the LRO session
8434 */
8435 return -1;
8436 }
8437
6aa20a22 8438 /*
7d3d0439
RA		 8439 * Allow only one TCP timestamp option. Don't aggregate if
8440 * any other options are detected.
8441 */
8442 if (tcp->doff != 5 && tcp->doff != 8)
8443 return -1;
8444
8445 if (tcp->doff == 8) {
6aa20a22 8446 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8447 while (*ptr == TCPOPT_NOP)
8448 ptr++;
8449 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8450 return -1;
8451
8452 /* Ensure timestamp value increases monotonically */
8453 if (l_lro)
c8855953 8454 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8455 return -1;
8456
8457 /* timestamp echo reply should be non-zero */
c8855953 8458 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8459 return -1;
8460 }
8461
8462 return 0;
8463}
8464
8465static int
0425b46a
SH		 8466s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8467 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8468 struct s2io_nic *sp)
7d3d0439
RA		 8469{
8470 struct iphdr *ip;
8471 struct tcphdr *tcph;
8472 int ret = 0, i;
cdb5bf02 8473 u16 vlan_tag = 0;
7d3d0439
RA		 8474
8475 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8476 rxdp, sp))) {
7d3d0439
RA		 8477 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8478 ip->saddr, ip->daddr);
cdb5bf02 8479 } else
7d3d0439 8480 return ret;
7d3d0439 8481
cdb5bf02 8482 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8483 tcph = (struct tcphdr *)*tcp;
8484 *tcp_len = get_l4_pyld_length(ip, tcph);
8485 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8486 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8487 if (l_lro->in_use) {
8488 if (check_for_socket_match(l_lro, ip, tcph))
8489 continue;
8490 /* Sock pair matched */
8491 *lro = l_lro;
8492
8493 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8494 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8495 "0x%x, actual 0x%x\n", __FUNCTION__,
8496 (*lro)->tcp_next_seq,
8497 ntohl(tcph->seq));
8498
8499 sp->mac_control.stats_info->
8500 sw_stat.outof_sequence_pkts++;
8501 ret = 2;
8502 break;
8503 }
8504
8505 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8506 ret = 1; /* Aggregate */
8507 else
8508 ret = 2; /* Flush both */
8509 break;
8510 }
8511 }
8512
8513 if (ret == 0) {
8514 /* Before searching for available LRO objects,
8515 * check if the pkt is L3/L4 aggregatable. If not
8516 * don't create new LRO session. Just send this
8517 * packet up.
8518 */
8519 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8520 return 5;
8521 }
8522
8523 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8524 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8525 if (!(l_lro->in_use)) {
8526 *lro = l_lro;
8527 ret = 3; /* Begin anew */
8528 break;
8529 }
8530 }
8531 }
8532
8533 if (ret == 0) { /* sessions exceeded */
8534 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8535 __FUNCTION__);
8536 *lro = NULL;
8537 return ret;
8538 }
8539
8540 switch (ret) {
8541 case 3:
cdb5bf02
SH		 8542 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8543 vlan_tag);
7d3d0439
RA		 8544 break;
8545 case 2:
8546 update_L3L4_header(sp, *lro);
8547 break;
8548 case 1:
8549 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8550 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8551 update_L3L4_header(sp, *lro);
8552 ret = 4; /* Flush the LRO */
8553 }
8554 break;
8555 default:
8556 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8557 __FUNCTION__);
8558 break;
8559 }
8560
8561 return ret;
8562}
8563
1ee6dd77 8564static void clear_lro_session(struct lro *lro)
7d3d0439 8565{
1ee6dd77 8566 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8567
8568 memset(lro, 0, lro_struct_size);
8569}
8570
cdb5bf02 8571static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8572{
8573 struct net_device *dev = skb->dev;
cdb5bf02 8574 struct s2io_nic *sp = dev->priv;
7d3d0439
RA		 8575
8576 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02
SH		 8577 if (sp->vlgrp && vlan_tag
8578 && (vlan_strip_flag)) {
8579 /* Queueing the vlan frame to the upper layer */
8580 if (sp->config.napi)
8581 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8582 else
8583 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8584 } else {
8585 if (sp->config.napi)
8586 netif_receive_skb(skb);
8587 else
8588 netif_rx(skb);
8589 }
7d3d0439
RA		 8590}
8591
1ee6dd77
RB		 8592static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8593 struct sk_buff *skb,
7d3d0439
RA		 8594 u32 tcp_len)
8595{
75c30b13 8596 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8597
8598 first->len += tcp_len;
8599 first->data_len = lro->frags_len;
8600 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8601 if (skb_shinfo(first)->frag_list)
8602 lro->last_frag->next = skb;
7d3d0439
RA		 8603 else
8604 skb_shinfo(first)->frag_list = skb;
372cc597 8605 first->truesize += skb->truesize;
75c30b13 8606 lro->last_frag = skb;
7d3d0439
RA		 8607 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8608 return;
8609}
d796fdb7
LV		 8610
8611/**
8612 * s2io_io_error_detected - called when PCI error is detected
8613 * @pdev: Pointer to PCI device
8453d43f 8614 * @state: The current pci connection state
d796fdb7
LV		 8615 *
8616 * This function is called after a PCI bus error affecting
8617 * this device has been detected.
8618 */
8619static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8620 pci_channel_state_t state)
8621{
8622 struct net_device *netdev = pci_get_drvdata(pdev);
8623 struct s2io_nic *sp = netdev->priv;
8624
8625 netif_device_detach(netdev);
8626
8627 if (netif_running(netdev)) {
8628 /* Bring down the card, while avoiding PCI I/O */
8629 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8630 }
8631 pci_disable_device(pdev);
8632
8633 return PCI_ERS_RESULT_NEED_RESET;
8634}
8635
8636/**
8637 * s2io_io_slot_reset - called after the pci bus has been reset.
8638 * @pdev: Pointer to PCI device
8639 *
8640 * Restart the card from scratch, as if from a cold-boot.
8641 * At this point, the card has exprienced a hard reset,
8642 * followed by fixups by BIOS, and has its config space
8643 * set up identically to what it was at cold boot.
8644 */
8645static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8646{
8647 struct net_device *netdev = pci_get_drvdata(pdev);
8648 struct s2io_nic *sp = netdev->priv;
8649
8650 if (pci_enable_device(pdev)) {
8651 printk(KERN_ERR "s2io: "
8652 "Cannot re-enable PCI device after reset.\n");
8653 return PCI_ERS_RESULT_DISCONNECT;
8654 }
8655
8656 pci_set_master(pdev);
8657 s2io_reset(sp);
8658
8659 return PCI_ERS_RESULT_RECOVERED;
8660}
8661
8662/**
8663 * s2io_io_resume - called when traffic can start flowing again.
8664 * @pdev: Pointer to PCI device
8665 *
8666 * This callback is called when the error recovery driver tells
8667 * us that its OK to resume normal operation.
8668 */
8669static void s2io_io_resume(struct pci_dev *pdev)
8670{
8671 struct net_device *netdev = pci_get_drvdata(pdev);
8672 struct s2io_nic *sp = netdev->priv;
8673
8674 if (netif_running(netdev)) {
8675 if (s2io_card_up(sp)) {
8676 printk(KERN_ERR "s2io: "
8677 "Can't bring device back up after reset.\n");
8678 return;
8679 }
8680
8681 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8682 s2io_card_down(sp);
8683 printk(KERN_ERR "s2io: "
8684 "Can't resetore mac addr after reset.\n");
8685 return;
8686 }
8687 }
8688
8689 netif_device_attach(netdev);
fd2ea0a7 8690 netif_tx_wake_all_queues(netdev);
d796fdb7 8691}
Clone of davem's net-next-2.6 tree