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drivers/net/: use DEFINE_PCI_DEVICE_TABLE()
[net-next-2.6.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
7d3d0439 82#include <net/tcp.h>
1da177e4 83
1da177e4 84#include <asm/system.h>
fe931395 85#include <asm/div64.h>
330ce0de 86#include <asm/irq.h>
1da177e4
LT		 87
88/* local include */
89#include "s2io.h"
90#include "s2io-regs.h"
91
29d0a2b0 92#define DRV_VERSION "2.0.26.25"
6c1792f4 93
1da177e4 94/* S2io Driver name & version. */
20346722 95static char s2io_driver_name[] = "Neterion";
6c1792f4 96static char s2io_driver_version[] = DRV_VERSION;
1da177e4 97
d44570e4
JP		 98static int rxd_size[2] = {32, 48};
99static int rxd_count[2] = {127, 85};
da6971d8 100
1ee6dd77 101static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 102{
103 int ret;
104
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 107
108 return ret;
109}
110
20346722 111/*
1da177e4
LT		 112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
115 */
d44570e4
JP		 116#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 120
121#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 123
d44570e4 124static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 125{
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127}
128
1da177e4 129/* Ethtool related variables and Macros. */
6fce365d 130static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
136};
137
6fce365d 138static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 139 {"tmac_frms"},
140 {"tmac_data_octets"},
141 {"tmac_drop_frms"},
142 {"tmac_mcst_frms"},
143 {"tmac_bcst_frms"},
144 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 145 {"tmac_ttl_octets"},
146 {"tmac_ucst_frms"},
147 {"tmac_nucst_frms"},
1da177e4 148 {"tmac_any_err_frms"},
bd1034f0 149 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 150 {"tmac_vld_ip_octets"},
151 {"tmac_vld_ip"},
152 {"tmac_drop_ip"},
153 {"tmac_icmp"},
154 {"tmac_rst_tcp"},
155 {"tmac_tcp"},
156 {"tmac_udp"},
157 {"rmac_vld_frms"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
160 {"rmac_drop_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
bd1034f0 164 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 165 {"rmac_long_frms"},
166 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 167 {"rmac_unsup_ctrl_frms"},
168 {"rmac_ttl_octets"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
1da177e4 171 {"rmac_discarded_frms"},
bd1034f0
AR		 172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
174 {"rmac_ttl_frms"},
1da177e4
LT		 175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
177 {"rmac_frag_frms"},
178 {"rmac_jabber_frms"},
bd1034f0
AR		 179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 185 {"rmac_ip"},
186 {"rmac_ip_octets"},
187 {"rmac_hdr_err_ip"},
188 {"rmac_drop_ip"},
189 {"rmac_icmp"},
190 {"rmac_tcp"},
191 {"rmac_udp"},
192 {"rmac_err_drp_udp"},
bd1034f0
AR		 193 {"rmac_xgmii_err_sym"},
194 {"rmac_frms_q0"},
195 {"rmac_frms_q1"},
196 {"rmac_frms_q2"},
197 {"rmac_frms_q3"},
198 {"rmac_frms_q4"},
199 {"rmac_frms_q5"},
200 {"rmac_frms_q6"},
201 {"rmac_frms_q7"},
202 {"rmac_full_q0"},
203 {"rmac_full_q1"},
204 {"rmac_full_q2"},
205 {"rmac_full_q3"},
206 {"rmac_full_q4"},
207 {"rmac_full_q5"},
208 {"rmac_full_q6"},
209 {"rmac_full_q7"},
1da177e4 210 {"rmac_pause_cnt"},
bd1034f0
AR		 211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 213 {"rmac_accepted_ip"},
214 {"rmac_err_tcp"},
bd1034f0
AR		 215 {"rd_req_cnt"},
216 {"new_rd_req_cnt"},
217 {"new_rd_req_rtry_cnt"},
218 {"rd_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
220 {"wr_req_cnt"},
221 {"new_wr_req_cnt"},
222 {"new_wr_req_rtry_cnt"},
223 {"wr_rtry_cnt"},
224 {"wr_disc_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
226 {"txp_wr_cnt"},
227 {"txd_rd_cnt"},
228 {"txd_wr_cnt"},
229 {"rxd_rd_cnt"},
230 {"rxd_wr_cnt"},
231 {"txf_rd_cnt"},
fa1f0cb3
SS		 232 {"rxf_wr_cnt"}
233};
234
6fce365d 235static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
243 {"rmac_vlan_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
246 {"rmac_pf_discard"},
247 {"rmac_da_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 251 {"link_fault_cnt"}
252};
253
6fce365d 254static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
bd1034f0
AR		 258 {"parity_err_cnt"},
259 {"serious_err_cnt"},
260 {"soft_reset_cnt"},
261 {"fifo_full_cnt"},
8116f3cf
SS		 262 {"ring_0_full_cnt"},
263 {"ring_1_full_cnt"},
264 {"ring_2_full_cnt"},
265 {"ring_3_full_cnt"},
266 {"ring_4_full_cnt"},
267 {"ring_5_full_cnt"},
268 {"ring_6_full_cnt"},
269 {"ring_7_full_cnt"},
43b7c451
SH		 270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
290 {"mem_allocated"},
291 {"mem_freed"},
292 {"link_up_cnt"},
293 {"link_down_cnt"},
294 {"link_up_time"},
295 {"link_down_time"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 310 {"tda_err_cnt"},
311 {"pfc_err_cnt"},
312 {"pcc_err_cnt"},
313 {"tti_err_cnt"},
314 {"tpa_err_cnt"},
315 {"sm_err_cnt"},
316 {"lso_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
321 {"rc_err_cnt"},
322 {"prc_pcix_err_cnt"},
323 {"rpa_err_cnt"},
324 {"rda_err_cnt"},
325 {"rti_err_cnt"},
326 {"mc_err_cnt"}
1da177e4
LT		 327};
328
4c3616cd
AMR		 329#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 332
d44570e4
JP		 333#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 335
d44570e4
JP		 336#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 338
4c3616cd 339#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 340#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 341
d44570e4
JP		 342#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
25fff88e 347
2fd37688
SS		 348/* copy mac addr to def_mac_addr array */
349static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350{
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357}
04025095 358
be3a6b02
K		 359/* Add the vlan */
360static void s2io_vlan_rx_register(struct net_device *dev,
04025095 361 struct vlan_group *grp)
be3a6b02 362{
2fda096d 363 int i;
4cf1653a 364 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 365 unsigned long flags[MAX_TX_FIFOS];
2fda096d 366 struct config_param *config = &nic->config;
ffb5df6c 367 struct mac_info *mac_control = &nic->mac_control;
2fda096d 368
13d866a9
JP		 369 for (i = 0; i < config->tx_fifo_num; i++) {
370 struct fifo_info *fifo = &mac_control->fifos[i];
371
372 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373 }
be3a6b02 374
be3a6b02 375 nic->vlgrp = grp;
13d866a9
JP		 376
377 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378 struct fifo_info *fifo = &mac_control->fifos[i];
379
380 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381 }
be3a6b02
K		 382}
383
cdb5bf02 384/* Unregister the vlan */
04025095 385static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 386{
387 int i;
4cf1653a 388 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 389 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 390 struct config_param *config = &nic->config;
ffb5df6c 391 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 392
13d866a9
JP		 393 for (i = 0; i < config->tx_fifo_num; i++) {
394 struct fifo_info *fifo = &mac_control->fifos[i];
395
396 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397 }
cdb5bf02
SH		 398
399 if (nic->vlgrp)
400 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
13d866a9
JP		 402 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403 struct fifo_info *fifo = &mac_control->fifos[i];
404
405 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406 }
cdb5bf02
SH		 407}
408
20346722 409/*
1da177e4
LT		 410 * Constants to be programmed into the Xena's registers, to configure
411 * the XAUI.
412 */
413
1da177e4 414#define END_SIGN 0x0
f71e1309 415static const u64 herc_act_dtx_cfg[] = {
541ae68f 416 /* Set address */
e960fc5c 417 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 418 /* Write data */
e960fc5c 419 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 420 /* Set address */
421 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 /* Write data */
423 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 /* Set address */
e960fc5c 425 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 /* Write data */
427 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 /* Set address */
541ae68f
K		 429 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 /* Write data */
431 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432 /* Done */
433 END_SIGN
434};
435
f71e1309 436static const u64 xena_dtx_cfg[] = {
c92ca04b 437 /* Set address */
1da177e4 438 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 439 /* Write data */
440 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 /* Set address */
442 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 /* Write data */
444 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 /* Set address */
1da177e4 446 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 447 /* Write data */
448 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 449 END_SIGN
450};
451
20346722 452/*
1da177e4
LT		 453 * Constants for Fixing the MacAddress problem seen mostly on
454 * Alpha machines.
455 */
f71e1309 456static const u64 fix_mac[] = {
1da177e4
LT		 457 0x0060000000000000ULL, 0x0060600000000000ULL,
458 0x0040600000000000ULL, 0x0000600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0000600000000000ULL,
470 0x0040600000000000ULL, 0x0060600000000000ULL,
471 END_SIGN
472};
473
b41477f3
AR		 474MODULE_LICENSE("GPL");
475MODULE_VERSION(DRV_VERSION);
476
477
1da177e4 478/* Module Loadable parameters. */
6cfc482b 479S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 480S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 481S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 482S2IO_PARM_INT(rx_ring_mode, 1);
483S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484S2IO_PARM_INT(rmac_pause_time, 0x100);
485S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487S2IO_PARM_INT(shared_splits, 0);
488S2IO_PARM_INT(tmac_util_period, 5);
489S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 490S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 491/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 493/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 494S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 495/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 496S2IO_PARM_INT(intr_type, 2);
7d3d0439 497/* Large receive offload feature */
43b7c451
SH		 498static unsigned int lro_enable;
499module_param_named(lro, lro_enable, uint, 0);
500
7d3d0439
RA		 501/* Max pkts to be aggregated by LRO at one time. If not specified,
502 * aggregation happens until we hit max IP pkt size(64K)
503 */
b41477f3 504S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 505S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 506
507S2IO_PARM_INT(napi, 1);
508S2IO_PARM_INT(ufo, 0);
926930b2 509S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 510
511static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 512{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 513static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 514{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 515static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 516{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 517
518module_param_array(tx_fifo_len, uint, NULL, 0);
519module_param_array(rx_ring_sz, uint, NULL, 0);
520module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 521
20346722 522/*
1da177e4 523 * S2IO device table.
20346722 524 * This table lists all the devices that this driver supports.
1da177e4 525 */
a3aa1884 526static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 532 PCI_ANY_ID, PCI_ANY_ID},
533 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
534 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 535 {0,}
536};
537
538MODULE_DEVICE_TABLE(pci, s2io_tbl);
539
d796fdb7
LV		 540static struct pci_error_handlers s2io_err_handler = {
541 .error_detected = s2io_io_error_detected,
542 .slot_reset = s2io_io_slot_reset,
543 .resume = s2io_io_resume,
544};
545
1da177e4 546static struct pci_driver s2io_driver = {
d44570e4
JP		 547 .name = "S2IO",
548 .id_table = s2io_tbl,
549 .probe = s2io_init_nic,
550 .remove = __devexit_p(s2io_rem_nic),
551 .err_handler = &s2io_err_handler,
1da177e4
LT		 552};
553
554/* A simplifier macro used both by init and free shared_mem Fns(). */
555#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
556
3a3d5756
SH		 557/* netqueue manipulation helper functions */
558static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
559{
fd2ea0a7
DM		 560 if (!sp->config.multiq) {
561 int i;
562
3a3d5756
SH		 563 for (i = 0; i < sp->config.tx_fifo_num; i++)
564 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 565 }
fd2ea0a7 566 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 567}
568
569static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
570{
fd2ea0a7 571 if (!sp->config.multiq)
3a3d5756
SH		 572 sp->mac_control.fifos[fifo_no].queue_state =
573 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 574
575 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 576}
577
578static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
579{
fd2ea0a7
DM		 580 if (!sp->config.multiq) {
581 int i;
582
3a3d5756
SH		 583 for (i = 0; i < sp->config.tx_fifo_num; i++)
584 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 585 }
fd2ea0a7 586 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 587}
588
589static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
590{
fd2ea0a7 591 if (!sp->config.multiq)
3a3d5756
SH		 592 sp->mac_control.fifos[fifo_no].queue_state =
593 FIFO_QUEUE_START;
fd2ea0a7
DM		 594
595 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 596}
597
598static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
599{
fd2ea0a7
DM		 600 if (!sp->config.multiq) {
601 int i;
602
3a3d5756
SH		 603 for (i = 0; i < sp->config.tx_fifo_num; i++)
604 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 605 }
fd2ea0a7 606 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 607}
608
609static inline void s2io_wake_tx_queue(
610 struct fifo_info *fifo, int cnt, u8 multiq)
611{
612
3a3d5756
SH		 613 if (multiq) {
614 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
615 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 616 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 617 if (netif_queue_stopped(fifo->dev)) {
618 fifo->queue_state = FIFO_QUEUE_START;
619 netif_wake_queue(fifo->dev);
620 }
621 }
622}
623
1da177e4
LT		 624/**
625 * init_shared_mem - Allocation and Initialization of Memory
626 * @nic: Device private variable.
20346722
K		 627 * Description: The function allocates all the memory areas shared
628 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 629 * Rx descriptors and the statistics block.
630 */
631
632static int init_shared_mem(struct s2io_nic *nic)
633{
634 u32 size;
635 void *tmp_v_addr, *tmp_v_addr_next;
636 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 637 struct RxD_block *pre_rxd_blk = NULL;
372cc597 638 int i, j, blk_cnt;
1da177e4
LT		 639 int lst_size, lst_per_page;
640 struct net_device *dev = nic->dev;
8ae418cf 641 unsigned long tmp;
1ee6dd77 642 struct buffAdd *ba;
ffb5df6c
JP		 643 struct config_param *config = &nic->config;
644 struct mac_info *mac_control = &nic->mac_control;
491976b2 645 unsigned long long mem_allocated = 0;
1da177e4 646
13d866a9 647 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 648 size = 0;
649 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 650 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
651
652 size += tx_cfg->fifo_len;
1da177e4
LT		 653 }
654 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 655 DBG_PRINT(ERR_DBG,
656 "Too many TxDs requested: %d, max supported: %d\n",
657 size, MAX_AVAILABLE_TXDS);
b41477f3 658 return -EINVAL;
1da177e4
LT		 659 }
660
2fda096d
SR		 661 size = 0;
662 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 663 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
664
665 size = tx_cfg->fifo_len;
2fda096d
SR		 666 /*
667 * Legal values are from 2 to 8192
668 */
669 if (size < 2) {
9e39f7c5
JP		 670 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
671 "Valid lengths are 2 through 8192\n",
672 i, size);
2fda096d
SR		 673 return -EINVAL;
674 }
675 }
676
1ee6dd77 677 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 678 lst_per_page = PAGE_SIZE / lst_size;
679
680 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 681 struct fifo_info *fifo = &mac_control->fifos[i];
682 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
683 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 684 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 685
686 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
687 if (!fifo->list_info) {
d44570e4 688 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 689 return -ENOMEM;
690 }
491976b2 691 mem_allocated += list_holder_size;
1da177e4
LT		 692 }
693 for (i = 0; i < config->tx_fifo_num; i++) {
694 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
695 lst_per_page);
13d866a9
JP		 696 struct fifo_info *fifo = &mac_control->fifos[i];
697 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
698
699 fifo->tx_curr_put_info.offset = 0;
700 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
701 fifo->tx_curr_get_info.offset = 0;
702 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
703 fifo->fifo_no = i;
704 fifo->nic = nic;
705 fifo->max_txds = MAX_SKB_FRAGS + 2;
706 fifo->dev = dev;
20346722 707
1da177e4
LT		 708 for (j = 0; j < page_num; j++) {
709 int k = 0;
710 dma_addr_t tmp_p;
711 void *tmp_v;
712 tmp_v = pci_alloc_consistent(nic->pdev,
713 PAGE_SIZE, &tmp_p);
714 if (!tmp_v) {
9e39f7c5
JP		 715 DBG_PRINT(INFO_DBG,
716 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 717 return -ENOMEM;
718 }
776bd20f 719 /* If we got a zero DMA address(can happen on
720 * certain platforms like PPC), reallocate.
721 * Store virtual address of page we don't want,
722 * to be freed later.
723 */
724 if (!tmp_p) {
725 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 726 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 727 "%s: Zero DMA address for TxDL. "
728 "Virtual address %p\n",
729 dev->name, tmp_v);
776bd20f 730 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 731 PAGE_SIZE, &tmp_p);
776bd20f 732 if (!tmp_v) {
0c61ed5f 733 DBG_PRINT(INFO_DBG,
9e39f7c5 734 "pci_alloc_consistent failed for TxDL\n");
776bd20f 735 return -ENOMEM;
736 }
491976b2 737 mem_allocated += PAGE_SIZE;
776bd20f 738 }
1da177e4
LT		 739 while (k < lst_per_page) {
740 int l = (j * lst_per_page) + k;
13d866a9 741 if (l == tx_cfg->fifo_len)
20346722 742 break;
13d866a9 743 fifo->list_info[l].list_virt_addr =
d44570e4 744 tmp_v + (k * lst_size);
13d866a9 745 fifo->list_info[l].list_phy_addr =
d44570e4 746 tmp_p + (k * lst_size);
1da177e4
LT		 747 k++;
748 }
749 }
750 }
1da177e4 751
2fda096d 752 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 753 struct fifo_info *fifo = &mac_control->fifos[i];
754 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
755
756 size = tx_cfg->fifo_len;
757 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
758 if (!fifo->ufo_in_band_v)
2fda096d
SR		 759 return -ENOMEM;
760 mem_allocated += (size * sizeof(u64));
761 }
fed5eccd 762
1da177e4
LT		 763 /* Allocation and initialization of RXDs in Rings */
764 size = 0;
765 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 766 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
767 struct ring_info *ring = &mac_control->rings[i];
768
769 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 770 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
771 "multiple of RxDs per Block\n",
772 dev->name, i);
1da177e4
LT		 773 return FAILURE;
774 }
13d866a9
JP		 775 size += rx_cfg->num_rxd;
776 ring->block_count = rx_cfg->num_rxd /
d44570e4 777 (rxd_count[nic->rxd_mode] + 1);
13d866a9 778 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 779 }
da6971d8 780 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 781 size = (size * (sizeof(struct RxD1)));
da6971d8 782 else
1ee6dd77 783 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 784
785 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 786 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
787 struct ring_info *ring = &mac_control->rings[i];
788
789 ring->rx_curr_get_info.block_index = 0;
790 ring->rx_curr_get_info.offset = 0;
791 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
792 ring->rx_curr_put_info.block_index = 0;
793 ring->rx_curr_put_info.offset = 0;
794 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
795 ring->nic = nic;
796 ring->ring_no = i;
797 ring->lro = lro_enable;
798
799 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 800 /* Allocating all the Rx blocks */
801 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 802 struct rx_block_info *rx_blocks;
da6971d8
AR		 803 int l;
804
13d866a9 805 rx_blocks = &ring->rx_blocks[j];
d44570e4 806 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 807 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
808 &tmp_p_addr);
809 if (tmp_v_addr == NULL) {
810 /*
20346722
K		 811 * In case of failure, free_shared_mem()
812 * is called, which should free any
813 * memory that was alloced till the
1da177e4
LT		 814 * failure happened.
815 */
da6971d8 816 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 817 return -ENOMEM;
818 }
491976b2 819 mem_allocated += size;
1da177e4 820 memset(tmp_v_addr, 0, size);
4f870320
JP		 821
822 size = sizeof(struct rxd_info) *
823 rxd_count[nic->rxd_mode];
da6971d8
AR		 824 rx_blocks->block_virt_addr = tmp_v_addr;
825 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 826 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 827 if (!rx_blocks->rxds)
828 return -ENOMEM;
4f870320 829 mem_allocated += size;
d44570e4 830 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 831 rx_blocks->rxds[l].virt_addr =
832 rx_blocks->block_virt_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 rx_blocks->rxds[l].dma_addr =
835 rx_blocks->block_dma_addr +
836 (rxd_size[nic->rxd_mode] * l);
837 }
1da177e4
LT		 838 }
839 /* Interlinking all Rx Blocks */
840 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 841 int next = (j + 1) % blk_cnt;
842 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
843 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
844 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
845 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 846
d44570e4 847 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 848 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 849 (unsigned long)tmp_v_addr_next;
1da177e4 850 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 851 (u64)tmp_p_addr_next;
1da177e4
LT		 852 }
853 }
6d517a27 854 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 855 /*
856 * Allocation of Storages for buffer addresses in 2BUFF mode
857 * and the buffers as well.
858 */
859 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 860 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
861 struct ring_info *ring = &mac_control->rings[i];
862
863 blk_cnt = rx_cfg->num_rxd /
d44570e4 864 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 865 size = sizeof(struct buffAdd *) * blk_cnt;
866 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 867 if (!ring->ba)
1da177e4 868 return -ENOMEM;
4f870320 869 mem_allocated += size;
da6971d8
AR		 870 for (j = 0; j < blk_cnt; j++) {
871 int k = 0;
4f870320
JP		 872
873 size = sizeof(struct buffAdd) *
874 (rxd_count[nic->rxd_mode] + 1);
875 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 876 if (!ring->ba[j])
1da177e4 877 return -ENOMEM;
4f870320 878 mem_allocated += size;
da6971d8 879 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 880 ba = &ring->ba[j][k];
4f870320
JP		 881 size = BUF0_LEN + ALIGN_SIZE;
882 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 883 if (!ba->ba_0_org)
884 return -ENOMEM;
4f870320 885 mem_allocated += size;
da6971d8
AR		 886 tmp = (unsigned long)ba->ba_0_org;
887 tmp += ALIGN_SIZE;
d44570e4
JP		 888 tmp &= ~((unsigned long)ALIGN_SIZE);
889 ba->ba_0 = (void *)tmp;
da6971d8 890
4f870320
JP		 891 size = BUF1_LEN + ALIGN_SIZE;
892 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 893 if (!ba->ba_1_org)
894 return -ENOMEM;
4f870320 895 mem_allocated += size;
d44570e4 896 tmp = (unsigned long)ba->ba_1_org;
da6971d8 897 tmp += ALIGN_SIZE;
d44570e4
JP		 898 tmp &= ~((unsigned long)ALIGN_SIZE);
899 ba->ba_1 = (void *)tmp;
da6971d8
AR		 900 k++;
901 }
1da177e4
LT		 902 }
903 }
904 }
1da177e4
LT		 905
906 /* Allocation and initialization of Statistics block */
1ee6dd77 907 size = sizeof(struct stat_block);
d44570e4
JP		 908 mac_control->stats_mem =
909 pci_alloc_consistent(nic->pdev, size,
910 &mac_control->stats_mem_phy);
1da177e4
LT		 911
912 if (!mac_control->stats_mem) {
20346722
K		 913 /*
914 * In case of failure, free_shared_mem() is called, which
915 * should free any memory that was alloced till the
1da177e4
LT		 916 * failure happened.
917 */
918 return -ENOMEM;
919 }
491976b2 920 mem_allocated += size;
1da177e4
LT		 921 mac_control->stats_mem_sz = size;
922
923 tmp_v_addr = mac_control->stats_mem;
d44570e4 924 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 925 memset(tmp_v_addr, 0, size);
9e39f7c5 926 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", dev->name,
d44570e4 927 (unsigned long long)tmp_p_addr);
491976b2 928 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 929 return SUCCESS;
930}
931
20346722
K		 932/**
933 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 934 * @nic: Device private variable.
935 * Description: This function is to free all memory locations allocated by
936 * the init_shared_mem() function and return it to the kernel.
937 */
938
939static void free_shared_mem(struct s2io_nic *nic)
940{
941 int i, j, blk_cnt, size;
942 void *tmp_v_addr;
943 dma_addr_t tmp_p_addr;
1da177e4 944 int lst_size, lst_per_page;
8910b49f 945 struct net_device *dev;
491976b2 946 int page_num = 0;
ffb5df6c
JP		 947 struct config_param *config;
948 struct mac_info *mac_control;
949 struct stat_block *stats;
950 struct swStat *swstats;
1da177e4
LT		 951
952 if (!nic)
953 return;
954
8910b49f
MG		 955 dev = nic->dev;
956
1da177e4 957 config = &nic->config;
ffb5df6c
JP		 958 mac_control = &nic->mac_control;
959 stats = mac_control->stats_info;
960 swstats = &stats->sw_stat;
1da177e4 961
d44570e4 962 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
13d866a9
JP		 972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
6aa20a22 975 return;
13d866a9
JP		 976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
1da177e4
LT		 979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 981 fli->list_virt_addr,
982 fli->list_phy_addr);
ffb5df6c 983 swstats->mem_freed += PAGE_SIZE;
1da177e4 984 }
776bd20f 985 /* If we got a zero DMA address during allocation,
986 * free the page now
987 */
988 if (mac_control->zerodma_virt_addr) {
989 pci_free_consistent(nic->pdev, PAGE_SIZE,
990 mac_control->zerodma_virt_addr,
991 (dma_addr_t)0);
6aa20a22 992 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 993 "%s: Freeing TxDL with zero DMA address. "
994 "Virtual address %p\n",
995 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 996 swstats->mem_freed += PAGE_SIZE;
776bd20f 997 }
13d866a9 998 kfree(fifo->list_info);
82c2d023 999 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1000 sizeof(struct list_info_hold);
1da177e4
LT		 1001 }
1002
1da177e4 1003 size = SIZE_OF_BLOCK;
1da177e4 1004 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1005 struct ring_info *ring = &mac_control->rings[i];
1006
1007 blk_cnt = ring->block_count;
1da177e4 1008 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1009 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1011 if (tmp_v_addr == NULL)
1012 break;
1013 pci_free_consistent(nic->pdev, size,
1014 tmp_v_addr, tmp_p_addr);
ffb5df6c 1015 swstats->mem_freed += size;
13d866a9 1016 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1017 swstats->mem_freed += sizeof(struct rxd_info) *
1018 rxd_count[nic->rxd_mode];
1da177e4
LT		 1019 }
1020 }
1021
6d517a27 1022 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1023 /* Freeing buffer storage addresses in 2BUFF mode. */
1024 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1025 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026 struct ring_info *ring = &mac_control->rings[i];
1027
1028 blk_cnt = rx_cfg->num_rxd /
1029 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1030 for (j = 0; j < blk_cnt; j++) {
1031 int k = 0;
13d866a9 1032 if (!ring->ba[j])
da6971d8
AR		 1033 continue;
1034 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1035 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1036 kfree(ba->ba_0_org);
ffb5df6c
JP		 1037 swstats->mem_freed +=
1038 BUF0_LEN + ALIGN_SIZE;
da6971d8 1039 kfree(ba->ba_1_org);
ffb5df6c
JP		 1040 swstats->mem_freed +=
1041 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1042 k++;
1043 }
13d866a9 1044 kfree(ring->ba[j]);
ffb5df6c
JP		 1045 swstats->mem_freed += sizeof(struct buffAdd) *
1046 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1047 }
13d866a9 1048 kfree(ring->ba);
ffb5df6c
JP		 1049 swstats->mem_freed += sizeof(struct buffAdd *) *
1050 blk_cnt;
1da177e4 1051 }
1da177e4 1052 }
1da177e4 1053
2fda096d 1054 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1055 struct fifo_info *fifo = &mac_control->fifos[i];
1056 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1059 swstats->mem_freed += tx_cfg->fifo_len *
1060 sizeof(u64);
13d866a9 1061 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1062 }
1063 }
1064
1da177e4 1065 if (mac_control->stats_mem) {
ffb5df6c 1066 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1067 pci_free_consistent(nic->pdev,
1068 mac_control->stats_mem_sz,
1069 mac_control->stats_mem,
1070 mac_control->stats_mem_phy);
491976b2 1071 }
1da177e4
LT		 1072}
1073
541ae68f
K		 1074/**
1075 * s2io_verify_pci_mode -
1076 */
1077
1ee6dd77 1078static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1079{
1ee6dd77 1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1081 register u64 val64 = 0;
1082 int mode;
1083
1084 val64 = readq(&bar0->pci_mode);
1085 mode = (u8)GET_PCI_MODE(val64);
1086
d44570e4 1087 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1088 return -1; /* Unknown PCI mode */
1089 return mode;
1090}
1091
c92ca04b
AR		 1092#define NEC_VENID 0x1033
1093#define NEC_DEVID 0x0125
1094static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095{
1096 struct pci_dev *tdev = NULL;
26d36b64
AC		 1097 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1099 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1100 pci_dev_put(tdev);
c92ca04b 1101 return 1;
7ad62dbc 1102 }
c92ca04b
AR		 1103 }
1104 }
1105 return 0;
1106}
541ae68f 1107
7b32a312 1108static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1109/**
1110 * s2io_print_pci_mode -
1111 */
1ee6dd77 1112static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1113{
1ee6dd77 1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1115 register u64 val64 = 0;
1116 int mode;
1117 struct config_param *config = &nic->config;
9e39f7c5 1118 const char *pcimode;
541ae68f
K		 1119
1120 val64 = readq(&bar0->pci_mode);
1121 mode = (u8)GET_PCI_MODE(val64);
1122
d44570e4 1123 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1124 return -1; /* Unknown PCI mode */
1125
c92ca04b
AR		 1126 config->bus_speed = bus_speed[mode];
1127
1128 if (s2io_on_nec_bridge(nic->pdev)) {
1129 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1130 nic->dev->name);
c92ca04b
AR		 1131 return mode;
1132 }
1133
d44570e4
JP		 1134 switch (mode) {
1135 case PCI_MODE_PCI_33:
9e39f7c5 1136 pcimode = "33MHz PCI bus";
d44570e4
JP		 1137 break;
1138 case PCI_MODE_PCI_66:
9e39f7c5 1139 pcimode = "66MHz PCI bus";
d44570e4
JP		 1140 break;
1141 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1142 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1143 break;
1144 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1145 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1146 break;
1147 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1148 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1149 break;
1150 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1151 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1152 break;
1153 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1154 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1155 break;
1156 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1157 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1158 break;
1159 default:
9e39f7c5
JP		 1160 pcimode = "unsupported bus!";
1161 mode = -1;
541ae68f
K		 1162 }
1163
9e39f7c5
JP		 1164 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
541ae68f
K		 1167 return mode;
1168}
1169
b7c5678f
RV		 1170/**
1171 * init_tti - Initialization transmit traffic interrupt scheme
1172 * @nic: device private variable
1173 * @link: link status (UP/DOWN) used to enable/disable continuous
1174 * transmit interrupts
1175 * Description: The function configures transmit traffic interrupts
1176 * Return Value: SUCCESS on success and
1177 * '-1' on failure
1178 */
1179
0d66afe7 1180static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1181{
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183 register u64 val64 = 0;
1184 int i;
ffb5df6c 1185 struct config_param *config = &nic->config;
b7c5678f
RV		 1186
1187 for (i = 0; i < config->tx_fifo_num; i++) {
1188 /*
1189 * TTI Initialization. Default Tx timer gets us about
1190 * 250 interrupts per sec. Continuous interrupts are enabled
1191 * by default.
1192 */
1193 if (nic->device_type == XFRAME_II_DEVICE) {
1194 int count = (nic->config.bus_speed * 125)/2;
1195 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196 } else
1197 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1200 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1203 if (i == 0)
1204 if (use_continuous_tx_intrs && (link == LINK_UP))
1205 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1206 writeq(val64, &bar0->tti_data1_mem);
1207
ac731ab6
SH		 1208 if (nic->config.intr_type == MSI_X) {
1209 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212 TTI_DATA2_MEM_TX_UFC_D(0x300);
1213 } else {
1214 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1215 TX_DEFAULT_STEERING) &&
1216 (config->tx_fifo_num > 1) &&
1217 (i >= nic->udp_fifo_idx) &&
1218 (i < (nic->udp_fifo_idx +
1219 nic->total_udp_fifos)))
ac731ab6
SH		 1220 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223 TTI_DATA2_MEM_TX_UFC_D(0x120);
1224 else
1225 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228 TTI_DATA2_MEM_TX_UFC_D(0x80);
1229 }
b7c5678f
RV		 1230
1231 writeq(val64, &bar0->tti_data2_mem);
1232
d44570e4
JP		 1233 val64 = TTI_CMD_MEM_WE |
1234 TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1236 writeq(val64, &bar0->tti_command_mem);
1237
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1239 TTI_CMD_MEM_STROBE_NEW_CMD,
1240 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1241 return FAILURE;
1242 }
1243
1244 return SUCCESS;
1245}
1246
20346722
K		 1247/**
1248 * init_nic - Initialization of hardware
b7c5678f 1249 * @nic: device private variable
20346722
K		 1250 * Description: The function sequentially configures every block
1251 * of the H/W from their reset values.
1252 * Return Value: SUCCESS on success and
1da177e4
LT		 1253 * '-1' on failure (endian settings incorrect).
1254 */
1255
1256static int init_nic(struct s2io_nic *nic)
1257{
1ee6dd77 1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1259 struct net_device *dev = nic->dev;
1260 register u64 val64 = 0;
1261 void __iomem *add;
1262 u32 time;
1263 int i, j;
c92ca04b 1264 int dtx_cnt = 0;
1da177e4 1265 unsigned long long mem_share;
20346722 1266 int mem_size;
ffb5df6c
JP		 1267 struct config_param *config = &nic->config;
1268 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1269
5e25b9dd 1270 /* to set the swapper controle on the card */
d44570e4
JP		 1271 if (s2io_set_swapper(nic)) {
1272 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1273 return -EIO;
1da177e4
LT		 1274 }
1275
541ae68f
K		 1276 /*
1277 * Herc requires EOI to be removed from reset before XGXS, so..
1278 */
1279 if (nic->device_type & XFRAME_II_DEVICE) {
1280 val64 = 0xA500000000ULL;
1281 writeq(val64, &bar0->sw_reset);
1282 msleep(500);
1283 val64 = readq(&bar0->sw_reset);
1284 }
1285
1da177e4
LT		 1286 /* Remove XGXS from reset state */
1287 val64 = 0;
1288 writeq(val64, &bar0->sw_reset);
1da177e4 1289 msleep(500);
20346722 1290 val64 = readq(&bar0->sw_reset);
1da177e4 1291
7962024e
SH		 1292 /* Ensure that it's safe to access registers by checking
1293 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294 */
1295 if (nic->device_type == XFRAME_II_DEVICE) {
1296 for (i = 0; i < 50; i++) {
1297 val64 = readq(&bar0->adapter_status);
1298 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299 break;
1300 msleep(10);
1301 }
1302 if (i == 50)
1303 return -ENODEV;
1304 }
1305
1da177e4
LT		 1306 /* Enable Receiving broadcasts */
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1309 val64 |= MAC_RMAC_BCAST_ENABLE;
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1311 writel((u32)val64, add);
1da177e4
LT		 1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) (val64 >> 32), (add + 4));
1314
1315 /* Read registers in all blocks */
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1319
1320 /* Set MTU */
1321 val64 = dev->mtu;
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
541ae68f
K		 1324 if (nic->device_type & XFRAME_II_DEVICE) {
1325 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1326 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1327 &bar0->dtx_control, UF);
541ae68f
K		 1328 if (dtx_cnt & 0x1)
1329 msleep(1); /* Necessary!! */
1da177e4
LT		 1330 dtx_cnt++;
1331 }
541ae68f 1332 } else {
c92ca04b
AR		 1333 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1337 dtx_cnt++;
1da177e4
LT		 1338 }
1339 }
1340
1341 /* Tx DMA Initialization */
1342 val64 = 0;
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1347
1da177e4 1348 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1349 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1353
1354 if (i == (config->tx_fifo_num - 1)) {
1355 if (i % 2 == 0)
1356 i++;
1357 }
1358
1359 switch (i) {
1360 case 1:
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1362 val64 = 0;
b7c5678f 1363 j = 0;
1da177e4
LT		 1364 break;
1365 case 3:
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1367 val64 = 0;
b7c5678f 1368 j = 0;
1da177e4
LT		 1369 break;
1370 case 5:
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1372 val64 = 0;
b7c5678f 1373 j = 0;
1da177e4
LT		 1374 break;
1375 case 7:
1376 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1377 val64 = 0;
1378 j = 0;
1379 break;
1380 default:
1381 j++;
1da177e4
LT		 1382 break;
1383 }
1384 }
1385
5e25b9dd
K		 1386 /*
1387 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389 */
d44570e4 1390 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1da177e4
LT		 1393 val64 = readq(&bar0->tx_fifo_partition_0);
1394 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1396
20346722
K		 1397 /*
1398 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1399 * integrity checking.
1400 */
1401 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1402 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403 TX_PA_CFG_IGNORE_SNAP_OUI |
1404 TX_PA_CFG_IGNORE_LLC_CTRL |
1405 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1406 writeq(val64, &bar0->tx_pa_cfg);
1407
1408 /* Rx DMA intialization. */
1409 val64 = 0;
1410 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1411 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1414 }
1415 writeq(val64, &bar0->rx_queue_priority);
1416
20346722
K		 1417 /*
1418 * Allocating equal share of memory to all the
1da177e4
LT		 1419 * configured Rings.
1420 */
1421 val64 = 0;
541ae68f
K		 1422 if (nic->device_type & XFRAME_II_DEVICE)
1423 mem_size = 32;
1424 else
1425 mem_size = 64;
1426
1da177e4
LT		 1427 for (i = 0; i < config->rx_ring_num; i++) {
1428 switch (i) {
1429 case 0:
20346722
K		 1430 mem_share = (mem_size / config->rx_ring_num +
1431 mem_size % config->rx_ring_num);
1da177e4
LT		 1432 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433 continue;
1434 case 1:
20346722 1435 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1436 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437 continue;
1438 case 2:
20346722 1439 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1440 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441 continue;
1442 case 3:
20346722 1443 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1444 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445 continue;
1446 case 4:
20346722 1447 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1448 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449 continue;
1450 case 5:
20346722 1451 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1452 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453 continue;
1454 case 6:
20346722 1455 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1456 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457 continue;
1458 case 7:
20346722 1459 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1460 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461 continue;
1462 }
1463 }
1464 writeq(val64, &bar0->rx_queue_cfg);
1465
20346722 1466 /*
5e25b9dd 1467 * Filling Tx round robin registers
b7c5678f 1468 * as per the number of FIFOs for equal scheduling priority
1da177e4 1469 */
5e25b9dd
K		 1470 switch (config->tx_fifo_num) {
1471 case 1:
b7c5678f 1472 val64 = 0x0;
5e25b9dd
K		 1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1478 break;
1479 case 2:
b7c5678f 1480 val64 = 0x0001000100010001ULL;
5e25b9dd 1481 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1485 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 3:
b7c5678f 1489 val64 = 0x0001020001020001ULL;
5e25b9dd 1490 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1491 val64 = 0x0200010200010200ULL;
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1493 val64 = 0x0102000102000102ULL;
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1495 val64 = 0x0001020001020001ULL;
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1497 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 4:
b7c5678f 1501 val64 = 0x0001020300010203ULL;
5e25b9dd 1502 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1506 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 5:
b7c5678f 1510 val64 = 0x0001020304000102ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1512 val64 = 0x0304000102030400ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1514 val64 = 0x0102030400010203ULL;
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1516 val64 = 0x0400010203040001ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1518 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1519 writeq(val64, &bar0->tx_w_round_robin_4);
1520 break;
1521 case 6:
b7c5678f 1522 val64 = 0x0001020304050001ULL;
5e25b9dd 1523 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1524 val64 = 0x0203040500010203ULL;
5e25b9dd 1525 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1526 val64 = 0x0405000102030405ULL;
5e25b9dd 1527 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1528 val64 = 0x0001020304050001ULL;
5e25b9dd 1529 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1530 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1531 writeq(val64, &bar0->tx_w_round_robin_4);
1532 break;
1533 case 7:
b7c5678f 1534 val64 = 0x0001020304050600ULL;
5e25b9dd 1535 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1536 val64 = 0x0102030405060001ULL;
5e25b9dd 1537 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1538 val64 = 0x0203040506000102ULL;
5e25b9dd 1539 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1540 val64 = 0x0304050600010203ULL;
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1542 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1543 writeq(val64, &bar0->tx_w_round_robin_4);
1544 break;
1545 case 8:
b7c5678f 1546 val64 = 0x0001020304050607ULL;
5e25b9dd 1547 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1551 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 }
1555
b41477f3 1556 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1557 val64 = readq(&bar0->tx_fifo_partition_0);
1558 val64 |= (TX_FIFO_PARTITION_EN);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1560
5e25b9dd 1561 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1562 * number of Rings and steering based on QoS with
1563 * equal priority.
1564 */
5e25b9dd
K		 1565 switch (config->rx_ring_num) {
1566 case 1:
0425b46a
SH		 1567 val64 = 0x0;
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1573
5e25b9dd
K		 1574 val64 = 0x8080808080808080ULL;
1575 writeq(val64, &bar0->rts_qos_steering);
1576 break;
1577 case 2:
0425b46a 1578 val64 = 0x0001000100010001ULL;
5e25b9dd 1579 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1580 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1583 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1584 writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586 val64 = 0x8080808040404040ULL;
1587 writeq(val64, &bar0->rts_qos_steering);
1588 break;
1589 case 3:
0425b46a 1590 val64 = 0x0001020001020001ULL;
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1592 val64 = 0x0200010200010200ULL;
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1594 val64 = 0x0102000102000102ULL;
5e25b9dd 1595 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1596 val64 = 0x0001020001020001ULL;
5e25b9dd 1597 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1598 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1599 writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601 val64 = 0x8080804040402020ULL;
1602 writeq(val64, &bar0->rts_qos_steering);
1603 break;
1604 case 4:
0425b46a 1605 val64 = 0x0001020300010203ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1607 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1610 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1611 writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613 val64 = 0x8080404020201010ULL;
1614 writeq(val64, &bar0->rts_qos_steering);
1615 break;
1616 case 5:
0425b46a 1617 val64 = 0x0001020304000102ULL;
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1619 val64 = 0x0304000102030400ULL;
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1621 val64 = 0x0102030400010203ULL;
5e25b9dd 1622 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1623 val64 = 0x0400010203040001ULL;
5e25b9dd 1624 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1625 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1626 writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628 val64 = 0x8080404020201008ULL;
1629 writeq(val64, &bar0->rts_qos_steering);
1630 break;
1631 case 6:
0425b46a 1632 val64 = 0x0001020304050001ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1634 val64 = 0x0203040500010203ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1636 val64 = 0x0405000102030405ULL;
5e25b9dd 1637 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1638 val64 = 0x0001020304050001ULL;
5e25b9dd 1639 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1640 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1641 writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643 val64 = 0x8080404020100804ULL;
1644 writeq(val64, &bar0->rts_qos_steering);
1645 break;
1646 case 7:
0425b46a 1647 val64 = 0x0001020304050600ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1649 val64 = 0x0102030405060001ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1651 val64 = 0x0203040506000102ULL;
5e25b9dd 1652 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1653 val64 = 0x0304050600010203ULL;
5e25b9dd 1654 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1655 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1656 writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658 val64 = 0x8080402010080402ULL;
1659 writeq(val64, &bar0->rts_qos_steering);
1660 break;
1661 case 8:
0425b46a 1662 val64 = 0x0001020304050607ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1664 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1667 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1668 writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670 val64 = 0x8040201008040201ULL;
1671 writeq(val64, &bar0->rts_qos_steering);
1672 break;
1673 }
1da177e4
LT		 1674
1675 /* UDP Fix */
1676 val64 = 0;
20346722 1677 for (i = 0; i < 8; i++)
1da177e4
LT		 1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1679
5e25b9dd
K		 1680 /* Set the default rts frame length for the rings configured */
1681 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682 for (i = 0 ; i < config->rx_ring_num ; i++)
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685 /* Set the frame length for the configured rings
1686 * desired by the user
1687 */
1688 for (i = 0; i < config->rx_ring_num; i++) {
1689 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690 * specified frame length steering.
1691 * If the user provides the frame length then program
1692 * the rts_frm_len register for those values or else
1693 * leave it as it is.
1694 */
1695 if (rts_frm_len[i] != 0) {
1696 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1697 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1698 }
1699 }
8a4bdbaa 1700
9fc93a41
SS		 1701 /* Disable differentiated services steering logic */
1702 for (i = 0; i < 64; i++) {
1703 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1704 DBG_PRINT(ERR_DBG,
1705 "%s: rts_ds_steer failed on codepoint %d\n",
1706 dev->name, i);
9f74ffde 1707 return -ENODEV;
9fc93a41
SS		 1708 }
1709 }
1710
20346722 1711 /* Program statistics memory */
1da177e4 1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1713
541ae68f
K		 1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = STAT_BC(0x320);
1716 writeq(val64, &bar0->stat_byte_cnt);
1717 }
1718
20346722 1719 /*
1da177e4
LT		 1720 * Initializing the sampling rate for the device to calculate the
1721 * bandwidth utilization.
1722 */
1723 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1724 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1725 writeq(val64, &bar0->mac_link_util);
1726
20346722
K		 1727 /*
1728 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1729 * Scheme.
1730 */
1da177e4 1731
b7c5678f
RV		 1732 /* Initialize TTI */
1733 if (SUCCESS != init_tti(nic, nic->last_link_state))
1734 return -ENODEV;
1da177e4 1735
8a4bdbaa
SS		 1736 /* RTI Initialization */
1737 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1738 /*
8a4bdbaa
SS		 1739 * Programmed to generate Apprx 500 Intrs per
1740 * second
1741 */
1742 int count = (nic->config.bus_speed * 125)/4;
1743 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744 } else
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1747 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1750
1751 writeq(val64, &bar0->rti_data1_mem);
1752
1753 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1758 else
d44570e4
JP		 1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1761 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1762
8a4bdbaa 1763 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1764 val64 = RTI_CMD_MEM_WE |
1765 RTI_CMD_MEM_STROBE_NEW_CMD |
1766 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1767 writeq(val64, &bar0->rti_command_mem);
1da177e4 1768
8a4bdbaa
SS		 1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
f957bcf0 1777 while (true) {
8a4bdbaa
SS		 1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
b6e3f982 1781
8a4bdbaa 1782 if (time > 10) {
9e39f7c5 1783 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1784 dev->name);
9f74ffde 1785 return -ENODEV;
b6e3f982 1786 }
8a4bdbaa
SS		 1787 time++;
1788 msleep(50);
1da177e4 1789 }
1da177e4
LT		 1790 }
1791
20346722
K		 1792 /*
1793 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
509a2671 1800 add = &bar0->mac_cfg;
1da177e4
LT		 1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
7d3d0439
RA		 1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
20346722
K		 1822 /*
1823 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
20346722 1831 /*
1da177e4
LT		 1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
d44570e4
JP		 1839 val64 |= (((u64)0xFF00 |
1840 nic->mac_control.mc_pause_threshold_q0q3)
1841 << (i * 2 * 8));
1da177e4
LT		 1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845 val64 = 0;
1846 for (i = 0; i < 4; i++) {
d44570e4
JP		 1847 val64 |= (((u64)0xFF00 |
1848 nic->mac_control.mc_pause_threshold_q4q7)
1849 << (i * 2 * 8));
1da177e4
LT		 1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
20346722
K		 1853 /*
1854 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1855 * exceeded the limit pointed by shared_splits
1856 */
1857 val64 = readq(&bar0->pic_control);
1858 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859 writeq(val64, &bar0->pic_control);
1860
863c11a9
AR		 1861 if (nic->config.bus_speed == 266) {
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1865 }
1866
541ae68f
K		 1867 /*
1868 * Programming the Herc to split every write transaction
1869 * that does not start on an ADB to reduce disconnects.
1870 */
1871 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1872 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
b7b5a128 1876 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1877 writeq(val64, &bar0->pic_control2);
541ae68f 1878 }
c92ca04b
AR		 1879 if (strstr(nic->product_name, "CX4")) {
1880 val64 = TMAC_AVG_IPG(0x17);
1881 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1882 }
1883
1da177e4
LT		 1884 return SUCCESS;
1885}
a371a07d
K		 1886#define LINK_UP_DOWN_INTERRUPT 1
1887#define MAC_RMAC_ERR_TIMER 2
1888
1ee6dd77 1889static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1890{
1891 if (nic->device_type == XFRAME_II_DEVICE)
1892 return LINK_UP_DOWN_INTERRUPT;
1893 else
1894 return MAC_RMAC_ERR_TIMER;
1895}
8116f3cf 1896
9caab458
SS		 1897/**
1898 * do_s2io_write_bits - update alarm bits in alarm register
1899 * @value: alarm bits
1900 * @flag: interrupt status
1901 * @addr: address value
1902 * Description: update alarm bits in alarm register
1903 * Return Value:
1904 * NONE.
1905 */
1906static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907{
1908 u64 temp64;
1909
1910 temp64 = readq(addr);
1911
d44570e4
JP		 1912 if (flag == ENABLE_INTRS)
1913 temp64 &= ~((u64)value);
9caab458 1914 else
d44570e4 1915 temp64 |= ((u64)value);
9caab458
SS		 1916 writeq(temp64, addr);
1917}
1da177e4 1918
43b7c451 1919static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1920{
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922 register u64 gen_int_mask = 0;
01e16faa 1923 u64 interruptible;
9caab458 1924
01e16faa 1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1926 if (mask & TX_DMA_INTR) {
9caab458
SS		 1927 gen_int_mask |= TXDMA_INT_M;
1928
1929 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1930 TXDMA_PCC_INT | TXDMA_TTI_INT |
1931 TXDMA_LSO_INT | TXDMA_TPA_INT |
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1933
1934 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1935 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937 &bar0->pfc_err_mask);
9caab458
SS		 1938
1939 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1940 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1942
1943 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1944 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945 PCC_N_SERR | PCC_6_COF_OV_ERR |
1946 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948 PCC_TXB_ECC_SG_ERR,
1949 flag, &bar0->pcc_err_mask);
9caab458
SS		 1950
1951 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1953
1954 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1955 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957 flag, &bar0->lso_err_mask);
9caab458
SS		 1958
1959 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1960 flag, &bar0->tpa_err_mask);
9caab458
SS		 1961
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1963 }
1964
1965 if (mask & TX_MAC_INTR) {
1966 gen_int_mask |= TXMAC_INT_M;
1967 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1968 &bar0->mac_int_mask);
9caab458 1969 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1970 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1973 }
1974
1975 if (mask & TX_XGXS_INTR) {
1976 gen_int_mask |= TXXGXS_INT_M;
1977 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1978 &bar0->xgxs_int_mask);
9caab458 1979 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1980 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1982 }
1983
1984 if (mask & RX_DMA_INTR) {
1985 gen_int_mask |= RXDMA_INT_M;
1986 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1987 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988 flag, &bar0->rxdma_int_mask);
9caab458 1989 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1990 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1993 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1994 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996 &bar0->prc_pcix_err_mask);
9caab458 1997 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1998 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999 &bar0->rpa_err_mask);
9caab458 2000 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2001 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003 RDA_FRM_ECC_SG_ERR |
2004 RDA_MISC_ERR|RDA_PCIX_ERR,
2005 flag, &bar0->rda_err_mask);
9caab458 2006 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2007 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008 flag, &bar0->rti_err_mask);
9caab458
SS		 2009 }
2010
2011 if (mask & RX_MAC_INTR) {
2012 gen_int_mask |= RXMAC_INT_M;
2013 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2014 &bar0->mac_int_mask);
2015 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2018 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020 do_s2io_write_bits(interruptible,
d44570e4 2021 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2022 }
2023
d44570e4 2024 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2025 gen_int_mask |= RXXGXS_INT_M;
2026 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2027 &bar0->xgxs_int_mask);
9caab458 2028 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2029 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2030 }
2031
2032 if (mask & MC_INTR) {
2033 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2034 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035 flag, &bar0->mc_int_mask);
9caab458 2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
9caab458
SS		 2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044}
d44570e4 2045
20346722
K		 2046/**
2047 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2048 * @nic: device private variable,
2049 * @mask: A mask indicating which Intr block must be modified and,
2050 * @flag: A flag indicating whether to enable or disable the Intrs.
2051 * Description: This function will either disable or enable the interrupts
20346722
K		 2052 * depending on the flag argument. The mask argument can be used to
2053 * enable/disable any Intr block.
1da177e4
LT		 2054 * Return Value: NONE.
2055 */
2056
2057static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058{
1ee6dd77 2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2060 register u64 temp64 = 0, intr_mask = 0;
2061
2062 intr_mask = nic->general_int_mask;
1da177e4
LT		 2063
2064 /* Top level interrupt classification */
2065 /* PIC Interrupts */
9caab458 2066 if (mask & TX_PIC_INTR) {
1da177e4 2067 /* Enable PIC Intrs in the general intr mask register */
9caab458 2068 intr_mask |= TXPIC_INT_M;
1da177e4 2069 if (flag == ENABLE_INTRS) {
20346722 2070 /*
a371a07d 2071 * If Hercules adapter enable GPIO otherwise
b41477f3 2072 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2073 * interrupts for now.
2074 * TODO
1da177e4 2075 */
a371a07d 2076 if (s2io_link_fault_indication(nic) ==
d44570e4 2077 LINK_UP_DOWN_INTERRUPT) {
9caab458 2078 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2079 &bar0->pic_int_mask);
9caab458 2080 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2081 &bar0->gpio_int_mask);
9caab458 2082 } else
a371a07d 2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2084 } else if (flag == DISABLE_INTRS) {
20346722
K		 2085 /*
2086 * Disable PIC Intrs in the general
2087 * intr mask register
1da177e4
LT		 2088 */
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2090 }
2091 }
2092
1da177e4
LT		 2093 /* Tx traffic interrupts */
2094 if (mask & TX_TRAFFIC_INTR) {
9caab458 2095 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2096 if (flag == ENABLE_INTRS) {
20346722 2097 /*
1da177e4 2098 * Enable all the Tx side interrupts
20346722 2099 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2100 */
2101 writeq(0x0, &bar0->tx_traffic_mask);
2102 } else if (flag == DISABLE_INTRS) {
20346722
K		 2103 /*
2104 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2105 * register.
2106 */
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2108 }
2109 }
2110
2111 /* Rx traffic interrupts */
2112 if (mask & RX_TRAFFIC_INTR) {
9caab458 2113 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2114 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2115 /* writing 0 Enables all 8 RX interrupt levels */
2116 writeq(0x0, &bar0->rx_traffic_mask);
2117 } else if (flag == DISABLE_INTRS) {
20346722
K		 2118 /*
2119 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2120 * register.
2121 */
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2123 }
2124 }
9caab458
SS		 2125
2126 temp64 = readq(&bar0->general_int_mask);
2127 if (flag == ENABLE_INTRS)
d44570e4 2128 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2129 else
2130 temp64 = DISABLE_ALL_INTRS;
2131 writeq(temp64, &bar0->general_int_mask);
2132
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2134}
2135
19a60522
SS		 2136/**
2137 * verify_pcc_quiescent- Checks for PCC quiescent state
2138 * Return: 1 If PCC is quiescence
2139 * 0 If PCC is not quiescence
2140 */
1ee6dd77 2141static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2142{
19a60522 2143 int ret = 0, herc;
1ee6dd77 2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2145 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2146
19a60522 2147 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2148
f957bcf0 2149 if (flag == false) {
44c10138 2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2152 ret = 1;
19a60522
SS		 2153 } else {
2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2155 ret = 1;
20346722
K		 2156 }
2157 } else {
44c10138 2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2160 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2161 ret = 1;
5e25b9dd
K		 2162 } else {
2163 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2164 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2165 ret = 1;
20346722
K		 2166 }
2167 }
2168
2169 return ret;
2170}
2171/**
2172 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2173 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2174 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2175 * differs and the calling function passes the input argument flag to
2176 * indicate this.
20346722 2177 * Return: 1 If xena is quiescence
1da177e4
LT		 2178 * 0 If Xena is not quiescence
2179 */
2180
1ee6dd77 2181static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2182{
19a60522 2183 int mode;
1ee6dd77 2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2185 u64 val64 = readq(&bar0->adapter_status);
2186 mode = s2io_verify_pci_mode(sp);
1da177e4 2187
19a60522 2188 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2189 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2193 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2197 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2201 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2205 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2209 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2213 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2217 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2218 return 0;
1da177e4
LT		 2219 }
2220
19a60522
SS		 2221 /*
2222 * In PCI 33 mode, the P_PLL is not used, and therefore,
2223 * the the P_PLL_LOCK bit in the adapter_status register will
2224 * not be asserted.
2225 */
2226 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2227 sp->device_type == XFRAME_II_DEVICE &&
2228 mode != PCI_MODE_PCI_33) {
9e39f7c5 2229 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2230 return 0;
2231 }
2232 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2233 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2234 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2235 return 0;
2236 }
2237 return 1;
1da177e4
LT		 2238}
2239
2240/**
2241 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
20346722 2243 * Description :
1da177e4
LT		 2244 * New procedure to clear mac address reading problems on Alpha platforms
2245 *
2246 */
2247
d44570e4 2248static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2249{
1ee6dd77 2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2251 u64 val64;
2252 int i = 0;
2253
2254 while (fix_mac[i] != END_SIGN) {
2255 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2256 udelay(10);
1da177e4
LT		 2257 val64 = readq(&bar0->gpio_control);
2258 }
2259}
2260
2261/**
20346722 2262 * start_nic - Turns the device on
1da177e4 2263 * @nic : device private variable.
20346722
K		 2264 * Description:
2265 * This function actually turns the device on. Before this function is
2266 * called,all Registers are configured from their reset states
2267 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2268 * calling this function, the device interrupts are cleared and the NIC is
2269 * literally switched on by writing into the adapter control register.
20346722 2270 * Return Value:
1da177e4
LT		 2271 * SUCCESS on success and -1 on failure.
2272 */
2273
2274static int start_nic(struct s2io_nic *nic)
2275{
1ee6dd77 2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2277 struct net_device *dev = nic->dev;
2278 register u64 val64 = 0;
20346722 2279 u16 subid, i;
ffb5df6c
JP		 2280 struct config_param *config = &nic->config;
2281 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2282
2283 /* PRC Initialization and configuration */
2284 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2285 struct ring_info *ring = &mac_control->rings[i];
2286
d44570e4 2287 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
1da177e4 2308
926930b2
SS		 2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2313 nic->vlan_strip_flag = 0;
926930b2
SS		 2314 }
2315
20346722 2316 /*
1da177e4
LT		 2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
20346722 2326 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
20346722
K		 2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
19a60522 2338 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340 "Adapter status reads: 0x%llx\n",
2341 dev->name, (unsigned long long)val64);
1da177e4
LT		 2342 return FAILURE;
2343 }
2344
20346722 2345 /*
1da177e4 2346 * With some switches, link might be already up at this point.
20346722
K		 2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
1da177e4
LT		 2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
c92ca04b
AR		 2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
1da177e4
LT		 2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
541ae68f
K		 2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
509a2671 2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2374 }
2375
1da177e4
LT		 2376 return SUCCESS;
2377}
fed5eccd
AR		 2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
d44570e4
JP		 2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382 struct TxD *txdlp, int get_off)
fed5eccd 2383{
1ee6dd77 2384 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2385 struct sk_buff *skb;
1ee6dd77 2386 struct TxD *txds;
fed5eccd
AR		 2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2fda096d 2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2391 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2393 txds++;
2394 }
2395
d44570e4 2396 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2397 if (!skb) {
1ee6dd77 2398 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2399 return NULL;
2400 }
d44570e4
JP		 2401 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2402 skb->len - skb->data_len, PCI_DMA_TODEVICE);
fed5eccd
AR		 2403 frg_cnt = skb_shinfo(skb)->nr_frags;
2404 if (frg_cnt) {
2405 txds++;
2406 for (j = 0; j < frg_cnt; j++, txds++) {
2407 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408 if (!txds->Buffer_Pointer)
2409 break;
d44570e4
JP		 2410 pci_unmap_page(nic->pdev,
2411 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2412 frag->size, PCI_DMA_TODEVICE);
2413 }
2414 }
d44570e4
JP		 2415 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416 return skb;
fed5eccd 2417}
1da177e4 2418
20346722
K		 2419/**
2420 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2421 * @nic : device private variable.
20346722 2422 * Description:
1da177e4 2423 * Free all queued Tx buffers.
20346722 2424 * Return Value: void
d44570e4 2425 */
1da177e4
LT		 2426
2427static void free_tx_buffers(struct s2io_nic *nic)
2428{
2429 struct net_device *dev = nic->dev;
2430 struct sk_buff *skb;
1ee6dd77 2431 struct TxD *txdp;
1da177e4 2432 int i, j;
fed5eccd 2433 int cnt = 0;
ffb5df6c
JP		 2434 struct config_param *config = &nic->config;
2435 struct mac_info *mac_control = &nic->mac_control;
2436 struct stat_block *stats = mac_control->stats_info;
2437 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2438
2439 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2440 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2442 unsigned long flags;
13d866a9
JP		 2443
2444 spin_lock_irqsave(&fifo->tx_lock, flags);
2445 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2447 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448 if (skb) {
ffb5df6c 2449 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2450 dev_kfree_skb(skb);
2451 cnt++;
1da177e4 2452 }
1da177e4
LT		 2453 }
2454 DBG_PRINT(INTR_DBG,
9e39f7c5 2455 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2456 dev->name, cnt, i);
13d866a9
JP		 2457 fifo->tx_curr_get_info.offset = 0;
2458 fifo->tx_curr_put_info.offset = 0;
2459 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2460 }
2461}
2462
20346722
K		 2463/**
2464 * stop_nic - To stop the nic
1da177e4 2465 * @nic ; device private variable.
20346722
K		 2466 * Description:
2467 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2468 * function does. This function is called to stop the device.
2469 * Return Value:
2470 * void.
2471 */
2472
2473static void stop_nic(struct s2io_nic *nic)
2474{
1ee6dd77 2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2476 register u64 val64 = 0;
5d3213cc 2477 u16 interruptible;
1da177e4
LT		 2478
2479 /* Disable all interrupts */
9caab458 2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2482 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
5d3213cc
AR		 2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2489}
2490
20346722
K		 2491/**
2492 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2493 * @ring_info: per ring structure
3f78d885
SH		 2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
20346722 2497 * Description:
1da177e4
LT		 2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2502 * 1. single buffer,
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
20346722
K		 2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2509 * supported.
2510 * Return Value:
2511 * SUCCESS on success or an appropriate -ve value on failure.
2512 */
8d8bb39b 2513static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2514 int from_card_up)
1da177e4 2515{
1da177e4 2516 struct sk_buff *skb;
1ee6dd77 2517 struct RxD_t *rxdp;
0425b46a 2518 int off, size, block_no, block_no1;
1da177e4 2519 u32 alloc_tab = 0;
20346722 2520 u32 alloc_cnt;
20346722 2521 u64 tmp;
1ee6dd77 2522 struct buffAdd *ba;
1ee6dd77 2523 struct RxD_t *first_rxdp = NULL;
363dc367 2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2525 int rxd_index = 0;
6d517a27
VP		 2526 struct RxD1 *rxdp1;
2527 struct RxD3 *rxdp3;
ffb5df6c 2528 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2529
0425b46a 2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2531
0425b46a 2532 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2533 while (alloc_tab < alloc_cnt) {
0425b46a 2534 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2535
0425b46a
SH		 2536 off = ring->rx_curr_put_info.offset;
2537
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540 rxd_index = off + 1;
2541 if (block_no)
2542 rxd_index += (block_no * ring->rxd_count);
da6971d8 2543
7d2e3cb7 2544 if ((block_no == block_no1) &&
d44570e4
JP		 2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
9e39f7c5
JP		 2547 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548 ring->dev->name);
1da177e4
LT		 2549 goto end;
2550 }
0425b46a
SH		 2551 if (off && (off == ring->rxd_count)) {
2552 ring->rx_curr_put_info.block_index++;
2553 if (ring->rx_curr_put_info.block_index ==
d44570e4 2554 ring->block_count)
0425b46a
SH		 2555 ring->rx_curr_put_info.block_index = 0;
2556 block_no = ring->rx_curr_put_info.block_index;
2557 off = 0;
2558 ring->rx_curr_put_info.offset = off;
2559 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2560 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2561 ring->dev->name, rxdp);
2562
1da177e4 2563 }
c9fcbf47 2564
da6971d8 2565 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2566 ((ring->rxd_mode == RXD_MODE_3B) &&
2567 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2568 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2569 goto end;
2570 }
da6971d8 2571 /* calculate size of skb based on ring mode */
d44570e4
JP		 2572 size = ring->mtu +
2573 HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2575 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2576 size += NET_IP_ALIGN;
da6971d8 2577 else
0425b46a 2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2579
da6971d8
AR		 2580 /* allocate skb */
2581 skb = dev_alloc_skb(size);
d44570e4 2582 if (!skb) {
9e39f7c5
JP		 2583 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584 ring->dev->name);
303bcb4b
K		 2585 if (first_rxdp) {
2586 wmb();
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588 }
ffb5df6c 2589 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2590
da6971d8
AR		 2591 return -ENOMEM ;
2592 }
ffb5df6c 2593 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2594
2595 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2596 /* 1 buffer mode - normal operation mode */
d44570e4 2597 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2598 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2599 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2600 rxdp1->Buffer0_ptr =
2601 pci_map_single(ring->pdev, skb->data,
2602 size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
8d8bb39b 2604 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2605 rxdp1->Buffer0_ptr))
491abf25
VP		 2606 goto pci_map_failed;
2607
8a4bdbaa 2608 rxdp->Control_2 =
491976b2 2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2610 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2612 /*
6d517a27
VP		 2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
da6971d8 2615 * byte aligned receive buffers.
da6971d8
AR		 2616 */
2617
d44570e4 2618 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2619 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2622 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2623 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2626
0425b46a 2627 ba = &ring->ba[block_no][off];
da6971d8 2628 skb_reserve(skb, BUF0_LEN);
d44570e4 2629 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
27a884dc 2633 skb_reset_tail_pointer(skb);
da6971d8 2634
3f78d885 2635 if (from_card_up) {
6d517a27 2636 rxdp3->Buffer0_ptr =
d44570e4
JP		 2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN,
2639 PCI_DMA_FROMDEVICE);
2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
3f78d885
SH		 2642 goto pci_map_failed;
2643 } else
0425b46a 2644 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2645 (dma_addr_t)rxdp3->Buffer0_ptr,
2646 BUF0_LEN,
2647 PCI_DMA_FROMDEVICE);
491abf25 2648
da6971d8 2649 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2650 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2651 /* Two buffer mode */
2652
2653 /*
6aa20a22 2654 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2655 * L4 payload
2656 */
d44570e4
JP		 2657 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658 skb->data,
2659 ring->mtu + 4,
2660 PCI_DMA_FROMDEVICE);
da6971d8 2661
8d8bb39b 2662 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2663 rxdp3->Buffer2_ptr))
491abf25
VP		 2664 goto pci_map_failed;
2665
3f78d885 2666 if (from_card_up) {
0425b46a
SH		 2667 rxdp3->Buffer1_ptr =
2668 pci_map_single(ring->pdev,
d44570e4
JP		 2669 ba->ba_1,
2670 BUF1_LEN,
2671 PCI_DMA_FROMDEVICE);
0425b46a 2672
8d8bb39b 2673 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2674 rxdp3->Buffer1_ptr)) {
2675 pci_unmap_single(ring->pdev,
2676 (dma_addr_t)(unsigned long)
2677 skb->data,
2678 ring->mtu + 4,
2679 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2680 goto pci_map_failed;
2681 }
75c30b13 2682 }
da6971d8
AR		 2683 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2685 (ring->mtu + 4);
da6971d8 2686 }
b7b5a128 2687 rxdp->Control_2 |= s2BIT(0);
0425b46a 2688 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2689 }
303bcb4b
K		 2690 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2692 off++;
0425b46a 2693 if (off == (ring->rxd_count + 1))
da6971d8 2694 off = 0;
0425b46a 2695 ring->rx_curr_put_info.offset = off;
20346722 2696
da6971d8 2697 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2698 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699 if (first_rxdp) {
2700 wmb();
2701 first_rxdp->Control_1 |= RXD_OWN_XENA;
2702 }
2703 first_rxdp = rxdp;
2704 }
0425b46a 2705 ring->rx_bufs_left += 1;
1da177e4
LT		 2706 alloc_tab++;
2707 }
2708
d44570e4 2709end:
303bcb4b
K		 2710 /* Transfer ownership of first descriptor to adapter just before
2711 * exiting. Before that, use memory barrier so that ownership
2712 * and other fields are seen by adapter correctly.
2713 */
2714 if (first_rxdp) {
2715 wmb();
2716 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717 }
2718
1da177e4 2719 return SUCCESS;
d44570e4 2720
491abf25 2721pci_map_failed:
ffb5df6c
JP		 2722 swstats->pci_map_fail_cnt++;
2723 swstats->mem_freed += skb->truesize;
491abf25
VP		 2724 dev_kfree_skb_irq(skb);
2725 return -ENOMEM;
1da177e4
LT		 2726}
2727
da6971d8
AR		 2728static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729{
2730 struct net_device *dev = sp->dev;
2731 int j;
2732 struct sk_buff *skb;
1ee6dd77 2733 struct RxD_t *rxdp;
1ee6dd77 2734 struct buffAdd *ba;
6d517a27
VP		 2735 struct RxD1 *rxdp1;
2736 struct RxD3 *rxdp3;
ffb5df6c
JP		 2737 struct mac_info *mac_control = &sp->mac_control;
2738 struct stat_block *stats = mac_control->stats_info;
2739 struct swStat *swstats = &stats->sw_stat;
da6971d8 2740
da6971d8
AR		 2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745 if (!skb)
da6971d8 2746 continue;
da6971d8 2747 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2748 rxdp1 = (struct RxD1 *)rxdp;
2749 pci_unmap_single(sp->pdev,
2750 (dma_addr_t)rxdp1->Buffer0_ptr,
2751 dev->mtu +
2752 HEADER_ETHERNET_II_802_3_SIZE +
2753 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754 PCI_DMA_FROMDEVICE);
1ee6dd77 2755 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2756 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757 rxdp3 = (struct RxD3 *)rxdp;
2758 ba = &mac_control->rings[ring_no].ba[blk][j];
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer0_ptr,
2761 BUF0_LEN,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer1_ptr,
2765 BUF1_LEN,
2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev,
2768 (dma_addr_t)rxdp3->Buffer2_ptr,
2769 dev->mtu + 4,
2770 PCI_DMA_FROMDEVICE);
1ee6dd77 2771 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2772 }
ffb5df6c 2773 swstats->mem_freed += skb->truesize;
da6971d8 2774 dev_kfree_skb(skb);
0425b46a 2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2776 }
2777}
2778
1da177e4 2779/**
20346722 2780 * free_rx_buffers - Frees all Rx buffers
1da177e4 2781 * @sp: device private variable.
20346722 2782 * Description:
1da177e4
LT		 2783 * This function will free all Rx buffers allocated by host.
2784 * Return Value:
2785 * NONE.
2786 */
2787
2788static void free_rx_buffers(struct s2io_nic *sp)
2789{
2790 struct net_device *dev = sp->dev;
da6971d8 2791 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2792 struct config_param *config = &sp->config;
2793 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2794
2795 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2796 struct ring_info *ring = &mac_control->rings[i];
2797
da6971d8 2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2799 free_rxd_blk(sp, i, blk);
1da177e4 2800
13d866a9
JP		 2801 ring->rx_curr_put_info.block_index = 0;
2802 ring->rx_curr_get_info.block_index = 0;
2803 ring->rx_curr_put_info.offset = 0;
2804 ring->rx_curr_get_info.offset = 0;
2805 ring->rx_bufs_left = 0;
9e39f7c5 2806 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2807 dev->name, buf_cnt, i);
2808 }
2809}
2810
8d8bb39b 2811static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2812{
8d8bb39b 2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2814 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815 ring->dev->name);
f61e0a35
SH		 2816 }
2817 return 0;
2818}
2819
1da177e4
LT		 2820/**
2821 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2822 * @napi : pointer to the napi structure.
20346722 2823 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
f61e0a35 2833static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2834{
f61e0a35
SH		 2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
f61e0a35 2837 int pkts_processed = 0;
1a79d1c3
AV		 2838 u8 __iomem *addr = NULL;
2839 u8 val8 = 0;
4cf1653a 2840 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2842 int budget_org = budget;
1da177e4 2843
f61e0a35
SH		 2844 if (unlikely(!is_s2io_card_up(nic)))
2845 return 0;
1da177e4 2846
f61e0a35 2847 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2848 s2io_chk_rx_buffers(nic, ring);
1da177e4 2849
f61e0a35 2850 if (pkts_processed < budget_org) {
288379f0 2851 napi_complete(napi);
f61e0a35 2852 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2854 addr += 7 - ring->ring_no;
2855 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856 writeb(val8, addr);
2857 val8 = readb(addr);
1da177e4 2858 }
f61e0a35
SH		 2859 return pkts_processed;
2860}
d44570e4 2861
f61e0a35
SH		 2862static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863{
2864 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2865 int pkts_processed = 0;
2866 int ring_pkts_processed, i;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868 int budget_org = budget;
ffb5df6c
JP		 2869 struct config_param *config = &nic->config;
2870 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
1da177e4 2875 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2876 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2877 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2878 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2879 pkts_processed += ring_pkts_processed;
2880 budget -= ring_pkts_processed;
2881 if (budget <= 0)
1da177e4 2882 break;
1da177e4 2883 }
f61e0a35 2884 if (pkts_processed < budget_org) {
288379f0 2885 napi_complete(napi);
f61e0a35
SH		 2886 /* Re enable the Rx interrupts for the ring */
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2889 }
2890 return pkts_processed;
1da177e4 2891}
20346722 2892
b41477f3 2893#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2894/**
b41477f3 2895 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2896 * @dev : pointer to the device structure.
2897 * Description:
b41477f3
AR		 2898 * This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
612eff0e 2902 */
612eff0e
BH		 2903static void s2io_netpoll(struct net_device *dev)
2904{
4cf1653a 2905 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2907 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2908 int i;
ffb5df6c
JP		 2909 struct config_param *config = &nic->config;
2910 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2911
d796fdb7
LV		 2912 if (pci_channel_offline(nic->pdev))
2913 return;
2914
612eff0e
BH		 2915 disable_irq(dev->irq);
2916
612eff0e 2917 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2918 writeq(val64, &bar0->tx_traffic_int);
2919
6aa20a22 2920 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2921 * run out of skbs and will fail and eventually netpoll application such
2922 * as netdump will fail.
2923 */
2924 for (i = 0; i < config->tx_fifo_num; i++)
2925 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2926
b41477f3 2927 /* check for received packet and indicate up to network */
13d866a9
JP		 2928 for (i = 0; i < config->rx_ring_num; i++) {
2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 rx_intr_handler(ring, 0);
2932 }
612eff0e
BH		 2933
2934 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2935 struct ring_info *ring = &mac_control->rings[i];
2936
2937 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2938 DBG_PRINT(INFO_DBG,
2939 "%s: Out of memory in Rx Netpoll!!\n",
2940 dev->name);
612eff0e
BH		 2941 break;
2942 }
2943 }
612eff0e
BH		 2944 enable_irq(dev->irq);
2945 return;
2946}
2947#endif
2948
20346722 2949/**
1da177e4 2950 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2951 * @ring_info: per ring structure.
2952 * @budget: budget for napi processing.
20346722
K		 2953 * Description:
2954 * If the interrupt is because of a received frame or if the
1da177e4 2955 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2956 * called. It picks out the RxD at which place the last Rx processing had
2957 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2958 * the offset.
2959 * Return Value:
f61e0a35 2960 * No. of napi packets processed.
1da177e4 2961 */
f61e0a35 2962static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2963{
c9fcbf47 2964 int get_block, put_block;
1ee6dd77
RB		 2965 struct rx_curr_get_info get_info, put_info;
2966 struct RxD_t *rxdp;
1da177e4 2967 struct sk_buff *skb;
f61e0a35 2968 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2969 int i;
d44570e4
JP		 2970 struct RxD1 *rxdp1;
2971 struct RxD3 *rxdp3;
7d3d0439 2972
20346722
K		 2973 get_info = ring_data->rx_curr_get_info;
2974 get_block = get_info.block_index;
1ee6dd77 2975 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2976 put_block = put_info.block_index;
da6971d8 2977 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2978
da6971d8 2979 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2980 /*
2981 * If your are next to put index then it's
2982 * FIFO full condition
2983 */
da6971d8
AR		 2984 if ((get_block == put_block) &&
2985 (get_info.offset + 1) == put_info.offset) {
0425b46a 2986 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2987 ring_data->dev->name);
da6971d8
AR		 2988 break;
2989 }
d44570e4 2990 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2991 if (skb == NULL) {
9e39f7c5 2992 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2993 ring_data->dev->name);
f61e0a35 2994 return 0;
1da177e4 2995 }
0425b46a 2996 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2997 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2998 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2999 rxdp1->Buffer0_ptr,
3000 ring_data->mtu +
3001 HEADER_ETHERNET_II_802_3_SIZE +
3002 HEADER_802_2_SIZE +
3003 HEADER_SNAP_SIZE,
3004 PCI_DMA_FROMDEVICE);
0425b46a 3005 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3006 rxdp3 = (struct RxD3 *)rxdp;
3007 pci_dma_sync_single_for_cpu(ring_data->pdev,
3008 (dma_addr_t)rxdp3->Buffer0_ptr,
3009 BUF0_LEN,
3010 PCI_DMA_FROMDEVICE);
3011 pci_unmap_single(ring_data->pdev,
3012 (dma_addr_t)rxdp3->Buffer2_ptr,
3013 ring_data->mtu + 4,
3014 PCI_DMA_FROMDEVICE);
da6971d8 3015 }
863c11a9 3016 prefetch(skb->data);
20346722
K		 3017 rx_osm_handler(ring_data, rxdp);
3018 get_info.offset++;
da6971d8
AR		 3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3021 rxds[get_info.offset].virt_addr;
0425b46a 3022 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3023 get_info.offset = 0;
da6971d8 3024 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3025 get_block++;
da6971d8
AR		 3026 if (get_block == ring_data->block_count)
3027 get_block = 0;
3028 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3029 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3030 }
1da177e4 3031
f61e0a35
SH		 3032 if (ring_data->nic->config.napi) {
3033 budget--;
3034 napi_pkts++;
3035 if (!budget)
0425b46a
SH		 3036 break;
3037 }
20346722 3038 pkt_cnt++;
1da177e4
LT		 3039 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3040 break;
3041 }
0425b46a 3042 if (ring_data->lro) {
7d3d0439 3043 /* Clear all LRO sessions before exiting */
d44570e4 3044 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3045 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3046 if (lro->in_use) {
0425b46a 3047 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3048 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3049 clear_lro_session(lro);
3050 }
3051 }
3052 }
d44570e4 3053 return napi_pkts;
1da177e4 3054}
20346722
K		 3055
3056/**
1da177e4
LT		 3057 * tx_intr_handler - Transmit interrupt handler
3058 * @nic : device private variable
20346722
K		 3059 * Description:
3060 * If an interrupt was raised to indicate DMA complete of the
3061 * Tx packet, this function is called. It identifies the last TxD
3062 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3063 * DMA'ed into the NICs internal memory.
3064 * Return Value:
3065 * NONE
3066 */
3067
1ee6dd77 3068static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3069{
1ee6dd77 3070 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3071 struct tx_curr_get_info get_info, put_info;
3a3d5756 3072 struct sk_buff *skb = NULL;
1ee6dd77 3073 struct TxD *txdlp;
3a3d5756 3074 int pkt_cnt = 0;
2fda096d 3075 unsigned long flags = 0;
f9046eb3 3076 u8 err_mask;
ffb5df6c
JP		 3077 struct stat_block *stats = nic->mac_control.stats_info;
3078 struct swStat *swstats = &stats->sw_stat;
1da177e4 3079
2fda096d 3080 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3081 return;
2fda096d 3082
20346722 3083 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3084 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3085 txdlp = (struct TxD *)
3086 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3087 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088 (get_info.offset != put_info.offset) &&
3089 (txdlp->Host_Control)) {
3090 /* Check for TxD errors */
3091 if (txdlp->Control_1 & TXD_T_CODE) {
3092 unsigned long long err;
3093 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3094 if (err & 0x1) {
ffb5df6c 3095 swstats->parity_err_cnt++;
bd1034f0 3096 }
491976b2
SH		 3097
3098 /* update t_code statistics */
f9046eb3 3099 err_mask = err >> 48;
d44570e4
JP		 3100 switch (err_mask) {
3101 case 2:
ffb5df6c 3102 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3103 break;
3104
d44570e4 3105 case 3:
ffb5df6c 3106 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3107 break;
3108
d44570e4 3109 case 7:
ffb5df6c 3110 swstats->tx_parity_err_cnt++;
491976b2
SH		 3111 break;
3112
d44570e4 3113 case 10:
ffb5df6c 3114 swstats->tx_link_loss_cnt++;
491976b2
SH		 3115 break;
3116
d44570e4 3117 case 15:
ffb5df6c 3118 swstats->tx_list_proc_err_cnt++;
491976b2 3119 break;
d44570e4 3120 }
20346722 3121 }
1da177e4 3122
fed5eccd 3123 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3124 if (skb == NULL) {
2fda096d 3125 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3126 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127 __func__);
20346722
K		 3128 return;
3129 }
3a3d5756 3130 pkt_cnt++;
20346722 3131
20346722 3132 /* Updating the statistics block */
dc56e634 3133 nic->dev->stats.tx_bytes += skb->len;
ffb5df6c 3134 swstats->mem_freed += skb->truesize;
20346722
K		 3135 dev_kfree_skb_irq(skb);
3136
3137 get_info.offset++;
863c11a9
AR		 3138 if (get_info.offset == get_info.fifo_len + 1)
3139 get_info.offset = 0;
d44570e4
JP		 3140 txdlp = (struct TxD *)
3141 fifo_data->list_info[get_info.offset].list_virt_addr;
3142 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3143 }
3144
3a3d5756 3145 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3146
3147 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3148}
3149
bd1034f0
AR		 3150/**
3151 * s2io_mdio_write - Function to write in to MDIO registers
3152 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3153 * @addr : address value
3154 * @value : data value
3155 * @dev : pointer to net_device structure
3156 * Description:
3157 * This function is used to write values to the MDIO registers
3158 * NONE
3159 */
d44570e4
JP		 3160static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3161 struct net_device *dev)
bd1034f0 3162{
d44570e4 3163 u64 val64;
4cf1653a 3164 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3165 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3166
d44570e4
JP		 3167 /* address transaction */
3168 val64 = MDIO_MMD_INDX_ADDR(addr) |
3169 MDIO_MMD_DEV_ADDR(mmd_type) |
3170 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3171 writeq(val64, &bar0->mdio_control);
3172 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173 writeq(val64, &bar0->mdio_control);
3174 udelay(100);
3175
d44570e4
JP		 3176 /* Data transaction */
3177 val64 = MDIO_MMD_INDX_ADDR(addr) |
3178 MDIO_MMD_DEV_ADDR(mmd_type) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_MDIO_DATA(value) |
3181 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
d44570e4
JP		 3187 val64 = MDIO_MMD_INDX_ADDR(addr) |
3188 MDIO_MMD_DEV_ADDR(mmd_type) |
3189 MDIO_MMS_PRT_ADDR(0x0) |
3190 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3191 writeq(val64, &bar0->mdio_control);
3192 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3193 writeq(val64, &bar0->mdio_control);
3194 udelay(100);
bd1034f0
AR		 3195}
3196
3197/**
3198 * s2io_mdio_read - Function to write in to MDIO registers
3199 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3200 * @addr : address value
3201 * @dev : pointer to net_device structure
3202 * Description:
3203 * This function is used to read values to the MDIO registers
3204 * NONE
3205 */
3206static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3207{
3208 u64 val64 = 0x0;
3209 u64 rval64 = 0x0;
4cf1653a 3210 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3211 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3212
3213 /* address transaction */
d44570e4
JP		 3214 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3215 | MDIO_MMD_DEV_ADDR(mmd_type)
3216 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3217 writeq(val64, &bar0->mdio_control);
3218 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64, &bar0->mdio_control);
3220 udelay(100);
3221
3222 /* Data transaction */
d44570e4
JP		 3223 val64 = MDIO_MMD_INDX_ADDR(addr) |
3224 MDIO_MMD_DEV_ADDR(mmd_type) |
3225 MDIO_MMS_PRT_ADDR(0x0) |
3226 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3227 writeq(val64, &bar0->mdio_control);
3228 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229 writeq(val64, &bar0->mdio_control);
3230 udelay(100);
3231
3232 /* Read the value from regs */
3233 rval64 = readq(&bar0->mdio_control);
3234 rval64 = rval64 & 0xFFFF0000;
3235 rval64 = rval64 >> 16;
3236 return rval64;
3237}
d44570e4 3238
bd1034f0
AR		 3239/**
3240 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3241 * @counter : counter value to be updated
bd1034f0
AR		 3242 * @flag : flag to indicate the status
3243 * @type : counter type
3244 * Description:
3245 * This function is to check the status of the xpak counters value
3246 * NONE
3247 */
3248
d44570e4
JP		 3249static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3250 u16 flag, u16 type)
bd1034f0
AR		 3251{
3252 u64 mask = 0x3;
3253 u64 val64;
3254 int i;
d44570e4 3255 for (i = 0; i < index; i++)
bd1034f0
AR		 3256 mask = mask << 0x2;
3257
d44570e4 3258 if (flag > 0) {
bd1034f0
AR		 3259 *counter = *counter + 1;
3260 val64 = *regs_stat & mask;
3261 val64 = val64 >> (index * 0x2);
3262 val64 = val64 + 1;
d44570e4
JP		 3263 if (val64 == 3) {
3264 switch (type) {
bd1034f0 3265 case 1:
9e39f7c5
JP		 3266 DBG_PRINT(ERR_DBG,
3267 "Take Xframe NIC out of service.\n");
3268 DBG_PRINT(ERR_DBG,
3269"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3270 break;
bd1034f0 3271 case 2:
9e39f7c5
JP		 3272 DBG_PRINT(ERR_DBG,
3273 "Take Xframe NIC out of service.\n");
3274 DBG_PRINT(ERR_DBG,
3275"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3276 break;
bd1034f0 3277 case 3:
9e39f7c5
JP		 3278 DBG_PRINT(ERR_DBG,
3279 "Take Xframe NIC out of service.\n");
3280 DBG_PRINT(ERR_DBG,
3281"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3282 break;
bd1034f0 3283 default:
d44570e4
JP		 3284 DBG_PRINT(ERR_DBG,
3285 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3286 }
3287 val64 = 0x0;
3288 }
3289 val64 = val64 << (index * 0x2);
3290 *regs_stat = (*regs_stat & (~mask)) | (val64);
3291
3292 } else {
3293 *regs_stat = *regs_stat & (~mask);
3294 }
3295}
3296
3297/**
3298 * s2io_updt_xpak_counter - Function to update the xpak counters
3299 * @dev : pointer to net_device struct
3300 * Description:
3301 * This function is to upate the status of the xpak counters value
3302 * NONE
3303 */
3304static void s2io_updt_xpak_counter(struct net_device *dev)
3305{
3306 u16 flag = 0x0;
3307 u16 type = 0x0;
3308 u16 val16 = 0x0;
3309 u64 val64 = 0x0;
3310 u64 addr = 0x0;
3311
4cf1653a 3312 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3313 struct stat_block *stats = sp->mac_control.stats_info;
3314 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3315
3316 /* Check the communication with the MDIO slave */
40239396 3317 addr = MDIO_CTRL1;
bd1034f0 3318 val64 = 0x0;
40239396 3319 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3320 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3321 DBG_PRINT(ERR_DBG,
3322 "ERR: MDIO slave access failed - Returned %llx\n",
3323 (unsigned long long)val64);
bd1034f0
AR		 3324 return;
3325 }
3326
40239396 3327 /* Check for the expected value of control reg 1 */
d44570e4 3328 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3329 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3330 "Returned: %llx- Expected: 0x%x\n",
40239396 3331 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3332 return;
3333 }
3334
3335 /* Loading the DOM register to MDIO register */
3336 addr = 0xA100;
40239396
BH		 3337 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3338 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3339
3340 /* Reading the Alarm flags */
3341 addr = 0xA070;
3342 val64 = 0x0;
40239396 3343 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3344
3345 flag = CHECKBIT(val64, 0x7);
3346 type = 1;
ffb5df6c
JP		 3347 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3348 &xstats->xpak_regs_stat,
d44570e4 3349 0x0, flag, type);
bd1034f0 3350
d44570e4 3351 if (CHECKBIT(val64, 0x6))
ffb5df6c 3352 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3353
3354 flag = CHECKBIT(val64, 0x3);
3355 type = 2;
ffb5df6c
JP		 3356 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3357 &xstats->xpak_regs_stat,
d44570e4 3358 0x2, flag, type);
bd1034f0 3359
d44570e4 3360 if (CHECKBIT(val64, 0x2))
ffb5df6c 3361 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3362
3363 flag = CHECKBIT(val64, 0x1);
3364 type = 3;
ffb5df6c
JP		 3365 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3366 &xstats->xpak_regs_stat,
d44570e4 3367 0x4, flag, type);
bd1034f0 3368
d44570e4 3369 if (CHECKBIT(val64, 0x0))
ffb5df6c 3370 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3371
3372 /* Reading the Warning flags */
3373 addr = 0xA074;
3374 val64 = 0x0;
40239396 3375 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3376
d44570e4 3377 if (CHECKBIT(val64, 0x7))
ffb5df6c 3378 xstats->warn_transceiver_temp_high++;
bd1034f0 3379
d44570e4 3380 if (CHECKBIT(val64, 0x6))
ffb5df6c 3381 xstats->warn_transceiver_temp_low++;
bd1034f0 3382
d44570e4 3383 if (CHECKBIT(val64, 0x3))
ffb5df6c 3384 xstats->warn_laser_bias_current_high++;
bd1034f0 3385
d44570e4 3386 if (CHECKBIT(val64, 0x2))
ffb5df6c 3387 xstats->warn_laser_bias_current_low++;
bd1034f0 3388
d44570e4 3389 if (CHECKBIT(val64, 0x1))
ffb5df6c 3390 xstats->warn_laser_output_power_high++;
bd1034f0 3391
d44570e4 3392 if (CHECKBIT(val64, 0x0))
ffb5df6c 3393 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3394}
3395
20346722 3396/**
1da177e4 3397 * wait_for_cmd_complete - waits for a command to complete.
20346722 3398 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3399 * s2io_nic structure.
20346722
K		 3400 * Description: Function that waits for a command to Write into RMAC
3401 * ADDR DATA registers to be completed and returns either success or
3402 * error depending on whether the command was complete or not.
1da177e4
LT		 3403 * Return value:
3404 * SUCCESS on success and FAILURE on failure.
3405 */
3406
9fc93a41 3407static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3408 int bit_state)
1da177e4 3409{
9fc93a41 3410 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3411 u64 val64;
3412
9fc93a41
SS		 3413 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3414 return FAILURE;
3415
3416 do {
c92ca04b 3417 val64 = readq(addr);
9fc93a41
SS		 3418 if (bit_state == S2IO_BIT_RESET) {
3419 if (!(val64 & busy_bit)) {
3420 ret = SUCCESS;
3421 break;
3422 }
3423 } else {
3424 if (!(val64 & busy_bit)) {
3425 ret = SUCCESS;
3426 break;
3427 }
1da177e4 3428 }
c92ca04b 3429
d44570e4 3430 if (in_interrupt())
9fc93a41 3431 mdelay(delay);
c92ca04b 3432 else
9fc93a41 3433 msleep(delay);
c92ca04b 3434
9fc93a41
SS		 3435 if (++cnt >= 10)
3436 delay = 50;
3437 } while (cnt < 20);
1da177e4
LT		 3438 return ret;
3439}
19a60522
SS		 3440/*
3441 * check_pci_device_id - Checks if the device id is supported
3442 * @id : device id
3443 * Description: Function to check if the pci device id is supported by driver.
3444 * Return value: Actual device id if supported else PCI_ANY_ID
3445 */
3446static u16 check_pci_device_id(u16 id)
3447{
3448 switch (id) {
3449 case PCI_DEVICE_ID_HERC_WIN:
3450 case PCI_DEVICE_ID_HERC_UNI:
3451 return XFRAME_II_DEVICE;
3452 case PCI_DEVICE_ID_S2IO_UNI:
3453 case PCI_DEVICE_ID_S2IO_WIN:
3454 return XFRAME_I_DEVICE;
3455 default:
3456 return PCI_ANY_ID;
3457 }
3458}
1da177e4 3459
20346722
K		 3460/**
3461 * s2io_reset - Resets the card.
1da177e4
LT		 3462 * @sp : private member of the device structure.
3463 * Description: Function to Reset the card. This function then also
20346722 3464 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3465 * the card reset also resets the configuration space.
3466 * Return value:
3467 * void.
3468 */
3469
d44570e4 3470static void s2io_reset(struct s2io_nic *sp)
1da177e4 3471{
1ee6dd77 3472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3473 u64 val64;
5e25b9dd 3474 u16 subid, pci_cmd;
19a60522
SS		 3475 int i;
3476 u16 val16;
491976b2
SH		 3477 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3478 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3479 struct stat_block *stats;
3480 struct swStat *swstats;
491976b2 3481
9e39f7c5 3482 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
d44570e4 3483 __func__, sp->dev->name);
1da177e4 3484
0b1f7ebe 3485 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3486 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3487
1da177e4
LT		 3488 val64 = SW_RESET_ALL;
3489 writeq(val64, &bar0->sw_reset);
d44570e4 3490 if (strstr(sp->product_name, "CX4"))
c92ca04b 3491 msleep(750);
19a60522
SS		 3492 msleep(250);
3493 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3494
19a60522
SS		 3495 /* Restore the PCI state saved during initialization. */
3496 pci_restore_state(sp->pdev);
b8a623bf 3497 pci_save_state(sp->pdev);
19a60522
SS		 3498 pci_read_config_word(sp->pdev, 0x2, &val16);
3499 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3500 break;
3501 msleep(200);
3502 }
1da177e4 3503
d44570e4
JP		 3504 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3505 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3506
3507 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3508
3509 s2io_init_pci(sp);
1da177e4 3510
20346722
K		 3511 /* Set swapper to enable I/O register access */
3512 s2io_set_swapper(sp);
3513
faa4f796
SH		 3514 /* restore mac_addr entries */
3515 do_s2io_restore_unicast_mc(sp);
3516
cc6e7c44
RA		 3517 /* Restore the MSIX table entries from local variables */
3518 restore_xmsi_data(sp);
3519
5e25b9dd 3520 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3521 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3522 /* Clear "detected parity error" bit */
303bcb4b 3523 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3524
303bcb4b
K		 3525 /* Clearing PCIX Ecc status register */
3526 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3527
303bcb4b 3528 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3529 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3530 }
5e25b9dd 3531
20346722 3532 /* Reset device statistics maintained by OS */
d44570e4 3533 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3534
ffb5df6c
JP		 3535 stats = sp->mac_control.stats_info;
3536 swstats = &stats->sw_stat;
3537
491976b2 3538 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3539 up_cnt = swstats->link_up_cnt;
3540 down_cnt = swstats->link_down_cnt;
3541 up_time = swstats->link_up_time;
3542 down_time = swstats->link_down_time;
3543 reset_cnt = swstats->soft_reset_cnt;
3544 mem_alloc_cnt = swstats->mem_allocated;
3545 mem_free_cnt = swstats->mem_freed;
3546 watchdog_cnt = swstats->watchdog_timer_cnt;
3547
3548 memset(stats, 0, sizeof(struct stat_block));
3549
491976b2 3550 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3551 swstats->link_up_cnt = up_cnt;
3552 swstats->link_down_cnt = down_cnt;
3553 swstats->link_up_time = up_time;
3554 swstats->link_down_time = down_time;
3555 swstats->soft_reset_cnt = reset_cnt;
3556 swstats->mem_allocated = mem_alloc_cnt;
3557 swstats->mem_freed = mem_free_cnt;
3558 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3559
1da177e4
LT		 3560 /* SXE-002: Configure link and activity LED to turn it off */
3561 subid = sp->pdev->subsystem_device;
541ae68f
K		 3562 if (((subid & 0xFF) >= 0x07) &&
3563 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3564 val64 = readq(&bar0->gpio_control);
3565 val64 |= 0x0000800000000000ULL;
3566 writeq(val64, &bar0->gpio_control);
3567 val64 = 0x0411040400000000ULL;
509a2671 3568 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3569 }
3570
541ae68f
K		 3571 /*
3572 * Clear spurious ECC interrupts that would have occured on
3573 * XFRAME II cards after reset.
3574 */
3575 if (sp->device_type == XFRAME_II_DEVICE) {
3576 val64 = readq(&bar0->pcc_err_reg);
3577 writeq(val64, &bar0->pcc_err_reg);
3578 }
3579
f957bcf0 3580 sp->device_enabled_once = false;
1da177e4
LT		 3581}
3582
3583/**
20346722
K		 3584 * s2io_set_swapper - to set the swapper controle on the card
3585 * @sp : private member of the device structure,
1da177e4 3586 * pointer to the s2io_nic structure.
20346722 3587 * Description: Function to set the swapper control on the card
1da177e4
LT		 3588 * correctly depending on the 'endianness' of the system.
3589 * Return value:
3590 * SUCCESS on success and FAILURE on failure.
3591 */
3592
d44570e4 3593static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3594{
3595 struct net_device *dev = sp->dev;
1ee6dd77 3596 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3597 u64 val64, valt, valr;
3598
20346722 3599 /*
1da177e4
LT		 3600 * Set proper endian settings and verify the same by reading
3601 * the PIF Feed-back register.
3602 */
3603
3604 val64 = readq(&bar0->pif_rd_swapper_fb);
3605 if (val64 != 0x0123456789ABCDEFULL) {
3606 int i = 0;
3607 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3608 0x8100008181000081ULL, /* FE=1, SE=0 */
3609 0x4200004242000042ULL, /* FE=0, SE=1 */
3610 0}; /* FE=0, SE=0 */
3611
d44570e4 3612 while (i < 4) {
1da177e4
LT		 3613 writeq(value[i], &bar0->swapper_ctrl);
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 == 0x0123456789ABCDEFULL)
3616 break;
3617 i++;
3618 }
3619 if (i == 4) {
9e39f7c5
JP		 3620 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3621 "feedback read %llx\n",
3622 dev->name, (unsigned long long)val64);
1da177e4
LT		 3623 return FAILURE;
3624 }
3625 valr = value[i];
3626 } else {
3627 valr = readq(&bar0->swapper_ctrl);
3628 }
3629
3630 valt = 0x0123456789ABCDEFULL;
3631 writeq(valt, &bar0->xmsi_address);
3632 val64 = readq(&bar0->xmsi_address);
3633
d44570e4 3634 if (val64 != valt) {
1da177e4
LT		 3635 int i = 0;
3636 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3637 0x0081810000818100ULL, /* FE=1, SE=0 */
3638 0x0042420000424200ULL, /* FE=0, SE=1 */
3639 0}; /* FE=0, SE=0 */
3640
d44570e4 3641 while (i < 4) {
1da177e4
LT		 3642 writeq((value[i] | valr), &bar0->swapper_ctrl);
3643 writeq(valt, &bar0->xmsi_address);
3644 val64 = readq(&bar0->xmsi_address);
d44570e4 3645 if (val64 == valt)
1da177e4
LT		 3646 break;
3647 i++;
3648 }
d44570e4 3649 if (i == 4) {
20346722 3650 unsigned long long x = val64;
9e39f7c5
JP		 3651 DBG_PRINT(ERR_DBG,
3652 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3653 return FAILURE;
3654 }
3655 }
3656 val64 = readq(&bar0->swapper_ctrl);
3657 val64 &= 0xFFFF000000000000ULL;
3658
d44570e4 3659#ifdef __BIG_ENDIAN
20346722
K		 3660 /*
3661 * The device by default set to a big endian format, so a
1da177e4
LT		 3662 * big endian driver need not set anything.
3663 */
3664 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3665 SWAPPER_CTRL_TXP_SE |
3666 SWAPPER_CTRL_TXD_R_FE |
3667 SWAPPER_CTRL_TXD_W_FE |
3668 SWAPPER_CTRL_TXF_R_FE |
3669 SWAPPER_CTRL_RXD_R_FE |
3670 SWAPPER_CTRL_RXD_W_FE |
3671 SWAPPER_CTRL_RXF_W_FE |
3672 SWAPPER_CTRL_XMSI_FE |
3673 SWAPPER_CTRL_STATS_FE |
3674 SWAPPER_CTRL_STATS_SE);
eaae7f72 3675 if (sp->config.intr_type == INTA)
cc6e7c44 3676 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3677 writeq(val64, &bar0->swapper_ctrl);
3678#else
20346722 3679 /*
1da177e4 3680 * Initially we enable all bits to make it accessible by the
20346722 3681 * driver, then we selectively enable only those bits that
1da177e4
LT		 3682 * we want to set.
3683 */
3684 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3685 SWAPPER_CTRL_TXP_SE |
3686 SWAPPER_CTRL_TXD_R_FE |
3687 SWAPPER_CTRL_TXD_R_SE |
3688 SWAPPER_CTRL_TXD_W_FE |
3689 SWAPPER_CTRL_TXD_W_SE |
3690 SWAPPER_CTRL_TXF_R_FE |
3691 SWAPPER_CTRL_RXD_R_FE |
3692 SWAPPER_CTRL_RXD_R_SE |
3693 SWAPPER_CTRL_RXD_W_FE |
3694 SWAPPER_CTRL_RXD_W_SE |
3695 SWAPPER_CTRL_RXF_W_FE |
3696 SWAPPER_CTRL_XMSI_FE |
3697 SWAPPER_CTRL_STATS_FE |
3698 SWAPPER_CTRL_STATS_SE);
eaae7f72 3699 if (sp->config.intr_type == INTA)
cc6e7c44 3700 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3701 writeq(val64, &bar0->swapper_ctrl);
3702#endif
3703 val64 = readq(&bar0->swapper_ctrl);
3704
20346722
K		 3705 /*
3706 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3707 * feedback register.
3708 */
3709 val64 = readq(&bar0->pif_rd_swapper_fb);
3710 if (val64 != 0x0123456789ABCDEFULL) {
3711 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3712 DBG_PRINT(ERR_DBG,
3713 "%s: Endian settings are wrong, feedback read %llx\n",
3714 dev->name, (unsigned long long)val64);
1da177e4
LT		 3715 return FAILURE;
3716 }
3717
3718 return SUCCESS;
3719}
3720
1ee6dd77 3721static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3722{
1ee6dd77 3723 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3724 u64 val64;
3725 int ret = 0, cnt = 0;
3726
3727 do {
3728 val64 = readq(&bar0->xmsi_access);
b7b5a128 3729 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3730 break;
3731 mdelay(1);
3732 cnt++;
d44570e4 3733 } while (cnt < 5);
cc6e7c44
RA		 3734 if (cnt == 5) {
3735 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3736 ret = 1;
3737 }
3738
3739 return ret;
3740}
3741
1ee6dd77 3742static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3743{
1ee6dd77 3744 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3745 u64 val64;
f61e0a35
SH		 3746 int i, msix_index;
3747
f61e0a35
SH		 3748 if (nic->device_type == XFRAME_I_DEVICE)
3749 return;
cc6e7c44 3750
d44570e4
JP		 3751 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3752 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3753 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3754 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3755 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3756 writeq(val64, &bar0->xmsi_access);
f61e0a35 3757 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3758 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3759 __func__, msix_index);
cc6e7c44
RA		 3760 continue;
3761 }
3762 }
3763}
3764
1ee6dd77 3765static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3766{
1ee6dd77 3767 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3768 u64 val64, addr, data;
f61e0a35
SH		 3769 int i, msix_index;
3770
3771 if (nic->device_type == XFRAME_I_DEVICE)
3772 return;
cc6e7c44
RA		 3773
3774 /* Store and display */
d44570e4
JP		 3775 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3776 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3777 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3778 writeq(val64, &bar0->xmsi_access);
f61e0a35 3779 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3780 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3781 __func__, msix_index);
cc6e7c44
RA		 3782 continue;
3783 }
3784 addr = readq(&bar0->xmsi_address);
3785 data = readq(&bar0->xmsi_data);
3786 if (addr && data) {
3787 nic->msix_info[i].addr = addr;
3788 nic->msix_info[i].data = data;
3789 }
3790 }
3791}
3792
1ee6dd77 3793static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3794{
1ee6dd77 3795 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3796 u64 rx_mat;
cc6e7c44
RA		 3797 u16 msi_control; /* Temp variable */
3798 int ret, i, j, msix_indx = 1;
4f870320 3799 int size;
ffb5df6c
JP		 3800 struct stat_block *stats = nic->mac_control.stats_info;
3801 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3802
4f870320 3803 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3804 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3805 if (!nic->entries) {
d44570e4
JP		 3806 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3807 __func__);
ffb5df6c 3808 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3809 return -ENOMEM;
3810 }
ffb5df6c 3811 swstats->mem_allocated += size;
f61e0a35 3812
4f870320 3813 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3814 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3815 if (!nic->s2io_entries) {
8a4bdbaa 3816 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3817 __func__);
ffb5df6c 3818 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3819 kfree(nic->entries);
ffb5df6c 3820 swstats->mem_freed
f61e0a35 3821 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3822 return -ENOMEM;
3823 }
ffb5df6c 3824 swstats->mem_allocated += size;
cc6e7c44 3825
ac731ab6
SH		 3826 nic->entries[0].entry = 0;
3827 nic->s2io_entries[0].entry = 0;
3828 nic->s2io_entries[0].in_use = MSIX_FLG;
3829 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3830 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3831
f61e0a35
SH		 3832 for (i = 1; i < nic->num_entries; i++) {
3833 nic->entries[i].entry = ((i - 1) * 8) + 1;
3834 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3835 nic->s2io_entries[i].arg = NULL;
3836 nic->s2io_entries[i].in_use = 0;
3837 }
3838
8a4bdbaa 3839 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3840 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3841 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3842 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3843 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3844 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3845 msix_indx += 8;
cc6e7c44 3846 }
8a4bdbaa 3847 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3848 readq(&bar0->rx_mat);
cc6e7c44 3849
f61e0a35 3850 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3851 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3852 if (ret) {
9e39f7c5 3853 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3854 kfree(nic->entries);
ffb5df6c
JP		 3855 swstats->mem_freed += nic->num_entries *
3856 sizeof(struct msix_entry);
cc6e7c44 3857 kfree(nic->s2io_entries);
ffb5df6c
JP		 3858 swstats->mem_freed += nic->num_entries *
3859 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3860 nic->entries = NULL;
3861 nic->s2io_entries = NULL;
3862 return -ENOMEM;
3863 }
3864
3865 /*
3866 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3867 * in the herc NIC. (Temp change, needs to be removed later)
3868 */
3869 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3870 msi_control |= 0x1; /* Enable MSI */
3871 pci_write_config_word(nic->pdev, 0x42, msi_control);
3872
3873 return 0;
3874}
3875
8abc4d5b 3876/* Handle software interrupt used during MSI(X) test */
33390a70 3877static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3878{
3879 struct s2io_nic *sp = dev_id;
3880
3881 sp->msi_detected = 1;
3882 wake_up(&sp->msi_wait);
3883
3884 return IRQ_HANDLED;
3885}
3886
3887/* Test interrupt path by forcing a a software IRQ */
33390a70 3888static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3889{
3890 struct pci_dev *pdev = sp->pdev;
3891 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3892 int err;
3893 u64 val64, saved64;
3894
3895 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3896 sp->name, sp);
8abc4d5b
SS		 3897 if (err) {
3898 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3899 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3900 return err;
3901 }
3902
d44570e4 3903 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3904 sp->msi_detected = 0;
3905
3906 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3907 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3908 val64 |= SCHED_INT_CTRL_TIMER_EN;
3909 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3910 writeq(val64, &bar0->scheduled_int_ctrl);
3911
3912 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3913
3914 if (!sp->msi_detected) {
3915 /* MSI(X) test failed, go back to INTx mode */
2450022a 3916 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3917 "using MSI(X) during test\n",
3918 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3919
3920 err = -EOPNOTSUPP;
3921 }
3922
3923 free_irq(sp->entries[1].vector, sp);
3924
3925 writeq(saved64, &bar0->scheduled_int_ctrl);
3926
3927 return err;
3928}
18b2b7bd
SH		 3929
3930static void remove_msix_isr(struct s2io_nic *sp)
3931{
3932 int i;
3933 u16 msi_control;
3934
f61e0a35 3935 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3936 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3937 int vector = sp->entries[i].vector;
3938 void *arg = sp->s2io_entries[i].arg;
3939 free_irq(vector, arg);
3940 }
3941 }
3942
3943 kfree(sp->entries);
3944 kfree(sp->s2io_entries);
3945 sp->entries = NULL;
3946 sp->s2io_entries = NULL;
3947
3948 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3949 msi_control &= 0xFFFE; /* Disable MSI */
3950 pci_write_config_word(sp->pdev, 0x42, msi_control);
3951
3952 pci_disable_msix(sp->pdev);
3953}
3954
3955static void remove_inta_isr(struct s2io_nic *sp)
3956{
3957 struct net_device *dev = sp->dev;
3958
3959 free_irq(sp->pdev->irq, dev);
3960}
3961
1da177e4
LT		 3962/* ********************************************************* *
3963 * Functions defined below concern the OS part of the driver *
3964 * ********************************************************* */
3965
20346722 3966/**
1da177e4
LT		 3967 * s2io_open - open entry point of the driver
3968 * @dev : pointer to the device structure.
3969 * Description:
3970 * This function is the open entry point of the driver. It mainly calls a
3971 * function to allocate Rx buffers and inserts them into the buffer
20346722 3972 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3973 * Return value:
3974 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3975 * file on failure.
3976 */
3977
ac1f60db 3978static int s2io_open(struct net_device *dev)
1da177e4 3979{
4cf1653a 3980 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3981 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3982 int err = 0;
3983
20346722
K		 3984 /*
3985 * Make sure you have link off by default every time
1da177e4
LT		 3986 * Nic is initialized
3987 */
3988 netif_carrier_off(dev);
0b1f7ebe 3989 sp->last_link_state = 0;
1da177e4
LT		 3990
3991 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3992 err = s2io_card_up(sp);
3993 if (err) {
1da177e4
LT		 3994 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3995 dev->name);
e6a8fee2 3996 goto hw_init_failed;
1da177e4
LT		 3997 }
3998
2fd37688 3999 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4000 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4001 s2io_card_down(sp);
20346722 4002 err = -ENODEV;
e6a8fee2 4003 goto hw_init_failed;
1da177e4 4004 }
3a3d5756 4005 s2io_start_all_tx_queue(sp);
1da177e4 4006 return 0;
20346722 4007
20346722 4008hw_init_failed:
eaae7f72 4009 if (sp->config.intr_type == MSI_X) {
491976b2 4010 if (sp->entries) {
cc6e7c44 4011 kfree(sp->entries);
ffb5df6c
JP		 4012 swstats->mem_freed += sp->num_entries *
4013 sizeof(struct msix_entry);
491976b2
SH		 4014 }
4015 if (sp->s2io_entries) {
cc6e7c44 4016 kfree(sp->s2io_entries);
ffb5df6c
JP		 4017 swstats->mem_freed += sp->num_entries *
4018 sizeof(struct s2io_msix_entry);
491976b2 4019 }
cc6e7c44 4020 }
20346722 4021 return err;
1da177e4
LT		 4022}
4023
4024/**
4025 * s2io_close -close entry point of the driver
4026 * @dev : device pointer.
4027 * Description:
4028 * This is the stop entry point of the driver. It needs to undo exactly
4029 * whatever was done by the open entry point,thus it's usually referred to
4030 * as the close function.Among other things this function mainly stops the
4031 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4032 * Return value:
4033 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4034 * file on failure.
4035 */
4036
ac1f60db 4037static int s2io_close(struct net_device *dev)
1da177e4 4038{
4cf1653a 4039 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4040 struct config_param *config = &sp->config;
4041 u64 tmp64;
4042 int offset;
cc6e7c44 4043
9f74ffde 4044 /* Return if the device is already closed *
d44570e4
JP		 4045 * Can happen when s2io_card_up failed in change_mtu *
4046 */
9f74ffde
SH		 4047 if (!is_s2io_card_up(sp))
4048 return 0;
4049
3a3d5756 4050 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4051 /* delete all populated mac entries */
4052 for (offset = 1; offset < config->max_mc_addr; offset++) {
4053 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4054 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4055 do_s2io_delete_unicast_mc(sp, tmp64);
4056 }
4057
e6a8fee2 4058 s2io_card_down(sp);
cc6e7c44 4059
1da177e4
LT		 4060 return 0;
4061}
4062
4063/**
4064 * s2io_xmit - Tx entry point of te driver
4065 * @skb : the socket buffer containing the Tx data.
4066 * @dev : device pointer.
4067 * Description :
4068 * This function is the Tx entry point of the driver. S2IO NIC supports
4069 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4070 * NOTE: when device cant queue the pkt,just the trans_start variable will
4071 * not be upadted.
4072 * Return value:
4073 * 0 on success & 1 on failure.
4074 */
4075
61357325 4076static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4077{
4cf1653a 4078 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4079 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4080 register u64 val64;
1ee6dd77
RB		 4081 struct TxD *txdp;
4082 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4083 unsigned long flags = 0;
be3a6b02 4084 u16 vlan_tag = 0;
2fda096d 4085 struct fifo_info *fifo = NULL;
6cfc482b 4086 int do_spin_lock = 1;
75c30b13 4087 int offload_type;
6cfc482b 4088 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4089 struct config_param *config = &sp->config;
4090 struct mac_info *mac_control = &sp->mac_control;
4091 struct stat_block *stats = mac_control->stats_info;
4092 struct swStat *swstats = &stats->sw_stat;
1da177e4 4093
20346722 4094 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4095
4096 if (unlikely(skb->len <= 0)) {
9e39f7c5 4097 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4098 dev_kfree_skb_any(skb);
6ed10654 4099 return NETDEV_TX_OK;
2fda096d 4100 }
491976b2 4101
92b84437 4102 if (!is_s2io_card_up(sp)) {
20346722 4103 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4104 dev->name);
20346722 4105 dev_kfree_skb(skb);
6ed10654 4106 return NETDEV_TX_OK;
1da177e4
LT		 4107 }
4108
4109 queue = 0;
3a3d5756 4110 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4111 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4112 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4113 if (skb->protocol == htons(ETH_P_IP)) {
4114 struct iphdr *ip;
4115 struct tcphdr *th;
4116 ip = ip_hdr(skb);
4117
4118 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4119 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4120 ip->ihl*4);
6cfc482b
SH		 4121
4122 if (ip->protocol == IPPROTO_TCP) {
4123 queue_len = sp->total_tcp_fifos;
4124 queue = (ntohs(th->source) +
d44570e4
JP		 4125 ntohs(th->dest)) &
4126 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4127 if (queue >= queue_len)
4128 queue = queue_len - 1;
4129 } else if (ip->protocol == IPPROTO_UDP) {
4130 queue_len = sp->total_udp_fifos;
4131 queue = (ntohs(th->source) +
d44570e4
JP		 4132 ntohs(th->dest)) &
4133 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4134 if (queue >= queue_len)
4135 queue = queue_len - 1;
4136 queue += sp->udp_fifo_idx;
4137 if (skb->len > 1024)
4138 enable_per_list_interrupt = 1;
4139 do_spin_lock = 0;
4140 }
4141 }
4142 }
4143 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4144 /* get fifo number based on skb->priority value */
4145 queue = config->fifo_mapping
d44570e4 4146 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4147 fifo = &mac_control->fifos[queue];
3a3d5756 4148
6cfc482b
SH		 4149 if (do_spin_lock)
4150 spin_lock_irqsave(&fifo->tx_lock, flags);
4151 else {
4152 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4153 return NETDEV_TX_LOCKED;
4154 }
be3a6b02 4155
3a3d5756
SH		 4156 if (sp->config.multiq) {
4157 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4158 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4159 return NETDEV_TX_BUSY;
4160 }
b19fa1fa 4161 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4162 if (netif_queue_stopped(dev)) {
4163 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4164 return NETDEV_TX_BUSY;
4165 }
4166 }
4167
d44570e4
JP		 4168 put_off = (u16)fifo->tx_curr_put_info.offset;
4169 get_off = (u16)fifo->tx_curr_get_info.offset;
4170 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4171
2fda096d 4172 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4173 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4174 if (txdp->Host_Control ||
d44570e4 4175 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4176 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4177 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4178 dev_kfree_skb(skb);
2fda096d 4179 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4180 return NETDEV_TX_OK;
1da177e4 4181 }
0b1f7ebe 4182
75c30b13 4183 offload_type = s2io_offload_type(skb);
75c30b13 4184 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4185 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4186 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4187 }
84fa7933 4188 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4189 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4190 TXD_TX_CKO_TCP_EN |
4191 TXD_TX_CKO_UDP_EN);
1da177e4 4192 }
fed5eccd
AR		 4193 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4194 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4195 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4196 if (enable_per_list_interrupt)
4197 if (put_off & (queue_len >> 5))
4198 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4199 if (vlan_tag) {
be3a6b02
K		 4200 txdp->Control_2 |= TXD_VLAN_ENABLE;
4201 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4202 }
4203
fed5eccd 4204 frg_len = skb->len - skb->data_len;
75c30b13 4205 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4206 int ufo_size;
4207
75c30b13 4208 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4209 ufo_size &= ~7;
4210 txdp->Control_1 |= TXD_UFO_EN;
4211 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4212 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4213#ifdef __BIG_ENDIAN
3459feb8 4214 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4215 fifo->ufo_in_band_v[put_off] =
d44570e4 4216 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4217#else
2fda096d 4218 fifo->ufo_in_band_v[put_off] =
d44570e4 4219 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4220#endif
2fda096d 4221 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4222 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4223 fifo->ufo_in_band_v,
4224 sizeof(u64),
4225 PCI_DMA_TODEVICE);
8d8bb39b 4226 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4227 goto pci_map_failed;
fed5eccd 4228 txdp++;
fed5eccd 4229 }
1da177e4 4230
d44570e4
JP		 4231 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4232 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4233 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4234 goto pci_map_failed;
4235
d44570e4 4236 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4237 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4238 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4239 txdp->Control_1 |= TXD_UFO_EN;
4240
4241 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4242 /* For fragmented SKB. */
4243 for (i = 0; i < frg_cnt; i++) {
4244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4245 /* A '0' length fragment will be ignored */
4246 if (!frag->size)
4247 continue;
1da177e4 4248 txdp++;
d44570e4
JP		 4249 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4250 frag->page_offset,
4251 frag->size,
4252 PCI_DMA_TODEVICE);
efd51b5c 4253 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4254 if (offload_type == SKB_GSO_UDP)
fed5eccd 4255 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4256 }
4257 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4258
75c30b13 4259 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4260 frg_cnt++; /* as Txd0 was used for inband header */
4261
1da177e4 4262 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4263 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4264 writeq(val64, &tx_fifo->TxDL_Pointer);
4265
4266 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4267 TX_FIFO_LAST_LIST);
75c30b13 4268 if (offload_type)
fed5eccd 4269 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4270
1da177e4
LT		 4271 writeq(val64, &tx_fifo->List_Control);
4272
303bcb4b
K		 4273 mmiowb();
4274
1da177e4 4275 put_off++;
2fda096d 4276 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4277 put_off = 0;
2fda096d 4278 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4279
4280 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4281 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4282 swstats->fifo_full_cnt++;
1da177e4
LT		 4283 DBG_PRINT(TX_DBG,
4284 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4285 put_off, get_off);
3a3d5756 4286 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4287 }
ffb5df6c 4288 swstats->mem_allocated += skb->truesize;
2fda096d 4289 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4290
f6f4bfa3
SH		 4291 if (sp->config.intr_type == MSI_X)
4292 tx_intr_handler(fifo);
4293
6ed10654 4294 return NETDEV_TX_OK;
ffb5df6c 4295
491abf25 4296pci_map_failed:
ffb5df6c 4297 swstats->pci_map_fail_cnt++;
3a3d5756 4298 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4299 swstats->mem_freed += skb->truesize;
491abf25 4300 dev_kfree_skb(skb);
2fda096d 4301 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4302 return NETDEV_TX_OK;
1da177e4
LT		 4303}
4304
25fff88e
K		 4305static void
4306s2io_alarm_handle(unsigned long data)
4307{
1ee6dd77 4308 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4309 struct net_device *dev = sp->dev;
25fff88e 4310
8116f3cf 4311 s2io_handle_errors(dev);
25fff88e
K		 4312 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4313}
4314
7d12e780 4315static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4316{
1ee6dd77
RB		 4317 struct ring_info *ring = (struct ring_info *)dev_id;
4318 struct s2io_nic *sp = ring->nic;
f61e0a35 4319 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4320
f61e0a35 4321 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4322 return IRQ_HANDLED;
92b84437 4323
f61e0a35 4324 if (sp->config.napi) {
1a79d1c3
AV		 4325 u8 __iomem *addr = NULL;
4326 u8 val8 = 0;
f61e0a35 4327
1a79d1c3 4328 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4329 addr += (7 - ring->ring_no);
4330 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4331 writeb(val8, addr);
4332 val8 = readb(addr);
288379f0 4333 napi_schedule(&ring->napi);
f61e0a35
SH		 4334 } else {
4335 rx_intr_handler(ring, 0);
8d8bb39b 4336 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4337 }
7d3d0439 4338
cc6e7c44
RA		 4339 return IRQ_HANDLED;
4340}
4341
7d12e780 4342static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4343{
ac731ab6
SH		 4344 int i;
4345 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4346 struct s2io_nic *sp = fifos->nic;
4347 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4348 struct config_param *config = &sp->config;
4349 u64 reason;
cc6e7c44 4350
ac731ab6
SH		 4351 if (unlikely(!is_s2io_card_up(sp)))
4352 return IRQ_NONE;
4353
4354 reason = readq(&bar0->general_int_status);
4355 if (unlikely(reason == S2IO_MINUS_ONE))
4356 /* Nothing much can be done. Get out */
92b84437 4357 return IRQ_HANDLED;
92b84437 4358
01e16faa
SH		 4359 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4360 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4361
01e16faa
SH		 4362 if (reason & GEN_INTR_TXPIC)
4363 s2io_txpic_intr_handle(sp);
ac731ab6 4364
01e16faa
SH		 4365 if (reason & GEN_INTR_TXTRAFFIC)
4366 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4367
01e16faa
SH		 4368 for (i = 0; i < config->tx_fifo_num; i++)
4369 tx_intr_handler(&fifos[i]);
ac731ab6 4370
01e16faa
SH		 4371 writeq(sp->general_int_mask, &bar0->general_int_mask);
4372 readl(&bar0->general_int_status);
4373 return IRQ_HANDLED;
4374 }
4375 /* The interrupt was not raised by us */
4376 return IRQ_NONE;
cc6e7c44 4377}
ac731ab6 4378
1ee6dd77 4379static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4380{
1ee6dd77 4381 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4382 u64 val64;
4383
4384 val64 = readq(&bar0->pic_int_status);
4385 if (val64 & PIC_INT_GPIO) {
4386 val64 = readq(&bar0->gpio_int_reg);
4387 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4388 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4389 /*
4390 * This is unstable state so clear both up/down
4391 * interrupt and adapter to re-evaluate the link state.
4392 */
d44570e4 4393 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4394 val64 |= GPIO_INT_REG_LINK_UP;
4395 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4396 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4397 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4398 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4399 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4400 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4401 val64 = readq(&bar0->adapter_status);
d44570e4 4402 /* Enable Adapter */
19a60522
SS		 4403 val64 = readq(&bar0->adapter_control);
4404 val64 |= ADAPTER_CNTL_EN;
4405 writeq(val64, &bar0->adapter_control);
4406 val64 |= ADAPTER_LED_ON;
4407 writeq(val64, &bar0->adapter_control);
4408 if (!sp->device_enabled_once)
4409 sp->device_enabled_once = 1;
c92ca04b 4410
19a60522
SS		 4411 s2io_link(sp, LINK_UP);
4412 /*
4413 * unmask link down interrupt and mask link-up
4414 * intr
4415 */
4416 val64 = readq(&bar0->gpio_int_mask);
4417 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4418 val64 |= GPIO_INT_MASK_LINK_UP;
4419 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4420
d44570e4 4421 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4422 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4423 s2io_link(sp, LINK_DOWN);
4424 /* Link is down so unmaks link up interrupt */
4425 val64 = readq(&bar0->gpio_int_mask);
4426 val64 &= ~GPIO_INT_MASK_LINK_UP;
4427 val64 |= GPIO_INT_MASK_LINK_DOWN;
4428 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4429
4430 /* turn off LED */
4431 val64 = readq(&bar0->adapter_control);
d44570e4 4432 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4433 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4434 }
4435 }
c92ca04b 4436 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4437}
4438
8116f3cf
SS		 4439/**
4440 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4441 * @value: alarm bits
4442 * @addr: address value
4443 * @cnt: counter variable
4444 * Description: Check for alarm and increment the counter
4445 * Return Value:
4446 * 1 - if alarm bit set
4447 * 0 - if alarm bit is not set
4448 */
d44570e4
JP		 4449static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4450 unsigned long long *cnt)
8116f3cf
SS		 4451{
4452 u64 val64;
4453 val64 = readq(addr);
d44570e4 4454 if (val64 & value) {
8116f3cf
SS		 4455 writeq(val64, addr);
4456 (*cnt)++;
4457 return 1;
4458 }
4459 return 0;
4460
4461}
4462
4463/**
4464 * s2io_handle_errors - Xframe error indication handler
4465 * @nic: device private variable
4466 * Description: Handle alarms such as loss of link, single or
4467 * double ECC errors, critical and serious errors.
4468 * Return Value:
4469 * NONE
4470 */
d44570e4 4471static void s2io_handle_errors(void *dev_id)
8116f3cf 4472{
d44570e4 4473 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4474 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4475 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4476 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4477 int i = 0;
4478
4479 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4480 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4481
92b84437 4482 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4483 return;
4484
4485 if (pci_channel_offline(sp->pdev))
4486 return;
4487
4488 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4489 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4490
4491 /* Handling the XPAK counters update */
d44570e4 4492 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4493 /* waiting for an hour */
4494 stats->xpak_timer_count++;
4495 } else {
4496 s2io_updt_xpak_counter(dev);
4497 /* reset the count to zero */
4498 stats->xpak_timer_count = 0;
4499 }
4500
4501 /* Handling link status change error Intr */
4502 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4503 val64 = readq(&bar0->mac_rmac_err_reg);
4504 writeq(val64, &bar0->mac_rmac_err_reg);
4505 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4506 schedule_work(&sp->set_link_task);
4507 }
4508
4509 /* In case of a serious error, the device will be Reset. */
4510 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4511 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4512 goto reset;
4513
4514 /* Check for data parity error */
4515 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4516 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4517 goto reset;
4518
4519 /* Check for ring full counter */
4520 if (sp->device_type == XFRAME_II_DEVICE) {
4521 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4522 for (i = 0; i < 4; i++) {
4523 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4524 temp64 >>= 64 - ((i+1)*16);
4525 sw_stat->ring_full_cnt[i] += temp64;
4526 }
4527
4528 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4529 for (i = 0; i < 4; i++) {
4530 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4531 temp64 >>= 64 - ((i+1)*16);
d44570e4 4532 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4533 }
4534 }
4535
4536 val64 = readq(&bar0->txdma_int_status);
4537 /*check for pfc_err*/
4538 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4539 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4540 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4541 PFC_PCIX_ERR,
4542 &bar0->pfc_err_reg,
4543 &sw_stat->pfc_err_cnt))
8116f3cf 4544 goto reset;
d44570e4
JP		 4545 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4546 &bar0->pfc_err_reg,
4547 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4548 }
4549
4550 /*check for tda_err*/
4551 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4552 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4553 TDA_SM0_ERR_ALARM |
4554 TDA_SM1_ERR_ALARM,
4555 &bar0->tda_err_reg,
4556 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4557 goto reset;
4558 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4559 &bar0->tda_err_reg,
4560 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4561 }
4562 /*check for pcc_err*/
4563 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4564 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4565 PCC_N_SERR | PCC_6_COF_OV_ERR |
4566 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4567 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4568 PCC_TXB_ECC_DB_ERR,
4569 &bar0->pcc_err_reg,
4570 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4571 goto reset;
4572 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4573 &bar0->pcc_err_reg,
4574 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4575 }
4576
4577 /*check for tti_err*/
4578 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4579 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4580 &bar0->tti_err_reg,
4581 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4582 goto reset;
4583 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4584 &bar0->tti_err_reg,
4585 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4586 }
4587
4588 /*check for lso_err*/
4589 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4590 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4591 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4592 &bar0->lso_err_reg,
4593 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4594 goto reset;
4595 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4596 &bar0->lso_err_reg,
4597 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4598 }
4599
4600 /*check for tpa_err*/
4601 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4602 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4603 &bar0->tpa_err_reg,
4604 &sw_stat->tpa_err_cnt))
8116f3cf 4605 goto reset;
d44570e4
JP		 4606 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4607 &bar0->tpa_err_reg,
4608 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4609 }
4610
4611 /*check for sm_err*/
4612 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4613 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4614 &bar0->sm_err_reg,
4615 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4616 goto reset;
4617 }
4618
4619 val64 = readq(&bar0->mac_int_status);
4620 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4621 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4622 &bar0->mac_tmac_err_reg,
4623 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4624 goto reset;
d44570e4
JP		 4625 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4626 TMAC_DESC_ECC_SG_ERR |
4627 TMAC_DESC_ECC_DB_ERR,
4628 &bar0->mac_tmac_err_reg,
4629 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4630 }
4631
4632 val64 = readq(&bar0->xgxs_int_status);
4633 if (val64 & XGXS_INT_STATUS_TXGXS) {
4634 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4635 &bar0->xgxs_txgxs_err_reg,
4636 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4637 goto reset;
4638 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4639 &bar0->xgxs_txgxs_err_reg,
4640 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4641 }
4642
4643 val64 = readq(&bar0->rxdma_int_status);
4644 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4645 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4646 RC_FTC_ECC_DB_ERR |
4647 RC_PRCn_SM_ERR_ALARM |
4648 RC_FTC_SM_ERR_ALARM,
4649 &bar0->rc_err_reg,
4650 &sw_stat->rc_err_cnt))
8116f3cf 4651 goto reset;
d44570e4
JP		 4652 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4653 RC_FTC_ECC_SG_ERR |
4654 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4655 &sw_stat->rc_err_cnt);
4656 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4657 PRC_PCI_AB_WR_Rn |
4658 PRC_PCI_AB_F_WR_Rn,
4659 &bar0->prc_pcix_err_reg,
4660 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4661 goto reset;
d44570e4
JP		 4662 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4663 PRC_PCI_DP_WR_Rn |
4664 PRC_PCI_DP_F_WR_Rn,
4665 &bar0->prc_pcix_err_reg,
4666 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4667 }
4668
4669 if (val64 & RXDMA_INT_RPA_INT_M) {
4670 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4671 &bar0->rpa_err_reg,
4672 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4673 goto reset;
4674 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4675 &bar0->rpa_err_reg,
4676 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4677 }
4678
4679 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4680 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4681 RDA_FRM_ECC_DB_N_AERR |
4682 RDA_SM1_ERR_ALARM |
4683 RDA_SM0_ERR_ALARM |
4684 RDA_RXD_ECC_DB_SERR,
4685 &bar0->rda_err_reg,
4686 &sw_stat->rda_err_cnt))
8116f3cf 4687 goto reset;
d44570e4
JP		 4688 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4689 RDA_FRM_ECC_SG_ERR |
4690 RDA_MISC_ERR |
4691 RDA_PCIX_ERR,
4692 &bar0->rda_err_reg,
4693 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4694 }
4695
4696 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4697 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4698 &bar0->rti_err_reg,
4699 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4700 goto reset;
4701 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4702 &bar0->rti_err_reg,
4703 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4704 }
4705
4706 val64 = readq(&bar0->mac_int_status);
4707 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4711 goto reset;
d44570e4
JP		 4712 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4713 RMAC_SINGLE_ECC_ERR |
4714 RMAC_DOUBLE_ECC_ERR,
4715 &bar0->mac_rmac_err_reg,
4716 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4717 }
4718
4719 val64 = readq(&bar0->xgxs_int_status);
4720 if (val64 & XGXS_INT_STATUS_RXGXS) {
4721 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4722 &bar0->xgxs_rxgxs_err_reg,
4723 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4724 goto reset;
4725 }
4726
4727 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4728 if (val64 & MC_INT_STATUS_MC_INT) {
4729 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4730 &bar0->mc_err_reg,
4731 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4732 goto reset;
4733
4734 /* Handling Ecc errors */
4735 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4736 writeq(val64, &bar0->mc_err_reg);
4737 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4738 sw_stat->double_ecc_errs++;
4739 if (sp->device_type != XFRAME_II_DEVICE) {
4740 /*
4741 * Reset XframeI only if critical error
4742 */
4743 if (val64 &
d44570e4
JP		 4744 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4745 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4746 goto reset;
4747 }
8116f3cf
SS		 4748 } else
4749 sw_stat->single_ecc_errs++;
4750 }
4751 }
4752 return;
4753
4754reset:
3a3d5756 4755 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4756 schedule_work(&sp->rst_timer_task);
4757 sw_stat->soft_reset_cnt++;
4758 return;
4759}
4760
1da177e4
LT		 4761/**
4762 * s2io_isr - ISR handler of the device .
4763 * @irq: the irq of the device.
4764 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4765 * Description: This function is the ISR handler of the device. It
4766 * identifies the reason for the interrupt and calls the relevant
4767 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4768 * recv buffers, if their numbers are below the panic value which is
4769 * presently set to 25% of the original number of rcv buffers allocated.
4770 * Return value:
20346722 4771 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4772 * IRQ_NONE: will be returned if interrupt is not from our device
4773 */
7d12e780 4774static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4775{
d44570e4 4776 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4777 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4778 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4779 int i;
19a60522 4780 u64 reason = 0;
1ee6dd77 4781 struct mac_info *mac_control;
1da177e4
LT		 4782 struct config_param *config;
4783
d796fdb7
LV		 4784 /* Pretend we handled any irq's from a disconnected card */
4785 if (pci_channel_offline(sp->pdev))
4786 return IRQ_NONE;
4787
596c5c97 4788 if (!is_s2io_card_up(sp))
92b84437 4789 return IRQ_NONE;
92b84437 4790
1da177e4 4791 config = &sp->config;
ffb5df6c 4792 mac_control = &sp->mac_control;
1da177e4 4793
20346722 4794 /*
1da177e4
LT		 4795 * Identify the cause for interrupt and call the appropriate
4796 * interrupt handler. Causes for the interrupt could be;
4797 * 1. Rx of packet.
4798 * 2. Tx complete.
4799 * 3. Link down.
1da177e4
LT		 4800 */
4801 reason = readq(&bar0->general_int_status);
4802
d44570e4
JP		 4803 if (unlikely(reason == S2IO_MINUS_ONE))
4804 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4805
d44570e4
JP		 4806 if (reason &
4807 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4808 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4809
4810 if (config->napi) {
4811 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4812 napi_schedule(&sp->napi);
f61e0a35
SH		 4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4814 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4815 readl(&bar0->rx_traffic_int);
db874e65 4816 }
596c5c97
SS		 4817 } else {
4818 /*
4819 * rx_traffic_int reg is an R1 register, writing all 1's
4820 * will ensure that the actual interrupt causing bit
4821 * get's cleared and hence a read can be avoided.
4822 */
4823 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4824 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4825
13d866a9
JP		 4826 for (i = 0; i < config->rx_ring_num; i++) {
4827 struct ring_info *ring = &mac_control->rings[i];
4828
4829 rx_intr_handler(ring, 0);
4830 }
db874e65 4831 }
596c5c97 4832
db874e65 4833 /*
596c5c97 4834 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4835 * will ensure that the actual interrupt causing bit get's
4836 * cleared and hence a read can be avoided.
4837 */
596c5c97
SS		 4838 if (reason & GEN_INTR_TXTRAFFIC)
4839 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4840
596c5c97
SS		 4841 for (i = 0; i < config->tx_fifo_num; i++)
4842 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4843
596c5c97
SS		 4844 if (reason & GEN_INTR_TXPIC)
4845 s2io_txpic_intr_handle(sp);
fe113638 4846
596c5c97
SS		 4847 /*
4848 * Reallocate the buffers from the interrupt handler itself.
4849 */
4850 if (!config->napi) {
13d866a9
JP		 4851 for (i = 0; i < config->rx_ring_num; i++) {
4852 struct ring_info *ring = &mac_control->rings[i];
4853
4854 s2io_chk_rx_buffers(sp, ring);
4855 }
596c5c97
SS		 4856 }
4857 writeq(sp->general_int_mask, &bar0->general_int_mask);
4858 readl(&bar0->general_int_status);
20346722 4859
596c5c97 4860 return IRQ_HANDLED;
db874e65 4861
d44570e4 4862 } else if (!reason) {
596c5c97
SS		 4863 /* The interrupt was not raised by us */
4864 return IRQ_NONE;
4865 }
db874e65 4866
1da177e4
LT		 4867 return IRQ_HANDLED;
4868}
4869
7ba013ac
K		 4870/**
4871 * s2io_updt_stats -
4872 */
1ee6dd77 4873static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4874{
1ee6dd77 4875 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4876 u64 val64;
4877 int cnt = 0;
4878
92b84437 4879 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4880 /* Apprx 30us on a 133 MHz bus */
4881 val64 = SET_UPDT_CLICKS(10) |
4882 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4883 writeq(val64, &bar0->stat_cfg);
4884 do {
4885 udelay(100);
4886 val64 = readq(&bar0->stat_cfg);
b7b5a128 4887 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4888 break;
4889 cnt++;
4890 if (cnt == 5)
4891 break; /* Updt failed */
d44570e4 4892 } while (1);
8a4bdbaa 4893 }
7ba013ac
K		 4894}
4895
1da177e4 4896/**
20346722 4897 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4898 * @dev : pointer to the device structure.
4899 * Description:
20346722 4900 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4901 * structure and returns a pointer to the same.
4902 * Return value:
4903 * pointer to the updated net_device_stats structure.
4904 */
4905
ac1f60db 4906static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4907{
4cf1653a 4908 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4909 struct config_param *config = &sp->config;
4910 struct mac_info *mac_control = &sp->mac_control;
4911 struct stat_block *stats = mac_control->stats_info;
0425b46a 4912 int i;
1da177e4 4913
7ba013ac
K		 4914 /* Configure Stats for immediate updt */
4915 s2io_updt_stats(sp);
4916
dc56e634
BL		 4917 /* Using sp->stats as a staging area, because reset (due to mtu
4918 change, for example) will clear some hardware counters */
ffb5df6c 4919 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
dc56e634 4920 sp->stats.tx_packets;
ffb5df6c
JP		 4921 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4922
4923 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
dc56e634 4924 sp->stats.tx_errors;
ffb5df6c
JP		 4925 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4926
4927 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
dc56e634 4928 sp->stats.rx_errors;
ffb5df6c
JP		 4929 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4930
4931 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
dc56e634 4932 sp->stats.multicast;
ffb5df6c
JP		 4933 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4934
4935 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
dc56e634 4936 sp->stats.rx_length_errors;
ffb5df6c 4937 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
1da177e4 4938
0425b46a 4939 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4940 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4941 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4942 struct ring_info *ring = &mac_control->rings[i];
4943
4944 dev->stats.rx_packets += ring->rx_packets;
4945 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4946 }
4947
d44570e4 4948 return &dev->stats;
1da177e4
LT		 4949}
4950
4951/**
4952 * s2io_set_multicast - entry point for multicast address enable/disable.
4953 * @dev : pointer to the device structure
4954 * Description:
20346722
K		 4955 * This function is a driver entry point which gets called by the kernel
4956 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4957 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4958 * determine, if multicast address must be enabled or if promiscuous mode
4959 * is to be disabled etc.
4960 * Return value:
4961 * void.
4962 */
4963
4964static void s2io_set_multicast(struct net_device *dev)
4965{
4966 int i, j, prev_cnt;
4967 struct dev_mc_list *mclist;
4cf1653a 4968 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4969 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4970 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4971 0xfeffffffffffULL;
faa4f796 4972 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4973 void __iomem *add;
faa4f796 4974 struct config_param *config = &sp->config;
1da177e4
LT		 4975
4976 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4977 /* Enable all Multicast addresses */
4978 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4979 &bar0->rmac_addr_data0_mem);
4980 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4981 &bar0->rmac_addr_data1_mem);
4982 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4983 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4984 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4985 writeq(val64, &bar0->rmac_addr_cmd_mem);
4986 /* Wait till command completes */
c92ca04b 4987 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 4988 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4989 S2IO_BIT_RESET);
1da177e4
LT		 4990
4991 sp->m_cast_flg = 1;
faa4f796 4992 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4993 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4994 /* Disable all Multicast addresses */
4995 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4996 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4997 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4998 &bar0->rmac_addr_data1_mem);
1da177e4 4999 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5000 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5001 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5002 writeq(val64, &bar0->rmac_addr_cmd_mem);
5003 /* Wait till command completes */
c92ca04b 5004 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5005 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5006 S2IO_BIT_RESET);
1da177e4
LT		 5007
5008 sp->m_cast_flg = 0;
5009 sp->all_multi_pos = 0;
5010 }
5011
5012 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5013 /* Put the NIC into promiscuous mode */
5014 add = &bar0->mac_cfg;
5015 val64 = readq(&bar0->mac_cfg);
5016 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5017
5018 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5019 writel((u32)val64, add);
1da177e4
LT		 5020 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5021 writel((u32) (val64 >> 32), (add + 4));
5022
926930b2
SS		 5023 if (vlan_tag_strip != 1) {
5024 val64 = readq(&bar0->rx_pa_cfg);
5025 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5026 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5027 sp->vlan_strip_flag = 0;
926930b2
SS		 5028 }
5029
1da177e4
LT		 5030 val64 = readq(&bar0->mac_cfg);
5031 sp->promisc_flg = 1;
776bd20f 5032 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5033 dev->name);
5034 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5035 /* Remove the NIC from promiscuous mode */
5036 add = &bar0->mac_cfg;
5037 val64 = readq(&bar0->mac_cfg);
5038 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5039
5040 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5041 writel((u32)val64, add);
1da177e4
LT		 5042 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5043 writel((u32) (val64 >> 32), (add + 4));
5044
926930b2
SS		 5045 if (vlan_tag_strip != 0) {
5046 val64 = readq(&bar0->rx_pa_cfg);
5047 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5048 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5049 sp->vlan_strip_flag = 1;
926930b2
SS		 5050 }
5051
1da177e4
LT		 5052 val64 = readq(&bar0->mac_cfg);
5053 sp->promisc_flg = 0;
9e39f7c5 5054 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5055 }
5056
5057 /* Update individual M_CAST address list */
5058 if ((!sp->m_cast_flg) && dev->mc_count) {
5059 if (dev->mc_count >
faa4f796 5060 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5061 DBG_PRINT(ERR_DBG,
5062 "%s: No more Rx filters can be added - "
5063 "please enable ALL_MULTI instead\n",
1da177e4 5064 dev->name);
1da177e4
LT		 5065 return;
5066 }
5067
5068 prev_cnt = sp->mc_addr_count;
5069 sp->mc_addr_count = dev->mc_count;
5070
5071 /* Clear out the previous list of Mc in the H/W. */
5072 for (i = 0; i < prev_cnt; i++) {
5073 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5074 &bar0->rmac_addr_data0_mem);
5075 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5076 &bar0->rmac_addr_data1_mem);
1da177e4 5077 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5078 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5079 RMAC_ADDR_CMD_MEM_OFFSET
5080 (config->mc_start_offset + i);
1da177e4
LT		 5081 writeq(val64, &bar0->rmac_addr_cmd_mem);
5082
5083 /* Wait for command completes */
c92ca04b 5084 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5085 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5086 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5087 DBG_PRINT(ERR_DBG,
5088 "%s: Adding Multicasts failed\n",
5089 dev->name);
1da177e4
LT		 5090 return;
5091 }
5092 }
5093
5094 /* Create the new Rx filter list and update the same in H/W. */
5095 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5096 i++, mclist = mclist->next) {
5097 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5098 ETH_ALEN);
a7a80d5a 5099 mac_addr = 0;
1da177e4
LT		 5100 for (j = 0; j < ETH_ALEN; j++) {
5101 mac_addr |= mclist->dmi_addr[j];
5102 mac_addr <<= 8;
5103 }
5104 mac_addr >>= 8;
5105 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5106 &bar0->rmac_addr_data0_mem);
5107 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5108 &bar0->rmac_addr_data1_mem);
1da177e4 5109 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5110 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5111 RMAC_ADDR_CMD_MEM_OFFSET
5112 (i + config->mc_start_offset);
1da177e4
LT		 5113 writeq(val64, &bar0->rmac_addr_cmd_mem);
5114
5115 /* Wait for command completes */
c92ca04b 5116 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5117 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5118 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5119 DBG_PRINT(ERR_DBG,
5120 "%s: Adding Multicasts failed\n",
5121 dev->name);
1da177e4
LT		 5122 return;
5123 }
5124 }
5125 }
5126}
5127
faa4f796
SH		 5128/* read from CAM unicast & multicast addresses and store it in
5129 * def_mac_addr structure
5130 */
dac499f9 5131static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5132{
5133 int offset;
5134 u64 mac_addr = 0x0;
5135 struct config_param *config = &sp->config;
5136
5137 /* store unicast & multicast mac addresses */
5138 for (offset = 0; offset < config->max_mc_addr; offset++) {
5139 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140 /* if read fails disable the entry */
5141 if (mac_addr == FAILURE)
5142 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5144 }
5145}
5146
5147/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5149{
5150 int offset;
5151 struct config_param *config = &sp->config;
5152 /* restore unicast mac address */
5153 for (offset = 0; offset < config->max_mac_addr; offset++)
5154 do_s2io_prog_unicast(sp->dev,
d44570e4 5155 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5156
5157 /* restore multicast mac address */
5158 for (offset = config->mc_start_offset;
d44570e4 5159 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5160 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5161}
5162
5163/* add a multicast MAC address to CAM */
5164static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5165{
5166 int i;
5167 u64 mac_addr = 0;
5168 struct config_param *config = &sp->config;
5169
5170 for (i = 0; i < ETH_ALEN; i++) {
5171 mac_addr <<= 8;
5172 mac_addr |= addr[i];
5173 }
5174 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5175 return SUCCESS;
5176
5177 /* check if the multicast mac already preset in CAM */
5178 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5179 u64 tmp64;
5180 tmp64 = do_s2io_read_unicast_mc(sp, i);
5181 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5182 break;
5183
5184 if (tmp64 == mac_addr)
5185 return SUCCESS;
5186 }
5187 if (i == config->max_mc_addr) {
5188 DBG_PRINT(ERR_DBG,
d44570e4 5189 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5190 return FAILURE;
5191 }
5192 /* Update the internal structure with this new mac address */
5193 do_s2io_copy_mac_addr(sp, i, mac_addr);
5194
d44570e4 5195 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5196}
5197
5198/* add MAC address to CAM */
5199static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5200{
5201 u64 val64;
5202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5203
5204 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5205 &bar0->rmac_addr_data0_mem);
2fd37688 5206
d44570e4 5207 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5208 RMAC_ADDR_CMD_MEM_OFFSET(off);
5209 writeq(val64, &bar0->rmac_addr_cmd_mem);
5210
5211 /* Wait till command completes */
5212 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5213 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5214 S2IO_BIT_RESET)) {
faa4f796 5215 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5216 return FAILURE;
5217 }
5218 return SUCCESS;
5219}
faa4f796
SH		 5220/* deletes a specified unicast/multicast mac entry from CAM */
5221static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5222{
5223 int offset;
5224 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225 struct config_param *config = &sp->config;
5226
5227 for (offset = 1;
d44570e4 5228 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5229 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230 if (tmp64 == addr) {
5231 /* disable the entry by writing 0xffffffffffffULL */
5232 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5233 return FAILURE;
5234 /* store the new mac list from CAM */
5235 do_s2io_store_unicast_mc(sp);
5236 return SUCCESS;
5237 }
5238 }
5239 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5240 (unsigned long long)addr);
faa4f796
SH		 5241 return FAILURE;
5242}
5243
5244/* read mac entries from CAM */
5245static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5246{
5247 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250 /* read mac addr */
d44570e4 5251 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5252 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253 writeq(val64, &bar0->rmac_addr_cmd_mem);
5254
5255 /* Wait till command completes */
5256 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5257 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5258 S2IO_BIT_RESET)) {
faa4f796
SH		 5259 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5260 return FAILURE;
5261 }
5262 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5263
5264 return tmp64 >> 16;
faa4f796 5265}
2fd37688
SS		 5266
5267/**
5268 * s2io_set_mac_addr driver entry point
5269 */
faa4f796 5270
2fd37688
SS		 5271static int s2io_set_mac_addr(struct net_device *dev, void *p)
5272{
5273 struct sockaddr *addr = p;
5274
5275 if (!is_valid_ether_addr(addr->sa_data))
5276 return -EINVAL;
5277
5278 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5279
5280 /* store the MAC address in CAM */
d44570e4 5281 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5282}
1da177e4 5283/**
2fd37688 5284 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5285 * @dev : pointer to the device structure.
5286 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5287 * Description : This procedure will program the Xframe to receive
1da177e4 5288 * frames with new Mac Address
20346722 5289 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5290 * as defined in errno.h file on failure.
5291 */
faa4f796 5292
2fd37688 5293static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5294{
4cf1653a 5295 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5296 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5297 int i;
faa4f796
SH		 5298 u64 tmp64;
5299 struct config_param *config = &sp->config;
1da177e4 5300
20346722 5301 /*
d44570e4
JP		 5302 * Set the new MAC address as the new unicast filter and reflect this
5303 * change on the device address registered with the OS. It will be
5304 * at offset 0.
5305 */
1da177e4
LT		 5306 for (i = 0; i < ETH_ALEN; i++) {
5307 mac_addr <<= 8;
5308 mac_addr |= addr[i];
2fd37688
SS		 5309 perm_addr <<= 8;
5310 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5311 }
5312
2fd37688
SS		 5313 /* check if the dev_addr is different than perm_addr */
5314 if (mac_addr == perm_addr)
d8d70caf
SS		 5315 return SUCCESS;
5316
faa4f796
SH		 5317 /* check if the mac already preset in CAM */
5318 for (i = 1; i < config->max_mac_addr; i++) {
5319 tmp64 = do_s2io_read_unicast_mc(sp, i);
5320 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5321 break;
5322
5323 if (tmp64 == mac_addr) {
5324 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5325 "MAC addr:0x%llx already present in CAM\n",
5326 (unsigned long long)mac_addr);
faa4f796
SH		 5327 return SUCCESS;
5328 }
5329 }
5330 if (i == config->max_mac_addr) {
5331 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5332 return FAILURE;
5333 }
d8d70caf 5334 /* Update the internal structure with this new mac address */
faa4f796 5335 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5336
5337 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5338}
5339
5340/**
20346722 5341 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5342 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5343 * @info: pointer to the structure with parameters given by ethtool to set
5344 * link information.
5345 * Description:
20346722 5346 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5347 * the NIC.
5348 * Return value:
5349 * 0 on success.
d44570e4 5350 */
1da177e4
LT		 5351
5352static int s2io_ethtool_sset(struct net_device *dev,
5353 struct ethtool_cmd *info)
5354{
4cf1653a 5355 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5356 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5357 (info->speed != SPEED_10000) ||
5358 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5359 return -EINVAL;
5360 else {
5361 s2io_close(sp->dev);
5362 s2io_open(sp->dev);
5363 }
5364
5365 return 0;
5366}
5367
5368/**
20346722 5369 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5370 * @sp : private member of the device structure, pointer to the
5371 * s2io_nic structure.
5372 * @info : pointer to the structure with parameters given by ethtool
5373 * to return link information.
5374 * Description:
5375 * Returns link specific information like speed, duplex etc.. to ethtool.
5376 * Return value :
5377 * return 0 on success.
5378 */
5379
5380static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5381{
4cf1653a 5382 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5383 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5385 info->port = PORT_FIBRE;
1a7eb72b
SS		 5386
5387 /* info->transceiver */
5388 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5389
5390 if (netif_carrier_ok(sp->dev)) {
5391 info->speed = 10000;
5392 info->duplex = DUPLEX_FULL;
5393 } else {
5394 info->speed = -1;
5395 info->duplex = -1;
5396 }
5397
5398 info->autoneg = AUTONEG_DISABLE;
5399 return 0;
5400}
5401
5402/**
20346722
K		 5403 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5404 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool to
5407 * return driver information.
5408 * Description:
5409 * Returns driver specefic information like name, version etc.. to ethtool.
5410 * Return value:
5411 * void
5412 */
5413
5414static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5415 struct ethtool_drvinfo *info)
5416{
4cf1653a 5417 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5418
dbc2309d
JL		 5419 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5420 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5421 strncpy(info->fw_version, "", sizeof(info->fw_version));
5422 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5423 info->regdump_len = XENA_REG_SPACE;
5424 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5425}
5426
5427/**
5428 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5429 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5430 * s2io_nic structure.
20346722 5431 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5432 * dumping the registers.
5433 * @reg_space: The input argumnet into which all the registers are dumped.
5434 * Description:
5435 * Dumps the entire register space of xFrame NIC into the user given
5436 * buffer area.
5437 * Return value :
5438 * void .
d44570e4 5439 */
1da177e4
LT		 5440
5441static void s2io_ethtool_gregs(struct net_device *dev,
5442 struct ethtool_regs *regs, void *space)
5443{
5444 int i;
5445 u64 reg;
d44570e4 5446 u8 *reg_space = (u8 *)space;
4cf1653a 5447 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5448
5449 regs->len = XENA_REG_SPACE;
5450 regs->version = sp->pdev->subsystem_device;
5451
5452 for (i = 0; i < regs->len; i += 8) {
5453 reg = readq(sp->bar0 + i);
5454 memcpy((reg_space + i), &reg, 8);
5455 }
5456}
5457
5458/**
5459 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5460 * @data : address of the private member of the device structure, which
1da177e4 5461 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5462 * Description: This is actually the timer function that alternates the
5463 * adapter LED bit of the adapter control bit to set/reset every time on
5464 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5465 * once every second.
d44570e4 5466 */
1da177e4
LT		 5467static void s2io_phy_id(unsigned long data)
5468{
d44570e4 5469 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5471 u64 val64 = 0;
5472 u16 subid;
5473
5474 subid = sp->pdev->subsystem_device;
541ae68f 5475 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5476 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5477 val64 = readq(&bar0->gpio_control);
5478 val64 ^= GPIO_CTRL_GPIO_0;
5479 writeq(val64, &bar0->gpio_control);
5480 } else {
5481 val64 = readq(&bar0->adapter_control);
5482 val64 ^= ADAPTER_LED_ON;
5483 writeq(val64, &bar0->adapter_control);
5484 }
5485
5486 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5487}
5488
5489/**
5490 * s2io_ethtool_idnic - To physically identify the nic on the system.
5491 * @sp : private member of the device structure, which is a pointer to the
5492 * s2io_nic structure.
20346722 5493 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5494 * ethtool.
5495 * Description: Used to physically identify the NIC on the system.
20346722 5496 * The Link LED will blink for a time specified by the user for
1da177e4 5497 * identification.
20346722 5498 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5499 * identification is possible only if it's link is up.
5500 * Return value:
5501 * int , returns 0 on success
5502 */
5503
5504static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5505{
5506 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5507 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5509 u16 subid;
5510
5511 subid = sp->pdev->subsystem_device;
5512 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5513 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5514 val64 = readq(&bar0->adapter_control);
5515 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5516 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5517 return -EFAULT;
5518 }
5519 }
5520 if (sp->id_timer.function == NULL) {
5521 init_timer(&sp->id_timer);
5522 sp->id_timer.function = s2io_phy_id;
d44570e4 5523 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5524 }
5525 mod_timer(&sp->id_timer, jiffies);
5526 if (data)
20346722 5527 msleep_interruptible(data * HZ);
1da177e4 5528 else
20346722 5529 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5530 del_timer_sync(&sp->id_timer);
5531
541ae68f 5532 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5533 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5534 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5535 }
5536
5537 return 0;
5538}
5539
0cec35eb 5540static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5541 struct ethtool_ringparam *ering)
0cec35eb 5542{
4cf1653a 5543 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5544 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5545
5546 if (sp->rxd_mode == RXD_MODE_1)
5547 ering->rx_max_pending = MAX_RX_DESC_1;
5548 else if (sp->rxd_mode == RXD_MODE_3B)
5549 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5550
5551 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5552 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5553 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5554
9e39f7c5 5555 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5556 ering->tx_pending = tx_desc_count;
5557 rx_desc_count = 0;
8a4bdbaa 5558 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5559 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5560
0cec35eb
SH		 5561 ering->rx_pending = rx_desc_count;
5562
5563 ering->rx_mini_max_pending = 0;
5564 ering->rx_mini_pending = 0;
d44570e4 5565 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5566 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5567 else if (sp->rxd_mode == RXD_MODE_3B)
5568 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5569 ering->rx_jumbo_pending = rx_desc_count;
5570}
5571
1da177e4
LT		 5572/**
5573 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5574 * @sp : private member of the device structure, which is a pointer to the
5575 * s2io_nic structure.
1da177e4
LT		 5576 * @ep : pointer to the structure with pause parameters given by ethtool.
5577 * Description:
5578 * Returns the Pause frame generation and reception capability of the NIC.
5579 * Return value:
5580 * void
5581 */
5582static void s2io_ethtool_getpause_data(struct net_device *dev,
5583 struct ethtool_pauseparam *ep)
5584{
5585 u64 val64;
4cf1653a 5586 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5587 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5588
5589 val64 = readq(&bar0->rmac_pause_cfg);
5590 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5591 ep->tx_pause = true;
1da177e4 5592 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5593 ep->rx_pause = true;
5594 ep->autoneg = false;
1da177e4
LT		 5595}
5596
5597/**
5598 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5599 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5600 * s2io_nic structure.
5601 * @ep : pointer to the structure with pause parameters given by ethtool.
5602 * Description:
5603 * It can be used to set or reset Pause frame generation or reception
5604 * support of the NIC.
5605 * Return value:
5606 * int, returns 0 on Success
5607 */
5608
5609static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5610 struct ethtool_pauseparam *ep)
1da177e4
LT		 5611{
5612 u64 val64;
4cf1653a 5613 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5614 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5615
5616 val64 = readq(&bar0->rmac_pause_cfg);
5617 if (ep->tx_pause)
5618 val64 |= RMAC_PAUSE_GEN_ENABLE;
5619 else
5620 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5621 if (ep->rx_pause)
5622 val64 |= RMAC_PAUSE_RX_ENABLE;
5623 else
5624 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5625 writeq(val64, &bar0->rmac_pause_cfg);
5626 return 0;
5627}
5628
5629/**
5630 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5631 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5632 * s2io_nic structure.
5633 * @off : offset at which the data must be written
5634 * @data : Its an output parameter where the data read at the given
20346722 5635 * offset is stored.
1da177e4 5636 * Description:
20346722 5637 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5638 * read data.
5639 * NOTE: Will allow to read only part of the EEPROM visible through the
5640 * I2C bus.
5641 * Return value:
5642 * -1 on failure and 0 on success.
5643 */
5644
5645#define S2IO_DEV_ID 5
d44570e4 5646static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5647{
5648 int ret = -1;
5649 u32 exit_cnt = 0;
5650 u64 val64;
1ee6dd77 5651 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5652
ad4ebed0 5653 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5654 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5655 I2C_CONTROL_ADDR(off) |
5656 I2C_CONTROL_BYTE_CNT(0x3) |
5657 I2C_CONTROL_READ |
5658 I2C_CONTROL_CNTL_START;
ad4ebed0 5659 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5660
ad4ebed0 5661 while (exit_cnt < 5) {
5662 val64 = readq(&bar0->i2c_control);
5663 if (I2C_CONTROL_CNTL_END(val64)) {
5664 *data = I2C_CONTROL_GET_DATA(val64);
5665 ret = 0;
5666 break;
5667 }
5668 msleep(50);
5669 exit_cnt++;
1da177e4 5670 }
1da177e4
LT		 5671 }
5672
ad4ebed0 5673 if (sp->device_type == XFRAME_II_DEVICE) {
5674 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5675 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5676 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5677 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5678 val64 |= SPI_CONTROL_REQ;
5679 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5680 while (exit_cnt < 5) {
5681 val64 = readq(&bar0->spi_control);
5682 if (val64 & SPI_CONTROL_NACK) {
5683 ret = 1;
5684 break;
5685 } else if (val64 & SPI_CONTROL_DONE) {
5686 *data = readq(&bar0->spi_data);
5687 *data &= 0xffffff;
5688 ret = 0;
5689 break;
5690 }
5691 msleep(50);
5692 exit_cnt++;
5693 }
5694 }
1da177e4
LT		 5695 return ret;
5696}
5697
5698/**
5699 * write_eeprom - actually writes the relevant part of the data value.
5700 * @sp : private member of the device structure, which is a pointer to the
5701 * s2io_nic structure.
5702 * @off : offset at which the data must be written
5703 * @data : The data that is to be written
20346722 5704 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5705 * the Eeprom. (max of 3)
5706 * Description:
5707 * Actually writes the relevant part of the data value into the Eeprom
5708 * through the I2C bus.
5709 * Return value:
5710 * 0 on success, -1 on failure.
5711 */
5712
d44570e4 5713static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5714{
5715 int exit_cnt = 0, ret = -1;
5716 u64 val64;
1ee6dd77 5717 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5718
ad4ebed0 5719 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5720 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5721 I2C_CONTROL_ADDR(off) |
5722 I2C_CONTROL_BYTE_CNT(cnt) |
5723 I2C_CONTROL_SET_DATA((u32)data) |
5724 I2C_CONTROL_CNTL_START;
ad4ebed0 5725 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5726
5727 while (exit_cnt < 5) {
5728 val64 = readq(&bar0->i2c_control);
5729 if (I2C_CONTROL_CNTL_END(val64)) {
5730 if (!(val64 & I2C_CONTROL_NACK))
5731 ret = 0;
5732 break;
5733 }
5734 msleep(50);
5735 exit_cnt++;
5736 }
5737 }
1da177e4 5738
ad4ebed0 5739 if (sp->device_type == XFRAME_II_DEVICE) {
5740 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5741 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5742
5743 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5744 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5745 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5746 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5747 val64 |= SPI_CONTROL_REQ;
5748 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5749 while (exit_cnt < 5) {
5750 val64 = readq(&bar0->spi_control);
5751 if (val64 & SPI_CONTROL_NACK) {
5752 ret = 1;
5753 break;
5754 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5755 ret = 0;
ad4ebed0 5756 break;
5757 }
5758 msleep(50);
5759 exit_cnt++;
1da177e4 5760 }
1da177e4 5761 }
1da177e4
LT		 5762 return ret;
5763}
1ee6dd77 5764static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5765{
b41477f3
AR		 5766 u8 *vpd_data;
5767 u8 data;
d44570e4 5768 int i = 0, cnt, fail = 0;
9dc737a7 5769 int vpd_addr = 0x80;
ffb5df6c 5770 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5771
5772 if (nic->device_type == XFRAME_II_DEVICE) {
5773 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5774 vpd_addr = 0x80;
d44570e4 5775 } else {
9dc737a7
AR		 5776 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5777 vpd_addr = 0x50;
5778 }
19a60522 5779 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5780
b41477f3 5781 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5782 if (!vpd_data) {
ffb5df6c 5783 swstats->mem_alloc_fail_cnt++;
b41477f3 5784 return;
c53d4945 5785 }
ffb5df6c 5786 swstats->mem_allocated += 256;
b41477f3 5787
d44570e4 5788 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5789 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5790 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5791 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5792 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5793 msleep(2);
5794 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5795 if (data == 0x80)
5796 break;
5797 }
5798 if (cnt >= 5) {
5799 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5800 fail = 1;
5801 break;
5802 }
5803 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5804 (u32 *)&vpd_data[i]);
5805 }
19a60522 5806
d44570e4 5807 if (!fail) {
19a60522
SS		 5808 /* read serial number of adapter */
5809 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5810 if ((vpd_data[cnt] == 'S') &&
5811 (vpd_data[cnt+1] == 'N') &&
5812 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5813 memset(nic->serial_num, 0, VPD_STRING_LEN);
5814 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5815 vpd_data[cnt+2]);
19a60522
SS		 5816 break;
5817 }
5818 }
5819 }
5820
5821 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5822 memset(nic->product_name, 0, vpd_data[1]);
5823 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5824 }
b41477f3 5825 kfree(vpd_data);
ffb5df6c 5826 swstats->mem_freed += 256;
9dc737a7
AR		 5827}
5828
1da177e4
LT		 5829/**
5830 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5831 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5832 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5833 * containing all relevant information.
5834 * @data_buf : user defined value to be written into Eeprom.
5835 * Description: Reads the values stored in the Eeprom at given offset
5836 * for a given length. Stores these values int the input argument data
5837 * buffer 'data_buf' and returns these to the caller (ethtool.)
5838 * Return value:
5839 * int 0 on success
5840 */
5841
5842static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5843 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5844{
ad4ebed0 5845 u32 i, valid;
5846 u64 data;
4cf1653a 5847 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5848
5849 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5850
5851 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5852 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5853
5854 for (i = 0; i < eeprom->len; i += 4) {
5855 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5856 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5857 return -EFAULT;
5858 }
5859 valid = INV(data);
5860 memcpy((data_buf + i), &valid, 4);
5861 }
5862 return 0;
5863}
5864
5865/**
5866 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5867 * @sp : private member of the device structure, which is a pointer to the
5868 * s2io_nic structure.
20346722 5869 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5870 * containing all relevant information.
5871 * @data_buf ; user defined value to be written into Eeprom.
5872 * Description:
5873 * Tries to write the user provided value in the Eeprom, at the offset
5874 * given by the user.
5875 * Return value:
5876 * 0 on success, -EFAULT on failure.
5877 */
5878
5879static int s2io_ethtool_seeprom(struct net_device *dev,
5880 struct ethtool_eeprom *eeprom,
d44570e4 5881 u8 *data_buf)
1da177e4
LT		 5882{
5883 int len = eeprom->len, cnt = 0;
ad4ebed0 5884 u64 valid = 0, data;
4cf1653a 5885 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5886
5887 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5888 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5889 "ETHTOOL_WRITE_EEPROM Err: "
5890 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5891 (sp->pdev->vendor | (sp->pdev->device << 16)),
5892 eeprom->magic);
1da177e4
LT		 5893 return -EFAULT;
5894 }
5895
5896 while (len) {
d44570e4
JP		 5897 data = (u32)data_buf[cnt] & 0x000000FF;
5898 if (data)
5899 valid = (u32)(data << 24);
5900 else
1da177e4
LT		 5901 valid = data;
5902
5903 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5904 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5905 "ETHTOOL_WRITE_EEPROM Err: "
5906 "Cannot write into the specified offset\n");
1da177e4
LT		 5907 return -EFAULT;
5908 }
5909 cnt++;
5910 len--;
5911 }
5912
5913 return 0;
5914}
5915
5916/**
20346722
K		 5917 * s2io_register_test - reads and writes into all clock domains.
5918 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5919 * s2io_nic structure.
5920 * @data : variable that returns the result of each of the test conducted b
5921 * by the driver.
5922 * Description:
5923 * Read and write into all clock domains. The NIC has 3 clock domains,
5924 * see that registers in all the three regions are accessible.
5925 * Return value:
5926 * 0 on success.
5927 */
5928
d44570e4 5929static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5930{
1ee6dd77 5931 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5932 u64 val64 = 0, exp_val;
1da177e4
LT		 5933 int fail = 0;
5934
20346722
K		 5935 val64 = readq(&bar0->pif_rd_swapper_fb);
5936 if (val64 != 0x123456789abcdefULL) {
1da177e4 5937 fail = 1;
9e39f7c5 5938 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5939 }
5940
5941 val64 = readq(&bar0->rmac_pause_cfg);
5942 if (val64 != 0xc000ffff00000000ULL) {
5943 fail = 1;
9e39f7c5 5944 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5945 }
5946
5947 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5948 if (sp->device_type == XFRAME_II_DEVICE)
5949 exp_val = 0x0404040404040404ULL;
5950 else
5951 exp_val = 0x0808080808080808ULL;
5952 if (val64 != exp_val) {
1da177e4 5953 fail = 1;
9e39f7c5 5954 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5955 }
5956
5957 val64 = readq(&bar0->xgxs_efifo_cfg);
5958 if (val64 != 0x000000001923141EULL) {
5959 fail = 1;
9e39f7c5 5960 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5961 }
5962
5963 val64 = 0x5A5A5A5A5A5A5A5AULL;
5964 writeq(val64, &bar0->xmsi_data);
5965 val64 = readq(&bar0->xmsi_data);
5966 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5967 fail = 1;
9e39f7c5 5968 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5969 }
5970
5971 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5972 writeq(val64, &bar0->xmsi_data);
5973 val64 = readq(&bar0->xmsi_data);
5974 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5975 fail = 1;
9e39f7c5 5976 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 5977 }
5978
5979 *data = fail;
ad4ebed0 5980 return fail;
1da177e4
LT		 5981}
5982
5983/**
20346722 5984 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5985 * @sp : private member of the device structure, which is a pointer to the
5986 * s2io_nic structure.
5987 * @data:variable that returns the result of each of the test conducted by
5988 * the driver.
5989 * Description:
20346722 5990 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5991 * register.
5992 * Return value:
5993 * 0 on success.
5994 */
5995
d44570e4 5996static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 5997{
5998 int fail = 0;
ad4ebed0 5999 u64 ret_data, org_4F0, org_7F0;
6000 u8 saved_4F0 = 0, saved_7F0 = 0;
6001 struct net_device *dev = sp->dev;
1da177e4
LT		 6002
6003 /* Test Write Error at offset 0 */
ad4ebed0 6004 /* Note that SPI interface allows write access to all areas
6005 * of EEPROM. Hence doing all negative testing only for Xframe I.
6006 */
6007 if (sp->device_type == XFRAME_I_DEVICE)
6008 if (!write_eeprom(sp, 0, 0, 3))
6009 fail = 1;
6010
6011 /* Save current values at offsets 0x4F0 and 0x7F0 */
6012 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6013 saved_4F0 = 1;
6014 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6015 saved_7F0 = 1;
1da177e4
LT		 6016
6017 /* Test Write at offset 4f0 */
ad4ebed0 6018 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6019 fail = 1;
6020 if (read_eeprom(sp, 0x4F0, &ret_data))
6021 fail = 1;
6022
ad4ebed0 6023 if (ret_data != 0x012345) {
26b7625c 6024 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6025 "Data written %llx Data read %llx\n",
6026 dev->name, (unsigned long long)0x12345,
6027 (unsigned long long)ret_data);
1da177e4 6028 fail = 1;
ad4ebed0 6029 }
1da177e4
LT		 6030
6031 /* Reset the EEPROM data go FFFF */
ad4ebed0 6032 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6033
6034 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6035 if (sp->device_type == XFRAME_I_DEVICE)
6036 if (!write_eeprom(sp, 0x07C, 0, 3))
6037 fail = 1;
1da177e4 6038
ad4ebed0 6039 /* Test Write Request at offset 0x7f0 */
6040 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6041 fail = 1;
ad4ebed0 6042 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6043 fail = 1;
6044
ad4ebed0 6045 if (ret_data != 0x012345) {
26b7625c 6046 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6047 "Data written %llx Data read %llx\n",
6048 dev->name, (unsigned long long)0x12345,
6049 (unsigned long long)ret_data);
1da177e4 6050 fail = 1;
ad4ebed0 6051 }
1da177e4
LT		 6052
6053 /* Reset the EEPROM data go FFFF */
ad4ebed0 6054 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6055
ad4ebed0 6056 if (sp->device_type == XFRAME_I_DEVICE) {
6057 /* Test Write Error at offset 0x80 */
6058 if (!write_eeprom(sp, 0x080, 0, 3))
6059 fail = 1;
1da177e4 6060
ad4ebed0 6061 /* Test Write Error at offset 0xfc */
6062 if (!write_eeprom(sp, 0x0FC, 0, 3))
6063 fail = 1;
1da177e4 6064
ad4ebed0 6065 /* Test Write Error at offset 0x100 */
6066 if (!write_eeprom(sp, 0x100, 0, 3))
6067 fail = 1;
1da177e4 6068
ad4ebed0 6069 /* Test Write Error at offset 4ec */
6070 if (!write_eeprom(sp, 0x4EC, 0, 3))
6071 fail = 1;
6072 }
6073
6074 /* Restore values at offsets 0x4F0 and 0x7F0 */
6075 if (saved_4F0)
6076 write_eeprom(sp, 0x4F0, org_4F0, 3);
6077 if (saved_7F0)
6078 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6079
6080 *data = fail;
ad4ebed0 6081 return fail;
1da177e4
LT		 6082}
6083
6084/**
6085 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6086 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6087 * s2io_nic structure.
20346722 6088 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6089 * the driver.
6090 * Description:
6091 * This invokes the MemBist test of the card. We give around
6092 * 2 secs time for the Test to complete. If it's still not complete
20346722 6093 * within this peiod, we consider that the test failed.
1da177e4
LT		 6094 * Return value:
6095 * 0 on success and -1 on failure.
6096 */
6097
d44570e4 6098static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6099{
6100 u8 bist = 0;
6101 int cnt = 0, ret = -1;
6102
6103 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6104 bist |= PCI_BIST_START;
6105 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6106
6107 while (cnt < 20) {
6108 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6109 if (!(bist & PCI_BIST_START)) {
6110 *data = (bist & PCI_BIST_CODE_MASK);
6111 ret = 0;
6112 break;
6113 }
6114 msleep(100);
6115 cnt++;
6116 }
6117
6118 return ret;
6119}
6120
6121/**
20346722
K		 6122 * s2io-link_test - verifies the link state of the nic
6123 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6124 * s2io_nic structure.
6125 * @data: variable that returns the result of each of the test conducted by
6126 * the driver.
6127 * Description:
20346722 6128 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6129 * argument 'data' appropriately.
6130 * Return value:
6131 * 0 on success.
6132 */
6133
d44570e4 6134static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6135{
1ee6dd77 6136 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6137 u64 val64;
6138
6139 val64 = readq(&bar0->adapter_status);
d44570e4 6140 if (!(LINK_IS_UP(val64)))
1da177e4 6141 *data = 1;
c92ca04b
AR		 6142 else
6143 *data = 0;
1da177e4 6144
b41477f3 6145 return *data;
1da177e4
LT		 6146}
6147
6148/**
20346722
K		 6149 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6150 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6151 * s2io_nic structure.
20346722 6152 * @data - variable that returns the result of each of the test
1da177e4
LT		 6153 * conducted by the driver.
6154 * Description:
20346722 6155 * This is one of the offline test that tests the read and write
1da177e4
LT		 6156 * access to the RldRam chip on the NIC.
6157 * Return value:
6158 * 0 on success.
6159 */
6160
d44570e4 6161static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6162{
1ee6dd77 6163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6164 u64 val64;
ad4ebed0 6165 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6166
6167 val64 = readq(&bar0->adapter_control);
6168 val64 &= ~ADAPTER_ECC_EN;
6169 writeq(val64, &bar0->adapter_control);
6170
6171 val64 = readq(&bar0->mc_rldram_test_ctrl);
6172 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6173 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6174
6175 val64 = readq(&bar0->mc_rldram_mrs);
6176 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6177 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6178
6179 val64 |= MC_RLDRAM_MRS_ENABLE;
6180 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6181
6182 while (iteration < 2) {
6183 val64 = 0x55555555aaaa0000ULL;
d44570e4 6184 if (iteration == 1)
1da177e4 6185 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6186 writeq(val64, &bar0->mc_rldram_test_d0);
6187
6188 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6189 if (iteration == 1)
1da177e4 6190 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6191 writeq(val64, &bar0->mc_rldram_test_d1);
6192
6193 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6194 if (iteration == 1)
1da177e4 6195 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6196 writeq(val64, &bar0->mc_rldram_test_d2);
6197
ad4ebed0 6198 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6199 writeq(val64, &bar0->mc_rldram_test_add);
6200
d44570e4
JP		 6201 val64 = MC_RLDRAM_TEST_MODE |
6202 MC_RLDRAM_TEST_WRITE |
6203 MC_RLDRAM_TEST_GO;
ad4ebed0 6204 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6205
6206 for (cnt = 0; cnt < 5; cnt++) {
6207 val64 = readq(&bar0->mc_rldram_test_ctrl);
6208 if (val64 & MC_RLDRAM_TEST_DONE)
6209 break;
6210 msleep(200);
6211 }
6212
6213 if (cnt == 5)
6214 break;
6215
ad4ebed0 6216 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6217 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6218
6219 for (cnt = 0; cnt < 5; cnt++) {
6220 val64 = readq(&bar0->mc_rldram_test_ctrl);
6221 if (val64 & MC_RLDRAM_TEST_DONE)
6222 break;
6223 msleep(500);
6224 }
6225
6226 if (cnt == 5)
6227 break;
6228
6229 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6230 if (!(val64 & MC_RLDRAM_TEST_PASS))
6231 test_fail = 1;
1da177e4
LT		 6232
6233 iteration++;
6234 }
6235
ad4ebed0 6236 *data = test_fail;
1da177e4 6237
ad4ebed0 6238 /* Bring the adapter out of test mode */
6239 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6240
6241 return test_fail;
1da177e4
LT		 6242}
6243
6244/**
6245 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6246 * @sp : private member of the device structure, which is a pointer to the
6247 * s2io_nic structure.
6248 * @ethtest : pointer to a ethtool command specific structure that will be
6249 * returned to the user.
20346722 6250 * @data : variable that returns the result of each of the test
1da177e4
LT		 6251 * conducted by the driver.
6252 * Description:
6253 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6254 * the health of the card.
6255 * Return value:
6256 * void
6257 */
6258
6259static void s2io_ethtool_test(struct net_device *dev,
6260 struct ethtool_test *ethtest,
d44570e4 6261 uint64_t *data)
1da177e4 6262{
4cf1653a 6263 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6264 int orig_state = netif_running(sp->dev);
6265
6266 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6267 /* Offline Tests. */
20346722 6268 if (orig_state)
1da177e4 6269 s2io_close(sp->dev);
1da177e4
LT		 6270
6271 if (s2io_register_test(sp, &data[0]))
6272 ethtest->flags |= ETH_TEST_FL_FAILED;
6273
6274 s2io_reset(sp);
1da177e4
LT		 6275
6276 if (s2io_rldram_test(sp, &data[3]))
6277 ethtest->flags |= ETH_TEST_FL_FAILED;
6278
6279 s2io_reset(sp);
1da177e4
LT		 6280
6281 if (s2io_eeprom_test(sp, &data[1]))
6282 ethtest->flags |= ETH_TEST_FL_FAILED;
6283
6284 if (s2io_bist_test(sp, &data[4]))
6285 ethtest->flags |= ETH_TEST_FL_FAILED;
6286
6287 if (orig_state)
6288 s2io_open(sp->dev);
6289
6290 data[2] = 0;
6291 } else {
6292 /* Online Tests. */
6293 if (!orig_state) {
d44570e4 6294 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6295 dev->name);
6296 data[0] = -1;
6297 data[1] = -1;
6298 data[2] = -1;
6299 data[3] = -1;
6300 data[4] = -1;
6301 }
6302
6303 if (s2io_link_test(sp, &data[2]))
6304 ethtest->flags |= ETH_TEST_FL_FAILED;
6305
6306 data[0] = 0;
6307 data[1] = 0;
6308 data[3] = 0;
6309 data[4] = 0;
6310 }
6311}
6312
6313static void s2io_get_ethtool_stats(struct net_device *dev,
6314 struct ethtool_stats *estats,
d44570e4 6315 u64 *tmp_stats)
1da177e4 6316{
8116f3cf 6317 int i = 0, k;
4cf1653a 6318 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6319 struct stat_block *stats = sp->mac_control.stats_info;
6320 struct swStat *swstats = &stats->sw_stat;
6321 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6322
7ba013ac 6323 s2io_updt_stats(sp);
541ae68f 6324 tmp_stats[i++] =
ffb5df6c
JP		 6325 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6326 le32_to_cpu(stats->tmac_frms);
541ae68f 6327 tmp_stats[i++] =
ffb5df6c
JP		 6328 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6329 le32_to_cpu(stats->tmac_data_octets);
6330 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6331 tmp_stats[i++] =
ffb5df6c
JP		 6332 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6333 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6334 tmp_stats[i++] =
ffb5df6c
JP		 6335 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6336 le32_to_cpu(stats->tmac_bcst_frms);
6337 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6338 tmp_stats[i++] =
ffb5df6c
JP		 6339 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6340 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6341 tmp_stats[i++] =
ffb5df6c
JP		 6342 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6343 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6344 tmp_stats[i++] =
ffb5df6c
JP		 6345 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6346 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6347 tmp_stats[i++] =
ffb5df6c
JP		 6348 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6349 le32_to_cpu(stats->tmac_any_err_frms);
6350 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6351 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6352 tmp_stats[i++] =
ffb5df6c
JP		 6353 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6354 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6355 tmp_stats[i++] =
ffb5df6c
JP		 6356 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6357 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6358 tmp_stats[i++] =
ffb5df6c
JP		 6359 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6360 le32_to_cpu(stats->tmac_icmp);
541ae68f 6361 tmp_stats[i++] =
ffb5df6c
JP		 6362 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6363 le32_to_cpu(stats->tmac_rst_tcp);
6364 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6365 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6366 le32_to_cpu(stats->tmac_udp);
541ae68f 6367 tmp_stats[i++] =
ffb5df6c
JP		 6368 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6369 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6370 tmp_stats[i++] =
ffb5df6c
JP		 6371 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6372 le32_to_cpu(stats->rmac_data_octets);
6373 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6374 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6375 tmp_stats[i++] =
ffb5df6c
JP		 6376 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6377 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6378 tmp_stats[i++] =
ffb5df6c
JP		 6379 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6380 le32_to_cpu(stats->rmac_vld_bcst_frms);
6381 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6382 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6384 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6385 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6386 tmp_stats[i++] =
ffb5df6c
JP		 6387 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6388 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6389 tmp_stats[i++] =
ffb5df6c
JP		 6390 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6391 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6392 tmp_stats[i++] =
ffb5df6c
JP		 6393 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6394 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6395 tmp_stats[i++] =
ffb5df6c
JP		 6396 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6397 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6398 tmp_stats[i++] =
ffb5df6c
JP		 6399 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6400 << 32 | le32_to_cpu(stats->rmac_drop_events);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6403 tmp_stats[i++] =
ffb5df6c
JP		 6404 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6406 tmp_stats[i++] =
ffb5df6c
JP		 6407 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6408 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6409 tmp_stats[i++] =
ffb5df6c
JP		 6410 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6411 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6412 tmp_stats[i++] =
ffb5df6c
JP		 6413 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6414 le32_to_cpu(stats->rmac_jabber_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6420 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6421 tmp_stats[i++] =
ffb5df6c
JP		 6422 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6423 le32_to_cpu(stats->rmac_ip);
6424 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6425 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6426 tmp_stats[i++] =
ffb5df6c
JP		 6427 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6428 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6429 tmp_stats[i++] =
ffb5df6c
JP		 6430 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6431 le32_to_cpu(stats->rmac_icmp);
6432 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6433 tmp_stats[i++] =
ffb5df6c
JP		 6434 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6435 le32_to_cpu(stats->rmac_udp);
541ae68f 6436 tmp_stats[i++] =
ffb5df6c
JP		 6437 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6438 le32_to_cpu(stats->rmac_err_drp_udp);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6454 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6455 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6456 tmp_stats[i++] =
ffb5df6c
JP		 6457 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6458 le32_to_cpu(stats->rmac_pause_cnt);
6459 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6460 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6461 tmp_stats[i++] =
ffb5df6c
JP		 6462 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6463 le32_to_cpu(stats->rmac_accepted_ip);
6464 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6465 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6482 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6483
6484 /* Enhanced statistics exist only for Hercules */
d44570e4 6485 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6486 tmp_stats[i++] =
ffb5df6c 6487 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6488 tmp_stats[i++] =
ffb5df6c 6489 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6490 tmp_stats[i++] =
ffb5df6c
JP		 6491 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6495 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6496 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6503 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6504 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6505 }
6506
7ba013ac 6507 tmp_stats[i++] = 0;
ffb5df6c
JP		 6508 tmp_stats[i++] = swstats->single_ecc_errs;
6509 tmp_stats[i++] = swstats->double_ecc_errs;
6510 tmp_stats[i++] = swstats->parity_err_cnt;
6511 tmp_stats[i++] = swstats->serious_err_cnt;
6512 tmp_stats[i++] = swstats->soft_reset_cnt;
6513 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6514 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6515 tmp_stats[i++] = swstats->ring_full_cnt[k];
6516 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6517 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6518 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6519 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6520 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6521 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6522 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6523 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6524 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6525 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6526 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6527 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6528 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6529 tmp_stats[i++] = swstats->sending_both;
6530 tmp_stats[i++] = swstats->outof_sequence_pkts;
6531 tmp_stats[i++] = swstats->flush_max_pkts;
6532 if (swstats->num_aggregations) {
6533 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6534 int count = 0;
6aa20a22 6535 /*
bd1034f0
AR		 6536 * Since 64-bit divide does not work on all platforms,
6537 * do repeated subtraction.
6538 */
ffb5df6c
JP		 6539 while (tmp >= swstats->num_aggregations) {
6540 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6541 count++;
6542 }
6543 tmp_stats[i++] = count;
d44570e4 6544 } else
bd1034f0 6545 tmp_stats[i++] = 0;
ffb5df6c
JP		 6546 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6547 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6548 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6549 tmp_stats[i++] = swstats->mem_allocated;
6550 tmp_stats[i++] = swstats->mem_freed;
6551 tmp_stats[i++] = swstats->link_up_cnt;
6552 tmp_stats[i++] = swstats->link_down_cnt;
6553 tmp_stats[i++] = swstats->link_up_time;
6554 tmp_stats[i++] = swstats->link_down_time;
6555
6556 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6557 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6558 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6559 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6560 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6561
6562 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6563 tmp_stats[i++] = swstats->rx_abort_cnt;
6564 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6565 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6566 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6567 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6568 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6569 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6570 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6571 tmp_stats[i++] = swstats->tda_err_cnt;
6572 tmp_stats[i++] = swstats->pfc_err_cnt;
6573 tmp_stats[i++] = swstats->pcc_err_cnt;
6574 tmp_stats[i++] = swstats->tti_err_cnt;
6575 tmp_stats[i++] = swstats->tpa_err_cnt;
6576 tmp_stats[i++] = swstats->sm_err_cnt;
6577 tmp_stats[i++] = swstats->lso_err_cnt;
6578 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6579 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6580 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6581 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6582 tmp_stats[i++] = swstats->rc_err_cnt;
6583 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6584 tmp_stats[i++] = swstats->rpa_err_cnt;
6585 tmp_stats[i++] = swstats->rda_err_cnt;
6586 tmp_stats[i++] = swstats->rti_err_cnt;
6587 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6588}
6589
ac1f60db 6590static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6591{
d44570e4 6592 return XENA_REG_SPACE;
1da177e4
LT		 6593}
6594
6595
d44570e4 6596static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6597{
4cf1653a 6598 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6599
d44570e4 6600 return sp->rx_csum;
1da177e4 6601}
ac1f60db
AB		 6602
6603static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6604{
4cf1653a 6605 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6606
6607 if (data)
6608 sp->rx_csum = 1;
6609 else
6610 sp->rx_csum = 0;
6611
6612 return 0;
6613}
ac1f60db
AB		 6614
6615static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6616{
d44570e4 6617 return XENA_EEPROM_SPACE;
1da177e4
LT		 6618}
6619
b9f2c044 6620static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6621{
4cf1653a 6622 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6623
6624 switch (sset) {
6625 case ETH_SS_TEST:
6626 return S2IO_TEST_LEN;
6627 case ETH_SS_STATS:
d44570e4 6628 switch (sp->device_type) {
b9f2c044
JG		 6629 case XFRAME_I_DEVICE:
6630 return XFRAME_I_STAT_LEN;
6631 case XFRAME_II_DEVICE:
6632 return XFRAME_II_STAT_LEN;
6633 default:
6634 return 0;
6635 }
6636 default:
6637 return -EOPNOTSUPP;
6638 }
1da177e4 6639}
ac1f60db
AB		 6640
6641static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6642 u32 stringset, u8 *data)
1da177e4 6643{
fa1f0cb3 6644 int stat_size = 0;
4cf1653a 6645 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6646
1da177e4
LT		 6647 switch (stringset) {
6648 case ETH_SS_TEST:
6649 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6650 break;
6651 case ETH_SS_STATS:
fa1f0cb3 6652 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6653 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6654 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6655 memcpy(data + stat_size,
d44570e4
JP		 6656 &ethtool_enhanced_stats_keys,
6657 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6658 stat_size += sizeof(ethtool_enhanced_stats_keys);
6659 }
6660
6661 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6662 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6663 }
6664}
1da177e4 6665
ac1f60db 6666static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6667{
6668 if (data)
6669 dev->features |= NETIF_F_IP_CSUM;
6670 else
6671 dev->features &= ~NETIF_F_IP_CSUM;
6672
6673 return 0;
6674}
6675
75c30b13
AR		 6676static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6677{
6678 return (dev->features & NETIF_F_TSO) != 0;
6679}
6680static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6681{
6682 if (data)
6683 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6684 else
6685 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6686
6687 return 0;
6688}
1da177e4 6689
7282d491 6690static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6691 .get_settings = s2io_ethtool_gset,
6692 .set_settings = s2io_ethtool_sset,
6693 .get_drvinfo = s2io_ethtool_gdrvinfo,
6694 .get_regs_len = s2io_ethtool_get_regs_len,
6695 .get_regs = s2io_ethtool_gregs,
6696 .get_link = ethtool_op_get_link,
6697 .get_eeprom_len = s2io_get_eeprom_len,
6698 .get_eeprom = s2io_ethtool_geeprom,
6699 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6700 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6701 .get_pauseparam = s2io_ethtool_getpause_data,
6702 .set_pauseparam = s2io_ethtool_setpause_data,
6703 .get_rx_csum = s2io_ethtool_get_rx_csum,
6704 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6705 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6706 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6707 .get_tso = s2io_ethtool_op_get_tso,
6708 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6709 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6710 .self_test = s2io_ethtool_test,
6711 .get_strings = s2io_ethtool_get_strings,
6712 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6713 .get_ethtool_stats = s2io_get_ethtool_stats,
6714 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6715};
6716
6717/**
20346722 6718 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6719 * @dev : Device pointer.
6720 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6721 * a proprietary structure used to pass information to the driver.
6722 * @cmd : This is used to distinguish between the different commands that
6723 * can be passed to the IOCTL functions.
6724 * Description:
20346722
K		 6725 * Currently there are no special functionality supported in IOCTL, hence
6726 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6727 */
6728
ac1f60db 6729static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6730{
6731 return -EOPNOTSUPP;
6732}
6733
6734/**
6735 * s2io_change_mtu - entry point to change MTU size for the device.
6736 * @dev : device pointer.
6737 * @new_mtu : the new MTU size for the device.
6738 * Description: A driver entry point to change MTU size for the device.
6739 * Before changing the MTU the device must be stopped.
6740 * Return value:
6741 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6742 * file on failure.
6743 */
6744
ac1f60db 6745static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6746{
4cf1653a 6747 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6748 int ret = 0;
1da177e4
LT		 6749
6750 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6751 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6752 return -EPERM;
6753 }
6754
1da177e4 6755 dev->mtu = new_mtu;
d8892c6e 6756 if (netif_running(dev)) {
3a3d5756 6757 s2io_stop_all_tx_queue(sp);
e6a8fee2 6758 s2io_card_down(sp);
9f74ffde
SH		 6759 ret = s2io_card_up(sp);
6760 if (ret) {
d8892c6e 6761 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6762 __func__);
9f74ffde 6763 return ret;
d8892c6e 6764 }
3a3d5756 6765 s2io_wake_all_tx_queue(sp);
d8892c6e 6766 } else { /* Device is down */
1ee6dd77 6767 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6768 u64 val64 = new_mtu;
6769
6770 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6771 }
1da177e4 6772
9f74ffde 6773 return ret;
1da177e4
LT		 6774}
6775
1da177e4
LT		 6776/**
6777 * s2io_set_link - Set the LInk status
6778 * @data: long pointer to device private structue
6779 * Description: Sets the link status for the adapter
6780 */
6781
c4028958 6782static void s2io_set_link(struct work_struct *work)
1da177e4 6783{
d44570e4
JP		 6784 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6785 set_link_task);
1da177e4 6786 struct net_device *dev = nic->dev;
1ee6dd77 6787 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6788 register u64 val64;
6789 u16 subid;
6790
22747d6b
FR		 6791 rtnl_lock();
6792
6793 if (!netif_running(dev))
6794 goto out_unlock;
6795
92b84437 6796 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6797 /* The card is being reset, no point doing anything */
22747d6b 6798 goto out_unlock;
1da177e4
LT		 6799 }
6800
6801 subid = nic->pdev->subsystem_device;
a371a07d
K		 6802 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6803 /*
6804 * Allow a small delay for the NICs self initiated
6805 * cleanup to complete.
6806 */
6807 msleep(100);
6808 }
1da177e4
LT		 6809
6810 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6811 if (LINK_IS_UP(val64)) {
6812 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6813 if (verify_xena_quiescence(nic)) {
6814 val64 = readq(&bar0->adapter_control);
6815 val64 |= ADAPTER_CNTL_EN;
1da177e4 6816 writeq(val64, &bar0->adapter_control);
19a60522 6817 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6818 nic->device_type, subid)) {
19a60522
SS		 6819 val64 = readq(&bar0->gpio_control);
6820 val64 |= GPIO_CTRL_GPIO_0;
6821 writeq(val64, &bar0->gpio_control);
6822 val64 = readq(&bar0->gpio_control);
6823 } else {
6824 val64 |= ADAPTER_LED_ON;
6825 writeq(val64, &bar0->adapter_control);
a371a07d 6826 }
f957bcf0 6827 nic->device_enabled_once = true;
19a60522 6828 } else {
9e39f7c5
JP		 6829 DBG_PRINT(ERR_DBG,
6830 "%s: Error: device is not Quiescent\n",
6831 dev->name);
3a3d5756 6832 s2io_stop_all_tx_queue(nic);
1da177e4 6833 }
19a60522 6834 }
92c48799
SS		 6835 val64 = readq(&bar0->adapter_control);
6836 val64 |= ADAPTER_LED_ON;
6837 writeq(val64, &bar0->adapter_control);
6838 s2io_link(nic, LINK_UP);
19a60522
SS		 6839 } else {
6840 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6841 subid)) {
6842 val64 = readq(&bar0->gpio_control);
6843 val64 &= ~GPIO_CTRL_GPIO_0;
6844 writeq(val64, &bar0->gpio_control);
6845 val64 = readq(&bar0->gpio_control);
1da177e4 6846 }
92c48799
SS		 6847 /* turn off LED */
6848 val64 = readq(&bar0->adapter_control);
d44570e4 6849 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6850 writeq(val64, &bar0->adapter_control);
19a60522 6851 s2io_link(nic, LINK_DOWN);
1da177e4 6852 }
92b84437 6853 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6854
6855out_unlock:
d8d70caf 6856 rtnl_unlock();
1da177e4
LT		 6857}
6858
1ee6dd77 6859static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6860 struct buffAdd *ba,
6861 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6862 u64 *temp2, int size)
5d3213cc
AR		 6863{
6864 struct net_device *dev = sp->dev;
491abf25 6865 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6866
6867 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6868 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6869 /* allocate skb */
6870 if (*skb) {
6871 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6872 /*
6873 * As Rx frame are not going to be processed,
6874 * using same mapped address for the Rxd
6875 * buffer pointer
6876 */
6d517a27 6877 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6878 } else {
6879 *skb = dev_alloc_skb(size);
6880 if (!(*skb)) {
9e39f7c5
JP		 6881 DBG_PRINT(INFO_DBG,
6882 "%s: Out of memory to allocate %s\n",
6883 dev->name, "1 buf mode SKBs");
ffb5df6c 6884 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6885 return -ENOMEM ;
6886 }
ffb5df6c 6887 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6888 /* storing the mapped addr in a temp variable
6889 * such it will be used for next rxd whose
6890 * Host Control is NULL
6891 */
6d517a27 6892 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6893 pci_map_single(sp->pdev, (*skb)->data,
6894 size - NET_IP_ALIGN,
6895 PCI_DMA_FROMDEVICE);
8d8bb39b 6896 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6897 goto memalloc_failed;
5d3213cc
AR		 6898 rxdp->Host_Control = (unsigned long) (*skb);
6899 }
6900 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6901 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6902 /* Two buffer Mode */
6903 if (*skb) {
6d517a27
VP		 6904 rxdp3->Buffer2_ptr = *temp2;
6905 rxdp3->Buffer0_ptr = *temp0;
6906 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6907 } else {
6908 *skb = dev_alloc_skb(size);
2ceaac75 6909 if (!(*skb)) {
9e39f7c5
JP		 6910 DBG_PRINT(INFO_DBG,
6911 "%s: Out of memory to allocate %s\n",
6912 dev->name,
6913 "2 buf mode SKBs");
ffb5df6c 6914 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6915 return -ENOMEM;
6916 }
ffb5df6c 6917 stats->mem_allocated += (*skb)->truesize;
6d517a27 6918 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6919 pci_map_single(sp->pdev, (*skb)->data,
6920 dev->mtu + 4,
6921 PCI_DMA_FROMDEVICE);
8d8bb39b 6922 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6923 goto memalloc_failed;
6d517a27 6924 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6925 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6926 PCI_DMA_FROMDEVICE);
8d8bb39b 6927 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6928 rxdp3->Buffer0_ptr)) {
6929 pci_unmap_single(sp->pdev,
6930 (dma_addr_t)rxdp3->Buffer2_ptr,
6931 dev->mtu + 4,
6932 PCI_DMA_FROMDEVICE);
491abf25
VP		 6933 goto memalloc_failed;
6934 }
5d3213cc
AR		 6935 rxdp->Host_Control = (unsigned long) (*skb);
6936
6937 /* Buffer-1 will be dummy buffer not used */
6d517a27 6938 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6939 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6940 PCI_DMA_FROMDEVICE);
8d8bb39b 6941 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6942 rxdp3->Buffer1_ptr)) {
6943 pci_unmap_single(sp->pdev,
6944 (dma_addr_t)rxdp3->Buffer0_ptr,
6945 BUF0_LEN, PCI_DMA_FROMDEVICE);
6946 pci_unmap_single(sp->pdev,
6947 (dma_addr_t)rxdp3->Buffer2_ptr,
6948 dev->mtu + 4,
6949 PCI_DMA_FROMDEVICE);
491abf25
VP		 6950 goto memalloc_failed;
6951 }
5d3213cc
AR		 6952 }
6953 }
6954 return 0;
d44570e4
JP		 6955
6956memalloc_failed:
6957 stats->pci_map_fail_cnt++;
6958 stats->mem_freed += (*skb)->truesize;
6959 dev_kfree_skb(*skb);
6960 return -ENOMEM;
5d3213cc 6961}
491abf25 6962
1ee6dd77
RB		 6963static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6964 int size)
5d3213cc
AR		 6965{
6966 struct net_device *dev = sp->dev;
6967 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6968 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6969 } else if (sp->rxd_mode == RXD_MODE_3B) {
6970 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6971 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 6972 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 6973 }
6974}
6975
1ee6dd77 6976static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6977{
6978 int i, j, k, blk_cnt = 0, size;
5d3213cc 6979 struct config_param *config = &sp->config;
ffb5df6c 6980 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 6981 struct net_device *dev = sp->dev;
1ee6dd77 6982 struct RxD_t *rxdp = NULL;
5d3213cc 6983 struct sk_buff *skb = NULL;
1ee6dd77 6984 struct buffAdd *ba = NULL;
5d3213cc
AR		 6985 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6986
6987 /* Calculate the size based on ring mode */
6988 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6989 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6990 if (sp->rxd_mode == RXD_MODE_1)
6991 size += NET_IP_ALIGN;
6992 else if (sp->rxd_mode == RXD_MODE_3B)
6993 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6994
6995 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 6996 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6997 struct ring_info *ring = &mac_control->rings[i];
6998
d44570e4 6999 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 7000
7001 for (j = 0; j < blk_cnt; j++) {
7002 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7003 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7004 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7005 ba = &ring->ba[j][k];
d44570e4
JP		 7006 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7007 (u64 *)&temp0_64,
7008 (u64 *)&temp1_64,
7009 (u64 *)&temp2_64,
7010 size) == -ENOMEM) {
ac1f90d6
SS		 7011 return 0;
7012 }
5d3213cc
AR		 7013
7014 set_rxd_buffer_size(sp, rxdp, size);
7015 wmb();
7016 /* flip the Ownership bit to Hardware */
7017 rxdp->Control_1 |= RXD_OWN_XENA;
7018 }
7019 }
7020 }
7021 return 0;
7022
7023}
7024
d44570e4 7025static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7026{
e6a8fee2 7027 int ret = 0;
c92ca04b 7028 struct net_device *dev = sp->dev;
e6a8fee2 7029 int err = 0;
1da177e4 7030
eaae7f72 7031 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7032 ret = s2io_enable_msi_x(sp);
7033 if (ret) {
7034 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7035 sp->config.intr_type = INTA;
20346722 7036 }
1da177e4 7037
d44570e4
JP		 7038 /*
7039 * Store the values of the MSIX table in
7040 * the struct s2io_nic structure
7041 */
e6a8fee2 7042 store_xmsi_data(sp);
c92ca04b 7043
e6a8fee2 7044 /* After proper initialization of H/W, register ISR */
eaae7f72 7045 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7046 int i, msix_rx_cnt = 0;
7047
f61e0a35
SH		 7048 for (i = 0; i < sp->num_entries; i++) {
7049 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7050 if (sp->s2io_entries[i].type ==
d44570e4 7051 MSIX_RING_TYPE) {
ac731ab6
SH		 7052 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7053 dev->name, i);
7054 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7055 s2io_msix_ring_handle,
7056 0,
7057 sp->desc[i],
7058 sp->s2io_entries[i].arg);
ac731ab6 7059 } else if (sp->s2io_entries[i].type ==
d44570e4 7060 MSIX_ALARM_TYPE) {
ac731ab6 7061 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7062 dev->name, i);
ac731ab6 7063 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7064 s2io_msix_fifo_handle,
7065 0,
7066 sp->desc[i],
7067 sp->s2io_entries[i].arg);
ac731ab6 7068
fb6a825b 7069 }
ac731ab6
SH		 7070 /* if either data or addr is zero print it. */
7071 if (!(sp->msix_info[i].addr &&
d44570e4 7072 sp->msix_info[i].data)) {
ac731ab6 7073 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7074 "%s @Addr:0x%llx Data:0x%llx\n",
7075 sp->desc[i],
7076 (unsigned long long)
7077 sp->msix_info[i].addr,
7078 (unsigned long long)
7079 ntohl(sp->msix_info[i].data));
ac731ab6 7080 } else
fb6a825b 7081 msix_rx_cnt++;
ac731ab6
SH		 7082 if (err) {
7083 remove_msix_isr(sp);
7084
7085 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7086 "%s:MSI-X-%d registration "
7087 "failed\n", dev->name, i);
ac731ab6
SH		 7088
7089 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7090 "%s: Defaulting to INTA\n",
7091 dev->name);
ac731ab6
SH		 7092 sp->config.intr_type = INTA;
7093 break;
fb6a825b 7094 }
ac731ab6
SH		 7095 sp->s2io_entries[i].in_use =
7096 MSIX_REGISTERED_SUCCESS;
c92ca04b 7097 }
e6a8fee2 7098 }
18b2b7bd 7099 if (!err) {
6cef2b8e 7100 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7101 DBG_PRINT(INFO_DBG,
7102 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7103 }
e6a8fee2 7104 }
eaae7f72 7105 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7106 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7107 sp->name, dev);
e6a8fee2
AR		 7108 if (err) {
7109 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7110 dev->name);
7111 return -1;
7112 }
7113 }
7114 return 0;
7115}
d44570e4
JP		 7116
7117static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7118{
18b2b7bd
SH		 7119 if (sp->config.intr_type == MSI_X)
7120 remove_msix_isr(sp);
7121 else
7122 remove_inta_isr(sp);
e6a8fee2
AR		 7123}
7124
d44570e4 7125static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7126{
7127 int cnt = 0;
1ee6dd77 7128 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7129 register u64 val64 = 0;
5f490c96
SH		 7130 struct config_param *config;
7131 config = &sp->config;
e6a8fee2 7132
9f74ffde
SH		 7133 if (!is_s2io_card_up(sp))
7134 return;
7135
e6a8fee2
AR		 7136 del_timer_sync(&sp->alarm_timer);
7137 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7138 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7139 msleep(50);
92b84437 7140 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7141
5f490c96 7142 /* Disable napi */
f61e0a35
SH		 7143 if (sp->config.napi) {
7144 int off = 0;
7145 if (config->intr_type == MSI_X) {
7146 for (; off < sp->config.rx_ring_num; off++)
7147 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7148 }
f61e0a35
SH		 7149 else
7150 napi_disable(&sp->napi);
7151 }
5f490c96 7152
e6a8fee2 7153 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7154 if (do_io)
7155 stop_nic(sp);
e6a8fee2
AR		 7156
7157 s2io_rem_isr(sp);
1da177e4 7158
01e16faa
SH		 7159 /* stop the tx queue, indicate link down */
7160 s2io_link(sp, LINK_DOWN);
7161
1da177e4 7162 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7163 while (do_io) {
5d3213cc
AR		 7164 /* As per the HW requirement we need to replenish the
7165 * receive buffer to avoid the ring bump. Since there is
7166 * no intention of processing the Rx frame at this pointwe are
7167 * just settting the ownership bit of rxd in Each Rx
7168 * ring to HW and set the appropriate buffer size
7169 * based on the ring mode
7170 */
7171 rxd_owner_bit_reset(sp);
7172
1da177e4 7173 val64 = readq(&bar0->adapter_status);
19a60522 7174 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7175 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7176 break;
1da177e4
LT		 7177 }
7178
7179 msleep(50);
7180 cnt++;
7181 if (cnt == 10) {
9e39f7c5
JP		 7182 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7183 "adapter status reads 0x%llx\n",
d44570e4 7184 (unsigned long long)val64);
1da177e4
LT		 7185 break;
7186 }
d796fdb7
LV		 7187 }
7188 if (do_io)
7189 s2io_reset(sp);
1da177e4 7190
7ba013ac 7191 /* Free all Tx buffers */
1da177e4 7192 free_tx_buffers(sp);
7ba013ac
K		 7193
7194 /* Free all Rx buffers */
1da177e4
LT		 7195 free_rx_buffers(sp);
7196
92b84437 7197 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7198}
7199
d44570e4 7200static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7201{
7202 do_s2io_card_down(sp, 1);
7203}
7204
d44570e4 7205static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7206{
cc6e7c44 7207 int i, ret = 0;
1da177e4 7208 struct config_param *config;
ffb5df6c 7209 struct mac_info *mac_control;
d44570e4 7210 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7211 u16 interruptible;
1da177e4
LT		 7212
7213 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7214 ret = init_nic(sp);
7215 if (ret != 0) {
1da177e4
LT		 7216 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7217 dev->name);
9f74ffde
SH		 7218 if (ret != -EIO)
7219 s2io_reset(sp);
7220 return ret;
1da177e4
LT		 7221 }
7222
20346722
K		 7223 /*
7224 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7225 * Rx ring and initializing buffers into 30 Rx blocks
7226 */
1da177e4 7227 config = &sp->config;
ffb5df6c 7228 mac_control = &sp->mac_control;
1da177e4
LT		 7229
7230 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7231 struct ring_info *ring = &mac_control->rings[i];
7232
7233 ring->mtu = dev->mtu;
7234 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7235 if (ret) {
1da177e4
LT		 7236 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7237 dev->name);
7238 s2io_reset(sp);
7239 free_rx_buffers(sp);
7240 return -ENOMEM;
7241 }
7242 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7243 ring->rx_bufs_left);
1da177e4 7244 }
5f490c96
SH		 7245
7246 /* Initialise napi */
f61e0a35 7247 if (config->napi) {
f61e0a35
SH		 7248 if (config->intr_type == MSI_X) {
7249 for (i = 0; i < sp->config.rx_ring_num; i++)
7250 napi_enable(&sp->mac_control.rings[i].napi);
7251 } else {
7252 napi_enable(&sp->napi);
7253 }
7254 }
5f490c96 7255
19a60522
SS		 7256 /* Maintain the state prior to the open */
7257 if (sp->promisc_flg)
7258 sp->promisc_flg = 0;
7259 if (sp->m_cast_flg) {
7260 sp->m_cast_flg = 0;
d44570e4 7261 sp->all_multi_pos = 0;
19a60522 7262 }
1da177e4
LT		 7263
7264 /* Setting its receive mode */
7265 s2io_set_multicast(dev);
7266
7d3d0439 7267 if (sp->lro) {
b41477f3 7268 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7269 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7270 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7271 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7272 sp->lro_max_aggr_per_sess = lro_max_pkts;
7273 }
7274
1da177e4
LT		 7275 /* Enable Rx Traffic and interrupts on the NIC */
7276 if (start_nic(sp)) {
7277 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7278 s2io_reset(sp);
e6a8fee2
AR		 7279 free_rx_buffers(sp);
7280 return -ENODEV;
7281 }
7282
7283 /* Add interrupt service routine */
7284 if (s2io_add_isr(sp) != 0) {
eaae7f72 7285 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7286 s2io_rem_isr(sp);
7287 s2io_reset(sp);
1da177e4
LT		 7288 free_rx_buffers(sp);
7289 return -ENODEV;
7290 }
7291
25fff88e
K		 7292 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7293
01e16faa
SH		 7294 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7295
e6a8fee2 7296 /* Enable select interrupts */
9caab458 7297 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7298 if (sp->config.intr_type != INTA) {
7299 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7300 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7301 } else {
e6a8fee2 7302 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7303 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7304 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7305 }
7306
1da177e4
LT		 7307 return 0;
7308}
7309
20346722 7310/**
1da177e4
LT		 7311 * s2io_restart_nic - Resets the NIC.
7312 * @data : long pointer to the device private structure
7313 * Description:
7314 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7315 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7316 * the run time of the watch dog routine which is run holding a
7317 * spin lock.
7318 */
7319
c4028958 7320static void s2io_restart_nic(struct work_struct *work)
1da177e4 7321{
1ee6dd77 7322 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7323 struct net_device *dev = sp->dev;
1da177e4 7324
22747d6b
FR		 7325 rtnl_lock();
7326
7327 if (!netif_running(dev))
7328 goto out_unlock;
7329
e6a8fee2 7330 s2io_card_down(sp);
1da177e4 7331 if (s2io_card_up(sp)) {
d44570e4 7332 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7333 }
3a3d5756 7334 s2io_wake_all_tx_queue(sp);
d44570e4 7335 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7336out_unlock:
7337 rtnl_unlock();
1da177e4
LT		 7338}
7339
20346722
K		 7340/**
7341 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7342 * @dev : Pointer to net device structure
7343 * Description:
7344 * This function is triggered if the Tx Queue is stopped
7345 * for a pre-defined amount of time when the Interface is still up.
7346 * If the Interface is jammed in such a situation, the hardware is
7347 * reset (by s2io_close) and restarted again (by s2io_open) to
7348 * overcome any problem that might have been caused in the hardware.
7349 * Return value:
7350 * void
7351 */
7352
7353static void s2io_tx_watchdog(struct net_device *dev)
7354{
4cf1653a 7355 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7356 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7357
7358 if (netif_carrier_ok(dev)) {
ffb5df6c 7359 swstats->watchdog_timer_cnt++;
1da177e4 7360 schedule_work(&sp->rst_timer_task);
ffb5df6c 7361 swstats->soft_reset_cnt++;
1da177e4
LT		 7362 }
7363}
7364
7365/**
7366 * rx_osm_handler - To perform some OS related operations on SKB.
7367 * @sp: private member of the device structure,pointer to s2io_nic structure.
7368 * @skb : the socket buffer pointer.
7369 * @len : length of the packet
7370 * @cksum : FCS checksum of the frame.
7371 * @ring_no : the ring from which this RxD was extracted.
20346722 7372 * Description:
b41477f3 7373 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7374 * some OS related operations on the SKB before passing it to the upper
7375 * layers. It mainly checks if the checksum is OK, if so adds it to the
7376 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7377 * to the upper layer. If the checksum is wrong, it increments the Rx
7378 * packet error count, frees the SKB and returns error.
7379 * Return value:
7380 * SUCCESS on success and -1 on failure.
7381 */
1ee6dd77 7382static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7383{
1ee6dd77 7384 struct s2io_nic *sp = ring_data->nic;
d44570e4 7385 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7386 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7387 ((unsigned long)rxdp->Host_Control);
20346722 7388 int ring_no = ring_data->ring_no;
1da177e4 7389 u16 l3_csum, l4_csum;
863c11a9 7390 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7391 struct lro *uninitialized_var(lro);
f9046eb3 7392 u8 err_mask;
ffb5df6c 7393 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7394
20346722 7395 skb->dev = dev;
c92ca04b 7396
863c11a9 7397 if (err) {
bd1034f0 7398 /* Check for parity error */
d44570e4 7399 if (err & 0x1)
ffb5df6c 7400 swstats->parity_err_cnt++;
d44570e4 7401
f9046eb3 7402 err_mask = err >> 48;
d44570e4
JP		 7403 switch (err_mask) {
7404 case 1:
ffb5df6c 7405 swstats->rx_parity_err_cnt++;
491976b2
SH		 7406 break;
7407
d44570e4 7408 case 2:
ffb5df6c 7409 swstats->rx_abort_cnt++;
491976b2
SH		 7410 break;
7411
d44570e4 7412 case 3:
ffb5df6c 7413 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7414 break;
7415
d44570e4 7416 case 4:
ffb5df6c 7417 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7418 break;
7419
d44570e4 7420 case 5:
ffb5df6c 7421 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7422 break;
7423
d44570e4 7424 case 6:
ffb5df6c 7425 swstats->rx_fcs_err_cnt++;
491976b2 7426 break;
bd1034f0 7427
d44570e4 7428 case 7:
ffb5df6c 7429 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7430 break;
7431
d44570e4 7432 case 8:
ffb5df6c 7433 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7434 break;
7435
d44570e4 7436 case 15:
ffb5df6c 7437 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7438 break;
7439 }
863c11a9 7440 /*
d44570e4
JP		 7441 * Drop the packet if bad transfer code. Exception being
7442 * 0x5, which could be due to unsupported IPv6 extension header.
7443 * In this case, we let stack handle the packet.
7444 * Note that in this case, since checksum will be incorrect,
7445 * stack will validate the same.
7446 */
f9046eb3
OH		 7447 if (err_mask != 0x5) {
7448 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7449 dev->name, err_mask);
dc56e634 7450 dev->stats.rx_crc_errors++;
ffb5df6c 7451 swstats->mem_freed
491976b2 7452 += skb->truesize;
863c11a9 7453 dev_kfree_skb(skb);
0425b46a 7454 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7455 rxdp->Host_Control = 0;
7456 return 0;
7457 }
20346722 7458 }
1da177e4 7459
20346722 7460 /* Updating statistics */
0425b46a 7461 ring_data->rx_packets++;
20346722 7462 rxdp->Host_Control = 0;
da6971d8
AR		 7463 if (sp->rxd_mode == RXD_MODE_1) {
7464 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7465
0425b46a 7466 ring_data->rx_bytes += len;
da6971d8
AR		 7467 skb_put(skb, len);
7468
6d517a27 7469 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7470 int get_block = ring_data->rx_curr_get_info.block_index;
7471 int get_off = ring_data->rx_curr_get_info.offset;
7472 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7473 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7474 unsigned char *buff = skb_push(skb, buf0_len);
7475
1ee6dd77 7476 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7477 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7478 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7479 skb_put(skb, buf2_len);
da6971d8 7480 }
20346722 7481
d44570e4
JP		 7482 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7483 ((!ring_data->lro) ||
7484 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7485 (sp->rx_csum)) {
7486 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7487 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7488 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7489 /*
1da177e4
LT		 7490 * NIC verifies if the Checksum of the received
7491 * frame is Ok or not and accordingly returns
7492 * a flag in the RxD.
7493 */
7494 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7495 if (ring_data->lro) {
7d3d0439
RA		 7496 u32 tcp_len;
7497 u8 *tcp;
7498 int ret = 0;
7499
0425b46a 7500 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7501 skb->data, &tcp,
7502 &tcp_len, &lro,
7503 rxdp, sp);
7d3d0439 7504 switch (ret) {
d44570e4
JP		 7505 case 3: /* Begin anew */
7506 lro->parent = skb;
7507 goto aggregate;
7508 case 1: /* Aggregate */
7509 lro_append_pkt(sp, lro, skb, tcp_len);
7510 goto aggregate;
7511 case 4: /* Flush session */
7512 lro_append_pkt(sp, lro, skb, tcp_len);
7513 queue_rx_frame(lro->parent,
7514 lro->vlan_tag);
7515 clear_lro_session(lro);
ffb5df6c 7516 swstats->flush_max_pkts++;
d44570e4
JP		 7517 goto aggregate;
7518 case 2: /* Flush both */
7519 lro->parent->data_len = lro->frags_len;
ffb5df6c 7520 swstats->sending_both++;
d44570e4
JP		 7521 queue_rx_frame(lro->parent,
7522 lro->vlan_tag);
7523 clear_lro_session(lro);
7524 goto send_up;
7525 case 0: /* sessions exceeded */
7526 case -1: /* non-TCP or not L2 aggregatable */
7527 case 5: /*
7528 * First pkt in session not
7529 * L3/L4 aggregatable
7530 */
7531 break;
7532 default:
7533 DBG_PRINT(ERR_DBG,
7534 "%s: Samadhana!!\n",
7535 __func__);
7536 BUG();
7d3d0439
RA		 7537 }
7538 }
1da177e4 7539 } else {
20346722
K		 7540 /*
7541 * Packet with erroneous checksum, let the
1da177e4
LT		 7542 * upper layers deal with it.
7543 */
7544 skb->ip_summed = CHECKSUM_NONE;
7545 }
cdb5bf02 7546 } else
1da177e4 7547 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7548
ffb5df6c 7549 swstats->mem_freed += skb->truesize;
7d3d0439 7550send_up:
0c8dfc83 7551 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7552 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7553aggregate:
0425b46a 7554 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7555 return SUCCESS;
7556}
7557
7558/**
7559 * s2io_link - stops/starts the Tx queue.
7560 * @sp : private member of the device structure, which is a pointer to the
7561 * s2io_nic structure.
7562 * @link : inidicates whether link is UP/DOWN.
7563 * Description:
7564 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7565 * status of the NIC is is down or up. This is called by the Alarm
7566 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7567 * Return value:
7568 * void.
7569 */
7570
d44570e4 7571static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7572{
d44570e4 7573 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7574 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7575
7576 if (link != sp->last_link_state) {
b7c5678f 7577 init_tti(sp, link);
1da177e4
LT		 7578 if (link == LINK_DOWN) {
7579 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7580 s2io_stop_all_tx_queue(sp);
1da177e4 7581 netif_carrier_off(dev);
ffb5df6c
JP		 7582 if (swstats->link_up_cnt)
7583 swstats->link_up_time =
7584 jiffies - sp->start_time;
7585 swstats->link_down_cnt++;
1da177e4
LT		 7586 } else {
7587 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7588 if (swstats->link_down_cnt)
7589 swstats->link_down_time =
d44570e4 7590 jiffies - sp->start_time;
ffb5df6c 7591 swstats->link_up_cnt++;
1da177e4 7592 netif_carrier_on(dev);
3a3d5756 7593 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7594 }
7595 }
7596 sp->last_link_state = link;
491976b2 7597 sp->start_time = jiffies;
1da177e4
LT		 7598}
7599
20346722
K		 7600/**
7601 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7602 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7603 * s2io_nic structure.
7604 * Description:
7605 * This function initializes a few of the PCI and PCI-X configuration registers
7606 * with recommended values.
7607 * Return value:
7608 * void
7609 */
7610
d44570e4 7611static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7612{
20346722 7613 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7614
7615 /* Enable Data Parity Error Recovery in PCI-X command register. */
7616 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7617 &(pcix_cmd));
1da177e4 7618 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7619 (pcix_cmd | 1));
1da177e4 7620 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7621 &(pcix_cmd));
1da177e4
LT		 7622
7623 /* Set the PErr Response bit in PCI command register. */
7624 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7625 pci_write_config_word(sp->pdev, PCI_COMMAND,
7626 (pci_cmd | PCI_COMMAND_PARITY));
7627 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7628}
7629
3a3d5756 7630static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7631 u8 *dev_multiq)
9dc737a7 7632{
d44570e4 7633 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7634 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7635 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7636
7637 if (tx_fifo_num < 1)
7638 tx_fifo_num = 1;
7639 else
7640 tx_fifo_num = MAX_TX_FIFOS;
7641
9e39f7c5 7642 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7643 }
2fda096d 7644
6cfc482b 7645 if (multiq)
3a3d5756 7646 *dev_multiq = multiq;
6cfc482b
SH		 7647
7648 if (tx_steering_type && (1 == tx_fifo_num)) {
7649 if (tx_steering_type != TX_DEFAULT_STEERING)
7650 DBG_PRINT(ERR_DBG,
9e39f7c5 7651 "Tx steering is not supported with "
d44570e4 7652 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7653 tx_steering_type = NO_STEERING;
7654 }
7655
7656 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7657 (tx_steering_type > TX_DEFAULT_STEERING)) {
7658 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7659 "Requested transmit steering not supported\n");
7660 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7661 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7662 }
7663
0425b46a 7664 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7665 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7666 "Requested number of rx rings not supported\n");
7667 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7668 MAX_RX_RINGS);
0425b46a 7669 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7670 }
0425b46a 7671
eccb8628 7672 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7673 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7674 "Defaulting to INTA\n");
7675 *dev_intr_type = INTA;
7676 }
596c5c97 7677
9dc737a7 7678 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7679 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7680 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7681 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7682 "Defaulting to INTA\n");
9dc737a7
AR		 7683 *dev_intr_type = INTA;
7684 }
fb6a825b 7685
6d517a27 7686 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7687 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7688 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7689 rx_ring_mode = 1;
9dc737a7
AR		 7690 }
7691 return SUCCESS;
7692}
7693
9fc93a41
SS		 7694/**
7695 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7696 * or Traffic class respectively.
b7c5678f 7697 * @nic: device private variable
9fc93a41
SS		 7698 * Description: The function configures the receive steering to
7699 * desired receive ring.
7700 * Return Value: SUCCESS on success and
7701 * '-1' on failure (endian settings incorrect).
7702 */
7703static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7704{
7705 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7706 register u64 val64 = 0;
7707
7708 if (ds_codepoint > 63)
7709 return FAILURE;
7710
7711 val64 = RTS_DS_MEM_DATA(ring);
7712 writeq(val64, &bar0->rts_ds_mem_data);
7713
7714 val64 = RTS_DS_MEM_CTRL_WE |
7715 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7716 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7717
7718 writeq(val64, &bar0->rts_ds_mem_ctrl);
7719
7720 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7721 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7722 S2IO_BIT_RESET);
9fc93a41
SS		 7723}
7724
04025095
SH		 7725static const struct net_device_ops s2io_netdev_ops = {
7726 .ndo_open = s2io_open,
7727 .ndo_stop = s2io_close,
7728 .ndo_get_stats = s2io_get_stats,
7729 .ndo_start_xmit = s2io_xmit,
7730 .ndo_validate_addr = eth_validate_addr,
7731 .ndo_set_multicast_list = s2io_set_multicast,
7732 .ndo_do_ioctl = s2io_ioctl,
7733 .ndo_set_mac_address = s2io_set_mac_addr,
7734 .ndo_change_mtu = s2io_change_mtu,
7735 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7736 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7737 .ndo_tx_timeout = s2io_tx_watchdog,
7738#ifdef CONFIG_NET_POLL_CONTROLLER
7739 .ndo_poll_controller = s2io_netpoll,
7740#endif
7741};
7742
1da177e4 7743/**
20346722 7744 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7745 * @pdev : structure containing the PCI related information of the device.
7746 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7747 * Description:
7748 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7749 * All OS related initialization including memory and device structure and
7750 * initlaization of the device private variable is done. Also the swapper
7751 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7752 * registers of the device.
7753 * Return value:
7754 * returns 0 on success and negative on failure.
7755 */
7756
7757static int __devinit
7758s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7759{
1ee6dd77 7760 struct s2io_nic *sp;
1da177e4 7761 struct net_device *dev;
1da177e4 7762 int i, j, ret;
f957bcf0 7763 int dma_flag = false;
1da177e4
LT		 7764 u32 mac_up, mac_down;
7765 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7766 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7767 u16 subid;
1da177e4 7768 struct config_param *config;
ffb5df6c 7769 struct mac_info *mac_control;
541ae68f 7770 int mode;
cc6e7c44 7771 u8 dev_intr_type = intr_type;
3a3d5756 7772 u8 dev_multiq = 0;
1da177e4 7773
3a3d5756
SH		 7774 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7775 if (ret)
9dc737a7 7776 return ret;
1da177e4 7777
d44570e4
JP		 7778 ret = pci_enable_device(pdev);
7779 if (ret) {
1da177e4 7780 DBG_PRINT(ERR_DBG,
9e39f7c5 7781 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7782 return ret;
7783 }
7784
6a35528a 7785 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7786 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7787 dma_flag = true;
d44570e4 7788 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7789 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7790 "Unable to obtain 64bit DMA "
7791 "for consistent allocations\n");
1da177e4
LT		 7792 pci_disable_device(pdev);
7793 return -ENOMEM;
7794 }
284901a9 7795 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7796 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7797 } else {
7798 pci_disable_device(pdev);
7799 return -ENOMEM;
7800 }
d44570e4
JP		 7801 ret = pci_request_regions(pdev, s2io_driver_name);
7802 if (ret) {
9e39f7c5 7803 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7804 __func__, ret);
eccb8628
VP		 7805 pci_disable_device(pdev);
7806 return -ENODEV;
1da177e4 7807 }
3a3d5756 7808 if (dev_multiq)
6cfc482b 7809 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7810 else
b19fa1fa 7811 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7812 if (dev == NULL) {
7813 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7814 pci_disable_device(pdev);
7815 pci_release_regions(pdev);
7816 return -ENODEV;
7817 }
7818
7819 pci_set_master(pdev);
7820 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7821 SET_NETDEV_DEV(dev, &pdev->dev);
7822
7823 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7824 sp = netdev_priv(dev);
1ee6dd77 7825 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7826 sp->dev = dev;
7827 sp->pdev = pdev;
1da177e4 7828 sp->high_dma_flag = dma_flag;
f957bcf0 7829 sp->device_enabled_once = false;
da6971d8
AR		 7830 if (rx_ring_mode == 1)
7831 sp->rxd_mode = RXD_MODE_1;
7832 if (rx_ring_mode == 2)
7833 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7834
eaae7f72 7835 sp->config.intr_type = dev_intr_type;
1da177e4 7836
541ae68f 7837 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7838 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7839 sp->device_type = XFRAME_II_DEVICE;
7840 else
7841 sp->device_type = XFRAME_I_DEVICE;
7842
43b7c451 7843 sp->lro = lro_enable;
6aa20a22 7844
1da177e4
LT		 7845 /* Initialize some PCI/PCI-X fields of the NIC. */
7846 s2io_init_pci(sp);
7847
20346722 7848 /*
1da177e4 7849 * Setting the device configuration parameters.
20346722
K		 7850 * Most of these parameters can be specified by the user during
7851 * module insertion as they are module loadable parameters. If
7852 * these parameters are not not specified during load time, they
1da177e4
LT		 7853 * are initialized with default values.
7854 */
1da177e4 7855 config = &sp->config;
ffb5df6c 7856 mac_control = &sp->mac_control;
1da177e4 7857
596c5c97 7858 config->napi = napi;
6cfc482b 7859 config->tx_steering_type = tx_steering_type;
596c5c97 7860
1da177e4 7861 /* Tx side parameters. */
6cfc482b
SH		 7862 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7863 config->tx_fifo_num = MAX_TX_FIFOS;
7864 else
7865 config->tx_fifo_num = tx_fifo_num;
7866
7867 /* Initialize the fifos used for tx steering */
7868 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7869 if (config->tx_fifo_num == 1)
7870 sp->total_tcp_fifos = 1;
7871 else
7872 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7873 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7874 sp->total_udp_fifos = 1;
7875 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7876 } else {
7877 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7878 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7879 sp->udp_fifo_idx = sp->total_tcp_fifos;
7880 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7881 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7882 }
7883
3a3d5756 7884 config->multiq = dev_multiq;
6cfc482b 7885 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7886 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7887
7888 tx_cfg->fifo_len = tx_fifo_len[i];
7889 tx_cfg->fifo_priority = i;
1da177e4
LT		 7890 }
7891
20346722
K		 7892 /* mapping the QoS priority to the configured fifos */
7893 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7894 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7895
6cfc482b
SH		 7896 /* map the hashing selector table to the configured fifos */
7897 for (i = 0; i < config->tx_fifo_num; i++)
7898 sp->fifo_selector[i] = fifo_selector[i];
7899
7900
1da177e4
LT		 7901 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7902 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7903 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7904
7905 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7906 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7907 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7908 break;
7909 }
7910 }
fed5eccd
AR		 7911 /* + 2 because one Txd for skb->data and one Txd for UFO */
7912 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7913
7914 /* Rx side parameters. */
1da177e4 7915 config->rx_ring_num = rx_ring_num;
0425b46a 7916 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7917 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7918 struct ring_info *ring = &mac_control->rings[i];
7919
7920 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7921 rx_cfg->ring_priority = i;
7922 ring->rx_bufs_left = 0;
7923 ring->rxd_mode = sp->rxd_mode;
7924 ring->rxd_count = rxd_count[sp->rxd_mode];
7925 ring->pdev = sp->pdev;
7926 ring->dev = sp->dev;
1da177e4
LT		 7927 }
7928
7929 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7930 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7931
7932 rx_cfg->ring_org = RING_ORG_BUFF1;
7933 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7934 }
7935
7936 /* Setting Mac Control parameters */
7937 mac_control->rmac_pause_time = rmac_pause_time;
7938 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7939 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7940
7941
1da177e4
LT		 7942 /* initialize the shared memory used by the NIC and the host */
7943 if (init_shared_mem(sp)) {
d44570e4 7944 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7945 ret = -ENOMEM;
7946 goto mem_alloc_failed;
7947 }
7948
275f165f 7949 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7950 if (!sp->bar0) {
19a60522 7951 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7952 dev->name);
7953 ret = -ENOMEM;
7954 goto bar0_remap_failed;
7955 }
7956
275f165f 7957 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7958 if (!sp->bar1) {
19a60522 7959 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7960 dev->name);
7961 ret = -ENOMEM;
7962 goto bar1_remap_failed;
7963 }
7964
7965 dev->irq = pdev->irq;
d44570e4 7966 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7967
7968 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7969 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 7970 mac_control->tx_FIFO_start[j] =
7971 (struct TxFIFO_element __iomem *)
7972 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 7973 }
7974
7975 /* Driver entry points */
04025095 7976 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7977 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7978 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 7979
1da177e4 7980 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 7981 if (sp->high_dma_flag == true)
1da177e4 7982 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7983 dev->features |= NETIF_F_TSO;
f83ef8c0 7984 dev->features |= NETIF_F_TSO6;
db874e65 7985 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7986 dev->features |= NETIF_F_UFO;
7987 dev->features |= NETIF_F_HW_CSUM;
7988 }
1da177e4 7989 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7990 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7991 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7992
e960fc5c 7993 pci_save_state(sp->pdev);
1da177e4
LT		 7994
7995 /* Setting swapper control on the NIC, for proper reset operation */
7996 if (s2io_set_swapper(sp)) {
9e39f7c5 7997 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 7998 dev->name);
7999 ret = -EAGAIN;
8000 goto set_swap_failed;
8001 }
8002
541ae68f
K		 8003 /* Verify if the Herc works on the slot its placed into */
8004 if (sp->device_type & XFRAME_II_DEVICE) {
8005 mode = s2io_verify_pci_mode(sp);
8006 if (mode < 0) {
9e39f7c5
JP		 8007 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8008 __func__);
541ae68f
K		 8009 ret = -EBADSLT;
8010 goto set_swap_failed;
8011 }
8012 }
8013
f61e0a35
SH		 8014 if (sp->config.intr_type == MSI_X) {
8015 sp->num_entries = config->rx_ring_num + 1;
8016 ret = s2io_enable_msi_x(sp);
8017
8018 if (!ret) {
8019 ret = s2io_test_msi(sp);
8020 /* rollback MSI-X, will re-enable during add_isr() */
8021 remove_msix_isr(sp);
8022 }
8023 if (ret) {
8024
8025 DBG_PRINT(ERR_DBG,
9e39f7c5 8026 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8027 sp->config.intr_type = INTA;
8028 }
8029 }
8030
8031 if (config->intr_type == MSI_X) {
13d866a9
JP		 8032 for (i = 0; i < config->rx_ring_num ; i++) {
8033 struct ring_info *ring = &mac_control->rings[i];
8034
8035 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8036 }
f61e0a35
SH		 8037 } else {
8038 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8039 }
8040
541ae68f
K		 8041 /* Not needed for Herc */
8042 if (sp->device_type & XFRAME_I_DEVICE) {
8043 /*
8044 * Fix for all "FFs" MAC address problems observed on
8045 * Alpha platforms
8046 */
8047 fix_mac_address(sp);
8048 s2io_reset(sp);
8049 }
1da177e4
LT		 8050
8051 /*
1da177e4
LT		 8052 * MAC address initialization.
8053 * For now only one mac address will be read and used.
8054 */
8055 bar0 = sp->bar0;
8056 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8057 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8058 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8059 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8060 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8061 S2IO_BIT_RESET);
1da177e4 8062 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8063 mac_down = (u32)tmp64;
1da177e4
LT		 8064 mac_up = (u32) (tmp64 >> 32);
8065
1da177e4
LT		 8066 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8067 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8068 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8069 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8070 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8071 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8072
1da177e4
LT		 8073 /* Set the factory defined MAC address initially */
8074 dev->addr_len = ETH_ALEN;
8075 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8076 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8077
faa4f796
SH		 8078 /* initialize number of multicast & unicast MAC entries variables */
8079 if (sp->device_type == XFRAME_I_DEVICE) {
8080 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8081 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8082 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8083 } else if (sp->device_type == XFRAME_II_DEVICE) {
8084 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8085 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8086 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8087 }
8088
8089 /* store mac addresses from CAM to s2io_nic structure */
8090 do_s2io_store_unicast_mc(sp);
8091
f61e0a35
SH		 8092 /* Configure MSIX vector for number of rings configured plus one */
8093 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8094 (config->intr_type == MSI_X))
f61e0a35
SH		 8095 sp->num_entries = config->rx_ring_num + 1;
8096
d44570e4 8097 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8098 store_xmsi_data(sp);
b41477f3
AR		 8099 /* reset Nic and bring it to known state */
8100 s2io_reset(sp);
8101
1da177e4 8102 /*
99993af6 8103 * Initialize link state flags
541ae68f 8104 * and the card state parameter
1da177e4 8105 */
92b84437 8106 sp->state = 0;
1da177e4 8107
1da177e4 8108 /* Initialize spinlocks */
13d866a9
JP		 8109 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8110 struct fifo_info *fifo = &mac_control->fifos[i];
8111
8112 spin_lock_init(&fifo->tx_lock);
8113 }
db874e65 8114
20346722
K		 8115 /*
8116 * SXE-002: Configure link and activity LED to init state
8117 * on driver load.
1da177e4
LT		 8118 */
8119 subid = sp->pdev->subsystem_device;
8120 if ((subid & 0xFF) >= 0x07) {
8121 val64 = readq(&bar0->gpio_control);
8122 val64 |= 0x0000800000000000ULL;
8123 writeq(val64, &bar0->gpio_control);
8124 val64 = 0x0411040400000000ULL;
d44570e4 8125 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8126 val64 = readq(&bar0->gpio_control);
8127 }
8128
8129 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8130
8131 if (register_netdev(dev)) {
8132 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8133 ret = -ENODEV;
8134 goto register_failed;
8135 }
9dc737a7 8136 s2io_vpd_read(sp);
0c61ed5f 8137 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8138 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8139 sp->product_name, pdev->revision);
b41477f3
AR		 8140 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8141 s2io_driver_version);
9e39f7c5
JP		 8142 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8143 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8144 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8145 mode = s2io_print_pci_mode(sp);
541ae68f 8146 if (mode < 0) {
541ae68f 8147 ret = -EBADSLT;
9dc737a7 8148 unregister_netdev(dev);
541ae68f
K		 8149 goto set_swap_failed;
8150 }
541ae68f 8151 }
d44570e4
JP		 8152 switch (sp->rxd_mode) {
8153 case RXD_MODE_1:
8154 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8155 dev->name);
8156 break;
8157 case RXD_MODE_3B:
8158 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8159 dev->name);
8160 break;
9dc737a7 8161 }
db874e65 8162
f61e0a35
SH		 8163 switch (sp->config.napi) {
8164 case 0:
8165 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8166 break;
8167 case 1:
db874e65 8168 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8169 break;
8170 }
3a3d5756
SH		 8171
8172 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8173 sp->config.tx_fifo_num);
3a3d5756 8174
0425b46a
SH		 8175 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8176 sp->config.rx_ring_num);
8177
d44570e4
JP		 8178 switch (sp->config.intr_type) {
8179 case INTA:
8180 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8181 break;
8182 case MSI_X:
8183 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8184 break;
9dc737a7 8185 }
3a3d5756 8186 if (sp->config.multiq) {
13d866a9
JP		 8187 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8188 struct fifo_info *fifo = &mac_control->fifos[i];
8189
8190 fifo->multiq = config->multiq;
8191 }
3a3d5756 8192 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8193 dev->name);
3a3d5756
SH		 8194 } else
8195 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8196 dev->name);
3a3d5756 8197
6cfc482b
SH		 8198 switch (sp->config.tx_steering_type) {
8199 case NO_STEERING:
d44570e4
JP		 8200 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8201 dev->name);
8202 break;
6cfc482b 8203 case TX_PRIORITY_STEERING:
d44570e4
JP		 8204 DBG_PRINT(ERR_DBG,
8205 "%s: Priority steering enabled for transmit\n",
8206 dev->name);
6cfc482b
SH		 8207 break;
8208 case TX_DEFAULT_STEERING:
d44570e4
JP		 8209 DBG_PRINT(ERR_DBG,
8210 "%s: Default steering enabled for transmit\n",
8211 dev->name);
6cfc482b
SH		 8212 }
8213
7d3d0439
RA		 8214 if (sp->lro)
8215 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8216 dev->name);
db874e65 8217 if (ufo)
d44570e4
JP		 8218 DBG_PRINT(ERR_DBG,
8219 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8220 dev->name);
7ba013ac 8221 /* Initialize device name */
9dc737a7 8222 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8223
cd0fce03
BL		 8224 if (vlan_tag_strip)
8225 sp->vlan_strip_flag = 1;
8226 else
8227 sp->vlan_strip_flag = 0;
8228
20346722
K		 8229 /*
8230 * Make Link state as off at this point, when the Link change
8231 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8232 * the right state.
8233 */
8234 netif_carrier_off(dev);
1da177e4
LT		 8235
8236 return 0;
8237
d44570e4
JP		 8238register_failed:
8239set_swap_failed:
1da177e4 8240 iounmap(sp->bar1);
d44570e4 8241bar1_remap_failed:
1da177e4 8242 iounmap(sp->bar0);
d44570e4
JP		 8243bar0_remap_failed:
8244mem_alloc_failed:
1da177e4
LT		 8245 free_shared_mem(sp);
8246 pci_disable_device(pdev);
eccb8628 8247 pci_release_regions(pdev);
1da177e4
LT		 8248 pci_set_drvdata(pdev, NULL);
8249 free_netdev(dev);
8250
8251 return ret;
8252}
8253
8254/**
20346722 8255 * s2io_rem_nic - Free the PCI device
1da177e4 8256 * @pdev: structure containing the PCI related information of the device.
20346722 8257 * Description: This function is called by the Pci subsystem to release a
1da177e4 8258 * PCI device and free up all resource held up by the device. This could
20346722 8259 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8260 * from memory.
8261 */
8262
8263static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8264{
8265 struct net_device *dev =
d44570e4 8266 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8267 struct s2io_nic *sp;
1da177e4
LT		 8268
8269 if (dev == NULL) {
8270 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8271 return;
8272 }
8273
22747d6b
FR		 8274 flush_scheduled_work();
8275
4cf1653a 8276 sp = netdev_priv(dev);
1da177e4
LT		 8277 unregister_netdev(dev);
8278
8279 free_shared_mem(sp);
8280 iounmap(sp->bar0);
8281 iounmap(sp->bar1);
eccb8628 8282 pci_release_regions(pdev);
1da177e4 8283 pci_set_drvdata(pdev, NULL);
1da177e4 8284 free_netdev(dev);
19a60522 8285 pci_disable_device(pdev);
1da177e4
LT		 8286}
8287
8288/**
8289 * s2io_starter - Entry point for the driver
8290 * Description: This function is the entry point for the driver. It verifies
8291 * the module loadable parameters and initializes PCI configuration space.
8292 */
8293
43b7c451 8294static int __init s2io_starter(void)
1da177e4 8295{
29917620 8296 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8297}
8298
8299/**
20346722 8300 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8301 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8302 */
8303
372cc597 8304static __exit void s2io_closer(void)
1da177e4
LT		 8305{
8306 pci_unregister_driver(&s2io_driver);
8307 DBG_PRINT(INIT_DBG, "cleanup done\n");
8308}
8309
8310module_init(s2io_starter);
8311module_exit(s2io_closer);
7d3d0439 8312
6aa20a22 8313static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8314 struct tcphdr **tcp, struct RxD_t *rxdp,
8315 struct s2io_nic *sp)
7d3d0439
RA		 8316{
8317 int ip_off;
8318 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8319
8320 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8321 DBG_PRINT(INIT_DBG,
8322 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8323 __func__);
7d3d0439
RA		 8324 return -1;
8325 }
8326
cdb5bf02 8327 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8328 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8329 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8330 /*
8331 * If vlan stripping is disabled and the frame is VLAN tagged,
8332 * shift the offset by the VLAN header size bytes.
8333 */
cd0fce03 8334 if ((!sp->vlan_strip_flag) &&
d44570e4 8335 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8336 ip_off += HEADER_VLAN_SIZE;
8337 } else {
7d3d0439 8338 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8339 return -1;
7d3d0439
RA		 8340 }
8341
8342 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8343 ip_len = (u8)((*ip)->ihl);
8344 ip_len <<= 2;
8345 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8346
8347 return 0;
8348}
8349
1ee6dd77 8350static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8351 struct tcphdr *tcp)
8352{
d44570e4
JP		 8353 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8354 if ((lro->iph->saddr != ip->saddr) ||
8355 (lro->iph->daddr != ip->daddr) ||
8356 (lro->tcph->source != tcp->source) ||
8357 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8358 return -1;
8359 return 0;
8360}
8361
8362static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8363{
d44570e4 8364 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8365}
8366
1ee6dd77 8367static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8368 struct iphdr *ip, struct tcphdr *tcp,
8369 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8370{
d44570e4 8371 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8372 lro->l2h = l2h;
8373 lro->iph = ip;
8374 lro->tcph = tcp;
8375 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8376 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8377 lro->sg_num = 1;
8378 lro->total_len = ntohs(ip->tot_len);
8379 lro->frags_len = 0;
cdb5bf02 8380 lro->vlan_tag = vlan_tag;
6aa20a22 8381 /*
d44570e4
JP		 8382 * Check if we saw TCP timestamp.
8383 * Other consistency checks have already been done.
8384 */
7d3d0439 8385 if (tcp->doff == 8) {
c8855953
SR		 8386 __be32 *ptr;
8387 ptr = (__be32 *)(tcp+1);
7d3d0439 8388 lro->saw_ts = 1;
c8855953 8389 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8390 lro->cur_tsecr = *(ptr+2);
8391 }
8392 lro->in_use = 1;
8393}
8394
1ee6dd77 8395static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8396{
8397 struct iphdr *ip = lro->iph;
8398 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8399 __sum16 nchk;
ffb5df6c
JP		 8400 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8401
d44570e4 8402 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8403
8404 /* Update L3 header */
8405 ip->tot_len = htons(lro->total_len);
8406 ip->check = 0;
8407 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8408 ip->check = nchk;
8409
8410 /* Update L4 header */
8411 tcp->ack_seq = lro->tcp_ack;
8412 tcp->window = lro->window;
8413
8414 /* Update tsecr field if this session has timestamps enabled */
8415 if (lro->saw_ts) {
c8855953 8416 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8417 *(ptr+2) = lro->cur_tsecr;
8418 }
8419
8420 /* Update counters required for calculation of
8421 * average no. of packets aggregated.
8422 */
ffb5df6c
JP		 8423 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8424 swstats->num_aggregations++;
7d3d0439
RA		 8425}
8426
1ee6dd77 8427static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8428 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8429{
d44570e4 8430 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8431 lro->total_len += l4_pyld;
8432 lro->frags_len += l4_pyld;
8433 lro->tcp_next_seq += l4_pyld;
8434 lro->sg_num++;
8435
8436 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8437 lro->tcp_ack = tcp->ack_seq;
8438 lro->window = tcp->window;
6aa20a22 8439
7d3d0439 8440 if (lro->saw_ts) {
c8855953 8441 __be32 *ptr;
7d3d0439 8442 /* Update tsecr and tsval from this packet */
c8855953
SR		 8443 ptr = (__be32 *)(tcp+1);
8444 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8445 lro->cur_tsecr = *(ptr + 2);
8446 }
8447}
8448
1ee6dd77 8449static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8450 struct tcphdr *tcp, u32 tcp_pyld_len)
8451{
7d3d0439
RA		 8452 u8 *ptr;
8453
d44570e4 8454 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8455
7d3d0439
RA		 8456 if (!tcp_pyld_len) {
8457 /* Runt frame or a pure ack */
8458 return -1;
8459 }
8460
8461 if (ip->ihl != 5) /* IP has options */
8462 return -1;
8463
75c30b13
AR		 8464 /* If we see CE codepoint in IP header, packet is not mergeable */
8465 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8466 return -1;
8467
8468 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8469 if (tcp->urg || tcp->psh || tcp->rst ||
8470 tcp->syn || tcp->fin ||
8471 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8472 /*
8473 * Currently recognize only the ack control word and
8474 * any other control field being set would result in
8475 * flushing the LRO session
8476 */
8477 return -1;
8478 }
8479
6aa20a22 8480 /*
7d3d0439
RA		 8481 * Allow only one TCP timestamp option. Don't aggregate if
8482 * any other options are detected.
8483 */
8484 if (tcp->doff != 5 && tcp->doff != 8)
8485 return -1;
8486
8487 if (tcp->doff == 8) {
6aa20a22 8488 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8489 while (*ptr == TCPOPT_NOP)
8490 ptr++;
8491 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8492 return -1;
8493
8494 /* Ensure timestamp value increases monotonically */
8495 if (l_lro)
c8855953 8496 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8497 return -1;
8498
8499 /* timestamp echo reply should be non-zero */
c8855953 8500 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8501 return -1;
8502 }
8503
8504 return 0;
8505}
8506
d44570e4
JP		 8507static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8508 u8 **tcp, u32 *tcp_len, struct lro **lro,
8509 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8510{
8511 struct iphdr *ip;
8512 struct tcphdr *tcph;
8513 int ret = 0, i;
cdb5bf02 8514 u16 vlan_tag = 0;
ffb5df6c 8515 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8516
d44570e4
JP		 8517 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8518 rxdp, sp);
8519 if (ret)
7d3d0439 8520 return ret;
7d3d0439 8521
d44570e4
JP		 8522 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8523
cdb5bf02 8524 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8525 tcph = (struct tcphdr *)*tcp;
8526 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8527 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8528 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8529 if (l_lro->in_use) {
8530 if (check_for_socket_match(l_lro, ip, tcph))
8531 continue;
8532 /* Sock pair matched */
8533 *lro = l_lro;
8534
8535 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8536 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8537 "expected 0x%x, actual 0x%x\n",
8538 __func__,
7d3d0439
RA		 8539 (*lro)->tcp_next_seq,
8540 ntohl(tcph->seq));
8541
ffb5df6c 8542 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8543 ret = 2;
8544 break;
8545 }
8546
d44570e4
JP		 8547 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8548 *tcp_len))
7d3d0439
RA		 8549 ret = 1; /* Aggregate */
8550 else
8551 ret = 2; /* Flush both */
8552 break;
8553 }
8554 }
8555
8556 if (ret == 0) {
8557 /* Before searching for available LRO objects,
8558 * check if the pkt is L3/L4 aggregatable. If not
8559 * don't create new LRO session. Just send this
8560 * packet up.
8561 */
d44570e4 8562 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8563 return 5;
7d3d0439 8564
d44570e4 8565 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8566 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8567 if (!(l_lro->in_use)) {
8568 *lro = l_lro;
8569 ret = 3; /* Begin anew */
8570 break;
8571 }
8572 }
8573 }
8574
8575 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8576 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8577 __func__);
7d3d0439
RA		 8578 *lro = NULL;
8579 return ret;
8580 }
8581
8582 switch (ret) {
d44570e4
JP		 8583 case 3:
8584 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8585 vlan_tag);
8586 break;
8587 case 2:
8588 update_L3L4_header(sp, *lro);
8589 break;
8590 case 1:
8591 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8592 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8593 update_L3L4_header(sp, *lro);
d44570e4
JP		 8594 ret = 4; /* Flush the LRO */
8595 }
8596 break;
8597 default:
9e39f7c5 8598 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8599 break;
7d3d0439
RA		 8600 }
8601
8602 return ret;
8603}
8604
1ee6dd77 8605static void clear_lro_session(struct lro *lro)
7d3d0439 8606{
1ee6dd77 8607 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8608
8609 memset(lro, 0, lro_struct_size);
8610}
8611
cdb5bf02 8612static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8613{
8614 struct net_device *dev = skb->dev;
4cf1653a 8615 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8616
8617 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8618 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8619 /* Queueing the vlan frame to the upper layer */
8620 if (sp->config.napi)
8621 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8622 else
8623 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8624 } else {
8625 if (sp->config.napi)
8626 netif_receive_skb(skb);
8627 else
8628 netif_rx(skb);
8629 }
7d3d0439
RA		 8630}
8631
1ee6dd77 8632static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8633 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8634{
75c30b13 8635 struct sk_buff *first = lro->parent;
ffb5df6c 8636 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8637
8638 first->len += tcp_len;
8639 first->data_len = lro->frags_len;
8640 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8641 if (skb_shinfo(first)->frag_list)
8642 lro->last_frag->next = skb;
7d3d0439
RA		 8643 else
8644 skb_shinfo(first)->frag_list = skb;
372cc597 8645 first->truesize += skb->truesize;
75c30b13 8646 lro->last_frag = skb;
ffb5df6c 8647 swstats->clubbed_frms_cnt++;
7d3d0439
RA		 8648 return;
8649}
d796fdb7
LV		 8650
8651/**
8652 * s2io_io_error_detected - called when PCI error is detected
8653 * @pdev: Pointer to PCI device
8453d43f 8654 * @state: The current pci connection state
d796fdb7
LV		 8655 *
8656 * This function is called after a PCI bus error affecting
8657 * this device has been detected.
8658 */
8659static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8660 pci_channel_state_t state)
d796fdb7
LV		 8661{
8662 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8663 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8664
8665 netif_device_detach(netdev);
8666
1e3c8bd6
DN		 8667 if (state == pci_channel_io_perm_failure)
8668 return PCI_ERS_RESULT_DISCONNECT;
8669
d796fdb7
LV		 8670 if (netif_running(netdev)) {
8671 /* Bring down the card, while avoiding PCI I/O */
8672 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8673 }
8674 pci_disable_device(pdev);
8675
8676 return PCI_ERS_RESULT_NEED_RESET;
8677}
8678
8679/**
8680 * s2io_io_slot_reset - called after the pci bus has been reset.
8681 * @pdev: Pointer to PCI device
8682 *
8683 * Restart the card from scratch, as if from a cold-boot.
8684 * At this point, the card has exprienced a hard reset,
8685 * followed by fixups by BIOS, and has its config space
8686 * set up identically to what it was at cold boot.
8687 */
8688static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8689{
8690 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8691 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8692
8693 if (pci_enable_device(pdev)) {
6cef2b8e 8694 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8695 return PCI_ERS_RESULT_DISCONNECT;
8696 }
8697
8698 pci_set_master(pdev);
8699 s2io_reset(sp);
8700
8701 return PCI_ERS_RESULT_RECOVERED;
8702}
8703
8704/**
8705 * s2io_io_resume - called when traffic can start flowing again.
8706 * @pdev: Pointer to PCI device
8707 *
8708 * This callback is called when the error recovery driver tells
8709 * us that its OK to resume normal operation.
8710 */
8711static void s2io_io_resume(struct pci_dev *pdev)
8712{
8713 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8714 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8715
8716 if (netif_running(netdev)) {
8717 if (s2io_card_up(sp)) {
6cef2b8e 8718 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8719 return;
8720 }
8721
8722 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8723 s2io_card_down(sp);
6cef2b8e 8724 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8725 return;
8726 }
8727 }
8728
8729 netif_device_attach(netdev);
fd2ea0a7 8730 netif_tx_wake_all_queues(netdev);
d796fdb7 8731}
Clone of davem's net-next-2.6 tree