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af19b491 AKS |
1 | /* |
2 | * Copyright (C) 2009 - QLogic Corporation. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called "COPYING". | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "qlcnic.h" | |
26 | ||
af19b491 AKS |
27 | static u32 |
28 | qlcnic_poll_rsp(struct qlcnic_adapter *adapter) | |
29 | { | |
30 | u32 rsp; | |
31 | int timeout = 0; | |
32 | ||
33 | do { | |
34 | /* give atleast 1ms for firmware to respond */ | |
35 | msleep(1); | |
36 | ||
37 | if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT) | |
38 | return QLCNIC_CDRP_RSP_TIMEOUT; | |
39 | ||
40 | rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET); | |
41 | } while (!QLCNIC_CDRP_IS_RSP(rsp)); | |
42 | ||
43 | return rsp; | |
44 | } | |
45 | ||
7eb9855d | 46 | u32 |
af19b491 AKS |
47 | qlcnic_issue_cmd(struct qlcnic_adapter *adapter, |
48 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd) | |
49 | { | |
50 | u32 rsp; | |
51 | u32 signature; | |
52 | u32 rcode = QLCNIC_RCODE_SUCCESS; | |
53 | struct pci_dev *pdev = adapter->pdev; | |
54 | ||
55 | signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version); | |
56 | ||
57 | /* Acquire semaphore before accessing CRB */ | |
58 | if (qlcnic_api_lock(adapter)) | |
59 | return QLCNIC_RCODE_TIMEOUT; | |
60 | ||
61 | QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature); | |
62 | QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1); | |
63 | QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2); | |
64 | QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3); | |
65 | QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd)); | |
66 | ||
67 | rsp = qlcnic_poll_rsp(adapter); | |
68 | ||
69 | if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) { | |
70 | dev_err(&pdev->dev, "card response timeout.\n"); | |
71 | rcode = QLCNIC_RCODE_TIMEOUT; | |
72 | } else if (rsp == QLCNIC_CDRP_RSP_FAIL) { | |
73 | rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
74 | dev_err(&pdev->dev, "failed card response code:0x%x\n", | |
75 | rcode); | |
76 | } | |
77 | ||
78 | /* Release semaphore */ | |
79 | qlcnic_api_unlock(adapter); | |
80 | ||
81 | return rcode; | |
82 | } | |
83 | ||
84 | int | |
85 | qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu) | |
86 | { | |
87 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
88 | ||
89 | if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) { | |
90 | if (qlcnic_issue_cmd(adapter, | |
2e9d722d AC |
91 | adapter->ahw.pci_func, |
92 | adapter->fw_hal_version, | |
93 | recv_ctx->context_id, | |
94 | mtu, | |
95 | 0, | |
96 | QLCNIC_CDRP_CMD_SET_MTU)) { | |
af19b491 AKS |
97 | |
98 | dev_err(&adapter->pdev->dev, "Failed to set mtu\n"); | |
99 | return -EIO; | |
100 | } | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static int | |
107 | qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
108 | { | |
109 | void *addr; | |
110 | struct qlcnic_hostrq_rx_ctx *prq; | |
111 | struct qlcnic_cardrsp_rx_ctx *prsp; | |
112 | struct qlcnic_hostrq_rds_ring *prq_rds; | |
113 | struct qlcnic_hostrq_sds_ring *prq_sds; | |
114 | struct qlcnic_cardrsp_rds_ring *prsp_rds; | |
115 | struct qlcnic_cardrsp_sds_ring *prsp_sds; | |
116 | struct qlcnic_host_rds_ring *rds_ring; | |
117 | struct qlcnic_host_sds_ring *sds_ring; | |
118 | ||
119 | dma_addr_t hostrq_phys_addr, cardrsp_phys_addr; | |
120 | u64 phys_addr; | |
121 | ||
122 | int i, nrds_rings, nsds_rings; | |
123 | size_t rq_size, rsp_size; | |
2e9d722d | 124 | u32 cap, reg, val, reg2; |
af19b491 AKS |
125 | int err; |
126 | ||
127 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
128 | ||
129 | nrds_rings = adapter->max_rds_rings; | |
130 | nsds_rings = adapter->max_sds_rings; | |
131 | ||
132 | rq_size = | |
133 | SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings, | |
134 | nsds_rings); | |
135 | rsp_size = | |
136 | SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings, | |
137 | nsds_rings); | |
138 | ||
139 | addr = pci_alloc_consistent(adapter->pdev, | |
140 | rq_size, &hostrq_phys_addr); | |
141 | if (addr == NULL) | |
142 | return -ENOMEM; | |
143 | prq = (struct qlcnic_hostrq_rx_ctx *)addr; | |
144 | ||
145 | addr = pci_alloc_consistent(adapter->pdev, | |
146 | rsp_size, &cardrsp_phys_addr); | |
147 | if (addr == NULL) { | |
148 | err = -ENOMEM; | |
149 | goto out_free_rq; | |
150 | } | |
151 | prsp = (struct qlcnic_cardrsp_rx_ctx *)addr; | |
152 | ||
153 | prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr); | |
154 | ||
8f891387 | 155 | cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
156 | | QLCNIC_CAP0_VALIDOFF); | |
af19b491 AKS |
157 | cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS); |
158 | ||
8f891387 | 159 | prq->valid_field_offset = offsetof(struct qlcnic_hostrq_rx_ctx, |
160 | msix_handler); | |
161 | prq->txrx_sds_binding = nsds_rings - 1; | |
162 | ||
af19b491 AKS |
163 | prq->capabilities[0] = cpu_to_le32(cap); |
164 | prq->host_int_crb_mode = | |
165 | cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED); | |
166 | prq->host_rds_crb_mode = | |
167 | cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE); | |
168 | ||
169 | prq->num_rds_rings = cpu_to_le16(nrds_rings); | |
170 | prq->num_sds_rings = cpu_to_le16(nsds_rings); | |
171 | prq->rds_ring_offset = cpu_to_le32(0); | |
172 | ||
173 | val = le32_to_cpu(prq->rds_ring_offset) + | |
174 | (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings); | |
175 | prq->sds_ring_offset = cpu_to_le32(val); | |
176 | ||
177 | prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data + | |
178 | le32_to_cpu(prq->rds_ring_offset)); | |
179 | ||
180 | for (i = 0; i < nrds_rings; i++) { | |
181 | ||
182 | rds_ring = &recv_ctx->rds_rings[i]; | |
8a15ad1f | 183 | rds_ring->producer = 0; |
af19b491 AKS |
184 | |
185 | prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr); | |
186 | prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc); | |
187 | prq_rds[i].ring_kind = cpu_to_le32(i); | |
188 | prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size); | |
189 | } | |
190 | ||
191 | prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data + | |
192 | le32_to_cpu(prq->sds_ring_offset)); | |
193 | ||
194 | for (i = 0; i < nsds_rings; i++) { | |
195 | ||
196 | sds_ring = &recv_ctx->sds_rings[i]; | |
8a15ad1f AKS |
197 | sds_ring->consumer = 0; |
198 | memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring)); | |
af19b491 AKS |
199 | |
200 | prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr); | |
201 | prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc); | |
202 | prq_sds[i].msi_index = cpu_to_le16(i); | |
203 | } | |
204 | ||
205 | phys_addr = hostrq_phys_addr; | |
206 | err = qlcnic_issue_cmd(adapter, | |
207 | adapter->ahw.pci_func, | |
2e9d722d | 208 | adapter->fw_hal_version, |
af19b491 AKS |
209 | (u32)(phys_addr >> 32), |
210 | (u32)(phys_addr & 0xffffffff), | |
211 | rq_size, | |
212 | QLCNIC_CDRP_CMD_CREATE_RX_CTX); | |
213 | if (err) { | |
214 | dev_err(&adapter->pdev->dev, | |
215 | "Failed to create rx ctx in firmware%d\n", err); | |
216 | goto out_free_rsp; | |
217 | } | |
218 | ||
219 | ||
220 | prsp_rds = ((struct qlcnic_cardrsp_rds_ring *) | |
221 | &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]); | |
222 | ||
223 | for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) { | |
224 | rds_ring = &recv_ctx->rds_rings[i]; | |
225 | ||
226 | reg = le32_to_cpu(prsp_rds[i].host_producer_crb); | |
2e9d722d AC |
227 | if (adapter->fw_hal_version == QLCNIC_FW_BASE) |
228 | rds_ring->crb_rcv_producer = qlcnic_get_ioaddr(adapter, | |
af19b491 | 229 | QLCNIC_REG(reg - 0x200)); |
2e9d722d AC |
230 | else |
231 | rds_ring->crb_rcv_producer = adapter->ahw.pci_base0 + | |
232 | reg; | |
af19b491 AKS |
233 | } |
234 | ||
235 | prsp_sds = ((struct qlcnic_cardrsp_sds_ring *) | |
236 | &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]); | |
237 | ||
238 | for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) { | |
239 | sds_ring = &recv_ctx->sds_rings[i]; | |
240 | ||
241 | reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); | |
2e9d722d | 242 | reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb); |
af19b491 | 243 | |
2e9d722d AC |
244 | if (adapter->fw_hal_version == QLCNIC_FW_BASE) { |
245 | sds_ring->crb_sts_consumer = qlcnic_get_ioaddr(adapter, | |
af19b491 | 246 | QLCNIC_REG(reg - 0x200)); |
2e9d722d AC |
247 | sds_ring->crb_intr_mask = qlcnic_get_ioaddr(adapter, |
248 | QLCNIC_REG(reg2 - 0x200)); | |
249 | } else { | |
250 | sds_ring->crb_sts_consumer = adapter->ahw.pci_base0 + | |
251 | reg; | |
252 | sds_ring->crb_intr_mask = adapter->ahw.pci_base0 + reg2; | |
253 | } | |
af19b491 AKS |
254 | } |
255 | ||
256 | recv_ctx->state = le32_to_cpu(prsp->host_ctx_state); | |
257 | recv_ctx->context_id = le16_to_cpu(prsp->context_id); | |
258 | recv_ctx->virt_port = prsp->virt_port; | |
259 | ||
260 | out_free_rsp: | |
261 | pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr); | |
262 | out_free_rq: | |
263 | pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr); | |
264 | return err; | |
265 | } | |
266 | ||
267 | static void | |
268 | qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter) | |
269 | { | |
270 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
271 | ||
272 | if (qlcnic_issue_cmd(adapter, | |
273 | adapter->ahw.pci_func, | |
2e9d722d | 274 | adapter->fw_hal_version, |
af19b491 AKS |
275 | recv_ctx->context_id, |
276 | QLCNIC_DESTROY_CTX_RESET, | |
277 | 0, | |
278 | QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) { | |
279 | ||
280 | dev_err(&adapter->pdev->dev, | |
281 | "Failed to destroy rx ctx in firmware\n"); | |
282 | } | |
d626ad4d AKS |
283 | |
284 | recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; | |
af19b491 AKS |
285 | } |
286 | ||
287 | static int | |
288 | qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter) | |
289 | { | |
290 | struct qlcnic_hostrq_tx_ctx *prq; | |
291 | struct qlcnic_hostrq_cds_ring *prq_cds; | |
292 | struct qlcnic_cardrsp_tx_ctx *prsp; | |
293 | void *rq_addr, *rsp_addr; | |
294 | size_t rq_size, rsp_size; | |
295 | u32 temp; | |
296 | int err; | |
297 | u64 phys_addr; | |
298 | dma_addr_t rq_phys_addr, rsp_phys_addr; | |
299 | struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring; | |
300 | ||
8a15ad1f AKS |
301 | /* reset host resources */ |
302 | tx_ring->producer = 0; | |
303 | tx_ring->sw_consumer = 0; | |
304 | *(tx_ring->hw_consumer) = 0; | |
305 | ||
af19b491 AKS |
306 | rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx); |
307 | rq_addr = pci_alloc_consistent(adapter->pdev, | |
308 | rq_size, &rq_phys_addr); | |
309 | if (!rq_addr) | |
310 | return -ENOMEM; | |
311 | ||
312 | rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx); | |
313 | rsp_addr = pci_alloc_consistent(adapter->pdev, | |
314 | rsp_size, &rsp_phys_addr); | |
315 | if (!rsp_addr) { | |
316 | err = -ENOMEM; | |
317 | goto out_free_rq; | |
318 | } | |
319 | ||
320 | memset(rq_addr, 0, rq_size); | |
321 | prq = (struct qlcnic_hostrq_tx_ctx *)rq_addr; | |
322 | ||
323 | memset(rsp_addr, 0, rsp_size); | |
324 | prsp = (struct qlcnic_cardrsp_tx_ctx *)rsp_addr; | |
325 | ||
326 | prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr); | |
327 | ||
328 | temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN | | |
329 | QLCNIC_CAP0_LSO); | |
330 | prq->capabilities[0] = cpu_to_le32(temp); | |
331 | ||
332 | prq->host_int_crb_mode = | |
333 | cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED); | |
334 | ||
335 | prq->interrupt_ctl = 0; | |
336 | prq->msi_index = 0; | |
337 | prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr); | |
338 | ||
339 | prq_cds = &prq->cds_ring; | |
340 | ||
341 | prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr); | |
342 | prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc); | |
343 | ||
344 | phys_addr = rq_phys_addr; | |
345 | err = qlcnic_issue_cmd(adapter, | |
346 | adapter->ahw.pci_func, | |
2e9d722d | 347 | adapter->fw_hal_version, |
af19b491 AKS |
348 | (u32)(phys_addr >> 32), |
349 | ((u32)phys_addr & 0xffffffff), | |
350 | rq_size, | |
351 | QLCNIC_CDRP_CMD_CREATE_TX_CTX); | |
352 | ||
353 | if (err == QLCNIC_RCODE_SUCCESS) { | |
354 | temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); | |
2e9d722d AC |
355 | if (adapter->fw_hal_version == QLCNIC_FW_BASE) |
356 | tx_ring->crb_cmd_producer = qlcnic_get_ioaddr(adapter, | |
af19b491 | 357 | QLCNIC_REG(temp - 0x200)); |
2e9d722d AC |
358 | else |
359 | tx_ring->crb_cmd_producer = adapter->ahw.pci_base0 + | |
360 | temp; | |
af19b491 AKS |
361 | |
362 | adapter->tx_context_id = | |
363 | le16_to_cpu(prsp->context_id); | |
364 | } else { | |
365 | dev_err(&adapter->pdev->dev, | |
366 | "Failed to create tx ctx in firmware%d\n", err); | |
367 | err = -EIO; | |
368 | } | |
369 | ||
370 | pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr); | |
371 | ||
372 | out_free_rq: | |
373 | pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr); | |
374 | ||
375 | return err; | |
376 | } | |
377 | ||
378 | static void | |
379 | qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter) | |
380 | { | |
381 | if (qlcnic_issue_cmd(adapter, | |
382 | adapter->ahw.pci_func, | |
2e9d722d | 383 | adapter->fw_hal_version, |
af19b491 AKS |
384 | adapter->tx_context_id, |
385 | QLCNIC_DESTROY_CTX_RESET, | |
386 | 0, | |
387 | QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) { | |
388 | ||
389 | dev_err(&adapter->pdev->dev, | |
390 | "Failed to destroy tx ctx in firmware\n"); | |
391 | } | |
392 | } | |
393 | ||
394 | int | |
395 | qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val) | |
396 | { | |
397 | ||
398 | if (qlcnic_issue_cmd(adapter, | |
399 | adapter->ahw.pci_func, | |
2e9d722d | 400 | adapter->fw_hal_version, |
af19b491 AKS |
401 | reg, |
402 | 0, | |
403 | 0, | |
404 | QLCNIC_CDRP_CMD_READ_PHY)) { | |
405 | ||
406 | return -EIO; | |
407 | } | |
408 | ||
409 | return QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
410 | } | |
411 | ||
412 | int | |
413 | qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val) | |
414 | { | |
415 | return qlcnic_issue_cmd(adapter, | |
416 | adapter->ahw.pci_func, | |
2e9d722d | 417 | adapter->fw_hal_version, |
af19b491 AKS |
418 | reg, |
419 | val, | |
420 | 0, | |
421 | QLCNIC_CDRP_CMD_WRITE_PHY); | |
422 | } | |
423 | ||
424 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter) | |
425 | { | |
426 | void *addr; | |
427 | int err; | |
428 | int ring; | |
429 | struct qlcnic_recv_context *recv_ctx; | |
430 | struct qlcnic_host_rds_ring *rds_ring; | |
431 | struct qlcnic_host_sds_ring *sds_ring; | |
432 | struct qlcnic_host_tx_ring *tx_ring; | |
433 | ||
434 | struct pci_dev *pdev = adapter->pdev; | |
435 | ||
436 | recv_ctx = &adapter->recv_ctx; | |
437 | tx_ring = adapter->tx_ring; | |
438 | ||
439 | tx_ring->hw_consumer = (__le32 *)pci_alloc_consistent(pdev, sizeof(u32), | |
440 | &tx_ring->hw_cons_phys_addr); | |
441 | if (tx_ring->hw_consumer == NULL) { | |
442 | dev_err(&pdev->dev, "failed to allocate tx consumer\n"); | |
443 | return -ENOMEM; | |
444 | } | |
445 | *(tx_ring->hw_consumer) = 0; | |
446 | ||
447 | /* cmd desc ring */ | |
448 | addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring), | |
449 | &tx_ring->phys_addr); | |
450 | ||
451 | if (addr == NULL) { | |
452 | dev_err(&pdev->dev, "failed to allocate tx desc ring\n"); | |
aadd8184 AC |
453 | err = -ENOMEM; |
454 | goto err_out_free; | |
af19b491 AKS |
455 | } |
456 | ||
457 | tx_ring->desc_head = (struct cmd_desc_type0 *)addr; | |
458 | ||
459 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
460 | rds_ring = &recv_ctx->rds_rings[ring]; | |
461 | addr = pci_alloc_consistent(adapter->pdev, | |
462 | RCV_DESC_RINGSIZE(rds_ring), | |
463 | &rds_ring->phys_addr); | |
464 | if (addr == NULL) { | |
465 | dev_err(&pdev->dev, | |
466 | "failed to allocate rds ring [%d]\n", ring); | |
467 | err = -ENOMEM; | |
468 | goto err_out_free; | |
469 | } | |
470 | rds_ring->desc_head = (struct rcv_desc *)addr; | |
471 | ||
472 | } | |
473 | ||
474 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
475 | sds_ring = &recv_ctx->sds_rings[ring]; | |
476 | ||
477 | addr = pci_alloc_consistent(adapter->pdev, | |
478 | STATUS_DESC_RINGSIZE(sds_ring), | |
479 | &sds_ring->phys_addr); | |
480 | if (addr == NULL) { | |
481 | dev_err(&pdev->dev, | |
482 | "failed to allocate sds ring [%d]\n", ring); | |
483 | err = -ENOMEM; | |
484 | goto err_out_free; | |
485 | } | |
486 | sds_ring->desc_head = (struct status_desc *)addr; | |
487 | } | |
488 | ||
af19b491 AKS |
489 | return 0; |
490 | ||
491 | err_out_free: | |
492 | qlcnic_free_hw_resources(adapter); | |
493 | return err; | |
494 | } | |
495 | ||
8a15ad1f AKS |
496 | |
497 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter) | |
af19b491 | 498 | { |
8a15ad1f AKS |
499 | int err; |
500 | ||
501 | err = qlcnic_fw_cmd_create_rx_ctx(adapter); | |
502 | if (err) | |
503 | return err; | |
504 | ||
505 | err = qlcnic_fw_cmd_create_tx_ctx(adapter); | |
506 | if (err) { | |
507 | qlcnic_fw_cmd_destroy_rx_ctx(adapter); | |
508 | return err; | |
509 | } | |
af19b491 | 510 | |
8a15ad1f AKS |
511 | set_bit(__QLCNIC_FW_ATTACHED, &adapter->state); |
512 | return 0; | |
513 | } | |
af19b491 | 514 | |
8a15ad1f AKS |
515 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter) |
516 | { | |
af19b491 AKS |
517 | if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) { |
518 | qlcnic_fw_cmd_destroy_rx_ctx(adapter); | |
519 | qlcnic_fw_cmd_destroy_tx_ctx(adapter); | |
520 | ||
521 | /* Allow dma queues to drain after context reset */ | |
522 | msleep(20); | |
523 | } | |
8a15ad1f AKS |
524 | } |
525 | ||
526 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter) | |
527 | { | |
528 | struct qlcnic_recv_context *recv_ctx; | |
529 | struct qlcnic_host_rds_ring *rds_ring; | |
530 | struct qlcnic_host_sds_ring *sds_ring; | |
531 | struct qlcnic_host_tx_ring *tx_ring; | |
532 | int ring; | |
af19b491 AKS |
533 | |
534 | recv_ctx = &adapter->recv_ctx; | |
535 | ||
536 | tx_ring = adapter->tx_ring; | |
537 | if (tx_ring->hw_consumer != NULL) { | |
538 | pci_free_consistent(adapter->pdev, | |
539 | sizeof(u32), | |
540 | tx_ring->hw_consumer, | |
541 | tx_ring->hw_cons_phys_addr); | |
542 | tx_ring->hw_consumer = NULL; | |
543 | } | |
544 | ||
545 | if (tx_ring->desc_head != NULL) { | |
546 | pci_free_consistent(adapter->pdev, | |
547 | TX_DESC_RINGSIZE(tx_ring), | |
548 | tx_ring->desc_head, tx_ring->phys_addr); | |
549 | tx_ring->desc_head = NULL; | |
550 | } | |
551 | ||
552 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
553 | rds_ring = &recv_ctx->rds_rings[ring]; | |
554 | ||
555 | if (rds_ring->desc_head != NULL) { | |
556 | pci_free_consistent(adapter->pdev, | |
557 | RCV_DESC_RINGSIZE(rds_ring), | |
558 | rds_ring->desc_head, | |
559 | rds_ring->phys_addr); | |
560 | rds_ring->desc_head = NULL; | |
561 | } | |
562 | } | |
563 | ||
564 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
565 | sds_ring = &recv_ctx->sds_rings[ring]; | |
566 | ||
567 | if (sds_ring->desc_head != NULL) { | |
568 | pci_free_consistent(adapter->pdev, | |
569 | STATUS_DESC_RINGSIZE(sds_ring), | |
570 | sds_ring->desc_head, | |
571 | sds_ring->phys_addr); | |
572 | sds_ring->desc_head = NULL; | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
2e9d722d AC |
577 | /* Set MAC address of a NIC partition */ |
578 | int qlcnic_set_mac_address(struct qlcnic_adapter *adapter, u8* mac) | |
579 | { | |
580 | int err = 0; | |
581 | u32 arg1, arg2, arg3; | |
582 | ||
583 | arg1 = adapter->ahw.pci_func | BIT_9; | |
584 | arg2 = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24); | |
585 | arg3 = mac[4] | (mac[5] << 16); | |
586 | ||
587 | err = qlcnic_issue_cmd(adapter, | |
588 | adapter->ahw.pci_func, | |
589 | adapter->fw_hal_version, | |
590 | arg1, | |
591 | arg2, | |
592 | arg3, | |
593 | QLCNIC_CDRP_CMD_MAC_ADDRESS); | |
594 | ||
595 | if (err != QLCNIC_RCODE_SUCCESS) { | |
596 | dev_err(&adapter->pdev->dev, | |
597 | "Failed to set mac address%d\n", err); | |
598 | err = -EIO; | |
599 | } | |
600 | ||
601 | return err; | |
602 | } | |
603 | ||
604 | /* Get MAC address of a NIC partition */ | |
605 | int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac) | |
606 | { | |
607 | int err; | |
608 | u32 arg1; | |
609 | ||
610 | arg1 = adapter->ahw.pci_func | BIT_8; | |
611 | err = qlcnic_issue_cmd(adapter, | |
612 | adapter->ahw.pci_func, | |
613 | adapter->fw_hal_version, | |
614 | arg1, | |
615 | 0, | |
616 | 0, | |
617 | QLCNIC_CDRP_CMD_MAC_ADDRESS); | |
618 | ||
7f9a0c34 | 619 | if (err == QLCNIC_RCODE_SUCCESS) |
2e9d722d AC |
620 | qlcnic_fetch_mac(adapter, QLCNIC_ARG1_CRB_OFFSET, |
621 | QLCNIC_ARG2_CRB_OFFSET, 0, mac); | |
7f9a0c34 | 622 | else { |
2e9d722d AC |
623 | dev_err(&adapter->pdev->dev, |
624 | "Failed to get mac address%d\n", err); | |
625 | err = -EIO; | |
626 | } | |
627 | ||
628 | return err; | |
629 | } | |
630 | ||
631 | /* Get info of a NIC partition */ | |
632 | int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, u8 func_id) | |
633 | { | |
634 | int err; | |
635 | dma_addr_t nic_dma_t; | |
636 | struct qlcnic_info *nic_info; | |
637 | void *nic_info_addr; | |
638 | size_t nic_size = sizeof(struct qlcnic_info); | |
639 | ||
640 | nic_info_addr = pci_alloc_consistent(adapter->pdev, | |
641 | nic_size, &nic_dma_t); | |
642 | if (!nic_info_addr) | |
643 | return -ENOMEM; | |
644 | memset(nic_info_addr, 0, nic_size); | |
645 | ||
646 | nic_info = (struct qlcnic_info *) nic_info_addr; | |
647 | err = qlcnic_issue_cmd(adapter, | |
648 | adapter->ahw.pci_func, | |
649 | adapter->fw_hal_version, | |
650 | MSD(nic_dma_t), | |
651 | LSD(nic_dma_t), | |
652 | (func_id << 16 | nic_size), | |
653 | QLCNIC_CDRP_CMD_GET_NIC_INFO); | |
654 | ||
655 | if (err == QLCNIC_RCODE_SUCCESS) { | |
656 | adapter->physical_port = le16_to_cpu(nic_info->phys_port); | |
657 | adapter->switch_mode = le16_to_cpu(nic_info->switch_mode); | |
658 | adapter->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques); | |
659 | adapter->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques); | |
660 | adapter->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw); | |
661 | adapter->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw); | |
662 | adapter->max_mtu = le16_to_cpu(nic_info->max_mtu); | |
663 | adapter->capabilities = le32_to_cpu(nic_info->capabilities); | |
664 | adapter->max_mac_filters = nic_info->max_mac_filters; | |
665 | ||
0e33c664 AC |
666 | if (adapter->capabilities & BIT_6) |
667 | adapter->flags |= QLCNIC_ESWITCH_ENABLED; | |
668 | else | |
669 | adapter->flags &= ~QLCNIC_ESWITCH_ENABLED; | |
670 | ||
2e9d722d AC |
671 | dev_info(&adapter->pdev->dev, |
672 | "phy port: %d switch_mode: %d,\n" | |
673 | "\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n" | |
674 | "\tmax_tx_bw: 0x%x max_mtu:0x%x, capabilities: 0x%x\n", | |
675 | adapter->physical_port, adapter->switch_mode, | |
676 | adapter->max_tx_ques, adapter->max_rx_ques, | |
677 | adapter->min_tx_bw, adapter->max_tx_bw, | |
678 | adapter->max_mtu, adapter->capabilities); | |
679 | } else { | |
680 | dev_err(&adapter->pdev->dev, | |
681 | "Failed to get nic info%d\n", err); | |
682 | err = -EIO; | |
683 | } | |
684 | ||
685 | pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t); | |
686 | return err; | |
687 | } | |
688 | ||
689 | /* Configure a NIC partition */ | |
690 | int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, struct qlcnic_info *nic) | |
691 | { | |
692 | int err = -EIO; | |
693 | u32 func_state; | |
694 | dma_addr_t nic_dma_t; | |
695 | void *nic_info_addr; | |
696 | struct qlcnic_info *nic_info; | |
697 | size_t nic_size = sizeof(struct qlcnic_info); | |
698 | ||
699 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
700 | return err; | |
701 | ||
702 | if (qlcnic_api_lock(adapter)) | |
703 | return err; | |
704 | ||
705 | func_state = QLCRD32(adapter, QLCNIC_CRB_DEV_REF_COUNT); | |
706 | if (QLC_DEV_CHECK_ACTIVE(func_state, nic->pci_func)) { | |
707 | qlcnic_api_unlock(adapter); | |
708 | return err; | |
709 | } | |
710 | ||
711 | qlcnic_api_unlock(adapter); | |
712 | ||
713 | nic_info_addr = pci_alloc_consistent(adapter->pdev, nic_size, | |
714 | &nic_dma_t); | |
715 | if (!nic_info_addr) | |
716 | return -ENOMEM; | |
717 | ||
718 | memset(nic_info_addr, 0, nic_size); | |
719 | nic_info = (struct qlcnic_info *)nic_info_addr; | |
720 | ||
721 | nic_info->pci_func = cpu_to_le16(nic->pci_func); | |
722 | nic_info->op_mode = cpu_to_le16(nic->op_mode); | |
723 | nic_info->phys_port = cpu_to_le16(nic->phys_port); | |
724 | nic_info->switch_mode = cpu_to_le16(nic->switch_mode); | |
725 | nic_info->capabilities = cpu_to_le32(nic->capabilities); | |
726 | nic_info->max_mac_filters = nic->max_mac_filters; | |
727 | nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques); | |
728 | nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques); | |
729 | nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw); | |
730 | nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw); | |
731 | ||
732 | err = qlcnic_issue_cmd(adapter, | |
733 | adapter->ahw.pci_func, | |
734 | adapter->fw_hal_version, | |
735 | MSD(nic_dma_t), | |
736 | LSD(nic_dma_t), | |
737 | nic_size, | |
738 | QLCNIC_CDRP_CMD_SET_NIC_INFO); | |
739 | ||
740 | if (err != QLCNIC_RCODE_SUCCESS) { | |
741 | dev_err(&adapter->pdev->dev, | |
742 | "Failed to set nic info%d\n", err); | |
743 | err = -EIO; | |
744 | } | |
745 | ||
746 | pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t); | |
747 | return err; | |
748 | } | |
749 | ||
750 | /* Get PCI Info of a partition */ | |
751 | int qlcnic_get_pci_info(struct qlcnic_adapter *adapter) | |
752 | { | |
753 | int err = 0, i; | |
754 | dma_addr_t pci_info_dma_t; | |
755 | struct qlcnic_pci_info *npar; | |
756 | void *pci_info_addr; | |
757 | size_t npar_size = sizeof(struct qlcnic_pci_info); | |
758 | size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC; | |
759 | ||
760 | pci_info_addr = pci_alloc_consistent(adapter->pdev, pci_size, | |
761 | &pci_info_dma_t); | |
762 | if (!pci_info_addr) | |
763 | return -ENOMEM; | |
764 | memset(pci_info_addr, 0, pci_size); | |
765 | ||
766 | if (!adapter->npars) | |
767 | adapter->npars = kzalloc(pci_size, GFP_KERNEL); | |
768 | if (!adapter->npars) { | |
769 | err = -ENOMEM; | |
770 | goto err_npar; | |
771 | } | |
772 | ||
773 | if (!adapter->eswitch) | |
774 | adapter->eswitch = kzalloc(sizeof(struct qlcnic_eswitch) * | |
775 | QLCNIC_NIU_MAX_XG_PORTS, GFP_KERNEL); | |
776 | if (!adapter->eswitch) { | |
777 | err = -ENOMEM; | |
778 | goto err_eswitch; | |
779 | } | |
780 | ||
781 | npar = (struct qlcnic_pci_info *) pci_info_addr; | |
782 | err = qlcnic_issue_cmd(adapter, | |
783 | adapter->ahw.pci_func, | |
784 | adapter->fw_hal_version, | |
785 | MSD(pci_info_dma_t), | |
786 | LSD(pci_info_dma_t), | |
787 | pci_size, | |
788 | QLCNIC_CDRP_CMD_GET_PCI_INFO); | |
789 | ||
790 | if (err == QLCNIC_RCODE_SUCCESS) { | |
791 | for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++) { | |
792 | adapter->npars[i].id = le32_to_cpu(npar->id); | |
793 | adapter->npars[i].active = le32_to_cpu(npar->active); | |
794 | adapter->npars[i].type = le32_to_cpu(npar->type); | |
795 | adapter->npars[i].default_port = | |
796 | le32_to_cpu(npar->default_port); | |
797 | adapter->npars[i].tx_min_bw = | |
798 | le32_to_cpu(npar->tx_min_bw); | |
799 | adapter->npars[i].tx_max_bw = | |
800 | le32_to_cpu(npar->tx_max_bw); | |
801 | memcpy(adapter->npars[i].mac, npar->mac, ETH_ALEN); | |
802 | } | |
803 | } else { | |
804 | dev_err(&adapter->pdev->dev, | |
805 | "Failed to get PCI Info%d\n", err); | |
806 | kfree(adapter->npars); | |
807 | err = -EIO; | |
808 | } | |
809 | goto err_npar; | |
810 | ||
811 | err_eswitch: | |
812 | kfree(adapter->npars); | |
813 | adapter->npars = NULL; | |
814 | ||
815 | err_npar: | |
816 | pci_free_consistent(adapter->pdev, pci_size, pci_info_addr, | |
817 | pci_info_dma_t); | |
818 | return err; | |
819 | } | |
820 | ||
821 | /* Reset a NIC partition */ | |
822 | ||
823 | int qlcnic_reset_partition(struct qlcnic_adapter *adapter, u8 func_no) | |
824 | { | |
825 | int err = -EIO; | |
826 | ||
827 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
828 | return err; | |
829 | ||
830 | err = qlcnic_issue_cmd(adapter, | |
831 | adapter->ahw.pci_func, | |
832 | adapter->fw_hal_version, | |
833 | func_no, | |
834 | 0, | |
835 | 0, | |
836 | QLCNIC_CDRP_CMD_RESET_NPAR); | |
837 | ||
838 | if (err != QLCNIC_RCODE_SUCCESS) { | |
839 | dev_err(&adapter->pdev->dev, | |
840 | "Failed to issue reset partition%d\n", err); | |
841 | err = -EIO; | |
842 | } | |
843 | ||
844 | return err; | |
845 | } | |
846 | ||
847 | /* Get eSwitch Capabilities */ | |
848 | int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *adapter, u8 port, | |
849 | struct qlcnic_eswitch *eswitch) | |
850 | { | |
851 | int err = -EIO; | |
852 | u32 arg1, arg2; | |
853 | ||
854 | if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) | |
855 | return err; | |
856 | ||
857 | err = qlcnic_issue_cmd(adapter, | |
858 | adapter->ahw.pci_func, | |
859 | adapter->fw_hal_version, | |
860 | port, | |
861 | 0, | |
862 | 0, | |
863 | QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY); | |
864 | ||
865 | if (err == QLCNIC_RCODE_SUCCESS) { | |
866 | arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
867 | arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET); | |
868 | ||
869 | eswitch->port = arg1 & 0xf; | |
870 | eswitch->active_vports = LSB(arg2); | |
871 | eswitch->max_ucast_filters = MSB(arg2); | |
872 | eswitch->max_active_vlans = LSB(MSW(arg2)); | |
873 | if (arg1 & BIT_6) | |
874 | eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING; | |
875 | if (arg1 & BIT_7) | |
876 | eswitch->flags |= QLCNIC_SWITCH_PROMISC_MODE; | |
877 | if (arg1 & BIT_8) | |
878 | eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING; | |
879 | } else { | |
880 | dev_err(&adapter->pdev->dev, | |
881 | "Failed to get eswitch capabilities%d\n", err); | |
882 | } | |
883 | ||
884 | return err; | |
885 | } | |
886 | ||
887 | /* Get current status of eswitch */ | |
888 | int qlcnic_get_eswitch_status(struct qlcnic_adapter *adapter, u8 port, | |
889 | struct qlcnic_eswitch *eswitch) | |
890 | { | |
891 | int err = -EIO; | |
892 | u32 arg1, arg2; | |
893 | ||
894 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
895 | return err; | |
896 | ||
897 | err = qlcnic_issue_cmd(adapter, | |
898 | adapter->ahw.pci_func, | |
899 | adapter->fw_hal_version, | |
900 | port, | |
901 | 0, | |
902 | 0, | |
903 | QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS); | |
904 | ||
905 | if (err == QLCNIC_RCODE_SUCCESS) { | |
906 | arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
907 | arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET); | |
908 | ||
909 | eswitch->port = arg1 & 0xf; | |
910 | eswitch->active_vports = LSB(arg2); | |
911 | eswitch->active_ucast_filters = MSB(arg2); | |
912 | eswitch->active_vlans = LSB(MSW(arg2)); | |
913 | if (arg1 & BIT_6) | |
914 | eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING; | |
915 | if (arg1 & BIT_8) | |
916 | eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING; | |
917 | ||
918 | } else { | |
919 | dev_err(&adapter->pdev->dev, | |
920 | "Failed to get eswitch status%d\n", err); | |
921 | } | |
922 | ||
923 | return err; | |
924 | } | |
925 | ||
926 | /* Enable/Disable eSwitch */ | |
927 | int qlcnic_toggle_eswitch(struct qlcnic_adapter *adapter, u8 id, u8 enable) | |
928 | { | |
929 | int err = -EIO; | |
930 | u32 arg1, arg2; | |
931 | struct qlcnic_eswitch *eswitch; | |
932 | ||
933 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
934 | return err; | |
935 | ||
936 | eswitch = &adapter->eswitch[id]; | |
937 | if (!eswitch) | |
938 | return err; | |
939 | ||
940 | arg1 = eswitch->port | (enable ? BIT_4 : 0); | |
941 | arg2 = eswitch->active_vports | (eswitch->max_ucast_filters << 8) | | |
942 | (eswitch->max_active_vlans << 16); | |
943 | err = qlcnic_issue_cmd(adapter, | |
944 | adapter->ahw.pci_func, | |
945 | adapter->fw_hal_version, | |
946 | arg1, | |
947 | arg2, | |
948 | 0, | |
949 | QLCNIC_CDRP_CMD_TOGGLE_ESWITCH); | |
950 | ||
951 | if (err != QLCNIC_RCODE_SUCCESS) { | |
952 | dev_err(&adapter->pdev->dev, | |
953 | "Failed to enable eswitch%d\n", eswitch->port); | |
954 | eswitch->flags &= ~QLCNIC_SWITCH_ENABLE; | |
955 | err = -EIO; | |
956 | } else { | |
957 | eswitch->flags |= QLCNIC_SWITCH_ENABLE; | |
958 | dev_info(&adapter->pdev->dev, | |
959 | "Enabled eSwitch for port %d\n", eswitch->port); | |
960 | } | |
961 | ||
962 | return err; | |
963 | } | |
964 | ||
965 | /* Configure eSwitch for port mirroring */ | |
966 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id, | |
967 | u8 enable_mirroring, u8 pci_func) | |
968 | { | |
969 | int err = -EIO; | |
970 | u32 arg1; | |
971 | ||
972 | if (adapter->op_mode != QLCNIC_MGMT_FUNC || | |
973 | !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) | |
974 | return err; | |
975 | ||
976 | arg1 = id | (enable_mirroring ? BIT_4 : 0); | |
977 | arg1 |= pci_func << 8; | |
978 | ||
979 | err = qlcnic_issue_cmd(adapter, | |
980 | adapter->ahw.pci_func, | |
981 | adapter->fw_hal_version, | |
982 | arg1, | |
983 | 0, | |
984 | 0, | |
985 | QLCNIC_CDRP_CMD_SET_PORTMIRRORING); | |
986 | ||
987 | if (err != QLCNIC_RCODE_SUCCESS) { | |
988 | dev_err(&adapter->pdev->dev, | |
989 | "Failed to configure port mirroring%d on eswitch:%d\n", | |
990 | pci_func, id); | |
991 | } else { | |
992 | dev_info(&adapter->pdev->dev, | |
993 | "Configured eSwitch %d for port mirroring:%d\n", | |
994 | id, pci_func); | |
995 | } | |
996 | ||
997 | return err; | |
998 | } | |
999 | ||
1000 | /* Configure eSwitch port */ | |
1001 | int qlcnic_config_switch_port(struct qlcnic_adapter *adapter, u8 id, | |
1002 | int vlan_tagging, u8 discard_tagged, u8 promsc_mode, | |
1003 | u8 mac_learn, u8 pci_func, u16 vlan_id) | |
1004 | { | |
1005 | int err = -EIO; | |
1006 | u32 arg1; | |
1007 | struct qlcnic_eswitch *eswitch; | |
1008 | ||
1009 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
1010 | return err; | |
1011 | ||
1012 | eswitch = &adapter->eswitch[id]; | |
1013 | if (!(eswitch->flags & QLCNIC_SWITCH_ENABLE)) | |
1014 | return err; | |
1015 | ||
1016 | arg1 = eswitch->port | (discard_tagged ? BIT_4 : 0); | |
1017 | arg1 |= (promsc_mode ? BIT_6 : 0) | (mac_learn ? BIT_7 : 0); | |
1018 | arg1 |= pci_func << 8; | |
1019 | if (vlan_tagging) | |
1020 | arg1 |= BIT_5 | (vlan_id << 16); | |
1021 | ||
1022 | err = qlcnic_issue_cmd(adapter, | |
1023 | adapter->ahw.pci_func, | |
1024 | adapter->fw_hal_version, | |
1025 | arg1, | |
1026 | 0, | |
1027 | 0, | |
1028 | QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH); | |
1029 | ||
1030 | if (err != QLCNIC_RCODE_SUCCESS) { | |
1031 | dev_err(&adapter->pdev->dev, | |
1032 | "Failed to configure eswitch port%d\n", eswitch->port); | |
1033 | eswitch->flags |= QLCNIC_SWITCH_ENABLE; | |
1034 | } else { | |
1035 | eswitch->flags &= ~QLCNIC_SWITCH_ENABLE; | |
1036 | dev_info(&adapter->pdev->dev, | |
1037 | "Configured eSwitch for port %d\n", eswitch->port); | |
1038 | } | |
1039 | ||
1040 | return err; | |
1041 | } |