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gianfar: Add per queue structure support
[net-next-2.6.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
1da177e4
LT		 85
86#include <asm/io.h>
87#include <asm/irq.h>
88#include <asm/uaccess.h>
89#include <linux/module.h>
1da177e4
LT		 90#include <linux/dma-mapping.h>
91#include <linux/crc32.h>
bb40dcbb
AF		 92#include <linux/mii.h>
93#include <linux/phy.h>
b31a1d8b
AF		 94#include <linux/phy_fixed.h>
95#include <linux/of.h>
1da177e4
LT		 96
97#include "gianfar.h"
1577ecef 98#include "fsl_pq_mdio.h"
1da177e4
LT		 99
100#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 101#undef BRIEF_GFAR_ERRORS
102#undef VERBOSE_GFAR_ERRORS
103
1da177e4 104const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 105const char gfar_driver_version[] = "1.3";
1da177e4 106
1da177e4
LT		 107static int gfar_enet_open(struct net_device *dev);
108static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 109static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 110static void gfar_timeout(struct net_device *dev);
111static int gfar_close(struct net_device *dev);
815b97c6 112struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 113static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 114 struct sk_buff *skb);
1da177e4
LT		 115static int gfar_set_mac_address(struct net_device *dev);
116static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 117static irqreturn_t gfar_error(int irq, void *dev_id);
118static irqreturn_t gfar_transmit(int irq, void *dev_id);
119static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 120static void adjust_link(struct net_device *dev);
121static void init_registers(struct net_device *dev);
122static int init_phy(struct net_device *dev);
b31a1d8b
AF		 123static int gfar_probe(struct of_device *ofdev,
124 const struct of_device_id *match);
125static int gfar_remove(struct of_device *ofdev);
bb40dcbb 126static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 127static void gfar_set_multi(struct net_device *dev);
128static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 129static void gfar_configure_serdes(struct net_device *dev);
bea3348e 130static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 131#ifdef CONFIG_NET_POLL_CONTROLLER
132static void gfar_netpoll(struct net_device *dev);
133#endif
a12f801d
SG		 134int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 136static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull);
0bbaf069
KG		 138static void gfar_vlan_rx_register(struct net_device *netdev,
139 struct vlan_group *grp);
7f7f5316 140void gfar_halt(struct net_device *dev);
d87eb127 141static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 142void gfar_start(struct net_device *dev);
143static void gfar_clear_exact_match(struct net_device *dev);
144static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 145static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 146
1da177e4
LT		 147MODULE_AUTHOR("Freescale Semiconductor, Inc");
148MODULE_DESCRIPTION("Gianfar Ethernet Driver");
149MODULE_LICENSE("GPL");
150
a12f801d 151static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 152 dma_addr_t buf)
153{
a12f801d 154 struct net_device *dev = rx_queue->dev;
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
8728327e
AV		 175 int i;
176
a12f801d
SG		 177 tx_queue = priv->tx_queue;
178 rx_queue = priv->rx_queue;
179
8728327e 180 /* Initialize some variables in our dev structure */
a12f801d
SG		 181 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182 tx_queue->dirty_tx = tx_queue->cur_tx = tx_queue->tx_bd_base;
183 rx_queue->cur_rx = rx_queue->rx_bd_base;
184 tx_queue->skb_curtx = tx_queue->skb_dirtytx = 0;
185 rx_queue->skb_currx = 0;
8728327e
AV		 186
187 /* Initialize Transmit Descriptor Ring */
a12f801d
SG		 188 txbdp = tx_queue->tx_bd_base;
189 for (i = 0; i < tx_queue->tx_ring_size; i++) {
8728327e
AV		 190 txbdp->lstatus = 0;
191 txbdp->bufPtr = 0;
192 txbdp++;
193 }
194
195 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp--;
197 txbdp->status |= TXBD_WRAP;
198
a12f801d
SG		 199 rxbdp = rx_queue->rx_bd_base;
200 for (i = 0; i < rx_queue->rx_ring_size; i++) {
201 struct sk_buff *skb = rx_queue->rx_skbuff[i];
8728327e
AV		 202
203 if (skb) {
a12f801d 204 gfar_init_rxbdp(rx_queue, rxbdp, rxbdp->bufPtr);
8728327e
AV		 205 } else {
206 skb = gfar_new_skb(ndev);
207 if (!skb) {
208 pr_err("%s: Can't allocate RX buffers\n",
209 ndev->name);
210 return -ENOMEM;
211 }
a12f801d 212 rx_queue->rx_skbuff[i] = skb;
8728327e 213
a12f801d 214 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e
AV		 215 }
216
217 rxbdp++;
218 }
219
220 return 0;
221}
222
223static int gfar_alloc_skb_resources(struct net_device *ndev)
224{
826aa4a0
AV		 225 void *vaddr;
226 int i;
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
231
232 tx_queue = priv->tx_queue;
233 rx_queue = priv->rx_queue;
826aa4a0
AV		 234
235 /* Allocate memory for the buffer descriptors */
8728327e 236 vaddr = dma_alloc_coherent(dev,
a12f801d
SG		 237 sizeof(*tx_queue->tx_bd_base) * tx_queue->tx_ring_size +
238 sizeof(*rx_queue->rx_bd_base) * rx_queue->rx_ring_size,
239 &tx_queue->tx_bd_dma_base, GFP_KERNEL);
826aa4a0
AV		 240 if (!vaddr) {
241 if (netif_msg_ifup(priv))
242 pr_err("%s: Could not allocate buffer descriptors!\n",
243 ndev->name);
244 return -ENOMEM;
245 }
246
a12f801d
SG		 247 tx_queue->tx_bd_base = vaddr;
248 tx_queue->dev = ndev;
826aa4a0 249
826aa4a0 250 /* Start the rx descriptor ring where the tx ring leaves off */
a12f801d
SG		 251 vaddr = vaddr + sizeof(*tx_queue->tx_bd_base) * tx_queue->tx_ring_size;
252 rx_queue->rx_bd_base = vaddr;
253 rx_queue->dev = ndev;
826aa4a0
AV		 254
255 /* Setup the skbuff rings */
a12f801d
SG		 256 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
257 tx_queue->tx_ring_size, GFP_KERNEL);
258 if (!tx_queue->tx_skbuff) {
826aa4a0
AV		 259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate tx_skbuff\n",
261 ndev->name);
262 goto cleanup;
263 }
264
a12f801d
SG		 265 for (i = 0; i < tx_queue->tx_ring_size; i++)
266 tx_queue->tx_skbuff[i] = NULL;
826aa4a0 267
a12f801d
SG		 268 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
269 rx_queue->rx_ring_size, GFP_KERNEL);
270 if (!rx_queue->rx_skbuff) {
826aa4a0
AV		 271 if (netif_msg_ifup(priv))
272 pr_err("%s: Could not allocate rx_skbuff\n",
273 ndev->name);
274 goto cleanup;
275 }
276
a12f801d
SG		 277 for (i = 0; i < rx_queue->rx_ring_size; i++)
278 rx_queue->rx_skbuff[i] = NULL;
826aa4a0 279
8728327e
AV		 280 if (gfar_init_bds(ndev))
281 goto cleanup;
826aa4a0
AV		 282
283 return 0;
284
285cleanup:
286 free_skb_resources(priv);
287 return -ENOMEM;
288}
289
290static void gfar_init_mac(struct net_device *ndev)
291{
292 struct gfar_private *priv = netdev_priv(ndev);
293 struct gfar __iomem *regs = priv->regs;
a12f801d
SG		 294 struct gfar_priv_tx_q *tx_queue = NULL;
295 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 296 u32 rctrl = 0;
297 u32 tctrl = 0;
298 u32 attrs = 0;
299
a12f801d
SG		 300 tx_queue = priv->tx_queue;
301 rx_queue = priv->rx_queue;
302
32c513bc 303 /* enet DMA only understands physical addresses */
a12f801d
SG		 304 gfar_write(&regs->tbase0, tx_queue->tx_bd_dma_base);
305 gfar_write(&regs->rbase0, tx_queue->tx_bd_dma_base +
306 sizeof(*tx_queue->tx_bd_base) *
307 tx_queue->tx_ring_size);
32c513bc 308
826aa4a0
AV		 309 /* Configure the coalescing support */
310 gfar_write(&regs->txic, 0);
a12f801d
SG		 311 if (tx_queue->txcoalescing)
312 gfar_write(&regs->txic, tx_queue->txic);
826aa4a0
AV		 313
314 gfar_write(&regs->rxic, 0);
a12f801d
SG		 315 if (rx_queue->rxcoalescing)
316 gfar_write(&regs->rxic, rx_queue->rxic);
826aa4a0
AV		 317
318 if (priv->rx_csum_enable)
319 rctrl |= RCTRL_CHECKSUMMING;
320
321 if (priv->extended_hash) {
322 rctrl |= RCTRL_EXTHASH;
323
324 gfar_clear_exact_match(ndev);
325 rctrl |= RCTRL_EMEN;
326 }
327
328 if (priv->padding) {
329 rctrl &= ~RCTRL_PAL_MASK;
330 rctrl |= RCTRL_PADDING(priv->padding);
331 }
332
333 /* keep vlan related bits if it's enabled */
334 if (priv->vlgrp) {
335 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
336 tctrl |= TCTRL_VLINS;
337 }
338
339 /* Init rctrl based on our settings */
340 gfar_write(&regs->rctrl, rctrl);
341
342 if (ndev->features & NETIF_F_IP_CSUM)
343 tctrl |= TCTRL_INIT_CSUM;
344
345 gfar_write(&regs->tctrl, tctrl);
346
347 /* Set the extraction length and index */
348 attrs = ATTRELI_EL(priv->rx_stash_size) |
349 ATTRELI_EI(priv->rx_stash_index);
350
351 gfar_write(&regs->attreli, attrs);
352
353 /* Start with defaults, and add stashing or locking
354 * depending on the approprate variables */
355 attrs = ATTR_INIT_SETTINGS;
356
357 if (priv->bd_stash_en)
358 attrs |= ATTR_BDSTASH;
359
360 if (priv->rx_stash_size != 0)
361 attrs |= ATTR_BUFSTASH;
362
363 gfar_write(&regs->attr, attrs);
364
365 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
366 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
367 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
368}
369
26ccfc37
AF		 370static const struct net_device_ops gfar_netdev_ops = {
371 .ndo_open = gfar_enet_open,
372 .ndo_start_xmit = gfar_start_xmit,
373 .ndo_stop = gfar_close,
374 .ndo_change_mtu = gfar_change_mtu,
375 .ndo_set_multicast_list = gfar_set_multi,
376 .ndo_tx_timeout = gfar_timeout,
377 .ndo_do_ioctl = gfar_ioctl,
378 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 379 .ndo_set_mac_address = eth_mac_addr,
380 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 381#ifdef CONFIG_NET_POLL_CONTROLLER
382 .ndo_poll_controller = gfar_netpoll,
383#endif
384};
385
7f7f5316
AF		 386/* Returns 1 if incoming frames use an FCB */
387static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 388{
77ecaf2d 389 return priv->vlgrp || priv->rx_csum_enable;
0bbaf069 390}
bb40dcbb 391
b31a1d8b
AF		 392static int gfar_of_init(struct net_device *dev)
393{
b31a1d8b
AF		 394 const char *model;
395 const char *ctype;
396 const void *mac_addr;
b31a1d8b
AF		 397 u64 addr, size;
398 int err = 0;
399 struct gfar_private *priv = netdev_priv(dev);
400 struct device_node *np = priv->node;
4d7902f2
AF		 401 const u32 *stash;
402 const u32 *stash_len;
403 const u32 *stash_idx;
b31a1d8b
AF		 404
405 if (!np || !of_device_is_available(np))
406 return -ENODEV;
407
408 /* get a pointer to the register memory */
409 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
410 priv->regs = ioremap(addr, size);
411
412 if (priv->regs == NULL)
413 return -ENOMEM;
414
415 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
416
417 model = of_get_property(np, "model", NULL);
418
419 /* If we aren't the FEC we have multiple interrupts */
420 if (model && strcasecmp(model, "FEC")) {
421 priv->interruptReceive = irq_of_parse_and_map(np, 1);
422
423 priv->interruptError = irq_of_parse_and_map(np, 2);
424
425 if (priv->interruptTransmit < 0 ||
426 priv->interruptReceive < 0 ||
427 priv->interruptError < 0) {
428 err = -EINVAL;
429 goto err_out;
430 }
431 }
432
4d7902f2
AF		 433 stash = of_get_property(np, "bd-stash", NULL);
434
a12f801d 435 if (stash) {
4d7902f2
AF		 436 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
437 priv->bd_stash_en = 1;
438 }
439
440 stash_len = of_get_property(np, "rx-stash-len", NULL);
441
442 if (stash_len)
443 priv->rx_stash_size = *stash_len;
444
445 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
446
447 if (stash_idx)
448 priv->rx_stash_index = *stash_idx;
449
450 if (stash_len || stash_idx)
451 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
452
b31a1d8b
AF		 453 mac_addr = of_get_mac_address(np);
454 if (mac_addr)
455 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
456
457 if (model && !strcasecmp(model, "TSEC"))
458 priv->device_flags =
459 FSL_GIANFAR_DEV_HAS_GIGABIT |
460 FSL_GIANFAR_DEV_HAS_COALESCE |
461 FSL_GIANFAR_DEV_HAS_RMON |
462 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
463 if (model && !strcasecmp(model, "eTSEC"))
464 priv->device_flags =
465 FSL_GIANFAR_DEV_HAS_GIGABIT |
466 FSL_GIANFAR_DEV_HAS_COALESCE |
467 FSL_GIANFAR_DEV_HAS_RMON |
468 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 469 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 470 FSL_GIANFAR_DEV_HAS_CSUM |
471 FSL_GIANFAR_DEV_HAS_VLAN |
472 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
473 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
474
475 ctype = of_get_property(np, "phy-connection-type", NULL);
476
477 /* We only care about rgmii-id. The rest are autodetected */
478 if (ctype && !strcmp(ctype, "rgmii-id"))
479 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
480 else
481 priv->interface = PHY_INTERFACE_MODE_MII;
482
483 if (of_get_property(np, "fsl,magic-packet", NULL))
484 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
485
fe192a49 486 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 487
488 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 489 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 490
491 return 0;
492
493err_out:
494 iounmap(priv->regs);
495 return err;
496}
497
0faac9f7
CW		 498/* Ioctl MII Interface */
499static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
500{
501 struct gfar_private *priv = netdev_priv(dev);
502
503 if (!netif_running(dev))
504 return -EINVAL;
505
506 if (!priv->phydev)
507 return -ENODEV;
508
509 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
510}
511
bb40dcbb
AF		 512/* Set up the ethernet device structure, private data,
513 * and anything else we need before we start */
b31a1d8b
AF		 514static int gfar_probe(struct of_device *ofdev,
515 const struct of_device_id *match)
1da177e4
LT		 516{
517 u32 tempval;
518 struct net_device *dev = NULL;
519 struct gfar_private *priv = NULL;
c50a5d9a
DH		 520 int err = 0;
521 int len_devname;
1da177e4
LT		 522
523 /* Create an ethernet device instance */
524 dev = alloc_etherdev(sizeof (*priv));
525
bb40dcbb 526 if (NULL == dev)
1da177e4
LT		 527 return -ENOMEM;
528
529 priv = netdev_priv(dev);
4826857f
KG		 530 priv->ndev = dev;
531 priv->ofdev = ofdev;
b31a1d8b 532 priv->node = ofdev->node;
4826857f 533 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 534
b31a1d8b 535 err = gfar_of_init(dev);
1da177e4 536
b31a1d8b 537 if (err)
1da177e4 538 goto regs_fail;
1da177e4 539
a12f801d
SG		 540 priv->tx_queue = (struct gfar_priv_tx_q *)kmalloc(
541 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
542 if (!priv->tx_queue)
543 goto regs_fail;
544
545 priv->rx_queue = (struct gfar_priv_rx_q *)kmalloc(
546 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
547 if (!priv->rx_queue)
548 goto rx_queue_fail;
549
550 spin_lock_init(&priv->tx_queue->txlock);
551 spin_lock_init(&priv->rx_queue->rxlock);
d87eb127 552 spin_lock_init(&priv->bflock);
ab939905 553 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 554
b31a1d8b 555 dev_set_drvdata(&ofdev->dev, priv);
1da177e4
LT		 556
557 /* Stop the DMA engine now, in case it was running before */
558 /* (The firmware could have used it, and left it running). */
257d938a 559 gfar_halt(dev);
1da177e4
LT		 560
561 /* Reset MAC layer */
562 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
563
b98ac702
AF		 564 /* We need to delay at least 3 TX clocks */
565 udelay(2);
566
1da177e4
LT		 567 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
568 gfar_write(&priv->regs->maccfg1, tempval);
569
570 /* Initialize MACCFG2. */
571 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
572
573 /* Initialize ECNTRL */
574 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
575
1da177e4
LT		 576 /* Set the dev->base_addr to the gfar reg region */
577 dev->base_addr = (unsigned long) (priv->regs);
578
b31a1d8b 579 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 580
581 /* Fill in the dev structure */
1da177e4 582 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 583 dev->mtu = 1500;
26ccfc37 584 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 585 dev->ethtool_ops = &gfar_ethtool_ops;
586
a12f801d
SG		 587 /* Register for napi ...NAPI is for each rx_queue */
588 netif_napi_add(dev, &priv->rx_queue->napi, gfar_poll, GFAR_DEV_WEIGHT);
589
b31a1d8b 590 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 591 priv->rx_csum_enable = 1;
4669bc90 592 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 593 } else
594 priv->rx_csum_enable = 0;
595
596 priv->vlgrp = NULL;
1da177e4 597
26ccfc37 598 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 599 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 600
b31a1d8b 601 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 602 priv->extended_hash = 1;
603 priv->hash_width = 9;
604
605 priv->hash_regs[0] = &priv->regs->igaddr0;
606 priv->hash_regs[1] = &priv->regs->igaddr1;
607 priv->hash_regs[2] = &priv->regs->igaddr2;
608 priv->hash_regs[3] = &priv->regs->igaddr3;
609 priv->hash_regs[4] = &priv->regs->igaddr4;
610 priv->hash_regs[5] = &priv->regs->igaddr5;
611 priv->hash_regs[6] = &priv->regs->igaddr6;
612 priv->hash_regs[7] = &priv->regs->igaddr7;
613 priv->hash_regs[8] = &priv->regs->gaddr0;
614 priv->hash_regs[9] = &priv->regs->gaddr1;
615 priv->hash_regs[10] = &priv->regs->gaddr2;
616 priv->hash_regs[11] = &priv->regs->gaddr3;
617 priv->hash_regs[12] = &priv->regs->gaddr4;
618 priv->hash_regs[13] = &priv->regs->gaddr5;
619 priv->hash_regs[14] = &priv->regs->gaddr6;
620 priv->hash_regs[15] = &priv->regs->gaddr7;
621
622 } else {
623 priv->extended_hash = 0;
624 priv->hash_width = 8;
625
626 priv->hash_regs[0] = &priv->regs->gaddr0;
1577ecef 627 priv->hash_regs[1] = &priv->regs->gaddr1;
0bbaf069
KG		 628 priv->hash_regs[2] = &priv->regs->gaddr2;
629 priv->hash_regs[3] = &priv->regs->gaddr3;
630 priv->hash_regs[4] = &priv->regs->gaddr4;
631 priv->hash_regs[5] = &priv->regs->gaddr5;
632 priv->hash_regs[6] = &priv->regs->gaddr6;
633 priv->hash_regs[7] = &priv->regs->gaddr7;
634 }
635
b31a1d8b 636 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 637 priv->padding = DEFAULT_PADDING;
638 else
639 priv->padding = 0;
640
0bbaf069
KG		 641 if (dev->features & NETIF_F_IP_CSUM)
642 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4
LT		 643
644 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 645
a12f801d
SG		 646 /* Initializing some of the rx/tx queue level parameters */
647 priv->tx_queue->tx_ring_size = DEFAULT_TX_RING_SIZE;
648 priv->tx_queue->num_txbdfree = DEFAULT_TX_RING_SIZE;
649 priv->tx_queue->txcoalescing = DEFAULT_TX_COALESCE;
650 priv->tx_queue->txic = DEFAULT_TXIC;
651
652 priv->rx_queue->rx_ring_size = DEFAULT_RX_RING_SIZE;
653 priv->rx_queue->rxcoalescing = DEFAULT_RX_COALESCE;
654 priv->rx_queue->rxic = DEFAULT_RXIC;
1da177e4 655
0bbaf069
KG		 656 /* Enable most messages by default */
657 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
658
d3eab82b
TP		 659 /* Carrier starts down, phylib will bring it up */
660 netif_carrier_off(dev);
661
1da177e4
LT		 662 err = register_netdev(dev);
663
664 if (err) {
665 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
666 dev->name);
667 goto register_fail;
668 }
669
2884e5cc
AV		 670 device_init_wakeup(&dev->dev,
671 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
672
c50a5d9a
DH		 673 /* fill out IRQ number and name fields */
674 len_devname = strlen(dev->name);
675 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
676 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
677 strncpy(&priv->int_name_tx[len_devname],
678 "_tx", sizeof("_tx") + 1);
679
680 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
681 strncpy(&priv->int_name_rx[len_devname],
682 "_rx", sizeof("_rx") + 1);
683
684 strncpy(&priv->int_name_er[0], dev->name, len_devname);
685 strncpy(&priv->int_name_er[len_devname],
686 "_er", sizeof("_er") + 1);
687 } else
688 priv->int_name_tx[len_devname] = '\0';
689
7f7f5316
AF		 690 /* Create all the sysfs files */
691 gfar_init_sysfs(dev);
692
1da177e4 693 /* Print out the device info */
e174961c 694 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 695
696 /* Even more device info helps when determining which kernel */
7f7f5316 697 /* provided which set of benchmarks. */
1da177e4 698 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1da177e4 699 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
a12f801d 700 dev->name, priv->rx_queue->rx_ring_size, priv->tx_queue->tx_ring_size);
1da177e4
LT		 701
702 return 0;
703
704register_fail:
cc8c6e37 705 iounmap(priv->regs);
a12f801d
SG		 706 kfree(priv->rx_queue);
707rx_queue_fail:
708 kfree(priv->tx_queue);
1da177e4 709regs_fail:
fe192a49
GL		 710 if (priv->phy_node)
711 of_node_put(priv->phy_node);
712 if (priv->tbi_node)
713 of_node_put(priv->tbi_node);
1da177e4 714 free_netdev(dev);
bb40dcbb 715 return err;
1da177e4
LT		 716}
717
b31a1d8b 718static int gfar_remove(struct of_device *ofdev)
1da177e4 719{
b31a1d8b 720 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 721
fe192a49
GL		 722 if (priv->phy_node)
723 of_node_put(priv->phy_node);
724 if (priv->tbi_node)
725 of_node_put(priv->tbi_node);
726
b31a1d8b 727 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 728
d9d8e041 729 unregister_netdev(priv->ndev);
cc8c6e37 730 iounmap(priv->regs);
4826857f 731 free_netdev(priv->ndev);
1da177e4
LT		 732
733 return 0;
734}
735
d87eb127 736#ifdef CONFIG_PM
be926fc4
AV		 737
738static int gfar_suspend(struct device *dev)
d87eb127 739{
be926fc4
AV		 740 struct gfar_private *priv = dev_get_drvdata(dev);
741 struct net_device *ndev = priv->ndev;
a12f801d
SG		 742 struct gfar_priv_tx_q *tx_queue = NULL;
743 struct gfar_priv_rx_q *rx_queue = NULL;
d87eb127
SW		 744 unsigned long flags;
745 u32 tempval;
746
747 int magic_packet = priv->wol_en &&
b31a1d8b 748 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 749
be926fc4 750 netif_device_detach(ndev);
a12f801d
SG		 751 tx_queue = priv->tx_queue;
752 rx_queue = priv->rx_queue;
d87eb127 753
be926fc4 754 if (netif_running(ndev)) {
a12f801d
SG		 755 spin_lock_irqsave(&tx_queue->txlock, flags);
756 spin_lock(&rx_queue->rxlock);
d87eb127 757
be926fc4 758 gfar_halt_nodisable(ndev);
d87eb127
SW		 759
760 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
761 tempval = gfar_read(&priv->regs->maccfg1);
762
763 tempval &= ~MACCFG1_TX_EN;
764
765 if (!magic_packet)
766 tempval &= ~MACCFG1_RX_EN;
767
768 gfar_write(&priv->regs->maccfg1, tempval);
769
a12f801d
SG		 770 spin_unlock(&rx_queue->rxlock);
771 spin_unlock_irqrestore(&tx_queue->txlock, flags);
d87eb127 772
a12f801d 773 napi_disable(&rx_queue->napi);
d87eb127
SW		 774
775 if (magic_packet) {
776 /* Enable interrupt on Magic Packet */
777 gfar_write(&priv->regs->imask, IMASK_MAG);
778
779 /* Enable Magic Packet mode */
780 tempval = gfar_read(&priv->regs->maccfg2);
781 tempval |= MACCFG2_MPEN;
782 gfar_write(&priv->regs->maccfg2, tempval);
783 } else {
784 phy_stop(priv->phydev);
785 }
786 }
787
788 return 0;
789}
790
be926fc4 791static int gfar_resume(struct device *dev)
d87eb127 792{
be926fc4
AV		 793 struct gfar_private *priv = dev_get_drvdata(dev);
794 struct net_device *ndev = priv->ndev;
a12f801d
SG		 795 struct gfar_priv_tx_q *tx_queue = NULL;
796 struct gfar_priv_rx_q *rx_queue = NULL;
d87eb127
SW		 797 unsigned long flags;
798 u32 tempval;
799 int magic_packet = priv->wol_en &&
b31a1d8b 800 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 801
be926fc4
AV		 802 if (!netif_running(ndev)) {
803 netif_device_attach(ndev);
d87eb127
SW		 804 return 0;
805 }
806
807 if (!magic_packet && priv->phydev)
808 phy_start(priv->phydev);
809
810 /* Disable Magic Packet mode, in case something
811 * else woke us up.
812 */
a12f801d
SG		 813 rx_queue = priv->rx_queue;
814 tx_queue = priv->tx_queue;
d87eb127 815
a12f801d
SG		 816 spin_lock_irqsave(&tx_queue->txlock, flags);
817 spin_lock(&rx_queue->rxlock);
d87eb127
SW		 818
819 tempval = gfar_read(&priv->regs->maccfg2);
820 tempval &= ~MACCFG2_MPEN;
821 gfar_write(&priv->regs->maccfg2, tempval);
822
be926fc4 823 gfar_start(ndev);
d87eb127 824
a12f801d
SG		 825 spin_unlock(&rx_queue->rxlock);
826 spin_unlock_irqrestore(&tx_queue->txlock, flags);
d87eb127 827
be926fc4
AV		 828 netif_device_attach(ndev);
829
a12f801d 830 napi_enable(&rx_queue->napi);
be926fc4
AV		 831
832 return 0;
833}
834
835static int gfar_restore(struct device *dev)
836{
837 struct gfar_private *priv = dev_get_drvdata(dev);
838 struct net_device *ndev = priv->ndev;
839
840 if (!netif_running(ndev))
841 return 0;
842
843 gfar_init_bds(ndev);
844 init_registers(ndev);
845 gfar_set_mac_address(ndev);
846 gfar_init_mac(ndev);
847 gfar_start(ndev);
848
849 priv->oldlink = 0;
850 priv->oldspeed = 0;
851 priv->oldduplex = -1;
852
853 if (priv->phydev)
854 phy_start(priv->phydev);
d87eb127 855
be926fc4 856 netif_device_attach(ndev);
d87eb127 857 napi_enable(&priv->napi);
d87eb127
SW		 858
859 return 0;
860}
be926fc4
AV		 861
862static struct dev_pm_ops gfar_pm_ops = {
863 .suspend = gfar_suspend,
864 .resume = gfar_resume,
865 .freeze = gfar_suspend,
866 .thaw = gfar_resume,
867 .restore = gfar_restore,
868};
869
870#define GFAR_PM_OPS (&gfar_pm_ops)
871
872static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
873{
874 return gfar_suspend(&ofdev->dev);
875}
876
877static int gfar_legacy_resume(struct of_device *ofdev)
878{
879 return gfar_resume(&ofdev->dev);
880}
881
d87eb127 882#else
be926fc4
AV		 883
884#define GFAR_PM_OPS NULL
885#define gfar_legacy_suspend NULL
886#define gfar_legacy_resume NULL
887
d87eb127 888#endif
1da177e4 889
e8a2b6a4
AF		 890/* Reads the controller's registers to determine what interface
891 * connects it to the PHY.
892 */
893static phy_interface_t gfar_get_interface(struct net_device *dev)
894{
895 struct gfar_private *priv = netdev_priv(dev);
896 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
897
898 if (ecntrl & ECNTRL_SGMII_MODE)
899 return PHY_INTERFACE_MODE_SGMII;
900
901 if (ecntrl & ECNTRL_TBI_MODE) {
902 if (ecntrl & ECNTRL_REDUCED_MODE)
903 return PHY_INTERFACE_MODE_RTBI;
904 else
905 return PHY_INTERFACE_MODE_TBI;
906 }
907
908 if (ecntrl & ECNTRL_REDUCED_MODE) {
909 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
910 return PHY_INTERFACE_MODE_RMII;
7132ab7f 911 else {
b31a1d8b 912 phy_interface_t interface = priv->interface;
7132ab7f
AF		 913
914 /*
915 * This isn't autodetected right now, so it must
916 * be set by the device tree or platform code.
917 */
918 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
919 return PHY_INTERFACE_MODE_RGMII_ID;
920
e8a2b6a4 921 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 922 }
e8a2b6a4
AF		 923 }
924
b31a1d8b 925 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 926 return PHY_INTERFACE_MODE_GMII;
927
928 return PHY_INTERFACE_MODE_MII;
929}
930
931
bb40dcbb
AF		 932/* Initializes driver's PHY state, and attaches to the PHY.
933 * Returns 0 on success.
1da177e4
LT		 934 */
935static int init_phy(struct net_device *dev)
936{
937 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 938 uint gigabit_support =
b31a1d8b 939 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 940 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 941 phy_interface_t interface;
1da177e4
LT		 942
943 priv->oldlink = 0;
944 priv->oldspeed = 0;
945 priv->oldduplex = -1;
946
e8a2b6a4
AF		 947 interface = gfar_get_interface(dev);
948
1db780f8
AV		 949 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
950 interface);
951 if (!priv->phydev)
952 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
953 interface);
954 if (!priv->phydev) {
955 dev_err(&dev->dev, "could not attach to PHY\n");
956 return -ENODEV;
fe192a49 957 }
1da177e4 958
d3c12873
KJ		 959 if (interface == PHY_INTERFACE_MODE_SGMII)
960 gfar_configure_serdes(dev);
961
bb40dcbb 962 /* Remove any features not supported by the controller */
fe192a49
GL		 963 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
964 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 965
966 return 0;
1da177e4
LT		 967}
968
d0313587
PG		 969/*
970 * Initialize TBI PHY interface for communicating with the
971 * SERDES lynx PHY on the chip. We communicate with this PHY
972 * through the MDIO bus on each controller, treating it as a
973 * "normal" PHY at the address found in the TBIPA register. We assume
974 * that the TBIPA register is valid. Either the MDIO bus code will set
975 * it to a value that doesn't conflict with other PHYs on the bus, or the
976 * value doesn't matter, as there are no other PHYs on the bus.
977 */
d3c12873
KJ		 978static void gfar_configure_serdes(struct net_device *dev)
979{
980 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 981 struct phy_device *tbiphy;
982
983 if (!priv->tbi_node) {
984 dev_warn(&dev->dev, "error: SGMII mode requires that the "
985 "device tree specify a tbi-handle\n");
986 return;
987 }
c132419e 988
fe192a49
GL		 989 tbiphy = of_phy_find_device(priv->tbi_node);
990 if (!tbiphy) {
991 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 992 return;
993 }
d3c12873 994
b31a1d8b
AF		 995 /*
996 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 997 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
998 * everything for us? Resetting it takes the link down and requires
999 * several seconds for it to come back.
1000 */
fe192a49 1001 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1002 return;
d3c12873 1003
d0313587 1004 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1005 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1006
fe192a49 1007 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1008 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1009 ADVERTISE_1000XPSE_ASYM);
1010
fe192a49 1011 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1012 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1013}
1014
1da177e4
LT		 1015static void init_registers(struct net_device *dev)
1016{
1017 struct gfar_private *priv = netdev_priv(dev);
1018
1019 /* Clear IEVENT */
1020 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
1021
1022 /* Initialize IMASK */
1023 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
1024
1025 /* Init hash registers to zero */
0bbaf069
KG		 1026 gfar_write(&priv->regs->igaddr0, 0);
1027 gfar_write(&priv->regs->igaddr1, 0);
1028 gfar_write(&priv->regs->igaddr2, 0);
1029 gfar_write(&priv->regs->igaddr3, 0);
1030 gfar_write(&priv->regs->igaddr4, 0);
1031 gfar_write(&priv->regs->igaddr5, 0);
1032 gfar_write(&priv->regs->igaddr6, 0);
1033 gfar_write(&priv->regs->igaddr7, 0);
1da177e4
LT		 1034
1035 gfar_write(&priv->regs->gaddr0, 0);
1036 gfar_write(&priv->regs->gaddr1, 0);
1037 gfar_write(&priv->regs->gaddr2, 0);
1038 gfar_write(&priv->regs->gaddr3, 0);
1039 gfar_write(&priv->regs->gaddr4, 0);
1040 gfar_write(&priv->regs->gaddr5, 0);
1041 gfar_write(&priv->regs->gaddr6, 0);
1042 gfar_write(&priv->regs->gaddr7, 0);
1043
1da177e4 1044 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1045 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
cc8c6e37 1046 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1047
1048 /* Mask off the CAM interrupts */
1049 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
1050 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
1051 }
1052
1053 /* Initialize the max receive buffer length */
1054 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1055
1da177e4
LT		 1056 /* Initialize the Minimum Frame Length Register */
1057 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1058}
1059
0bbaf069
KG		 1060
1061/* Halt the receive and transmit queues */
d87eb127 1062static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1063{
1064 struct gfar_private *priv = netdev_priv(dev);
cc8c6e37 1065 struct gfar __iomem *regs = priv->regs;
1da177e4
LT		 1066 u32 tempval;
1067
1da177e4
LT		 1068 /* Mask all interrupts */
1069 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1070
1071 /* Clear all interrupts */
1072 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1073
1074 /* Stop the DMA, and wait for it to stop */
1075 tempval = gfar_read(&priv->regs->dmactrl);
1076 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1077 != (DMACTRL_GRS | DMACTRL_GTS)) {
1078 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1079 gfar_write(&priv->regs->dmactrl, tempval);
1080
1081 while (!(gfar_read(&priv->regs->ievent) &
1082 (IEVENT_GRSC | IEVENT_GTSC)))
1083 cpu_relax();
1084 }
d87eb127 1085}
d87eb127
SW		 1086
1087/* Halt the receive and transmit queues */
1088void gfar_halt(struct net_device *dev)
1089{
1090 struct gfar_private *priv = netdev_priv(dev);
1091 struct gfar __iomem *regs = priv->regs;
1092 u32 tempval;
1da177e4 1093
2a54adc3
SW		 1094 gfar_halt_nodisable(dev);
1095
1da177e4
LT		 1096 /* Disable Rx and Tx */
1097 tempval = gfar_read(&regs->maccfg1);
1098 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1099 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1100}
1101
1102void stop_gfar(struct net_device *dev)
1103{
1104 struct gfar_private *priv = netdev_priv(dev);
a12f801d
SG		 1105 struct gfar_priv_tx_q *tx_queue = NULL;
1106 struct gfar_priv_rx_q *rx_queue = NULL;
0bbaf069
KG		 1107 unsigned long flags;
1108
bb40dcbb
AF		 1109 phy_stop(priv->phydev);
1110
a12f801d
SG		 1111 tx_queue = priv->tx_queue;
1112 rx_queue = priv->rx_queue;
1113
0bbaf069 1114 /* Lock it down */
a12f801d
SG		 1115 spin_lock_irqsave(&tx_queue->txlock, flags);
1116 spin_lock(&rx_queue->rxlock);
0bbaf069 1117
0bbaf069 1118 gfar_halt(dev);
1da177e4 1119
a12f801d
SG		 1120 spin_unlock(&rx_queue->rxlock);
1121 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4
LT		 1122
1123 /* Free the IRQs */
b31a1d8b 1124 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1da177e4
LT		 1125 free_irq(priv->interruptError, dev);
1126 free_irq(priv->interruptTransmit, dev);
1127 free_irq(priv->interruptReceive, dev);
1128 } else {
1577ecef 1129 free_irq(priv->interruptTransmit, dev);
1da177e4
LT		 1130 }
1131
1132 free_skb_resources(priv);
1da177e4
LT		 1133}
1134
1135/* If there are any tx skbs or rx skbs still around, free them.
1136 * Then free tx_skbuff and rx_skbuff */
bb40dcbb 1137static void free_skb_resources(struct gfar_private *priv)
1da177e4 1138{
e69edd21 1139 struct device *dev = &priv->ofdev->dev;
1da177e4
LT		 1140 struct rxbd8 *rxbdp;
1141 struct txbd8 *txbdp;
a12f801d
SG		 1142 struct gfar_priv_tx_q *tx_queue = NULL;
1143 struct gfar_priv_rx_q *rx_queue = NULL;
4669bc90 1144 int i, j;
1da177e4
LT		 1145
1146 /* Go through all the buffer descriptors and free their data buffers */
a12f801d
SG		 1147 tx_queue = priv->tx_queue;
1148 txbdp = tx_queue->tx_bd_base;
1da177e4 1149
a12f801d 1150 if (!tx_queue->tx_skbuff)
e69edd21
AV		 1151 goto skip_tx_skbuff;
1152
a12f801d
SG		 1153 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1154 if (!tx_queue->tx_skbuff[i])
4669bc90 1155 continue;
1da177e4 1156
4826857f 1157 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1158 txbdp->length, DMA_TO_DEVICE);
1159 txbdp->lstatus = 0;
a12f801d 1160 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; j++) {
4669bc90 1161 txbdp++;
4826857f 1162 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1163 txbdp->length, DMA_TO_DEVICE);
1da177e4 1164 }
ad5da7ab 1165 txbdp++;
a12f801d
SG		 1166 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1167 tx_queue->tx_skbuff[i] = NULL;
1da177e4
LT		 1168 }
1169
a12f801d 1170 kfree(tx_queue->tx_skbuff);
e69edd21 1171skip_tx_skbuff:
1da177e4 1172
a12f801d
SG		 1173 rx_queue = priv->rx_queue;
1174 rxbdp = rx_queue->rx_bd_base;
1da177e4 1175
a12f801d 1176 if (!rx_queue->rx_skbuff)
e69edd21 1177 goto skip_rx_skbuff;
1da177e4 1178
a12f801d
SG		 1179 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1180 if (rx_queue->rx_skbuff[i]) {
e69edd21
AV		 1181 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
1182 priv->rx_buffer_size,
1183 DMA_FROM_DEVICE);
a12f801d
SG		 1184 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1185 rx_queue->rx_skbuff[i] = NULL;
1da177e4
LT		 1186 }
1187
e69edd21
AV		 1188 rxbdp->lstatus = 0;
1189 rxbdp->bufPtr = 0;
1190 rxbdp++;
1da177e4 1191 }
e69edd21 1192
a12f801d 1193 kfree(rx_queue->rx_skbuff);
e69edd21
AV		 1194skip_rx_skbuff:
1195
a12f801d
SG		 1196 dma_free_coherent(dev, sizeof(*txbdp) * tx_queue->tx_ring_size +
1197 sizeof(*rxbdp) * rx_queue->rx_ring_size,
1198 tx_queue->tx_bd_base, tx_queue->tx_bd_dma_base);
1da177e4
LT		 1199}
1200
0bbaf069
KG		 1201void gfar_start(struct net_device *dev)
1202{
1203 struct gfar_private *priv = netdev_priv(dev);
a12f801d
SG		 1204 struct gfar_priv_tx_q *tx_queue;
1205 struct gfar_priv_rx_q *rx_queue;
cc8c6e37 1206 struct gfar __iomem *regs = priv->regs;
0bbaf069
KG		 1207 u32 tempval;
1208
1209 /* Enable Rx and Tx in MACCFG1 */
1210 tempval = gfar_read(&regs->maccfg1);
1211 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1212 gfar_write(&regs->maccfg1, tempval);
1213
1214 /* Initialize DMACTRL to have WWR and WOP */
1215 tempval = gfar_read(&priv->regs->dmactrl);
1216 tempval |= DMACTRL_INIT_SETTINGS;
1217 gfar_write(&priv->regs->dmactrl, tempval);
1218
0bbaf069
KG		 1219 /* Make sure we aren't stopped */
1220 tempval = gfar_read(&priv->regs->dmactrl);
1221 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1222 gfar_write(&priv->regs->dmactrl, tempval);
1223
fef6108d
AF		 1224 /* Clear THLT/RHLT, so that the DMA starts polling now */
1225 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
1226 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
1227
0bbaf069
KG		 1228 /* Unmask the interrupts we look for */
1229 gfar_write(&regs->imask, IMASK_DEFAULT);
12dea57b
DH		 1230
1231 dev->trans_start = jiffies;
0bbaf069
KG		 1232}
1233
1da177e4 1234/* Bring the controller up and running */
ccc05c6e 1235int startup_gfar(struct net_device *ndev)
1da177e4 1236{
ccc05c6e 1237 struct gfar_private *priv = netdev_priv(ndev);
cc8c6e37 1238 struct gfar __iomem *regs = priv->regs;
ccc05c6e 1239 int err;
1da177e4
LT		 1240
1241 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1242
826aa4a0
AV		 1243 err = gfar_alloc_skb_resources(ndev);
1244 if (err)
1245 return err;
815b97c6 1246
826aa4a0 1247 gfar_init_mac(ndev);
1da177e4 1248
1da177e4
LT		 1249 /* If the device has multiple interrupts, register for
1250 * them. Otherwise, only register for the one */
b31a1d8b 1251 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1252 /* Install our interrupt handlers for Error,
1da177e4 1253 * Transmit, and Receive */
ccc05c6e
AV		 1254 err = request_irq(priv->interruptError, gfar_error, 0,
1255 priv->int_name_er, ndev);
1256 if (err) {
0bbaf069 1257 if (netif_msg_intr(priv))
ccc05c6e
AV		 1258 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1259 priv->interruptError);
1da177e4
LT		 1260 goto err_irq_fail;
1261 }
1262
ccc05c6e
AV		 1263 err = request_irq(priv->interruptTransmit, gfar_transmit, 0,
1264 priv->int_name_tx, ndev);
1265 if (err) {
0bbaf069 1266 if (netif_msg_intr(priv))
ccc05c6e
AV		 1267 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1268 priv->interruptTransmit);
1da177e4
LT		 1269 goto tx_irq_fail;
1270 }
1271
ccc05c6e
AV		 1272 err = request_irq(priv->interruptReceive, gfar_receive, 0,
1273 priv->int_name_rx, ndev);
1274 if (err) {
0bbaf069 1275 if (netif_msg_intr(priv))
ccc05c6e
AV		 1276 pr_err("%s: Can't get IRQ %d (receive0)\n",
1277 ndev->name, priv->interruptReceive);
1da177e4
LT		 1278 goto rx_irq_fail;
1279 }
1280 } else {
ccc05c6e
AV		 1281 err = request_irq(priv->interruptTransmit, gfar_interrupt,
1282 0, priv->int_name_tx, ndev);
1283 if (err) {
0bbaf069 1284 if (netif_msg_intr(priv))
ccc05c6e
AV		 1285 pr_err("%s: Can't get IRQ %d\n", ndev->name,
1286 priv->interruptTransmit);
1da177e4
LT		 1287 goto err_irq_fail;
1288 }
1289 }
1290
7f7f5316 1291 /* Start the controller */
ccc05c6e 1292 gfar_start(ndev);
1da177e4 1293
826aa4a0
AV		 1294 phy_start(priv->phydev);
1295
1da177e4
LT		 1296 return 0;
1297
1298rx_irq_fail:
ccc05c6e 1299 free_irq(priv->interruptTransmit, ndev);
1da177e4 1300tx_irq_fail:
ccc05c6e 1301 free_irq(priv->interruptError, ndev);
1da177e4 1302err_irq_fail:
e69edd21 1303 free_skb_resources(priv);
1da177e4
LT		 1304 return err;
1305}
1306
1307/* Called when something needs to use the ethernet device */
1308/* Returns 0 for success. */
1309static int gfar_enet_open(struct net_device *dev)
1310{
94e8cc35 1311 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1312 int err;
1313
a12f801d 1314 napi_enable(&priv->rx_queue->napi);
bea3348e 1315
0fd56bb5
AF		 1316 skb_queue_head_init(&priv->rx_recycle);
1317
1da177e4
LT		 1318 /* Initialize a bunch of registers */
1319 init_registers(dev);
1320
1321 gfar_set_mac_address(dev);
1322
1323 err = init_phy(dev);
1324
a12f801d
SG		 1325 if (err) {
1326 napi_disable(&priv->rx_queue->napi);
1da177e4 1327 return err;
bea3348e 1328 }
1da177e4
LT		 1329
1330 err = startup_gfar(dev);
db0e8e3f 1331 if (err) {
a12f801d 1332 napi_disable(&priv->rx_queue->napi);
db0e8e3f
AV		 1333 return err;
1334 }
1da177e4
LT		 1335
1336 netif_start_queue(dev);
1337
2884e5cc
AV		 1338 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1339
1da177e4
LT		 1340 return err;
1341}
1342
54dc79fe 1343static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1344{
54dc79fe 1345 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1346
1347 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1348
0bbaf069
KG		 1349 return fcb;
1350}
1351
1352static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1353{
7f7f5316 1354 u8 flags = 0;
0bbaf069
KG		 1355
1356 /* If we're here, it's a IP packet with a TCP or UDP
1357 * payload. We set it to checksum, using a pseudo-header
1358 * we provide
1359 */
7f7f5316 1360 flags = TXFCB_DEFAULT;
0bbaf069 1361
7f7f5316
AF		 1362 /* Tell the controller what the protocol is */
1363 /* And provide the already calculated phcs */
eddc9ec5 1364 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1365 flags |= TXFCB_UDP;
4bedb452 1366 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1367 } else
8da32de5 1368 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1369
1370 /* l3os is the distance between the start of the
1371 * frame (skb->data) and the start of the IP hdr.
1372 * l4os is the distance between the start of the
1373 * l3 hdr and the l4 hdr */
bbe735e4 1374 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1375 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1376
7f7f5316 1377 fcb->flags = flags;
0bbaf069
KG		 1378}
1379
7f7f5316 1380void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1381{
7f7f5316 1382 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1383 fcb->vlctl = vlan_tx_tag_get(skb);
1384}
1385
4669bc90
DH		 1386static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1387 struct txbd8 *base, int ring_size)
1388{
1389 struct txbd8 *new_bd = bdp + stride;
1390
1391 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1392}
1393
1394static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1395 int ring_size)
1396{
1397 return skip_txbd(bdp, 1, base, ring_size);
1398}
1399
1da177e4
LT		 1400/* This is called by the kernel when a frame is ready for transmission. */
1401/* It is pointed to by the dev->hard_start_xmit function pointer */
1402static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1403{
1404 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1405 struct gfar_priv_tx_q *tx_queue = NULL;
0bbaf069 1406 struct txfcb *fcb = NULL;
4669bc90 1407 struct txbd8 *txbdp, *txbdp_start, *base;
5a5efed4 1408 u32 lstatus;
4669bc90
DH		 1409 int i;
1410 u32 bufaddr;
fef6108d 1411 unsigned long flags;
4669bc90
DH		 1412 unsigned int nr_frags, length;
1413
a12f801d
SG		 1414 tx_queue = priv->tx_queue;
1415 base = tx_queue->tx_bd_base;
4669bc90 1416
5b28beaf
LY		 1417 /* make space for additional header when fcb is needed */
1418 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1419 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1420 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 1421 struct sk_buff *skb_new;
1422
1423 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1424 if (!skb_new) {
1425 dev->stats.tx_errors++;
bd14ba84 1426 kfree_skb(skb);
54dc79fe
SH		 1427 return NETDEV_TX_OK;
1428 }
1429 kfree_skb(skb);
1430 skb = skb_new;
1431 }
1432
4669bc90
DH		 1433 /* total number of fragments in the SKB */
1434 nr_frags = skb_shinfo(skb)->nr_frags;
1435
a12f801d 1436 spin_lock_irqsave(&tx_queue->txlock, flags);
4669bc90
DH		 1437
1438 /* check if there is space to queue this packet */
a12f801d 1439 if ((nr_frags+1) > tx_queue->num_txbdfree) {
4669bc90
DH		 1440 /* no space, stop the queue */
1441 netif_stop_queue(dev);
1442 dev->stats.tx_fifo_errors++;
a12f801d 1443 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90
DH		 1444 return NETDEV_TX_BUSY;
1445 }
1da177e4
LT		 1446
1447 /* Update transmit stats */
09f75cd7 1448 dev->stats.tx_bytes += skb->len;
1da177e4 1449
a12f801d 1450 txbdp = txbdp_start = tx_queue->cur_tx;
1da177e4 1451
4669bc90
DH		 1452 if (nr_frags == 0) {
1453 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1454 } else {
1455 /* Place the fragment addresses and lengths into the TxBDs */
1456 for (i = 0; i < nr_frags; i++) {
1457 /* Point at the next BD, wrapping as needed */
a12f801d 1458 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 1459
1460 length = skb_shinfo(skb)->frags[i].size;
1461
1462 lstatus = txbdp->lstatus | length |
1463 BD_LFLAG(TXBD_READY);
1464
1465 /* Handle the last BD specially */
1466 if (i == nr_frags - 1)
1467 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 1468
4826857f 1469 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 1470 skb_shinfo(skb)->frags[i].page,
1471 skb_shinfo(skb)->frags[i].page_offset,
1472 length,
1473 DMA_TO_DEVICE);
1474
1475 /* set the TxBD length and buffer pointer */
1476 txbdp->bufPtr = bufaddr;
1477 txbdp->lstatus = lstatus;
1478 }
1479
1480 lstatus = txbdp_start->lstatus;
1481 }
1da177e4 1482
0bbaf069 1483 /* Set up checksumming */
12dea57b 1484 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 1485 fcb = gfar_add_fcb(skb);
1486 lstatus |= BD_LFLAG(TXBD_TOE);
1487 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 1488 }
1489
77ecaf2d 1490 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 1491 if (unlikely(NULL == fcb)) {
1492 fcb = gfar_add_fcb(skb);
5a5efed4 1493 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 1494 }
54dc79fe
SH		 1495
1496 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 1497 }
1498
4669bc90 1499 /* setup the TxBD length and buffer pointer for the first BD */
a12f801d 1500 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
4826857f 1501 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 1502 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 1503
4669bc90 1504 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1da177e4 1505
4669bc90
DH		 1506 /*
1507 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 1508 * semantics (it requires synchronization between cacheable and
1509 * uncacheable mappings, which eieio doesn't provide and which we
1510 * don't need), thus requiring a more expensive sync instruction. At
1511 * some point, the set of architecture-independent barrier functions
1512 * should be expanded to include weaker barriers.
1513 */
3b6330ce 1514 eieio();
7f7f5316 1515
4669bc90
DH		 1516 txbdp_start->lstatus = lstatus;
1517
1518 /* Update the current skb pointer to the next entry we will use
1519 * (wrapping if necessary) */
a12f801d
SG		 1520 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1521 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 1522
a12f801d 1523 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 1524
1525 /* reduce TxBD free count */
a12f801d 1526 tx_queue->num_txbdfree -= (nr_frags + 1);
4669bc90
DH		 1527
1528 dev->trans_start = jiffies;
1da177e4
LT		 1529
1530 /* If the next BD still needs to be cleaned up, then the bds
1531 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 1532 if (!tx_queue->num_txbdfree) {
1da177e4
LT		 1533 netif_stop_queue(dev);
1534
09f75cd7 1535 dev->stats.tx_fifo_errors++;
1da177e4
LT		 1536 }
1537
1da177e4
LT		 1538 /* Tell the DMA to go go go */
1539 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1540
1541 /* Unlock priv */
a12f801d 1542 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 1543
54dc79fe 1544 return NETDEV_TX_OK;
1da177e4
LT		 1545}
1546
1547/* Stops the kernel queue, and halts the controller */
1548static int gfar_close(struct net_device *dev)
1549{
1550 struct gfar_private *priv = netdev_priv(dev);
bea3348e 1551
a12f801d 1552 napi_disable(&priv->rx_queue->napi);
bea3348e 1553
0fd56bb5 1554 skb_queue_purge(&priv->rx_recycle);
ab939905 1555 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 1556 stop_gfar(dev);
1557
bb40dcbb
AF		 1558 /* Disconnect from the PHY */
1559 phy_disconnect(priv->phydev);
1560 priv->phydev = NULL;
1da177e4
LT		 1561
1562 netif_stop_queue(dev);
1563
1564 return 0;
1565}
1566
1da177e4 1567/* Changes the mac address if the controller is not running. */
f162b9d5 1568static int gfar_set_mac_address(struct net_device *dev)
1da177e4 1569{
7f7f5316 1570 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 1571
1572 return 0;
1573}
1574
1575
0bbaf069
KG		 1576/* Enables and disables VLAN insertion/extraction */
1577static void gfar_vlan_rx_register(struct net_device *dev,
1578 struct vlan_group *grp)
1579{
1580 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1581 struct gfar_priv_rx_q *rx_queue = NULL;
0bbaf069
KG		 1582 unsigned long flags;
1583 u32 tempval;
1584
a12f801d
SG		 1585 rx_queue = priv->rx_queue;
1586 spin_lock_irqsave(&rx_queue->rxlock, flags);
0bbaf069 1587
cd1f55a5 1588 priv->vlgrp = grp;
0bbaf069
KG		 1589
1590 if (grp) {
1591 /* Enable VLAN tag insertion */
1592 tempval = gfar_read(&priv->regs->tctrl);
1593 tempval |= TCTRL_VLINS;
1594
1595 gfar_write(&priv->regs->tctrl, tempval);
6aa20a22 1596
0bbaf069
KG		 1597 /* Enable VLAN tag extraction */
1598 tempval = gfar_read(&priv->regs->rctrl);
77ecaf2d 1599 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
0bbaf069
KG		 1600 gfar_write(&priv->regs->rctrl, tempval);
1601 } else {
1602 /* Disable VLAN tag insertion */
1603 tempval = gfar_read(&priv->regs->tctrl);
1604 tempval &= ~TCTRL_VLINS;
1605 gfar_write(&priv->regs->tctrl, tempval);
1606
1607 /* Disable VLAN tag extraction */
1608 tempval = gfar_read(&priv->regs->rctrl);
1609 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 1610 /* If parse is no longer required, then disable parser */
1611 if (tempval & RCTRL_REQ_PARSER)
1612 tempval |= RCTRL_PRSDEP_INIT;
1613 else
1614 tempval &= ~RCTRL_PRSDEP_INIT;
0bbaf069
KG		 1615 gfar_write(&priv->regs->rctrl, tempval);
1616 }
1617
77ecaf2d
DH		 1618 gfar_change_mtu(dev, dev->mtu);
1619
a12f801d 1620 spin_unlock_irqrestore(&rx_queue->rxlock, flags);
0bbaf069
KG		 1621}
1622
1da177e4
LT		 1623static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1624{
1625 int tempsize, tempval;
1626 struct gfar_private *priv = netdev_priv(dev);
1627 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 1628 int frame_size = new_mtu + ETH_HLEN;
1629
77ecaf2d 1630 if (priv->vlgrp)
faa89577 1631 frame_size += VLAN_HLEN;
0bbaf069 1632
1da177e4 1633 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 1634 if (netif_msg_drv(priv))
1635 printk(KERN_ERR "%s: Invalid MTU setting\n",
1636 dev->name);
1da177e4
LT		 1637 return -EINVAL;
1638 }
1639
77ecaf2d
DH		 1640 if (gfar_uses_fcb(priv))
1641 frame_size += GMAC_FCB_LEN;
1642
1643 frame_size += priv->padding;
1644
1da177e4
LT		 1645 tempsize =
1646 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1647 INCREMENTAL_BUFFER_SIZE;
1648
1649 /* Only stop and start the controller if it isn't already
7f7f5316 1650 * stopped, and we changed something */
1da177e4
LT		 1651 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1652 stop_gfar(dev);
1653
1654 priv->rx_buffer_size = tempsize;
1655
1656 dev->mtu = new_mtu;
1657
1658 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1659 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1660
1661 /* If the mtu is larger than the max size for standard
1662 * ethernet frames (ie, a jumbo frame), then set maccfg2
1663 * to allow huge frames, and to check the length */
1664 tempval = gfar_read(&priv->regs->maccfg2);
1665
1666 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1667 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1668 else
1669 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1670
1671 gfar_write(&priv->regs->maccfg2, tempval);
1672
1673 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1674 startup_gfar(dev);
1675
1676 return 0;
1677}
1678
ab939905 1679/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 1680 * transmitted after a set amount of time.
1681 * For now, assume that clearing out all the structures, and
ab939905
SS		 1682 * starting over will fix the problem.
1683 */
1684static void gfar_reset_task(struct work_struct *work)
1da177e4 1685{
ab939905
SS		 1686 struct gfar_private *priv = container_of(work, struct gfar_private,
1687 reset_task);
4826857f 1688 struct net_device *dev = priv->ndev;
1da177e4
LT		 1689
1690 if (dev->flags & IFF_UP) {
cbea2707 1691 netif_stop_queue(dev);
1da177e4
LT		 1692 stop_gfar(dev);
1693 startup_gfar(dev);
cbea2707 1694 netif_start_queue(dev);
1da177e4
LT		 1695 }
1696
263ba320 1697 netif_tx_schedule_all(dev);
1da177e4
LT		 1698}
1699
ab939905
SS		 1700static void gfar_timeout(struct net_device *dev)
1701{
1702 struct gfar_private *priv = netdev_priv(dev);
1703
1704 dev->stats.tx_errors++;
1705 schedule_work(&priv->reset_task);
1706}
1707
1da177e4 1708/* Interrupt Handler for Transmit complete */
a12f801d 1709static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 1710{
a12f801d 1711 struct net_device *dev = tx_queue->dev;
d080cd63 1712 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1713 struct gfar_priv_rx_q *rx_queue = NULL;
4669bc90
DH		 1714 struct txbd8 *bdp;
1715 struct txbd8 *lbdp = NULL;
a12f801d 1716 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 1717 struct sk_buff *skb;
1718 int skb_dirtytx;
a12f801d 1719 int tx_ring_size = tx_queue->tx_ring_size;
4669bc90
DH		 1720 int frags = 0;
1721 int i;
d080cd63 1722 int howmany = 0;
4669bc90 1723 u32 lstatus;
1da177e4 1724
a12f801d
SG		 1725 rx_queue = priv->rx_queue;
1726 bdp = tx_queue->dirty_tx;
1727 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 1728
a12f801d 1729 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
4669bc90
DH		 1730 frags = skb_shinfo(skb)->nr_frags;
1731 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1da177e4 1732
4669bc90 1733 lstatus = lbdp->lstatus;
1da177e4 1734
4669bc90
DH		 1735 /* Only clean completed frames */
1736 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1737 (lstatus & BD_LENGTH_MASK))
1738 break;
1739
4826857f 1740 dma_unmap_single(&priv->ofdev->dev,
4669bc90
DH		 1741 bdp->bufPtr,
1742 bdp->length,
1743 DMA_TO_DEVICE);
81183059 1744
4669bc90
DH		 1745 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1746 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 1747
4669bc90 1748 for (i = 0; i < frags; i++) {
4826857f 1749 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 1750 bdp->bufPtr,
1751 bdp->length,
1752 DMA_TO_DEVICE);
1753 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1754 bdp = next_txbd(bdp, base, tx_ring_size);
1755 }
1da177e4 1756
0fd56bb5
AF		 1757 /*
1758 * If there's room in the queue (limit it to rx_buffer_size)
1759 * we add this skb back into the pool, if it's the right size
1760 */
a12f801d 1761 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 1762 skb_recycle_check(skb, priv->rx_buffer_size +
1763 RXBUF_ALIGNMENT))
1764 __skb_queue_head(&priv->rx_recycle, skb);
1765 else
1766 dev_kfree_skb_any(skb);
1767
a12f801d 1768 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 1769
4669bc90
DH		 1770 skb_dirtytx = (skb_dirtytx + 1) &
1771 TX_RING_MOD_MASK(tx_ring_size);
1772
1773 howmany++;
a12f801d 1774 tx_queue->num_txbdfree += frags + 1;
4669bc90 1775 }
1da177e4 1776
4669bc90 1777 /* If we freed a buffer, we can restart transmission, if necessary */
a12f801d 1778 if (netif_queue_stopped(dev) && tx_queue->num_txbdfree)
4669bc90 1779 netif_wake_queue(dev);
1da177e4 1780
4669bc90 1781 /* Update dirty indicators */
a12f801d
SG		 1782 tx_queue->skb_dirtytx = skb_dirtytx;
1783 tx_queue->dirty_tx = bdp;
1da177e4 1784
d080cd63
DH		 1785 dev->stats.tx_packets += howmany;
1786
1787 return howmany;
1788}
1789
8c7396ae 1790static void gfar_schedule_cleanup(struct net_device *dev)
d080cd63 1791{
d080cd63 1792 struct gfar_private *priv = netdev_priv(dev);
a12f801d
SG		 1793 struct gfar_priv_tx_q *tx_queue = NULL;
1794 struct gfar_priv_rx_q *rx_queue = NULL;
a6d0b91a
AV		 1795 unsigned long flags;
1796
a12f801d
SG		 1797 rx_queue = priv->rx_queue;
1798 tx_queue = priv->tx_queue;
1799 spin_lock_irqsave(&tx_queue->txlock, flags);
1800 spin_lock(&rx_queue->rxlock);
a6d0b91a 1801
a12f801d 1802 if (napi_schedule_prep(&rx_queue->napi)) {
8c7396ae 1803 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
a12f801d 1804 __napi_schedule(&rx_queue->napi);
8707bdd4
JP		 1805 } else {
1806 /*
1807 * Clear IEVENT, so interrupts aren't called again
1808 * because of the packets that have already arrived.
1809 */
1810 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
2f448911 1811 }
a6d0b91a 1812
a12f801d
SG		 1813 spin_unlock(&rx_queue->rxlock);
1814 spin_unlock_irqrestore(&tx_queue->txlock, flags);
8c7396ae 1815}
1da177e4 1816
8c7396ae
DH		 1817/* Interrupt Handler for Transmit complete */
1818static irqreturn_t gfar_transmit(int irq, void *dev_id)
1819{
1820 gfar_schedule_cleanup((struct net_device *)dev_id);
1da177e4
LT		 1821 return IRQ_HANDLED;
1822}
1823
a12f801d 1824static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 1825 struct sk_buff *skb)
1826{
a12f801d 1827 struct net_device *dev = rx_queue->dev;
815b97c6 1828 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 1829 dma_addr_t buf;
815b97c6 1830
8a102fe0
AV		 1831 buf = dma_map_single(&priv->ofdev->dev, skb->data,
1832 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 1833 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 1834}
1835
1836
1837struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 1838{
7f7f5316 1839 unsigned int alignamount;
1da177e4
LT		 1840 struct gfar_private *priv = netdev_priv(dev);
1841 struct sk_buff *skb = NULL;
1da177e4 1842
0fd56bb5
AF		 1843 skb = __skb_dequeue(&priv->rx_recycle);
1844 if (!skb)
1845 skb = netdev_alloc_skb(dev,
1846 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 1847
815b97c6 1848 if (!skb)
1da177e4
LT		 1849 return NULL;
1850
7f7f5316 1851 alignamount = RXBUF_ALIGNMENT -
bea3348e 1852 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 1853
1da177e4
LT		 1854 /* We need the data buffer to be aligned properly. We will reserve
1855 * as many bytes as needed to align the data properly
1856 */
7f7f5316 1857 skb_reserve(skb, alignamount);
1da177e4 1858
1da177e4
LT		 1859 return skb;
1860}
1861
298e1a9e 1862static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 1863{
298e1a9e 1864 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 1865 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 1866 struct gfar_extra_stats *estats = &priv->extra_stats;
1867
1868 /* If the packet was truncated, none of the other errors
1869 * matter */
1870 if (status & RXBD_TRUNCATED) {
1871 stats->rx_length_errors++;
1872
1873 estats->rx_trunc++;
1874
1875 return;
1876 }
1877 /* Count the errors, if there were any */
1878 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1879 stats->rx_length_errors++;
1880
1881 if (status & RXBD_LARGE)
1882 estats->rx_large++;
1883 else
1884 estats->rx_short++;
1885 }
1886 if (status & RXBD_NONOCTET) {
1887 stats->rx_frame_errors++;
1888 estats->rx_nonoctet++;
1889 }
1890 if (status & RXBD_CRCERR) {
1891 estats->rx_crcerr++;
1892 stats->rx_crc_errors++;
1893 }
1894 if (status & RXBD_OVERRUN) {
1895 estats->rx_overrun++;
1896 stats->rx_crc_errors++;
1897 }
1898}
1899
7d12e780 1900irqreturn_t gfar_receive(int irq, void *dev_id)
1da177e4 1901{
8c7396ae 1902 gfar_schedule_cleanup((struct net_device *)dev_id);
1da177e4
LT		 1903 return IRQ_HANDLED;
1904}
1905
0bbaf069
KG		 1906static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1907{
1908 /* If valid headers were found, and valid sums
1909 * were verified, then we tell the kernel that no
1910 * checksumming is necessary. Otherwise, it is */
7f7f5316 1911 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 1912 skb->ip_summed = CHECKSUM_UNNECESSARY;
1913 else
1914 skb->ip_summed = CHECKSUM_NONE;
1915}
1916
1917
1da177e4
LT		 1918/* gfar_process_frame() -- handle one incoming packet if skb
1919 * isn't NULL. */
1920static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 1921 int amount_pull)
1da177e4
LT		 1922{
1923 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1924 struct rxfcb *fcb = NULL;
1da177e4 1925
2c2db48a 1926 int ret;
1da177e4 1927
2c2db48a
DH		 1928 /* fcb is at the beginning if exists */
1929 fcb = (struct rxfcb *)skb->data;
0bbaf069 1930
2c2db48a
DH		 1931 /* Remove the FCB from the skb */
1932 /* Remove the padded bytes, if there are any */
1933 if (amount_pull)
1934 skb_pull(skb, amount_pull);
0bbaf069 1935
2c2db48a
DH		 1936 if (priv->rx_csum_enable)
1937 gfar_rx_checksum(skb, fcb);
0bbaf069 1938
2c2db48a
DH		 1939 /* Tell the skb what kind of packet this is */
1940 skb->protocol = eth_type_trans(skb, dev);
1da177e4 1941
2c2db48a
DH		 1942 /* Send the packet up the stack */
1943 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1944 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1945 else
1946 ret = netif_receive_skb(skb);
0bbaf069 1947
2c2db48a
DH		 1948 if (NET_RX_DROP == ret)
1949 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 1950
1951 return 0;
1952}
1953
1954/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 1955 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 1956 * of frames handled
1957 */
a12f801d 1958int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 1959{
a12f801d 1960 struct net_device *dev = rx_queue->dev;
31de198b 1961 struct rxbd8 *bdp, *base;
1da177e4 1962 struct sk_buff *skb;
2c2db48a
DH		 1963 int pkt_len;
1964 int amount_pull;
1da177e4
LT		 1965 int howmany = 0;
1966 struct gfar_private *priv = netdev_priv(dev);
1967
1968 /* Get the first full descriptor */
a12f801d
SG		 1969 bdp = rx_queue->cur_rx;
1970 base = rx_queue->rx_bd_base;
1da177e4 1971
2c2db48a
DH		 1972 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1973 priv->padding;
1974
1da177e4 1975 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 1976 struct sk_buff *newskb;
3b6330ce 1977 rmb();
815b97c6
AF		 1978
1979 /* Add another skb for the future */
1980 newskb = gfar_new_skb(dev);
1981
a12f801d 1982 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 1983
4826857f 1984 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 1985 priv->rx_buffer_size, DMA_FROM_DEVICE);
1986
815b97c6
AF		 1987 /* We drop the frame if we failed to allocate a new buffer */
1988 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1989 bdp->status & RXBD_ERR)) {
1990 count_errors(bdp->status, dev);
1991
1992 if (unlikely(!newskb))
1993 newskb = skb;
4e2fd555
LB		 1994 else if (skb) {
1995 /*
1996 * We need to reset ->data to what it
1997 * was before gfar_new_skb() re-aligned
1998 * it to an RXBUF_ALIGNMENT boundary
1999 * before we put the skb back on the
2000 * recycle list.
2001 */
2002 skb->data = skb->head + NET_SKB_PAD;
0fd56bb5 2003 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2004 }
815b97c6 2005 } else {
1da177e4 2006 /* Increment the number of packets */
09f75cd7 2007 dev->stats.rx_packets++;
1da177e4
LT		 2008 howmany++;
2009
2c2db48a
DH		 2010 if (likely(skb)) {
2011 pkt_len = bdp->length - ETH_FCS_LEN;
2012 /* Remove the FCS from the packet length */
2013 skb_put(skb, pkt_len);
2014 dev->stats.rx_bytes += pkt_len;
1da177e4 2015
1577ecef
AF		 2016 if (in_irq() || irqs_disabled())
2017 printk("Interrupt problem!\n");
2c2db48a
DH		 2018 gfar_process_frame(dev, skb, amount_pull);
2019
2020 } else {
2021 if (netif_msg_rx_err(priv))
2022 printk(KERN_WARNING
2023 "%s: Missing skb!\n", dev->name);
2024 dev->stats.rx_dropped++;
2025 priv->extra_stats.rx_skbmissing++;
2026 }
1da177e4 2027
1da177e4
LT		 2028 }
2029
a12f801d 2030 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2031
815b97c6 2032 /* Setup the new bdp */
a12f801d 2033 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2034
2035 /* Update to the next pointer */
a12f801d 2036 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2037
2038 /* update to point at the next skb */
a12f801d
SG		 2039 rx_queue->skb_currx =
2040 (rx_queue->skb_currx + 1) &
2041 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2042 }
2043
2044 /* Update the current rxbd pointer to be the next one */
a12f801d 2045 rx_queue->cur_rx = bdp;
1da177e4 2046
1da177e4
LT		 2047 return howmany;
2048}
2049
bea3348e 2050static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2051{
a12f801d
SG		 2052 struct gfar_priv_rx_q *rx_queue = container_of(napi,
2053 struct gfar_priv_rx_q, napi);
2054 struct net_device *dev = rx_queue->dev;
2055 struct gfar_private *priv = netdev_priv(dev);
2056 struct gfar_priv_tx_q *tx_queue = NULL;
42199884
AF		 2057 int tx_cleaned = 0;
2058 int rx_cleaned = 0;
d080cd63
DH		 2059 unsigned long flags;
2060
8c7396ae
DH		 2061 /* Clear IEVENT, so interrupts aren't called again
2062 * because of the packets that have already arrived */
2063 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
a12f801d 2064 tx_queue = priv->tx_queue;
8c7396ae 2065
d080cd63 2066 /* If we fail to get the lock, don't bother with the TX BDs */
a12f801d
SG		 2067 if (spin_trylock_irqsave(&tx_queue->txlock, flags)) {
2068 tx_cleaned = gfar_clean_tx_ring(tx_queue);
2069 spin_unlock_irqrestore(&tx_queue->txlock, flags);
d080cd63 2070 }
1da177e4 2071
a12f801d 2072 rx_cleaned = gfar_clean_rx_ring(rx_queue, budget);
1da177e4 2073
42199884
AF		 2074 if (tx_cleaned)
2075 return budget;
2076
2077 if (rx_cleaned < budget) {
288379f0 2078 napi_complete(napi);
1da177e4
LT		 2079
2080 /* Clear the halt bit in RSTAT */
2081 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
2082
2083 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
2084
2085 /* If we are coalescing interrupts, update the timer */
2086 /* Otherwise, clear it */
a12f801d 2087 if (likely(rx_queue->rxcoalescing)) {
2f448911 2088 gfar_write(&priv->regs->rxic, 0);
a12f801d 2089 gfar_write(&priv->regs->rxic, rx_queue->rxic);
2f448911 2090 }
a12f801d 2091 if (likely(tx_queue->txcoalescing)) {
8c7396ae 2092 gfar_write(&priv->regs->txic, 0);
a12f801d 2093 gfar_write(&priv->regs->txic, tx_queue->txic);
8c7396ae 2094 }
1da177e4
LT		 2095 }
2096
42199884 2097 return rx_cleaned;
1da177e4 2098}
1da177e4 2099
f2d71c2d
VW		 2100#ifdef CONFIG_NET_POLL_CONTROLLER
2101/*
2102 * Polling 'interrupt' - used by things like netconsole to send skbs
2103 * without having to re-enable interrupts. It's not called while
2104 * the interrupt routine is executing.
2105 */
2106static void gfar_netpoll(struct net_device *dev)
2107{
2108 struct gfar_private *priv = netdev_priv(dev);
2109
2110 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2111 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
f2d71c2d
VW		 2112 disable_irq(priv->interruptTransmit);
2113 disable_irq(priv->interruptReceive);
2114 disable_irq(priv->interruptError);
2115 gfar_interrupt(priv->interruptTransmit, dev);
2116 enable_irq(priv->interruptError);
2117 enable_irq(priv->interruptReceive);
2118 enable_irq(priv->interruptTransmit);
2119 } else {
2120 disable_irq(priv->interruptTransmit);
2121 gfar_interrupt(priv->interruptTransmit, dev);
2122 enable_irq(priv->interruptTransmit);
2123 }
2124}
2125#endif
2126
1da177e4 2127/* The interrupt handler for devices with one interrupt */
7d12e780 2128static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1da177e4
LT		 2129{
2130 struct net_device *dev = dev_id;
2131 struct gfar_private *priv = netdev_priv(dev);
2132
2133 /* Save ievent for future reference */
2134 u32 events = gfar_read(&priv->regs->ievent);
2135
1da177e4 2136 /* Check for reception */
538cc7ee 2137 if (events & IEVENT_RX_MASK)
7d12e780 2138 gfar_receive(irq, dev_id);
1da177e4
LT		 2139
2140 /* Check for transmit completion */
538cc7ee 2141 if (events & IEVENT_TX_MASK)
7d12e780 2142 gfar_transmit(irq, dev_id);
1da177e4 2143
538cc7ee
SS		 2144 /* Check for errors */
2145 if (events & IEVENT_ERR_MASK)
2146 gfar_error(irq, dev_id);
1da177e4
LT		 2147
2148 return IRQ_HANDLED;
2149}
2150
1da177e4
LT		 2151/* Called every time the controller might need to be made
2152 * aware of new link state. The PHY code conveys this
bb40dcbb 2153 * information through variables in the phydev structure, and this
1da177e4
LT		 2154 * function converts those variables into the appropriate
2155 * register values, and can bring down the device if needed.
2156 */
2157static void adjust_link(struct net_device *dev)
2158{
2159 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2160 struct gfar_priv_tx_q *tx_queue = NULL;
cc8c6e37 2161 struct gfar __iomem *regs = priv->regs;
bb40dcbb
AF		 2162 unsigned long flags;
2163 struct phy_device *phydev = priv->phydev;
2164 int new_state = 0;
2165
a12f801d
SG		 2166 tx_queue = priv->tx_queue;
2167 spin_lock_irqsave(&tx_queue->txlock, flags);
bb40dcbb
AF		 2168 if (phydev->link) {
2169 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2170 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2171
1da177e4
LT		 2172 /* Now we make sure that we can be in full duplex mode.
2173 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2174 if (phydev->duplex != priv->oldduplex) {
2175 new_state = 1;
2176 if (!(phydev->duplex))
1da177e4 2177 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2178 else
1da177e4 2179 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2180
bb40dcbb 2181 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2182 }
2183
bb40dcbb
AF		 2184 if (phydev->speed != priv->oldspeed) {
2185 new_state = 1;
2186 switch (phydev->speed) {
1da177e4 2187 case 1000:
1da177e4
LT		 2188 tempval =
2189 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2190
2191 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2192 break;
2193 case 100:
2194 case 10:
1da177e4
LT		 2195 tempval =
2196 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2197
2198 /* Reduced mode distinguishes
2199 * between 10 and 100 */
2200 if (phydev->speed == SPEED_100)
2201 ecntrl |= ECNTRL_R100;
2202 else
2203 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2204 break;
2205 default:
0bbaf069
KG		 2206 if (netif_msg_link(priv))
2207 printk(KERN_WARNING
bb40dcbb
AF		 2208 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2209 dev->name, phydev->speed);
1da177e4
LT		 2210 break;
2211 }
2212
bb40dcbb 2213 priv->oldspeed = phydev->speed;
1da177e4
LT		 2214 }
2215
bb40dcbb 2216 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2217 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2218
1da177e4 2219 if (!priv->oldlink) {
bb40dcbb 2220 new_state = 1;
1da177e4 2221 priv->oldlink = 1;
1da177e4 2222 }
bb40dcbb
AF		 2223 } else if (priv->oldlink) {
2224 new_state = 1;
2225 priv->oldlink = 0;
2226 priv->oldspeed = 0;
2227 priv->oldduplex = -1;
1da177e4 2228 }
1da177e4 2229
bb40dcbb
AF		 2230 if (new_state && netif_msg_link(priv))
2231 phy_print_status(phydev);
2232
a12f801d 2233 spin_unlock_irqrestore(&tx_queue->txlock, flags);
bb40dcbb 2234}
1da177e4
LT		 2235
2236/* Update the hash table based on the current list of multicast
2237 * addresses we subscribe to. Also, change the promiscuity of
2238 * the device based on the flags (this function is called
2239 * whenever dev->flags is changed */
2240static void gfar_set_multi(struct net_device *dev)
2241{
2242 struct dev_mc_list *mc_ptr;
2243 struct gfar_private *priv = netdev_priv(dev);
cc8c6e37 2244 struct gfar __iomem *regs = priv->regs;
1da177e4
LT		 2245 u32 tempval;
2246
a12f801d 2247 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2248 /* Set RCTRL to PROM */
2249 tempval = gfar_read(&regs->rctrl);
2250 tempval |= RCTRL_PROM;
2251 gfar_write(&regs->rctrl, tempval);
2252 } else {
2253 /* Set RCTRL to not PROM */
2254 tempval = gfar_read(&regs->rctrl);
2255 tempval &= ~(RCTRL_PROM);
2256 gfar_write(&regs->rctrl, tempval);
2257 }
6aa20a22 2258
a12f801d 2259 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2260 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2261 gfar_write(&regs->igaddr0, 0xffffffff);
2262 gfar_write(&regs->igaddr1, 0xffffffff);
2263 gfar_write(&regs->igaddr2, 0xffffffff);
2264 gfar_write(&regs->igaddr3, 0xffffffff);
2265 gfar_write(&regs->igaddr4, 0xffffffff);
2266 gfar_write(&regs->igaddr5, 0xffffffff);
2267 gfar_write(&regs->igaddr6, 0xffffffff);
2268 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2269 gfar_write(&regs->gaddr0, 0xffffffff);
2270 gfar_write(&regs->gaddr1, 0xffffffff);
2271 gfar_write(&regs->gaddr2, 0xffffffff);
2272 gfar_write(&regs->gaddr3, 0xffffffff);
2273 gfar_write(&regs->gaddr4, 0xffffffff);
2274 gfar_write(&regs->gaddr5, 0xffffffff);
2275 gfar_write(&regs->gaddr6, 0xffffffff);
2276 gfar_write(&regs->gaddr7, 0xffffffff);
2277 } else {
7f7f5316
AF		 2278 int em_num;
2279 int idx;
2280
1da177e4 2281 /* zero out the hash */
0bbaf069
KG		 2282 gfar_write(&regs->igaddr0, 0x0);
2283 gfar_write(&regs->igaddr1, 0x0);
2284 gfar_write(&regs->igaddr2, 0x0);
2285 gfar_write(&regs->igaddr3, 0x0);
2286 gfar_write(&regs->igaddr4, 0x0);
2287 gfar_write(&regs->igaddr5, 0x0);
2288 gfar_write(&regs->igaddr6, 0x0);
2289 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2290 gfar_write(&regs->gaddr0, 0x0);
2291 gfar_write(&regs->gaddr1, 0x0);
2292 gfar_write(&regs->gaddr2, 0x0);
2293 gfar_write(&regs->gaddr3, 0x0);
2294 gfar_write(&regs->gaddr4, 0x0);
2295 gfar_write(&regs->gaddr5, 0x0);
2296 gfar_write(&regs->gaddr6, 0x0);
2297 gfar_write(&regs->gaddr7, 0x0);
2298
7f7f5316
AF		 2299 /* If we have extended hash tables, we need to
2300 * clear the exact match registers to prepare for
2301 * setting them */
2302 if (priv->extended_hash) {
2303 em_num = GFAR_EM_NUM + 1;
2304 gfar_clear_exact_match(dev);
2305 idx = 1;
2306 } else {
2307 idx = 0;
2308 em_num = 0;
2309 }
2310
a12f801d 2311 if (dev->mc_count == 0)
1da177e4
LT		 2312 return;
2313
2314 /* Parse the list, and set the appropriate bits */
2315 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
7f7f5316
AF		 2316 if (idx < em_num) {
2317 gfar_set_mac_for_addr(dev, idx,
2318 mc_ptr->dmi_addr);
2319 idx++;
2320 } else
2321 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1da177e4
LT		 2322 }
2323 }
2324
2325 return;
2326}
2327
7f7f5316
AF		 2328
2329/* Clears each of the exact match registers to zero, so they
2330 * don't interfere with normal reception */
2331static void gfar_clear_exact_match(struct net_device *dev)
2332{
2333 int idx;
2334 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2335
2336 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2337 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2338}
2339
1da177e4
LT		 2340/* Set the appropriate hash bit for the given addr */
2341/* The algorithm works like so:
2342 * 1) Take the Destination Address (ie the multicast address), and
2343 * do a CRC on it (little endian), and reverse the bits of the
2344 * result.
2345 * 2) Use the 8 most significant bits as a hash into a 256-entry
2346 * table. The table is controlled through 8 32-bit registers:
2347 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2348 * gaddr7. This means that the 3 most significant bits in the
2349 * hash index which gaddr register to use, and the 5 other bits
2350 * indicate which bit (assuming an IBM numbering scheme, which
2351 * for PowerPC (tm) is usually the case) in the register holds
2352 * the entry. */
2353static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2354{
2355 u32 tempval;
2356 struct gfar_private *priv = netdev_priv(dev);
1da177e4 2357 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 2358 int width = priv->hash_width;
2359 u8 whichbit = (result >> (32 - width)) & 0x1f;
2360 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 2361 u32 value = (1 << (31-whichbit));
2362
0bbaf069 2363 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 2364 tempval |= value;
0bbaf069 2365 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 2366
2367 return;
2368}
2369
7f7f5316
AF		 2370
2371/* There are multiple MAC Address register pairs on some controllers
2372 * This function sets the numth pair to a given address
2373 */
2374static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2375{
2376 struct gfar_private *priv = netdev_priv(dev);
2377 int idx;
2378 char tmpbuf[MAC_ADDR_LEN];
2379 u32 tempval;
cc8c6e37 2380 u32 __iomem *macptr = &priv->regs->macstnaddr1;
7f7f5316
AF		 2381
2382 macptr += num*2;
2383
2384 /* Now copy it into the mac registers backwards, cuz */
2385 /* little endian is silly */
2386 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2387 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2388
2389 gfar_write(macptr, *((u32 *) (tmpbuf)));
2390
2391 tempval = *((u32 *) (tmpbuf + 4));
2392
2393 gfar_write(macptr+1, tempval);
2394}
2395
1da177e4 2396/* GFAR error interrupt handler */
7d12e780 2397static irqreturn_t gfar_error(int irq, void *dev_id)
1da177e4
LT		 2398{
2399 struct net_device *dev = dev_id;
2400 struct gfar_private *priv = netdev_priv(dev);
2401
2402 /* Save ievent for future reference */
2403 u32 events = gfar_read(&priv->regs->ievent);
2404
2405 /* Clear IEVENT */
d87eb127
SW		 2406 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2407
2408 /* Magic Packet is not an error. */
b31a1d8b 2409 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 2410 (events & IEVENT_MAG))
2411 events &= ~IEVENT_MAG;
1da177e4
LT		 2412
2413 /* Hmm... */
0bbaf069
KG		 2414 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2415 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
538cc7ee 2416 dev->name, events, gfar_read(&priv->regs->imask));
1da177e4
LT		 2417
2418 /* Update the error counters */
2419 if (events & IEVENT_TXE) {
09f75cd7 2420 dev->stats.tx_errors++;
1da177e4
LT		 2421
2422 if (events & IEVENT_LC)
09f75cd7 2423 dev->stats.tx_window_errors++;
1da177e4 2424 if (events & IEVENT_CRL)
09f75cd7 2425 dev->stats.tx_aborted_errors++;
1da177e4 2426 if (events & IEVENT_XFUN) {
0bbaf069 2427 if (netif_msg_tx_err(priv))
538cc7ee
SS		 2428 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2429 "packet dropped.\n", dev->name);
09f75cd7 2430 dev->stats.tx_dropped++;
1da177e4
LT		 2431 priv->extra_stats.tx_underrun++;
2432
2433 /* Reactivate the Tx Queues */
2434 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2435 }
0bbaf069
KG		 2436 if (netif_msg_tx_err(priv))
2437 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 2438 }
2439 if (events & IEVENT_BSY) {
09f75cd7 2440 dev->stats.rx_errors++;
1da177e4
LT		 2441 priv->extra_stats.rx_bsy++;
2442
7d12e780 2443 gfar_receive(irq, dev_id);
1da177e4 2444
0bbaf069 2445 if (netif_msg_rx_err(priv))
538cc7ee
SS		 2446 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2447 dev->name, gfar_read(&priv->regs->rstat));
1da177e4
LT		 2448 }
2449 if (events & IEVENT_BABR) {
09f75cd7 2450 dev->stats.rx_errors++;
1da177e4
LT		 2451 priv->extra_stats.rx_babr++;
2452
0bbaf069 2453 if (netif_msg_rx_err(priv))
538cc7ee 2454 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 2455 }
2456 if (events & IEVENT_EBERR) {
2457 priv->extra_stats.eberr++;
0bbaf069 2458 if (netif_msg_rx_err(priv))
538cc7ee 2459 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 2460 }
0bbaf069 2461 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 2462 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 2463
2464 if (events & IEVENT_BABT) {
2465 priv->extra_stats.tx_babt++;
0bbaf069 2466 if (netif_msg_tx_err(priv))
538cc7ee 2467 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 2468 }
2469 return IRQ_HANDLED;
2470}
2471
b31a1d8b
AF		 2472static struct of_device_id gfar_match[] =
2473{
2474 {
2475 .type = "network",
2476 .compatible = "gianfar",
2477 },
2478 {},
2479};
e72701ac 2480MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 2481
1da177e4 2482/* Structure for a device driver */
b31a1d8b
AF		 2483static struct of_platform_driver gfar_driver = {
2484 .name = "fsl-gianfar",
2485 .match_table = gfar_match,
2486
1da177e4
LT		 2487 .probe = gfar_probe,
2488 .remove = gfar_remove,
be926fc4
AV		 2489 .suspend = gfar_legacy_suspend,
2490 .resume = gfar_legacy_resume,
2491 .driver.pm = GFAR_PM_OPS,
1da177e4
LT		 2492};
2493
2494static int __init gfar_init(void)
2495{
1577ecef 2496 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 2497}
2498
2499static void __exit gfar_exit(void)
2500{
b31a1d8b 2501 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 2502}
2503
2504module_init(gfar_init);
2505module_exit(gfar_exit);
2506
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