[net-next-2.6.git] / arch / x86 / kernel / cpu / cyrix.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/dma.h>
#include <linux/io.h>
#include <asm/processor-cyrix.h>
#include <asm/processor-flags.h>
#include <linux/timer.h>
#include <asm/pci-direct.h>
#include <asm/tsc.h>

#include "cpu.h"

/*
 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
 */
static void __cpuinit __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned char ccr2, ccr3;

	/* we test for DEVID by checking whether CCR3 is writable */
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	getCx86(0xc0);   /* dummy to change bus */

	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
		ccr2 = getCx86(CX86_CCR2);
		setCx86(CX86_CCR2, ccr2 ^ 0x04);
		getCx86(0xc0);  /* dummy */

		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
			*dir0 = 0xfd;
		else {                          /* Cx486S A step */
			setCx86(CX86_CCR2, ccr2);
			*dir0 = 0xfe;
		}
	} else {
		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */

		/* read DIR0 and DIR1 CPU registers */
		*dir0 = getCx86(CX86_DIR0);
		*dir1 = getCx86(CX86_DIR1);
	}
}

static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned long flags;

	local_irq_save(flags);
	__do_cyrix_devid(dir0, dir1);
	local_irq_restore(flags);
}
/*
 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
 * order to identify the Cyrix CPU model after we're out of setup.c
 *
 * Actually since bugs.h doesn't even reference this perhaps someone should
 * fix the documentation ???
 */
static unsigned char Cx86_dir0_msb __cpuinitdata = 0;

static const char __cpuinitconst Cx86_model[][9] = {
	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	"M II ", "Unknown"
};
static const char __cpuinitconst Cx486_name[][5] = {
	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	"SRx2", "DRx2"
};
static const char __cpuinitconst Cx486S_name[][4] = {
	"S", "S2", "Se", "S2e"
};
static const char __cpuinitconst Cx486D_name[][4] = {
	"DX", "DX2", "?", "?", "?", "DX4"
};
static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
static const char __cpuinitconst cyrix_model_mult1[] = "12??43";
static const char __cpuinitconst cyrix_model_mult2[] = "12233445";

/*
 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
 * BIOSes for compatibility with DOS games.  This makes the udelay loop
 * work correctly, and improves performance.
 *
 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
 */

static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
{
	unsigned long flags;

	if (Cx86_dir0_msb == 3) {
		unsigned char ccr3, ccr5;

		local_irq_save(flags);
		ccr3 = getCx86(CX86_CCR3);
		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
		ccr5 = getCx86(CX86_CCR5);
		if (ccr5 & 2)
			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
		local_irq_restore(flags);

		if (ccr5 & 2) { /* possible wrong calibration done */
			printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
			calibrate_delay();
			c->loops_per_jiffy = loops_per_jiffy;
		}
	}
}


static void __cpuinit set_cx86_reorder(void)
{
	u8 ccr3;

	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */

	/* Load/Store Serialize to mem access disable (=reorder it) */
	setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
	/* set load/store serialize from 1GB to 4GB */
	ccr3 |= 0xe0;
	setCx86(CX86_CCR3, ccr3);
}

static void __cpuinit set_cx86_memwb(void)
{
	printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");

	/* CCR2 bit 2: unlock NW bit */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
	/* set 'Not Write-through' */
	write_cr0(read_cr0() | X86_CR0_NW);
	/* CCR2 bit 2: lock NW bit and set WT1 */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
}

/*
 *	Configure later MediaGX and/or Geode processor.
 */

static void __cpuinit geode_configure(void)
{
	unsigned long flags;
	u8 ccr3;
	local_irq_save(flags);

	/* Suspend on halt power saving and enable #SUSP pin */
	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */


	/* FPU fast, DTE cache, Mem bypass */
	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */

	set_cx86_memwb();
	set_cx86_reorder();

	local_irq_restore(flags);
}

static void __cpuinit early_init_cyrix(struct cpuinfo_x86 *c)
{
	unsigned char dir0, dir0_msn, dir1 = 0;

	__do_cyrix_devid(&dir0, &dir1);
	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */

	switch (dir0_msn) {
	case 3: /* 6x86/6x86L */
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;
	case 5: /* 6x86MX/M II */
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;
	}
}

static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
{
	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	char *buf = c->x86_model_id;
	const char *p = NULL;

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_cpu_cap(c, 0*32+31);

	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
	if (test_cpu_cap(c, 1*32+24)) {
		clear_cpu_cap(c, 1*32+24);
		set_cpu_cap(c, X86_FEATURE_CXMMX);
	}

	do_cyrix_devid(&dir0, &dir1);

	check_cx686_slop(c);

	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */

	/* common case step number/rev -- exceptions handled below */
	c->x86_model = (dir1 >> 4) + 1;
	c->x86_mask = dir1 & 0xf;

	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	 * We do the same thing for each generation: we work out
	 * the model, multiplier and stepping.  Black magic included,
	 * to make the silicon step/rev numbers match the printed ones.
	 */

	switch (dir0_msn) {
		unsigned char tmp;

	case 0: /* Cx486SLC/DLC/SRx/DRx */
		p = Cx486_name[dir0_lsn & 7];
		break;

	case 1: /* Cx486S/DX/DX2/DX4 */
		p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
			: Cx486S_name[dir0_lsn & 3];
		break;

	case 2: /* 5x86 */
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		p = Cx86_cb+2;
		break;

	case 3: /* 6x86/6x86L */
		Cx86_cb[1] = ' ';
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		if (dir1 > 0x21) { /* 686L */
			Cx86_cb[0] = 'L';
			p = Cx86_cb;
			(c->x86_model)++;
		} else             /* 686 */
			p = Cx86_cb+1;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		/* 6x86's contain this bug */
		c->coma_bug = 1;
		break;

	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
#ifdef CONFIG_PCI
	{
		u32 vendor, device;
		/*
		 * It isn't really a PCI quirk directly, but the cure is the
		 * same. The MediaGX has deep magic SMM stuff that handles the
		 * SB emulation. It throws away the fifo on disable_dma() which
		 * is wrong and ruins the audio.
		 *
		 *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
		 *  causes bad things. According to NatSemi VSA2 has another
		 *  bug to do with 'hlt'. I've not seen any boards using VSA2
		 *  and X doesn't seem to support it either so who cares 8).
		 *  VSA1 we work around however.
		 */

		printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
		isa_dma_bridge_buggy = 2;

		/* We do this before the PCI layer is running. However we
		   are safe here as we know the bridge must be a Cyrix
		   companion and must be present */
		vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
		device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);

		/*
		 *  The 5510/5520 companion chips have a funky PIT.
		 */
		if (vendor == PCI_VENDOR_ID_CYRIX &&
			(device == PCI_DEVICE_ID_CYRIX_5510 ||
					device == PCI_DEVICE_ID_CYRIX_5520))
			mark_tsc_unstable("cyrix 5510/5520 detected");
	}
#endif
		c->x86_cache_size = 16;	/* Yep 16K integrated cache thats it */

		/* GXm supports extended cpuid levels 'ala' AMD */
		if (c->cpuid_level == 2) {
			/* Enable cxMMX extensions (GX1 Datasheet 54) */
			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);

			/*
			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
			 * GXlv: 0x6x          GXlv datasheet 54
			 *  ?  : 0x7x
			 * GX1 : 0x8x          GX1  datasheet 56
			 */
			if ((0x30 <= dir1 && dir1 <= 0x6f) ||
					(0x80 <= dir1 && dir1 <= 0x8f))
				geode_configure();
			return;
		} else { /* MediaGX */
			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
			p = Cx86_cb+2;
			c->x86_model = (dir1 & 0x20) ? 1 : 2;
		}
		break;

	case 5: /* 6x86MX/M II */
		if (dir1 > 7) {
			dir0_msn++;  /* M II */
			/* Enable MMX extensions (App note 108) */
			setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
		} else {
			c->coma_bug = 1;      /* 6x86MX, it has the bug. */
		}
		tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
		Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
		p = Cx86_cb+tmp;
		if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
			(c->x86_model)++;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;

	case 0xf:  /* Cyrix 486 without DEVID registers */
		switch (dir0_lsn) {
		case 0xd:  /* either a 486SLC or DLC w/o DEVID */
			dir0_msn = 0;
			p = Cx486_name[(c->hard_math) ? 1 : 0];
			break;

		case 0xe:  /* a 486S A step */
			dir0_msn = 0;
			p = Cx486S_name[0];
			break;
		}
		break;

	default:  /* unknown (shouldn't happen, we know everyone ;-) */
		dir0_msn = 7;
		break;
	}
	strcpy(buf, Cx86_model[dir0_msn & 7]);
	if (p)
		strcat(buf, p);
	return;
}

/*
 * Handle National Semiconductor branded processors
 */
static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
{
	/*
	 * There may be GX1 processors in the wild that are branded
	 * NSC and not Cyrix.
	 *
	 * This function only handles the GX processor, and kicks every
	 * thing else to the Cyrix init function above - that should
	 * cover any processors that might have been branded differently
	 * after NSC acquired Cyrix.
	 *
	 * If this breaks your GX1 horribly, please e-mail
	 * info-linux@ldcmail.amd.com to tell us.
	 */

	/* Handle the GX (Formally known as the GX2) */

	if (c->x86 == 5 && c->x86_model == 5)
		cpu_detect_cache_sizes(c);
	else
		init_cyrix(c);
}

/*
 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 * by the fact that they preserve the flags across the division of 5/2.
 * PII and PPro exhibit this behavior too, but they have cpuid available.
 */

/*
 * Perform the Cyrix 5/2 test. A Cyrix won't change
 * the flags, while other 486 chips will.
 */
static inline int test_cyrix_52div(void)
{
	unsigned int test;

	__asm__ __volatile__(
	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
	     "div %b2\n\t"	/* divide 5 by 2 */
	     "lahf"		/* store flags into %ah */
	     : "=a" (test)
	     : "0" (5), "q" (2)
	     : "cc");

	/* AH is 0x02 on Cyrix after the divide.. */
	return (unsigned char) (test >> 8) == 0x02;
}

static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
{
	/* Detect Cyrix with disabled CPUID */
	if (c->x86 == 4 && test_cyrix_52div()) {
		unsigned char dir0, dir1;

		strcpy(c->x86_vendor_id, "CyrixInstead");
		c->x86_vendor = X86_VENDOR_CYRIX;

		/* Actually enable cpuid on the older cyrix */

		/* Retrieve CPU revisions */

		do_cyrix_devid(&dir0, &dir1);

		dir0 >>= 4;

		/* Check it is an affected model */

		if (dir0 == 5 || dir0 == 3) {
			unsigned char ccr3;
			unsigned long flags;
			printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
			local_irq_save(flags);
			ccr3 = getCx86(CX86_CCR3);
			/* enable MAPEN  */
			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
			/* enable cpuid  */
			setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);
			/* disable MAPEN */
			setCx86(CX86_CCR3, ccr3);
			local_irq_restore(flags);
		}
	}
}

static const struct cpu_dev __cpuinitconst cyrix_cpu_dev = {
	.c_vendor	= "Cyrix",
	.c_ident	= { "CyrixInstead" },
	.c_early_init	= early_init_cyrix,
	.c_init		= init_cyrix,
	.c_identify	= cyrix_identify,
	.c_x86_vendor	= X86_VENDOR_CYRIX,
};

cpu_dev_register(cyrix_cpu_dev);

static const struct cpu_dev __cpuinitconst nsc_cpu_dev = {
	.c_vendor	= "NSC",
	.c_ident	= { "Geode by NSC" },
	.c_init		= init_nsc,
	.c_x86_vendor	= X86_VENDOR_NSC,
};

cpu_dev_register(nsc_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/delay.h>
	4	#include <linux/pci.h>
	5	#include <asm/dma.h>
8bdbd962	6	#include <linux/io.h>
f25f64ed	7	#include <asm/processor-cyrix.h>
7ebad705	8	#include <asm/processor-flags.h>
8bdbd962	9	#include <linux/timer.h>
120fad72	10	#include <asm/pci-direct.h>
e8edc6e0	11	#include <asm/tsc.h>
1da177e4 LT	12
	13	#include "cpu.h"
	14
	15	/*
	16	* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
	17	*/
5fef55fd	18	static void __cpuinit __do_cyrix_devid(unsigned char dir0, unsigned char dir1)
1da177e4 LT	19	{
1da177e4 LT	20	unsigned char ccr2, ccr3;
adf85265	21
1da177e4	22	/* we test for DEVID by checking whether CCR3 is writable */
1da177e4 LT	23	ccr3 = getCx86(CX86_CCR3);
	24	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	25	getCx86(0xc0); /* dummy to change bus */
	26
	27	if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
	28	ccr2 = getCx86(CX86_CCR2);
	29	setCx86(CX86_CCR2, ccr2 ^ 0x04);
	30	getCx86(0xc0); /* dummy */
	31
	32	if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
	33	*dir0 = 0xfd;
	34	else { /* Cx486S A step */
	35	setCx86(CX86_CCR2, ccr2);
	36	*dir0 = 0xfe;
	37	}
adf85265	38	} else {
1da177e4 LT	39	setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
	40
	41	/* read DIR0 and DIR1 CPU registers */
	42	*dir0 = getCx86(CX86_DIR0);
	43	*dir1 = getCx86(CX86_DIR1);
	44	}
1da177e4 LT	45	}
1da177e4 LT	46
5fef55fd YL	47	static void __cpuinit do_cyrix_devid(unsigned char dir0, unsigned char dir1)
	48	{
	49	unsigned long flags;
	50
	51	local_irq_save(flags);
	52	__do_cyrix_devid(dir0, dir1);
	53	local_irq_restore(flags);
	54	}
1da177e4 LT	55	/*
	56	* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
	57	* order to identify the Cyrix CPU model after we're out of setup.c
	58	*
	59	* Actually since bugs.h doesn't even reference this perhaps someone should
	60	* fix the documentation ???
	61	*/
b4af3f7c	62	static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
1da177e4	63
02dde8b4	64	static const char __cpuinitconst Cx86_model[][9] = {
1da177e4 LT	65	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	66	"M II ", "Unknown"
	67	};
02dde8b4	68	static const char __cpuinitconst Cx486_name[][5] = {
1da177e4 LT	69	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	70	"SRx2", "DRx2"
	71	};
02dde8b4	72	static const char __cpuinitconst Cx486S_name[][4] = {
1da177e4 LT	73	"S", "S2", "Se", "S2e"
1da177e4 LT	74	};
02dde8b4	75	static const char __cpuinitconst Cx486D_name[][4] = {
1da177e4 LT	76	"DX", "DX2", "?", "?", "?", "DX4"
1da177e4 LT	77	};
b4af3f7c	78	static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
02dde8b4 JB	79	static const char __cpuinitconst cyrix_model_mult1[] = "12??43";
02dde8b4 JB	80	static const char __cpuinitconst cyrix_model_mult2[] = "12233445";
1da177e4 LT	81
	82	/*
	83	* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
	84	* BIOSes for compatibility with DOS games. This makes the udelay loop
	85	* work correctly, and improves performance.
	86	*
	87	* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
	88	*/
	89
b4af3f7c	90	static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
1da177e4 LT	91	{
1da177e4 LT	92	unsigned long flags;
adf85265	93
1da177e4 LT	94	if (Cx86_dir0_msb == 3) {
	95	unsigned char ccr3, ccr5;
	96
	97	local_irq_save(flags);
	98	ccr3 = getCx86(CX86_CCR3);
db955170	99	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4 LT	100	ccr5 = getCx86(CX86_CCR5);
	101	if (ccr5 & 2)
	102	setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
	103	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
	104	local_irq_restore(flags);
	105
	106	if (ccr5 & 2) { /* possible wrong calibration done */
	107	printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
	108	calibrate_delay();
	109	c->loops_per_jiffy = loops_per_jiffy;
	110	}
	111	}
	112	}
	113
	114
b4af3f7c	115	static void __cpuinit set_cx86_reorder(void)
1da177e4 LT	116	{
	117	u8 ccr3;
	118
	119	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	120	ccr3 = getCx86(CX86_CCR3);
96de0e25	121	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4	122
96de0e25	123	/* Load/Store Serialize to mem access disable (=reorder it) */
026e2c05	124	setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
1da177e4 LT	125	/* set load/store serialize from 1GB to 4GB */
	126	ccr3 \|= 0xe0;
	127	setCx86(CX86_CCR3, ccr3);
	128	}
	129
b4af3f7c	130	static void __cpuinit set_cx86_memwb(void)
1da177e4	131	{
1da177e4 LT	132	printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
	133
	134	/* CCR2 bit 2: unlock NW bit */
026e2c05	135	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
1da177e4	136	/* set 'Not Write-through' */
7ebad705	137	write_cr0(read_cr0() \| X86_CR0_NW);
1da177e4	138	/* CCR2 bit 2: lock NW bit and set WT1 */
026e2c05	139	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) \| 0x14);
1da177e4 LT	140	}
1da177e4 LT	141
1da177e4 LT	142	/*
	143	* Configure later MediaGX and/or Geode processor.
	144	*/
	145
b4af3f7c	146	static void __cpuinit geode_configure(void)
1da177e4 LT	147	{
1da177e4 LT	148	unsigned long flags;
bcde1ebb	149	u8 ccr3;
1da177e4 LT	150	local_irq_save(flags);
	151
	152	/* Suspend on halt power saving and enable #SUSP pin */
026e2c05	153	setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) \| 0x88);
1da177e4 LT	154
1da177e4 LT	155	ccr3 = getCx86(CX86_CCR3);
bcde1ebb	156	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
adf85265	157
bcde1ebb TY	158
bcde1ebb TY	159	/* FPU fast, DTE cache, Mem bypass */
026e2c05	160	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) \| 0x38);
bcde1ebb	161	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
adf85265	162
1da177e4	163	set_cx86_memwb();
adf85265	164	set_cx86_reorder();
adf85265	165
1da177e4 LT	166	local_irq_restore(flags);
	167	}
	168
5fef55fd YL	169	static void __cpuinit early_init_cyrix(struct cpuinfo_x86 *c)
	170	{
	171	unsigned char dir0, dir0_msn, dir1 = 0;
	172
	173	__do_cyrix_devid(&dir0, &dir1);
	174	dir0_msn = dir0 >> 4; /* identifies CPU "family" */
	175
	176	switch (dir0_msn) {
	177	case 3: /* 6x86/6x86L */
	178	/* Emulate MTRRs using Cyrix's ARRs. */
	179	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
	180	break;
	181	case 5: /* 6x86MX/M II */
	182	/* Emulate MTRRs using Cyrix's ARRs. */
	183	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
	184	break;
	185	}
	186	}
1da177e4	187
b4af3f7c	188	static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
1da177e4 LT	189	{
	190	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	191	char *buf = c->x86_model_id;
	192	const char *p = NULL;
	193
adf85265 PC	194	/*
	195	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	196	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	197	*/
1d007cd5	198	clear_cpu_cap(c, 0*32+31);
1da177e4 LT	199
1da177e4 LT	200	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
1d007cd5 IM	201	if (test_cpu_cap(c, 1*32+24)) {
	202	clear_cpu_cap(c, 1*32+24);
	203	set_cpu_cap(c, X86_FEATURE_CXMMX);
1da177e4 LT	204	}
	205
	206	do_cyrix_devid(&dir0, &dir1);
	207
	208	check_cx686_slop(c);
	209
	210	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
	211	dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
	212
	213	/* common case step number/rev -- exceptions handled below */
	214	c->x86_model = (dir1 >> 4) + 1;
	215	c->x86_mask = dir1 & 0xf;
	216
	217	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	218	* We do the same thing for each generation: we work out
	219	* the model, multiplier and stepping. Black magic included,
	220	* to make the silicon step/rev numbers match the printed ones.
	221	*/
adf85265	222
1da177e4 LT	223	switch (dir0_msn) {
	224	unsigned char tmp;
	225
	226	case 0: /* Cx486SLC/DLC/SRx/DRx */
	227	p = Cx486_name[dir0_lsn & 7];
	228	break;
	229
	230	case 1: /* Cx486S/DX/DX2/DX4 */
	231	p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
	232	: Cx486S_name[dir0_lsn & 3];
	233	break;
	234
	235	case 2: /* 5x86 */
	236	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	237	p = Cx86_cb+2;
	238	break;
	239
	240	case 3: /* 6x86/6x86L */
	241	Cx86_cb[1] = ' ';
	242	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	243	if (dir1 > 0x21) { /* 686L */
	244	Cx86_cb[0] = 'L';
	245	p = Cx86_cb;
	246	(c->x86_model)++;
	247	} else /* 686 */
	248	p = Cx86_cb+1;
	249	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	250	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4 LT	251	/* 6x86's contain this bug */
	252	c->coma_bug = 1;
	253	break;
	254
	255	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
	256	#ifdef CONFIG_PCI
120fad72 AC	257	{
120fad72 AC	258	u32 vendor, device;
adf85265 PC	259	/*
	260	* It isn't really a PCI quirk directly, but the cure is the
	261	* same. The MediaGX has deep magic SMM stuff that handles the
	262	* SB emulation. It throws away the fifo on disable_dma() which
	263	* is wrong and ruins the audio.
	264	*
	265	* Bug2: VSA1 has a wrap bug so that using maximum sized DMA
	266	* causes bad things. According to NatSemi VSA2 has another
	267	* bug to do with 'hlt'. I've not seen any boards using VSA2
	268	* and X doesn't seem to support it either so who cares 8).
	269	* VSA1 we work around however.
	270	*/
1da177e4 LT	271
	272	printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
	273	isa_dma_bridge_buggy = 2;
cefc0113	274
120fad72 AC	275	/* We do this before the PCI layer is running. However we
	276	are safe here as we know the bridge must be a Cyrix
	277	companion and must be present */
	278	vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
	279	device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
cefc0113	280
1da177e4 LT	281	/*
1da177e4 LT	282	* The 5510/5520 companion chips have a funky PIT.
adf85265	283	*/
120fad72	284	if (vendor == PCI_VENDOR_ID_CYRIX &&
8bdbd962 AC	285	(device == PCI_DEVICE_ID_CYRIX_5510 \|\|
8bdbd962 AC	286	device == PCI_DEVICE_ID_CYRIX_5520))
5a90cf20	287	mark_tsc_unstable("cyrix 5510/5520 detected");
120fad72	288	}
cefc0113	289	#endif
adf85265	290	c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
1da177e4 LT	291
	292	/* GXm supports extended cpuid levels 'ala' AMD */
	293	if (c->cpuid_level == 2) {
	294	/* Enable cxMMX extensions (GX1 Datasheet 54) */
026e2c05	295	setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) \| 1);
adf85265	296
2632f01a	297	/*
	298	* GXm : 0x30 ... 0x5f GXm datasheet 51
	299	* GXlv: 0x6x GXlv datasheet 54
	300	* ? : 0x7x
	301	* GX1 : 0x8x GX1 datasheet 56
	302	*/
8bdbd962 AC	303	if ((0x30 <= dir1 && dir1 <= 0x6f) \|\|
8bdbd962 AC	304	(0x80 <= dir1 && dir1 <= 0x8f))
1da177e4	305	geode_configure();
1da177e4	306	return;
adf85265	307	} else { /* MediaGX */
1da177e4 LT	308	Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
	309	p = Cx86_cb+2;
	310	c->x86_model = (dir1 & 0x20) ? 1 : 2;
	311	}
	312	break;
	313
adf85265 PC	314	case 5: /* 6x86MX/M II */
adf85265 PC	315	if (dir1 > 7) {
1da177e4 LT	316	dir0_msn++; /* M II */
1da177e4 LT	317	/* Enable MMX extensions (App note 108) */
026e2c05	318	setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)\|1);
adf85265	319	} else {
1da177e4 LT	320	c->coma_bug = 1; /* 6x86MX, it has the bug. */
	321	}
	322	tmp = (!(dir0_lsn & 7) \|\| dir0_lsn & 1) ? 2 : 0;
	323	Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
	324	p = Cx86_cb+tmp;
adf85265	325	if (((dir1 & 0x0f) > 4) \|\| ((dir1 & 0xf0) == 0x20))
1da177e4 LT	326	(c->x86_model)++;
1da177e4 LT	327	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	328	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4 LT	329	break;
	330
	331	case 0xf: /* Cyrix 486 without DEVID registers */
	332	switch (dir0_lsn) {
	333	case 0xd: /* either a 486SLC or DLC w/o DEVID */
	334	dir0_msn = 0;
	335	p = Cx486_name[(c->hard_math) ? 1 : 0];
	336	break;
	337
	338	case 0xe: /* a 486S A step */
	339	dir0_msn = 0;
	340	p = Cx486S_name[0];
	341	break;
	342	}
	343	break;
	344
	345	default: /* unknown (shouldn't happen, we know everyone ;-) */
	346	dir0_msn = 7;
	347	break;
	348	}
	349	strcpy(buf, Cx86_model[dir0_msn & 7]);
adf85265 PC	350	if (p)
adf85265 PC	351	strcat(buf, p);
1da177e4 LT	352	return;
	353	}
	354
f90b8116 JC	355	/*
	356	* Handle National Semiconductor branded processors
	357	*/
b4af3f7c	358	static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
f90b8116	359	{
adf85265 PC	360	/*
adf85265 PC	361	* There may be GX1 processors in the wild that are branded
f90b8116 JC	362	* NSC and not Cyrix.
	363	*
	364	* This function only handles the GX processor, and kicks every
	365	* thing else to the Cyrix init function above - that should
	366	* cover any processors that might have been branded differently
d6e05edc	367	* after NSC acquired Cyrix.
f90b8116 JC	368	*
	369	* If this breaks your GX1 horribly, please e-mail
	370	* info-linux@ldcmail.amd.com to tell us.
	371	*/
	372
	373	/* Handle the GX (Formally known as the GX2) */
	374
	375	if (c->x86 == 5 && c->x86_model == 5)
27c13ece	376	cpu_detect_cache_sizes(c);
f90b8116 JC	377	else
	378	init_cyrix(c);
	379	}
	380
1da177e4 LT	381	/*
	382	* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
	383	* by the fact that they preserve the flags across the division of 5/2.
	384	* PII and PPro exhibit this behavior too, but they have cpuid available.
	385	*/
adf85265	386
1da177e4 LT	387	/*
	388	* Perform the Cyrix 5/2 test. A Cyrix won't change
	389	* the flags, while other 486 chips will.
	390	*/
	391	static inline int test_cyrix_52div(void)
	392	{
	393	unsigned int test;
	394
	395	__asm__ __volatile__(
	396	"sahf\n\t" /* clear flags (%eax = 0x0005) */
	397	"div %b2\n\t" /* divide 5 by 2 */
	398	"lahf" /* store flags into %ah */
	399	: "=a" (test)
	400	: "0" (5), "q" (2)
	401	: "cc");
	402
	403	/* AH is 0x02 on Cyrix after the divide.. */
	404	return (unsigned char) (test >> 8) == 0x02;
	405	}
	406
adf85265	407	static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
1da177e4 LT	408	{
1da177e4 LT	409	/* Detect Cyrix with disabled CPUID */
adf85265	410	if (c->x86 == 4 && test_cyrix_52div()) {
1da177e4	411	unsigned char dir0, dir1;
adf85265	412
1da177e4	413	strcpy(c->x86_vendor_id, "CyrixInstead");
adf85265 PC	414	c->x86_vendor = X86_VENDOR_CYRIX;
	415
	416	/* Actually enable cpuid on the older cyrix */
	417
	418	/* Retrieve CPU revisions */
	419
1da177e4 LT	420	do_cyrix_devid(&dir0, &dir1);
1da177e4 LT	421
adf85265 PC	422	dir0 >>= 4;
adf85265 PC	423
1da177e4	424	/* Check it is an affected model */
adf85265 PC	425
adf85265 PC	426	if (dir0 == 5 \|\| dir0 == 3) {
bcde1ebb	427	unsigned char ccr3;
1da177e4 LT	428	unsigned long flags;
	429	printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
	430	local_irq_save(flags);
	431	ccr3 = getCx86(CX86_CCR3);
8bdbd962 AC	432	/* enable MAPEN */
	433	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10);
	434	/* enable cpuid */
	435	setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) \| 0x80);
	436	/* disable MAPEN */
	437	setCx86(CX86_CCR3, ccr3);
1da177e4 LT	438	local_irq_restore(flags);
	439	}
	440	}
1da177e4 LT	441	}
1da177e4 LT	442
02dde8b4	443	static const struct cpu_dev __cpuinitconst cyrix_cpu_dev = {
1da177e4	444	.c_vendor = "Cyrix",
adf85265	445	.c_ident = { "CyrixInstead" },
5fef55fd	446	.c_early_init = early_init_cyrix,
1da177e4 LT	447	.c_init = init_cyrix,
1da177e4 LT	448	.c_identify = cyrix_identify,
10a434fc	449	.c_x86_vendor = X86_VENDOR_CYRIX,
1da177e4 LT	450	};
1da177e4 LT	451
10a434fc	452	cpu_dev_register(cyrix_cpu_dev);
1da177e4	453
02dde8b4	454	static const struct cpu_dev __cpuinitconst nsc_cpu_dev = {
1da177e4	455	.c_vendor = "NSC",
adf85265	456	.c_ident = { "Geode by NSC" },
f90b8116	457	.c_init = init_nsc,
10a434fc	458	.c_x86_vendor = X86_VENDOR_NSC,
1da177e4 LT	459	};
1da177e4 LT	460
10a434fc	461	cpu_dev_register(nsc_cpu_dev);