[net-next-2.6.git] / arch / sh / boards / mach-dreamcast / irq.c

/*
 * arch/sh/boards/dreamcast/irq.c
 *
 * Holly IRQ support for the Sega Dreamcast.
 *
 * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
 *
 * This file is part of the LinuxDC project (www.linuxdc.org)
 * Released under the terms of the GNU GPL v2.0
 */

#include <linux/irq.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <mach/sysasic.h>

/*
 * Dreamcast System ASIC Hardware Events -
 *
 * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
 * hardware events from system peripherals and triggering an SH7750 IRQ.
 * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
 * set in the Event Mask Registers (EMRs).  When a hardware event is
 * triggered, its corresponding bit in the Event Status Registers (ESRs)
 * is set, and that bit should be rewritten to the ESR to acknowledge that
 * event.
 *
 * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908.  Event
 * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
 * There are three groups of EMRs that parallel the ESRs.  Each EMR group
 * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
 * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
 * triggers IRQ 9.
 *
 * In the kernel, these events are mapped to virtual IRQs so that drivers can
 * respond to them as they would a normal interrupt.  In order to keep this
 * mapping simple, the events are mapped as:
 *
 * 6900/6910 - Events  0-31, IRQ 13
 * 6904/6924 - Events 32-63, IRQ 11
 * 6908/6938 - Events 64-95, IRQ  9
 *
 */

#define ESR_BASE 0x005f6900    /* Base event status register */
#define EMR_BASE 0x005f6910    /* Base event mask register */

/*
 * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
 * 1 = 0x6920, 2 = 0x6930; also determine the event offset.
 */
#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)

/* Return the hardware event's bit positon within the EMR/ESR */
#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)

/*
 * For each of these *_irq routines, the IRQ passed in is the virtual IRQ
 * (logically mapped to the corresponding bit for the hardware event).
 */

/* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
	__u32 mask;

	mask = inl(emr);
	mask &= ~(1 << EVENT_BIT(irq));
	outl(mask, emr);
}

/* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
	__u32 mask;

	mask = inl(emr);
	mask |= (1 << EVENT_BIT(irq));
	outl(mask, emr);
}

/* Acknowledge a hardware event by writing its bit back to its ESR */
static void mask_ack_systemasic_irq(struct irq_data *data)
{
	unsigned int irq = data->irq;
	__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
	disable_systemasic_irq(data);
	outl((1 << EVENT_BIT(irq)), esr);
}

struct irq_chip systemasic_int = {
	.name		= "System ASIC",
	.irq_mask	= disable_systemasic_irq,
	.irq_mask_ack	= mask_ack_systemasic_irq,
	.irq_unmask	= enable_systemasic_irq,
};

/*
 * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
 */
int systemasic_irq_demux(int irq)
{
	__u32 emr, esr, status, level;
	__u32 j, bit;

	switch (irq) {
	case 13:
		level = 0;
		break;
	case 11:
		level = 1;
		break;
	case  9:
		level = 2;
		break;
	default:
		return irq;
	}
	emr = EMR_BASE + (level << 4) + (level << 2);
	esr = ESR_BASE + (level << 2);

	/* Mask the ESR to filter any spurious, unwanted interrupts */
	status = inl(esr);
	status &= inl(emr);

	/* Now scan and find the first set bit as the event to map */
	for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
		if (status & bit) {
			irq = HW_EVENT_IRQ_BASE + j + (level << 5);
			return irq;
		}
	}

	/* Not reached */
	return irq;
}

void systemasic_irq_init(void)
{
	int i, nid = cpu_to_node(boot_cpu_data);

	/* Assign all virtual IRQs to the System ASIC int. handler */
	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
		unsigned int irq;

		irq = create_irq_nr(i, nid);
		if (unlikely(irq == 0)) {
			pr_err("%s: failed hooking irq %d for systemasic\n",
			       __func__, i);
			return;
		}

		if (unlikely(irq != i)) {
			pr_err("%s: got irq %d but wanted %d, bailing.\n",
			       __func__, irq, i);
			destroy_irq(irq);
			return;
		}

		set_irq_chip_and_handler(i, &systemasic_int,
					 handle_level_irq);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/boards/dreamcast/irq.c
	3	*
	4	* Holly IRQ support for the Sega Dreamcast.
	5	*
	6	* Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
	7	*
	8	* This file is part of the LinuxDC project (www.linuxdc.org)
	9	* Released under the terms of the GNU GPL v2.0
	10	*/
	11
	12	#include <linux/irq.h>
e85a4774	13	#include <linux/io.h>
1da177e4	14	#include <asm/irq.h>
f15cbe6f	15	#include <mach/sysasic.h>
1da177e4	16
e85a4774 MF	17	/*
	18	* Dreamcast System ASIC Hardware Events -
	19	*
	20	* The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
	21	* hardware events from system peripherals and triggering an SH7750 IRQ.
	22	* Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
	23	* set in the Event Mask Registers (EMRs). When a hardware event is
	24	* triggered, its corresponding bit in the Event Status Registers (ESRs)
	25	* is set, and that bit should be rewritten to the ESR to acknowledge that
	26	* event.
	27	*
	28	* There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event
	29	* types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.
	30	* There are three groups of EMRs that parallel the ESRs. Each EMR group
	31	* corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,
	32	* 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938
	33	* triggers IRQ 9.
	34	*
	35	* In the kernel, these events are mapped to virtual IRQs so that drivers can
	36	* respond to them as they would a normal interrupt. In order to keep this
	37	* mapping simple, the events are mapped as:
	38	*
	39	* 6900/6910 - Events 0-31, IRQ 13
	40	* 6904/6924 - Events 32-63, IRQ 11
	41	* 6908/6938 - Events 64-95, IRQ 9
	42	*
	43	*/
1da177e4 LT	44
	45	#define ESR_BASE 0x005f6900 /* Base event status register */
	46	#define EMR_BASE 0x005f6910 /* Base event mask register */
	47
e85a4774 MF	48	/*
	49	* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
	50	* 1 = 0x6920, 2 = 0x6930; also determine the event offset.
	51	*/
1da177e4 LT	52	#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
	53
	54	/* Return the hardware event's bit positon within the EMR/ESR */
	55	#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
	56
e85a4774 MF	57	/*
	58	* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
	59	* (logically mapped to the corresponding bit for the hardware event).
	60	*/
1da177e4 LT	61
1da177e4 LT	62	/* Disable the hardware event by masking its bit in its EMR */
0d338071	63	static inline void disable_systemasic_irq(struct irq_data *data)
1da177e4	64	{
0d338071	65	unsigned int irq = data->irq;
e85a4774 MF	66	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
e85a4774 MF	67	__u32 mask;
1da177e4	68
e85a4774 MF	69	mask = inl(emr);
	70	mask &= ~(1 << EVENT_BIT(irq));
	71	outl(mask, emr);
1da177e4 LT	72	}
	73
	74	/* Enable the hardware event by setting its bit in its EMR */
0d338071	75	static inline void enable_systemasic_irq(struct irq_data *data)
1da177e4	76	{
0d338071	77	unsigned int irq = data->irq;
e85a4774 MF	78	__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
e85a4774 MF	79	__u32 mask;
1da177e4	80
e85a4774 MF	81	mask = inl(emr);
	82	mask \|= (1 << EVENT_BIT(irq));
	83	outl(mask, emr);
1da177e4 LT	84	}
	85
	86	/* Acknowledge a hardware event by writing its bit back to its ESR */
0d338071	87	static void mask_ack_systemasic_irq(struct irq_data *data)
1da177e4	88	{
0d338071	89	unsigned int irq = data->irq;
e85a4774	90	__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
0d338071	91	disable_systemasic_irq(data);
e85a4774	92	outl((1 << EVENT_BIT(irq)), esr);
1da177e4 LT	93	}
1da177e4 LT	94
e85a4774 MF	95	struct irq_chip systemasic_int = {
e85a4774 MF	96	.name = "System ASIC",
0d338071 PM	97	.irq_mask = disable_systemasic_irq,
	98	.irq_mask_ack = mask_ack_systemasic_irq,
	99	.irq_unmask = enable_systemasic_irq,
1da177e4 LT	100	};
	101
	102	/*
	103	* Map the hardware event indicated by the processor IRQ to a virtual IRQ.
	104	*/
	105	int systemasic_irq_demux(int irq)
	106	{
e85a4774 MF	107	__u32 emr, esr, status, level;
	108	__u32 j, bit;
	109
	110	switch (irq) {
	111	case 13:
	112	level = 0;
	113	break;
	114	case 11:
	115	level = 1;
	116	break;
	117	case 9:
	118	level = 2;
	119	break;
	120	default:
	121	return irq;
	122	}
	123	emr = EMR_BASE + (level << 4) + (level << 2);
	124	esr = ESR_BASE + (level << 2);
	125
	126	/* Mask the ESR to filter any spurious, unwanted interrupts */
	127	status = inl(esr);
	128	status &= inl(emr);
	129
	130	/* Now scan and find the first set bit as the event to map */
	131	for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
	132	if (status & bit) {
	133	irq = HW_EVENT_IRQ_BASE + j + (level << 5);
	134	return irq;
	135	}
	136	}
	137
	138	/* Not reached */
	139	return irq;
1da177e4	140	}
deb9b22b PM	141
	142	void systemasic_irq_init(void)
	143	{
	144	int i, nid = cpu_to_node(boot_cpu_data);
	145
	146	/* Assign all virtual IRQs to the System ASIC int. handler */
	147	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
	148	unsigned int irq;
	149
	150	irq = create_irq_nr(i, nid);
	151	if (unlikely(irq == 0)) {
	152	pr_err("%s: failed hooking irq %d for systemasic\n",
	153	__func__, i);
	154	return;
	155	}
	156
	157	if (unlikely(irq != i)) {
	158	pr_err("%s: got irq %d but wanted %d, bailing.\n",
	159	__func__, irq, i);
	160	destroy_irq(irq);
	161	return;
	162	}
	163
	164	set_irq_chip_and_handler(i, &systemasic_int,
	165	handle_level_irq);
	166	}
	167	}