[net-next-2.6.git] / arch / arm / plat-omap / io.c

/*
 * Common io.c file
 * This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <mach/omap7xx.h>
#include <mach/omap1510.h>
#include <mach/omap16xx.h>
#include <mach/omap24xx.h>
#include <mach/omap34xx.h>
#include <mach/omap44xx.h>

#define BETWEEN(p,st,sz)	((p) >= (st) && (p) < ((st) + (sz)))
#define XLATE(p,pst,vst)	((void __iomem *)((p) - (pst) + (vst)))

/*
 * Intercept ioremap() requests for addresses in our fixed mapping regions.
 */
void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
{
#ifdef CONFIG_ARCH_OMAP1
	if (cpu_class_is_omap1()) {
		if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
			return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
	}
	if (cpu_is_omap7xx()) {
		if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
			return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);

		if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
			return XLATE(p, OMAP7XX_DSPREG_BASE,
					OMAP7XX_DSPREG_START);
	}
	if (cpu_is_omap15xx()) {
		if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
			return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);

		if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
			return XLATE(p, OMAP1510_DSPREG_BASE,
					OMAP1510_DSPREG_START);
	}
	if (cpu_is_omap16xx()) {
		if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
			return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);

		if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
			return XLATE(p, OMAP16XX_DSPREG_BASE,
					OMAP16XX_DSPREG_START);
	}
#endif
#ifdef CONFIG_ARCH_OMAP2
	if (cpu_is_omap24xx()) {
		if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
			return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
		if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
			return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
	}
	if (cpu_is_omap2420()) {
		if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
			return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
		if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
			return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
		if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
			return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
	}
	if (cpu_is_omap2430()) {
		if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
			return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
		if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
			return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
		if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
			return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
		if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
			return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
	}
#endif
#ifdef CONFIG_ARCH_OMAP3
	if (cpu_is_omap34xx()) {
		if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
			return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
		if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
			return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
		if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
			return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
		if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
			return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
		if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
			return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
		if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
			return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
		if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
			return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
		if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
			return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
	}
#endif
#ifdef CONFIG_ARCH_OMAP4
	if (cpu_is_omap44xx()) {
		if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
			return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
		if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
			return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
		if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
			return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
		if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
			return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
		if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
			return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
		if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
			return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
	}
#endif
	return __arm_ioremap(p, size, type);
}
EXPORT_SYMBOL(omap_ioremap);

void omap_iounmap(volatile void __iomem *addr)
{
	unsigned long virt = (unsigned long)addr;

	if (virt >= VMALLOC_START && virt < VMALLOC_END)
		__iounmap(addr);
}
EXPORT_SYMBOL(omap_iounmap);

/*
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 */

u8 omap_readb(u32 pa)
{
	if (cpu_class_is_omap1())
		return __raw_readb(OMAP1_IO_ADDRESS(pa));
	else
		return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_readb);

u16 omap_readw(u32 pa)
{
	if (cpu_class_is_omap1())
		return __raw_readw(OMAP1_IO_ADDRESS(pa));
	else
		return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_readw);

u32 omap_readl(u32 pa)
{
	if (cpu_class_is_omap1())
		return __raw_readl(OMAP1_IO_ADDRESS(pa));
	else
		return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_readl);

void omap_writeb(u8 v, u32 pa)
{
	if (cpu_class_is_omap1())
		__raw_writeb(v, OMAP1_IO_ADDRESS(pa));
	else
		__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_writeb);

void omap_writew(u16 v, u32 pa)
{
	if (cpu_class_is_omap1())
		__raw_writew(v, OMAP1_IO_ADDRESS(pa));
	else
		__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_writew);

void omap_writel(u32 v, u32 pa)
{
	if (cpu_class_is_omap1())
		__raw_writel(v, OMAP1_IO_ADDRESS(pa));
	else
		__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
}
EXPORT_SYMBOL(omap_writel);
Commit	Line	Data
44169075 SS	1	/*
	2	* Common io.c file
	3	* This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
	4	*
	5	* Copyright (C) 2009 Texas Instruments
	6	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
690b5a13 RK	12	#include <linux/module.h>
	13	#include <linux/io.h>
	14	#include <linux/mm.h>
	15
b51988db	16	#include <mach/omap7xx.h>
690b5a13 RK	17	#include <mach/omap1510.h>
	18	#include <mach/omap16xx.h>
	19	#include <mach/omap24xx.h>
	20	#include <mach/omap34xx.h>
44169075	21	#include <mach/omap44xx.h>
690b5a13 RK	22
	23	#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
	24	#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
	25
	26	/*
	27	* Intercept ioremap() requests for addresses in our fixed mapping regions.
	28	*/
	29	void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
	30	{
	31	#ifdef CONFIG_ARCH_OMAP1
	32	if (cpu_class_is_omap1()) {
db326be1 TL	33	if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
db326be1 TL	34	return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
690b5a13	35	}
ab49df73	36	if (cpu_is_omap7xx()) {
b51988db AB	37	if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
b51988db AB	38	return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
690b5a13	39
b51988db AB	40	if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
	41	return XLATE(p, OMAP7XX_DSPREG_BASE,
	42	OMAP7XX_DSPREG_START);
690b5a13 RK	43	}
	44	if (cpu_is_omap15xx()) {
	45	if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
	46	return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
	47
	48	if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
	49	return XLATE(p, OMAP1510_DSPREG_BASE,
	50	OMAP1510_DSPREG_START);
	51	}
	52	if (cpu_is_omap16xx()) {
	53	if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
	54	return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
	55
	56	if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
	57	return XLATE(p, OMAP16XX_DSPREG_BASE,
	58	OMAP16XX_DSPREG_START);
	59	}
	60	#endif
	61	#ifdef CONFIG_ARCH_OMAP2
cc26b3b0	62	if (cpu_is_omap24xx()) {
690b5a13 RK	63	if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
	64	return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
	65	if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
	66	return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
cc26b3b0 SMK	67	}
cc26b3b0 SMK	68	if (cpu_is_omap2420()) {
690b5a13 RK	69	if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
	70	return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
	71	if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
	72	return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
	73	if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
	74	return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
	75	}
690b5a13 RK	76	if (cpu_is_omap2430()) {
690b5a13 RK	77	if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
cc26b3b0	78	return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
690b5a13	79	if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
cc26b3b0 SMK	80	return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
	81	if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
	82	return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
	83	if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
	84	return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
690b5a13 RK	85	}
690b5a13 RK	86	#endif
cc26b3b0 SMK	87	#ifdef CONFIG_ARCH_OMAP3
	88	if (cpu_is_omap34xx()) {
	89	if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
	90	return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
	91	if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
	92	return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
	93	if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
	94	return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
	95	if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
	96	return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
	97	if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
	98	return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
	99	if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
	100	return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
	101	if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
	102	return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
	103	if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
	104	return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
	105	}
690b5a13	106	#endif
44169075 SS	107	#ifdef CONFIG_ARCH_OMAP4
	108	if (cpu_is_omap44xx()) {
	109	if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
	110	return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
	111	if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
	112	return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
	113	if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
	114	return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
	115	if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
	116	return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
	117	if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
	118	return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
	119	if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
	120	return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
	121	}
	122	#endif
690b5a13 RK	123	return __arm_ioremap(p, size, type);
	124	}
	125	EXPORT_SYMBOL(omap_ioremap);
	126
	127	void omap_iounmap(volatile void __iomem *addr)
	128	{
	129	unsigned long virt = (unsigned long)addr;
	130
	131	if (virt >= VMALLOC_START && virt < VMALLOC_END)
	132	__iounmap(addr);
	133	}
	134	EXPORT_SYMBOL(omap_iounmap);
94113260 TL	135
	136	/*
	137	* NOTE: Please use ioremap + __raw_read/write where possible instead of these
	138	*/
	139
	140	u8 omap_readb(u32 pa)
	141	{
	142	if (cpu_class_is_omap1())
	143	return __raw_readb(OMAP1_IO_ADDRESS(pa));
	144	else
233fd64e	145	return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	146	}
	147	EXPORT_SYMBOL(omap_readb);
	148
	149	u16 omap_readw(u32 pa)
	150	{
	151	if (cpu_class_is_omap1())
	152	return __raw_readw(OMAP1_IO_ADDRESS(pa));
	153	else
233fd64e	154	return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	155	}
	156	EXPORT_SYMBOL(omap_readw);
	157
	158	u32 omap_readl(u32 pa)
	159	{
	160	if (cpu_class_is_omap1())
	161	return __raw_readl(OMAP1_IO_ADDRESS(pa));
	162	else
233fd64e	163	return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	164	}
	165	EXPORT_SYMBOL(omap_readl);
	166
	167	void omap_writeb(u8 v, u32 pa)
	168	{
	169	if (cpu_class_is_omap1())
	170	__raw_writeb(v, OMAP1_IO_ADDRESS(pa));
	171	else
233fd64e	172	__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	173	}
	174	EXPORT_SYMBOL(omap_writeb);
	175
	176	void omap_writew(u16 v, u32 pa)
	177	{
	178	if (cpu_class_is_omap1())
	179	__raw_writew(v, OMAP1_IO_ADDRESS(pa));
	180	else
233fd64e	181	__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	182	}
	183	EXPORT_SYMBOL(omap_writew);
	184
	185	void omap_writel(u32 v, u32 pa)
	186	{
	187	if (cpu_class_is_omap1())
	188	__raw_writel(v, OMAP1_IO_ADDRESS(pa));
	189	else
233fd64e	190	__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
94113260 TL	191	}
94113260 TL	192	EXPORT_SYMBOL(omap_writel);