]> bbs.cooldavid.org Git - net-next-2.6.git/commitdiff
Davinci: configurable pll divider mask
authorCyril Chemparathy <cyril@ti.com>
Wed, 14 Apr 2010 18:44:49 +0000 (14:44 -0400)
committerKevin Hilman <khilman@deeprootsystems.com>
Thu, 6 May 2010 22:02:07 +0000 (15:02 -0700)
This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.

Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
arch/arm/mach-davinci/clock.c
arch/arm/mach-davinci/clock.h

index 5de60ae5790329faf2cb2d0c33191ea35aa3357c..868cb76934997f52d2361a8b79fdcd8ca9cf0441 100644 (file)
@@ -279,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 
        v = __raw_readl(pll->base + clk->div_reg);
        if (v & PLLDIV_EN) {
-               plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+               plldiv = (v & pll->div_ratio_mask) + 1;
                if (plldiv)
                        rate /= plldiv;
        }
@@ -319,7 +319,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
        if (pll->flags & PLL_HAS_PREDIV) {
                prediv = __raw_readl(pll->base + PREDIV);
                if (prediv & PLLDIV_EN)
-                       prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+                       prediv = (prediv & pll->div_ratio_mask) + 1;
                else
                        prediv = 1;
        }
@@ -331,7 +331,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
        if (pll->flags & PLL_HAS_POSTDIV) {
                postdiv = __raw_readl(pll->base + POSTDIV);
                if (postdiv & PLLDIV_EN)
-                       postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+                       postdiv = (postdiv & pll->div_ratio_mask) + 1;
                else
                        postdiv = 1;
        }
@@ -458,6 +458,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
                                clk->recalc = clk_leafclk_recalc;
                }
 
+               if (clk->pll_data && !clk->pll_data->div_ratio_mask)
+                       clk->pll_data->div_ratio_mask = PLLDIV_RATIO_MASK;
+
                if (clk->recalc)
                        clk->rate = clk->recalc(clk);
 
index 53a0f7b901198741a5d8e13d627bcaf513bd8a15..ce260153a717ad1fc6402368e6206c587f075008 100644 (file)
@@ -76,6 +76,7 @@ struct pll_data {
        u32 num;
        u32 flags;
        u32 input_rate;
+       u32 div_ratio_mask;
 };
 #define PLL_HAS_PREDIV          0x01
 #define PLL_HAS_POSTDIV         0x02