]> bbs.cooldavid.org Git - net-next-2.6.git/commitdiff
powerpc/cell: Move CBE_IOPTE_* to <asm/cell-regs.h>
authorGeert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Wed, 29 Jul 2009 02:06:42 +0000 (02:06 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 20 Aug 2009 00:29:26 +0000 (10:29 +1000)
As <asm/iommu.h> doesn't contain any other hardware specific definitions
but only interfaces.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/cell-regs.h
arch/powerpc/include/asm/iommu.h
arch/powerpc/platforms/ps3/mm.c
arch/powerpc/platforms/ps3/system-bus.c
drivers/block/ps3vram.c
drivers/video/ps3fb.c

index fd6fd00434efc04e0e0bffdaeb98d4c9e1aac8dd..fdf64fd259508c94e8e4ab39635d7a4ef27aaa56 100644 (file)
@@ -303,6 +303,17 @@ struct cbe_mic_tm_regs {
 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 
+
+/* Cell page table entries */
+#define CBE_IOPTE_PP_W         0x8000000000000000ul /* protection: write */
+#define CBE_IOPTE_PP_R         0x4000000000000000ul /* protection: read */
+#define CBE_IOPTE_M            0x2000000000000000ul /* coherency required */
+#define CBE_IOPTE_SO_R         0x1000000000000000ul /* ordering: writes */
+#define CBE_IOPTE_SO_RW                0x1800000000000000ul /* ordering: r & w */
+#define CBE_IOPTE_RPN_Mask     0x07fffffffffff000ul /* RPN */
+#define CBE_IOPTE_H            0x0000000000000800ul /* cache hint */
+#define CBE_IOPTE_IOID_Mask    0x00000000000007fful /* ioid */
+
 /* some utility functions to deal with SMT */
 extern u32 cbe_get_hw_thread_id(int cpu);
 extern u32 cbe_cpu_to_node(int cpu);
index 7ead7c16fb7cdb563ee41f0146b16471bf700d7a..7464c0daddd1d02f5f8f66d1df9a26f92bbc7783 100644 (file)
 #define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
 #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
 
-/* Cell page table entries */
-#define CBE_IOPTE_PP_W         0x8000000000000000ul /* protection: write */
-#define CBE_IOPTE_PP_R         0x4000000000000000ul /* protection: read */
-#define CBE_IOPTE_M            0x2000000000000000ul /* coherency required */
-#define CBE_IOPTE_SO_R         0x1000000000000000ul /* ordering: writes */
-#define CBE_IOPTE_SO_RW                0x1800000000000000ul /* ordering: r & w */
-#define CBE_IOPTE_RPN_Mask     0x07fffffffffff000ul /* RPN */
-#define CBE_IOPTE_H            0x0000000000000800ul /* cache hint */
-#define CBE_IOPTE_IOID_Mask    0x00000000000007fful /* ioid */
-
 /* Boot time flags */
 extern int iommu_is_off;
 extern int iommu_force_on;
index 846eb8b57fd1dbb80fca175bb2813e97f0e7ef49..189a25b80735cb7c6731b3ce5d7ab9cd24ca605e 100644 (file)
@@ -23,8 +23,8 @@
 #include <linux/memory_hotplug.h>
 #include <linux/lmb.h>
 
+#include <asm/cell-regs.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
index 3f763c5284acc2e682f0f9a3832159565bf3598b..676f989ed4e411e208cbd8129a57b1bd5843eed8 100644 (file)
@@ -27,7 +27,7 @@
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
+#include <asm/cell-regs.h>
 
 #include "platform.h"
 
index 095f97e6066562671eaad46eed57478aa3bafaf7..c8753a9ed290766c84cf3f7cd9da4b096b789270 100644 (file)
@@ -13,8 +13,8 @@
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
 
+#include <asm/cell-regs.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
 #include <asm/lv1call.h>
 #include <asm/ps3.h>
 #include <asm/ps3gpu.h>
index c0af638fe702441c4095d168f4b464769296274c..9c0144ee7ae516f6d0042127f8acad4279249f46 100644 (file)
@@ -32,7 +32,7 @@
 #include <linux/init.h>
 
 #include <asm/abs_addr.h>
-#include <asm/iommu.h>
+#include <asm/cell-regs.h>
 #include <asm/lv1call.h>
 #include <asm/ps3av.h>
 #include <asm/ps3fb.h>