* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
genirq: Fix up irq_node() for irq_data changes.
genirq: Add single IRQ reservation helper
genirq: Warn if enable_irq is called before irq is set up
* 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
semaphore: Remove mutex emulation
staging: Final semaphore cleanup
jbd2: Convert jbd2_slab_create_sem to mutex
hpfs: Convert sbi->hpfs_creation_de to mutex
Fix up trivial change/delete conflicts with deleted 'dream' drivers
(drivers/staging/dream/camera/{mt9d112.c,mt9p012_fox.c,mt9t013.c,s5k3e2fx.c})
<listitem><para>A simple shell</para></listitem>
<listitem><para>The kdb core command set</para></listitem>
<listitem><para>A registration API to register additional kdb shell commands.</para>
- <para>A good example of a self-contained kdb module is the "ftdump" command for dumping the ftrace buffer. See: kernel/trace/trace_kdb.c</para></listitem>
+ <itemizedlist>
+ <listitem><para>A good example of a self-contained kdb module
+ is the "ftdump" command for dumping the ftrace buffer. See:
+ kernel/trace/trace_kdb.c</para></listitem>
+ <listitem><para>For an example of how to dynamically register
+ a new kdb command you can build the kdb_hello.ko kernel module
+ from samples/kdb/kdb_hello.c. To build this example you can
+ set CONFIG_SAMPLES=y and CONFIG_SAMPLE_KDB=m in your kernel
+ config. Later run "modprobe kdb_hello" and the next time you
+ enter the kdb shell, you can run the "hello"
+ command.</para></listitem>
+ </itemizedlist></listitem>
<listitem><para>The implementation for kdb_printf() which
emits messages directly to I/O drivers, bypassing the kernel
log.</para></listitem>
prototypes:
int (*fl_compare_owner)(struct file_lock *, struct file_lock *);
void (*fl_notify)(struct file_lock *); /* unblock callback */
- void (*fl_copy_lock)(struct file_lock *, struct file_lock *);
void (*fl_release_private)(struct file_lock *);
void (*fl_break)(struct file_lock *); /* break_lease callback */
BKL may block
fl_compare_owner: yes no
fl_notify: yes no
-fl_copy_lock: yes no
fl_release_private: yes yes
fl_break: yes no
endif
# Additional ARCH settings for sparc
+ifeq ($(ARCH),sparc32)
+ SRCARCH := sparc
+endif
ifeq ($(ARCH),sparc64)
SRCARCH := sparc
endif
for kernel debugging, non-intrusive instrumentation and testing.
If in doubt, say "N".
+config JUMP_LABEL
+ bool "Optimize trace point call sites"
+ depends on HAVE_ARCH_JUMP_LABEL
+ help
+ If it is detected that the compiler has support for "asm goto",
+ the kernel will compile trace point locations with just a
+ nop instruction. When trace points are enabled, the nop will
+ be converted to a jump to the trace function. This technique
+ lowers overhead and stress on the branch prediction of the
+ processor.
+
+ On i386, options added to the compiler flags may increase
+ the size of the kernel slightly.
+
config OPTPROBES
def_bool y
depends on KPROBES && HAVE_OPTPROBES
config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select CPU_V7
+ select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select ARM_L1_CACHE_SHIFT_6
+ select ARCH_HAS_CPUFREQ
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
config ARCH_S5PV310
bool "Samsung S5PV310/S5PC210"
select CPU_V7
+ select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
select GENERIC_CLOCKEVENTS
+ select HAVE_S3C_RTC
+ select HAVE_S3C2410_I2C
+ select HAVE_S3C2410_WATCHDOG
help
Samsung S5PV310 series based systems
source "drivers/cpufreq/Kconfig"
+config CPU_FREQ_IMX
+ tristate "CPUfreq driver for i.MX CPUs"
+ depends on ARCH_MXC && CPU_FREQ
+ help
+ This enables the CPUfreq driver for i.MX CPUs.
+
config CPU_FREQ_SA1100
bool
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_EVBUG=m
CONFIG_MOUSE_PS2=m
CONFIG_MOUSE_PS2_ELANTECH=y
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
-#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
-#define L2X0_CACHE_ID_PART_L210 (1 << 6)
-#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
#define L2X0_LINE_DATA 0xF10
#define L2X0_LINE_TAG 0xF30
#define L2X0_DEBUG_CTRL 0xF40
+#define L2X0_PREFETCH_CTRL 0xF60
+#define L2X0_POWER_CTRL 0xF80
+#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
+#define L2X0_STNDBY_MODE_EN (1 << 0)
+
+/* Registers shifts and masks */
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L210 (1 << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
#define _GP_REGS 16
#define _FP_REGS 8
#define _EXTRA_REGS 2
-#define DBG_MAX_REG_NUM (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define GDB_MAX_REGS (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define DBG_MAX_REG_NUM (_GP_REGS + _FP_REGS + _EXTRA_REGS)
#define KGDB_MAX_NO_CPUS 1
#define BUFMAX 400
#define _SPT 13
#define _LR 14
#define _PC 15
-#define _CPSR (DBG_MAX_REG_NUM - 1)
+#define _CPSR (GDB_MAX_REGS - 1)
/*
* So that we can denote the end of a frame for tracing,
#ifndef _ASM_ARM_MEMBLOCK_H
#define _ASM_ARM_MEMBLOCK_H
-#ifdef CONFIG_MMU
-extern phys_addr_t lowmem_end_addr;
-#define MEMBLOCK_REAL_LIMIT lowmem_end_addr
-#else
-#define MEMBLOCK_REAL_LIMIT 0
-#endif
-
struct meminfo;
struct machine_desc;
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
void (*flush_range)(unsigned long, unsigned long);
+ void (*flush_all)(void);
+ void (*inv_all)(void);
+ void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
void (*sync)(void);
#endif
outer_cache.flush_range(start, end);
}
+static inline void outer_flush_all(void)
+{
+ if (outer_cache.flush_all)
+ outer_cache.flush_all();
+}
+
+static inline void outer_inv_all(void)
+{
+ if (outer_cache.inv_all)
+ outer_cache.inv_all();
+}
+
+static inline void outer_disable(void)
+{
+ if (outer_cache.disable)
+ outer_cache.disable();
+}
+
#else
static inline void outer_inv_range(unsigned long start, unsigned long end)
{ }
static inline void outer_flush_range(unsigned long start, unsigned long end)
{ }
+static inline void outer_flush_all(void) { }
+static inline void outer_inv_all(void) { }
+static inline void outer_disable(void) { }
#endif
return;
/* Initialize to zero */
- for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
+ for (regno = 0; regno < GDB_MAX_REGS; regno++)
gdb_regs[regno] = 0;
/* Otherwise, we have only some registers from switch_to() */
local_fiq_disable();
setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
flush_cache_all();
+ outer_flush_all();
+ outer_disable();
cpu_proc_fin();
+ outer_inv_all();
flush_cache_all();
cpu_reset(reboot_code_buffer_phys);
}
*(.rodata.*)
*(.glue_7)
*(.glue_7t)
+ . = ALIGN(4);
*(.got) /* Global offset table */
ARM_CPU_KEEP(PROC_INFO)
}
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
+#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
+#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
+#define SD1_EN_GPIO (GPIO_PORTB + 25)
+
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
+ /* SDHC1 */
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
+static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
+ IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
+}
+
+static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOB(26), data);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+ .init = mx27_3ds_sdhc1_init,
+ .exit = mx27_3ds_sdhc1_exit,
+};
+
+static void mx27_3ds_sdhc1_enable_level_translator(void)
+{
+ /* Turn on TXB0108 OE pin */
+ gpio_request(SD1_EN_GPIO, "sd1_enable");
+ gpio_direction_output(SD1_EN_GPIO, 1);
+}
+
static void __init mx27pdk_init(void)
{
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
+ mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
+ mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
}
static void __init mx27pdk_timer_init(void)
return offset / ticks_per_usec;
}
-static int ixp2000_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
{
/* clear timer 1 */
ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
config ARCH_MSM7X00A
bool "MSM7x00A / MSM7x01A"
+ select MACH_TROUT if !MACH_HALIBUT
select ARCH_MSM_ARM11
select MSM_SMD
select MSM_SMD_PKG3
config ARCH_MSM7X30
bool "MSM7x30"
+ select MACH_MSM7X30_SURF # if !
select ARCH_MSM_SCORPION
select MSM_SMD
select MSM_VIC
select CPU_V7
- select MSM_REMOTE_SPINLOCK_DEKKERS
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_QSD8X50
bool "QSD8X50"
+ select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
select ARCH_MSM_SCORPION
select MSM_SMD
select MSM_VIC
select CPU_V7
- select MSM_REMOTE_SPINLOCK_LDREX
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM8X60
bool "MSM8X60"
+ select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
+ && !MACH_MSM8X60_FFA)
select ARM_GIC
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
- select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
- && !MACH_MSM8X60_FFA)
endchoice
{
mi->nr_banks=1;
mi->bank[0].start = PHYS_OFFSET;
- mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
mi->bank[0].size = (101*1024*1024);
}
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
-#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
+#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
.macro addruart, rp, rv
ldr \rp, =MSM_DEBUG_UART_PHYS
ldr \rv, =MSM_DEBUG_UART_BASE
tst \rd, #0x04
beq 1001b
.endm
+#else
+ .macro addruart, rp, rv
+ mov \rv, #0xff000000
+ orr \rv, \rv, #0x00f00000
+ .endm
- .macro busyuart,rd,rx
+ .macro senduart,rd,rx
+ .endm
+
+ .macro waituart,rd,rx
.endm
#endif
+
+ .macro busyuart,rd,rx
+ .endm
static int msm_iommu_probe(struct platform_device *pdev)
{
- struct resource *r;
+ struct resource *r, *r2;
struct clk *iommu_clk;
struct msm_iommu_drvdata *drvdata;
struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
len = r->end - r->start + 1;
- r = request_mem_region(r->start, len, r->name);
- if (!r) {
+ r2 = request_mem_region(r->start, len, r->name);
+ if (!r2) {
pr_err("Could not request memory region: "
"start=%p, len=%d\n", (void *) r->start, len);
ret = -EBUSY;
goto fail;
}
- regs_base = ioremap(r->start, len);
+ regs_base = ioremap(r2->start, len);
if (!regs_base) {
pr_err("Could not ioremap: start=%p, len=%d\n",
- (void *) r->start, len);
+ (void *) r2->start, len);
ret = -EBUSY;
- goto fail;
+ goto fail_mem;
}
irq = platform_get_irq_byname(pdev, "secure_irq");
if (irq < 0) {
ret = -ENODEV;
- goto fail;
+ goto fail_io;
}
mb();
if (GET_IDR(regs_base) == 0) {
pr_err("Invalid IDR value detected\n");
ret = -ENODEV;
- goto fail;
+ goto fail_io;
}
ret = request_irq(irq, msm_iommu_fault_handler, 0,
"msm_iommu_secure_irpt_handler", drvdata);
if (ret) {
pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
- goto fail;
+ goto fail_io;
}
msm_iommu_reset(regs_base);
return 0;
+fail_io:
+ iounmap(regs_base);
+fail_mem:
+ release_mem_region(r->start, len);
fail:
kfree(drvdata);
return ret;
.rating = 200,
.read = msm_gpt_read,
.mask = CLOCKSOURCE_MASK(32),
- .shift = 24,
+ .shift = 17,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
},
.irq = {
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_ESDHC
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
MX25_PAD_KPP_COL1__KPP_COL1,
MX25_PAD_KPP_COL2__KPP_COL2,
MX25_PAD_KPP_COL3__KPP_COL3,
+
+ /* SD1 */
+ MX25_PAD_SD1_CMD__SD1_CMD,
+ MX25_PAD_SD1_CLK__SD1_CLK,
+ MX25_PAD_SD1_DATA0__SD1_DATA0,
+ MX25_PAD_SD1_DATA1__SD1_DATA1,
+ MX25_PAD_SD1_DATA2__SD1_DATA2,
+ MX25_PAD_SD1_DATA3__SD1_DATA3,
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
+
+ imx25_add_esdhc(0, NULL);
}
static void __init mx25pdk_timer_init(void)
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
+ select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_ESDHC
default n
help
Include support for MX35PDK platform. This includes specific
#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
{
- .start = MMC_SDHC1_BASE_ADDR,
- .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+ .start = MX31_MMC_SDHC1_BASE_ADDR,
+ .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = MXC_INT_MMC_SDHC1,
- .end = MXC_INT_MMC_SDHC1,
+ .start = MX31_INT_MMC_SDHC1,
+ .end = MX31_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxcsdhc1_resources[] = {
{
- .start = MMC_SDHC2_BASE_ADDR,
- .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+ .start = MX31_MMC_SDHC2_BASE_ADDR,
+ .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = MXC_INT_MMC_SDHC2,
- .end = MXC_INT_MMC_SDHC2,
+ .start = MX31_INT_MMC_SDHC2,
+ .end = MX31_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
#include "devices-imx31.h"
#include "devices.h"
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
-
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
-
/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
-
-#define MXC_MAX_EXP_IO_LINES 16
-
/*
* This file contains the board-specific initialization routines.
*/
imx31_add_imx_uart0(&uart_pdata);
imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
- imx31_add_spi_imx0(&spi1_pdata);
+ imx31_add_spi_imx1(&spi1_pdata);
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
mx31_3ds_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
- if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
- printk(KERN_WARNING "Init of the debugboard failed, all "
- "devices on the board are unusable.\n");
+ if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ printk(KERN_WARNING "Init of the debug board failed, all "
+ "devices on the debug board are unusable.\n");
}
static void __init mx31_3ds_timer_init(void)
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
+#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
+
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/* USBH1 */
MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
+ /* SDCARD */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
};
/* OTG config */
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
+ imx35_add_esdhc(0, NULL);
+
+ if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ pr_warn("Init of the debugboard failed, all "
+ "devices on the debugboard are unusable.\n");
}
static void __init mx35pdk_timer_init(void)
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
+ select ARCH_HAS_CPUFREQ
comment "MX5 platforms:"
bool "Support MX51 BABBAGE platforms"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_ESDHC
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
# Object file lists.
obj-y := cpu.o mm.o clock-mx51.o devices.o
+obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
*
* The code contained herein is licensed under the GNU General Public
#include <linux/io.h>
#include <linux/fsl_devices.h>
#include <linux/fec.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include "devices-imx51.h"
#include "devices.h"
+#include "cpu_op-mx51.h"
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
+#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define MX51_USB_PLL_DIV_24_MHZ 0x02
+static struct gpio_keys_button babbage_buttons[] = {
+ {
+ .gpio = BABBAGE_POWER_KEY,
+ .code = BTN_0,
+ .desc = "PWR",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+};
+
+static const struct gpio_keys_platform_data imx_button_data __initconst = {
+ .buttons = babbage_buttons,
+ .nbuttons = ARRAY_SIZE(babbage_buttons),
+};
+
static struct pad_desc mx51babbage_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
/* FEC PHY reset line */
MX51_PAD_EIM_A20__GPIO_2_14,
+
+ /* SD 1 */
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+ /* SD 2 */
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+ MX51_PAD_SD2_DATA1__SD2_DATA1,
+ MX51_PAD_SD2_DATA2__SD2_DATA2,
+ MX51_PAD_SD2_DATA3__SD2_DATA3,
};
/* Serial ports */
static void __init mxc_board_init(void)
{
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+ struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
+#if defined(CONFIG_CPU_FREQ_IMX)
+ get_cpu_op = mx51_get_cpu_op;
+#endif
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
ARRAY_SIZE(mx51babbage_pads));
mxc_init_imx_uart();
babbage_fec_reset();
imx51_add_fec(NULL);
+ /* Set the PAD settings for the pwr key. */
+ power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
+ mxc_iomux_v3_setup_pad(&power_key);
+ imx51_add_gpio_keys(&imx_button_data);
+
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(&usbh1stp);
babbage_usbhub_reset();
+
+ imx51_add_esdhc(0, NULL);
+ imx51_add_esdhc(1, NULL);
}
static void __init mx51_babbage_timer_init(void)
return 0;
}
-static unsigned long clk_arm_get_rate(struct clk *clk)
+static unsigned long clk_cpu_get_rate(struct clk *clk)
{
u32 cacrr, div;
unsigned long parent_rate;
return parent_rate / div;
}
+static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, cpu_podf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+ cpu_podf = parent_rate / rate - 1;
+ /* use post divider to change freq */
+ reg = __raw_readl(MXC_CCM_CACRR);
+ reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+ reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CACRR);
+
+ return 0;
+}
+
static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
static struct clk cpu_clk = {
.parent = &pll1_sw_clk,
- .get_rate = clk_arm_get_rate,
+ .get_rate = clk_cpu_get_rate,
+ .set_rate = clk_cpu_set_rate,
};
static struct clk ahb_clk = {
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
};
static void clk_tree_init(void)
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <mach/hardware.h>
+#include <linux/kernel.h>
+
+static struct cpu_op mx51_cpu_op[] = {
+ {
+ .cpu_rate = 160000000,},
+ {
+ .cpu_rate = 800000000,},
+};
+
+struct cpu_op *mx51_get_cpu_op(int *op)
+{
+ *op = ARRAY_SIZE(mx51_cpu_op);
+ return mx51_cpu_op;
+}
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+extern struct cpu_op *mx51_get_cpu_op(int *op);
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
+#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
+
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
}
#ifdef CONFIG_CACHE_L2X0
+
+static void omap4_l2x0_disable(void)
+{
+ /* Disable PL310 L2 Cache controller */
+ omap_smc1(0x102, 0x0);
+}
+
static int __init omap_l2_cache_init(void)
{
/*
else
l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
+ /*
+ * Override default outer_cache.disable with a OMAP4
+ * specific one
+ */
+ outer_cache.disable = omap4_l2x0_disable;
+
return 0;
}
early_initcall(omap_l2_cache_init);
{
if (on) {
/* Power on the chip */
- h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
+ gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
/* Reset the chip */
mdelay(10);
mdelay(10);
gpio_set_value(S3C2410_GPH(1), 0);
mdelay(10);
- h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
+ gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
}
}
ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
if (ret) {
- dev_err(&pdev->dev, "could not get GPH1\n");\
+ dev_err(&pdev->dev, "could not get GPH1\n");
+ return ret;
+ }
+
+ ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
+ if (ret) {
+ gpio_free(S3C2410_GPH(1));
+ dev_err(&pdev->dev, "could not get BT_POWER\n");
return ret;
}
#ifdef CONFIG_CPU_S3C244X
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
#else
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#endif
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
-#ifdef CONFIG_CPU_S3C24XX
-#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
+#ifdef CONFIG_CPU_S3C244X
+#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
#else
-#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
+#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
#endif
#ifndef __ASM_ARCH_H1940_LATCH_H
#define __ASM_ARCH_H1940_LATCH_H
+#include <mach/gpio.h>
-#ifndef __ASSEMBLY__
-#define H1940_LATCH ((void __force __iomem *)0xF8000000)
-#else
-#define H1940_LATCH 0xF8000000
-#endif
-
-#define H1940_PA_LATCH (S3C2410_CS2)
+#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
/* SD layer latch */
-#define H1940_LATCH_SDQ1 (1<<16)
-#define H1940_LATCH_LCD_P1 (1<<17)
-#define H1940_LATCH_LCD_P2 (1<<18)
-#define H1940_LATCH_LCD_P3 (1<<19)
-#define H1940_LATCH_MAX1698_nSHUTDOWN (1<<20) /* LCD backlight */
-#define H1940_LATCH_LED_RED (1<<21)
-#define H1940_LATCH_SDQ7 (1<<22)
-#define H1940_LATCH_USB_DP (1<<23)
+#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
+#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
+#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
+#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
+#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
+#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
+#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
+#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
/* CPU layer latch */
-#define H1940_LATCH_UDA_POWER (1<<24)
-#define H1940_LATCH_AUDIO_POWER (1<<25)
-#define H1940_LATCH_SM803_ENABLE (1<<26)
-#define H1940_LATCH_LCD_P4 (1<<27)
-#define H1940_LATCH_CPUQ5 (1<<28) /* untraced */
-#define H1940_LATCH_BLUETOOTH_POWER (1<<29) /* active high */
-#define H1940_LATCH_LED_GREEN (1<<30)
-#define H1940_LATCH_LED_FLASH (1<<31)
-
-/* default settings */
-
-#define H1940_LATCH_DEFAULT \
- H1940_LATCH_LCD_P4 | \
- H1940_LATCH_SM803_ENABLE | \
- H1940_LATCH_SDQ1 | \
- H1940_LATCH_LCD_P1 | \
- H1940_LATCH_LCD_P2 | \
- H1940_LATCH_LCD_P3 | \
- H1940_LATCH_MAX1698_nSHUTDOWN | \
- H1940_LATCH_CPUQ5
-
-/* control functions */
-
-extern void h1940_latch_control(unsigned int clear, unsigned int set);
+#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
+#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
+#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
+#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
+#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
+#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
+#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
+#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
#endif /* __ASM_ARCH_H1940_LATCH_H */
#define S3C2443_SCLKCON_UARTCLK (1<<8)
#define S3C2443_SCLKCON_USBHOST (1<<1)
+#define S3C2443_PWRCFG_SLEEP (1<<15)
+
#include <asm/div64.h>
static inline unsigned int
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END 0xE0000000UL
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pwm_backlight.h>
+#include <linux/i2c.h>
#include <video/platform_lcd.h>
#include <linux/mmc/host.h>
#include <plat/mci.h>
#include <plat/ts.h>
+#include <sound/uda1380.h>
+
+#define H1940_LATCH ((void __force __iomem *)0xF8000000)
+
+#define H1940_PA_LATCH S3C2410_CS2
+
+#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
+
static struct map_desc h1940_iodesc[] __initdata = {
[0] = {
.virtual = (unsigned long)H1940_LATCH,
/* Board control latch control */
-static unsigned int latch_state = H1940_LATCH_DEFAULT;
+static unsigned int latch_state;
-void h1940_latch_control(unsigned int clear, unsigned int set)
+static void h1940_latch_control(unsigned int clear, unsigned int set)
{
unsigned long flags;
local_irq_restore(flags);
}
-EXPORT_SYMBOL_GPL(h1940_latch_control);
+static inline int h1940_gpiolib_to_latch(int offset)
+{
+ return 1 << (offset + 16);
+}
+
+static void h1940_gpiolib_latch_set(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ int latch_bit = h1940_gpiolib_to_latch(offset);
+
+ h1940_latch_control(value ? 0 : latch_bit,
+ value ? latch_bit : 0);
+}
+
+static int h1940_gpiolib_latch_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ h1940_gpiolib_latch_set(chip, offset, value);
+ return 0;
+}
+
+static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
+ unsigned offset)
+{
+ return (latch_state >> (offset + 16)) & 1;
+}
+
+struct gpio_chip h1940_latch_gpiochip = {
+ .base = H1940_LATCH_GPIO(0),
+ .owner = THIS_MODULE,
+ .label = "H1940_LATCH",
+ .ngpio = 16,
+ .direction_output = h1940_gpiolib_latch_output,
+ .set = h1940_gpiolib_latch_set,
+ .get = h1940_gpiolib_latch_get,
+};
static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
{
switch (cmd)
{
case S3C2410_UDC_P_ENABLE :
- h1940_latch_control(0, H1940_LATCH_USB_DP);
+ gpio_set_value(H1940_LATCH_USB_DP, 1);
break;
case S3C2410_UDC_P_DISABLE :
- h1940_latch_control(H1940_LATCH_USB_DP, 0);
+ gpio_set_value(H1940_LATCH_USB_DP, 0);
break;
case S3C2410_UDC_P_RESET :
break;
.id = -1,
};
+static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
+{
+ switch (power_mode) {
+ case MMC_POWER_OFF:
+ gpio_set_value(H1940_LATCH_SD_POWER, 0);
+ break;
+ case MMC_POWER_UP:
+ case MMC_POWER_ON:
+ gpio_set_value(H1940_LATCH_SD_POWER, 1);
+ break;
+ default:
+ break;
+ };
+}
+
static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
.gpio_detect = S3C2410_GPF(5),
.gpio_wprotect = S3C2410_GPH(8),
- .set_power = NULL,
+ .set_power = h1940_set_mmc_power,
.ocr_avail = MMC_VDD_32_33,
};
gpio_direction_output(S3C2410_GPB(0), 0);
s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+ gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
return 0;
}
+static int h1940_backlight_notify(struct device *dev, int brightness)
+{
+ if (!brightness) {
+ gpio_direction_output(S3C2410_GPB(0), 1);
+ gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
+ } else {
+ gpio_direction_output(S3C2410_GPB(0), 0);
+ s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+ gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
+ }
+ return brightness;
+}
+
static void h1940_backlight_exit(struct device *dev)
{
gpio_direction_output(S3C2410_GPB(0), 1);
+ gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
}
+
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
/* tcnt = 0x31 */
.pwm_period_ns = 36296,
.init = h1940_backlight_init,
+ .notify = h1940_backlight_notify,
.exit = h1940_backlight_exit,
};
int value;
if (!power) {
- /* set to 3ec */
- gpio_direction_output(S3C2410_GPC(0), 0);
+ gpio_set_value(S3C2410_GPC(0), 0);
/* wait for 3ac */
do {
value = gpio_get_value(S3C2410_GPC(6));
} while (value);
- /* set to 38c */
- gpio_direction_output(S3C2410_GPC(5), 0);
+
+ gpio_set_value(H1940_LATCH_LCD_P2, 0);
+ gpio_set_value(H1940_LATCH_LCD_P3, 0);
+ gpio_set_value(H1940_LATCH_LCD_P4, 0);
+
+ gpio_direction_output(S3C2410_GPC(1), 0);
+ gpio_direction_output(S3C2410_GPC(4), 0);
+
+ gpio_set_value(H1940_LATCH_LCD_P1, 0);
+ gpio_set_value(H1940_LATCH_LCD_P0, 0);
+
+ gpio_set_value(S3C2410_GPC(5), 0);
+
} else {
- /* Set to 3ac */
- gpio_direction_output(S3C2410_GPC(5), 1);
- /* Set to 3ad */
- gpio_direction_output(S3C2410_GPC(0), 1);
+ gpio_set_value(H1940_LATCH_LCD_P0, 1);
+ gpio_set_value(H1940_LATCH_LCD_P1, 1);
+
+ s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2));
+
+ gpio_set_value(S3C2410_GPC(5), 1);
+ gpio_set_value(S3C2410_GPC(0), 1);
+
+ gpio_set_value(H1940_LATCH_LCD_P3, 1);
+ gpio_set_value(H1940_LATCH_LCD_P2, 1);
+ gpio_set_value(H1940_LATCH_LCD_P4, 1);
}
}
.dev.platform_data = &h1940_lcd_power_data,
};
+static struct uda1380_platform_data uda1380_info = {
+ .gpio_power = H1940_LATCH_UDA_POWER,
+ .gpio_reset = S3C2410_GPA(12),
+ .dac_clk = UDA1380_DAC_CLK_SYSCLK,
+};
+
+static struct i2c_board_info h1940_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("uda1380", 0x1a),
+ .platform_data = &uda1380_info,
+ },
+};
+
static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_ohci,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
+ &s3c_device_pcm,
&s3c_device_usbgadget,
&h1940_device_leds,
&h1940_device_bluetooth,
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
s3c_pm_init();
+
+ /* Add latch gpio chip, set latch initial value */
+ h1940_latch_control(0, 0);
+ WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
}
/* H1940 and RX3715 need to reserve this for suspend */
writel(tmp, S3C2410_UPLLCON);
gpio_request(S3C2410_GPC(0), "LCD power");
+ gpio_request(S3C2410_GPC(1), "LCD power");
+ gpio_request(S3C2410_GPC(4), "LCD power");
gpio_request(S3C2410_GPC(5), "LCD power");
gpio_request(S3C2410_GPC(6), "LCD power");
-
+ gpio_request(H1940_LATCH_LCD_P0, "LCD power");
+ gpio_request(H1940_LATCH_LCD_P1, "LCD power");
+ gpio_request(H1940_LATCH_LCD_P2, "LCD power");
+ gpio_request(H1940_LATCH_LCD_P3, "LCD power");
+ gpio_request(H1940_LATCH_LCD_P4, "LCD power");
+ gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power");
+ gpio_direction_output(S3C2410_GPC(0), 0);
+ gpio_direction_output(S3C2410_GPC(1), 0);
+ gpio_direction_output(S3C2410_GPC(4), 0);
+ gpio_direction_output(S3C2410_GPC(5), 0);
gpio_direction_input(S3C2410_GPC(6));
+ gpio_direction_output(H1940_LATCH_LCD_P0, 0);
+ gpio_direction_output(H1940_LATCH_LCD_P1, 0);
+ gpio_direction_output(H1940_LATCH_LCD_P2, 0);
+ gpio_direction_output(H1940_LATCH_LCD_P3, 0);
+ gpio_direction_output(H1940_LATCH_LCD_P4, 0);
+ gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
+
+ gpio_request(H1940_LATCH_USB_DP, "USB pullup");
+ gpio_direction_output(H1940_LATCH_USB_DP, 0);
+
+ gpio_request(H1940_LATCH_SD_POWER, "SD power");
+ gpio_direction_output(H1940_LATCH_SD_POWER, 0);
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
+
+ i2c_register_board_info(0, h1940_i2c_devices,
+ ARRAY_SIZE(h1940_i2c_devices));
}
MACHINE_START(H1940, "IPAQ-H1940")
#include <plat/clock.h>
#include <plat/pm.h>
#include <plat/pll.h>
+#include <plat/nand-core.h>
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
/* rename devices that are s3c2412/s3c2413 specific */
s3c_device_sdi.name = "s3c2412-sdi";
s3c_device_lcd.name = "s3c2412-lcd";
- s3c_device_nand.name = "s3c2412-nand";
+ s3c_nand_setname("s3c2412-nand");
/* alter IRQ of SDI controller */
help
Internal config node for S3C2416 DMA support
+config S3C2416_PM
+ bool
+ help
+ Internal config node to apply S3C2416 power management
+
menu "S3C2416 Machines"
config MACH_SMDK2416
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
+ select S3C2416_PM if PM
help
Say Y here if you are using an SMDK2416
obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
obj-$(CONFIG_CPU_S3C2416) += irq.o
-
+obj-$(CONFIG_S3C2416_PM) += pm.o
#obj-$(CONFIG_S3C2416_DMA) += dma.o
# Machine support
static struct sysdev_driver s3c2416_irq_driver = {
.add = s3c2416_irq_add,
+ .suspend = s3c24xx_irq_suspend,
+ .resume = s3c24xx_irq_resume,
};
static int __init s3c2416_irq_init(void)
--- /dev/null
+/* linux/arch/arm/mach-s3c2416/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S3C2416 - PM support (Based on Ben Dooks' S3C2412 PM support)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/regs-power.h>
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+extern void s3c2412_sleep_enter(void);
+
+static void s3c2416_cpu_suspend(void)
+{
+ flush_cache_all();
+
+ /* enable wakeup sources regardless of battery state */
+ __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
+
+ /* set the mode as sleep, 2BED represents "Go to BED" */
+ __raw_writel(0x2BED, S3C2443_PWRMODE);
+
+ s3c2412_sleep_enter();
+}
+
+static void s3c2416_pm_prepare(void)
+{
+ /*
+ * write the magic value u-boot uses to check for resume into
+ * the INFORM0 register, and ensure INFORM1 is set to the
+ * correct address to resume from.
+ */
+ __raw_writel(0x2BED, S3C2412_INFORM0);
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+}
+
+static int s3c2416_pm_add(struct sys_device *sysdev)
+{
+ pm_cpu_prep = s3c2416_pm_prepare;
+ pm_cpu_sleep = s3c2416_cpu_suspend;
+
+ return 0;
+}
+
+static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+ return 0;
+}
+
+static int s3c2416_pm_resume(struct sys_device *dev)
+{
+ /* unset the return-from-sleep amd inform flags */
+ __raw_writel(0x0, S3C2443_PWRMODE);
+ __raw_writel(0x0, S3C2412_INFORM0);
+ __raw_writel(0x0, S3C2412_INFORM1);
+
+ return 0;
+}
+
+static struct sysdev_driver s3c2416_pm_driver = {
+ .add = s3c2416_pm_add,
+ .suspend = s3c2416_pm_suspend,
+ .resume = s3c2416_pm_resume,
+};
+
+static __init int s3c2416_pm_init(void)
+{
+ return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
+}
+
+arch_initcall(s3c2416_pm_init);
#include <plat/iic-core.h>
#include <plat/fb-core.h>
+#include <plat/nand-core.h>
static struct map_desc s3c2416_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
{
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
- s3c_device_nand.name = "s3c2416-nand";
+ s3c_nand_setname("s3c2412-nand");
}
/* s3c2416_map_io
config CPU_S3C2440
bool
- depends on ARCH_S3C2410
select CPU_ARM920T
select S3C_GPIO_PULL_UP
select S3C2410_CLOCK
config CPU_S3C2442
bool
- depends on ARCH_S3C2410
select CPU_ARM920T
select S3C2410_CLOCK
select S3C2410_GPIO
config CPU_S3C244X
bool
- depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
+ depends on CPU_S3C2440 || CPU_S3C2442
help
Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
config S3C2440_DMA
bool
- depends on ARCH_S3C2410 && CPU_S3C24405B
+ depends on CPU_S3C2440
help
Support for S3C2440 specific DMA code5A
select CPU_S3C2440
select EEPROM_AT24
select LEDS_TRIGGER_BACKLIGHT
- select SND_S3C24XX_SOC_S3C24XX_UDA134X
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
help
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/sysdev.h>
+#include <linux/pda_power.h>
#include <linux/pwm_backlight.h>
#include <linux/pwm.h>
+#include <linux/s3c_adc_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <plat/irq.h>
#include <plat/ts.h>
+#include <sound/uda1380.h>
+
#define LCD_PWM_PERIOD 192960
#define LCD_PWM_DUTY 127353
};
+static int power_supply_init(struct device *dev)
+{
+ return gpio_request(S3C2410_GPF(2), "cable plugged");
+}
+
+static int rx1950_is_ac_online(void)
+{
+ return !gpio_get_value(S3C2410_GPF(2));
+}
+
+static void power_supply_exit(struct device *dev)
+{
+ gpio_free(S3C2410_GPF(2));
+}
+
+static char *rx1950_supplicants[] = {
+ "main-battery"
+};
+
+static struct pda_power_pdata power_supply_info = {
+ .init = power_supply_init,
+ .is_ac_online = rx1950_is_ac_online,
+ .exit = power_supply_exit,
+ .supplied_to = rx1950_supplicants,
+ .num_supplicants = ARRAY_SIZE(rx1950_supplicants),
+};
+
+static struct resource power_supply_resources[] = {
+ [0] = {
+ .name = "ac",
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
+ IORESOURCE_IRQ_HIGHEDGE,
+ .start = IRQ_EINT2,
+ .end = IRQ_EINT2,
+ },
+};
+
+static struct platform_device power_supply = {
+ .name = "pda-power",
+ .id = -1,
+ .dev = {
+ .platform_data =
+ &power_supply_info,
+ },
+ .resource = power_supply_resources,
+ .num_resources = ARRAY_SIZE(power_supply_resources),
+};
+
+static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
+ { .volt = 4100, .cur = 156, .level = 100},
+ { .volt = 4050, .cur = 156, .level = 95},
+ { .volt = 4025, .cur = 141, .level = 90},
+ { .volt = 3995, .cur = 144, .level = 85},
+ { .volt = 3957, .cur = 162, .level = 80},
+ { .volt = 3931, .cur = 147, .level = 75},
+ { .volt = 3902, .cur = 147, .level = 70},
+ { .volt = 3863, .cur = 153, .level = 65},
+ { .volt = 3838, .cur = 150, .level = 60},
+ { .volt = 3800, .cur = 153, .level = 55},
+ { .volt = 3765, .cur = 153, .level = 50},
+ { .volt = 3748, .cur = 172, .level = 45},
+ { .volt = 3740, .cur = 153, .level = 40},
+ { .volt = 3714, .cur = 175, .level = 35},
+ { .volt = 3710, .cur = 156, .level = 30},
+ { .volt = 3963, .cur = 156, .level = 25},
+ { .volt = 3672, .cur = 178, .level = 20},
+ { .volt = 3651, .cur = 178, .level = 15},
+ { .volt = 3629, .cur = 178, .level = 10},
+ { .volt = 3612, .cur = 162, .level = 5},
+ { .volt = 3605, .cur = 162, .level = 0},
+};
+
+static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
+ { .volt = 4200, .cur = 0, .level = 100},
+ { .volt = 4190, .cur = 0, .level = 99},
+ { .volt = 4178, .cur = 0, .level = 95},
+ { .volt = 4110, .cur = 0, .level = 70},
+ { .volt = 4076, .cur = 0, .level = 65},
+ { .volt = 4046, .cur = 0, .level = 60},
+ { .volt = 4021, .cur = 0, .level = 55},
+ { .volt = 3999, .cur = 0, .level = 50},
+ { .volt = 3982, .cur = 0, .level = 45},
+ { .volt = 3965, .cur = 0, .level = 40},
+ { .volt = 3957, .cur = 0, .level = 35},
+ { .volt = 3948, .cur = 0, .level = 30},
+ { .volt = 3936, .cur = 0, .level = 25},
+ { .volt = 3927, .cur = 0, .level = 20},
+ { .volt = 3906, .cur = 0, .level = 15},
+ { .volt = 3880, .cur = 0, .level = 10},
+ { .volt = 3829, .cur = 0, .level = 5},
+ { .volt = 3820, .cur = 0, .level = 0},
+};
+
+int rx1950_bat_init(void)
+{
+ int ret;
+
+ ret = gpio_request(S3C2410_GPJ(2), "rx1950-charger-enable-1");
+ if (ret)
+ goto err_gpio1;
+ ret = gpio_request(S3C2410_GPJ(3), "rx1950-charger-enable-2");
+ if (ret)
+ goto err_gpio2;
+
+ return 0;
+
+err_gpio2:
+ gpio_free(S3C2410_GPJ(2));
+err_gpio1:
+ return ret;
+}
+
+void rx1950_bat_exit(void)
+{
+ gpio_free(S3C2410_GPJ(2));
+ gpio_free(S3C2410_GPJ(3));
+}
+
+void rx1950_enable_charger(void)
+{
+ gpio_direction_output(S3C2410_GPJ(2), 1);
+ gpio_direction_output(S3C2410_GPJ(3), 1);
+}
+
+void rx1950_disable_charger(void)
+{
+ gpio_direction_output(S3C2410_GPJ(2), 0);
+ gpio_direction_output(S3C2410_GPJ(3), 0);
+}
+
+static struct gpio_led rx1950_leds_desc[] = {
+ {
+ .name = "Green",
+ .default_trigger = "main-battery-charging-or-full",
+ .gpio = S3C2410_GPA(6),
+ },
+ {
+ .name = "Red",
+ .default_trigger = "main-battery-full",
+ .gpio = S3C2410_GPA(7),
+ },
+ {
+ .name = "Blue",
+ .default_trigger = "rx1950-acx-mem",
+ .gpio = S3C2410_GPA(11),
+ },
+};
+
+static struct gpio_led_platform_data rx1950_leds_pdata = {
+ .num_leds = ARRAY_SIZE(rx1950_leds_desc),
+ .leds = rx1950_leds_desc,
+};
+
+static struct platform_device rx1950_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &rx1950_leds_pdata,
+ },
+};
+
+static struct s3c_adc_bat_pdata rx1950_bat_cfg = {
+ .init = rx1950_bat_init,
+ .exit = rx1950_bat_exit,
+ .enable_charger = rx1950_enable_charger,
+ .disable_charger = rx1950_disable_charger,
+ .gpio_charge_finished = S3C2410_GPF(3),
+ .lut_noac = bat_lut_noac,
+ .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
+ .lut_acin = bat_lut_acin,
+ .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
+ .volt_channel = 0,
+ .current_channel = 1,
+ .volt_mult = 4235,
+ .current_mult = 2900,
+ .internal_impedance = 200,
+};
+
+static struct platform_device rx1950_battery = {
+ .name = "s3c-adc-battery",
+ .id = -1,
+ .dev = {
+ .parent = &s3c_device_adc.dev,
+ .platform_data = &rx1950_bat_cfg,
+ },
+};
+
static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
.displays = &rx1950_display,
.num_displays = 1,
.dev.platform_data = &rx1950_gpio_keys_data,
};
-static struct s3c2410_platform_i2c rx1950_i2c_data = {
- .flags = 0,
- .slave_addr = 0x42,
- .frequency = 400 * 1000,
- .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+static struct uda1380_platform_data uda1380_info = {
+ .gpio_power = S3C2410_GPJ(0),
+ .gpio_reset = S3C2410_GPD(0),
+ .dac_clk = UDA1380_DAC_CLK_SYSCLK,
+};
+
+static struct i2c_board_info rx1950_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("uda1380", 0x1a),
+ .platform_data = &uda1380_info,
+ },
};
static struct platform_device *rx1950_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
+ &s3c_device_pcm,
&s3c_device_usbgadget,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_timer[1],
&rx1950_backlight,
&rx1950_device_gpiokeys,
+ &power_supply,
+ &rx1950_battery,
+ &rx1950_leds,
};
static struct clk *rx1950_clocks[] __initdata = {
s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
- s3c_i2c0_set_platdata(&rx1950_i2c_data);
+ s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&rx1950_nand_info);
/* Turn off suspend on both USB ports, and switch the
WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
+
+ i2c_register_board_info(0, rx1950_i2c_devices,
+ ARRAY_SIZE(rx1950_i2c_devices));
}
/* H1940 and RX3715 need to reserve this for suspend */
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
+#include <plat/nand-core.h>
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_i2c0.name = "s3c2440-i2c";
- s3c_device_nand.name = "s3c2440-nand";
+ s3c_nand_setname("s3c2440-nand");
s3c_device_ts.name = "s3c2440-ts";
s3c_device_usbgadget.name = "s3c2440-usbgadget";
}
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/fb-core.h>
+#include <plat/nand-core.h>
static struct map_desc s3c2443_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
s3c24xx_reset_hook = s3c2443_hard_reset;
- s3c_device_nand.name = "s3c2412-nand";
+ s3c_nand_setname("s3c2412-nand");
s3c_fb_setname("s3c2443-fb");
/* change WDT IRQ number */
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END (0xe0000000UL)
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
help
Machine support for the A&W6410
+config MACH_MINI6410
+ bool "MINI6410"
+ select CPU_S3C6410
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C64XX_SETUP_SDHCI
+ select S3C_DEV_USB_HOST
+ select S3C_DEV_NAND
+ select S3C_DEV_FB
+ select S3C64XX_SETUP_FB_24BPP
+ select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_TS
+ help
+ Machine support for the FriendlyARM MINI6410
+
config MACH_REAL6410
bool "REAL6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C64XX_SETUP_SDHCI
+ select S3C_DEV_FB
+ select S3C64XX_SETUP_FB_24BPP
+ select S3C_DEV_NAND
+ select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_TS
+ select S3C_DEV_USB_HOST
help
Machine support for the CoreWind REAL6410
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
+obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
obj-$(CONFIG_MACH_HMT) += mach-hmt.o
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
#include <plat/audio.h>
#include <plat/gpio-cfg.h>
-#include <mach/gpio-bank-c.h>
-#include <mach/gpio-bank-d.h>
-#include <mach/gpio-bank-e.h>
-#include <mach/gpio-bank-h.h>
-
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
- s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
+ base = S3C64XX_GPD(0);
break;
case 1:
- s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
- s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
+ base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
return -EINVAL;
}
+ s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
+
return 0;
}
static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
{
- s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
- s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
- s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
- s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
- s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
- s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
- s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
+ s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
}
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
- s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
- s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
+ base = S3C64XX_GPD(0);
break;
case 1:
- s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
- s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
- s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
+ base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
return -EINVAL;
}
+ s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
{
- s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK);
- s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
- s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
- s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
- s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
-
- return 0;
+ return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
}
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{
- s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK);
- s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
- s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
- s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
- s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
-
- return 0;
+ return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s3c64xx_ac97_resource[] = {
.get_pull = s3c_gpio_getpull_updown,
};
-int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
-{
- return IRQ_EINT(0) + pin;
-}
-
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
},
}, {
.base = S3C64XX_GPN_BASE,
+ .irq_base = IRQ_EINT(0),
.config = &gpio_2bit_cfg_eint10,
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
- .to_irq = s3c64xx_gpio2int_gpn,
+ .to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = S3C64XX_GPO_BASE,
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END 0xE0000000UL
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
--- /dev/null
+/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
+ *
+ * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/dm9000.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/serial_core.h>
+#include <linux/types.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
+#include <mach/regs-srom.h>
+#include <mach/s3c6410.h>
+
+#include <plat/adc.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
+#include <plat/regs-serial.h>
+#include <plat/ts.h>
+
+#include <video/platform_lcd.h>
+
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+};
+
+/* DM9000AEP 10/100 ethernet controller */
+
+static struct resource mini6410_dm9k_resource[] = {
+ [0] = {
+ .start = S3C64XX_PA_XM0CSN1,
+ .end = S3C64XX_PA_XM0CSN1 + 1,
+ .flags = IORESOURCE_MEM
+ },
+ [1] = {
+ .start = S3C64XX_PA_XM0CSN1 + 4,
+ .end = S3C64XX_PA_XM0CSN1 + 5,
+ .flags = IORESOURCE_MEM
+ },
+ [2] = {
+ .start = S3C_EINT(7),
+ .end = S3C_EINT(7),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
+ }
+};
+
+static struct dm9000_plat_data mini6410_dm9k_pdata = {
+ .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+};
+
+static struct platform_device mini6410_device_eth = {
+ .name = "dm9000",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
+ .resource = mini6410_dm9k_resource,
+ .dev = {
+ .platform_data = &mini6410_dm9k_pdata,
+ },
+};
+
+static struct mtd_partition mini6410_nand_part[] = {
+ [0] = {
+ .name = "uboot",
+ .size = SZ_1M,
+ .offset = 0,
+ },
+ [1] = {
+ .name = "kernel",
+ .size = SZ_2M,
+ .offset = SZ_1M,
+ },
+ [2] = {
+ .name = "rootfs",
+ .size = MTDPART_SIZ_FULL,
+ .offset = SZ_1M + SZ_2M,
+ },
+};
+
+static struct s3c2410_nand_set mini6410_nand_sets[] = {
+ [0] = {
+ .name = "nand",
+ .nr_chips = 1,
+ .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
+ .partitions = mini6410_nand_part,
+ },
+};
+
+static struct s3c2410_platform_nand mini6410_nand_info = {
+ .tacls = 25,
+ .twrph0 = 55,
+ .twrph1 = 40,
+ .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
+ .sets = mini6410_nand_sets,
+};
+
+static struct s3c_fb_pd_win mini6410_fb_win[] = {
+ {
+ .win_mode = { /* 4.3" 480x272 */
+ .left_margin = 3,
+ .right_margin = 2,
+ .upper_margin = 1,
+ .lower_margin = 1,
+ .hsync_len = 40,
+ .vsync_len = 1,
+ .xres = 480,
+ .yres = 272,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+ }, {
+ .win_mode = { /* 7.0" 800x480 */
+ .left_margin = 8,
+ .right_margin = 13,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+ },
+};
+
+static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
+ .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
+ .win[0] = &mini6410_fb_win[0],
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power)
+ gpio_direction_output(S3C64XX_GPE(0), 1);
+ else
+ gpio_direction_output(S3C64XX_GPE(0), 0);
+}
+
+static struct plat_lcd_data mini6410_lcd_power_data = {
+ .set_power = mini6410_lcd_power_set,
+};
+
+static struct platform_device mini6410_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.parent = &s3c_device_fb.dev,
+ .dev.platform_data = &mini6410_lcd_power_data,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+ .delay = 10000,
+ .presc = 49,
+ .oversampling_shift = 2,
+};
+
+static struct platform_device *mini6410_devices[] __initdata = {
+ &mini6410_device_eth,
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_ohci,
+ &s3c_device_nand,
+ &s3c_device_fb,
+ &mini6410_lcd_powerdev,
+ &s3c_device_adc,
+ &s3c_device_ts,
+};
+
+static void __init mini6410_map_io(void)
+{
+ u32 tmp;
+
+ s3c64xx_init_io(NULL, 0);
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+
+ /* set the LCD type */
+ tmp = __raw_readl(S3C64XX_SPCON);
+ tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+ tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+ __raw_writel(tmp, S3C64XX_SPCON);
+
+ /* remove the LCD bypass */
+ tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+ tmp &= ~MIFPCON_LCD_BYPASS;
+ __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+/*
+ * mini6410_features string
+ *
+ * 0-9 LCD configuration
+ *
+ */
+static char mini6410_features_str[12] __initdata = "0";
+
+static int __init mini6410_features_setup(char *str)
+{
+ if (str)
+ strlcpy(mini6410_features_str, str,
+ sizeof(mini6410_features_str));
+ return 1;
+}
+
+__setup("mini6410=", mini6410_features_setup);
+
+#define FEATURE_SCREEN (1 << 0)
+
+struct mini6410_features_t {
+ int done;
+ int lcd_index;
+};
+
+static void mini6410_parse_features(
+ struct mini6410_features_t *features,
+ const char *features_str)
+{
+ const char *fp = features_str;
+
+ features->done = 0;
+ features->lcd_index = 0;
+
+ while (*fp) {
+ char f = *fp++;
+
+ switch (f) {
+ case '0'...'9': /* tft screen */
+ if (features->done & FEATURE_SCREEN) {
+ printk(KERN_INFO "MINI6410: '%c' ignored, "
+ "screen type already set\n", f);
+ } else {
+ int li = f - '0';
+ if (li >= ARRAY_SIZE(mini6410_fb_win))
+ printk(KERN_INFO "MINI6410: '%c' out "
+ "of range LCD mode\n", f);
+ else {
+ features->lcd_index = li;
+ }
+ }
+ features->done |= FEATURE_SCREEN;
+ break;
+ }
+ }
+}
+
+static void __init mini6410_machine_init(void)
+{
+ u32 cs1;
+ struct mini6410_features_t features = { 0 };
+
+ printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
+ mini6410_features_str);
+
+ /* Parse the feature string */
+ mini6410_parse_features(&features, mini6410_features_str);
+
+ mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
+
+ printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
+ mini6410_lcd_pdata.win[0]->win_mode.xres,
+ mini6410_lcd_pdata.win[0]->win_mode.yres);
+
+ s3c_nand_set_platdata(&mini6410_nand_info);
+ s3c_fb_set_platdata(&mini6410_lcd_pdata);
+ s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+ /* configure nCS1 width to 16 bits */
+
+ cs1 = __raw_readl(S3C64XX_SROM_BW) &
+ ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
+ cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
+ (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
+ (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
+ S3C64XX_SROM_BW__NCS1__SHIFT;
+ __raw_writel(cs1, S3C64XX_SROM_BW);
+
+ /* set timing for nCS1 suitable for ethernet chip */
+
+ __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
+ (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
+ (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
+ (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
+ (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
+ (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
+ (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
+
+ gpio_request(S3C64XX_GPF(15), "LCD power");
+ gpio_request(S3C64XX_GPE(0), "LCD power");
+
+ platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
+}
+
+MACHINE_START(MINI6410, "MINI6410")
+ /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
+ .boot_params = S3C64XX_PA_SDRAM + 0x100,
+ .init_irq = s3c6410_init_irq,
+ .map_io = mini6410_map_io,
+ .init_machine = mini6410_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
*
*/
-#include <linux/kernel.h>
-#include <linux/types.h>
+#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
#include <linux/list.h>
-#include <linux/init.h>
#include <linux/dm9000.h>
-#include <linux/serial_core.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/types.h>
+
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+
#include <mach/map.h>
-#include <mach/s3c6410.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
+#include <mach/s3c6410.h>
+
+#include <plat/adc.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
#include <plat/regs-serial.h>
+#include <plat/ts.h>
+
+#include <video/platform_lcd.h>
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
},
};
+static struct s3c_fb_pd_win real6410_fb_win[] = {
+ {
+ .win_mode = { /* 4.3" 480x272 */
+ .left_margin = 3,
+ .right_margin = 2,
+ .upper_margin = 1,
+ .lower_margin = 1,
+ .hsync_len = 40,
+ .vsync_len = 1,
+ .xres = 480,
+ .yres = 272,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+ }, {
+ .win_mode = { /* 7.0" 800x480 */
+ .left_margin = 8,
+ .right_margin = 13,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+ },
+};
+
+static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
+ .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
+ .win[0] = &real6410_fb_win[0],
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static struct mtd_partition real6410_nand_part[] = {
+ [0] = {
+ .name = "uboot",
+ .size = SZ_1M,
+ .offset = 0,
+ },
+ [1] = {
+ .name = "kernel",
+ .size = SZ_2M,
+ .offset = SZ_1M,
+ },
+ [2] = {
+ .name = "rootfs",
+ .size = MTDPART_SIZ_FULL,
+ .offset = SZ_1M + SZ_2M,
+ },
+};
+
+static struct s3c2410_nand_set real6410_nand_sets[] = {
+ [0] = {
+ .name = "nand",
+ .nr_chips = 1,
+ .nr_partitions = ARRAY_SIZE(real6410_nand_part),
+ .partitions = real6410_nand_part,
+ },
+};
+
+static struct s3c2410_platform_nand real6410_nand_info = {
+ .tacls = 25,
+ .twrph0 = 55,
+ .twrph1 = 40,
+ .nr_sets = ARRAY_SIZE(real6410_nand_sets),
+ .sets = real6410_nand_sets,
+};
+
static struct platform_device *real6410_devices[] __initdata = {
&real6410_device_eth,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
+ &s3c_device_fb,
+ &s3c_device_nand,
+ &s3c_device_adc,
+ &s3c_device_ts,
+ &s3c_device_ohci,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+ .delay = 10000,
+ .presc = 49,
+ .oversampling_shift = 2,
};
static void __init real6410_map_io(void)
{
+ u32 tmp;
+
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+
+ /* set the LCD type */
+ tmp = __raw_readl(S3C64XX_SPCON);
+ tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+ tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+ __raw_writel(tmp, S3C64XX_SPCON);
+
+ /* remove the LCD bypass */
+ tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+ tmp &= ~MIFPCON_LCD_BYPASS;
+ __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+/*
+ * real6410_features string
+ *
+ * 0-9 LCD configuration
+ *
+ */
+static char real6410_features_str[12] __initdata = "0";
+
+static int __init real6410_features_setup(char *str)
+{
+ if (str)
+ strlcpy(real6410_features_str, str,
+ sizeof(real6410_features_str));
+ return 1;
+}
+
+__setup("real6410=", real6410_features_setup);
+
+#define FEATURE_SCREEN (1 << 0)
+
+struct real6410_features_t {
+ int done;
+ int lcd_index;
+};
+
+static void real6410_parse_features(
+ struct real6410_features_t *features,
+ const char *features_str)
+{
+ const char *fp = features_str;
+
+ features->done = 0;
+ features->lcd_index = 0;
+
+ while (*fp) {
+ char f = *fp++;
+
+ switch (f) {
+ case '0'...'9': /* tft screen */
+ if (features->done & FEATURE_SCREEN) {
+ printk(KERN_INFO "REAL6410: '%c' ignored, "
+ "screen type already set\n", f);
+ } else {
+ int li = f - '0';
+ if (li >= ARRAY_SIZE(real6410_fb_win))
+ printk(KERN_INFO "REAL6410: '%c' out "
+ "of range LCD mode\n", f);
+ else {
+ features->lcd_index = li;
+ }
+ }
+ features->done |= FEATURE_SCREEN;
+ break;
+ }
+ }
}
static void __init real6410_machine_init(void)
{
u32 cs1;
+ struct real6410_features_t features = { 0 };
+
+ printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
+ real6410_features_str);
+
+ /* Parse the feature string */
+ real6410_parse_features(&features, real6410_features_str);
+
+ real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
+
+ printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
+ real6410_lcd_pdata.win[0]->win_mode.xres,
+ real6410_lcd_pdata.win[0]->win_mode.yres);
+
+ s3c_fb_set_platdata(&real6410_lcd_pdata);
+ s3c_nand_set_platdata(&real6410_nand_info);
+ s3c24xx_ts_set_platdata(&s3c_ts_platform);
/* configure nCS1 width to 16 bits */
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
+ gpio_request(S3C64XX_GPF(15), "LCD power");
+
platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
}
extern void s3c64xx_fb_gpio_setup_24bpp(void)
{
- unsigned int gpio;
-
- for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
-
- for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
}
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
+#include <plat/ata.h>
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
- u32 gpio = 0;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
- for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
- for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+ s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
- for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+ s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
+#include <plat/keypad.h>
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
- unsigned int gpio;
- unsigned int end;
-
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
- end = S3C64XX_GPK(8 + rows);
- for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
- end = S3C64XX_GPL(0 + cols);
- for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
}
void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- unsigned int end;
- end = S3C64XX_GPG(2 + width);
-
- /* Set all the necessary GPG pins to special-function 0 */
- for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ /* Set all the necessary GPG pins to special-function 2 */
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- unsigned int end;
- end = S3C64XX_GPH(2 + width);
-
- /* Set all the necessary GPG pins to special-function 0 */
- for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ /* Set all the necessary GPH pins to special-function 2 */
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
- unsigned int gpio;
- unsigned int end;
+ /* Set all the necessary GPH pins to special-function 3 */
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
- end = S3C64XX_GPH(6 + width);
-
- /* Set all the necessary GPH pins to special-function 1 */
- for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
-
- /* Set all the necessary GPC pins to special-function 1 */
- for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ /* Set all the necessary GPC pins to special-function 3 */
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
}
config CPU_S5P6442
bool
- select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6442 CPU support
.parent = &clk_hclkd1,
};
+int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
+}
+
int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
clk_pclkd1.rate = pclkd1;
}
+static struct clk init_clocks_disable[] = {
+ {
+ .name = "pdma",
+ .id = -1,
+ .parent = &clk_pclkd1,
+ .enable = s5p6442_clk_ip0_ctrl,
+ .ctrlbit = (1 << 3),
+ },
+};
+
static struct clk init_clocks[] = {
{
.name = "systimer",
void __init s5p6442_register_clocks(void)
{
+ struct clk *clkptr;
+ int i, ret;
+
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+ clkptr = init_clocks_disable;
+ for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
+ ret = s3c24xx_register_clock(clkptr);
+ if (ret < 0) {
+ printk(KERN_ERR "Fail to register clock %s (%d)\n",
+ clkptr->name, ret);
+ } else
+ (clkptr->enable)(clkptr, 0);
+ }
+
s3c_pwmclk_init();
}
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
+ unsigned int base;
+
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
- s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
+ base = S5P6442_GPC1(0);
break;
case -1:
- s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
+ base = S5P6442_GPC0(0);
break;
default:
return -EINVAL;
}
+ s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
+ base = S5P6442_GPC0(0);
break;
case 1:
- s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
+ base = S5P6442_GPC1(0);
break;
default:
return -EINVAL;
}
+ s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
break;
default:
static struct platform_device s5p6442_device_pdma = {
.name = "s3c-pl330",
- .id = 1,
+ .id = -1,
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
.resource = s5p6442_pdma_resource,
.dev = {
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
+#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
/* CLK_OUT */
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END 0xE0000000UL
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
config CPU_S5P6440
bool
- select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6440 CPU support
config CPU_S5P6450
bool
- select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6450 CPU support
__raw_writel(epll_con, S5P64X0_EPLL_CON);
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+ printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+ clk->rate, rate);
+
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6440_epll_ops = {
- .get_rate = s5p64x0_epll_get_rate,
+ .get_rate = s5p_epll_get_rate,
.set_rate = s5p6440_epll_set_rate,
};
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8),
+ }, {
+ .name = "pdma",
+ .id = -1,
+ .parent = &clk_hclk_low.clk,
+ .enable = s5p64x0_hclk0_ctrl,
+ .ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
- }, {
- .name = "dma",
- .id = -1,
- .parent = &clk_hclk_low.clk,
- .enable = s5p64x0_hclk0_ctrl,
- .ctrlbit = (1 << 12),
}, {
.name = "uart",
.id = 0,
/* Set S5P6440 functions for clk_fout_epll */
- clk_fout_epll.enable = s5p64x0_epll_enable;
+ clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
__raw_writel(epll_con, S5P64X0_EPLL_CON);
__raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
+ printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+ clk->rate, rate);
+
clk->rate = rate;
return 0;
}
static struct clk_ops s5p6450_epll_ops = {
- .get_rate = s5p64x0_epll_get_rate,
+ .get_rate = s5p_epll_get_rate,
.set_rate = s5p6450_epll_set_rate,
};
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
+ }, {
+ .name = "pdma",
+ .id = -1,
+ .parent = &clk_hclk_low.clk,
+ .enable = s5p64x0_hclk0_ctrl,
+ .ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
- }, {
- .name = "dma",
- .id = -1,
- .parent = &clk_hclk_low.clk,
- .enable = s5p64x0_hclk0_ctrl,
- .ctrlbit = (1 << 12),
}, {
.name = "uart",
.id = 0,
/* Set S5P6450 functions for clk_fout_epll */
- clk_fout_epll.enable = s5p64x0_epll_enable;
+ clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5p6450_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
{L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
};
-int s5p64x0_epll_enable(struct clk *clk, int enable)
-{
- unsigned int ctrlbit = clk->ctrlbit;
- unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
-
- if (enable)
- __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
- else
- __raw_writel(epll_con, S5P64X0_EPLL_CON);
-
- return 0;
-}
-
-unsigned long s5p64x0_epll_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
- s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));
break;
default:
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
+
break;
default:
{
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
break;
default:
*/
static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+ base = S5P6440_GPC(0);
break;
case 1:
- s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+ base = S5P6440_GPC(4);
break;
default:
return -EINVAL;
}
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
return 0;
}
static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
+ base = S5P6450_GPC(0);
break;
case 1:
- s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
+ base = S5P6450_GPC(4);
break;
default:
return -EINVAL;
}
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
return 0;
}
static struct platform_device s5p64x0_device_pdma = {
.name = "s3c-pl330",
- .id = 0,
+ .id = -1,
.num_resources = ARRAY_SIZE(s5p64x0_pdma_resource),
.resource = s5p64x0_pdma_resource,
.dev = {
#define ARM_DIV_RATIO_SHIFT 0
#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
+#define S5P_EPLL_CON S5P64X0_EPLL_CON
+
#endif /* __ASM_ARCH_REGS_CLOCK_H */
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END 0xE0000000UL
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
- s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
- s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
+ S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
}
void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
- s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
- s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
+ S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
config CPU_S5PC100
bool
- select PLAT_S5P
select S5P_EXT_INT
select S3C_PL330_DMA
help
# Core support for S5PC100 system
-obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o
+obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o
obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
obj-$(CONFIG_CPU_S5PC100) += dma.o
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
};
-static int s5pc100_epll_enable(struct clk *clk, int enable)
-{
- unsigned int ctrlbit = clk->ctrlbit;
- unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
- if (enable)
- __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
- else
- __raw_writel(epll_con, S5P_EPLL_CON);
-
- return 0;
-}
-
-static unsigned long s5pc100_epll_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
static u32 epll_div[][4] = {
{ 32750000, 131, 3, 4 },
{ 32768000, 131, 3, 4 },
__raw_writel(epll_con, S5P_EPLL_CON);
+ printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+ clk->rate, rate);
+
clk->rate = rate;
return 0;
}
static struct clk_ops s5pc100_epll_ops = {
- .get_rate = s5pc100_epll_get_rate,
+ .get_rate = s5p_epll_get_rate,
.set_rate = s5pc100_epll_set_rate,
};
}, {
.name = "iis",
.id = 0,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
.id = 1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
.id = 2,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "ac97",
.id = -1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pcm",
.id = 0,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "pcm",
.id = 1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spdif",
.id = -1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
.id = -1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "keypad",
.id = -1,
- .parent = &clk_div_d1_bus.clk,
+ .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
.nr_sources = ARRAY_SIZE(clk_src_group3_list),
};
+static struct clksrc_clk clk_sclk_audio0 = {
+ .clk = {
+ .name = "sclk_audio",
+ .id = 0,
+ .ctrlbit = (1 << 8),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_group3,
+ .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
static struct clk *clk_src_group4_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_div_mpll.clk,
.nr_sources = ARRAY_SIZE(clk_src_group4_list),
};
+static struct clksrc_clk clk_sclk_audio1 = {
+ .clk = {
+ .name = "sclk_audio",
+ .id = 1,
+ .ctrlbit = (1 << 9),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_group4,
+ .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+};
+
static struct clk *clk_src_group5_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_div_mpll.clk,
.nr_sources = ARRAY_SIZE(clk_src_group5_list),
};
+static struct clksrc_clk clk_sclk_audio2 = {
+ .clk = {
+ .name = "sclk_audio",
+ .id = 2,
+ .ctrlbit = (1 << 10),
+ .enable = s5pc100_sclk1_ctrl,
+ },
+ .sources = &clk_src_group5,
+ .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
+ .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+};
+
static struct clk *clk_src_group6_list[] = {
[0] = &s5p_clk_27m,
[1] = &clk_vclk54m,
.nr_sources = ARRAY_SIZE(clk_src_pwi_list),
};
+static struct clk *clk_sclk_spdif_list[] = {
+ [0] = &clk_sclk_audio0.clk,
+ [1] = &clk_sclk_audio1.clk,
+ [2] = &clk_sclk_audio2.clk,
+};
+
+struct clksrc_sources clk_src_sclk_spdif = {
+ .sources = clk_sclk_spdif_list,
+ .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
+};
+
+static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *pclk;
+ int ret;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ ret = pclk->ops->set_rate(pclk, rate);
+ clk_put(pclk);
+
+ return ret;
+}
+
+static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
+{
+ struct clk *pclk;
+ int rate;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ rate = pclk->ops->get_rate(clk);
+ clk_put(pclk);
+
+ return rate;
+}
+
+static struct clk_ops s5pc100_sclk_spdif_ops = {
+ .set_rate = s5pc100_spdif_set_rate,
+ .get_rate = s5pc100_spdif_get_rate,
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+ .clk = {
+ .name = "sclk_spdif",
+ .id = -1,
+ .ctrlbit = (1 << 11),
+ .enable = s5pc100_sclk1_ctrl,
+ .ops = &s5pc100_sclk_spdif_ops,
+ },
+ .sources = &clk_src_sclk_spdif,
+ .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
+};
+
static struct clksrc_clk clksrcs[] = {
{
.clk = {
},
.sources = &clk_src_group6,
.reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
- }, {
- .clk = {
- .name = "sclk_audio",
- .id = 0,
- .ctrlbit = (1 << 8),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_group3,
- .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_audio",
- .id = 1,
- .ctrlbit = (1 << 9),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_group4,
- .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_audio",
- .id = 2,
- .ctrlbit = (1 << 10),
- .enable = s5pc100_sclk1_ctrl,
-
- },
- .sources = &clk_src_group5,
- .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
- .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_lcd",
&clk_div_pclkd1,
&clk_div_cam,
&clk_div_hdmi,
+ &clk_sclk_audio0,
+ &clk_sclk_audio1,
+ &clk_sclk_audio2,
+ &clk_sclk_spdif,
};
void __init_or_cpufreq s5pc100_setup_clocks(void)
unsigned int ptr;
/* Set S5PC100 functions for clk_fout_epll */
- clk_fout_epll.enable = s5pc100_epll_enable;
+ clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5pc100_epll_ops;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
- s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
- s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
+ s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
break;
case -1: /* Dedicated pins */
{
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
- s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
+ s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
break;
case 1:
- s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
+ s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
break;
default:
static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
{
- s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
-
- return 0;
+ return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s5pc100_ac97_resource[] = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
+
+/* S/PDIF Controller platform_device */
+static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
+{
+ s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
+
+ return 0;
+}
+
+static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
+{
+ s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
+
+ return 0;
+}
+
+static struct resource s5pc100_spdif_resource[] = {
+ [0] = {
+ .start = S5PC100_PA_SPDIF,
+ .end = S5PC100_PA_SPDIF + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = DMACH_SPDIF,
+ .end = DMACH_SPDIF,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct s3c_audio_pdata s5p_spdif_pdata = {
+ .cfg_gpio = s5pc100_spdif_cfg_gpd,
+};
+
+static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_spdif = {
+ .name = "samsung-spdif",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5pc100_spdif_resource),
+ .resource = s5pc100_spdif_resource,
+ .dev = {
+ .platform_data = &s5p_spdif_pdata,
+ .dma_mask = &s5pc100_spdif_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init s5pc100_spdif_setup_gpio(int gpio)
+{
+ if (gpio == S5PC100_SPDIF_GPD)
+ s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
+ else
+ s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
+}
{
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
break;
case 1:
- s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
break;
case 2:
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
break;
default:
static struct platform_device s5pc100_device_pdma0 = {
.name = "s3c-pl330",
- .id = 1,
+ .id = 0,
.num_resources = ARRAY_SIZE(s5pc100_pdma0_resource),
.resource = s5pc100_pdma0_resource,
.dev = {
static struct platform_device s5pc100_device_pdma1 = {
.name = "s3c-pl330",
- .id = 2,
+ .id = 1,
.num_resources = ARRAY_SIZE(s5pc100_pdma1_resource),
.resource = s5pc100_pdma1_resource,
.dev = {
-/*
- * arch/arm/plat-s5pc100/gpiolib.c
+/* linux/arch/arm/mach-s5pc100/gpiolib.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
*
* Copyright 2009 Samsung Electronics Co
* Kyungmin Park <kyungmin.park@samsung.com>
* L3 8 4Bit None
*/
-static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
- return S3C_IRQ_GPIO(chip->base + offset);
-}
-
-static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
- int base;
-
- base = chip->base - S5PC100_GPH0(0);
- if (base == 0)
- return IRQ_EINT(offset);
- base = chip->base - S5PC100_GPH1(0);
- if (base == 0)
- return IRQ_EINT(8 + offset);
- base = chip->base - S5PC100_GPH2(0);
- if (base == 0)
- return IRQ_EINT(16 + offset);
- base = chip->base - S5PC100_GPH3(0);
- if (base == 0)
- return IRQ_EINT(24 + offset);
- return -EINVAL;
-}
-
static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
+/*
+ * GPIO bank's base address given the index of the bank in the
+ * list of all gpio banks.
+ */
+#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
+
+/*
+ * Following are the gpio banks in S5PC100.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
{
- .base = S5PC100_GPA0_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPA0(0),
.ngpio = S5PC100_GPIO_A0_NR,
.label = "GPA0",
},
}, {
- .base = S5PC100_GPA1_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPA1(0),
.ngpio = S5PC100_GPIO_A1_NR,
.label = "GPA1",
},
}, {
- .base = S5PC100_GPB_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPB(0),
.ngpio = S5PC100_GPIO_B_NR,
.label = "GPB",
},
}, {
- .base = S5PC100_GPC_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPC(0),
.ngpio = S5PC100_GPIO_C_NR,
.label = "GPC",
},
}, {
- .base = S5PC100_GPD_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPD(0),
.ngpio = S5PC100_GPIO_D_NR,
.label = "GPD",
},
}, {
- .base = S5PC100_GPE0_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPE0(0),
.ngpio = S5PC100_GPIO_E0_NR,
.label = "GPE0",
},
}, {
- .base = S5PC100_GPE1_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPE1(0),
.ngpio = S5PC100_GPIO_E1_NR,
.label = "GPE1",
},
}, {
- .base = S5PC100_GPF0_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF0(0),
.ngpio = S5PC100_GPIO_F0_NR,
.label = "GPF0",
},
}, {
- .base = S5PC100_GPF1_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF1(0),
.ngpio = S5PC100_GPIO_F1_NR,
.label = "GPF1",
},
}, {
- .base = S5PC100_GPF2_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF2(0),
.ngpio = S5PC100_GPIO_F2_NR,
.label = "GPF2",
},
}, {
- .base = S5PC100_GPF3_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF3(0),
.ngpio = S5PC100_GPIO_F3_NR,
.label = "GPF3",
},
}, {
- .base = S5PC100_GPG0_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG0(0),
.ngpio = S5PC100_GPIO_G0_NR,
.label = "GPG0",
},
}, {
- .base = S5PC100_GPG1_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG1(0),
.ngpio = S5PC100_GPIO_G1_NR,
.label = "GPG1",
},
}, {
- .base = S5PC100_GPG2_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG2(0),
.ngpio = S5PC100_GPIO_G2_NR,
.label = "GPG2",
},
}, {
- .base = S5PC100_GPG3_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG3(0),
.ngpio = S5PC100_GPIO_G3_NR,
.label = "GPG3",
},
}, {
- .base = S5PC100_GPH0_BASE,
- .config = &gpio_cfg_eint,
- .chip = {
- .base = S5PC100_GPH0(0),
- .ngpio = S5PC100_GPIO_H0_NR,
- .label = "GPH0",
- },
- }, {
- .base = S5PC100_GPH1_BASE,
- .config = &gpio_cfg_eint,
- .chip = {
- .base = S5PC100_GPH1(0),
- .ngpio = S5PC100_GPIO_H1_NR,
- .label = "GPH1",
- },
- }, {
- .base = S5PC100_GPH2_BASE,
- .config = &gpio_cfg_eint,
- .chip = {
- .base = S5PC100_GPH2(0),
- .ngpio = S5PC100_GPIO_H2_NR,
- .label = "GPH2",
- },
- }, {
- .base = S5PC100_GPH3_BASE,
- .config = &gpio_cfg_eint,
- .chip = {
- .base = S5PC100_GPH3(0),
- .ngpio = S5PC100_GPIO_H3_NR,
- .label = "GPH3",
- },
- }, {
- .base = S5PC100_GPI_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPI(0),
.ngpio = S5PC100_GPIO_I_NR,
.label = "GPI",
},
}, {
- .base = S5PC100_GPJ0_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ0(0),
.ngpio = S5PC100_GPIO_J0_NR,
.label = "GPJ0",
},
}, {
- .base = S5PC100_GPJ1_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ1(0),
.ngpio = S5PC100_GPIO_J1_NR,
.label = "GPJ1",
},
}, {
- .base = S5PC100_GPJ2_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ2(0),
.ngpio = S5PC100_GPIO_J2_NR,
.label = "GPJ2",
},
}, {
- .base = S5PC100_GPJ3_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ3(0),
.ngpio = S5PC100_GPIO_J3_NR,
.label = "GPJ3",
},
}, {
- .base = S5PC100_GPJ4_BASE,
- .config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ4(0),
.ngpio = S5PC100_GPIO_J4_NR,
.label = "GPJ4",
},
}, {
- .base = S5PC100_GPK0_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK0(0),
.label = "GPK0",
},
}, {
- .base = S5PC100_GPK1_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK1(0),
.label = "GPK1",
},
}, {
- .base = S5PC100_GPK2_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK2(0),
.label = "GPK2",
},
}, {
- .base = S5PC100_GPK3_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK3(0),
.label = "GPK3",
},
}, {
- .base = S5PC100_GPL0_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL0(0),
.label = "GPL0",
},
}, {
- .base = S5PC100_GPL1_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL1(0),
.label = "GPL1",
},
}, {
- .base = S5PC100_GPL2_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL2(0),
.label = "GPL2",
},
}, {
- .base = S5PC100_GPL3_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL3(0),
.label = "GPL3",
},
}, {
- .base = S5PC100_GPL4_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL4(0),
.ngpio = S5PC100_GPIO_L4_NR,
.label = "GPL4",
},
+ }, {
+ .base = (S5P_VA_GPIO + 0xC00),
+ .config = &gpio_cfg_eint,
+ .irq_base = IRQ_EINT(0),
+ .chip = {
+ .base = S5PC100_GPH0(0),
+ .ngpio = S5PC100_GPIO_H0_NR,
+ .label = "GPH0",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO + 0xC20),
+ .config = &gpio_cfg_eint,
+ .irq_base = IRQ_EINT(8),
+ .chip = {
+ .base = S5PC100_GPH1(0),
+ .ngpio = S5PC100_GPIO_H1_NR,
+ .label = "GPH1",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO + 0xC40),
+ .config = &gpio_cfg_eint,
+ .irq_base = IRQ_EINT(16),
+ .chip = {
+ .base = S5PC100_GPH2(0),
+ .ngpio = S5PC100_GPIO_H2_NR,
+ .label = "GPH2",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO + 0xC60),
+ .config = &gpio_cfg_eint,
+ .irq_base = IRQ_EINT(24),
+ .chip = {
+ .base = S5PC100_GPH3(0),
+ .ngpio = S5PC100_GPIO_H3_NR,
+ .label = "GPH3",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
},
};
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc100_gpioint;
-extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+static __init int s5pc100_gpiolib_init(void)
{
- /* Interrupt */
- if (chip->config == &gpio_cfg) {
- int i, irq;
-
- chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+ struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
+ int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+ int gpioint_group = 0;
+ int i;
- for (i = 0; i < chip->chip.ngpio; i++) {
- irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
- set_irq_chip(irq, &s5pc100_gpioint);
- set_irq_data(irq, &chip->chip);
- set_irq_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
+ for (i = 0; i < nr_chips; i++, chip++) {
+ if (chip->config == NULL) {
+ chip->config = &gpio_cfg;
+ chip->group = gpioint_group++;
}
- } else if (chip->config == &gpio_cfg_eint) {
- chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+ if (chip->base == NULL)
+ chip->base = S5PC100_BANK_BASE(i);
}
-}
-
-static __init int s5pc100_gpiolib_init(void)
-{
- struct s3c_gpio_chip *chip;
- int nr_chips;
-
- chip = s5pc100_gpio_chips;
- nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
-
- for (; nr_chips > 0; nr_chips--, chip++)
- s5pc100_gpiolib_link(chip);
-
- samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
- ARRAY_SIZE(s5pc100_gpio_chips));
- /* Interrupt */
- set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
+ samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
return 0;
}
/* define the number of gpios we need to the one after the MP04() range */
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
-#define EINT_MODE S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x) S5PC100_GPH0(x)
-#define EINT_GPIO_1(x) S5PC100_GPH1(x)
-#define EINT_GPIO_2(x) S5PC100_GPH2(x)
-#define EINT_GPIO_3(x) S5PC100_GPH3(x)
-
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
#define IRQ_IRDA S5P_IRQ_VIC1(18)
-#define IRQ_CAN0 S5P_IRQ_VIC1(19)
-#define IRQ_CAN1 S5P_IRQ_VIC1(20)
+#define IRQ_IIC2 S5P_IRQ_VIC1(19)
+#define IRQ_IIC3 S5P_IRQ_VIC1(20)
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
#define IRQ_HSITX S5P_IRQ_VIC1(22)
#define IRQ_UHOST S5P_IRQ_VIC1(23)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
-#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
+/* GPIO interrupt */
+#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
+#define S5P_GPIOINT_GROUP_MAXNR 21
-/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
-#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
+/* Set the default NR_IRQS */
+#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
/* Compatibility */
#define IRQ_LCD_FIFO IRQ_LCD0
#define S5PC100_PA_PCM0 0xF2400000
#define S5PC100_PA_PCM1 0xF2500000
+#define S5PC100_PA_SPDIF 0xF2600000
+
#define S5PC100_PA_TSADC (0xF3000000)
/* KEYPAD */
#include <mach/map.h>
-/* S5PC100 */
-#define S5PC100_GPIO_BASE S5P_VA_GPIO
-#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
-#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
-#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
-#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
-#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
-#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
-#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
-#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
-#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
-#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
-#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
-#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
-#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
-#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
-#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
-#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
-#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
-#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
-#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
-#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
-#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
-#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
-#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
-#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
-#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
-#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
-#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
-#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
-#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
-#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
-#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
-#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
-#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
-#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
-
#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
-/* values for S5P_EXTINT0 */
-#define S5P_EXTINT_LOWLEV (0x00)
-#define S5P_EXTINT_HILEV (0x01)
-#define S5P_EXTINT_FALLEDGE (0x02)
-#define S5P_EXTINT_RISEEDGE (0x03)
-#define S5P_EXTINT_BOTHEDGE (0x04)
+#define EINT_MODE S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x) S5PC100_GPH0(x)
+#define EINT_GPIO_1(x) S5PC100_GPH1(x)
+#define EINT_GPIO_2(x) S5PC100_GPH2(x)
+#define EINT_GPIO_3(x) S5PC100_GPH3(x)
#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END (0xe0000000UL)
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
+++ /dev/null
-/*
- * arch/arm/mach-s5pc100/irq-gpio.c
- *
- * Copyright (C) 2009 Samsung Electronics
- *
- * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <plat/gpio-cfg.h>
-
-#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
-
-#define CON_OFFSET 0x700
-#define MASK_OFFSET 0x900
-#define PEND_OFFSET 0xA00
-#define CON_OFFSET_2 0xE00
-#define MASK_OFFSET_2 0xF00
-#define PEND_OFFSET_2 0xF40
-
-#define GPIOINT_LEVEL_LOW 0x0
-#define GPIOINT_LEVEL_HIGH 0x1
-#define GPIOINT_EDGE_FALLING 0x2
-#define GPIOINT_EDGE_RISING 0x3
-#define GPIOINT_EDGE_BOTH 0x4
-
-static int group_to_con_offset(int group)
-{
- return group << 2;
-}
-
-static int group_to_mask_offset(int group)
-{
- return group << 2;
-}
-
-static int group_to_pend_offset(int group)
-{
- return group << 2;
-}
-
-static int s5pc100_get_start(unsigned int group)
-{
- switch (group) {
- case 0: return S5PC100_GPIO_A0_START;
- case 1: return S5PC100_GPIO_A1_START;
- case 2: return S5PC100_GPIO_B_START;
- case 3: return S5PC100_GPIO_C_START;
- case 4: return S5PC100_GPIO_D_START;
- case 5: return S5PC100_GPIO_E0_START;
- case 6: return S5PC100_GPIO_E1_START;
- case 7: return S5PC100_GPIO_F0_START;
- case 8: return S5PC100_GPIO_F1_START;
- case 9: return S5PC100_GPIO_F2_START;
- case 10: return S5PC100_GPIO_F3_START;
- case 11: return S5PC100_GPIO_G0_START;
- case 12: return S5PC100_GPIO_G1_START;
- case 13: return S5PC100_GPIO_G2_START;
- case 14: return S5PC100_GPIO_G3_START;
- case 15: return S5PC100_GPIO_I_START;
- case 16: return S5PC100_GPIO_J0_START;
- case 17: return S5PC100_GPIO_J1_START;
- case 18: return S5PC100_GPIO_J2_START;
- case 19: return S5PC100_GPIO_J3_START;
- case 20: return S5PC100_GPIO_J4_START;
- default:
- BUG();
- }
-
- return -EINVAL;
-}
-
-static int s5pc100_get_group(unsigned int irq)
-{
- irq -= S3C_IRQ_GPIO(0);
-
- switch (irq) {
- case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
- return 0;
- case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
- return 1;
- case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
- return 2;
- case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
- return 3;
- case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
- return 4;
- case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
- return 5;
- case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
- return 6;
- case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
- return 7;
- case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
- return 8;
- case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
- return 9;
- case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
- return 10;
- case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
- return 11;
- case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
- return 12;
- case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
- return 13;
- case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
- return 14;
- case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
- return 15;
- case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
- return 16;
- case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
- return 17;
- case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
- return 18;
- case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
- return 19;
- case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
- return 20;
- default:
- BUG();
- }
-
- return -EINVAL;
-}
-
-static int s5pc100_get_offset(unsigned int irq)
-{
- struct gpio_chip *chip = get_irq_data(irq);
- return irq - S3C_IRQ_GPIO(chip->base);
-}
-
-static void s5pc100_gpioint_ack(unsigned int irq)
-{
- int group, offset, pend_offset;
- unsigned int value;
-
- group = s5pc100_get_group(irq);
- offset = s5pc100_get_offset(irq);
- pend_offset = group_to_pend_offset(group);
-
- value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
- value |= 1 << offset;
- __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-}
-
-static void s5pc100_gpioint_mask(unsigned int irq)
-{
- int group, offset, mask_offset;
- unsigned int value;
-
- group = s5pc100_get_group(irq);
- offset = s5pc100_get_offset(irq);
- mask_offset = group_to_mask_offset(group);
-
- value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
- value |= 1 << offset;
- __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_unmask(unsigned int irq)
-{
- int group, offset, mask_offset;
- unsigned int value;
-
- group = s5pc100_get_group(irq);
- offset = s5pc100_get_offset(irq);
- mask_offset = group_to_mask_offset(group);
-
- value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
- value &= ~(1 << offset);
- __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_mask_ack(unsigned int irq)
-{
- s5pc100_gpioint_mask(irq);
- s5pc100_gpioint_ack(irq);
-}
-
-static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
-{
- int group, offset, con_offset;
- unsigned int value;
-
- group = s5pc100_get_group(irq);
- offset = s5pc100_get_offset(irq);
- con_offset = group_to_con_offset(group);
-
- switch (type) {
- case IRQ_TYPE_NONE:
- printk(KERN_WARNING "No irq type\n");
- return -EINVAL;
- case IRQ_TYPE_EDGE_RISING:
- type = GPIOINT_EDGE_RISING;
- break;
- case IRQ_TYPE_EDGE_FALLING:
- type = GPIOINT_EDGE_FALLING;
- break;
- case IRQ_TYPE_EDGE_BOTH:
- type = GPIOINT_EDGE_BOTH;
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- type = GPIOINT_LEVEL_HIGH;
- break;
- case IRQ_TYPE_LEVEL_LOW:
- type = GPIOINT_LEVEL_LOW;
- break;
- default:
- BUG();
- }
-
-
- value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
- value &= ~(0xf << (offset * 0x4));
- value |= (type << (offset * 0x4));
- __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
-
- return 0;
-}
-
-struct irq_chip s5pc100_gpioint = {
- .name = "GPIO",
- .ack = s5pc100_gpioint_ack,
- .mask = s5pc100_gpioint_mask,
- .mask_ack = s5pc100_gpioint_mask_ack,
- .unmask = s5pc100_gpioint_unmask,
- .set_type = s5pc100_gpioint_set_type,
-};
-
-void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
-{
- int group, offset, pend_offset, mask_offset;
- int real_irq, group_end;
- unsigned int pend, mask;
-
- group_end = 21;
-
- for (group = 0; group < group_end; group++) {
- pend_offset = group_to_pend_offset(group);
- pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
- if (!pend)
- continue;
-
- mask_offset = group_to_mask_offset(group);
- mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
- pend &= ~mask;
-
- for (offset = 0; offset < 8; offset++) {
- if (pend & (1 << offset)) {
- real_irq = s5pc100_get_start(group) + offset;
- generic_handle_irq(S3C_IRQ_GPIO(real_irq));
- }
- }
- }
-}
#include <plat/adc.h>
#include <plat/keypad.h>
#include <plat/ts.h>
+#include <plat/audio.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
+ &s5pc100_device_spdif,
};
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
samsung_keypad_set_platdata(&smdkc100_keypad_data);
+ s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
+
/* LCD init */
gpio_request(S5PC100_GPD(0), "GPD");
gpio_request(S5PC100_GPH0(6), "GPH0");
#define DISR_OFFSET 0x7008
-void s5pc100_fb_gpio_setup_24bpp(void)
+static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
{
- unsigned int gpio = 0;
-
- for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
-
- for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
-
- for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
+}
- for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+ s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
+ s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
+ s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
+ s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
}
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
+static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
+{
+ s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
+
+ for (; nr > 0; nr--, base++)
+ s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
+
void s5pc100_ide_setup_gpio(void)
{
u32 reg;
- u32 gpio = 0;
/* Independent CF interface, CF chip select configuration */
reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
- for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
/*CF_Data[0 - 7] */
- for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
/* CF_Data[8 - 15] */
- for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
- for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
/* EBI_OE, EBI_WE */
- for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
+ s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
/* CF_OE, CF_WE */
- for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
/* CF_CD */
s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
- unsigned int gpio;
- unsigned int end;
-
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
- end = S5PC100_GPH3(rows);
- for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
- end = S5PC100_GPH2(cols);
- for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
}
void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- unsigned int end;
unsigned int num;
num = width;
if (width == 8)
num = width - 2;
- end = S5PC100_GPG0(2 + num);
-
/* Set all the necessary GPG0/GPG1 pins to special-function 0 */
- for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
- if (width == 8) {
- for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
- }
+ if (width == 8)
+ s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- unsigned int end;
-
- end = S5PC100_GPG2(2 + width);
/* Set all the necessary GPG2 pins to special-function 2 */
- for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- unsigned int end;
-
- end = S5PC100_GPG3(2 + width);
/* Set all the necessary GPG3 pins to special-function 2 */
- for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
config CPU_S5PV210
bool
- select PLAT_S5P
select S3C_PL330_DMA
select S5P_EXT_INT
+ select S5PV210_PM if PM
help
Enable S5PV210 CPU support
config MACH_AQUILA
bool "Aquila"
select CPU_S5PV210
- select ARCH_SPARSEMEM_ENABLE
select S3C_DEV_FB
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
config MACH_GONI
bool "GONI"
select CPU_S5PV210
- select ARCH_SPARSEMEM_ENABLE
+ select S5P_GPIO_INT
select S3C_DEV_FB
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
+ select S3C_DEV_I2C1
+ select S3C_DEV_I2C2
+ select S3C_DEV_USB_HSOTG
select S5P_DEV_ONENAND
+ select SAMSUNG_DEV_KEYPAD
select S5PV210_SETUP_FB_24BPP
+ select S5PV210_SETUP_I2C1
+ select S5PV210_SETUP_I2C2
+ select S5PV210_SETUP_KEYPAD
select S5PV210_SETUP_SDHCI
help
Machine support for Samsung GONI board
config MACH_SMDKC110
bool "SMDKC110"
select CPU_S5PV210
- select ARCH_SPARSEMEM_ENABLE
select S3C_DEV_I2C1
select S3C_DEV_I2C2
select S3C_DEV_RTC
config MACH_SMDKV210
bool "SMDKV210"
select CPU_S5PV210
- select ARCH_SPARSEMEM_ENABLE
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
help
Machine support for Samsung SMDKV210
+config MACH_TORBRECK
+ bool "Torbreck"
+ select CPU_S5PV210
+ select ARCH_SPARSEMEM_ENABLE
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_HSMMC3
+ select S3C_DEV_I2C1
+ select S3C_DEV_I2C2
+ select S3C_DEV_RTC
+ select S3C_DEV_WDT
+ select S5PV210_SETUP_I2C1
+ select S5PV210_SETUP_I2C2
+ select S5PV210_SETUP_SDHCI
+ help
+ Machine support for aESOP Torbreck
+
endmenu
+config S5PV210_PM
+ bool
+ help
+ Power Management code common to S5PV210
+
endif
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
+obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
+obj-$(CONFIG_CPU_FREQ) += cpufreq.o
# machine support
obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
obj-$(CONFIG_MACH_GONI) += mach-goni.o
+obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
# device support
#include <plat/clock-clksrc.h>
#include <plat/s5pv210.h>
+static unsigned long xtal;
+
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
};
+static struct clk *clkset_moutdmc0src_list[] = {
+ [0] = &clk_sclk_a2m.clk,
+ [1] = &clk_mout_mpll.clk,
+ [2] = NULL,
+ [3] = NULL,
+};
+
+static struct clksrc_sources clkset_moutdmc0src = {
+ .sources = clkset_moutdmc0src_list,
+ .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
+};
+
+static struct clksrc_clk clk_mout_dmc0 = {
+ .clk = {
+ .name = "mout_dmc0",
+ .id = -1,
+ },
+ .sources = &clkset_moutdmc0src,
+ .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
+};
+
+static struct clksrc_clk clk_sclk_dmc0 = {
+ .clk = {
+ .name = "sclk_dmc0",
+ .id = -1,
+ .parent = &clk_mout_dmc0.clk,
+ },
+ .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
+};
+
static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 2;
.get_rate = s5pv210_clk_imem_get_rate,
};
+static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
+{
+ return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
+}
+
+static struct clk_ops clk_fout_apll_ops = {
+ .get_rate = s5pv210_clk_fout_apll_get_rate,
+};
+
static struct clk init_clocks_disable[] = {
{
+ .name = "pdma",
+ .id = 0,
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip0_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "pdma",
+ .id = 1,
+ .parent = &clk_hclk_psys.clk,
+ .enable = s5pv210_clk_ip0_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
.name = "rot",
.id = -1,
.parent = &clk_hclk_dsys.clk,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6),
+ }, {
+ .name = "spdif",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s5pv210_clk_ip3_ctrl,
+ .ctrlbit = (1 << 0),
},
};
.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
};
+static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *pclk;
+ int ret;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ ret = pclk->ops->set_rate(pclk, rate);
+ clk_put(pclk);
+
+ return ret;
+}
+
+static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
+{
+ struct clk *pclk;
+ int rate;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ rate = pclk->ops->get_rate(clk);
+ clk_put(pclk);
+
+ return rate;
+}
+
+static struct clk_ops s5pv210_sclk_spdif_ops = {
+ .set_rate = s5pv210_spdif_set_rate,
+ .get_rate = s5pv210_spdif_get_rate,
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+ .clk = {
+ .name = "sclk_spdif",
+ .id = -1,
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 27),
+ .ops = &s5pv210_sclk_spdif_ops,
+ },
+ .sources = &clkset_sclk_spdif,
+ .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
+};
+
static struct clk *clkset_group2_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
},
.sources = &clkset_sclk_mixer,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
- }, {
- .clk = {
- .name = "sclk_spdif",
- .id = -1,
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 27),
- },
- .sources = &clkset_sclk_spdif,
- .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
}, {
.clk = {
.name = "sclk_fimc",
&clk_sclk_dac,
&clk_sclk_pixel,
&clk_sclk_hdmi,
+ &clk_mout_dmc0,
+ &clk_sclk_dmc0,
+ &clk_sclk_audio0,
+ &clk_sclk_audio1,
+ &clk_sclk_audio2,
+ &clk_sclk_spdif,
+};
+
+static u32 epll_div[][6] = {
+ { 48000000, 0, 48, 3, 3, 0 },
+ { 96000000, 0, 48, 3, 2, 0 },
+ { 144000000, 1, 72, 3, 2, 0 },
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 288000000, 1, 72, 3, 1, 0 },
+ { 32750000, 1, 65, 3, 4, 35127 },
+ { 32768000, 1, 65, 3, 4, 35127 },
+ { 45158400, 0, 45, 3, 3, 10355 },
+ { 45000000, 0, 45, 3, 3, 10355 },
+ { 45158000, 0, 45, 3, 3, 10355 },
+ { 49125000, 0, 49, 3, 3, 9961 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 67737600, 1, 67, 3, 3, 48366 },
+ { 67738000, 1, 67, 3, 3, 48366 },
+ { 73800000, 1, 73, 3, 3, 47710 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 36000000, 1, 32, 3, 4, 0 },
+ { 60000000, 1, 60, 3, 3, 0 },
+ { 72000000, 1, 72, 3, 3, 0 },
+ { 80000000, 1, 80, 3, 3, 0 },
+ { 84000000, 0, 42, 3, 2, 0 },
+ { 50000000, 0, 50, 3, 3, 0 },
+};
+
+static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ epll_con = __raw_readl(S5P_EPLL_CON);
+ epll_con_k = __raw_readl(S5P_EPLL_CON1);
+
+ epll_con_k &= ~PLL46XX_KDIV_MASK;
+ epll_con &= ~(1 << 27 |
+ PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
+ PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
+ PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+ if (epll_div[i][0] == rate) {
+ epll_con_k |= epll_div[i][5] << 0;
+ epll_con |= (epll_div[i][1] << 27 |
+ epll_div[i][2] << PLL46XX_MDIV_SHIFT |
+ epll_div[i][3] << PLL46XX_PDIV_SHIFT |
+ epll_div[i][4] << PLL46XX_SDIV_SHIFT);
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(epll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ __raw_writel(epll_con, S5P_EPLL_CON);
+ __raw_writel(epll_con_k, S5P_EPLL_CON1);
+
+ printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+ clk->rate, rate);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static struct clk_ops s5pv210_epll_ops = {
+ .set_rate = s5pv210_epll_set_rate,
+ .get_rate = s5p_epll_get_rate,
};
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
struct clk *xtal_clk;
- unsigned long xtal;
unsigned long vpllsrc;
unsigned long armclk;
unsigned long hclk_msys;
unsigned int ptr;
u32 clkdiv0, clkdiv1;
+ /* Set functions for clk_fout_epll */
+ clk_fout_epll.enable = s5p_epll_enable;
+ clk_fout_epll.ops = &s5pv210_epll_ops;
+
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
- epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
+ epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
+ __raw_readl(S5P_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
- clk_fout_apll.rate = apll;
+ clk_fout_apll.ops = &clk_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
.pfn = __phys_to_pfn(S5PV210_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_DMC0,
+ .pfn = __phys_to_pfn(S5PV210_PA_DMC0),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_DMC1,
+ .pfn = __phys_to_pfn(S5PV210_PA_DMC1),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_USB_HSPHY,
+ .pfn =__phys_to_pfn(S5PV210_PA_HSPHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
}
};
--- /dev/null
+/* linux/arch/arm/mach-s5pv210/cpufreq.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * CPU frequency scaling for S5PC110/S5PV210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+static struct clk *cpu_clk;
+static struct clk *dmc0_clk;
+static struct clk *dmc1_clk;
+static struct cpufreq_freqs freqs;
+
+/* APLL M,P,S values for 1G/800Mhz */
+#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
+#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
+
+/*
+ * DRAM configurations to calculate refresh counter for changing
+ * frequency of memory.
+ */
+struct dram_conf {
+ unsigned long freq; /* HZ */
+ unsigned long refresh; /* DRAM refresh counter * 1000 */
+};
+
+/* DRAM configuration (DMC0 and DMC1) */
+static struct dram_conf s5pv210_dram_conf[2];
+
+enum perf_level {
+ L0, L1, L2, L3, L4,
+};
+
+enum s5pv210_mem_type {
+ LPDDR = 0x1,
+ LPDDR2 = 0x2,
+ DDR2 = 0x4,
+};
+
+enum s5pv210_dmc_port {
+ DMC0 = 0,
+ DMC1,
+};
+
+static struct cpufreq_frequency_table s5pv210_freq_table[] = {
+ {L0, 1000*1000},
+ {L1, 800*1000},
+ {L2, 400*1000},
+ {L3, 200*1000},
+ {L4, 100*1000},
+ {0, CPUFREQ_TABLE_END},
+};
+
+static u32 clkdiv_val[5][11] = {
+ /*
+ * Clock divider value for following
+ * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
+ * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
+ * ONEDRAM, MFC, G3D }
+ */
+
+ /* L0 : [1000/200/100][166/83][133/66][200/200] */
+ {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
+
+ /* L1 : [800/200/100][166/83][133/66][200/200] */
+ {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
+
+ /* L2 : [400/200/100][166/83][133/66][200/200] */
+ {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
+
+ /* L3 : [200/200/100][166/83][133/66][200/200] */
+ {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
+
+ /* L4 : [100/100/100][83/83][66/66][100/100] */
+ {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
+};
+
+/*
+ * This function set DRAM refresh counter
+ * accoriding to operating frequency of DRAM
+ * ch: DMC port number 0 or 1
+ * freq: Operating frequency of DRAM(KHz)
+ */
+static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
+{
+ unsigned long tmp, tmp1;
+ void __iomem *reg = NULL;
+
+ if (ch == DMC0)
+ reg = (S5P_VA_DMC0 + 0x30);
+ else if (ch == DMC1)
+ reg = (S5P_VA_DMC1 + 0x30);
+ else
+ printk(KERN_ERR "Cannot find DMC port\n");
+
+ /* Find current DRAM frequency */
+ tmp = s5pv210_dram_conf[ch].freq;
+
+ do_div(tmp, freq);
+
+ tmp1 = s5pv210_dram_conf[ch].refresh;
+
+ do_div(tmp1, tmp);
+
+ __raw_writel(tmp1, reg);
+}
+
+int s5pv210_verify_speed(struct cpufreq_policy *policy)
+{
+ if (policy->cpu)
+ return -EINVAL;
+
+ return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
+}
+
+unsigned int s5pv210_getspeed(unsigned int cpu)
+{
+ if (cpu)
+ return 0;
+
+ return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int s5pv210_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ unsigned long reg;
+ unsigned int index, priv_index;
+ unsigned int pll_changing = 0;
+ unsigned int bus_speed_changing = 0;
+
+ freqs.old = s5pv210_getspeed(0);
+
+ if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
+ target_freq, relation, &index))
+ return -EINVAL;
+
+ freqs.new = s5pv210_freq_table[index].frequency;
+ freqs.cpu = 0;
+
+ if (freqs.new == freqs.old)
+ return 0;
+
+ /* Finding current running level index */
+ if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
+ freqs.old, relation, &priv_index))
+ return -EINVAL;
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ if (freqs.new > freqs.old) {
+ /* Voltage up: will be implemented */
+ }
+
+ /* Check if there need to change PLL */
+ if ((index == L0) || (priv_index == L0))
+ pll_changing = 1;
+
+ /* Check if there need to change System bus clock */
+ if ((index == L4) || (priv_index == L4))
+ bus_speed_changing = 1;
+
+ if (bus_speed_changing) {
+ /*
+ * Reconfigure DRAM refresh counter value for minimum
+ * temporary clock while changing divider.
+ * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
+ */
+ if (pll_changing)
+ s5pv210_set_refresh(DMC1, 83000);
+ else
+ s5pv210_set_refresh(DMC1, 100000);
+
+ s5pv210_set_refresh(DMC0, 83000);
+ }
+
+ /*
+ * APLL should be changed in this level
+ * APLL -> MPLL(for stable transition) -> APLL
+ * Some clock source's clock API are not prepared.
+ * Do not use clock API in below code.
+ */
+ if (pll_changing) {
+ /*
+ * 1. Temporary Change divider for MFC and G3D
+ * SCLKA2M(200/1=200)->(200/4=50)Mhz
+ */
+ reg = __raw_readl(S5P_CLK_DIV2);
+ reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
+ reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
+ (3 << S5P_CLKDIV2_MFC_SHIFT);
+ __raw_writel(reg, S5P_CLK_DIV2);
+
+ /* For MFC, G3D dividing */
+ do {
+ reg = __raw_readl(S5P_CLKDIV_STAT0);
+ } while (reg & ((1 << 16) | (1 << 17)));
+
+ /*
+ * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
+ * (200/4=50)->(667/4=166)Mhz
+ */
+ reg = __raw_readl(S5P_CLK_SRC2);
+ reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+ reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
+ (1 << S5P_CLKSRC2_MFC_SHIFT);
+ __raw_writel(reg, S5P_CLK_SRC2);
+
+ do {
+ reg = __raw_readl(S5P_CLKMUX_STAT1);
+ } while (reg & ((1 << 7) | (1 << 3)));
+
+ /*
+ * 3. DMC1 refresh count for 133Mhz if (index == L4) is
+ * true refresh counter is already programed in upper
+ * code. 0x287@83Mhz
+ */
+ if (!bus_speed_changing)
+ s5pv210_set_refresh(DMC1, 133000);
+
+ /* 4. SCLKAPLL -> SCLKMPLL */
+ reg = __raw_readl(S5P_CLK_SRC0);
+ reg &= ~(S5P_CLKSRC0_MUX200_MASK);
+ reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
+ __raw_writel(reg, S5P_CLK_SRC0);
+
+ do {
+ reg = __raw_readl(S5P_CLKMUX_STAT0);
+ } while (reg & (0x1 << 18));
+
+ }
+
+ /* Change divider */
+ reg = __raw_readl(S5P_CLK_DIV0);
+
+ reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
+ S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
+ S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
+ S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
+
+ reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
+ (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
+ (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
+ (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
+ (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
+ (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
+ (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
+ (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
+
+ __raw_writel(reg, S5P_CLK_DIV0);
+
+ do {
+ reg = __raw_readl(S5P_CLKDIV_STAT0);
+ } while (reg & 0xff);
+
+ /* ARM MCS value changed */
+ reg = __raw_readl(S5P_ARM_MCS_CON);
+ reg &= ~0x3;
+ if (index >= L3)
+ reg |= 0x3;
+ else
+ reg |= 0x1;
+
+ __raw_writel(reg, S5P_ARM_MCS_CON);
+
+ if (pll_changing) {
+ /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
+ __raw_writel(0x2cf, S5P_APLL_LOCK);
+
+ /*
+ * 6. Turn on APLL
+ * 6-1. Set PMS values
+ * 6-2. Wait untile the PLL is locked
+ */
+ if (index == L0)
+ __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
+ else
+ __raw_writel(APLL_VAL_800, S5P_APLL_CON);
+
+ do {
+ reg = __raw_readl(S5P_APLL_CON);
+ } while (!(reg & (0x1 << 29)));
+
+ /*
+ * 7. Change souce clock from SCLKMPLL(667Mhz)
+ * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
+ * (667/4=166)->(200/4=50)Mhz
+ */
+ reg = __raw_readl(S5P_CLK_SRC2);
+ reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+ reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
+ (0 << S5P_CLKSRC2_MFC_SHIFT);
+ __raw_writel(reg, S5P_CLK_SRC2);
+
+ do {
+ reg = __raw_readl(S5P_CLKMUX_STAT1);
+ } while (reg & ((1 << 7) | (1 << 3)));
+
+ /*
+ * 8. Change divider for MFC and G3D
+ * (200/4=50)->(200/1=200)Mhz
+ */
+ reg = __raw_readl(S5P_CLK_DIV2);
+ reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
+ reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
+ (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
+ __raw_writel(reg, S5P_CLK_DIV2);
+
+ /* For MFC, G3D dividing */
+ do {
+ reg = __raw_readl(S5P_CLKDIV_STAT0);
+ } while (reg & ((1 << 16) | (1 << 17)));
+
+ /* 9. Change MPLL to APLL in MSYS_MUX */
+ reg = __raw_readl(S5P_CLK_SRC0);
+ reg &= ~(S5P_CLKSRC0_MUX200_MASK);
+ reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
+ __raw_writel(reg, S5P_CLK_SRC0);
+
+ do {
+ reg = __raw_readl(S5P_CLKMUX_STAT0);
+ } while (reg & (0x1 << 18));
+
+ /*
+ * 10. DMC1 refresh counter
+ * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
+ * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
+ */
+ if (!bus_speed_changing)
+ s5pv210_set_refresh(DMC1, 200000);
+ }
+
+ /*
+ * L4 level need to change memory bus speed, hence onedram clock divier
+ * and memory refresh parameter should be changed
+ */
+ if (bus_speed_changing) {
+ reg = __raw_readl(S5P_CLK_DIV6);
+ reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
+ reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
+ __raw_writel(reg, S5P_CLK_DIV6);
+
+ do {
+ reg = __raw_readl(S5P_CLKDIV_STAT1);
+ } while (reg & (1 << 15));
+
+ /* Reconfigure DRAM refresh counter value */
+ if (index != L4) {
+ /*
+ * DMC0 : 166Mhz
+ * DMC1 : 200Mhz
+ */
+ s5pv210_set_refresh(DMC0, 166000);
+ s5pv210_set_refresh(DMC1, 200000);
+ } else {
+ /*
+ * DMC0 : 83Mhz
+ * DMC1 : 100Mhz
+ */
+ s5pv210_set_refresh(DMC0, 83000);
+ s5pv210_set_refresh(DMC1, 100000);
+ }
+ }
+
+ if (freqs.new < freqs.old) {
+ /* Voltage down: will be implemented */
+ }
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ printk(KERN_DEBUG "Perf changed[L%d]\n", index);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy,
+ pm_message_t pmsg)
+{
+ return 0;
+}
+
+static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
+{
+ return 0;
+}
+#endif
+
+static int check_mem_type(void __iomem *dmc_reg)
+{
+ unsigned long val;
+
+ val = __raw_readl(dmc_reg + 0x4);
+ val = (val & (0xf << 8));
+
+ return val >> 8;
+}
+
+static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
+{
+ unsigned long mem_type;
+
+ cpu_clk = clk_get(NULL, "armclk");
+ if (IS_ERR(cpu_clk))
+ return PTR_ERR(cpu_clk);
+
+ dmc0_clk = clk_get(NULL, "sclk_dmc0");
+ if (IS_ERR(dmc0_clk)) {
+ clk_put(cpu_clk);
+ return PTR_ERR(dmc0_clk);
+ }
+
+ dmc1_clk = clk_get(NULL, "hclk_msys");
+ if (IS_ERR(dmc1_clk)) {
+ clk_put(dmc0_clk);
+ clk_put(cpu_clk);
+ return PTR_ERR(dmc1_clk);
+ }
+
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ /*
+ * check_mem_type : This driver only support LPDDR & LPDDR2.
+ * other memory type is not supported.
+ */
+ mem_type = check_mem_type(S5P_VA_DMC0);
+
+ if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
+ printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
+ return -EINVAL;
+ }
+
+ /* Find current refresh counter and frequency each DMC */
+ s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
+ s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
+
+ s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
+ s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
+
+ policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
+
+ cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
+
+ policy->cpuinfo.transition_latency = 40000;
+
+ return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
+}
+
+static struct cpufreq_driver s5pv210_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = s5pv210_verify_speed,
+ .target = s5pv210_target,
+ .get = s5pv210_getspeed,
+ .init = s5pv210_cpu_init,
+ .name = "s5pv210",
+#ifdef CONFIG_PM
+ .suspend = s5pv210_cpufreq_suspend,
+ .resume = s5pv210_cpufreq_resume,
+#endif
+};
+
+static int __init s5pv210_cpufreq_init(void)
+{
+ return cpufreq_register_driver(&s5pv210_driver);
+}
+
+late_initcall(s5pv210_cpufreq_init);
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
- s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
- s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4));
+ s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
break;
case -1:
- s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
break;
default:
{
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3));
+ s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
break;
case 1:
- s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3));
- s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3));
+ s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
break;
case 2:
- s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2));
+ s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
{
- s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4));
- s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4));
-
- return 0;
+ return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s5pv210_ac97_resource[] = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
+
+/* S/PDIF Controller platform_device */
+
+static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
+{
+ s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
+
+ return 0;
+}
+
+static struct resource s5pv210_spdif_resource[] = {
+ [0] = {
+ .start = S5PV210_PA_SPDIF,
+ .end = S5PV210_PA_SPDIF + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = DMACH_SPDIF,
+ .end = DMACH_SPDIF,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct s3c_audio_pdata samsung_spdif_pdata = {
+ .cfg_gpio = s5pv210_spdif_cfg_gpio,
+};
+
+static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pv210_device_spdif = {
+ .name = "samsung-spdif",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5pv210_spdif_resource),
+ .resource = s5pv210_spdif_resource,
+ .dev = {
+ .platform_data = &samsung_spdif_pdata,
+ .dma_mask = &s5pv210_spdif_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
*/
static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
{
+ unsigned int base;
+
switch (pdev->id) {
case 0:
- s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP);
+ base = S5PV210_GPB(0);
break;
case 1:
- s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2));
- s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP);
- s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP);
+ base = S5PV210_GPB(4);
break;
default:
return -EINVAL;
}
+ s3c_gpio_cfgall_range(base, 3,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
return 0;
}
static struct platform_device s5pv210_device_pdma0 = {
.name = "s3c-pl330",
- .id = 1,
+ .id = 0,
.num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
.resource = s5pv210_pdma0_resource,
.dev = {
static struct platform_device s5pv210_device_pdma1 = {
.name = "s3c-pl330",
- .id = 2,
+ .id = 1,
.num_resources = ARRAY_SIZE(s5pv210_pdma1_resource),
.resource = s5pv210_pdma1_resource,
.dev = {
.label = "GPG3",
},
}, {
+ .config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_GPI(0),
.ngpio = S5PV210_GPIO_I_NR,
}, {
.base = (S5P_VA_GPIO + 0xC00),
.config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(0),
.chip = {
.base = S5PV210_GPH0(0),
.ngpio = S5PV210_GPIO_H0_NR,
.label = "GPH0",
+ .to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = (S5P_VA_GPIO + 0xC20),
.config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(8),
.chip = {
.base = S5PV210_GPH1(0),
.ngpio = S5PV210_GPIO_H1_NR,
.label = "GPH1",
+ .to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = (S5P_VA_GPIO + 0xC40),
.config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(16),
.chip = {
.base = S5PV210_GPH2(0),
.ngpio = S5PV210_GPIO_H2_NR,
.label = "GPH2",
+ .to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = (S5P_VA_GPIO + 0xC60),
.config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(24),
.chip = {
.base = S5PV210_GPH3(0),
.ngpio = S5PV210_GPIO_H3_NR,
.label = "GPH3",
+ .to_irq = samsung_gpiolib_to_irq,
},
},
};
{
struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+ int gpioint_group = 0;
int i = 0;
for (i = 0; i < nr_chips; i++, chip++) {
- if (chip->config == NULL)
+ if (chip->config == NULL) {
chip->config = &gpio_cfg;
+ chip->group = gpioint_group++;
+ }
if (chip->base == NULL)
chip->base = S5PV210_BANK_BASE(i);
}
#define IRQ_SPI1 S5P_IRQ_VIC1(16)
#define IRQ_SPI2 S5P_IRQ_VIC1(17)
#define IRQ_IRDA S5P_IRQ_VIC1(18)
-#define IRQ_CAN0 S5P_IRQ_VIC1(19)
-#define IRQ_CAN1 S5P_IRQ_VIC1(20)
+#define IRQ_IIC2 S5P_IRQ_VIC1(19)
+#define IRQ_IIC3 S5P_IRQ_VIC1(20)
#define IRQ_HSIRX S5P_IRQ_VIC1(21)
#define IRQ_HSITX S5P_IRQ_VIC1(22)
#define IRQ_UHOST S5P_IRQ_VIC1(23)
#define IRQ_IPC S5P_IRQ_VIC3(0)
#define IRQ_HOSTIF S5P_IRQ_VIC3(1)
-#define IRQ_MMC3 S5P_IRQ_VIC3(2)
+#define IRQ_HSMMC3 S5P_IRQ_VIC3(2)
#define IRQ_CEC S5P_IRQ_VIC3(3)
#define IRQ_TSI S5P_IRQ_VIC3(4)
#define IRQ_MDNIE0 S5P_IRQ_VIC3(5)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
+/* GPIO interrupt */
+#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
+#define S5P_GPIOINT_GROUP_MAXNR 22
+
/* Set the default NR_IRQS */
-#define NR_IRQS (IRQ_EINT(31) + 1)
+#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
/* Compatibility */
#define IRQ_LCD_FIFO IRQ_LCD0
#define S5P_SZ_UART SZ_256
+#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
#define S5PV210_PA_SROMC (0xE8000000)
#define S5PV210_PA_CFCON (0xE8200000)
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
+#define S5PV210_PA_HSOTG (0xEC000000)
+#define S5PV210_PA_HSPHY (0xEC100000)
+
#define S5PV210_PA_VIC0 (0xF2000000)
#define S5PV210_PA_VIC1 (0xF2100000)
#define S5PV210_PA_VIC2 (0xF2200000)
#define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
+/* S/PDIF */
+#define S5PV210_PA_SPDIF 0xE1100000
+
/* I2S */
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_ADC (0xE1700000)
+#define S5PV210_PA_DMC0 (0xF0000000)
+#define S5PV210_PA_DMC1 (0xF1400000)
+
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV210_PA_UART
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
+#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
--- /dev/null
+/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+ /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
+ __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+ /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+ /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+ /* nothing here yet */
+}
#define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x108)
#define S5P_EPLL_CON S5P_CLKREG(0x110)
+#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
#define S5P_VPLL_CON S5P_CLKREG(0x120)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
#define S5P_CLK_OUT S5P_CLKREG(0x500)
+/* DIV/MUX STATUS */
+#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
+#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
+#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
+#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
+
/* CLKSRC0 */
-#define S5P_CLKSRC0_MUX200_MASK (0x1<<16)
+#define S5P_CLKSRC0_MUX200_SHIFT (16)
+#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
+/* CLKSRC2 */
+#define S5P_CLKSRC2_G3D_SHIFT (0)
+#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
+#define S5P_CLKSRC2_MFC_SHIFT (4)
+#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
+
+/* CLKSRC6*/
+#define S5P_CLKSRC6_ONEDRAM_SHIFT (24)
+#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
+
/* CLKDIV0 */
#define S5P_CLKDIV0_APLL_SHIFT (0)
#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
#define S5P_CLKDIV0_PCLK66_SHIFT (28)
#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
+/* CLKDIV2 */
+#define S5P_CLKDIV2_G3D_SHIFT (0)
+#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
+#define S5P_CLKDIV2_MFC_SHIFT (4)
+#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
+
+/* CLKDIV6 */
+#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
+#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
+
#define S5P_SWRESET S5P_CLKREG(0x2000)
+#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
+
/* Registers related to power management */
#define S5P_PWR_CFG S5P_CLKREG(0xC000)
#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
-#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
+#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
#define S5P_PWR_MODE S5P_CLKREG(0xC00C)
#define S5P_NORMAL_CFG S5P_CLKREG(0xC010)
#define S5P_IDLE_CFG S5P_CLKREG(0xC020)
#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
/* OTHERS Resgister */
+#define S5P_OTHERS_RET_IO (1 << 31)
+#define S5P_OTHERS_RET_CF (1 << 30)
+#define S5P_OTHERS_RET_MMC (1 << 29)
+#define S5P_OTHERS_RET_UART (1 << 28)
#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
-#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28)
/* MIPI */
#define S5P_MIPI_DPHY_EN (3)
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
-/* values for S5P_EXTINT0 */
-#define S5P_EXTINT_LOWLEV (0x00)
-#define S5P_EXTINT_HILEV (0x01)
-#define S5P_EXTINT_FALLEDGE (0x02)
-#define S5P_EXTINT_RISEEDGE (0x03)
-#define S5P_EXTINT_BOTHEDGE (0x04)
-
#define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) S5PV210_GPH0(x)
--- /dev/null
+/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV210 - System registers definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C)
+#define S5PV210_USB_PHY0_EN (1 << 0)
+#define S5PV210_USB_PHY1_EN (1 << 1)
+
+/* compatibility defines for s3c-hsotg driver */
+#define S3C64XX_OTHERS S5PV210_USB_PHY_CON
+#define S3C64XX_OTHERS_USBMASK S5PV210_USB_PHY0_EN
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END (0xE0000000UL)
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/mfd/max8998.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/regulator/fixed.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
};
#endif
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+ {
+ .dev_name = "5-001a",
+ .supply = "DBVDD",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "AVDD2",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "CPVDD",
+ },
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+ {
+ .dev_name = "5-001a",
+ .supply = "SPKVDD1",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "SPKVDD2",
+ },
+};
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+ .consumer_supplies = wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+ .consumer_supplies = wm8994_fixed_voltage1_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+ .supply_name = "VCC_1.8V_PDA",
+ .microvolts = 1800000,
+ .gpio = -EINVAL,
+ .init_data = &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+ .supply_name = "V_BAT",
+ .microvolts = 3700000,
+ .gpio = -EINVAL,
+ .init_data = &wm8994_fixed_voltage1_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+ .name = "reg-fixed-voltage",
+ .id = 0,
+ .dev = {
+ .platform_data = &wm8994_fixed_voltage0_config,
+ },
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &wm8994_fixed_voltage1_config,
+ },
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply = {
+ .dev_name = "5-001a",
+ .supply = "AVDD1",
+};
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply = {
+ .dev_name = "5-001a",
+ .supply = "DCVDD",
+};
+
+static struct regulator_init_data wm8994_ldo1_data = {
+ .constraints = {
+ .name = "AVDD1_3.0V",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+ .constraints = {
+ .name = "DCVDD_1.0V",
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+ /* configure gpio1 function: 0x0001(Logic level input/output) */
+ .gpio_defaults[0] = 0x0001,
+ /* configure gpio3/4/5/7 function for AIF2 voice */
+ .gpio_defaults[2] = 0x8100,
+ .gpio_defaults[3] = 0x8100,
+ .gpio_defaults[4] = 0x8100,
+ .gpio_defaults[6] = 0x0100,
+ /* configure gpio8/9/10/11 function for AIF3 BT */
+ .gpio_defaults[7] = 0x8100,
+ .gpio_defaults[8] = 0x0100,
+ .gpio_defaults[9] = 0x0100,
+ .gpio_defaults[10] = 0x0100,
+ .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+ .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
/* GPIO I2C PMIC */
#define AP_I2C_GPIO_PMIC_BUS_4 4
static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
#endif
};
+/* GPIO I2C AP 1.8V */
+#define AP_I2C_GPIO_BUS_5 5
+static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
+ .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
+ .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
+};
+
+static struct platform_device aquila_i2c_gpio5 = {
+ .name = "i2c-gpio",
+ .id = AP_I2C_GPIO_BUS_5,
+ .dev = {
+ .platform_data = &aquila_i2c_gpio5_data,
+ },
+};
+
+static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
+ {
+ /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
+ I2C_BOARD_INFO("wm8994", 0x1a),
+ .platform_data = &wm8994_platform_data,
+ },
+};
+
/* PMIC Power button */
static struct gpio_keys_button aquila_gpio_keys_table[] = {
{
static struct platform_device *aquila_devices[] __initdata = {
&aquila_i2c_gpio_pmic,
+ &aquila_i2c_gpio5,
&aquila_device_gpiokeys,
&s3c_device_fb,
&s5p_device_onenand,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s5p_device_fimc2,
+ &s5pv210_device_iis0,
+ &wm8994_fixed_voltage0,
+ &wm8994_fixed_voltage1,
};
+static void __init aquila_sound_init(void)
+{
+ unsigned int gpio;
+
+ /* CODEC_XTAL_EN
+ *
+ * The Aquila board have a oscillator which provide main clock
+ * to WM8994 codec. The oscillator provide 24MHz clock to WM8994
+ * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
+ * */
+ gpio = S5PV210_GPH3(2); /* XEINT_26 */
+ gpio_request(gpio, "CODEC_XTAL_EN");
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+ /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
+ * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
+ * because it needs 24MHz clock to operate WM8994 codec.
+ */
+ __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
+}
+
static void __init aquila_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c_fimc_setname(1, "s5p-fimc");
s3c_fimc_setname(2, "s5p-fimc");
+ /* SOUND */
+ aquila_sound_init();
+ i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
+ ARRAY_SIZE(i2c_gpio5_devs));
+
/* FB */
s3c_fb_set_platdata(&aquila_lcd_pdata);
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
+#include <linux/i2c/qt602240_ts.h>
#include <linux/mfd/max8998.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/regulator/fixed.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/lcd.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/fb.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
#include <plat/sdhci.h>
+#include <plat/clock.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
/* Frame Buffer */
static struct s3c_fb_pd_win goni_fb_win0 = {
.win_mode = {
- .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*55),
.left_margin = 16,
.right_margin = 16,
- .upper_margin = 3,
+ .upper_margin = 2,
.lower_margin = 28,
.hsync_len = 2,
- .vsync_len = 2,
+ .vsync_len = 1,
.xres = 480,
.yres = 800,
.refresh = 55,
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
};
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+ return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+ static unsigned int first = 1;
+ int reset_gpio = -1;
+
+ reset_gpio = S5PV210_MP05(5);
+
+ if (first) {
+ gpio_request(reset_gpio, "MLCD_RST");
+ first = 0;
+ }
+
+ gpio_direction_output(reset_gpio, 1);
+ return 1;
+}
+
+static struct lcd_platform_data goni_lcd_platform_data = {
+ .reset = reset_lcd,
+ .power_on = lcd_power_on,
+ .lcd_enabled = 0,
+ .reset_delay = 120, /* 120ms */
+ .power_on_delay = 25, /* 25ms */
+ .power_off_delay = 200, /* 200ms */
+};
+
+#define LCD_BUS_NUM 3
+static struct spi_board_info spi_board_info[] __initdata = {
+ {
+ .modalias = "s6e63m0",
+ .platform_data = &goni_lcd_platform_data,
+ .max_speed_hz = 1200000,
+ .bus_num = LCD_BUS_NUM,
+ .chip_select = 0,
+ .mode = SPI_MODE_3,
+ .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
+ },
+};
+
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+ .sck = S5PV210_MP04(1), /* DISPLAY_CLK */
+ .mosi = S5PV210_MP04(3), /* DISPLAY_SI */
+ .miso = SPI_GPIO_NO_MISO,
+ .num_chipselect = 1,
+};
+
+static struct platform_device goni_spi_gpio = {
+ .name = "spi_gpio",
+ .id = LCD_BUS_NUM,
+ .dev = {
+ .parent = &s3c_device_fb.dev,
+ .platform_data = &lcd_spi_gpio_data,
+ },
+};
+
+/* KEYPAD */
+static uint32_t keymap[] __initdata = {
+ /* KEY(row, col, keycode) */
+ KEY(0, 1, KEY_MENU), /* Send */
+ KEY(0, 2, KEY_BACK), /* End */
+ KEY(1, 1, KEY_CONFIG), /* Half shot */
+ KEY(1, 2, KEY_VOLUMEUP),
+ KEY(2, 1, KEY_CAMERA), /* Full shot */
+ KEY(2, 2, KEY_VOLUMEDOWN),
+};
+
+static struct matrix_keymap_data keymap_data __initdata = {
+ .keymap = keymap,
+ .keymap_size = ARRAY_SIZE(keymap),
+};
+
+static struct samsung_keypad_platdata keypad_data __initdata = {
+ .keymap_data = &keymap_data,
+ .rows = 3,
+ .cols = 3,
+};
+
+/* Radio */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("si470x", 0x10),
+ },
+};
+
+static void __init goni_radio_init(void)
+{
+ int gpio;
+
+ gpio = S5PV210_GPJ2(4); /* XMSMDATA_4 */
+ gpio_request(gpio, "FM_INT");
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ i2c1_devs[0].irq = gpio_to_irq(gpio);
+
+ gpio = S5PV210_GPJ2(5); /* XMSMDATA_5 */
+ gpio_request(gpio, "FM_RST");
+ gpio_direction_output(gpio, 1);
+}
+
+/* TSP */
+static struct qt602240_platform_data qt602240_platform_data = {
+ .x_line = 17,
+ .y_line = 11,
+ .x_size = 800,
+ .y_size = 480,
+ .blen = 0x21,
+ .threshold = 0x28,
+ .voltage = 2800000, /* 2.8V */
+ .orient = QT602240_DIAGONAL,
+};
+
+static struct s3c2410_platform_i2c i2c2_data __initdata = {
+ .flags = 0,
+ .bus_num = 2,
+ .slave_addr = 0x10,
+ .frequency = 400 * 1000,
+ .sda_delay = 100,
+};
+
+static struct i2c_board_info i2c2_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("qt602240_ts", 0x4a),
+ .platform_data = &qt602240_platform_data,
+ },
+};
+
+static void __init goni_tsp_init(void)
+{
+ int gpio;
+
+ gpio = S5PV210_GPJ1(3); /* XMSMADDR_11 */
+ gpio_request(gpio, "TSP_LDO_ON");
+ gpio_direction_output(gpio, 1);
+ gpio_export(gpio, 0);
+
+ gpio = S5PV210_GPJ0(5); /* XMSMADDR_5 */
+ gpio_request(gpio, "TSP_INT");
+
+ s5p_register_gpio_interrupt(gpio);
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ i2c2_devs[0].irq = gpio_to_irq(gpio);
+}
+
/* MAX8998 regulators */
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
+static struct regulator_consumer_supply goni_ldo5_consumers[] = {
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
static struct regulator_init_data goni_ldo2_data = {
.constraints = {
.name = "VALIVE_1.1V",
.max_uV = 2800000,
.apply_uV = 1,
},
+ .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
+ .consumer_supplies = goni_ldo5_consumers,
};
static struct regulator_init_data goni_ldo6_data = {
};
#endif
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+ {
+ .dev_name = "5-001a",
+ .supply = "DBVDD",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "AVDD2",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "CPVDD",
+ },
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+ {
+ .dev_name = "5-001a",
+ .supply = "SPKVDD1",
+ }, {
+ .dev_name = "5-001a",
+ .supply = "SPKVDD2",
+ },
+};
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+ .consumer_supplies = wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+ .consumer_supplies = wm8994_fixed_voltage1_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+ .supply_name = "VCC_1.8V_PDA",
+ .microvolts = 1800000,
+ .gpio = -EINVAL,
+ .init_data = &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+ .supply_name = "V_BAT",
+ .microvolts = 3700000,
+ .gpio = -EINVAL,
+ .init_data = &wm8994_fixed_voltage1_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+ .name = "reg-fixed-voltage",
+ .id = 0,
+ .dev = {
+ .platform_data = &wm8994_fixed_voltage0_config,
+ },
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &wm8994_fixed_voltage1_config,
+ },
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply = {
+ .dev_name = "5-001a",
+ .supply = "AVDD1",
+};
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply = {
+ .dev_name = "5-001a",
+ .supply = "DCVDD",
+};
+
+static struct regulator_init_data wm8994_ldo1_data = {
+ .constraints = {
+ .name = "AVDD1_3.0V",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+ .constraints = {
+ .name = "DCVDD_1.0V",
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+ /* configure gpio1 function: 0x0001(Logic level input/output) */
+ .gpio_defaults[0] = 0x0001,
+ /* configure gpio3/4/5/7 function for AIF2 voice */
+ .gpio_defaults[2] = 0x8100,
+ .gpio_defaults[3] = 0x8100,
+ .gpio_defaults[4] = 0x8100,
+ .gpio_defaults[6] = 0x0100,
+ /* configure gpio8/9/10/11 function for AIF3 BT */
+ .gpio_defaults[7] = 0x8100,
+ .gpio_defaults[8] = 0x0100,
+ .gpio_defaults[9] = 0x0100,
+ .gpio_defaults[10] = 0x0100,
+ .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+ .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
/* GPIO I2C PMIC */
#define AP_I2C_GPIO_PMIC_BUS_4 4
static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
#endif
};
+/* GPIO I2C AP 1.8V */
+#define AP_I2C_GPIO_BUS_5 5
+static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
+ .sda_pin = S5PV210_MP05(3), /* XM0ADDR_11 */
+ .scl_pin = S5PV210_MP05(2), /* XM0ADDR_10 */
+};
+
+static struct platform_device goni_i2c_gpio5 = {
+ .name = "i2c-gpio",
+ .id = AP_I2C_GPIO_BUS_5,
+ .dev = {
+ .platform_data = &goni_i2c_gpio5_data,
+ },
+};
+
+static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
+ {
+ /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
+ I2C_BOARD_INFO("wm8994", 0x1a),
+ .platform_data = &wm8994_platform_data,
+ },
+};
+
/* PMIC Power button */
static struct gpio_keys_button goni_gpio_keys_table[] = {
{
.ext_cd_gpio_invert = 1,
};
+static struct regulator_consumer_supply mmc2_supplies[] = {
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
+};
+
+static struct regulator_init_data mmc2_fixed_voltage_init_data = {
+ .constraints = {
+ .name = "V_TF_2.8V",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(mmc2_supplies),
+ .consumer_supplies = mmc2_supplies,
+};
+
+static struct fixed_voltage_config mmc2_fixed_voltage_config = {
+ .supply_name = "EXT_FLASH_EN",
+ .microvolts = 2800000,
+ .gpio = GONI_EXT_FLASH_EN,
+ .enable_high = true,
+ .init_data = &mmc2_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc2_fixed_voltage = {
+ .name = "reg-fixed-voltage",
+ .id = 2,
+ .dev = {
+ .platform_data = &mmc2_fixed_voltage_config,
+ },
+};
+
static void goni_setup_sdhci(void)
{
- gpio_request(GONI_EXT_FLASH_EN, "FLASH_EN");
- gpio_direction_output(GONI_EXT_FLASH_EN, 1);
-
s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
static struct platform_device *goni_devices[] __initdata = {
&s3c_device_fb,
&s5p_device_onenand,
+ &goni_spi_gpio,
&goni_i2c_gpio_pmic,
+ &goni_i2c_gpio5,
+ &mmc2_fixed_voltage,
&goni_device_gpiokeys,
&s5p_device_fimc0,
&s5p_device_fimc1,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
+ &s5pv210_device_iis0,
+ &s3c_device_usb_hsotg,
+ &samsung_device_keypad,
+ &s3c_device_i2c1,
+ &s3c_device_i2c2,
+ &wm8994_fixed_voltage0,
+ &wm8994_fixed_voltage1,
};
+static void __init goni_sound_init(void)
+{
+ /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
+ * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
+ * because it needs 24MHz clock to operate WM8994 codec.
+ */
+ __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
+}
+
static void __init goni_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
static void __init goni_machine_init(void)
{
+ /* Radio: call before I2C 1 registeration */
+ goni_radio_init();
+
+ /* I2C1 */
+ s3c_i2c1_set_platdata(NULL);
+ i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+ /* TSP: call before I2C 2 registeration */
+ goni_tsp_init();
+
+ /* I2C2 */
+ s3c_i2c2_set_platdata(&i2c2_data);
+ i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
+
/* PMIC */
goni_pmic_init();
i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
/* SDHCI */
goni_setup_sdhci();
+ /* SOUND */
+ goni_sound_init();
+ i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
+ ARRAY_SIZE(i2c_gpio5_devs));
+
/* FB */
s3c_fb_set_platdata(&goni_lcd_pdata);
+ /* SPI */
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+ /* KEYPAD */
+ samsung_keypad_set_platdata(&keypad_data);
+
+ clk_xusbxti.rate = 24000000;
+
platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
}
#include <plat/cpu.h>
#include <plat/ata.h>
#include <plat/iic.h>
+#include <plat/pm.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
static struct platform_device *smdkc110_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
+ &s5pv210_device_spdif,
&s3c_device_cfcon,
&s3c_device_i2c0,
&s3c_device_i2c1,
static void __init smdkc110_machine_init(void)
{
+ s3c_pm_init();
+
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_i2c2_set_platdata(NULL);
#include <plat/ata.h>
#include <plat/iic.h>
#include <plat/keypad.h>
+#include <plat/pm.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
+ &s5pv210_device_spdif,
&s3c_device_adc,
&s3c_device_cfcon,
&s3c_device_hsmmc0,
static void __init smdkv210_machine_init(void)
{
+ s3c_pm_init();
+
samsung_keypad_set_platdata(&smdkv210_keypad_data);
s3c24xx_ts_set_platdata(&s3c_ts_platform);
--- /dev/null
+/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
+ *
+ * Copyright (c) 2010 aESOP Community
+ * http://www.aesop.or.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv210.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
+ S3C2410_UCON_RXILEVEL | \
+ S3C2410_UCON_TXIRQMODE | \
+ S3C2410_UCON_RXIRQMODE | \
+ S3C2410_UCON_RXFIFO_TOI | \
+ S3C2443_UCON_RXERR_IRQEN)
+
+#define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
+ S5PV210_UFCON_TXTRIG4 | \
+ S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = TORBRECK_UCON_DEFAULT,
+ .ulcon = TORBRECK_ULCON_DEFAULT,
+ .ufcon = TORBRECK_UFCON_DEFAULT,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = TORBRECK_UCON_DEFAULT,
+ .ulcon = TORBRECK_ULCON_DEFAULT,
+ .ufcon = TORBRECK_UFCON_DEFAULT,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = TORBRECK_UCON_DEFAULT,
+ .ulcon = TORBRECK_ULCON_DEFAULT,
+ .ufcon = TORBRECK_UFCON_DEFAULT,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = TORBRECK_UCON_DEFAULT,
+ .ulcon = TORBRECK_ULCON_DEFAULT,
+ .ufcon = TORBRECK_UFCON_DEFAULT,
+ },
+};
+
+static struct platform_device *torbreck_devices[] __initdata = {
+ &s5pv210_device_iis0,
+ &s3c_device_cfcon,
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_hsmmc2,
+ &s3c_device_hsmmc3,
+ &s3c_device_i2c0,
+ &s3c_device_i2c1,
+ &s3c_device_i2c2,
+ &s3c_device_rtc,
+ &s3c_device_wdt,
+};
+
+static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
+ /* To Be Updated */
+};
+
+static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
+ /* To Be Updated */
+};
+
+static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
+ /* To Be Updated */
+};
+
+static void __init torbreck_map_io(void)
+{
+ s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+ s3c24xx_init_clocks(24000000);
+ s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
+}
+
+static void __init torbreck_machine_init(void)
+{
+ s3c_i2c0_set_platdata(NULL);
+ s3c_i2c1_set_platdata(NULL);
+ s3c_i2c2_set_platdata(NULL);
+ i2c_register_board_info(0, torbreck_i2c_devs0,
+ ARRAY_SIZE(torbreck_i2c_devs0));
+ i2c_register_board_info(1, torbreck_i2c_devs1,
+ ARRAY_SIZE(torbreck_i2c_devs1));
+ i2c_register_board_info(2, torbreck_i2c_devs2,
+ ARRAY_SIZE(torbreck_i2c_devs2));
+
+ platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
+}
+
+MACHINE_START(TORBRECK, "TORBRECK")
+ /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
+ .boot_params = S5P_PA_SDRAM + 0x100,
+ .init_irq = s5pv210_init_irq,
+ .map_io = torbreck_map_io,
+ .init_machine = torbreck_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
--- /dev/null
+/* linux/arch/arm/mach-s5pv210/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV210 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-clock.h>
+
+static struct sleep_save s5pv210_core_save[] = {
+ /* Clock source */
+ SAVE_ITEM(S5P_CLK_SRC0),
+ SAVE_ITEM(S5P_CLK_SRC1),
+ SAVE_ITEM(S5P_CLK_SRC2),
+ SAVE_ITEM(S5P_CLK_SRC3),
+ SAVE_ITEM(S5P_CLK_SRC4),
+ SAVE_ITEM(S5P_CLK_SRC5),
+ SAVE_ITEM(S5P_CLK_SRC6),
+
+ /* Clock source Mask */
+ SAVE_ITEM(S5P_CLK_SRC_MASK0),
+ SAVE_ITEM(S5P_CLK_SRC_MASK1),
+
+ /* Clock Divider */
+ SAVE_ITEM(S5P_CLK_DIV0),
+ SAVE_ITEM(S5P_CLK_DIV1),
+ SAVE_ITEM(S5P_CLK_DIV2),
+ SAVE_ITEM(S5P_CLK_DIV3),
+ SAVE_ITEM(S5P_CLK_DIV4),
+ SAVE_ITEM(S5P_CLK_DIV5),
+ SAVE_ITEM(S5P_CLK_DIV6),
+ SAVE_ITEM(S5P_CLK_DIV7),
+
+ /* Clock Main Gate */
+ SAVE_ITEM(S5P_CLKGATE_MAIN0),
+ SAVE_ITEM(S5P_CLKGATE_MAIN1),
+ SAVE_ITEM(S5P_CLKGATE_MAIN2),
+
+ /* Clock source Peri Gate */
+ SAVE_ITEM(S5P_CLKGATE_PERI0),
+ SAVE_ITEM(S5P_CLKGATE_PERI1),
+
+ /* Clock source SCLK Gate */
+ SAVE_ITEM(S5P_CLKGATE_SCLK0),
+ SAVE_ITEM(S5P_CLKGATE_SCLK1),
+
+ /* Clock IP Clock gate */
+ SAVE_ITEM(S5P_CLKGATE_IP0),
+ SAVE_ITEM(S5P_CLKGATE_IP1),
+ SAVE_ITEM(S5P_CLKGATE_IP2),
+ SAVE_ITEM(S5P_CLKGATE_IP3),
+ SAVE_ITEM(S5P_CLKGATE_IP4),
+
+ /* Clock Blcok and Bus gate */
+ SAVE_ITEM(S5P_CLKGATE_BLOCK),
+ SAVE_ITEM(S5P_CLKGATE_BUS0),
+
+ /* Clock ETC */
+ SAVE_ITEM(S5P_CLK_OUT),
+ SAVE_ITEM(S5P_MDNIE_SEL),
+
+ /* PWM Register */
+ SAVE_ITEM(S3C2410_TCFG0),
+ SAVE_ITEM(S3C2410_TCFG1),
+ SAVE_ITEM(S3C64XX_TINT_CSTAT),
+ SAVE_ITEM(S3C2410_TCON),
+ SAVE_ITEM(S3C2410_TCNTB(0)),
+ SAVE_ITEM(S3C2410_TCMPB(0)),
+ SAVE_ITEM(S3C2410_TCNTO(0)),
+};
+
+void s5pv210_cpu_suspend(void)
+{
+ unsigned long tmp;
+
+ /* issue the standby signal into the pm unit. Note, we
+ * issue a write-buffer drain just in case */
+
+ tmp = 0;
+
+ asm("b 1f\n\t"
+ ".align 5\n\t"
+ "1:\n\t"
+ "mcr p15, 0, %0, c7, c10, 5\n\t"
+ "mcr p15, 0, %0, c7, c10, 4\n\t"
+ "wfi" : : "r" (tmp));
+
+ /* we should never get past here */
+ panic("sleep resumed to originator?");
+}
+
+static void s5pv210_pm_prepare(void)
+{
+ unsigned int tmp;
+
+ /* ensure at least INFORM0 has the resume address */
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+
+ tmp = __raw_readl(S5P_SLEEP_CFG);
+ tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
+ __raw_writel(tmp, S5P_SLEEP_CFG);
+
+ /* WFI for SLEEP mode configuration by SYSCON */
+ tmp = __raw_readl(S5P_PWR_CFG);
+ tmp &= S5P_CFG_WFI_CLEAN;
+ tmp |= S5P_CFG_WFI_SLEEP;
+ __raw_writel(tmp, S5P_PWR_CFG);
+
+ /* SYSCON interrupt handling disable */
+ tmp = __raw_readl(S5P_OTHERS);
+ tmp |= S5P_OTHER_SYSC_INTOFF;
+ __raw_writel(tmp, S5P_OTHERS);
+
+ s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
+}
+
+static int s5pv210_pm_add(struct sys_device *sysdev)
+{
+ pm_cpu_prep = s5pv210_pm_prepare;
+ pm_cpu_sleep = s5pv210_cpu_suspend;
+
+ return 0;
+}
+
+static int s5pv210_pm_resume(struct sys_device *dev)
+{
+ u32 tmp;
+
+ tmp = __raw_readl(S5P_OTHERS);
+ tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\
+ S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
+ __raw_writel(tmp , S5P_OTHERS);
+
+ s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
+
+ return 0;
+}
+
+static struct sysdev_driver s5pv210_pm_driver = {
+ .add = s5pv210_pm_add,
+ .resume = s5pv210_pm_resume,
+};
+
+static __init int s5pv210_pm_drvinit(void)
+{
+ return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
+}
+arch_initcall(s5pv210_pm_drvinit);
#include <mach/regs-clock.h>
#include <plat/gpio-cfg.h>
-void s5pv210_fb_gpio_setup_24bpp(void)
+static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
{
- unsigned int gpio = 0;
-
- for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
- for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ for (; nr > 0; nr--, base++)
+ s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
- for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
- for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+void s5pv210_fb_gpio_setup_24bpp(void)
+{
+ s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
+ s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
+ s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
+ s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
/* Set DISPLAY_CONTROL register for Display path selection.
*
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c2_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
#include <plat/gpio-cfg.h>
+static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
+{
+ s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
+
+ for (; nr > 0; nr--, base++)
+ s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
+
void s5pv210_ide_setup_gpio(void)
{
- unsigned int gpio = 0;
-
- for (gpio = S5PV210_GPJ0(0); gpio <= S5PV210_GPJ0(7); gpio++) {
- /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST,
- CF_DMACK */
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
-
- for (gpio = S5PV210_GPJ2(0); gpio <= S5PV210_GPJ2(7); gpio++) {
- /*CF_Data[0 - 7] */
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
-
- for (gpio = S5PV210_GPJ3(0); gpio <= S5PV210_GPJ3(7); gpio++) {
- /* CF_Data[8 - 15] */
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
-
- for (gpio = S5PV210_GPJ4(0); gpio <= S5PV210_GPJ4(3); gpio++) {
- /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
- }
+ /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
+ s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
+
+ /* CF_Data[0 - 7] */
+ s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
+
+ /* CF_Data[8 - 15] */
+ s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
+
+ /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
+ s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
}
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
- unsigned int gpio, end;
-
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
- end = S5PV210_GPH3(rows);
- for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
- end = S5PV210_GPH2(cols);
- for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
}
void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
- for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
+
switch (width) {
case 8:
/* GPG1[3:6] special-funtion 3 */
- for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
case 4:
/* GPG0[3:6] special-funtion 2 */
- for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
default:
break;
}
void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
/* Set all the necessary GPG1[0:1] pins to special-function 2 */
- for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
/* Data pin GPG1[3:6] to special-function 2 */
- for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
/* Set all the necessary GPG2[0:1] pins to special-function 2 */
- for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
switch (width) {
case 8:
/* Data pin GPG3[3:6] to special-function 3 */
- for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
case 4:
/* Data pin GPG2[3:6] to special-function 2 */
- for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
default:
break;
}
void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
- unsigned int gpio;
- /* Set all the necessary GPG3[0:2] pins to special-function 2 */
- for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ /* Set all the necessary GPG3[0:1] pins to special-function 2 */
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
/* Data pin GPG3[3:6] to special-function 2 */
- for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
- s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
+ s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
--- /dev/null
+/* linux/arch/arm/plat-s5p/sleep.S
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV210 power Manager (Suspend-To-RAM) support
+ * Based on S3C2410 sleep code by:
+ * Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ * Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+ .text
+
+ /* s3c_cpu_save
+ *
+ * entry:
+ * r0 = save address (virtual addr of s3c_sleep_save_phys)
+ */
+
+ENTRY(s3c_cpu_save)
+
+ stmfd sp!, { r3 - r12, lr }
+
+ mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
+ mrc p15, 0, r5, c3, c0, 0 @ Domain ID
+ mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
+ mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
+ mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
+ mrc p15, 0, r9, c1, c0, 0 @ Control register
+ mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+ mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
+ mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
+ mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
+
+ stmia r0, { r3 - r13 }
+
+ bl s3c_pm_cb_flushcache
+
+ ldr r0, =pm_cpu_sleep
+ ldr r0, [ r0 ]
+ mov pc, r0
+
+resume_with_mmu:
+ /*
+ * After MMU is turned on, restore the previous MMU table.
+ */
+ ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
+ add r4, r4, r9
+ str r12, [r4]
+
+ ldmfd sp!, { r3 - r12, pc }
+
+ .ltorg
+
+ .data
+
+ .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
+ .word 0
+
+ /* sleep magic, to allow the bootloader to check for an valid
+ * image to resume to. Must be the first word before the
+ * s3c_cpu_resume entry.
+ */
+
+ .word 0x2bedf00d
+
+ /* s3c_cpu_resume
+ *
+ * resume code entry for bootloader to call
+ *
+ * we must put this code here in the data segment as we have no
+ * other way of restoring the stack pointer after sleep, and we
+ * must not write to the code segment (code is read-only)
+ */
+
+ENTRY(s3c_cpu_resume)
+ mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+ msr cpsr_c, r0
+
+ mov r1, #0
+ mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
+ mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
+
+ ldr r0, s3c_sleep_save_phys @ address of restore block
+ ldmia r0, { r3 - r13 }
+
+ mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
+ mcr p15, 0, r5, c3, c0, 0 @ Domain ID
+
+ mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
+ mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
+ mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
+
+ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
+
+ mov r0, #0 @ restore copro access
+ mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
+ mcr p15, 0, r0, c7, c5, 4
+
+ mcr p15, 0, r12, c10, c2, 0 @ write PRRR
+ mcr p15, 0, r3, c10, c2, 1 @ write NMRR
+
+ /*
+ * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
+ * And there are no valid entries in the MMU table at this point.
+ * So before turning on the MMU, the MMU entry for the DRAM address
+ * range is added. After the MMU is turned on, the other entries
+ * in the MMU table will be restored.
+ */
+
+ /* r6 = Translation Table BASE0 */
+ mov r4, r6
+ mov r4, r4, LSR #14
+ mov r4, r4, LSL #14
+
+ /* Load address for adding to MMU table list */
+ ldr r11, =0xE010F000 @ INFORM0 reg.
+ ldr r10, [r11, #0]
+ mov r10, r10, LSR #18
+ bic r10, r10, #0x3
+ orr r4, r4, r10
+
+ /* Calculate MMU table entry */
+ mov r10, r10, LSL #18
+ ldr r5, =0x40E
+ orr r10, r10, r5
+
+ /* Back up originally data */
+ ldr r12, [r4]
+
+ /* Add calculated MMU table entry into MMU table list */
+ str r10, [r4]
+
+ ldr r2, =resume_with_mmu
+ mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
+
+ nop
+ nop
+ nop
+ nop
+ nop @ second-to-last before mmu
+
+ mov pc, r2 @ go back to virtual address
+
+ .ltorg
config CPU_S5PV310
bool
- select PLAT_S5P
help
Enable S5PV310 CPU support
help
Common setup code for i2c bus 2.
+config S5PV310_SETUP_I2C3
+ bool
+ help
+ Common setup code for i2c bus 3.
+
+config S5PV310_SETUP_I2C4
+ bool
+ help
+ Common setup code for i2c bus 4.
+
+config S5PV310_SETUP_I2C5
+ bool
+ help
+ Common setup code for i2c bus 5.
+
+config S5PV310_SETUP_I2C6
+ bool
+ help
+ Common setup code for i2c bus 6.
+
+config S5PV310_SETUP_I2C7
+ bool
+ help
+ Common setup code for i2c bus 7.
+
+config S5PV310_SETUP_SDHCI
+ bool
+ select S5PV310_SETUP_SDHCI_GPIO
+ help
+ Internal helper functions for S5PV310 based SDHCI systems.
+
+config S5PV310_SETUP_SDHCI_GPIO
+ bool
+ help
+ Common setup code for SDHCI gpio.
+
# machine support
-config MACH_SMDKV310
- bool "SMDKV310"
+menu "S5PC210 Machines"
+
+config MACH_SMDKC210
+ bool "SMDKC210"
select CPU_S5PV310
- select ARCH_SPARSEMEM_ENABLE
+ select S3C_DEV_RTC
+ select S3C_DEV_WDT
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_HSMMC3
+ select S5PV310_SETUP_SDHCI
help
- Machine support for Samsung SMDKV310
+ Machine support for Samsung SMDKC210
+ S5PC210(MCP) is one of package option of S5PV310
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_S5PV310
- select ARCH_SPARSEMEM_ENABLE
+ select S5P_DEV_ONENAND
+ select S3C_DEV_I2C1
+ select S5PV310_SETUP_I2C1
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board. S5PC210(MCP) is one of package option of S5PV310
+endmenu
+
+menu "S5PV310 Machines"
+
+config MACH_SMDKV310
+ bool "SMDKV310"
+ select CPU_S5PV310
+ select S3C_DEV_RTC
+ select S3C_DEV_WDT
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_HSMMC3
+ select S5PV310_SETUP_SDHCI
+ help
+ Machine support for Samsung SMDKV310
+
+endmenu
+
+comment "Configuration for HSMMC bus width"
+
+menu "Use 8-bit bus width"
+
+config S5PV310_SDHCI_CH0_8BIT
+ bool "Channel 0 with 8-bit bus"
+ help
+ Support HSMMC Channel 0 8-bit bus.
+ If selected, Channel 1 is disabled.
+
+config S5PV310_SDHCI_CH2_8BIT
+ bool "Channel 2 with 8-bit bus"
+ help
+ Support HSMMC Channel 2 8-bit bus.
+ If selected, Channel 3 is disabled.
+
+endmenu
+
endif
# Core support for S5PV310 system
obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o
+obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
# machine support
+obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
+obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
+obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
+obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
+obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
+obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
.rate = 27000000,
};
+static struct clk clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+ .id = -1,
+};
+
+static struct clk clk_sclk_usbphy0 = {
+ .name = "sclk_usbphy0",
+ .id = -1,
+ .rate = 27000000,
+};
+
+static struct clk clk_sclk_usbphy1 = {
+ .name = "sclk_usbphy1",
+ .id = -1,
+};
+
+static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+}
+
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
+static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+}
+
+static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+}
+
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
+static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
+}
+
/* Core list of CMU_CPU side */
static struct clksrc_clk clk_mout_apll = {
};
static struct clk *clkset_moutcore_list[] = {
- [0] = &clk_sclk_apll.clk,
+ [0] = &clk_mout_apll.clk,
[1] = &clk_mout_mpll.clk,
};
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
};
-static struct clksrc_clk clk_atclk = {
- .clk = {
- .name = "atclk",
- .id = -1,
- .parent = &clk_moutcore.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_dbg = {
- .clk = {
- .name = "pclk_dbg",
- .id = -1,
- .parent = &clk_atclk.clk,
- },
- .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
-};
-
/* Core list of CMU_CORE side */
static struct clk *clkset_corebus_list[] = {
[1] = &clk_sclk_apll.clk,
};
-static struct clksrc_sources clkset_aclk_200 = {
+static struct clksrc_sources clkset_aclk = {
.sources = clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
};
.name = "aclk_200",
.id = -1,
},
- .sources = &clkset_aclk_200,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
};
-static struct clksrc_sources clkset_aclk_100 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_100 = {
.clk = {
.name = "aclk_100",
.id = -1,
},
- .sources = &clkset_aclk_100,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
};
-static struct clksrc_sources clkset_aclk_160 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_160 = {
.clk = {
.name = "aclk_160",
.id = -1,
},
- .sources = &clkset_aclk_160,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
};
-static struct clksrc_sources clkset_aclk_133 = {
- .sources = clkset_aclk_top_list,
- .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
static struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
.id = -1,
},
- .sources = &clkset_aclk_133,
+ .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
};
.clk = {
.name = "vpll_src",
.id = -1,
+ .enable = s5pv310_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
},
.sources = &clkset_vpllsrc,
.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
- }
+ }, {
+ .name = "csis",
+ .id = 0,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "csis",
+ .id = 1,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "fimc",
+ .id = 0,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimc",
+ .id = 1,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "fimc",
+ .id = 2,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "fimc",
+ .id = 3,
+ .enable = s5pv310_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "fimd",
+ .id = 0,
+ .enable = s5pv310_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimd",
+ .id = 1,
+ .enable = s5pv310_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hsmmc",
+ .id = 0,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "hsmmc",
+ .id = 1,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "hsmmc",
+ .id = 2,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "hsmmc",
+ .id = 3,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "hsmmc",
+ .id = 4,
+ .parent = &clk_aclk_133.clk,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "sata",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "adc",
+ .id = -1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "rtc",
+ .id = -1,
+ .enable = s5pv310_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "watchdog",
+ .id = -1,
+ .enable = s5pv310_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "usbhost",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "otg",
+ .id = -1,
+ .enable = s5pv310_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "spi",
+ .id = 0,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .id = 1,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .id = 2,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "fimg2d",
+ .id = -1,
+ .enable = s5pv310_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .id = 0,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .id = 1,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .id = 2,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .id = 3,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .id = 4,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .id = 5,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .id = 6,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .id = 7,
+ .parent = &clk_aclk_100.clk,
+ .enable = s5pv310_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 13),
+ },
};
static struct clk init_clocks[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &clk_sclk_hdmi27m,
+ [3] = &clk_sclk_usbphy0,
+ [4] = &clk_sclk_usbphy1,
+ [5] = &clk_sclk_hdmiphy,
[6] = &clk_mout_mpll.clk,
[7] = &clk_mout_epll.clk,
[8] = &clk_sclk_vpll.clk,
.nr_sources = ARRAY_SIZE(clkset_group_list),
};
+static struct clk *clkset_mout_g2d0_list[] = {
+ [0] = &clk_mout_mpll.clk,
+ [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d0 = {
+ .sources = clkset_mout_g2d0_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk clk_mout_g2d0 = {
+ .clk = {
+ .name = "mout_g2d0",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d0,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d1_list[] = {
+ [0] = &clk_mout_epll.clk,
+ [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d1 = {
+ .sources = clkset_mout_g2d1_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk clk_mout_g2d1 = {
+ .clk = {
+ .name = "mout_g2d1",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d1,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d_list[] = {
+ [0] = &clk_mout_g2d0.clk,
+ [1] = &clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d = {
+ .sources = clkset_mout_g2d_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
+};
+
+static struct clksrc_clk clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ .id = -1,
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
- },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 2,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .id = 3,
+ .enable = s5pv310_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_sata",
+ .id = -1,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_mout_corebus,
+ .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 0,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 1,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_spi",
+ .id = 2,
+ .enable = s5pv310_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &clkset_group,
+ .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimg2d",
+ .id = -1,
+ },
+ .sources = &clkset_mout_g2d,
+ .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 0,
+ .parent = &clk_dout_mmc0.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 1,
+ .parent = &clk_dout_mmc1.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 2,
+ .parent = &clk_dout_mmc2.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 3,
+ .parent = &clk_dout_mmc3.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+ }, {
+ .clk = {
+ .name = "sclk_mmc",
+ .id = 4,
+ .parent = &clk_dout_mmc4.clk,
+ .enable = s5pv310_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+ }
};
/* Clock initialization code */
&clk_aclk_cores,
&clk_aclk_corem1,
&clk_periphclk,
- &clk_atclk,
- &clk_pclk_dbg,
&clk_mout_corebus,
&clk_sclk_dmc,
&clk_aclk_cored,
&clk_aclk_100,
&clk_aclk_160,
&clk_aclk_133,
+ &clk_dout_mmc0,
+ &clk_dout_mmc1,
+ &clk_dout_mmc2,
+ &clk_dout_mmc3,
+ &clk_dout_mmc4,
};
void __init_or_cpufreq s5pv310_setup_clocks(void)
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
- unsigned long aclk_corem0;
- unsigned long aclk_cores;
- unsigned long aclk_corem1;
- unsigned long periphclk;
unsigned long sclk_dmc;
- unsigned long aclk_cored;
- unsigned long aclk_corep;
- unsigned long aclk_acp;
- unsigned long pclk_acp;
+ unsigned long aclk_200;
+ unsigned long aclk_100;
+ unsigned long aclk_160;
+ unsigned long aclk_133;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
apll, mpll, epll, vpll);
armclk = clk_get_rate(&clk_armclk.clk);
- aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
- aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
- aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
- periphclk = clk_get_rate(&clk_periphclk.clk);
sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
- aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
- aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
- aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
- pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
-
- printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
- "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
- "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
- armclk, aclk_corem0, aclk_cores, aclk_corem1,
- periphclk, sclk_dmc, aclk_cored, aclk_corep,
- aclk_acp, pclk_acp);
+
+ aclk_200 = clk_get_rate(&clk_aclk_200.clk);
+ aclk_100 = clk_get_rate(&clk_aclk_100.clk);
+ aclk_160 = clk_get_rate(&clk_aclk_160.clk);
+ aclk_133 = clk_get_rate(&clk_aclk_133.clk);
+
+ printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+ "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+ armclk, sclk_dmc, aclk_200,
+ aclk_100, aclk_160, aclk_133);
clk_f.rate = armclk;
clk_h.rate = sclk_dmc;
- clk_p.rate = periphclk;
+ clk_p.rate = aclk_100;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
#include <asm/mach/irq.h>
#include <asm/proc-fns.h>
+#include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/s5pv310.h>
+#include <plat/sdhci.h>
#include <mach/regs-irq.h>
.length = SZ_4K,
.type = MT_DEVICE,
}, {
- .virtual = (unsigned long)S5P_VA_GPIO,
+ .virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GPIO2,
+ .pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GPIO3,
+ .pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
+ .length = SZ_256,
+ .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_UART,
.pfn = __phys_to_pfn(S3C_PA_UART),
.length = SZ_512K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_SROMC,
+ .pfn = __phys_to_pfn(S5PV310_PA_SROMC),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
},
};
void __init s5pv310_map_io(void)
{
iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
+
+ /* initialize device information early */
+ s5pv310_default_sdhci0();
+ s5pv310_default_sdhci1();
+ s5pv310_default_sdhci2();
+ s5pv310_default_sdhci3();
}
void __init s5pv310_init_clocks(int xtal)
core_initcall(s5pv310_core_init);
+#ifdef CONFIG_CACHE_L2X0
+static int __init s5pv310_l2x0_cache_init(void)
+{
+ /* TAG, Data Latency Control: 2cycle */
+ __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+ __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+ /* L2X0 Prefetch Control */
+ __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+ /* L2X0 Power Control */
+ __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+ S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+ l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+
+ return 0;
+}
+
+early_initcall(s5pv310_l2x0_cache_init);
+#endif
+
int __init s5pv310_init(void)
{
printk(KERN_INFO "S5PV310: Initializing architecture\n");
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/gpiolib.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV310 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+static struct s3c_gpio_cfg gpio_cfg = {
+ .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+ .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+/*
+ * Following are the gpio banks in v310.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
+static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
+ {
+ .chip = {
+ .base = S5PV310_GPA0(0),
+ .ngpio = S5PV310_GPIO_A0_NR,
+ .label = "GPA0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPA1(0),
+ .ngpio = S5PV310_GPIO_A1_NR,
+ .label = "GPA1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPB(0),
+ .ngpio = S5PV310_GPIO_B_NR,
+ .label = "GPB",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPC0(0),
+ .ngpio = S5PV310_GPIO_C0_NR,
+ .label = "GPC0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPC1(0),
+ .ngpio = S5PV310_GPIO_C1_NR,
+ .label = "GPC1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPD0(0),
+ .ngpio = S5PV310_GPIO_D0_NR,
+ .label = "GPD0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPD1(0),
+ .ngpio = S5PV310_GPIO_D1_NR,
+ .label = "GPD1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPE0(0),
+ .ngpio = S5PV310_GPIO_E0_NR,
+ .label = "GPE0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPE1(0),
+ .ngpio = S5PV310_GPIO_E1_NR,
+ .label = "GPE1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPE2(0),
+ .ngpio = S5PV310_GPIO_E2_NR,
+ .label = "GPE2",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPE3(0),
+ .ngpio = S5PV310_GPIO_E3_NR,
+ .label = "GPE3",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPE4(0),
+ .ngpio = S5PV310_GPIO_E4_NR,
+ .label = "GPE4",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPF0(0),
+ .ngpio = S5PV310_GPIO_F0_NR,
+ .label = "GPF0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPF1(0),
+ .ngpio = S5PV310_GPIO_F1_NR,
+ .label = "GPF1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPF2(0),
+ .ngpio = S5PV310_GPIO_F2_NR,
+ .label = "GPF2",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPF3(0),
+ .ngpio = S5PV310_GPIO_F3_NR,
+ .label = "GPF3",
+ },
+ },
+};
+
+static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
+ {
+ .chip = {
+ .base = S5PV310_GPJ0(0),
+ .ngpio = S5PV310_GPIO_J0_NR,
+ .label = "GPJ0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPJ1(0),
+ .ngpio = S5PV310_GPIO_J1_NR,
+ .label = "GPJ1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPK0(0),
+ .ngpio = S5PV310_GPIO_K0_NR,
+ .label = "GPK0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPK1(0),
+ .ngpio = S5PV310_GPIO_K1_NR,
+ .label = "GPK1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPK2(0),
+ .ngpio = S5PV310_GPIO_K2_NR,
+ .label = "GPK2",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPK3(0),
+ .ngpio = S5PV310_GPIO_K3_NR,
+ .label = "GPK3",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPL0(0),
+ .ngpio = S5PV310_GPIO_L0_NR,
+ .label = "GPL0",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPL1(0),
+ .ngpio = S5PV310_GPIO_L1_NR,
+ .label = "GPL1",
+ },
+ }, {
+ .chip = {
+ .base = S5PV310_GPL2(0),
+ .ngpio = S5PV310_GPIO_L2_NR,
+ .label = "GPL2",
+ },
+ }, {
+ .base = (S5P_VA_GPIO2 + 0xC00),
+ .config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(0),
+ .chip = {
+ .base = S5PV310_GPX0(0),
+ .ngpio = S5PV310_GPIO_X0_NR,
+ .label = "GPX0",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO2 + 0xC20),
+ .config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(8),
+ .chip = {
+ .base = S5PV310_GPX1(0),
+ .ngpio = S5PV310_GPIO_X1_NR,
+ .label = "GPX1",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO2 + 0xC40),
+ .config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(16),
+ .chip = {
+ .base = S5PV310_GPX2(0),
+ .ngpio = S5PV310_GPIO_X2_NR,
+ .label = "GPX2",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ }, {
+ .base = (S5P_VA_GPIO2 + 0xC60),
+ .config = &gpio_cfg_noint,
+ .irq_base = IRQ_EINT(24),
+ .chip = {
+ .base = S5PV310_GPX3(0),
+ .ngpio = S5PV310_GPIO_X3_NR,
+ .label = "GPX3",
+ .to_irq = samsung_gpiolib_to_irq,
+ },
+ },
+};
+
+static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
+ {
+ .chip = {
+ .base = S5PV310_GPZ(0),
+ .ngpio = S5PV310_GPIO_Z_NR,
+ .label = "GPZ",
+ },
+ },
+};
+
+static __init int s5pv310_gpiolib_init(void)
+{
+ struct s3c_gpio_chip *chip;
+ int i;
+ int nr_chips;
+
+ /* GPIO part 1 */
+
+ chip = s5pv310_gpio_part1_4bit;
+ nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
+
+ for (i = 0; i < nr_chips; i++, chip++) {
+ if (chip->config == NULL)
+ chip->config = &gpio_cfg;
+ if (chip->base == NULL)
+ chip->base = S5P_VA_GPIO1 + (i) * 0x20;
+ }
+
+ samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
+
+ /* GPIO part 2 */
+
+ chip = s5pv310_gpio_part2_4bit;
+ nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
+
+ for (i = 0; i < nr_chips; i++, chip++) {
+ if (chip->config == NULL)
+ chip->config = &gpio_cfg;
+ if (chip->base == NULL)
+ chip->base = S5P_VA_GPIO2 + (i) * 0x20;
+ }
+
+ samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
+
+ /* GPIO part 3 */
+
+ chip = s5pv310_gpio_part3_4bit;
+ nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
+
+ for (i = 0; i < nr_chips; i++, chip++) {
+ if (chip->config == NULL)
+ chip->config = &gpio_cfg;
+ if (chip->base == NULL)
+ chip->base = S5P_VA_GPIO3 + (i) * 0x20;
+ }
+
+ samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
+
+ return 0;
+}
+core_initcall(s5pv310_gpiolib_init);
--- /dev/null
+/* linux arch/arm/mach-s5pv310/hotplug.c
+ *
+ * Cloned from linux/arch/arm/mach-realview/hotplug.c
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ " mcr p15, 0, %1, c7, c5, 0\n"
+ " mcr p15, 0, %1, c7, c10, 4\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, #0x04\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0)
+ : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile(
+ "mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, #0x04\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, #0x20\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ :
+ : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+ /*
+ * there is no power-control hardware on this platform, so all
+ * we can do is put the core into WFI; this is safe as the calling
+ * code will have already disabled interrupts
+ */
+ for (;;) {
+ /*
+ * here's the WFI
+ */
+ asm(".word 0xe320f003\n"
+ :
+ :
+ : "memory", "cc");
+
+ if (pen_release == cpu) {
+ /*
+ * OK, proper wakeup, we're done
+ */
+ break;
+ }
+
+ /*
+ * getting here, means that we have come out of WFI without
+ * having been woken up - this shouldn't happen
+ *
+ * The trouble is, letting people know about this is not really
+ * possible, since we are currently running incoherently, and
+ * therefore cannot safely call printk() or anything else
+ */
+#ifdef DEBUG
+ printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
+#endif
+ }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+ unsigned int this_cpu = hard_smp_processor_id();
+
+ if (cpu != this_cpu) {
+ printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+ this_cpu, cpu);
+ BUG();
+ }
+#endif
+
+ printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+ complete(&cpu_killed);
+
+ /*
+ * we're ready for shutdown now, so do it
+ */
+ cpu_enter_lowpower();
+ platform_do_lowpower(cpu);
+
+ /*
+ * bring this CPU back into the world of cache
+ * coherency, and then restore interrupts
+ */
+ cpu_leave_lowpower();
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ /*
+ * we don't allow CPU 0 to be shutdown (it is still too special
+ * e.g. clock tick interrupts)
+ */
+ return cpu == 0 ? -EPERM : 0;
+}
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
- * S5PV210 - IRQ definitions
+ * S5PV310 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
+#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
+#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
+
#define IRQ_UART0 COMBINER_IRQ(26, 0)
#define IRQ_UART1 COMBINER_IRQ(26, 1)
#define IRQ_UART2 COMBINER_IRQ(26, 2)
#define IRQ_UART4 COMBINER_IRQ(26, 4)
#define IRQ_IIC COMBINER_IRQ(27, 0)
+#define IRQ_IIC1 COMBINER_IRQ(27, 1)
+#define IRQ_IIC2 COMBINER_IRQ(27, 2)
+#define IRQ_IIC3 COMBINER_IRQ(27, 3)
+#define IRQ_IIC4 COMBINER_IRQ(27, 4)
+#define IRQ_IIC5 COMBINER_IRQ(27, 5)
+#define IRQ_IIC6 COMBINER_IRQ(27, 6)
+#define IRQ_IIC7 COMBINER_IRQ(27, 7)
+
+#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
+#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
+#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
+#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
-/* Set the default NR_IRQS */
+#define IRQ_EINT4 COMBINER_IRQ(37, 0)
+#define IRQ_EINT5 COMBINER_IRQ(37, 1)
+#define IRQ_EINT6 COMBINER_IRQ(37, 2)
+#define IRQ_EINT7 COMBINER_IRQ(37, 3)
+#define IRQ_EINT8 COMBINER_IRQ(38, 0)
+
+#define IRQ_EINT9 COMBINER_IRQ(38, 1)
+#define IRQ_EINT10 COMBINER_IRQ(38, 2)
+#define IRQ_EINT11 COMBINER_IRQ(38, 3)
+#define IRQ_EINT12 COMBINER_IRQ(38, 4)
+#define IRQ_EINT13 COMBINER_IRQ(38, 5)
+#define IRQ_EINT14 COMBINER_IRQ(38, 6)
+#define IRQ_EINT15 COMBINER_IRQ(38, 7)
+
+#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
-#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define MAX_COMBINER_NR 40
+
+#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
+
+/* Set the default NR_IRQS */
-#define MAX_COMBINER_NR 39
+#define NR_IRQS (S5P_IRQ_EINT_BASE + 32)
#endif /* __ASM_ARCH_IRQS_H */
#define S5PV310_PA_SYSRAM (0x02025000)
+#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
+
#define S5PC210_PA_ONENAND (0x0C000000)
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
-#define S5PV310_PA_SYSCON (0x10020000)
+#define S5PV310_PA_SYSCON (0x10010000)
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5PV310_PA_CMU (0x10030000)
#define S5PV310_PA_WATCHDOG (0x10060000)
+#define S5PV310_PA_RTC (0x10070000)
#define S5PV310_PA_COMBINER (0x10448000)
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
+#define S5PV310_PA_SROMC (0x12570000)
+
#define S5PV310_PA_UART (0x13800000)
#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_SZ_UART SZ_256
-#define S5PV310_PA_IIC0 (0x13860000)
+#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define S5PV310_PA_TIMER (0x139D0000)
#define S5P_PA_TIMER S5PV310_PA_TIMER
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
-#define S3C_PA_IIC S5PV310_PA_IIC0
+#define S3C_PA_IIC S5PV310_PA_IIC(0)
+#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
+#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
+#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
+#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
+#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
+#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
+#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
+#define S3C_PA_RTC S5PV310_PA_RTC
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
#endif /* __ASM_ARCH_MAP_H */
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
-
+#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
+#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
+#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
+#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
-
+#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
+#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
+#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
+#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
+#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
+#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
+#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
+#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
+#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
+#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
+#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
+#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
+#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
+#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
+/* Compatibility defines */
+
+#define S5P_EPLL_CON S5P_EPLL_CON0
+
#endif /* __ASM_ARCH_REGS_CLOCK_H */
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV310 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
+#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
+
+#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
+#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
+
+#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
+#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
+
+#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
+#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE S3C_GPIO_SFN(0xf)
+
+#define EINT_GPIO_0(x) S5PV310_GPX0(x)
+#define EINT_GPIO_1(x) S5PV310_GPX1(x)
+#define EINT_GPIO_2(x) S5PV310_GPX2(x)
+#define EINT_GPIO_3(x) S5PV310_GPX3(x)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV310 - SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SROM_H
+#define __ASM_ARCH_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
+
+#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
+#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
+#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
+#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
+#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
+#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
+#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
+#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
+
+#define S5PV310_SROM_BW__CS_MASK 0xf
+
+#define S5PV310_SROM_BW__NCS0__SHIFT 0
+#define S5PV310_SROM_BW__NCS1__SHIFT 4
+#define S5PV310_SROM_BW__NCS2__SHIFT 8
+#define S5PV310_SROM_BW__NCS3__SHIFT 12
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5PV310_SROM_BCX__PMC__SHIFT 0
+#define S5PV310_SROM_BCX__TACP__SHIFT 4
+#define S5PV310_SROM_BCX__TCAH__SHIFT 8
+#define S5PV310_SROM_BCX__TCOH__SHIFT 12
+#define S5PV310_SROM_BCX__TACC__SHIFT 16
+#define S5PV310_SROM_BCX__TCOS__SHIFT 24
+#define S5PV310_SROM_BCX__TACS__SHIFT 28
+
+#endif /* __ASM_ARCH_REGS_SROM_H */
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END (0xF0000000UL)
+#define VMALLOC_END 0xF6000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
if (status == 0)
goto out;
- for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) {
- if (status & 0x1)
- break;
- status >>= 1;
- }
+ combiner_irq = __ffs(status);
cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
if (unlikely(cascade_irq >= NR_IRQS))
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/irq-eint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5PV310 - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <plat/pm.h>
+#include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+
+static DEFINE_SPINLOCK(eint_lock);
+
+static unsigned int eint0_15_data[16];
+
+static unsigned int s5pv310_get_irq_nr(unsigned int number)
+{
+ u32 ret = 0;
+
+ switch (number) {
+ case 0 ... 3:
+ ret = (number + IRQ_EINT0);
+ break;
+ case 4 ... 7:
+ ret = (number + (IRQ_EINT4 - 4));
+ break;
+ case 8 ... 15:
+ ret = (number + (IRQ_EINT8 - 8));
+ break;
+ default:
+ printk(KERN_ERR "number available : %d\n", number);
+ }
+
+ return ret;
+}
+
+static inline void s5pv310_irq_eint_mask(unsigned int irq)
+{
+ u32 mask;
+
+ spin_lock(&eint_lock);
+ mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+ mask |= eint_irq_to_bit(irq);
+ __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+ spin_unlock(&eint_lock);
+}
+
+static void s5pv310_irq_eint_unmask(unsigned int irq)
+{
+ u32 mask;
+
+ spin_lock(&eint_lock);
+ mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+ mask &= ~(eint_irq_to_bit(irq));
+ __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+ spin_unlock(&eint_lock);
+}
+
+static inline void s5pv310_irq_eint_ack(unsigned int irq)
+{
+ __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+}
+
+static void s5pv310_irq_eint_maskack(unsigned int irq)
+{
+ s5pv310_irq_eint_mask(irq);
+ s5pv310_irq_eint_ack(irq);
+}
+
+static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+ int offs = EINT_OFFSET(irq);
+ int shift;
+ u32 ctrl, mask;
+ u32 newvalue = 0;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+ break;
+
+ case IRQ_TYPE_EDGE_FALLING:
+ newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+ break;
+
+ case IRQ_TYPE_EDGE_BOTH:
+ newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+ break;
+
+ case IRQ_TYPE_LEVEL_LOW:
+ newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+ break;
+
+ case IRQ_TYPE_LEVEL_HIGH:
+ newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+ break;
+
+ default:
+ printk(KERN_ERR "No such irq type %d", type);
+ return -EINVAL;
+ }
+
+ shift = (offs & 0x7) * 4;
+ mask = 0x7 << shift;
+
+ spin_lock(&eint_lock);
+ ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+ ctrl &= ~mask;
+ ctrl |= newvalue << shift;
+ __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+ spin_unlock(&eint_lock);
+
+ switch (offs) {
+ case 0 ... 7:
+ s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+ break;
+ case 8 ... 15:
+ s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+ break;
+ case 16 ... 23:
+ s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+ break;
+ case 24 ... 31:
+ s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+ break;
+ default:
+ printk(KERN_ERR "No such irq number %d", offs);
+ }
+
+ return 0;
+}
+
+static struct irq_chip s5pv310_irq_eint = {
+ .name = "s5pv310-eint",
+ .mask = s5pv310_irq_eint_mask,
+ .unmask = s5pv310_irq_eint_unmask,
+ .mask_ack = s5pv310_irq_eint_maskack,
+ .ack = s5pv310_irq_eint_ack,
+ .set_type = s5pv310_irq_eint_set_type,
+#ifdef CONFIG_PM
+ .set_wake = s3c_irqext_wake,
+#endif
+};
+
+/* s5pv310_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void s5pv310_irq_demux_eint(unsigned int start)
+{
+ unsigned int irq;
+
+ u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+ u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+
+ status &= ~mask;
+ status &= 0xff;
+
+ while (status) {
+ irq = fls(status) - 1;
+ generic_handle_irq(irq + start);
+ status &= ~(1 << irq);
+ }
+}
+
+static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+ s5pv310_irq_demux_eint(IRQ_EINT(16));
+ s5pv310_irq_demux_eint(IRQ_EINT(24));
+}
+
+static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+ u32 *irq_data = get_irq_data(irq);
+ struct irq_chip *chip = get_irq_chip(irq);
+
+ chip->mask(irq);
+
+ if (chip->ack)
+ chip->ack(irq);
+
+ generic_handle_irq(*irq_data);
+
+ chip->unmask(irq);
+}
+
+int __init s5pv310_init_irq_eint(void)
+{
+ int irq;
+
+ for (irq = 0 ; irq <= 31 ; irq++) {
+ set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
+ set_irq_handler(IRQ_EINT(irq), handle_level_irq);
+ set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+ }
+
+ set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
+
+ for (irq = 0 ; irq <= 15 ; irq++) {
+ eint0_15_data[irq] = IRQ_EINT(irq);
+
+ set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
+ set_irq_chained_handler(s5pv310_get_irq_nr(irq),
+ s5pv310_irq_eint0_15);
+ }
+
+ return 0;
+}
+
+arch_initcall(s5pv310_init_irq_eint);
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv310.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+#include <mach/regs-srom.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
+ S3C2410_UCON_RXILEVEL | \
+ S3C2410_UCON_TXIRQMODE | \
+ S3C2410_UCON_RXIRQMODE | \
+ S3C2410_UCON_RXFIFO_TOI | \
+ S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
+
+#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
+ S5PV210_UFCON_TXTRIG4 | \
+ S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = SMDKC210_UCON_DEFAULT,
+ .ulcon = SMDKC210_ULCON_DEFAULT,
+ .ufcon = SMDKC210_UFCON_DEFAULT,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = SMDKC210_UCON_DEFAULT,
+ .ulcon = SMDKC210_ULCON_DEFAULT,
+ .ufcon = SMDKC210_UFCON_DEFAULT,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = SMDKC210_UCON_DEFAULT,
+ .ulcon = SMDKC210_ULCON_DEFAULT,
+ .ufcon = SMDKC210_UFCON_DEFAULT,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = SMDKC210_UCON_DEFAULT,
+ .ulcon = SMDKC210_ULCON_DEFAULT,
+ .ufcon = SMDKC210_UFCON_DEFAULT,
+ },
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK0(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK0(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK2(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK2(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct resource smdkc210_smsc911x_resources[] = {
+ [0] = {
+ .start = S5PV310_PA_SROM_BANK(1),
+ .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_EINT(5),
+ .end = IRQ_EINT(5),
+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+ },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkc210_smsc911x = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
+ .resource = smdkc210_smsc911x_resources,
+ .dev = {
+ .platform_data = &smsc9215_config,
+ },
+};
+
+static struct platform_device *smdkc210_devices[] __initdata = {
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_hsmmc2,
+ &s3c_device_hsmmc3,
+ &s3c_device_rtc,
+ &s3c_device_wdt,
+ &smdkc210_smsc911x,
+};
+
+static void __init smdkc210_smsc911x_init(void)
+{
+ u32 cs1;
+
+ /* configure nCS1 width to 16 bits */
+ cs1 = __raw_readl(S5PV310_SROM_BW) &
+ ~(S5PV310_SROM_BW__CS_MASK <<
+ S5PV310_SROM_BW__NCS1__SHIFT);
+ cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
+ (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
+ (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
+ S5PV310_SROM_BW__NCS1__SHIFT;
+ __raw_writel(cs1, S5PV310_SROM_BW);
+
+ /* set timing for nCS1 suitable for ethernet chip */
+ __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
+ (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
+ (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
+ (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+}
+
+static void __init smdkc210_map_io(void)
+{
+ s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+ s3c24xx_init_clocks(24000000);
+ s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
+}
+
+static void __init smdkc210_machine_init(void)
+{
+ smdkc210_smsc911x_init();
+
+ s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+
+ platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+}
+
+MACHINE_START(SMDKC210, "SMDKC210")
+ /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+ .boot_params = S5P_PA_SDRAM + 0x100,
+ .init_irq = s5pv310_init_irq,
+ .map_io = smdkc210_map_io,
+ .init_machine = smdkc210_machine_init,
+ .timer = &s5pv310_timer,
+MACHINE_END
*/
#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
-#include <asm/hardware/cache-l2x0.h>
#include <plat/regs-serial.h>
#include <plat/s5pv310.h>
#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
#include <mach/map.h>
+#include <mach/regs-srom.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
},
};
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK0(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK0(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK2(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+ .max_width = 8,
+ .host_caps = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S5PV310_GPK2(2),
+ .ext_cd_gpio_invert = 1,
+ .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct resource smdkv310_smsc911x_resources[] = {
+ [0] = {
+ .start = S5PV310_PA_SROM_BANK(1),
+ .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_EINT(5),
+ .end = IRQ_EINT(5),
+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+ },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkv310_smsc911x = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
+ .resource = smdkv310_smsc911x_resources,
+ .dev = {
+ .platform_data = &smsc9215_config,
+ },
+};
+
+static struct platform_device *smdkv310_devices[] __initdata = {
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_hsmmc2,
+ &s3c_device_hsmmc3,
+ &s3c_device_rtc,
+ &s3c_device_wdt,
+ &smdkv310_smsc911x,
+};
+
+static void __init smdkv310_smsc911x_init(void)
+{
+ u32 cs1;
+
+ /* configure nCS1 width to 16 bits */
+ cs1 = __raw_readl(S5PV310_SROM_BW) &
+ ~(S5PV310_SROM_BW__CS_MASK <<
+ S5PV310_SROM_BW__NCS1__SHIFT);
+ cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
+ (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
+ (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
+ S5PV310_SROM_BW__NCS1__SHIFT;
+ __raw_writel(cs1, S5PV310_SROM_BW);
+
+ /* set timing for nCS1 suitable for ethernet chip */
+ __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
+ (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
+ (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
+ (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
+ (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+}
+
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
static void __init smdkv310_machine_init(void)
{
-#ifdef CONFIG_CACHE_L2X0
- l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
-#endif
+ smdkv310_smsc911x_init();
+
+ s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+
+ platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
}
MACHINE_START(SMDKV310, "SMDKV310")
* published by the Free Software Foundation.
*/
+#include <linux/platform_device.h>
#include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
-#include <asm/hardware/cache-l2x0.h>
#include <plat/regs-serial.h>
#include <plat/s5pv310.h>
#include <plat/cpu.h>
+#include <plat/devs.h>
#include <mach/map.h>
},
};
+static struct gpio_keys_button universal_gpio_keys_tables[] = {
+ {
+ .code = KEY_VOLUMEUP,
+ .gpio = S5PV310_GPX2(0), /* XEINT16 */
+ .desc = "gpio-keys: KEY_VOLUMEUP",
+ .type = EV_KEY,
+ .active_low = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_VOLUMEDOWN,
+ .gpio = S5PV310_GPX2(1), /* XEINT17 */
+ .desc = "gpio-keys: KEY_VOLUMEDOWN",
+ .type = EV_KEY,
+ .active_low = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_CONFIG,
+ .gpio = S5PV310_GPX2(2), /* XEINT18 */
+ .desc = "gpio-keys: KEY_CONFIG",
+ .type = EV_KEY,
+ .active_low = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_CAMERA,
+ .gpio = S5PV310_GPX2(3), /* XEINT19 */
+ .desc = "gpio-keys: KEY_CAMERA",
+ .type = EV_KEY,
+ .active_low = 1,
+ .debounce_interval = 1,
+ }, {
+ .code = KEY_OK,
+ .gpio = S5PV310_GPX3(5), /* XEINT29 */
+ .desc = "gpio-keys: KEY_OK",
+ .type = EV_KEY,
+ .active_low = 1,
+ .debounce_interval = 1,
+ },
+};
+
+static struct gpio_keys_platform_data universal_gpio_keys_data = {
+ .buttons = universal_gpio_keys_tables,
+ .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
+};
+
+static struct platform_device universal_gpio_keys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &universal_gpio_keys_data,
+ },
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+ /* Camera, To be updated */
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+ /* Gyro, To be updated */
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+ &universal_gpio_keys,
+ &s5p_device_onenand,
+};
+
static void __init universal_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
static void __init universal_machine_init(void)
{
-#ifdef CONFIG_CACHE_L2X0
- l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
-#endif
+ i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+ i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+ /* Last */
+ platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV310_GPD1(0), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV310_GPD1(1), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV310_GPD1(2), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV310_GPD1(3), S3C_GPIO_SFN(2));
- s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
void s3c_i2c2_cfg_gpio(struct platform_device *dev)
{
- s3c_gpio_cfgpin(S5PV310_GPA0(6), S3C_GPIO_SFN(3));
- s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP);
- s3c_gpio_cfgpin(S5PV310_GPA0(7), S3C_GPIO_SFN(3));
- s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP);
+ s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}
--- /dev/null
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C3 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c3_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C4 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c4_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c5.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C5 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c5_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C6 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c6_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
+ S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C7 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c7_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
+ S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+ struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+ unsigned int gpio;
+
+ /* Set all the necessary GPK0[0:1] pins to special-function 2 */
+ for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ switch (width) {
+ case 8:
+ for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+ /* Data pin GPK1[3:6] to special-funtion 3 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+ case 4:
+ for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
+ /* Data pin GPK0[3:6] to special-funtion 2 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+ default:
+ break;
+ }
+
+ if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+ s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+}
+
+void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+ struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+ unsigned int gpio;
+
+ /* Set all the necessary GPK1[0:1] pins to special-function 2 */
+ for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+ /* Data pin GPK1[3:6] to special-function 2 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+ s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+}
+
+void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+ struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+ unsigned int gpio;
+
+ /* Set all the necessary GPK2[0:1] pins to special-function 2 */
+ for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ switch (width) {
+ case 8:
+ for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+ /* Data pin GPK3[3:6] to special-function 3 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+ case 4:
+ for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
+ /* Data pin GPK2[3:6] to special-function 2 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+ default:
+ break;
+ }
+
+ if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+ s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+}
+
+void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+ struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+ unsigned int gpio;
+
+ /* Set all the necessary GPK3[0:1] pins to special-function 2 */
+ for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+ /* Data pin GPK3[3:6] to special-function 2 */
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+
+ if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+ s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
+ s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+ }
+}
--- /dev/null
+/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pv310_hsmmc_clksrcs[4] = {
+ [0] = NULL,
+ [1] = NULL,
+ [2] = "sclk_mmc", /* mmc_bus */
+ [3] = NULL,
+};
+
+void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
+ struct mmc_ios *ios, struct mmc_card *card)
+{
+ u32 ctrl2, ctrl3;
+
+ /* don't need to alter anything acording to card-type */
+
+ ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+
+ /* select base clock source to HCLK */
+
+ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+
+ /*
+ * clear async mode, enable conflict mask, rx feedback ctrl, SD
+ * clk hold and no use debounce count
+ */
+
+ ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+ S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+ S3C_SDHCI_CTRL2_ENFBCLKRX |
+ S3C_SDHCI_CTRL2_DFCNT_NONE |
+ S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+ /* Tx and Rx feedback clock delay control */
+
+ if (ios->clock < 25 * 1000000)
+ ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+ S3C_SDHCI_CTRL3_FCSEL2 |
+ S3C_SDHCI_CTRL3_FCSEL1 |
+ S3C_SDHCI_CTRL3_FCSEL0);
+ else
+ ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+ writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+ writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
{
unsigned int cur = sa11x0_getspeed(0);
unsigned int new_ppcr;
-
struct cpufreq_freqs freqs;
+
+ new_ppcr = sa11x0_freq_to_ppcr(target_freq);
switch(relation){
case CPUFREQ_RELATION_L:
- new_ppcr = sa11x0_freq_to_ppcr(target_freq);
if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
new_ppcr--;
break;
case CPUFREQ_RELATION_H:
- new_ppcr = sa11x0_freq_to_ppcr(target_freq);
if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
(sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
new_ppcr--;
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
-#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/input/sh_keysc.h>
#include <linux/usb/r8a66597.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/sh_mobile_csi2.h>
+#include <media/soc_camera.h>
+
#include <sound/sh_fsi.h>
#include <video/sh_mobile_hdmi.h>
/* SH_MMCIF */
static struct resource sh_mmcif_resources[] = {
[0] = {
- .name = "SH_MMCIF",
+ .name = "MMCIF",
.start = 0xE6BD0000,
.end = 0xE6BD00FF,
.flags = IORESOURCE_MEM,
.resource = usb1_host_resources,
};
+const static struct fb_videomode ap4evb_lcdc_modes[] = {
+ {
+#ifdef CONFIG_AP4EVB_QHD
+ .name = "R63302(QHD)",
+ .xres = 544,
+ .yres = 961,
+ .left_margin = 72,
+ .right_margin = 600,
+ .hsync_len = 16,
+ .upper_margin = 8,
+ .lower_margin = 8,
+ .vsync_len = 2,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+#else
+ .name = "WVGA Panel",
+ .xres = 800,
+ .yres = 480,
+ .left_margin = 220,
+ .right_margin = 110,
+ .hsync_len = 70,
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+ .sync = 0,
+#endif
+ },
+};
+
static struct sh_mobile_lcdc_info lcdc_info = {
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
+ .lcd_cfg = ap4evb_lcdc_modes,
+ .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
}
};
/* FSI */
#define IRQ_FSI evt2irq(0x1840)
-#define FSIACKCR 0xE6150018
-static void fsiackcr_init(struct clk *clk)
-{
- u32 status = __raw_readl(clk->enable_reg);
-
- /* use external clock */
- status &= ~0x000000ff;
- status |= 0x00000080;
- __raw_writel(status, clk->enable_reg);
-}
-
-static struct clk_ops fsiackcr_clk_ops = {
- .init = fsiackcr_init,
-};
-
-static struct clk fsiackcr_clk = {
- .ops = &fsiackcr_clk_ops,
- .enable_reg = (void __iomem *)FSIACKCR,
- .rate = 0, /* unknown */
-};
-
static struct sh_fsi_platform_info fsi_info = {
.porta_flags = SH_FSI_BRS_INV |
SH_FSI_OUT_SLAVE_MODE |
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
- .lcd_cfg = {
- .name = "HDMI",
- /* So far only 720p is supported */
- .xres = 1280,
- .yres = 720,
- /*
- * If left and right margins are not multiples of 8,
- * LDHAJR will be adjusted accordingly by the LCDC
- * driver. Until we start using EDID, these values
- * might have to be adjusted for different monitors.
- */
- .left_margin = 200,
- .right_margin = 88,
- .hsync_len = 48,
- .upper_margin = 20,
- .lower_margin = 5,
- .vsync_len = 5,
- .pixclock = 13468,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
- },
}
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = intcs_evt2irq(0x17a0),
+ .start = intcs_evt2irq(0x1780),
.flags = IORESOURCE_IRQ,
},
};
},
};
+static struct i2c_board_info imx074_info = {
+ I2C_BOARD_INFO("imx074", 0x1a),
+};
+
+struct soc_camera_link imx074_link = {
+ .bus_id = 0,
+ .board_info = &imx074_info,
+ .i2c_adapter_id = 0,
+ .module_name = "imx074",
+};
+
+static struct platform_device ap4evb_camera = {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+ .platform_data = &imx074_link,
+ },
+};
+
+static struct sh_csi2_client_config csi2_clients[] = {
+ {
+ .phy = SH_CSI2_PHY_MAIN,
+ .lanes = 3,
+ .channel = 0,
+ .pdev = &ap4evb_camera,
+ },
+};
+
+static struct sh_csi2_pdata csi2_info = {
+ .type = SH_CSI2C,
+ .clients = csi2_clients,
+ .num_clients = ARRAY_SIZE(csi2_clients),
+ .flags = SH_CSI2_ECC | SH_CSI2_CRC,
+};
+
+static struct resource csi2_resources[] = {
+ [0] = {
+ .name = "CSI2",
+ .start = 0xffc90000,
+ .end = 0xffc90fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0x17a0),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device csi2_device = {
+ .name = "sh-mobile-csi2",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(csi2_resources),
+ .resource = csi2_resources,
+ .dev = {
+ .platform_data = &csi2_info,
+ },
+};
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+ .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+ .csi2_dev = &csi2_device.dev,
+};
+
+static struct resource ceu_resources[] = {
+ [0] = {
+ .name = "CEU",
+ .start = 0xfe910000,
+ .end = 0xfe91009f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0x880),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* place holder for contiguous memory */
+ },
+};
+
+static struct platform_device ceu_device = {
+ .name = "sh_mobile_ceu",
+ .id = 0, /* "ceu0" clock */
+ .num_resources = ARRAY_SIZE(ceu_resources),
+ .resource = ceu_resources,
+ .dev = {
+ .platform_data = &sh_mobile_ceu_info,
+ },
+};
+
static struct platform_device *ap4evb_devices[] __initdata = {
&leds_device,
&nor_flash_device,
&lcdc1_device,
&lcdc_device,
&hdmi_device,
+ &csi2_device,
+ &ceu_device,
+ &ap4evb_camera,
};
static int __init hdmi_init_pm_clock(void)
goto out;
}
- ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk);
+ ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
if (ret < 0) {
- pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount);
+ pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
goto out;
}
- pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk));
+ pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
- rate = clk_round_rate(&pllc2_clk, 594000000);
+ rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
if (rate < 0) {
pr_err("Cannot get suitable rate: %ld\n", rate);
ret = rate;
goto out;
}
- ret = clk_set_rate(&pllc2_clk, rate);
+ ret = clk_set_rate(&sh7372_pllc2_clk, rate);
if (ret < 0) {
pr_err("Cannot set rate %ld: %d\n", rate, ret);
goto out;
pr_debug("PLLC2 set frequency %lu\n", rate);
- ret = clk_set_parent(hdmi_ick, &pllc2_clk);
+ ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
if (ret < 0) {
pr_err("Cannot set HDMI parent: %d\n", ret);
goto out;
device_initcall(hdmi_init_pm_clock);
+#define FSIACK_DUMMY_RATE 48000
+static int __init fsi_init_pm_clock(void)
+{
+ struct clk *fsia_ick;
+ int ret;
+
+ /*
+ * FSIACK is connected to AK4642,
+ * and the rate is depend on playing sound rate.
+ * So, set dummy rate (= 48k) here
+ */
+ ret = clk_set_rate(&sh7372_fsiack_clk, FSIACK_DUMMY_RATE);
+ if (ret < 0) {
+ pr_err("Cannot set FSIACK dummy rate: %d\n", ret);
+ return ret;
+ }
+
+ fsia_ick = clk_get(&fsi_device.dev, "icka");
+ if (IS_ERR(fsia_ick)) {
+ ret = PTR_ERR(fsia_ick);
+ pr_err("Cannot get FSI ICK: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
+ if (ret < 0) {
+ pr_err("Cannot set FSI-A parent: %d\n", ret);
+ goto out;
+ }
+
+ ret = clk_set_rate(fsia_ick, FSIACK_DUMMY_RATE);
+ if (ret < 0)
+ pr_err("Cannot set FSI-A rate: %d\n", ret);
+
+out:
+ clk_put(fsia_ick);
+
+ return ret;
+}
+device_initcall(fsi_init_pm_clock);
+
/*
* FIXME !!
*
* gpio_no_direction
- * gpio_pull_up
* are quick_hack.
*
* current gpio frame work doesn't have
__raw_writeb(0x00, addr);
}
-static void __init gpio_pull_up(u32 addr)
-{
- u8 data = __raw_readb(addr);
-
- data &= 0x0F;
- data |= 0xC0;
- __raw_writeb(data, addr);
-}
-
/* TouchScreen */
+#ifdef CONFIG_AP4EVB_QHD
+# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
+# define GPIO_TSC_PORT GPIO_PORT123
+#else /* WVGA */
+# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
+# define GPIO_TSC_PORT GPIO_PORT40
+#endif
+
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
static int ts_get_pendown_state(void)
{
- int val1, val2;
+ int val;
- gpio_free(GPIO_FN_IRQ28_123);
- gpio_free(GPIO_FN_IRQ7_40);
+ gpio_free(GPIO_TSC_IRQ);
- gpio_request(GPIO_PORT123, NULL);
- gpio_request(GPIO_PORT40, NULL);
+ gpio_request(GPIO_TSC_PORT, NULL);
- gpio_direction_input(GPIO_PORT123);
- gpio_direction_input(GPIO_PORT40);
+ gpio_direction_input(GPIO_TSC_PORT);
- val1 = gpio_get_value(GPIO_PORT123);
- val2 = gpio_get_value(GPIO_PORT40);
+ val = gpio_get_value(GPIO_TSC_PORT);
- gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */
- gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */
+ gpio_request(GPIO_TSC_IRQ, NULL);
- return val1 ^ val2;
+ return !val;
}
-#define PORT40CR 0xE6051028
-#define PORT123CR 0xE605007B
static int ts_init(void)
{
- gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */
- gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */
-
- gpio_pull_up(PORT40CR);
- gpio_pull_up(PORT123CR);
+ gpio_request(GPIO_TSC_IRQ, NULL);
return 0;
}
clk_put(clk);
}
- /* change parent of FSI A */
- clk = clk_get(NULL, "fsia_clk");
- if (!IS_ERR(clk)) {
- clk_register(&fsiackcr_clk);
- clk_set_parent(clk, &fsiackcr_clk);
- clk_put(clk);
- }
-
/*
* set irq priority, to avoid sound chopping
* when NFS rootfs is used
ARRAY_SIZE(i2c1_devices));
#ifdef CONFIG_AP4EVB_QHD
+
/*
- * QHD
+ * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
+ * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
*/
/* enable KEYSC */
lcdc_info.ch[0].interface_type = RGB24;
lcdc_info.ch[0].clock_divider = 1;
lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
- lcdc_info.ch[0].lcd_cfg.name = "R63302(QHD)";
- lcdc_info.ch[0].lcd_cfg.xres = 544;
- lcdc_info.ch[0].lcd_cfg.yres = 961;
- lcdc_info.ch[0].lcd_cfg.left_margin = 72;
- lcdc_info.ch[0].lcd_cfg.right_margin = 600;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 16;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 8;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 8;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
- lcdc_info.ch[0].lcd_cfg.sync = FB_SYNC_VERT_HIGH_ACT |
- FB_SYNC_HOR_HIGH_ACT;
lcdc_info.ch[0].lcd_size_cfg.width = 44;
lcdc_info.ch[0].lcd_size_cfg.height = 79;
#else
/*
- * WVGA
+ * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
+ * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
*/
+
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
lcdc_info.ch[0].interface_type = RGB18;
lcdc_info.ch[0].clock_divider = 2;
lcdc_info.ch[0].flags = 0;
- lcdc_info.ch[0].lcd_cfg.name = "WVGA Panel";
- lcdc_info.ch[0].lcd_cfg.xres = 800;
- lcdc_info.ch[0].lcd_cfg.yres = 480;
- lcdc_info.ch[0].lcd_cfg.left_margin = 220;
- lcdc_info.ch[0].lcd_cfg.right_margin = 110;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
- lcdc_info.ch[0].lcd_cfg.sync = 0;
lcdc_info.ch[0].lcd_size_cfg.width = 152;
lcdc_info.ch[0].lcd_size_cfg.height = 91;
i2c_register_board_info(0, &tsc_device, 1);
#endif /* CONFIG_AP4EVB_QHD */
+ /* CEU */
+
+ /*
+ * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
+ * becomes available
+ */
+
+ /* MIPI-CSI stuff */
+ gpio_request(GPIO_FN_VIO_CKO, NULL);
+
+ clk = clk_get(NULL, "vck1_clk");
+ if (!IS_ERR(clk)) {
+ clk_set_rate(clk, clk_round_rate(clk, 13000000));
+ clk_enable(clk);
+ clk_put(clk);
+ }
+
sh7372_add_standard_devices();
/* HDMI */
shmobile_timer.init();
/* External clock source */
- clk_set_rate(&dv_clki_clk, 27000000);
+ clk_set_rate(&sh7372_dv_clki_clk, 27000000);
}
static struct sys_timer ap4evb_timer = {
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
- CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */
+ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
#define SMSTPCR4 0xe6150140
/* Platforms must set frequency on their DV_CLKI pin */
-struct clk dv_clki_clk = {
+struct clk sh7372_dv_clki_clk = {
};
/* Fixed 32 KHz root clock from EXTALR pin */
};
/* Divide dv_clki by two */
-struct clk dv_clki_div2_clk = {
+struct clk sh7372_dv_clki_div2_clk = {
.ops = &div2_clk_ops,
- .parent = &dv_clki_clk,
+ .parent = &sh7372_dv_clki_clk,
};
/* Divide extal1 by two */
static struct clk *pllc2_parent[] = {
[0] = &extal1_div2_clk,
[1] = &extal2_div2_clk,
- [2] = &dv_clki_div2_clk,
+ [2] = &sh7372_dv_clki_div2_clk,
};
/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
.set_parent = pllc2_set_parent,
};
-struct clk pllc2_clk = {
+struct clk sh7372_pllc2_clk = {
.ops = &pllc2_clk_ops,
.parent = &extal1_div2_clk,
.freq_table = pllc2_freq_table,
.parent_num = ARRAY_SIZE(pllc2_parent),
};
+/* External input clock (pin name: FSIACK/FSIBCK ) */
+struct clk sh7372_fsiack_clk = {
+};
+
+struct clk sh7372_fsibck_clk = {
+};
+
static struct clk *main_clks[] = {
- &dv_clki_clk,
+ &sh7372_dv_clki_clk,
&r_clk,
&sh7372_extal1_clk,
&sh7372_extal2_clk,
- &dv_clki_div2_clk,
+ &sh7372_dv_clki_div2_clk,
&extal1_div2_clk,
&extal2_div2_clk,
&extal2_div4_clk,
&pllc0_clk,
&pllc1_clk,
&pllc1_div2_clk,
- &pllc2_clk,
+ &sh7372_pllc2_clk,
+ &sh7372_fsiack_clk,
+ &sh7372_fsibck_clk,
};
static void div4_kick(struct clk *clk)
};
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
- DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
+ DIV6_SUB, DIV6_SPU,
DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
DIV6_NR };
[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
- [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
- [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
};
-enum { DIV6_HDMI, DIV6_REPARENT_NR };
+enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
/* Indices are important - they are the actual src selecting values */
static struct clk *hdmi_parent[] = {
[0] = &pllc1_div2_clk,
- [1] = &pllc2_clk,
- [2] = &dv_clki_clk,
+ [1] = &sh7372_pllc2_clk,
+ [2] = &sh7372_dv_clki_clk,
[3] = NULL, /* pllc2_div4 not implemented yet */
};
+static struct clk *fsiackcr_parent[] = {
+ [0] = &pllc1_div2_clk,
+ [1] = &sh7372_pllc2_clk,
+ [2] = &sh7372_fsiack_clk, /* external input for FSI A */
+ [3] = NULL, /* setting prohibited */
+};
+
+static struct clk *fsibckcr_parent[] = {
+ [0] = &pllc1_div2_clk,
+ [1] = &sh7372_pllc2_clk,
+ [2] = &sh7372_fsibck_clk, /* external input for FSI B */
+ [3] = NULL, /* setting prohibited */
+};
+
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
+ [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
+ fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
+ [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
+ fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
};
enum { MSTP001,
MSTP131, MSTP130,
- MSTP129, MSTP128, MSTP127, MSTP126,
+ MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
MSTP118, MSTP117, MSTP116,
MSTP106, MSTP101, MSTP100,
MSTP223,
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
+ [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
- [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
+ [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
static struct clk_lookup lookups[] = {
/* main clocks */
- CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
+ CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
- CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+ CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
- CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
- CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
+ CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
+ CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
+ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
- CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
- {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
+
+ CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
+ CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
+ CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
};
void __init sh7372_clock_init(void)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
- ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
+ ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
- CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
SHDMA_SLAVE_SDHI2_TX,
};
-extern struct clk dv_clki_clk;
-extern struct clk dv_clki_div2_clk;
-extern struct clk pllc2_clk;
+extern struct clk sh7372_extal1_clk;
+extern struct clk sh7372_extal2_clk;
+extern struct clk sh7372_dv_clki_clk;
+extern struct clk sh7372_dv_clki_div2_clk;
+extern struct clk sh7372_pllc2_clk;
+extern struct clk sh7372_fsiack_clk;
+extern struct clk sh7372_fsibck_clk;
#endif /* __ASM_SH7372_H__ */
INTCS,
/* interrupt sources INTCS */
+
+ /* IRQ0S - IRQ31S */
VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
+ /* MFI */
+ /* BBIF2 */
VPU,
TSIF1,
_3DG_SGX530,
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
IPMMU_IPMMUR, IPMMU_IPMMUR2,
RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+ /* KEYSC */
+ /* TTI20 */
MSIOF,
IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
CMT0,
TSIF0,
+ /* CMT2 */
LMB,
CTI,
+ /* RWDT0 */
ICB,
JPU_JPEG,
LCDC,
CSIRX,
DSITX_DSITX0,
DSITX_DSITX1,
+ /* SPU2 */
+ /* FSI */
+ /* FMSI */
+ /* HDMI */
TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
CMT4,
DSITX1_DSITX1_0,
DSITX1_DSITX1_1,
+ /* MFIS2 */
CPORTS2R,
+ /* CEC */
JPU6E,
/* interrupt groups INTCS */
};
static struct intc_vect intcs_vectors[] = {
+ /* IRQ0S - IRQ31S */
INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
+ /* MFI */
+ /* BBIF2 */
INTCS_VECT(VPU, 0x980),
INTCS_VECT(TSIF1, 0x9a0),
INTCS_VECT(_3DG_SGX530, 0x9e0),
INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+ /* KEYSC */
+ /* TTI20 */
+ INTCS_VECT(MSIOF, 0x0d20),
INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
INTCS_VECT(TMU_TUNI2, 0xec0),
INTCS_VECT(CMT0, 0xf00),
INTCS_VECT(TSIF0, 0xf20),
+ /* CMT2 */
INTCS_VECT(LMB, 0xf60),
INTCS_VECT(CTI, 0x400),
+ /* RWDT0 */
INTCS_VECT(ICB, 0x480),
INTCS_VECT(JPU_JPEG, 0x560),
INTCS_VECT(LCDC, 0x580),
INTCS_VECT(CSIRX, 0x17a0),
INTCS_VECT(DSITX_DSITX0, 0x17c0),
INTCS_VECT(DSITX_DSITX1, 0x17e0),
+ /* SPU2 */
+ /* FSI */
+ /* FMSI */
+ /* HDMI */
INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
INTCS_VECT(TMU1_TUNI2, 0x1940),
INTCS_VECT(CMT4, 0x1980),
INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
+ /* MFIS2 */
INTCS_VECT(CPORTS2R, 0x1a20),
+ /* CEC */
INTCS_VECT(JPU6E, 0x1a80),
INTC_VECT(INTCS, 0xf80),
MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK,
MSIOF2_TXD_MARK,
- /* MSIOF3 */
+ /* BBIF1 */
BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK,
BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK,
- /* MSIOF4 */
+ /* BBIF2 */
BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK,
BBIF2_TXD1_MARK, BBIF2_RXD_MARK,
GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD),
GPIO_FN(MSIOF2_TXD),
- /* MSIOF3 */
+ /* BBIF1 */
GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK),
GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N),
- /* MSIOF4 */
+ /* BBIF2 */
GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1),
GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD),
.name = "CMT10",
.channel_offset = 0x10,
.timer_bit = 0,
- .clk = "r_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
.name = "CMT10",
.channel_offset = 0x10,
.timer_bit = 0,
- .clk = "cmt1",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
.num_resources = ARRAY_SIZE(cmt10_resources),
};
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+ .name = "TMU00",
+ .channel_offset = 0x4,
+ .timer_bit = 0,
+ .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+ [0] = {
+ .name = "TMU00",
+ .start = 0xfff60008,
+ .end = 0xfff60013,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tmu00_device = {
+ .name = "sh_tmu",
+ .id = 0,
+ .dev = {
+ .platform_data = &tmu00_platform_data,
+ },
+ .resource = tmu00_resources,
+ .num_resources = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+ .name = "TMU01",
+ .channel_offset = 0x10,
+ .timer_bit = 1,
+ .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+ [0] = {
+ .name = "TMU01",
+ .start = 0xfff60014,
+ .end = 0xfff6001f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tmu01_device = {
+ .name = "sh_tmu",
+ .id = 1,
+ .dev = {
+ .platform_data = &tmu01_platform_data,
+ },
+ .resource = tmu01_resources,
+ .num_resources = ARRAY_SIZE(tmu01_resources),
+};
+
/* I2C */
static struct resource iic0_resources[] = {
[0] = {
},
{
/* DMA error IRQ */
- .start = 246,
- .end = 246,
+ .start = evt2irq(0x20c0),
+ .end = evt2irq(0x20c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
- .start = 240,
- .end = 245,
+ .start = evt2irq(0x2000),
+ .end = evt2irq(0x20a0),
.flags = IORESOURCE_IRQ,
},
};
},
{
/* DMA error IRQ */
- .start = 254,
- .end = 254,
+ .start = evt2irq(0x21c0),
+ .end = evt2irq(0x21c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
- .start = 248,
- .end = 253,
+ .start = evt2irq(0x2100),
+ .end = evt2irq(0x21a0),
.flags = IORESOURCE_IRQ,
},
};
},
{
/* DMA error IRQ */
- .start = 262,
- .end = 262,
+ .start = evt2irq(0x22c0),
+ .end = evt2irq(0x22c0),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
- .start = 256,
- .end = 261,
+ .start = evt2irq(0x2200),
+ .end = evt2irq(0x22a0),
.flags = IORESOURCE_IRQ,
},
};
&scif5_device,
&scif6_device,
&cmt10_device,
+ &tmu00_device,
+ &tmu01_device,
+};
+
+static struct platform_device *sh7372_late_devices[] __initdata = {
&iic0_device,
&iic1_device,
&dma0_device,
{
platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
+
+ platform_add_devices(sh7372_late_devices,
+ ARRAY_SIZE(sh7372_late_devices));
}
void __init sh7372_add_early_devices(void)
.name = "CMT10",
.channel_offset = 0x10,
.timer_bit = 0,
- .clk = "r_clk",
.clockevent_rating = 125,
.clocksource_rating = 125,
};
* AMBA bus
* |
* +- CPU
- * +- NANDIF NAND Flash interface
+ * +- FSMC NANDIF NAND Flash interface
* +- SEMI Shared Memory interface
* +- ISP Image Signal Processor (U335 only)
* +- CDS (U335 only)
};
static struct clk nandif_clk = {
- .name = "NANDIF",
+ .name = "FSMC",
.parent = &amba_clk,
.hw_ctrld = false,
.reset = true,
/* Connected directly to the AMBA bus */
DEF_LOOKUP("amba", &amba_clk),
DEF_LOOKUP("cpu", &cpu_clk),
- DEF_LOOKUP("fsmc", &nandif_clk),
+ DEF_LOOKUP("fsmc-nand", &nandif_clk),
DEF_LOOKUP("semi", &semi_clk),
#ifdef CONFIG_MACH_U300_BS335
DEF_LOOKUP("isp", &isp_clk),
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/err.h>
-#include <mach/coh901318.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
+#include <mach/coh901318.h>
#include <mach/hardware.h>
#include <mach/syscon.h>
#include <mach/dma_channels.h>
*/
static struct resource fsmc_resources[] = {
{
+ .name = "nand_data",
+ .start = U300_NAND_CS0_PHYS_BASE,
+ .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fsmc_regs",
.start = U300_NAND_IF_PHYS_BASE,
.end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
.resource = rtc_resources,
};
-static struct platform_device fsmc_device = {
- .name = "nandif",
+static struct mtd_partition u300_partitions[] = {
+ {
+ .name = "bootrecords",
+ .offset = 0,
+ .size = SZ_128K,
+ },
+ {
+ .name = "free",
+ .offset = SZ_128K,
+ .size = 8064 * SZ_1K,
+ },
+ {
+ .name = "platform",
+ .offset = 8192 * SZ_1K,
+ .size = 253952 * SZ_1K,
+ },
+};
+
+static struct fsmc_nand_platform_data nand_platform_data = {
+ .partitions = u300_partitions,
+ .nr_partitions = ARRAY_SIZE(u300_partitions),
+ .options = NAND_SKIP_BBTSCAN,
+ .width = FSMC_NAND_BW8,
+};
+
+static struct platform_device nand_device = {
+ .name = "fsmc-nand",
.id = -1,
- .num_resources = ARRAY_SIZE(fsmc_resources),
.resource = fsmc_resources,
+ .num_resources = ARRAY_SIZE(fsmc_resources),
+ .dev = {
+ .platform_data = &nand_platform_data,
+ },
};
static struct platform_device ave_device = {
&keypad_device,
&rtc_device,
&gpio_device,
- &fsmc_device,
+ &nand_device,
&wdog_device,
&ave_device
};
/* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE 0x80000000
-#define U300_NAND_CS0_VIRT_BASE 0xff040000
/* NFIF */
#define U300_NAND_IF_PHYS_BASE 0x9f800000
-#define U300_NAND_IF_VIRT_BASE 0xff030000
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#include <linux/io.h>
#include <linux/clk.h>
+#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
}
#ifdef CONFIG_CACHE_L2X0
+static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
+{
+ /* wait for the operation to complete */
+ while (readl(reg) & mask)
+ ;
+}
+
+static inline void ux500_cache_sync(void)
+{
+ void __iomem *base = __io_address(UX500_L2CC_BASE);
+ writel(0, base + L2X0_CACHE_SYNC);
+ ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
+}
+
+/*
+ * The L2 cache cannot be turned off in the non-secure world.
+ * Dummy until a secure service is in place.
+ */
+static void ux500_l2x0_disable(void)
+{
+}
+
+/*
+ * This is only called when doing a kexec, just after turning off the L2
+ * and L1 cache, and it is surrounded by a spinlock in the generic version.
+ * However, we're not really turning off the L2 cache right now and the
+ * PL310 does not support exclusive accesses (used to implement the spinlock).
+ * So, the invalidation needs to be done without the spinlock.
+ */
+static void ux500_l2x0_inv_all(void)
+{
+ void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
+ uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
+
+ /* invalidate all ways */
+ writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+ ux500_cache_sync();
+}
+
static int ux500_l2x0_init(void)
{
void __iomem *l2x0_base;
/* 64KB way size, 8 way associativity, force WA */
l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+ /* Override invalidate function */
+ outer_cache.disable = ux500_l2x0_disable;
+ outer_cache.inv_all = ux500_l2x0_inv_all;
+
return 0;
}
early_initcall(ux500_l2x0_init);
help
This option enables the L2x0 PrimeCell.
+config CACHE_PL310
+ bool
+ depends on CACHE_L2X0
+ default y if CPU_V7 && !CPU_V6
+ help
+ This option enables optimisations for the PL310 cache
+ controller.
+
config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller"
depends on (ARCH_DOVE || ARCH_MMP)
/* FIXME: put optimal value here. Current one is just estimation */
#define CACHE_DLIMIT (CACHE_DSIZE * 2)
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(fa_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(fa_flush_icache_all)
+
/*
* flush_user_cache_all()
*
.type fa_cache_fns, #object
ENTRY(fa_cache_fns)
+ .long fa_flush_icache_all
.long fa_flush_kern_cache_all
.long fa_flush_user_cache_all
.long fa_flush_user_cache_range
static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
static uint32_t l2x0_way_mask; /* Bitmask of active ways */
+static uint32_t l2x0_size;
-static inline void cache_wait(void __iomem *reg, unsigned long mask)
+static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
{
- /* wait for the operation to complete */
+ /* wait for cache operation by line or way to complete */
while (readl_relaxed(reg) & mask)
;
}
+#ifdef CONFIG_CACHE_PL310
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
+{
+ /* cache operations by line are atomic on PL310 */
+}
+#else
+#define cache_wait cache_wait_way
+#endif
+
static inline void cache_sync(void)
{
void __iomem *base = l2x0_base;
spin_unlock_irqrestore(&l2x0_lock, flags);
}
-static inline void l2x0_inv_all(void)
+static void l2x0_flush_all(void)
+{
+ unsigned long flags;
+
+ /* clean all ways */
+ spin_lock_irqsave(&l2x0_lock, flags);
+ writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+ cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
+ cache_sync();
+ spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
+static void l2x0_clean_all(void)
+{
+ unsigned long flags;
+
+ /* clean all ways */
+ spin_lock_irqsave(&l2x0_lock, flags);
+ writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
+ cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
+ cache_sync();
+ spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
+static void l2x0_inv_all(void)
{
unsigned long flags;
/* invalidate all ways */
spin_lock_irqsave(&l2x0_lock, flags);
+ /* Invalidating when L2 is enabled is a nono */
+ BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
- cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+ cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
spin_unlock_irqrestore(&l2x0_lock, flags);
}
void __iomem *base = l2x0_base;
unsigned long flags;
+ if ((end - start) >= l2x0_size) {
+ l2x0_clean_all();
+ return;
+ }
+
spin_lock_irqsave(&l2x0_lock, flags);
start &= ~(CACHE_LINE_SIZE - 1);
while (start < end) {
void __iomem *base = l2x0_base;
unsigned long flags;
+ if ((end - start) >= l2x0_size) {
+ l2x0_flush_all();
+ return;
+ }
+
spin_lock_irqsave(&l2x0_lock, flags);
start &= ~(CACHE_LINE_SIZE - 1);
while (start < end) {
spin_unlock_irqrestore(&l2x0_lock, flags);
}
+static void l2x0_disable(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&l2x0_lock, flags);
+ writel(0, l2x0_base + L2X0_CTRL);
+ spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
{
__u32 aux;
__u32 cache_id;
+ __u32 way_size = 0;
int ways;
const char *type;
l2x0_way_mask = (1 << ways) - 1;
+ /*
+ * L2 cache Size = Way size * Number of ways
+ */
+ way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
+ way_size = 1 << (way_size + 3);
+ l2x0_size = ways * way_size * SZ_1K;
+
/*
* Check if l2x0 controller is already enabled.
* If you are booting from non-secure mode
outer_cache.clean_range = l2x0_clean_range;
outer_cache.flush_range = l2x0_flush_range;
outer_cache.sync = l2x0_cache_sync;
+ outer_cache.flush_all = l2x0_flush_all;
+ outer_cache.inv_all = l2x0_inv_all;
+ outer_cache.disable = l2x0_disable;
printk(KERN_INFO "%s cache controller enabled\n", type);
- printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
- ways, cache_id, aux);
+ printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
+ ways, cache_id, aux, l2x0_size);
}
#include <asm/page.h>
#include "proc-macros.S"
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v3_flush_icache_all)
+ mov pc, lr
+ENDPROC(v3_flush_icache_all)
+
/*
* flush_user_cache_all()
*
.type v3_cache_fns, #object
ENTRY(v3_cache_fns)
+ .long v3_flush_icache_all
.long v3_flush_kern_cache_all
.long v3_flush_user_cache_all
.long v3_flush_user_cache_range
#include <asm/page.h>
#include "proc-macros.S"
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4_flush_icache_all)
+ mov pc, lr
+ENDPROC(v4_flush_icache_all)
+
/*
* flush_user_cache_all()
*
.type v4_cache_fns, #object
ENTRY(v4_cache_fns)
+ .long v4_flush_icache_all
.long v4_flush_kern_cache_all
.long v4_flush_user_cache_all
.long v4_flush_user_cache_range
.long FLUSH_BASE
.text
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4wb_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(v4wb_flush_icache_all)
+
/*
* flush_user_cache_all()
*
.type v4wb_cache_fns, #object
ENTRY(v4wb_cache_fns)
+ .long v4wb_flush_icache_all
.long v4wb_flush_kern_cache_all
.long v4wb_flush_user_cache_all
.long v4wb_flush_user_cache_range
*/
#define CACHE_DLIMIT 16384
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4wt_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(v4wt_flush_icache_all)
+
/*
* flush_user_cache_all()
*
.type v4wt_cache_fns, #object
ENTRY(v4wt_cache_fns)
+ .long v4wt_flush_icache_all
.long v4wt_flush_kern_cache_all
.long v4wt_flush_user_cache_all
.long v4wt_flush_user_cache_range
return ret;
}
+#if USE_SPLIT_PTLOCKS
+/*
+ * If we are using split PTE locks, then we need to take the page
+ * lock here. Otherwise we are using shared mm->page_table_lock
+ * which is already locked, thus cannot take it.
+ */
+static inline void do_pte_lock(spinlock_t *ptl)
+{
+ /*
+ * Use nested version here to indicate that we are already
+ * holding one similar spinlock.
+ */
+ spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
+}
+
+static inline void do_pte_unlock(spinlock_t *ptl)
+{
+ spin_unlock(ptl);
+}
+#else /* !USE_SPLIT_PTLOCKS */
+static inline void do_pte_lock(spinlock_t *ptl) {}
+static inline void do_pte_unlock(spinlock_t *ptl) {}
+#endif /* USE_SPLIT_PTLOCKS */
+
static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
unsigned long pfn)
{
*/
ptl = pte_lockptr(vma->vm_mm, pmd);
pte = pte_offset_map(pmd, address);
- spin_lock(ptl);
+ do_pte_lock(ptl);
ret = do_adjust_pte(vma, address, pfn, pte);
- spin_unlock(ptl);
+ do_pte_unlock(ptl);
pte_unmap(pte);
return ret;
#include <linux/highmem.h>
#include <linux/gfp.h>
#include <linux/memblock.h>
+#include <linux/sort.h>
#include <asm/mach-types.h>
#include <asm/sections.h>
printk("%d pages swap cached\n", cached);
}
-static void __init find_limits(struct meminfo *mi,
- unsigned long *min, unsigned long *max_low, unsigned long *max_high)
+static void __init find_limits(unsigned long *min, unsigned long *max_low,
+ unsigned long *max_high)
{
+ struct meminfo *mi = &meminfo;
int i;
*min = -1UL;
}
}
-static void __init arm_bootmem_init(struct meminfo *mi,
- unsigned long start_pfn, unsigned long end_pfn)
+static void __init arm_bootmem_init(unsigned long start_pfn,
+ unsigned long end_pfn)
{
struct memblock_region *reg;
unsigned int boot_pages;
phys_addr_t bitmap;
pg_data_t *pgdat;
- int i;
/*
* Allocate the bootmem bitmap page. This must be in a region
pgdat = NODE_DATA(0);
init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
- for_each_bank(i, mi) {
- struct membank *bank = &mi->bank[i];
- if (!bank->highmem)
- free_bootmem(bank_phys_start(bank), bank_phys_size(bank));
+ /* Free the lowmem regions from memblock into bootmem. */
+ for_each_memblock(memory, reg) {
+ unsigned long start = memblock_region_memory_base_pfn(reg);
+ unsigned long end = memblock_region_memory_end_pfn(reg);
+
+ if (end >= end_pfn)
+ end = end_pfn;
+ if (start >= end)
+ break;
+
+ free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT);
}
- /*
- * Reserve the memblock reserved regions in bootmem.
- */
+ /* Reserve the lowmem memblock reserved regions in bootmem. */
for_each_memblock(reserved, reg) {
- phys_addr_t start = memblock_region_reserved_base_pfn(reg);
- phys_addr_t end = memblock_region_reserved_end_pfn(reg);
- if (start >= start_pfn && end <= end_pfn)
- reserve_bootmem_node(pgdat, __pfn_to_phys(start),
- (end - start) << PAGE_SHIFT,
- BOOTMEM_DEFAULT);
+ unsigned long start = memblock_region_reserved_base_pfn(reg);
+ unsigned long end = memblock_region_reserved_end_pfn(reg);
+
+ if (end >= end_pfn)
+ end = end_pfn;
+ if (start >= end)
+ break;
+
+ reserve_bootmem(__pfn_to_phys(start),
+ (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT);
}
}
-static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
- unsigned long max_low, unsigned long max_high)
+static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
+ unsigned long max_high)
{
unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
- int i;
+ struct memblock_region *reg;
/*
* initialise the zones.
* holes = node_size - sum(bank_sizes)
*/
memcpy(zhole_size, zone_size, sizeof(zhole_size));
- for_each_bank(i, mi) {
- int idx = 0;
+ for_each_memblock(memory, reg) {
+ unsigned long start = memblock_region_memory_base_pfn(reg);
+ unsigned long end = memblock_region_memory_end_pfn(reg);
+
+ if (start < max_low) {
+ unsigned long low_end = min(end, max_low);
+ zhole_size[0] -= low_end - start;
+ }
#ifdef CONFIG_HIGHMEM
- if (mi->bank[i].highmem)
- idx = ZONE_HIGHMEM;
+ if (end > max_low) {
+ unsigned long high_start = max(start, max_low);
+ zhole_size[ZONE_HIGHMEM] -= end - high_start;
+ }
#endif
- zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
}
/*
}
#endif
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+ const struct membank *a = _a, *b = _b;
+ long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+ return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
+
void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
{
int i;
+ sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
+
memblock_init();
for (i = 0; i < mi->nr_banks; i++)
memblock_add(mi->bank[i].start, mi->bank[i].size);
void __init bootmem_init(void)
{
- struct meminfo *mi = &meminfo;
unsigned long min, max_low, max_high;
max_low = max_high = 0;
- find_limits(mi, &min, &max_low, &max_high);
+ find_limits(&min, &max_low, &max_high);
- arm_bootmem_init(mi, min, max_low);
+ arm_bootmem_init(min, max_low);
/*
* Sparsemem tries to allocate bootmem in memory_present(),
* the sparse mem_map arrays initialized by sparse_init()
* for memmap_init_zone(), otherwise all PFNs are invalid.
*/
- arm_bootmem_free(mi, min, max_low, max_high);
+ arm_bootmem_free(min, max_low, max_high);
high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
}
}
+static void __init free_highpages(void)
+{
+#ifdef CONFIG_HIGHMEM
+ unsigned long max_low = max_low_pfn + PHYS_PFN_OFFSET;
+ struct memblock_region *mem, *res;
+
+ /* set highmem page free */
+ for_each_memblock(memory, mem) {
+ unsigned long start = memblock_region_memory_base_pfn(mem);
+ unsigned long end = memblock_region_memory_end_pfn(mem);
+
+ /* Ignore complete lowmem entries */
+ if (end <= max_low)
+ continue;
+
+ /* Truncate partial highmem entries */
+ if (start < max_low)
+ start = max_low;
+
+ /* Find and exclude any reserved regions */
+ for_each_memblock(reserved, res) {
+ unsigned long res_start, res_end;
+
+ res_start = memblock_region_reserved_base_pfn(res);
+ res_end = memblock_region_reserved_end_pfn(res);
+
+ if (res_end < start)
+ continue;
+ if (res_start < start)
+ res_start = start;
+ if (res_start > end)
+ res_start = end;
+ if (res_end > end)
+ res_end = end;
+ if (res_start != start)
+ totalhigh_pages += free_area(start, res_start,
+ NULL);
+ start = res_end;
+ if (start == end)
+ break;
+ }
+
+ /* And now free anything which remains */
+ if (start < end)
+ totalhigh_pages += free_area(start, end, NULL);
+ }
+ totalram_pages += totalhigh_pages;
+#endif
+}
+
/*
* mem_init() marks the free areas in the mem_map and tells us how much
* memory is free. This is done after various parts of the system have
void __init mem_init(void)
{
unsigned long reserved_pages, free_pages;
+ struct memblock_region *reg;
int i;
#ifdef CONFIG_HAVE_TCM
/* These pointers are filled in on TCM detection */
__phys_to_pfn(__pa(swapper_pg_dir)), NULL);
#endif
-#ifdef CONFIG_HIGHMEM
- /* set highmem page free */
- for_each_bank (i, &meminfo) {
- unsigned long start = bank_pfn_start(&meminfo.bank[i]);
- unsigned long end = bank_pfn_end(&meminfo.bank[i]);
- if (start >= max_low_pfn + PHYS_PFN_OFFSET)
- totalhigh_pages += free_area(start, end, NULL);
- }
- totalram_pages += totalhigh_pages;
-#endif
+ free_highpages();
reserved_pages = free_pages = 0;
*/
printk(KERN_INFO "Memory:");
num_physpages = 0;
- for (i = 0; i < meminfo.nr_banks; i++) {
- num_physpages += bank_pfn_size(&meminfo.bank[i]);
- printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20);
+ for_each_memblock(memory, reg) {
+ unsigned long pages = memblock_region_memory_end_pfn(reg) -
+ memblock_region_memory_base_pfn(reg);
+ num_physpages += pages;
+ printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
}
printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
#include <linux/mman.h>
#include <linux/nodemask.h>
#include <linux/memblock.h>
-#include <linux/sort.h>
#include <linux/fs.h>
#include <asm/cputype.h>
.domain = DOMAIN_KERNEL,
},
[MT_MEMORY_DTCM] = {
- .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG |
- L_PTE_DIRTY | L_PTE_WRITE,
- .prot_l1 = PMD_TYPE_TABLE,
- .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
- .domain = DOMAIN_KERNEL,
+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+ L_PTE_WRITE,
+ .prot_l1 = PMD_TYPE_TABLE,
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
+ .domain = DOMAIN_KERNEL,
},
[MT_MEMORY_ITCM] = {
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
- L_PTE_USER | L_PTE_EXEC,
+ L_PTE_WRITE | L_PTE_EXEC,
.prot_l1 = PMD_TYPE_TABLE,
- .domain = DOMAIN_IO,
+ .domain = DOMAIN_KERNEL,
},
};
}
early_param("vmalloc", early_vmalloc);
-phys_addr_t lowmem_end_addr;
+static phys_addr_t lowmem_limit __initdata = 0;
static void __init sanity_check_meminfo(void)
{
int i, j, highmem = 0;
- lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
+ lowmem_limit = __pa(vmalloc_min - 1) + 1;
+ memblock_set_current_limit(lowmem_limit);
for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
struct membank *bank = &meminfo.bank[j];
static inline void prepare_page_table(void)
{
unsigned long addr;
+ phys_addr_t end;
/*
* Clear out all the mappings below the kernel image.
for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
pmd_clear(pmd_off_k(addr));
+ /*
+ * Find the end of the first block of lowmem.
+ */
+ end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
+ if (end >= lowmem_limit)
+ end = lowmem_limit;
+
/*
* Clear out all the kernel space mappings, except for the first
* memory bank, up to the end of the vmalloc region.
*/
- for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
+ for (addr = __phys_to_virt(end);
addr < VMALLOC_END; addr += PGDIR_SIZE)
pmd_clear(pmd_off_k(addr));
}
#endif
}
-static inline void map_memory_bank(struct membank *bank)
-{
- struct map_desc map;
-
- map.pfn = bank_pfn_start(bank);
- map.virtual = __phys_to_virt(bank_phys_start(bank));
- map.length = bank_phys_size(bank);
- map.type = MT_MEMORY;
-
- create_mapping(&map);
-}
-
static void __init map_lowmem(void)
{
- struct meminfo *mi = &meminfo;
- int i;
+ struct memblock_region *reg;
/* Map all the lowmem memory banks. */
- for (i = 0; i < mi->nr_banks; i++) {
- struct membank *bank = &mi->bank[i];
+ for_each_memblock(memory, reg) {
+ phys_addr_t start = reg->base;
+ phys_addr_t end = start + reg->size;
+ struct map_desc map;
+
+ if (end > lowmem_limit)
+ end = lowmem_limit;
+ if (start >= end)
+ break;
- if (!bank->highmem)
- map_memory_bank(bank);
- }
-}
+ map.pfn = __phys_to_pfn(start);
+ map.virtual = __phys_to_virt(start);
+ map.length = end - start;
+ map.type = MT_MEMORY;
-static int __init meminfo_cmp(const void *_a, const void *_b)
-{
- const struct membank *a = _a, *b = _b;
- long cmp = bank_pfn_start(a) - bank_pfn_start(b);
- return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+ create_mapping(&map);
+ }
}
/*
{
void *zero_page;
- sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
-
build_mem_type_table();
sanity_check_meminfo();
prepare_page_table();
/* ================================= CACHE ================================ */
.align 5
+
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1020_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+#endif
+ mov pc, lr
+ENDPROC(arm1020_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm1020_dma_unmap_area)
ENTRY(arm1020_cache_fns)
+ .long arm1020_flush_icache_all
.long arm1020_flush_kern_cache_all
.long arm1020_flush_user_cache_all
.long arm1020_flush_user_cache_range
/* ================================= CACHE ================================ */
.align 5
+
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1020e_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+#endif
+ mov pc, lr
+ENDPROC(arm1020e_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm1020e_dma_unmap_area)
ENTRY(arm1020e_cache_fns)
+ .long arm1020e_flush_icache_all
.long arm1020e_flush_kern_cache_all
.long arm1020e_flush_user_cache_all
.long arm1020e_flush_user_cache_range
/* ================================= CACHE ================================ */
.align 5
+
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1022_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+#endif
+ mov pc, lr
+ENDPROC(arm1022_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm1022_dma_unmap_area)
ENTRY(arm1022_cache_fns)
+ .long arm1022_flush_icache_all
.long arm1022_flush_kern_cache_all
.long arm1022_flush_user_cache_all
.long arm1022_flush_user_cache_range
/* ================================= CACHE ================================ */
.align 5
+
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1026_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+#endif
+ mov pc, lr
+ENDPROC(arm1026_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm1026_dma_unmap_area)
ENTRY(arm1026_cache_fns)
+ .long arm1026_flush_icache_all
.long arm1026_flush_kern_cache_all
.long arm1026_flush_user_cache_all
.long arm1026_flush_user_cache_range
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm920_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm920_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm920_dma_unmap_area)
ENTRY(arm920_cache_fns)
+ .long arm920_flush_icache_all
.long arm920_flush_kern_cache_all
.long arm920_flush_user_cache_all
.long arm920_flush_user_cache_range
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm922_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm922_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm922_dma_unmap_area)
ENTRY(arm922_cache_fns)
+ .long arm922_flush_icache_all
.long arm922_flush_kern_cache_all
.long arm922_flush_user_cache_all
.long arm922_flush_user_cache_range
mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
mov pc, lr
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm925_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm925_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm925_dma_unmap_area)
ENTRY(arm925_cache_fns)
+ .long arm925_flush_icache_all
.long arm925_flush_kern_cache_all
.long arm925_flush_user_cache_all
.long arm925_flush_user_cache_range
msr cpsr_c, r3 @ Restore FIQ state
mov pc, lr
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm926_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm926_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(arm926_dma_unmap_area)
ENTRY(arm926_cache_fns)
+ .long arm926_flush_icache_all
.long arm926_flush_kern_cache_all
.long arm926_flush_user_cache_all
.long arm926_flush_user_cache_range
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
mov pc, lr
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm940_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm940_flush_icache_all)
+
/*
* flush_user_cache_all()
*/
ENDPROC(arm940_dma_unmap_area)
ENTRY(arm940_cache_fns)
+ .long arm940_flush_icache_all
.long arm940_flush_kern_cache_all
.long arm940_flush_user_cache_all
.long arm940_flush_user_cache_range
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
mov pc, lr
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm946_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(arm946_flush_icache_all)
+
/*
* flush_user_cache_all()
*/
ENDPROC(arm946_dma_unmap_area)
ENTRY(arm946_cache_fns)
+ .long arm946_flush_icache_all
.long arm946_flush_kern_cache_all
.long arm946_flush_user_cache_all
.long arm946_flush_user_cache_range
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
mov pc, lr
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(feroceon_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(feroceon_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(feroceon_dma_unmap_area)
ENTRY(feroceon_cache_fns)
+ .long feroceon_flush_icache_all
.long feroceon_flush_kern_cache_all
.long feroceon_flush_user_cache_all
.long feroceon_flush_user_cache_range
.long feroceon_dma_flush_range
ENTRY(feroceon_range_cache_fns)
+ .long feroceon_flush_icache_all
.long feroceon_flush_kern_cache_all
.long feroceon_flush_user_cache_all
.long feroceon_flush_user_cache_range
/* ================================= CACHE ================================ */
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(xsc3_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(xsc3_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(xsc3_dma_unmap_area)
ENTRY(xsc3_cache_fns)
+ .long xsc3_flush_icache_all
.long xsc3_flush_kern_cache_all
.long xsc3_flush_user_cache_all
.long xsc3_flush_user_cache_range
/* ================================= CACHE ================================ */
+/*
+ * flush_icache_all()
+ *
+ * Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(xscale_flush_icache_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mov pc, lr
+ENDPROC(xscale_flush_icache_all)
+
/*
* flush_user_cache_all()
*
ENDPROC(xscale_dma_unmap_area)
ENTRY(xscale_cache_fns)
+ .long xscale_flush_icache_all
.long xscale_flush_kern_cache_all
.long xscale_flush_user_cache_all
.long xscale_flush_user_cache_range
obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
+obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
ifdef CONFIG_SND_IMX_SOC
obj-y += ssi-fiq.o
obj-y += ssi-fiq-ksym.o
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
+ * The CPUFREQ driver is for controling CPU frequency. It allows you to change
+ * the CPU clock speed on the fly.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+
+#define CLK32_FREQ 32768
+#define NANOSECOND (1000 * 1000 * 1000)
+
+struct cpu_op *(*get_cpu_op)(int *op);
+
+static int cpu_freq_khz_min;
+static int cpu_freq_khz_max;
+
+static struct clk *cpu_clk;
+static struct cpufreq_frequency_table *imx_freq_table;
+
+static int cpu_op_nr;
+static struct cpu_op *cpu_op_tbl;
+
+static int set_cpu_freq(int freq)
+{
+ int ret = 0;
+ int org_cpu_rate;
+
+ org_cpu_rate = clk_get_rate(cpu_clk);
+ if (org_cpu_rate == freq)
+ return ret;
+
+ ret = clk_set_rate(cpu_clk, freq);
+ if (ret != 0) {
+ printk(KERN_DEBUG "cannot set CPU clock rate\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int mxc_verify_speed(struct cpufreq_policy *policy)
+{
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ return cpufreq_frequency_table_verify(policy, imx_freq_table);
+}
+
+static unsigned int mxc_get_speed(unsigned int cpu)
+{
+ if (cpu)
+ return 0;
+
+ return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int mxc_set_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ int freq_Hz;
+ int ret = 0;
+ unsigned int index;
+
+ cpufreq_frequency_table_target(policy, imx_freq_table,
+ target_freq, relation, &index);
+ freq_Hz = imx_freq_table[index].frequency * 1000;
+
+ freqs.old = clk_get_rate(cpu_clk) / 1000;
+ freqs.new = freq_Hz / 1000;
+ freqs.cpu = 0;
+ freqs.flags = 0;
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ ret = set_cpu_freq(freq_Hz);
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ return ret;
+}
+
+static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int ret;
+ int i;
+
+ printk(KERN_INFO "i.MXC CPU frequency driver\n");
+
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ if (!get_cpu_op)
+ return -EINVAL;
+
+ cpu_clk = clk_get(NULL, "cpu_clk");
+ if (IS_ERR(cpu_clk)) {
+ printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
+ return PTR_ERR(cpu_clk);
+ }
+
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+
+ cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
+ cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
+
+ imx_freq_table = kmalloc(
+ sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
+ GFP_KERNEL);
+ if (!imx_freq_table) {
+ ret = -ENOMEM;
+ goto err1;
+ }
+
+ for (i = 0; i < cpu_op_nr; i++) {
+ imx_freq_table[i].index = i;
+ imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
+
+ if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
+ cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
+
+ if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
+ cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
+ }
+
+ imx_freq_table[i].index = i;
+ imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+ policy->cur = clk_get_rate(cpu_clk) / 1000;
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+ policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
+ policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
+
+ /* Manual states, that PLL stabilizes in two CLK32 periods */
+ policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
+
+ ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
+
+ if (ret < 0) {
+ printk(KERN_ERR "%s: failed to register i.MXC CPUfreq \
+ with error code %d\n", __func__, ret);
+ goto err;
+ }
+
+ cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
+ return 0;
+err:
+ kfree(imx_freq_table);
+err1:
+ clk_put(cpu_clk);
+ return ret;
+}
+
+static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+
+ set_cpu_freq(cpu_freq_khz_max * 1000);
+ clk_put(cpu_clk);
+ kfree(imx_freq_table);
+ return 0;
+}
+
+static struct cpufreq_driver mxc_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = mxc_verify_speed,
+ .target = mxc_set_target,
+ .get = mxc_get_speed,
+ .init = mxc_cpufreq_init,
+ .exit = mxc_cpufreq_exit,
+ .name = "imx",
+};
+
+static int __devinit mxc_cpufreq_driver_init(void)
+{
+ return cpufreq_register_driver(&mxc_driver);
+}
+
+static void mxc_cpufreq_driver_exit(void)
+{
+ cpufreq_unregister_driver(&mxc_driver);
+}
+
+module_init(mxc_cpufreq_driver_init);
+module_exit(mxc_cpufreq_driver_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
+MODULE_DESCRIPTION("CPUfreq driver for i.MX");
+MODULE_LICENSE("GPL");
default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
config IMX_HAVE_PLATFORM_FLEXCAN
- select HAVE_CAN_FLEXCAN
+ select HAVE_CAN_FLEXCAN if CAN
bool
+config IMX_HAVE_PLATFORM_GPIO_KEYS
+ bool
+ default y if ARCH_MX51
+
config IMX_HAVE_PLATFORM_IMX_I2C
bool
obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
obj-y += platform-imx-dma.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
--- /dev/null
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_gpio_keys(
+ const struct gpio_keys_platform_data *pdata)
+{
+ return imx_add_platform_device("gpio-keys", -1, NULL,
+ 0, pdata, sizeof(*pdata));
+}
*/
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
}
}
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param irq interrupt source number
+ * @param enable enable as wake-up if equal to non-zero
+ * @return This function returns 0 on success.
+ */
+static int gpio_set_wake_irq(u32 irq, u32 enable)
+{
+ u32 gpio = irq_to_gpio(irq);
+ u32 gpio_idx = gpio & 0x1F;
+ struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
+
+ if (enable) {
+ if (port->irq_high && (gpio_idx >= 16))
+ enable_irq_wake(port->irq_high);
+ else
+ enable_irq_wake(port->irq);
+ } else {
+ if (port->irq_high && (gpio_idx >= 16))
+ disable_irq_wake(port->irq_high);
+ else
+ disable_irq_wake(port->irq);
+ }
+
+ return 0;
+}
+
static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq,
.mask = gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_set_irq_type,
+ .set_wake = gpio_set_wake_irq,
};
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
resource_size_t irq,
const struct flexcan_platform_data *pdata);
+#include <linux/gpio_keys.h>
+struct platform_device *__init imx_add_gpio_keys(
+ const struct gpio_keys_platform_data *pdata);
+
#include <mach/i2c.h>
struct imx_imx_i2c_data {
int id;
PAD_CTL_PKE | PAD_CTL_HYS)
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
PAD_CTL_SRE_FAST)
+#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
PAD_CTL_SRE_FAST)
#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
#define MXC_INT_FIRI MX31_INT_FIRI
-#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
#define MXC_INT_MBX MX31_INT_MBX
#define MXC_INT_CSPI3 MX31_INT_CSPI3
#define MXC_INT_SIM2 MX31_INT_SIM2
/* these should go away */
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
#define MXC_INT_OWIRE MX35_INT_OWIRE
-#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
-#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
#define MXC_INT_GPU2D MX35_INT_GPU2D
#define MXC_INT_ASRC MX35_INT_ASRC
#define MXC_INT_USBHS MX35_INT_USBHS
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
#ifndef __ASM_ARCH_MXC_H__
#define __ASM_ARCH_MXC_H__
+#include <linux/types.h>
+
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
# define cpu_is_mxc91231() (0)
#endif
+#ifndef __ASSEMBLY__
+
+struct cpu_op {
+ u32 cpu_rate;
+};
+
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
};
struct pxa3xx_nand_flash {
- const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
- const struct pxa3xx_nand_cmdset *cmdset;
-
- uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
- uint32_t page_size; /* Page size in bytes (PAGE_SZ) */
- uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */
- uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */
- uint32_t num_blocks; /* Number of physical blocks in Flash */
- uint32_t chip_id;
+ uint32_t chip_id;
+ unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
+ unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
+ unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
+ unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
+ unsigned int num_blocks; /* Number of physical blocks in Flash */
+
+ struct pxa3xx_nand_cmdset *cmdset; /* NAND command set */
+ struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
};
struct pxa3xx_nand_platform_data {
int
default 128 if S3C24XX_GPIO_EXTRA128
default 64 if S3C24XX_GPIO_EXTRA64
+ default 16 if ARCH_H1940
default 0
config S3C24XX_GPIO_EXTRA64
[7] = {
.name = "S3C2410 flash partition 7",
.offset = SZ_1M * 48,
- .size = SZ_16M,
+ .size = MTDPART_SIZ_FULL,
}
};
return -EINVAL;
}
-static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
-{
- return IRQ_EINT8 + offset;
-}
-
static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
.set_config = s3c_gpio_setcfg_s3c24xx_a,
.get_config = s3c_gpio_getcfg_s3c24xx_a,
struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
.set_config = s3c_gpio_setcfg_s3c24xx,
.get_config = s3c_gpio_getcfg_s3c24xx,
+ .set_pull = s3c_gpio_setpull_1up,
+ .get_pull = s3c_gpio_getpull_1up,
};
struct s3c_gpio_chip s3c24xx_gpios[] = {
[6] = {
.base = S3C2410_GPGCON,
.pm = __gpio_pm(&s3c_gpio_pm_2bit),
+ .irq_base = IRQ_EINT8,
.chip = {
.base = S3C2410_GPG(0),
.owner = THIS_MODULE,
.label = "GPIOG",
.ngpio = 16,
- .to_irq = s3c24xx_gpiolib_bankg_toirq,
+ .to_irq = samsung_gpiolib_to_irq,
},
}, {
.base = S3C2410_GPHCON,
Use the external interrupts (other than GPIO interrupts.)
Note: Do not choose this for S5P6440 and S5P6450.
+config S5P_GPIO_INT
+ bool
+ help
+ Common code for the GPIO interrupts (other than external interrupts.)
+
config S5P_DEV_FIMC0
bool
help
obj-y += clock.o
obj-y += irq.o
obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
+obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
+obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM) += irq-pm.o
# devices
#include <linux/io.h>
#include <asm/div64.h>
+#include <mach/regs-clock.h>
+
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/s5p-clock.h>
.ctrlbit = (1 << 31),
};
-/* ARM clock */
-struct clk clk_arm = {
- .name = "armclk",
- .id = -1,
- .rate = 0,
- .ctrlbit = 0,
-};
-
/* Possible clock sources for APLL Mux */
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
return 0;
}
+int s5p_epll_enable(struct clk *clk, int enable)
+{
+ unsigned int ctrlbit = clk->ctrlbit;
+ unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
+
+ if (enable)
+ __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
+ else
+ __raw_writel(epll_con, S5P_EPLL_CON);
+
+ return 0;
+}
+
+unsigned long s5p_epll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
static struct clk *s5p_clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_48m,
&clk_fout_epll,
&clk_fout_dpll,
&clk_fout_vpll,
- &clk_arm,
&clk_vpll,
&clk_xusbxti,
};
((irq) - S5P_EINT_BASE1) : \
((irq) + 16 - S5P_EINT_BASE2))
+#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
+
+/* Typically only a few gpio chips require gpio interrupt support.
+ To avoid memory waste irq descriptors are allocated only for
+ S5P_GPIOINT_GROUP_COUNT chips, each with total number of
+ S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
+ to any gpio chip with the s5p_register_gpio_interrupt() function */
+#define S5P_GPIOINT_GROUP_COUNT 4
+#define S5P_GPIOINT_GROUP_SIZE 8
+#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
+
+/* IRQ types common for all s5p platforms */
+#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
+#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
+#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
+#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
+#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
+
#endif /* __ASM_PLAT_S5P_IRQS_H */
#ifndef __ASM_PLAT_MAP_S5P_H
#define __ASM_PLAT_MAP_S5P_H __FILE__
-#define S5P_VA_CHIPID S3C_ADDR(0x00700000)
-#define S5P_VA_GPIO S3C_ADDR(0x00500000)
-#define S5P_VA_SYSTIMER S3C_ADDR(0x01200000)
-#define S5P_VA_SROMC S3C_ADDR(0x01100000)
-#define S5P_VA_SYSRAM S3C_ADDR(0x01180000)
-
-#define S5P_VA_COMBINER_BASE S3C_ADDR(0x00600000)
+#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
+#define S5P_VA_CMU S3C_ADDR(0x02100000)
+#define S5P_VA_GPIO S3C_ADDR(0x02200000)
+#define S5P_VA_GPIO1 S5P_VA_GPIO
+#define S5P_VA_GPIO2 S3C_ADDR(0x02240000)
+#define S5P_VA_GPIO3 S3C_ADDR(0x02280000)
+
+#define S5P_VA_SYSRAM S3C_ADDR(0x02400000)
+#define S5P_VA_DMC0 S3C_ADDR(0x02440000)
+#define S5P_VA_DMC1 S3C_ADDR(0x02480000)
+#define S5P_VA_SROMC S3C_ADDR(0x024C0000)
+
+#define S5P_VA_SYSTIMER S3C_ADDR(0x02500000)
+#define S5P_VA_L2CC S3C_ADDR(0x02600000)
+
+#define S5P_VA_COMBINER_BASE S3C_ADDR(0x02700000)
#define S5P_VA_COMBINER(x) (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
-#define S5P_VA_COREPERI_BASE S3C_ADDR(0x00800000)
+#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
-#define S5P_VA_L2CC S3C_ADDR(0x00900000)
-#define S5P_VA_CMU S3C_ADDR(0x00920000)
+#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
+
+#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
+#define VA_VIC0 VA_VIC(0)
+#define VA_VIC1 VA_VIC(1)
+#define VA_VIC2 VA_VIC(2)
+#define VA_VIC3 VA_VIC(3)
#define S5P_VA_UART(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_VA_UART0 S5P_VA_UART(0)
#define S3C_UART_OFFSET (0x400)
#endif
-#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
-#define VA_VIC0 VA_VIC(0)
-#define VA_VIC1 VA_VIC(1)
-#define VA_VIC2 VA_VIC(2)
-#define VA_VIC3 VA_VIC(3)
-
#endif /* __ASM_PLAT_MAP_S5P_H */
extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
+/* Common EPLL operations for S5P platform */
+extern int s5p_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p_epll_get_rate(struct clk *clk);
+
#endif /* __ASM_PLAT_S5P_CLOCK_H */
switch (type) {
case IRQ_TYPE_EDGE_RISING:
- newvalue = S5P_EXTINT_RISEEDGE;
+ newvalue = S5P_IRQ_TYPE_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
- newvalue = S5P_EXTINT_FALLEDGE;
+ newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
- newvalue = S5P_EXTINT_BOTHEDGE;
+ newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_LOW:
- newvalue = S5P_EXTINT_LOWLEV;
+ newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
break;
case IRQ_TYPE_LEVEL_HIGH:
- newvalue = S5P_EXTINT_HILEV;
+ newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
break;
default:
--- /dev/null
+/* linux/arch/arm/plat-s5p/irq-gpioint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Author: Kyungmin Park <kyungmin.park@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+
+#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
+
+#define GPIOINT_CON_OFFSET 0x700
+#define GPIOINT_MASK_OFFSET 0x900
+#define GPIOINT_PEND_OFFSET 0xA00
+
+static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
+
+static int s5p_gpioint_get_group(unsigned int irq)
+{
+ struct gpio_chip *chip = get_irq_data(irq);
+ struct s3c_gpio_chip *s3c_chip = container_of(chip,
+ struct s3c_gpio_chip, chip);
+ int group;
+
+ for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
+ if (s3c_chip == irq_chips[group])
+ break;
+
+ return group;
+}
+
+static int s5p_gpioint_get_offset(unsigned int irq)
+{
+ struct gpio_chip *chip = get_irq_data(irq);
+ struct s3c_gpio_chip *s3c_chip = container_of(chip,
+ struct s3c_gpio_chip, chip);
+
+ return irq - s3c_chip->irq_base;
+}
+
+static void s5p_gpioint_ack(unsigned int irq)
+{
+ int group, offset, pend_offset;
+ unsigned int value;
+
+ group = s5p_gpioint_get_group(irq);
+ offset = s5p_gpioint_get_offset(irq);
+ pend_offset = group << 2;
+
+ value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+ value |= 1 << offset;
+ __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+}
+
+static void s5p_gpioint_mask(unsigned int irq)
+{
+ int group, offset, mask_offset;
+ unsigned int value;
+
+ group = s5p_gpioint_get_group(irq);
+ offset = s5p_gpioint_get_offset(irq);
+ mask_offset = group << 2;
+
+ value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+ value |= 1 << offset;
+ __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_unmask(unsigned int irq)
+{
+ int group, offset, mask_offset;
+ unsigned int value;
+
+ group = s5p_gpioint_get_group(irq);
+ offset = s5p_gpioint_get_offset(irq);
+ mask_offset = group << 2;
+
+ value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+ value &= ~(1 << offset);
+ __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_mask_ack(unsigned int irq)
+{
+ s5p_gpioint_mask(irq);
+ s5p_gpioint_ack(irq);
+}
+
+static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+ int group, offset, con_offset;
+ unsigned int value;
+
+ group = s5p_gpioint_get_group(irq);
+ offset = s5p_gpioint_get_offset(irq);
+ con_offset = group << 2;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ type = S5P_IRQ_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ type = S5P_IRQ_TYPE_EDGE_FALLING;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ type = S5P_IRQ_TYPE_EDGE_BOTH;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ type = S5P_IRQ_TYPE_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ type = S5P_IRQ_TYPE_LEVEL_LOW;
+ break;
+ case IRQ_TYPE_NONE:
+ default:
+ printk(KERN_WARNING "No irq type\n");
+ return -EINVAL;
+ }
+
+ value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+ value &= ~(0x7 << (offset * 0x4));
+ value |= (type << (offset * 0x4));
+ __raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+
+ return 0;
+}
+
+struct irq_chip s5p_gpioint = {
+ .name = "s5p_gpioint",
+ .ack = s5p_gpioint_ack,
+ .mask = s5p_gpioint_mask,
+ .mask_ack = s5p_gpioint_mask_ack,
+ .unmask = s5p_gpioint_unmask,
+ .set_type = s5p_gpioint_set_type,
+};
+
+static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+ int group, offset, pend_offset, mask_offset;
+ int real_irq;
+ unsigned int pend, mask;
+
+ for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
+ pend_offset = group << 2;
+ pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
+ pend_offset);
+ if (!pend)
+ continue;
+
+ mask_offset = group << 2;
+ mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
+ mask_offset);
+ pend &= ~mask;
+
+ for (offset = 0; offset < 8; offset++) {
+ if (pend & (1 << offset)) {
+ struct s3c_gpio_chip *chip = irq_chips[group];
+ if (chip) {
+ real_irq = chip->irq_base + offset;
+ generic_handle_irq(real_irq);
+ }
+ }
+ }
+ }
+}
+
+static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
+{
+ static int used_gpioint_groups = 0;
+ static bool handler_registered = 0;
+ int irq, group = chip->group;
+ int i;
+
+ if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
+ return -ENOMEM;
+
+ chip->irq_base = S5P_GPIOINT_BASE +
+ used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
+ used_gpioint_groups++;
+
+ if (!handler_registered) {
+ set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
+ handler_registered = 1;
+ }
+
+ irq_chips[group] = chip;
+ for (i = 0; i < chip->chip.ngpio; i++) {
+ irq = chip->irq_base + i;
+ set_irq_chip(irq, &s5p_gpioint);
+ set_irq_data(irq, &chip->chip);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+ return 0;
+}
+
+int __init s5p_register_gpio_interrupt(int pin)
+{
+ struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
+ int offset, group;
+ int ret;
+
+ if (!my_chip)
+ return -EINVAL;
+
+ offset = pin - my_chip->chip.base;
+ group = my_chip->group;
+
+ /* check if the group has been already registered */
+ if (my_chip->irq_base)
+ return my_chip->irq_base + offset;
+
+ /* register gpio group */
+ ret = s5p_gpioint_add(my_chip);
+ if (ret == 0) {
+ my_chip->chip.to_irq = samsung_gpiolib_to_irq;
+ printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
+ group);
+ return my_chip->irq_base + offset;
+ }
+ return ret;
+}
--- /dev/null
+/* linux/arch/arm/plat-s5p/irq-pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Based on arch/arm/plat-s3c24xx/irq-pm.c,
+ * Copyright (c) 2003,2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+
+#include <plat/cpu.h>
+#include <plat/irqs.h>
+#include <plat/pm.h>
+#include <mach/map.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
+
+/* state for IRQs over sleep */
+
+/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
+ * as wakeup sources
+ *
+ * set bit to 1 in allow bitfield to enable the wakeup settings on it
+*/
+
+unsigned long s3c_irqwake_intallow = 0x00000006L;
+unsigned long s3c_irqwake_eintallow = 0xffffffffL;
+
+int s3c_irq_wake(unsigned int irqno, unsigned int state)
+{
+ unsigned long irqbit;
+
+ switch (irqno) {
+ case IRQ_RTC_TIC:
+ case IRQ_RTC_ALARM:
+ irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
+ if (!state)
+ s3c_irqwake_intmask |= irqbit;
+ else
+ s3c_irqwake_intmask &= ~irqbit;
+ break;
+ default:
+ return -ENOENT;
+ }
+ return 0;
+}
+
+static struct sleep_save eint_save[] = {
+ SAVE_ITEM(S5P_EINT_CON(0)),
+ SAVE_ITEM(S5P_EINT_CON(1)),
+ SAVE_ITEM(S5P_EINT_CON(2)),
+ SAVE_ITEM(S5P_EINT_CON(3)),
+
+ SAVE_ITEM(S5P_EINT_FLTCON(0)),
+ SAVE_ITEM(S5P_EINT_FLTCON(1)),
+ SAVE_ITEM(S5P_EINT_FLTCON(2)),
+ SAVE_ITEM(S5P_EINT_FLTCON(3)),
+ SAVE_ITEM(S5P_EINT_FLTCON(4)),
+ SAVE_ITEM(S5P_EINT_FLTCON(5)),
+ SAVE_ITEM(S5P_EINT_FLTCON(6)),
+ SAVE_ITEM(S5P_EINT_FLTCON(7)),
+
+ SAVE_ITEM(S5P_EINT_MASK(0)),
+ SAVE_ITEM(S5P_EINT_MASK(1)),
+ SAVE_ITEM(S5P_EINT_MASK(2)),
+ SAVE_ITEM(S5P_EINT_MASK(3)),
+};
+
+int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
+{
+ s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
+
+ return 0;
+}
+
+int s3c24xx_irq_resume(struct sys_device *dev)
+{
+ s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
+
+ return 0;
+}
+
--- /dev/null
+/* linux/arch/arm/plat-s5p/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * S5P Power Manager (Suspend-To-RAM) support
+ *
+ * Based on arch/arm/plat-s3c24xx/pm.c
+ * Copyright (c) 2004,2006 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <plat/pm.h>
+
+#define PFX "s5p pm: "
+
+/* s3c_pm_check_resume_pin
+ *
+ * check to see if the pin is configured correctly for sleep mode, and
+ * make any necessary adjustments if it is not
+*/
+
+static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
+{
+ /* nothing here yet */
+}
+
+/* s3c_pm_configure_extint
+ *
+ * configure all external interrupt pins
+*/
+
+void s3c_pm_configure_extint(void)
+{
+ /* nothing here yet */
+}
+
+void s3c_pm_restore_core(void)
+{
+ /* nothing here yet */
+}
+
+void s3c_pm_save_core(void)
+{
+ /* nothing here yet */
+}
+
help
Compile in platform device definitions for I2C channel 2
+config S3C_DEV_I2C3
+ bool
+ help
+ Compile in platform device definition for I2C controller 3
+
+config S3C_DEV_I2C4
+ bool
+ help
+ Compile in platform device definition for I2C controller 4
+
+config S3C_DEV_I2C5
+ bool
+ help
+ Compile in platform device definition for I2C controller 5
+
+config S3C_DEV_I2C6
+ bool
+ help
+ Compile in platform device definition for I2C controller 6
+
+config S3C_DEV_I2C7
+ bool
+ help
+ Compile in platform device definition for I2C controller 7
+
config S3C_DEV_FB
bool
help
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_I2C2) += dev-i2c2.o
+obj-$(CONFIG_S3C_DEV_I2C3) += dev-i2c3.o
+obj-$(CONFIG_S3C_DEV_I2C4) += dev-i2c4.o
+obj-$(CONFIG_S3C_DEV_I2C5) += dev-i2c5.o
+obj-$(CONFIG_S3C_DEV_I2C6) += dev-i2c6.o
+obj-$(CONFIG_S3C_DEV_I2C7) += dev-i2c7.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
obj-y += dev-uart.o
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc0 = {
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
- set->max_width = pd->max_width;
set->cd_type = pd->cd_type;
set->ext_cd_init = pd->ext_cd_init;
set->ext_cd_cleanup = pd->ext_cd_cleanup;
set->ext_cd_gpio = pd->ext_cd_gpio;
set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+ if (pd->max_width)
+ set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
- set->host_caps = pd->host_caps;
+ set->host_caps |= pd->host_caps;
+ if (pd->clk_type)
+ set->clk_type = pd->clk_type;
}
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc1 = {
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
- set->max_width = pd->max_width;
set->cd_type = pd->cd_type;
set->ext_cd_init = pd->ext_cd_init;
set->ext_cd_cleanup = pd->ext_cd_cleanup;
set->ext_cd_gpio = pd->ext_cd_gpio;
set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+ if (pd->max_width)
+ set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
- set->host_caps = pd->host_caps;
+ set->host_caps |= pd->host_caps;
+ if (pd->clk_type)
+ set->clk_type = pd->clk_type;
}
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc2 = {
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
- set->max_width = pd->max_width;
set->cd_type = pd->cd_type;
set->ext_cd_init = pd->ext_cd_init;
set->ext_cd_cleanup = pd->ext_cd_cleanup;
set->ext_cd_gpio = pd->ext_cd_gpio;
set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+ if (pd->max_width)
+ set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
if (pd->host_caps)
- set->host_caps = pd->host_caps;
+ set->host_caps |= pd->host_caps;
+ if (pd->clk_type)
+ set->clk_type = pd->clk_type;
}
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_MMC3,
- .end = IRQ_MMC3,
+ .start = IRQ_HSMMC3,
+ .end = IRQ_HSMMC3,
.flags = IORESOURCE_IRQ,
}
};
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+ .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
};
struct platform_device s3c_device_hsmmc3 = {
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
- set->max_width = pd->max_width;
set->cd_type = pd->cd_type;
set->ext_cd_init = pd->ext_cd_init;
set->ext_cd_cleanup = pd->ext_cd_cleanup;
set->ext_cd_gpio = pd->ext_cd_gpio;
set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+ if (pd->max_width)
+ set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
+ if (pd->host_caps)
+ set->host_caps |= pd->host_caps;
+ if (pd->clk_type)
+ set->clk_type = pd->clk_type;
}
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = IRQ_CAN0,
- .end = IRQ_CAN0,
+ .start = IRQ_IIC2,
+ .end = IRQ_IIC2,
.flags = IORESOURCE_IRQ,
},
};
--- /dev/null
+/* linux/arch/arm/plat-samsung/dev-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC3,
+ .end = S3C_PA_IIC3 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC3,
+ .end = IRQ_IIC3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c3 = {
+ .name = "s3c2440-i2c",
+ .id = 3,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data3 __initdata = {
+ .flags = 0,
+ .bus_num = 3,
+ .slave_addr = 0x10,
+ .frequency = 100*1000,
+ .sda_delay = 100,
+};
+
+void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data3;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c3_cfg_gpio;
+
+ s3c_device_i2c3.dev.platform_data = npd;
+}
--- /dev/null
+/* linux/arch/arm/plat-samsung/dev-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC4,
+ .end = S3C_PA_IIC4 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC4,
+ .end = IRQ_IIC4,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c4 = {
+ .name = "s3c2440-i2c",
+ .id = 4,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data4 __initdata = {
+ .flags = 0,
+ .bus_num = 4,
+ .slave_addr = 0x10,
+ .frequency = 100*1000,
+ .sda_delay = 100,
+};
+
+void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data4;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c4_cfg_gpio;
+
+ s3c_device_i2c4.dev.platform_data = npd;
+}
--- /dev/null
+/* linux/arch/arm/plat-samsung/dev-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC5,
+ .end = S3C_PA_IIC5 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC5,
+ .end = IRQ_IIC5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c5 = {
+ .name = "s3c2440-i2c",
+ .id = 5,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data5 __initdata = {
+ .flags = 0,
+ .bus_num = 5,
+ .slave_addr = 0x10,
+ .frequency = 100*1000,
+ .sda_delay = 100,
+};
+
+void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data5;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c5_cfg_gpio;
+
+ s3c_device_i2c5.dev.platform_data = npd;
+}
--- /dev/null
+/* linux/arch/arm/plat-samsung/dev-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 6
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC6,
+ .end = S3C_PA_IIC6 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC6,
+ .end = IRQ_IIC6,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c6 = {
+ .name = "s3c2440-i2c",
+ .id = 6,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data6 __initdata = {
+ .flags = 0,
+ .bus_num = 6,
+ .slave_addr = 0x10,
+ .frequency = 100*1000,
+ .sda_delay = 100,
+};
+
+void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data6;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c6_cfg_gpio;
+
+ s3c_device_i2c6.dev.platform_data = npd;
+}
--- /dev/null
+/* linux/arch/arm/plat-samsung/dev-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 7
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC7,
+ .end = S3C_PA_IIC7 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC7,
+ .end = IRQ_IIC7,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c7 = {
+ .name = "s3c2440-i2c",
+ .id = 7,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data7 __initdata = {
+ .flags = 0,
+ .bus_num = 7,
+ .slave_addr = 0x10,
+ .frequency = 100*1000,
+ .sda_delay = 100,
+};
+
+void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data7;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c7_cfg_gpio;
+
+ s3c_device_i2c7.dev.platform_data = npd;
+}
}
EXPORT_SYMBOL(s3c_gpio_cfgpin);
+int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
+ unsigned int cfg)
+{
+ int ret;
+
+ for (; nr > 0; nr--, start++) {
+ ret = s3c_gpio_cfgpin(start, cfg);
+ if (ret != 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
+
+int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
+ unsigned int cfg, s3c_gpio_pull_t pull)
+{
+ int ret;
+
+ for (; nr > 0; nr--, start++) {
+ s3c_gpio_setpull(start, pull);
+ ret = s3c_gpio_cfgpin(start, cfg);
+ if (ret != 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
+
unsigned s3c_gpio_getcfg(unsigned int pin)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
}
EXPORT_SYMBOL(s3c_gpio_setpull);
+s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
+{
+ struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+ unsigned long flags;
+ int offset;
+ u32 pup = 0;
+
+ if (chip) {
+ offset = pin - chip->chip.base;
+
+ s3c_gpio_lock(chip, flags);
+ pup = s3c_gpio_do_getpull(chip, offset);
+ s3c_gpio_unlock(chip, flags);
+ }
+
+ return (__force s3c_gpio_pull_t)pup;
+}
+EXPORT_SYMBOL(s3c_gpio_getpull);
+
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
if (ret >= 0)
s3c_gpiolib_track(chip);
}
+
+int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+ struct s3c_gpio_chip *s3c_chip = container_of(chip,
+ struct s3c_gpio_chip, chip);
+
+ return s3c_chip->irq_base + offset;
+}
#define S3C64XX_AC97_GPE 1
extern void s3c64xx_ac97_setup_gpio(int);
+/*
+ * The machine init code calls s5p*_spdif_setup_gpio with
+ * one of these defines in order to select appropriate bank
+ * of GPIO for S/PDIF pins
+ */
+#define S5PC100_SPDIF_GPD 0
+#define S5PC100_SPDIF_GPG3 1
+extern void s5pc100_spdif_setup_gpio(int);
+
/**
* struct s3c_audio_pdata - common platform data for audio device drivers
* @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_i2c2;
+extern struct platform_device s3c_device_i2c3;
+extern struct platform_device s3c_device_i2c4;
+extern struct platform_device s3c_device_i2c5;
+extern struct platform_device s3c_device_i2c6;
+extern struct platform_device s3c_device_i2c7;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s5pv210_device_iis0;
extern struct platform_device s5pv210_device_iis1;
extern struct platform_device s5pv210_device_iis2;
+extern struct platform_device s5pv210_device_spdif;
extern struct platform_device s5p6442_device_pcm0;
extern struct platform_device s5p6442_device_pcm1;
extern struct platform_device s5pc100_device_iis0;
extern struct platform_device s5pc100_device_iis1;
extern struct platform_device s5pc100_device_iis2;
+extern struct platform_device s5pc100_device_spdif;
extern struct platform_device samsung_device_keypad;
return (chip->config->set_pull)(chip, off, pull);
}
+static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip,
+ unsigned int off)
+{
+ return chip->config->get_pull(chip, off);
+}
+
/**
* s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
* @chip: The gpio chip that is being configured.
*/
extern unsigned s3c_gpio_getcfg(unsigned int pin);
+/**
+ * s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range
+ * @start: The pin number to start at
+ * @nr: The number of pins to configure from @start.
+ * @cfg: The configuration for the pin's function
+ *
+ * Call s3c_gpio_cfgpin() for the @nr pins starting at @start.
+ *
+ * @sa s3c_gpio_cfgpin.
+ */
+extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
+ unsigned int cfg);
+
/* Define values for the pull-{up,down} available for each gpio pin.
*
* These values control the state of the weak pull-{up,down} resistors
*/
extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
+/* configure `all` aspects of an gpio */
+
+/**
+ * s3c_gpio_cfgall_range() - configure range of gpio functtion and pull.
+ * @start: The gpio number to start at.
+ * @nr: The number of gpio to configure from @start.
+ * @cfg: The configuration to use
+ * @pull: The pull setting to use.
+ *
+ * Run s3c_gpio_cfgpin() and s3c_gpio_setpull() over the gpio range starting
+ * @gpio and running for @size.
+ *
+ * @sa s3c_gpio_cfgpin
+ * @sa s3c_gpio_setpull
+ * @sa s3c_gpio_cfgpin_range
+ */
+extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
+ unsigned int cfg, s3c_gpio_pull_t pull);
+
+static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
+ unsigned int cfg)
+{
+ return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
+}
+
/* Define values for the drvstr available for each gpio pin.
*
* These values control the value of the output signal driver strength,
*/
extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
+/**
+ * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
+ * @pin: The pin number from the group to be registered
+ *
+ * This function registers gpio interrupt support for the group that the
+ * specified pin belongs to.
+ *
+ * The total number of gpio pins is quite large ob s5p series. Registering
+ * irq support for all of them would be a resource waste. Because of that the
+ * interrupt support for standard gpio pins is registered dynamically.
+ *
+ * It will return the irq number of the interrupt that has been registered
+ * or -ENOMEM if no more gpio interrupts can be registered. It is allowed
+ * to call this function more than once for the same gpio group (the group
+ * will be registered only once).
+ */
+extern int s5p_register_gpio_interrupt(int pin);
+
#endif /* __PLAT_GPIO_CFG_H */
* struct s3c_gpio_chip - wrapper for specific implementation of gpio
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
+ * @group: The group register number for gpio interrupt support.
+ * @irq_base: The base irq number.
* @config: special function and pull-resistor control information.
* @lock: Lock for exclusive access to this gpio bank.
* @pm_save: Save information for suspend/resume support.
struct s3c_gpio_cfg *config;
struct s3c_gpio_pm *pm;
void __iomem *base;
+ int irq_base;
+ int group;
spinlock_t lock;
#ifdef CONFIG_PM
u32 pm_save[4];
extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
+
+/**
+ * samsung_gpiolib_to_irq - convert gpio pin to irq number
+ * @chip: The gpio chip that the pin belongs to.
+ * @offset: The offset of the pin in the chip.
+ *
+ * This helper returns the irq number calculated from the chip->irq_base and
+ * the provided offset.
+ */
+extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
+
/* exported for core SoC support to change */
extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c3_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c4_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARCH_IIC_H */
#ifndef __ASM_PLAT_MAP_H
#define __ASM_PLAT_MAP_H __FILE__
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+/* Fit all our registers in at 0xF6000000 upwards, trying to use as
* little of the VA space as possible so vmalloc and friends have a
* better chance of getting memory.
*
* an single MOVS instruction (ie, only 8 bits of set data)
*/
-#define S3C_ADDR_BASE (0xF4000000)
+#define S3C_ADDR_BASE 0xF6000000
#ifndef __ASSEMBLY__
#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
--- /dev/null
+/* arch/arm/plat-samsung/include/plat/nand-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S3C - Nand Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_NAND_CORE_H
+#define __ASM_ARCH_NAND_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_nand_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_NAND
+ s3c_device_nand.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_NAND_CORE_H */
S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
};
+enum clk_types {
+ S3C_SDHCI_CLK_DIV_INTERNAL, /* use mmc internal clock divider */
+ S3C_SDHCI_CLK_DIV_EXTERNAL, /* use external clock divider */
+};
+
/**
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @clk_type: Type of clock divider method (see clk_types enum above)
* @ext_cd_init: Initialize external card detect subsystem. Called on
* sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
* notify_func argument is a callback to the sdhci-s3c driver
unsigned int max_width;
unsigned int host_caps;
enum cd_types cd_type;
+ enum clk_types clk_type;
char **clocks; /* set of clock sources */
extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
/* S3C64XX SDHCI setup */
#endif /* CONFIG_S5PV210_SETUP_SDHCI */
+/* S5PV310 SDHCI setup */
+#ifdef CONFIG_S5PV310_SETUP_SDHCI
+extern char *s5pv310_hsmmc_clksrcs[4];
+
+extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev,
+ void __iomem *r,
+ struct mmc_ios *ios,
+ struct mmc_card *card);
+
+static inline void s5pv310_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+ s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+ s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio;
+ s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+ s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+ s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio;
+ s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+ s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+ s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio;
+ s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci3(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC3
+ s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+ s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio;
+ s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+#else
+static inline void s5pv310_default_sdhci0(void) { }
+static inline void s5pv310_default_sdhci1(void) { }
+static inline void s5pv310_default_sdhci2(void) { }
+static inline void s5pv310_default_sdhci3(void) { }
+
+#endif /* CONFIG_S5PV310_SETUP_SDHCI */
+
#endif /* __PLAT_S3C_SDHCI_H */
.resume = s3c_gpio_pm_2bit_resume,
};
-#ifdef CONFIG_ARCH_S3C64XX
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
{
chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
.save = s3c_gpio_pm_4bit_save,
.resume = s3c_gpio_pm_4bit_resume,
};
-#endif /* CONFIG_ARCH_S3C64XX */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
/**
* s3c_pm_save_gpio() - save gpio chip data for suspend
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
#include <asm/hardware/pl330.h>
* @node: To attach to the global list of DMACs.
* @pi: PL330 configuration info for the DMAC.
* @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
+ * @clk: Pointer of DMAC operation clock.
*/
struct s3c_pl330_dmac {
unsigned busy_chan;
struct list_head node;
struct pl330_info *pi;
struct kmem_cache *kmcache;
+ struct clk *clk;
};
/**
if (ret)
goto probe_err4;
- ret = pl330_add(pl330_info);
- if (ret)
- goto probe_err5;
-
/* Allocate a new DMAC */
s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL);
if (!s3c_pl330_dmac) {
ret = -ENOMEM;
+ goto probe_err5;
+ }
+
+ /* Get operation clock and enable it */
+ s3c_pl330_dmac->clk = clk_get(&pdev->dev, "pdma");
+ if (IS_ERR(s3c_pl330_dmac->clk)) {
+ dev_err(&pdev->dev, "Cannot get operation clock.\n");
+ ret = -EINVAL;
goto probe_err6;
}
+ clk_enable(s3c_pl330_dmac->clk);
+
+ ret = pl330_add(pl330_info);
+ if (ret)
+ goto probe_err7;
/* Hook the info */
s3c_pl330_dmac->pi = pl330_info;
if (!s3c_pl330_dmac->kmcache) {
ret = -ENOMEM;
- goto probe_err7;
+ goto probe_err8;
}
/* Get the list of peripherals */
return 0;
+probe_err8:
+ pl330_del(pl330_info);
probe_err7:
- kfree(s3c_pl330_dmac);
+ clk_disable(s3c_pl330_dmac->clk);
+ clk_put(s3c_pl330_dmac->clk);
probe_err6:
- pl330_del(pl330_info);
+ kfree(s3c_pl330_dmac);
probe_err5:
free_irq(irq, pl330_info);
probe_err4:
}
}
+ /* Disable operation clock */
+ clk_disable(dmac->clk);
+ clk_put(dmac->clk);
+
/* Remove the DMAC */
list_del(&dmac->node);
kfree(dmac);
}
}
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void bfin_disable_hw_debug(struct pt_regs *regs)
{
/* Disable hardware debugging while we are in kgdb */
bfin_write_WPIACTL(0);
#endif
.set_hw_breakpoint = bfin_set_hw_break,
.remove_hw_breakpoint = bfin_remove_hw_break,
+ .disable_hw_break = bfin_disable_hw_debug,
.remove_all_hw_break = bfin_remove_all_hw_break,
.correct_hw_break = bfin_correct_hw_break,
};
}
-static int
-pfmfs_get_sb(struct file_system_type *fs_type, int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *
+pfmfs_mount(struct file_system_type *fs_type, int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC, mnt);
+ return mount_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC);
}
static struct file_system_type pfm_fs_type = {
.name = "pfmfs",
- .get_sb = pfmfs_get_sb,
+ .mount = pfmfs_mount,
.kill_sb = kill_anon_super,
};
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
select HAVE_OPROFILE
+ select HAVE_PERF_EVENTS
+ select PERF_USE_VMALLOC
select HAVE_ARCH_KGDB
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
+ select HAVE_C_RECORDMCOUNT
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_KPROBES
select HAVE_KRETPROBES
select RTC_LIB if !MACH_LOONGSON
select GENERIC_ATOMIC64 if !64BIT
+ select HAVE_DMA_ATTRS
+ select HAVE_DMA_API_DEBUG
menu "Machine selection"
select SWAP_IO_SPACE
select HW_HAS_PCI
select ARCH_SUPPORTS_MSI
+ select ZONE_DMA32
+ select USB_ARCH_HAS_OHCI
+ select USB_ARCH_HAS_EHCI
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
Full details can be found at http://www.caviumnetworks.com.
+config CPU_BMIPS3300
+ bool "BMIPS3300"
+ depends on SYS_HAS_CPU_BMIPS3300
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS3300 processors.
+
+config CPU_BMIPS4350
+ bool "BMIPS4350"
+ depends on SYS_HAS_CPU_BMIPS4350
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS4350 ("VIPER") processors.
+
+config CPU_BMIPS4380
+ bool "BMIPS4380"
+ depends on SYS_HAS_CPU_BMIPS4380
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS4380 processors.
+
+config CPU_BMIPS5000
+ bool "BMIPS5000"
+ depends on SYS_HAS_CPU_BMIPS5000
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_HIGHMEM
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SWAP_IO_SPACE
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_HOTPLUG_CPU
+ select WEAK_ORDERING
+ help
+ Broadcom BMIPS5000 processors.
+
endchoice
if CPU_LOONGSON2F
config SYS_HAS_CPU_CAVIUM_OCTEON
bool
+config SYS_HAS_CPU_BMIPS3300
+ bool
+
+config SYS_HAS_CPU_BMIPS4350
+ bool
+
+config SYS_HAS_CPU_BMIPS4380
+ bool
+
+config SYS_HAS_CPU_BMIPS5000
+ bool
+
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
default "6"
depends on NEED_MULTIPLE_NODES
+config HW_PERF_EVENTS
+ bool "Enable hardware performance counter support for perf events"
+ depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+ default y
+ help
+ Enable hardware performance counter support for perf events. If
+ disabled, perf events will use software events only.
+
source "mm/Kconfig"
config SMP
Normally, you will choose 'N' here.
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+ help
+ This option will cause messages to be printed if free stack space
+ drops below a certain limit(2GB on MIPS). The debugging option
+ provides another way to check stack overflow happened on kernel mode
+ stack usually caused by nested interruption.
+
config DEBUG_STACK_USAGE
bool "Enable stack utilization instrumentation"
depends on DEBUG_KERNEL
endif
endif
-ifndef CONFIG_FUNCTION_TRACER
-cflags-y := -ffunction-sections
-endif
ifdef CONFIG_FUNCTION_GRAPH_TRACER
ifndef KBUILD_MCOUNT_RA_ADDRESS
ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
endif
+cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
- * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
return readl(gpio_in) & (1 << gpio);
}
+static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
+ void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
+
+ return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
static void ar7_gpio_set_value(struct gpio_chip *chip,
unsigned gpio, int value)
{
writel(tmp, gpio_out);
}
+static void titan_gpio_set_value(struct gpio_chip *chip,
+ unsigned gpio, int value)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
+ void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
+ unsigned tmp;
+
+ tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+ if (value)
+ tmp |= 1 << (gpio & 0x1f);
+ writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch =
return 0;
}
+static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+ void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_dir1 : gpio_dir0);
+ return 0;
+}
+
static int ar7_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
return 0;
}
+static int titan_gpio_direction_output(struct gpio_chip *chip,
+ unsigned gpio, int value)
+{
+ struct ar7_gpio_chip *gpch =
+ container_of(chip, struct ar7_gpio_chip, chip);
+ void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+ void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ titan_gpio_set_value(chip, gpio, value);
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+ (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
static struct ar7_gpio_chip ar7_gpio_chip = {
.chip = {
.label = "ar7-gpio",
}
};
-int ar7_gpio_enable(unsigned gpio)
+static struct ar7_gpio_chip titan_gpio_chip = {
+ .chip = {
+ .label = "titan-gpio",
+ .direction_input = titan_gpio_direction_input,
+ .direction_output = titan_gpio_direction_output,
+ .set = titan_gpio_set_value,
+ .get = titan_gpio_get_value,
+ .base = 0,
+ .ngpio = TITAN_GPIO_MAX,
+ }
+};
+
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
return 0;
}
+
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+ void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+int ar7_gpio_enable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+ ar7_gpio_enable_ar7(gpio);
+}
EXPORT_SYMBOL(ar7_gpio_enable);
-int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
return 0;
}
+
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+ void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+int ar7_gpio_disable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+ ar7_gpio_disable_ar7(gpio);
+}
EXPORT_SYMBOL(ar7_gpio_disable);
-static int __init ar7_gpio_init(void)
+struct titan_gpio_cfg {
+ u32 reg;
+ u32 shift;
+ u32 func;
+};
+
+static struct titan_gpio_cfg titan_gpio_table[] = {
+ /* reg, start bit, mux value */
+ {4, 24, 1},
+ {4, 26, 1},
+ {4, 28, 1},
+ {4, 30, 1},
+ {5, 6, 1},
+ {5, 8, 1},
+ {5, 10, 1},
+ {5, 12, 1},
+ {7, 14, 3},
+ {7, 16, 3},
+ {7, 18, 3},
+ {7, 20, 3},
+ {7, 22, 3},
+ {7, 26, 3},
+ {7, 28, 3},
+ {7, 30, 3},
+ {8, 0, 3},
+ {8, 2, 3},
+ {8, 4, 3},
+ {8, 10, 3},
+ {8, 14, 3},
+ {8, 16, 3},
+ {8, 18, 3},
+ {8, 20, 3},
+ {9, 8, 3},
+ {9, 10, 3},
+ {9, 12, 3},
+ {9, 14, 3},
+ {9, 18, 3},
+ {9, 20, 3},
+ {9, 24, 3},
+ {9, 26, 3},
+ {9, 28, 3},
+ {9, 30, 3},
+ {10, 0, 3},
+ {10, 2, 3},
+ {10, 8, 3},
+ {10, 10, 3},
+ {10, 12, 3},
+ {10, 14, 3},
+ {13, 12, 3},
+ {13, 14, 3},
+ {13, 16, 3},
+ {13, 18, 3},
+ {13, 24, 3},
+ {13, 26, 3},
+ {13, 28, 3},
+ {13, 30, 3},
+ {14, 2, 3},
+ {14, 6, 3},
+ {14, 8, 3},
+ {14, 12, 3}
+};
+
+static int titan_gpio_pinsel(unsigned gpio)
+{
+ struct titan_gpio_cfg gpio_cfg;
+ u32 mux_status, pin_sel_reg, tmp;
+ void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
+
+ if (gpio >= ARRAY_SIZE(titan_gpio_table))
+ return -EINVAL;
+
+ gpio_cfg = titan_gpio_table[gpio];
+ pin_sel_reg = gpio_cfg.reg - 1;
+
+ mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
+
+ /* Check the mux status */
+ if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
+ return 0;
+
+ /* Set the pin sel value */
+ tmp = readl(pin_sel + pin_sel_reg);
+ tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+ writel(tmp, pin_sel + pin_sel_reg);
+
+ return 0;
+}
+
+/* Perform minimal Titan GPIO configuration */
+static void titan_gpio_init(void)
+{
+ unsigned i;
+
+ for (i = 44; i < 48; i++) {
+ titan_gpio_pinsel(i);
+ ar7_gpio_enable_titan(i);
+ titan_gpio_direction_input(&titan_gpio_chip.chip, i);
+ }
+}
+
+int __init ar7_gpio_init(void)
{
int ret;
+ struct ar7_gpio_chip *gpch;
+ unsigned size;
+
+ if (!ar7_is_titan()) {
+ gpch = &ar7_gpio_chip;
+ size = 0x10;
+ } else {
+ gpch = &titan_gpio_chip;
+ size = 0x1f;
+ }
- ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
+ gpch->regs = ioremap_nocache(AR7_REGS_GPIO,
AR7_REGS_GPIO + 0x10);
- if (!ar7_gpio_chip.regs) {
- printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
+ if (!gpch->regs) {
+ printk(KERN_ERR "%s: failed to ioremap regs\n",
+ gpch->chip.label);
return -ENOMEM;
}
- ret = gpiochip_add(&ar7_gpio_chip.chip);
+ ret = gpiochip_add(&gpch->chip);
if (ret) {
- printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
+ printk(KERN_ERR "%s: failed to add gpiochip\n",
+ gpch->chip.label);
return ret;
}
- printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
- ar7_gpio_chip.chip.ngpio);
+ printk(KERN_INFO "%s: registered %d GPIOs\n",
+ gpch->chip.label, gpch->chip.ngpio);
+
+ if (ar7_is_titan())
+ titan_gpio_init();
+
return ret;
}
-arch_initcall(ar7_gpio_init);
},
};
+static struct gpio_led titan_leds[] = {
+ { .name = "status", .gpio = 8, .active_low = 1, },
+ { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
static struct gpio_led dsl502t_leds[] = {
{
.name = "status",
} else if (strstr(prid, "DG834")) {
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
ar7_led_data.leds = dg834g_leds;
+ } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
+ ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+ ar7_led_data.leds = titan_leds;
}
}
return 0;
}
+static void __init titan_fixup_devices(void)
+{
+ /* Set vlynq0 data */
+ vlynq_low_data.reset_bit = 15;
+ vlynq_low_data.gpio_bit = 14;
+
+ /* Set vlynq1 data */
+ vlynq_high_data.reset_bit = 16;
+ vlynq_high_data.gpio_bit = 7;
+
+ /* Set vlynq0 resources */
+ vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
+ vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
+ vlynq_low_res[1].start = 33;
+ vlynq_low_res[1].end = 33;
+ vlynq_low_res[2].start = 0x0c000000;
+ vlynq_low_res[2].end = 0x0fffffff;
+ vlynq_low_res[3].start = 80;
+ vlynq_low_res[3].end = 111;
+
+ /* Set vlynq1 resources */
+ vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
+ vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
+ vlynq_high_res[1].start = 34;
+ vlynq_high_res[1].end = 34;
+ vlynq_high_res[2].start = 0x40000000;
+ vlynq_high_res[2].end = 0x43ffffff;
+ vlynq_high_res[3].start = 112;
+ vlynq_high_res[3].end = 143;
+
+ /* Set cpmac0 data */
+ cpmac_low_data.phy_mask = 0x40000000;
+
+ /* Set cpmac1 data */
+ cpmac_high_data.phy_mask = 0x80000000;
+
+ /* Set cpmac0 resources */
+ cpmac_low_res[0].start = TITAN_REGS_MAC0;
+ cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
+
+ /* Set cpmac1 resources */
+ cpmac_high_res[0].start = TITAN_REGS_MAC1;
+ cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
+}
+
static int __init ar7_register_devices(void)
{
void __iomem *bootcr;
if (res)
pr_warning("unable to register physmap-flash: %d\n", res);
+ if (ar7_is_titan())
+ titan_fixup_devices();
+
ar7_device_disable(vlynq_low_data.reset_bit);
res = platform_device_register(&vlynq_low);
if (res)
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
ar7_init_env((struct env_var *)fw_arg2);
console_config();
+
+ ar7_gpio_init();
}
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
+#include <asm/mach-ar7/gpio.h>
static void ar7_machine_restart(char *command)
{
const char *get_system_type(void)
{
u16 chip_id = ar7_chip_id();
+ u16 titan_variant_id = titan_chip_id();
+
switch (chip_id) {
case AR7_CHIP_7100:
return "TI AR7 (TNETD7100)";
return "TI AR7 (TNETD7200)";
case AR7_CHIP_7300:
return "TI AR7 (TNETD7300)";
+ case AR7_CHIP_TITAN:
+ switch (titan_variant_id) {
+ case TITAN_CHIP_1050:
+ return "TI AR7 (TNETV1050)";
+ case TITAN_CHIP_1055:
+ return "TI AR7 (TNETV1055)";
+ case TITAN_CHIP_1056:
+ return "TI AR7 (TNETV1056)";
+ case TITAN_CHIP_1060:
+ return "TI AR7 (TNETV1060)";
+ }
default:
return "TI AR7 (unknown)";
}
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/cpu.h>
+#include <asm/cpu.h>
#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
expected_cpu_id = 0;
switch (c->cputype) {
- /*
- * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
- */
- case CPU_BCM3302:
- __cpu_name[cpu] = "Broadcom BCM6338";
- expected_cpu_id = BCM6338_CPU_ID;
- bcm63xx_regs_base = bcm96338_regs_base;
- bcm63xx_irqs = bcm96338_irqs;
+ case CPU_BMIPS3300:
+ if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
+ expected_cpu_id = BCM6348_CPU_ID;
+ bcm63xx_regs_base = bcm96348_regs_base;
+ bcm63xx_irqs = bcm96348_irqs;
+ } else {
+ __cpu_name[cpu] = "Broadcom BCM6338";
+ expected_cpu_id = BCM6338_CPU_ID;
+ bcm63xx_regs_base = bcm96338_regs_base;
+ bcm63xx_irqs = bcm96338_irqs;
+ }
break;
- case CPU_BCM6345:
+ case CPU_BMIPS32:
expected_cpu_id = BCM6345_CPU_ID;
bcm63xx_regs_base = bcm96345_regs_base;
bcm63xx_irqs = bcm96345_irqs;
break;
- case CPU_BCM6348:
- expected_cpu_id = BCM6348_CPU_ID;
- bcm63xx_regs_base = bcm96348_regs_base;
- bcm63xx_irqs = bcm96348_irqs;
- break;
- case CPU_BCM6358:
+ case CPU_BMIPS4350:
expected_cpu_id = BCM6358_CPU_ID;
bcm63xx_regs_base = bcm96358_regs_base;
bcm63xx_irqs = bcm96358_irqs;
depends on CPU_CAVIUM_OCTEON
default "y"
+config CAVIUM_CN63XXP1
+ bool "Enable CN63XXP1 errata worarounds"
+ depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+ default "n"
+ help
+ The CN63XXP1 chip requires build time workarounds to
+ function reliably, select this option to enable them. These
+ workarounds will cause a slight decrease in performance on
+ non-CN63XXP1 hardware, so it is recommended to select "n"
+ unless it is known the workarounds are needed.
+
config CAVIUM_OCTEON_2ND_KERNEL
bool "Build the kernel to be used as a 2nd kernel on the same chip"
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
config CAVIUM_OCTEON_HELPER
def_bool y
depends on OCTEON_ETHERNET || PCI
+
+config IOMMU_HELPER
+ bool
+
+config NEED_SG_DMA_LENGTH
+ bool
+
+config SWIOTLB
+ def_bool y
+ depends on CPU_CAVIUM_OCTEON
+ select IOMMU_HELPER
+ select NEED_SG_DMA_LENGTH
* for more details.
*
* Copyright (C) 2007 by Ralf Baechle
+ * Copyright (C) 2009, 2010 Cavium Networks, Inc.
*/
#include <linux/clocksource.h>
#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/cpu-info.h>
#include <asm/time.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
/*
* Set the current core's cvmcount counter to the value of the
* on-line. This allows for a read from a local cpu register to
* access a synchronized counter.
*
+ * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
*/
void octeon_init_cvmcount(void)
{
unsigned long flags;
unsigned loops = 2;
+ u64 f = 0;
+ u64 rdiv = 0;
+ u64 sdiv = 0;
+ if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
+ union cvmx_mio_rst_boot rst_boot;
+ rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+ rdiv = rst_boot.s.c_mul; /* CPU clock */
+ sdiv = rst_boot.s.pnr_mul; /* I/O clock */
+ f = (0x8000000000000000ull / sdiv) * 2;
+ }
+
/* Clobber loops so GCC will not unroll the following while loop. */
asm("" : "+r" (loops));
* Loop several times so we are executing from the cache,
* which should give more deterministic timing.
*/
- while (loops--)
- write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
+ while (loops--) {
+ u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+ if (rdiv != 0) {
+ ipd_clk_count *= rdiv;
+ if (f != 0) {
+ asm("dmultu\t%[cnt],%[f]\n\t"
+ "mfhi\t%[cnt]"
+ : [cnt] "+r" (ipd_clk_count),
+ [f] "=r" (f)
+ : : "hi", "lo");
+ }
+ }
+ write_c0_cvmcount(ipd_clk_count);
+ }
local_irq_restore(flags);
}
void __init plat_time_init(void)
{
clocksource_mips.rating = 300;
- clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+ clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
clocksource_register(&clocksource_mips);
}
* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
* IP32 changes by Ilya.
- * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
- * the kernels original.
+ * Copyright (C) 2010 Cavium Networks, Inc.
*/
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/string.h>
#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
#include <linux/scatterlist.h>
+#include <linux/bootmem.h>
+#include <linux/swiotlb.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
-#include <linux/cache.h>
-#include <linux/io.h>
+#include <asm/bootinfo.h>
#include <asm/octeon/octeon.h>
+
+#ifdef CONFIG_PCI
+#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>
-#include <dma-coherence.h>
+static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
+{
+ if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
+ return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+ else
+ return paddr;
+}
-#ifdef CONFIG_PCI
-#include <asm/octeon/pci-octeon.h>
-#endif
+static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
+{
+ if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
+ return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
+ else
+ return daddr;
+}
+
+static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+ return octeon_hole_phys_to_dma(paddr);
+}
-#define BAR2_PCI_ADDRESS 0x8000000000ul
+static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ daddr = octeon_hole_dma_to_phys(daddr);
-struct bar1_index_state {
- int16_t ref_count; /* Number of PCI mappings using this index */
- uint16_t address_bits; /* Upper bits of physical address. This is
- shifted 22 bits */
-};
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
-#ifdef CONFIG_PCI
-static DEFINE_RAW_SPINLOCK(bar1_lock);
-static struct bar1_index_state bar1_state[32];
-#endif
+ return daddr;
+}
-dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
+static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
-#ifndef CONFIG_PCI
- /* Without PCI/PCIe this function can be called for Octeon internal
- devices such as USB. These devices all support 64bit addressing */
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+
+ /* Anything in the BAR1 hole or above goes via BAR2 */
+ if (paddr >= 0xf0000000ull)
+ paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+ return paddr;
+}
+
+static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+ daddr -= OCTEON_BAR2_PCI_ADDRESS;
+
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
+ return daddr;
+}
+
+static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
+ phys_addr_t paddr)
+{
+ if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+ paddr -= 0x400000000ull;
+
+ /* Anything not in the BAR1 range goes via BAR2 */
+ if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
+ paddr = paddr - octeon_bar1_pci_phys;
+ else
+ paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+ return paddr;
+}
+
+static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
+ dma_addr_t daddr)
+{
+ if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+ daddr -= OCTEON_BAR2_PCI_ADDRESS;
+ else
+ daddr += octeon_bar1_pci_phys;
+
+ if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+ daddr += 0x400000000ull;
+ return daddr;
+}
+
+#endif /* CONFIG_PCI */
+
+static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
+{
+ dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
+ direction, attrs);
mb();
- return virt_to_phys(ptr);
-#else
- unsigned long flags;
- uint64_t dma_mask;
- int64_t start_index;
- dma_addr_t result = -1;
- uint64_t physical = virt_to_phys(ptr);
- int64_t index;
+ return daddr;
+}
+
+static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
+{
+ int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
mb();
- /*
- * Use the DMA masks to determine the allowed memory
- * region. For us it doesn't limit the actual memory, just the
- * address visible over PCI. Devices with limits need to use
- * lower indexed Bar1 entries.
- */
- if (dev) {
- dma_mask = dev->coherent_dma_mask;
- if (dev->dma_mask)
- dma_mask = *dev->dma_mask;
- } else {
- dma_mask = 0xfffffffful;
- }
+ return r;
+}
- /*
- * Platform devices, such as the internal USB, skip all
- * translation and use Octeon physical addresses directly.
- */
- if (!dev || dev->bus == &platform_bus_type)
- return physical;
+static void octeon_dma_sync_single_for_device(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
+{
+ swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
+ mb();
+}
- switch (octeon_dma_bar_type) {
- case OCTEON_DMA_BAR_TYPE_PCIE:
- if (unlikely(physical < (16ul << 10)))
- panic("dma_map_single: Not allowed to map first 16KB."
- " It interferes with BAR0 special area\n");
- else if ((physical + size >= (256ul << 20)) &&
- (physical < (512ul << 20)))
- panic("dma_map_single: Not allowed to map bootbus\n");
- else if ((physical + size >= 0x400000000ull) &&
- physical < 0x410000000ull)
- panic("dma_map_single: "
- "Attempt to map illegal memory address 0x%llx\n",
- physical);
- else if (physical >= 0x420000000ull)
- panic("dma_map_single: "
- "Attempt to map illegal memory address 0x%llx\n",
- physical);
- else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
- physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
- result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
-
- if (((result+size-1) & dma_mask) != result+size-1)
- panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
- physical, physical+size-1, dma_mask);
- goto done;
- }
-
- /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
- if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
- result = physical - 0x400000000ull;
- else
- result = physical;
- if (((result+size-1) & dma_mask) != result+size-1)
- panic("dma_map_single: Attempt to map address "
- "0x%llx-0x%llx, which can't be accessed "
- "according to the dma mask 0x%llx\n",
- physical, physical+size-1, dma_mask);
- goto done;
+static void octeon_dma_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+ swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
+ mb();
+}
- case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
- /* If the device supports 64bit addressing, then use BAR2 */
- if (dma_mask > BAR2_PCI_ADDRESS) {
- result = physical + BAR2_PCI_ADDRESS;
- goto done;
- }
-#endif
- if (unlikely(physical < (4ul << 10))) {
- panic("dma_map_single: Not allowed to map first 4KB. "
- "It interferes with BAR0 special area\n");
- } else if (physical < (256ul << 20)) {
- if (unlikely(physical + size > (256ul << 20)))
- panic("dma_map_single: Requested memory spans "
- "Bar0 0:256MB and bootbus\n");
- result = physical;
- goto done;
- } else if (unlikely(physical < (512ul << 20))) {
- panic("dma_map_single: Not allowed to map bootbus\n");
- } else if (physical < (2ul << 30)) {
- if (unlikely(physical + size > (2ul << 30)))
- panic("dma_map_single: Requested memory spans "
- "Bar0 512MB:2GB and BAR1\n");
- result = physical;
- goto done;
- } else if (physical < (2ul << 30) + (128 << 20)) {
- /* Fall through */
- } else if (physical <
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
- if (unlikely
- (physical + size >
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
- panic("dma_map_single: Requested memory "
- "extends past Bar1 (4GB-%luMB)\n",
- OCTEON_PCI_BAR1_HOLE_SIZE);
- result = physical;
- goto done;
- } else if ((physical >= 0x410000000ull) &&
- (physical < 0x420000000ull)) {
- if (unlikely(physical + size > 0x420000000ull))
- panic("dma_map_single: Requested memory spans "
- "non existant memory\n");
- /* BAR0 fixed mapping 256MB:512MB ->
- * 16GB+256MB:16GB+512MB */
- result = physical - 0x400000000ull;
- goto done;
- } else {
- /* Continued below switch statement */
- }
- break;
+static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp)
+{
+ void *ret;
- case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
- /* If the device supports 64bit addressing, then use BAR2 */
- if (dma_mask > BAR2_PCI_ADDRESS) {
- result = physical + BAR2_PCI_ADDRESS;
- goto done;
- }
+ if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+ return ret;
+
+ /* ignore region specifiers */
+ gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+
+#ifdef CONFIG_ZONE_DMA
+ if (dev == NULL)
+ gfp |= __GFP_DMA;
+ else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
+ gfp |= __GFP_DMA;
+ else
#endif
- /* Continued below switch statement */
- break;
+#ifdef CONFIG_ZONE_DMA32
+ if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
+ gfp |= __GFP_DMA32;
+ else
+#endif
+ ;
- default:
- panic("dma_map_single: Invalid octeon_dma_bar_type\n");
- }
+ /* Don't invoke OOM killer */
+ gfp |= __GFP_NORETRY;
- /* Don't allow mapping to span multiple Bar entries. The hardware guys
- won't guarantee that DMA across boards work */
- if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
- panic("dma_map_single: "
- "Requested memory spans more than one Bar1 entry\n");
+ ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- start_index = 31;
- else if (unlikely(dma_mask < (1ul << 27)))
- start_index = (dma_mask >> 22);
- else
- start_index = 31;
-
- /* Only one processor can access the Bar register at once */
- raw_spin_lock_irqsave(&bar1_lock, flags);
-
- /* Look through Bar1 for existing mapping that will work */
- for (index = start_index; index >= 0; index--) {
- if ((bar1_state[index].address_bits == physical >> 22) &&
- (bar1_state[index].ref_count)) {
- /* An existing mapping will work, use it */
- bar1_state[index].ref_count++;
- if (unlikely(bar1_state[index].ref_count < 0))
- panic("dma_map_single: "
- "Bar1[%d] reference count overflowed\n",
- (int) index);
- result = (index << 22) | (physical & ((1 << 22) - 1));
- /* Large BAR1 is offset at 2GB */
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- result += 2ul << 30;
- goto done_unlock;
- }
- }
+ mb();
- /* No existing mappings, look for a free entry */
- for (index = start_index; index >= 0; index--) {
- if (unlikely(bar1_state[index].ref_count == 0)) {
- union cvmx_pci_bar1_indexx bar1_index;
- /* We have a free entry, use it */
- bar1_state[index].ref_count = 1;
- bar1_state[index].address_bits = physical >> 22;
- bar1_index.u32 = 0;
- /* Address bits[35:22] sent to L2C */
- bar1_index.s.addr_idx = physical >> 22;
- /* Don't put PCI accesses in L2. */
- bar1_index.s.ca = 1;
- /* Endian Swap Mode */
- bar1_index.s.end_swp = 1;
- /* Set '1' when the selected address range is valid. */
- bar1_index.s.addr_v = 1;
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
- bar1_index.u32);
- /* An existing mapping will work, use it */
- result = (index << 22) | (physical & ((1 << 22) - 1));
- /* Large BAR1 is offset at 2GB */
- if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
- result += 2ul << 30;
- goto done_unlock;
- }
- }
+ return ret;
+}
- pr_err("dma_map_single: "
- "Can't find empty BAR1 index for physical mapping 0x%llx\n",
- (unsigned long long) physical);
+static void octeon_dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ int order = get_order(size);
-done_unlock:
- raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
- pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
- return result;
-#endif
+ if (dma_release_from_coherent(dev, order, vaddr))
+ return;
+
+ swiotlb_free_coherent(dev, size, vaddr, dma_handle);
}
-void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
-#ifndef CONFIG_PCI
- /*
- * Without PCI/PCIe this function can be called for Octeon internal
- * devices such as USB. These devices all support 64bit addressing.
- */
- return;
-#else
- unsigned long flags;
- uint64_t index;
+ return paddr;
+}
+static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ return daddr;
+}
+
+struct octeon_dma_map_ops {
+ struct dma_map_ops dma_map_ops;
+ dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+ phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+ struct octeon_dma_map_ops,
+ dma_map_ops);
+
+ return ops->phys_to_dma(dev, paddr);
+}
+EXPORT_SYMBOL(phys_to_dma);
+
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+ struct octeon_dma_map_ops,
+ dma_map_ops);
+
+ return ops->dma_to_phys(dev, daddr);
+}
+EXPORT_SYMBOL(dma_to_phys);
+
+static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
+ .dma_map_ops = {
+ .alloc_coherent = octeon_dma_alloc_coherent,
+ .free_coherent = octeon_dma_free_coherent,
+ .map_page = octeon_dma_map_page,
+ .unmap_page = swiotlb_unmap_page,
+ .map_sg = octeon_dma_map_sg,
+ .unmap_sg = swiotlb_unmap_sg_attrs,
+ .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+ .sync_single_for_device = octeon_dma_sync_single_for_device,
+ .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+ .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+ .mapping_error = swiotlb_dma_mapping_error,
+ .dma_supported = swiotlb_dma_supported
+ },
+ .phys_to_dma = octeon_unity_phys_to_dma,
+ .dma_to_phys = octeon_unity_dma_to_phys
+};
+
+char *octeon_swiotlb;
+
+void __init plat_swiotlb_setup(void)
+{
+ int i;
+ phys_t max_addr;
+ phys_t addr_size;
+ size_t swiotlbsize;
+ unsigned long swiotlb_nslabs;
+
+ max_addr = 0;
+ addr_size = 0;
+
+ for (i = 0 ; i < boot_mem_map.nr_map; i++) {
+ struct boot_mem_map_entry *e = &boot_mem_map.map[i];
+ if (e->type != BOOT_MEM_RAM)
+ continue;
+
+ /* These addresses map low for PCI. */
+ if (e->addr > 0x410000000ull)
+ continue;
+
+ addr_size += e->size;
+
+ if (max_addr < e->addr + e->size)
+ max_addr = e->addr + e->size;
+
+ }
+
+ swiotlbsize = PAGE_SIZE;
+
+#ifdef CONFIG_PCI
/*
- * Platform devices, such as the internal USB, skip all
- * translation and use Octeon physical addresses directly.
+ * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
+ * size to a maximum of 64MB
*/
- if (dev->bus == &platform_bus_type)
- return;
+ if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+ || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+ swiotlbsize = addr_size / 4;
+ if (swiotlbsize > 64 * (1<<20))
+ swiotlbsize = 64 * (1<<20);
+ } else if (max_addr > 0xf0000000ul) {
+ /*
+ * Otherwise only allocate a big iotlb if there is
+ * memory past the BAR1 hole.
+ */
+ swiotlbsize = 64 * (1<<20);
+ }
+#endif
+ swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
+ swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
+ swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
+
+ octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
+ swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1);
+
+ mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
+}
+
+#ifdef CONFIG_PCI
+static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
+ .dma_map_ops = {
+ .alloc_coherent = octeon_dma_alloc_coherent,
+ .free_coherent = octeon_dma_free_coherent,
+ .map_page = octeon_dma_map_page,
+ .unmap_page = swiotlb_unmap_page,
+ .map_sg = octeon_dma_map_sg,
+ .unmap_sg = swiotlb_unmap_sg_attrs,
+ .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+ .sync_single_for_device = octeon_dma_sync_single_for_device,
+ .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+ .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+ .mapping_error = swiotlb_dma_mapping_error,
+ .dma_supported = swiotlb_dma_supported
+ },
+};
+
+struct dma_map_ops *octeon_pci_dma_map_ops;
+
+void __init octeon_pci_dma_init(void)
+{
switch (octeon_dma_bar_type) {
case OCTEON_DMA_BAR_TYPE_PCIE:
- /* Nothing to do, all mappings are static */
- goto done;
-
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
+ break;
case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
- /* Nothing to do for addresses using BAR2 */
- if (dma_addr >= BAR2_PCI_ADDRESS)
- goto done;
-#endif
- if (unlikely(dma_addr < (4ul << 10)))
- panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
- dma_addr);
- else if (dma_addr < (2ul << 30))
- /* Nothing to do for addresses using BAR0 */
- goto done;
- else if (dma_addr < (2ul << 30) + (128ul << 20))
- /* Need to unmap, fall through */
- index = (dma_addr - (2ul << 30)) >> 22;
- else if (dma_addr <
- (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
- goto done; /* Nothing to do for the rest of BAR1 */
- else
- panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
- dma_addr);
- /* Continued below switch statement */
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
break;
-
case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
- /* Nothing to do for addresses using BAR2 */
- if (dma_addr >= BAR2_PCI_ADDRESS)
- goto done;
-#endif
- index = dma_addr >> 22;
- /* Continued below switch statement */
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
break;
-
default:
- panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+ BUG();
}
-
- if (unlikely(index > 31))
- panic("dma_unmap_single: "
- "Attempt to unmap an invalid address (0x%llx)\n",
- dma_addr);
-
- raw_spin_lock_irqsave(&bar1_lock, flags);
- bar1_state[index].ref_count--;
- if (bar1_state[index].ref_count == 0)
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
- else if (unlikely(bar1_state[index].ref_count < 0))
- panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
- (int) index);
- raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
- pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
- return;
-#endif
+ octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
}
+#endif /* CONFIG_PCI */
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
***********************license end**************************************/
/*
- * Implementation of the Level 2 Cache (L2C) control, measurement, and
- * debugging facilities.
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
*/
#include <asm/octeon/cvmx.h>
* if multiple applications or operating systems are running, then it
* is up to the user program to coordinate between them.
*/
-static cvmx_spinlock_t cvmx_l2c_spinlock;
-
-static inline int l2_size_half(void)
-{
- uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
- return !!(val & (1ull << 34));
-}
+cvmx_spinlock_t cvmx_l2c_spinlock;
int cvmx_l2c_get_core_way_partition(uint32_t core)
{
if (core >= cvmx_octeon_num_cores())
return -1;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;
+
/*
* Use the lower two bits of the coreNumber to determine the
* bit offset of the UMSK[] field in the L2C_SPAR register.
switch (core & 0xC) {
case 0x0:
- return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
case 0x4:
- return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
case 0x8:
- return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
case 0xC:
- return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
- field;
+ return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
}
return 0;
}
mask &= valid_mask;
- /* A UMSK setting which blocks all L2C Ways is an error. */
- if (mask == valid_mask)
+ /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+ if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
return -1;
/* Validate the core number */
if (core >= cvmx_octeon_num_cores())
return -1;
- /* Check to make sure current mask & new mask don't block all ways */
- if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
- valid_mask)
- return -1;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+ return 0;
+ }
- /* Use the lower two bits of core to determine the bit offset of the
+ /*
+ * Use the lower two bits of core to determine the bit offset of the
* UMSK[] field in the L2C_SPAR register.
*/
field = (core & 0x3) * 8;
- /* Assign the new mask setting to the UMSK[] field in the appropriate
+ /*
+ * Assign the new mask setting to the UMSK[] field in the appropriate
* L2C_SPAR register based on the core_num.
*
*/
switch (core & 0xC) {
case 0x0:
cvmx_write_csr(CVMX_L2C_SPAR0,
- (cvmx_read_csr(CVMX_L2C_SPAR0) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+ mask << field);
break;
case 0x4:
cvmx_write_csr(CVMX_L2C_SPAR1,
- (cvmx_read_csr(CVMX_L2C_SPAR1) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+ mask << field);
break;
case 0x8:
cvmx_write_csr(CVMX_L2C_SPAR2,
- (cvmx_read_csr(CVMX_L2C_SPAR2) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+ mask << field);
break;
case 0xC:
cvmx_write_csr(CVMX_L2C_SPAR3,
- (cvmx_read_csr(CVMX_L2C_SPAR3) &
- ~(0xFF << field)) | mask << field);
+ (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+ mask << field);
break;
}
return 0;
{
uint32_t valid_mask;
- valid_mask = 0xff;
-
- if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
- if (l2_size_half())
- valid_mask = 0xf;
- } else if (l2_size_half())
- valid_mask = 0x3;
-
+ valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
mask &= valid_mask;
- /* A UMSK setting which blocks all L2C Ways is an error. */
- if (mask == valid_mask)
- return -1;
- /* Check to make sure current mask & new mask don't block all ways */
- if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
- valid_mask)
+ /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+ if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
return -1;
- cvmx_write_csr(CVMX_L2C_SPAR4,
- (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
+ else
+ cvmx_write_csr(CVMX_L2C_SPAR4,
+ (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
return 0;
}
int cvmx_l2c_get_hw_way_partition(void)
{
- return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
+ else
+ return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
}
void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
uint32_t clear_on_read)
{
- union cvmx_l2c_pfctl pfctl;
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+ union cvmx_l2c_pfctl pfctl;
- pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+ pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
- switch (counter) {
- case 0:
- pfctl.s.cnt0sel = event;
- pfctl.s.cnt0ena = 1;
- if (!cvmx_octeon_is_pass1())
+ switch (counter) {
+ case 0:
+ pfctl.s.cnt0sel = event;
+ pfctl.s.cnt0ena = 1;
pfctl.s.cnt0rdclr = clear_on_read;
- break;
- case 1:
- pfctl.s.cnt1sel = event;
- pfctl.s.cnt1ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 1:
+ pfctl.s.cnt1sel = event;
+ pfctl.s.cnt1ena = 1;
pfctl.s.cnt1rdclr = clear_on_read;
- break;
- case 2:
- pfctl.s.cnt2sel = event;
- pfctl.s.cnt2ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 2:
+ pfctl.s.cnt2sel = event;
+ pfctl.s.cnt2ena = 1;
pfctl.s.cnt2rdclr = clear_on_read;
- break;
- case 3:
- default:
- pfctl.s.cnt3sel = event;
- pfctl.s.cnt3ena = 1;
- if (!cvmx_octeon_is_pass1())
+ break;
+ case 3:
+ default:
+ pfctl.s.cnt3sel = event;
+ pfctl.s.cnt3ena = 1;
pfctl.s.cnt3rdclr = clear_on_read;
- break;
- }
+ break;
+ }
- cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+ cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+ } else {
+ union cvmx_l2c_tadx_prf l2c_tadx_prf;
+ int tad;
+
+ cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
+ if (clear_on_read)
+ cvmx_dprintf("L2C counters don't support clear on read for this chip\n");
+
+ l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
+
+ switch (counter) {
+ case 0:
+ l2c_tadx_prf.s.cnt0sel = event;
+ break;
+ case 1:
+ l2c_tadx_prf.s.cnt1sel = event;
+ break;
+ case 2:
+ l2c_tadx_prf.s.cnt2sel = event;
+ break;
+ default:
+ case 3:
+ l2c_tadx_prf.s.cnt3sel = event;
+ break;
+ }
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
+ l2c_tadx_prf.u64);
+ }
}
uint64_t cvmx_l2c_read_perf(uint32_t counter)
{
switch (counter) {
case 0:
- return cvmx_read_csr(CVMX_L2C_PFC0);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC0);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+ return counter;
+ }
case 1:
- return cvmx_read_csr(CVMX_L2C_PFC1);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC1);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+ return counter;
+ }
case 2:
- return cvmx_read_csr(CVMX_L2C_PFC2);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC2);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+ return counter;
+ }
case 3:
default:
- return cvmx_read_csr(CVMX_L2C_PFC3);
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+ return cvmx_read_csr(CVMX_L2C_PFC3);
+ else {
+ uint64_t counter = 0;
+ int tad;
+ for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+ counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+ return counter;
+ }
}
}
volatile char dummy;
/*
* Adjust addr and length so we get all cache lines even for
- * small ranges spanning two cache lines
+ * small ranges spanning two cache lines.
*/
len += addr & CVMX_CACHE_LINE_MASK;
addr &= ~CVMX_CACHE_LINE_MASK;
int cvmx_l2c_lock_line(uint64_t addr)
{
- int retval = 0;
- union cvmx_l2c_dbg l2cdbg;
- union cvmx_l2c_lckbase lckbase;
- union cvmx_l2c_lckoff lckoff;
- union cvmx_l2t_err l2t_err;
- l2cdbg.u64 = 0;
- lckbase.u64 = 0;
- lckoff.u64 = 0;
-
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-
- /* Clear l2t error bits if set */
- l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- l2t_err.s.lckerr = 1;
- l2t_err.s.lckerr2 = 1;
- cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+ uint64_t assoc = cvmx_l2c_get_num_assoc();
+ uint64_t tag = addr >> shift;
+ uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+ uint64_t way;
+ union cvmx_l2c_tadx_tag l2c_tadx_tag;
+
+ CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+
+ /* Make sure we were able to lock the line */
+ for (way = 0; way < assoc; way++) {
+ CVMX_CACHE_LTGL2I(index | (way << shift), 0);
+ /* make sure CVMX_L2C_TADX_TAG is updated */
+ CVMX_SYNC;
+ l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+ if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
+ break;
+ }
- addr &= ~CVMX_CACHE_LINE_MASK;
+ /* Check if a valid line is found */
+ if (way >= assoc) {
+ /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr); */
+ return -1;
+ }
- /* Set this core as debug core */
- l2cdbg.s.ppnum = cvmx_get_core_num();
- CVMX_SYNC;
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
- cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
- cvmx_read_csr(CVMX_L2C_LCKOFF);
-
- if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
- int alias_shift =
- CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
- uint64_t addr_tmp =
- addr ^ (addr & ((1 << alias_shift) - 1)) >>
- CVMX_L2_SET_BITS;
- lckbase.s.lck_base = addr_tmp >> 7;
+ /* Check if lock bit is not set */
+ if (!l2c_tadx_tag.s.lock) {
+ /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr); */
+ return -1;
+ }
+ return way;
} else {
- lckbase.s.lck_base = addr >> 7;
- }
+ int retval = 0;
+ union cvmx_l2c_dbg l2cdbg;
+ union cvmx_l2c_lckbase lckbase;
+ union cvmx_l2c_lckoff lckoff;
+ union cvmx_l2t_err l2t_err;
- lckbase.s.lck_ena = 1;
- cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
- cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- fault_in(addr, CVMX_CACHE_LINE_SIZE);
+ l2cdbg.u64 = 0;
+ lckbase.u64 = 0;
+ lckoff.u64 = 0;
- lckbase.s.lck_ena = 0;
- cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
- cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
+ /* Clear l2t error bits if set */
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ l2t_err.s.lckerr = 1;
+ l2t_err.s.lckerr2 = 1;
+ cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
- /* Stop being debug core */
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ addr &= ~CVMX_CACHE_LINE_MASK;
- l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
- if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
- retval = 1; /* We were unable to lock the line */
+ /* Set this core as debug core */
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+ cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+ cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+ if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+ int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+ uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+ lckbase.s.lck_base = addr_tmp >> 7;
+ } else {
+ lckbase.s.lck_base = addr >> 7;
+ }
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ lckbase.s.lck_ena = 1;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ /* Make sure it gets there */
+ cvmx_read_csr(CVMX_L2C_LCKBASE);
- return retval;
+ fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+ lckbase.s.lck_ena = 0;
+ cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+ /* Make sure it gets there */
+ cvmx_read_csr(CVMX_L2C_LCKBASE);
+
+ /* Stop being debug core */
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+ if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+ retval = 1; /* We were unable to lock the line */
+
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ return retval;
+ }
}
int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
start += CVMX_CACHE_LINE_SIZE;
len -= CVMX_CACHE_LINE_SIZE;
}
-
return retval;
}
{
uint64_t assoc, set;
uint64_t n_assoc, n_set;
- union cvmx_l2c_dbg l2cdbg;
-
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- l2cdbg.u64 = 0;
- if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.finv = 1;
- n_set = CVMX_L2_SETS;
- n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
- for (set = 0; set < n_set; set++) {
- for (assoc = 0; assoc < n_assoc; assoc++) {
- l2cdbg.s.set = assoc;
- /* Enter debug mode, and make sure all other
- ** writes complete before we enter debug
- ** mode */
- CVMX_SYNCW;
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
- (CVMX_MIPS_SPACE_XKPHYS,
- set * CVMX_CACHE_LINE_SIZE), 0);
- CVMX_SYNCW; /* Push STF out to L2 */
- /* Exit debug mode */
- CVMX_SYNC;
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ n_set = cvmx_l2c_get_num_sets();
+ n_assoc = cvmx_l2c_get_num_assoc();
+
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ uint64_t address;
+ /* These may look like constants, but they aren't... */
+ int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+ int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
+ for (set = 0; set < n_set; set++) {
+ for (assoc = 0; assoc < n_assoc; assoc++) {
+ address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (assoc << assoc_shift) | (set << set_shift));
+ CVMX_CACHE_WBIL2I(address, 0);
+ }
}
+ } else {
+ for (set = 0; set < n_set; set++)
+ for (assoc = 0; assoc < n_assoc; assoc++)
+ cvmx_l2c_flush_line(assoc, set);
}
-
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
}
+
int cvmx_l2c_unlock_line(uint64_t address)
{
- int assoc;
- union cvmx_l2c_tag tag;
- union cvmx_l2c_dbg l2cdbg;
- uint32_t tag_addr;
- uint32_t index = cvmx_l2c_address_to_index(address);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ int assoc;
+ union cvmx_l2c_tag tag;
+ uint32_t tag_addr;
+ uint32_t index = cvmx_l2c_address_to_index(address);
+
+ tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+
+ /*
+ * For 63XX, we can flush a line by using the physical
+ * address directly, so finding the cache line used by
+ * the address is only required to provide the proper
+ * return value for the function.
+ */
+ for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+ tag = cvmx_l2c_get_tag(assoc, index);
+
+ if (tag.s.V && (tag.s.addr == tag_addr)) {
+ CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+ return tag.s.L;
+ }
+ }
+ } else {
+ int assoc;
+ union cvmx_l2c_tag tag;
+ uint32_t tag_addr;
- cvmx_spinlock_lock(&cvmx_l2c_spinlock);
- /* Compute portion of address that is stored in tag */
- tag_addr =
- ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
- ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
- for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
- tag = cvmx_get_l2c_tag(assoc, index);
+ uint32_t index = cvmx_l2c_address_to_index(address);
- if (tag.s.V && (tag.s.addr == tag_addr)) {
- l2cdbg.u64 = 0;
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.set = assoc;
- l2cdbg.s.finv = 1;
+ /* Compute portion of address that is stored in tag */
+ tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+ for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+ tag = cvmx_l2c_get_tag(assoc, index);
- CVMX_SYNC;
- /* Enter debug mode */
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
- (CVMX_MIPS_SPACE_XKPHYS,
- address), 0);
- CVMX_SYNC;
- /* Exit debug mode */
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
- return tag.s.L;
+ if (tag.s.V && (tag.s.addr == tag_addr)) {
+ cvmx_l2c_flush_line(assoc, index);
+ return tag.s.L;
+ }
}
}
- cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
return 0;
}
uint64_t u64;
struct cvmx_l2c_tag_cn50xx {
uint64_t reserved:40;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:20; /* Phys mem addr (33..14) */
} cn50xx;
struct cvmx_l2c_tag_cn30xx {
uint64_t reserved:41;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:19; /* Phys mem addr (33..15) */
} cn30xx;
struct cvmx_l2c_tag_cn31xx {
uint64_t reserved:42;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:18; /* Phys mem addr (33..16) */
} cn31xx;
struct cvmx_l2c_tag_cn38xx {
uint64_t reserved:43;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:17; /* Phys mem addr (33..17) */
} cn38xx;
struct cvmx_l2c_tag_cn58xx {
uint64_t reserved:44;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:16; /* Phys mem addr (33..18) */
} cn58xx;
struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
};
+
/**
* @INTERNAL
* Function to read a L2C tag. This code make the current core
static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
{
- uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+ uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
uint64_t core = cvmx_get_core_num();
union __cvmx_l2c_tag tag_val;
uint64_t dbg_addr = CVMX_L2C_DBG;
union cvmx_l2c_dbg debug_val;
debug_val.u64 = 0;
/*
- * For low core count parts, the core number is always small enough
- * to stay in the correct field and not set any reserved bits.
+ * For low core count parts, the core number is always small
+ * enough to stay in the correct field and not set any
+ * reserved bits.
*/
debug_val.s.ppnum = core;
debug_val.s.l2t = 1;
debug_val.s.set = assoc;
+
+ local_irq_save(flags);
/*
* Make sure core is quiet (no prefetches, etc.) before
* entering debug mode.
/* Flush L1 to make sure debug load misses L1 */
CVMX_DCACHE_INVALIDATE;
- local_irq_save(flags);
-
/*
* The following must be done in assembly as when in debug
* mode all data loads from L2 return special debug data, not
- * normal memory contents. Also, interrupts must be
- * disabled, since if an interrupt occurs while in debug mode
- * the ISR will get debug data from all its memory reads
- * instead of the contents of memory
+ * normal memory contents. Also, interrupts must be disabled,
+ * since if an interrupt occurs while in debug mode the ISR
+ * will get debug data from all its memory * reads instead of
+ * the contents of memory.
*/
- asm volatile (".set push \n"
- " .set mips64 \n"
- " .set noreorder \n"
- /* Enter debug mode, wait for store */
- " sd %[dbg_val], 0(%[dbg_addr]) \n"
- " ld $0, 0(%[dbg_addr]) \n"
- /* Read L2C tag data */
- " ld %[tag_val], 0(%[tag_addr]) \n"
- /* Exit debug mode, wait for store */
- " sd $0, 0(%[dbg_addr]) \n"
- " ld $0, 0(%[dbg_addr]) \n"
- /* Invalidate dcache to discard debug data */
- " cache 9, 0($0) \n"
- " .set pop" :
- [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
- [dbg_val] "r"(debug_val.u64),
- [tag_addr] "r"(debug_tag_addr) : "memory");
+ asm volatile (
+ ".set push\n\t"
+ ".set mips64\n\t"
+ ".set noreorder\n\t"
+ "sd %[dbg_val], 0(%[dbg_addr])\n\t" /* Enter debug mode, wait for store */
+ "ld $0, 0(%[dbg_addr])\n\t"
+ "ld %[tag_val], 0(%[tag_addr])\n\t" /* Read L2C tag data */
+ "sd $0, 0(%[dbg_addr])\n\t" /* Exit debug mode, wait for store */
+ "ld $0, 0(%[dbg_addr])\n\t"
+ "cache 9, 0($0)\n\t" /* Invalidate dcache to discard debug data */
+ ".set pop"
+ : [tag_val] "=r" (tag_val)
+ : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
+ : "memory");
local_irq_restore(flags);
- return tag_val;
+ return tag_val;
}
+
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
{
- union __cvmx_l2c_tag tmp_tag;
union cvmx_l2c_tag tag;
tag.u64 = 0;
if ((int)association >= cvmx_l2c_get_num_assoc()) {
- cvmx_dprintf
- ("ERROR: cvmx_get_l2c_tag association out of range\n");
+ cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
return tag;
}
if ((int)index >= cvmx_l2c_get_num_sets()) {
- cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
- "index out of range (arg: %d, max: %d\n",
- index, cvmx_l2c_get_num_sets());
+ cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+ (int)index, cvmx_l2c_get_num_sets());
return tag;
}
- /* __read_l2_tag is intended for internal use only */
- tmp_tag = __read_l2_tag(association, index);
-
- /*
- * Convert all tag structure types to generic version, as it
- * can represent all models.
- */
- if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
- tag.s.V = tmp_tag.cn58xx.V;
- tag.s.D = tmp_tag.cn58xx.D;
- tag.s.L = tmp_tag.cn58xx.L;
- tag.s.U = tmp_tag.cn58xx.U;
- tag.s.addr = tmp_tag.cn58xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
- tag.s.V = tmp_tag.cn38xx.V;
- tag.s.D = tmp_tag.cn38xx.D;
- tag.s.L = tmp_tag.cn38xx.L;
- tag.s.U = tmp_tag.cn38xx.U;
- tag.s.addr = tmp_tag.cn38xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
- tag.s.V = tmp_tag.cn31xx.V;
- tag.s.D = tmp_tag.cn31xx.D;
- tag.s.L = tmp_tag.cn31xx.L;
- tag.s.U = tmp_tag.cn31xx.U;
- tag.s.addr = tmp_tag.cn31xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
- tag.s.V = tmp_tag.cn30xx.V;
- tag.s.D = tmp_tag.cn30xx.D;
- tag.s.L = tmp_tag.cn30xx.L;
- tag.s.U = tmp_tag.cn30xx.U;
- tag.s.addr = tmp_tag.cn30xx.addr;
- } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
- tag.s.V = tmp_tag.cn50xx.V;
- tag.s.D = tmp_tag.cn50xx.D;
- tag.s.L = tmp_tag.cn50xx.L;
- tag.s.U = tmp_tag.cn50xx.U;
- tag.s.addr = tmp_tag.cn50xx.addr;
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ union cvmx_l2c_tadx_tag l2c_tadx_tag;
+ uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+ (index << CVMX_L2C_IDX_ADDR_SHIFT));
+ /*
+ * Use L2 cache Index load tag cache instruction, as
+ * hardware loads the virtual tag for the L2 cache
+ * block with the contents of L2C_TAD0_TAG
+ * register.
+ */
+ CVMX_CACHE_LTGL2I(address, 0);
+ CVMX_SYNC; /* make sure CVMX_L2C_TADX_TAG is updated */
+ l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+ tag.s.V = l2c_tadx_tag.s.valid;
+ tag.s.D = l2c_tadx_tag.s.dirty;
+ tag.s.L = l2c_tadx_tag.s.lock;
+ tag.s.U = l2c_tadx_tag.s.use;
+ tag.s.addr = l2c_tadx_tag.s.tag;
} else {
- cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+ union __cvmx_l2c_tag tmp_tag;
+ /* __read_l2_tag is intended for internal use only */
+ tmp_tag = __read_l2_tag(association, index);
+
+ /*
+ * Convert all tag structure types to generic version,
+ * as it can represent all models.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+ tag.s.V = tmp_tag.cn58xx.V;
+ tag.s.D = tmp_tag.cn58xx.D;
+ tag.s.L = tmp_tag.cn58xx.L;
+ tag.s.U = tmp_tag.cn58xx.U;
+ tag.s.addr = tmp_tag.cn58xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+ tag.s.V = tmp_tag.cn38xx.V;
+ tag.s.D = tmp_tag.cn38xx.D;
+ tag.s.L = tmp_tag.cn38xx.L;
+ tag.s.U = tmp_tag.cn38xx.U;
+ tag.s.addr = tmp_tag.cn38xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+ tag.s.V = tmp_tag.cn31xx.V;
+ tag.s.D = tmp_tag.cn31xx.D;
+ tag.s.L = tmp_tag.cn31xx.L;
+ tag.s.U = tmp_tag.cn31xx.U;
+ tag.s.addr = tmp_tag.cn31xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+ tag.s.V = tmp_tag.cn30xx.V;
+ tag.s.D = tmp_tag.cn30xx.D;
+ tag.s.L = tmp_tag.cn30xx.L;
+ tag.s.U = tmp_tag.cn30xx.U;
+ tag.s.addr = tmp_tag.cn30xx.addr;
+ } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+ tag.s.V = tmp_tag.cn50xx.V;
+ tag.s.D = tmp_tag.cn50xx.D;
+ tag.s.L = tmp_tag.cn50xx.L;
+ tag.s.U = tmp_tag.cn50xx.U;
+ tag.s.addr = tmp_tag.cn50xx.addr;
+ } else {
+ cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+ }
}
-
return tag;
}
uint32_t cvmx_l2c_address_to_index(uint64_t addr)
{
uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
- union cvmx_l2c_cfg l2c_cfg;
- l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+ int indxalias = 0;
- if (l2c_cfg.s.idxalias) {
- idx ^=
- ((addr & CVMX_L2C_ALIAS_MASK) >>
- CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ union cvmx_l2c_ctl l2c_ctl;
+ l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+ indxalias = !l2c_ctl.s.disidxalias;
+ } else {
+ union cvmx_l2c_cfg l2c_cfg;
+ l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+ indxalias = l2c_cfg.s.idxalias;
+ }
+
+ if (indxalias) {
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
+ idx ^= idx / cvmx_l2c_get_num_sets();
+ idx ^= a_14_12;
+ } else {
+ idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+ }
}
idx &= CVMX_L2C_IDX_MASK;
return idx;
int l2_set_bits;
if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
l2_set_bits = 11; /* 2048 sets */
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
l2_set_bits = 10; /* 1024 sets */
- else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX))
+ else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
l2_set_bits = 9; /* 512 sets */
else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
l2_set_bits = 8; /* 256 sets */
l2_set_bits = 11; /* 2048 sets */
}
return l2_set_bits;
-
}
/* Return the number of sets in the L2 Cache */
if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
OCTEON_IS_MODEL(OCTEON_CN52XX) ||
OCTEON_IS_MODEL(OCTEON_CN58XX) ||
- OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
+ OCTEON_IS_MODEL(OCTEON_CN50XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN38XX))
l2_assoc = 8;
+ else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ l2_assoc = 16;
else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
OCTEON_IS_MODEL(OCTEON_CN30XX))
l2_assoc = 4;
}
/* Check to see if part of the cache is disabled */
- if (cvmx_fuse_read(265))
- l2_assoc = l2_assoc >> 2;
- else if (cvmx_fuse_read(264))
- l2_assoc = l2_assoc >> 1;
-
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ union cvmx_mio_fus_dat3 mio_fus_dat3;
+
+ mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+ /*
+ * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+ * <2> will be not used for 63xx
+ * <1> disables 1/2 ways
+ * <0> disables 1/4 ways
+ * They are cumulative, so for 63xx:
+ * <1> <0>
+ * 0 0 16-way 2MB cache
+ * 0 1 12-way 1.5MB cache
+ * 1 0 8-way 1MB cache
+ * 1 1 4-way 512KB cache
+ */
+
+ if (mio_fus_dat3.s.l2c_crip == 3)
+ l2_assoc = 4;
+ else if (mio_fus_dat3.s.l2c_crip == 2)
+ l2_assoc = 8;
+ else if (mio_fus_dat3.s.l2c_crip == 1)
+ l2_assoc = 12;
+ } else {
+ union cvmx_l2d_fus3 val;
+ val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+ /*
+ * Using shifts here, as bit position names are
+ * different for each model but they all mean the
+ * same.
+ */
+ if ((val.u64 >> 35) & 0x1)
+ l2_assoc = l2_assoc >> 2;
+ else if ((val.u64 >> 34) & 0x1)
+ l2_assoc = l2_assoc >> 1;
+ }
return l2_assoc;
}
*/
void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
{
- union cvmx_l2c_dbg l2cdbg;
+ /* Check the range of the index. */
+ if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
+ cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
+ return;
+ }
- l2cdbg.u64 = 0;
- l2cdbg.s.ppnum = cvmx_get_core_num();
- l2cdbg.s.finv = 1;
+ /* Check the range of association. */
+ if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
+ cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
+ return;
+ }
- l2cdbg.s.set = assoc;
- /*
- * Enter debug mode, and make sure all other writes complete
- * before we enter debug mode.
- */
- asm volatile ("sync" : : : "memory");
- cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
- cvmx_read_csr(CVMX_L2C_DBG);
-
- CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
- /* Exit debug mode */
- asm volatile ("sync" : : : "memory");
- cvmx_write_csr(CVMX_L2C_DBG, 0);
- cvmx_read_csr(CVMX_L2C_DBG);
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+ uint64_t address;
+ /* Create the address based on index and association.
+ * Bits<20:17> select the way of the cache block involved in
+ * the operation
+ * Bits<16:7> of the effect address select the index
+ */
+ address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+ (index << CVMX_L2C_IDX_ADDR_SHIFT));
+ CVMX_CACHE_WBIL2I(address, 0);
+ } else {
+ union cvmx_l2c_dbg l2cdbg;
+
+ l2cdbg.u64 = 0;
+ if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+ l2cdbg.s.ppnum = cvmx_get_core_num();
+ l2cdbg.s.finv = 1;
+
+ l2cdbg.s.set = assoc;
+ cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+ /*
+ * Enter debug mode, and make sure all other writes
+ * complete before we enter debug mode
+ */
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+ cvmx_read_csr(CVMX_L2C_DBG);
+
+ CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+ index * CVMX_CACHE_LINE_SIZE),
+ 0);
+ /* Exit debug mode */
+ CVMX_SYNC;
+ cvmx_write_csr(CVMX_L2C_DBG, 0);
+ cvmx_read_csr(CVMX_L2C_DBG);
+ cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+ }
}
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2004-2010 Cavium Networks
* Copyright (C) 2008 Wind River Systems
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/i2c.h>
+#include <linux/usb.h>
+#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
num_ports = 1;
for (port = 0; port < num_ports; port++) {
- octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
+ octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
/*FIXME: should be examined. At the moment is set for 100Khz */
octeon_i2c_data[port].i2c_freq = 100000;
ret = -ENOMEM;
goto out;
}
+ /* No DMA restrictions */
+ pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+ pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
+
switch (port) {
case 0:
mgmt_port_resource.start = OCTEON_IRQ_MII0;
}
device_initcall(octeon_mgmt_device_init);
+#ifdef CONFIG_USB
+
+static int __init octeon_ehci_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource usb_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ /* Only Octeon2 has ehci/ohci */
+ if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 0;
+
+ if (octeon_is_simulation() || usb_disabled())
+ return 0; /* No USB in the simulator. */
+
+ pd = platform_device_alloc("octeon-ehci", 0);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ usb_resources[0].start = 0x00016F0000000000ULL;
+ usb_resources[0].end = usb_resources[0].start + 0x100;
+
+ usb_resources[1].start = OCTEON_IRQ_USB0;
+ usb_resources[1].end = OCTEON_IRQ_USB0;
+
+ ret = platform_device_add_resources(pd, usb_resources,
+ ARRAY_SIZE(usb_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+out:
+ return ret;
+}
+device_initcall(octeon_ehci_device_init);
+
+static int __init octeon_ohci_device_init(void)
+{
+ struct platform_device *pd;
+ int ret = 0;
+
+ struct resource usb_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ /* Only Octeon2 has ehci/ohci */
+ if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+ return 0;
+
+ if (octeon_is_simulation() || usb_disabled())
+ return 0; /* No USB in the simulator. */
+
+ pd = platform_device_alloc("octeon-ohci", 0);
+ if (!pd) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ usb_resources[0].start = 0x00016F0000000400ULL;
+ usb_resources[0].end = usb_resources[0].start + 0x100;
+
+ usb_resources[1].start = OCTEON_IRQ_USB0;
+ usb_resources[1].end = OCTEON_IRQ_USB0;
+
+ ret = platform_device_add_resources(pd, usb_resources,
+ ARRAY_SIZE(usb_resources));
+ if (ret)
+ goto fail;
+
+ ret = platform_device_add(pd);
+ if (ret)
+ goto fail;
+
+ return ret;
+fail:
+ platform_device_put(pd);
+out:
+ return ret;
+}
+device_initcall(octeon_ohci_device_init);
+
+#endif /* CONFIG_USB */
+
MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Platform driver for Octeon SOC");
/* Make simulator output fast*/
p->uartclk = 115200 * 16;
else
- p->uartclk = mips_hpt_frequency;
+ p->uartclk = octeon_get_io_clock_rate();
p->serial_in = octeon_serial_in;
p->serial_out = octeon_serial_out;
}
#include <asm/octeon/octeon.h>
#include <asm/octeon/pci-octeon.h>
+#include <asm/octeon/cvmx-mio-defs.h>
#ifdef CONFIG_CAVIUM_DECODE_RSL
extern void cvmx_interrupt_rsl_decode(void);
*/
uint64_t octeon_get_clock_rate(void)
{
- if (octeon_is_simulation())
- octeon_bootinfo->eclock_hz = 6000000;
- return octeon_bootinfo->eclock_hz;
+ struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
+
+ return sysinfo->cpu_clock_hz;
}
EXPORT_SYMBOL(octeon_get_clock_rate);
+static u64 octeon_io_clock_rate;
+
+u64 octeon_get_io_clock_rate(void)
+{
+ return octeon_io_clock_rate;
+}
+EXPORT_SYMBOL(octeon_get_io_clock_rate);
+
+
/**
* Write to the LCD display connected to the bootbus. This display
* exists on most Cavium evaluation boards. If it doesn't exist, then
cvmmemctl.s.wbfltime = 0;
/* R/W If set, do not put Istream in the L2 cache. */
cvmmemctl.s.istrnol2 = 0;
- /* R/W The write buffer threshold. */
- cvmmemctl.s.wbthresh = 10;
+
+ /*
+ * R/W The write buffer threshold. As per erratum Core-14752
+ * for CN63XX, a sc/scd might fail if the write buffer is
+ * full. Lowering WBTHRESH greatly lowers the chances of the
+ * write buffer ever being full and triggering the erratum.
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+ cvmmemctl.s.wbthresh = 4;
+ else
+ cvmmemctl.s.wbthresh = 10;
+
/* R/W If set, CVMSEG is available for loads/stores in
* kernel/debug mode. */
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
* is max legal value. */
cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
+ write_c0_cvmmemctl(cvmmemctl.u64);
if (smp_processor_id() == 0)
pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
- write_c0_cvmmemctl(cvmmemctl.u64);
-
/* Move the performance counter interrupts to IRQ 6 */
cvmctl = read_c0_cvmctl();
cvmctl &= ~(7 << 7);
cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
+ sysinfo = cvmx_sysinfo_get();
+ memset(sysinfo, 0, sizeof(*sysinfo));
+ sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
+ sysinfo->phy_mem_desc_ptr =
+ cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
+ sysinfo->core_mask = octeon_bootinfo->core_mask;
+ sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
+ sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
+ sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
+ sysinfo->board_type = octeon_bootinfo->board_type;
+ sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
+ sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
+ memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
+ sizeof(sysinfo->mac_addr_base));
+ sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
+ memcpy(sysinfo->board_serial_number,
+ octeon_bootinfo->board_serial_number,
+ sizeof(sysinfo->board_serial_number));
+ sysinfo->compact_flash_common_base_addr =
+ octeon_bootinfo->compact_flash_common_base_addr;
+ sysinfo->compact_flash_attribute_base_addr =
+ octeon_bootinfo->compact_flash_attribute_base_addr;
+ sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
+ sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
+ sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ /* I/O clock runs at a different rate than the CPU. */
+ union cvmx_mio_rst_boot rst_boot;
+ rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+ octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
+ } else {
+ octeon_io_clock_rate = sysinfo->cpu_clock_hz;
+ }
+
/*
* Only enable the LED controller if we're running on a CN38XX, CN58XX,
* or CN56XX. The CN30XX and CN31XX don't have an LED controller.
}
#endif
- sysinfo = cvmx_sysinfo_get();
- memset(sysinfo, 0, sizeof(*sysinfo));
- sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
- sysinfo->phy_mem_desc_ptr =
- cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
- sysinfo->core_mask = octeon_bootinfo->core_mask;
- sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
- sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
- sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
- sysinfo->board_type = octeon_bootinfo->board_type;
- sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
- sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
- memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
- sizeof(sysinfo->mac_addr_base));
- sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
- memcpy(sysinfo->board_serial_number,
- octeon_bootinfo->board_serial_number,
- sizeof(sysinfo->board_serial_number));
- sysinfo->compact_flash_common_base_addr =
- octeon_bootinfo->compact_flash_common_base_addr;
- sysinfo->compact_flash_attribute_base_addr =
- octeon_bootinfo->compact_flash_attribute_base_addr;
- sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
- sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
- sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
-
-
octeon_check_cpu_bist();
octeon_uart = octeon_get_boot_uart();
void prom_free_prom_memory(void)
{
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+ /* Check for presence of Core-14449 fix. */
+ u32 insn;
+ u32 *foo;
+
+ foo = &insn;
+
+ asm volatile("# before" : : : "memory");
+ prefetch(foo);
+ asm volatile(
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ "bal 1f\n\t"
+ "nop\n"
+ "1:\tlw %0,-12($31)\n\t"
+ ".set pop\n\t"
+ : "=r" (insn) : : "$31", "memory");
+
+ if ((insn >> 26) != 0x33)
+ panic("No PREF instruction at Core-14449 probe point.\n");
+
+ if (((insn >> 16) & 0x1f) != 28)
+ panic("Core-14449 WAR not in place (%04x).\n"
+ "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+ }
#ifdef CONFIG_CAVIUM_DECODE_RSL
cvmx_interrupt_rsl_enable();
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_add \n"
- " addu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %1 # atomic_add \n"
+ " addu %0, %2 \n"
+ " sc %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %1 # atomic_sub \n"
- " subu %0, %2 \n"
- " sc %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %1 # atomic_sub \n"
+ " subu %0, %2 \n"
+ " sc %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_add_return \n"
- " addu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " addu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %1, %2 # atomic_add_return \n"
+ " addu %0, %1, %3 \n"
+ " sc %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp + i;
} else {
unsigned long flags;
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
+
+ result = temp - i;
} else if (kernel_uses_llsc) {
int temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %1, %2 # atomic_sub_return \n"
- " subu %0, %1, %3 \n"
- " sc %0, %2 \n"
- " beqz %0, 2f \n"
- " subu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %1, %2 # atomic_sub_return \n"
+ " subu %0, %1, %3 \n"
+ " sc %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp - i;
} else {
unsigned long flags;
" bltz %0, 1f \n"
" sc %0, %2 \n"
" .set noreorder \n"
- " beqz %0, 2f \n"
+ " beqz %0, 1b \n"
" subu %0, %1, %3 \n"
" .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_add \n"
- " daddu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %1 # atomic64_add \n"
+ " daddu %0, %2 \n"
+ " scd %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %1 # atomic64_sub \n"
- " dsubu %0, %2 \n"
- " scd %0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %1 # atomic64_sub \n"
+ " dsubu %0, %2 \n"
+ " scd %0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter));
+ } while (unlikely(!temp));
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_add_return \n"
- " daddu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " daddu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %1, %2 # atomic64_add_return \n"
+ " daddu %0, %1, %3 \n"
+ " scd %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp + i;
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %1, %2 # atomic64_sub_return \n"
- " dsubu %0, %1, %3 \n"
- " scd %0, %2 \n"
- " beqz %0, 2f \n"
- " dsubu %0, %1, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (result), "=&r" (temp), "=m" (v->counter)
- : "Ir" (i), "m" (v->counter)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %1, %2 # atomic64_sub_return \n"
+ " dsubu %0, %1, %3 \n"
+ " scd %0, %2 \n"
+ " .set mips0 \n"
+ : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+ : "Ir" (i), "m" (v->counter)
+ : "memory");
+ } while (unlikely(!result));
+
+ result = temp - i;
} else {
unsigned long flags;
" bltz %0, 1f \n"
" scd %0, %2 \n"
" .set noreorder \n"
- " beqz %0, 2f \n"
+ " beqz %0, 1b \n"
" dsubu %0, %1, %3 \n"
" .set reorder \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
"1: \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "ir" (1UL << bit), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # set_bit \n"
- " " __INS "%0, %4, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m), "r" (~0));
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # set_bit \n"
+ " " __INS "%0, %3, %2, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (bit), "r" (~0));
+ } while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (kernel_uses_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # set_bit \n"
- " or %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # set_bit \n"
+ " or %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (~(1UL << bit)));
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # clear_bit \n"
- " " __INS "%0, $0, %2, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # clear_bit \n"
+ " " __INS "%0, $0, %2, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (bit));
+ } while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (kernel_uses_llsc) {
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # clear_bit \n"
- " and %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << bit)), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # clear_bit \n"
+ " and %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (~(1UL << bit)));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: " __LL "%0, %1 # change_bit \n"
- " xor %0, %2 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << bit), "m" (*m));
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # change_bit \n"
+ " xor %0, %2 \n"
+ " " __SC "%0, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m)
+ : "ir" (1UL << bit));
+ } while (unlikely(!temp));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_set_bit \n"
+ " or %2, %0, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_set_bit \n"
- " or %2, %0, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_set_bit \n"
+ " or %2, %0, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
#ifdef CONFIG_CPU_MIPSR2
} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " " __EXT "%2, %0, %3, 1 \n"
- " " __INS "%0, $0, %3, 1 \n"
- " " __SC "%0, %1 \n"
- " beqz %0, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "ir" (bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " " __LL "%0, %1 # test_and_clear_bit \n"
+ " " __EXT "%2, %0, %3, 1 \n"
+ " " __INS "%0, $0, %3, 1 \n"
+ " " __SC "%0, %1 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "ir" (bit)
+ : "memory");
+ } while (unlikely(!temp));
#endif
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_clear_bit \n"
- " or %2, %0, %3 \n"
- " xor %2, %3 \n"
- " " __SC "%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_clear_bit \n"
+ " or %2, %0, %3 \n"
+ " xor %2, %3 \n"
+ " " __SC "%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
- __asm__ __volatile__(
- " .set push \n"
- " .set noreorder \n"
- " .set mips3 \n"
- "1: " __LL "%0, %1 # test_and_change_bit \n"
- " xor %2, %0, %3 \n"
- " " __SC "\t%2, %1 \n"
- " beqz %2, 2f \n"
- " and %2, %0, %3 \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " nop \n"
- " .previous \n"
- " .set pop \n"
- : "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << bit), "m" (*m)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " " __LL "%0, %1 # test_and_change_bit \n"
+ " xor %2, %0, %3 \n"
+ " " __SC "\t%2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (temp), "+m" (*m), "=&r" (res)
+ : "r" (1UL << bit)
+ : "memory");
+ } while (unlikely(!res));
+
+ res = temp & (1UL << bit);
} else {
volatile unsigned long *a = addr;
unsigned long mask;
*/
extern void plat_mem_setup(void);
+#ifdef CONFIG_SWIOTLB
+/*
+ * Optional platform hook to call swiotlb_setup().
+ */
+extern void plat_swiotlb_setup(void);
+
+#else
+
+static inline void plat_swiotlb_setup(void) {}
+
+#endif /* CONFIG_SWIOTLB */
+
#endif /* _ASM_BOOTINFO_H */
" move $1, %z4 \n" \
" .set mips3 \n" \
" " st " $1, %1 \n" \
- " beqz $1, 3f \n" \
- "2: \n" \
- " .subsection 2 \n" \
- "3: b 1b \n" \
- " .previous \n" \
+ " beqz $1, 1b \n" \
" .set pop \n" \
+ "2: \n" \
: "=&r" (__ret), "=R" (*m) \
: "R" (*m), "Jr" (old), "Jr" (new) \
: "memory"); \
* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
*/
-#define PRID_IMP_BCM4710 0x4000
-#define PRID_IMP_BCM3302 0x9000
-#define PRID_IMP_BCM6338 0x9000
-#define PRID_IMP_BCM6345 0x8000
-#define PRID_IMP_BCM6348 0x9100
-#define PRID_IMP_BCM4350 0xA000
-#define PRID_REV_BCM6358 0x0010
-#define PRID_REV_BCM6368 0x0030
+#define PRID_IMP_BMIPS4KC 0x4000
+#define PRID_IMP_BMIPS32 0x8000
+#define PRID_IMP_BMIPS3300 0x9000
+#define PRID_IMP_BMIPS3300_ALT 0x9100
+#define PRID_IMP_BMIPS3300_BUG 0x0000
+#define PRID_IMP_BMIPS43XX 0xa000
+#define PRID_IMP_BMIPS5000 0x5a00
+
+#define PRID_REV_BMIPS4380_LO 0x0040
+#define PRID_REV_BMIPS4380_HI 0x006f
/*
* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
/*
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
- CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
- CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
- CPU_JZRISC,
+ CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+ CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
/*
* MIPS64 class processors
*/
CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
CPU_LAST
};
*
* This file is released under the GPLv2
*/
-#include <asm-generic/device.h>
+#ifndef _ASM_MIPS_DEVICE_H
+#define _ASM_MIPS_DEVICE_H
+
+struct dma_map_ops;
+
+struct dev_archdata {
+ /* DMA operations on that device */
+ struct dma_map_ops *dma_ops;
+};
+
+struct pdev_archdata {
+};
+
+#endif /* _ASM_MIPS_DEVICE_H*/
#include <asm/cache.h>
#include <asm-generic/dma-coherent.h>
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
+#include <dma-coherence.h>
-void dma_free_noncoherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
+extern struct dma_map_ops *mips_dma_map_ops;
-void *dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag);
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+ if (dev && dev->archdata.dma_ops)
+ return dev->archdata.dma_ops;
+ else
+ return mips_dma_map_ops;
+}
-void dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle);
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+ if (!dev->dma_mask)
+ return 0;
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
- size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction direction);
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size, enum dma_data_direction direction)
+ return addr + size <= *dev->dma_mask;
+}
+
+static inline void dma_mark_clean(void *addr, size_t size) {}
+
+#include <asm-generic/dma-mapping-common.h>
+
+static inline int dma_supported(struct device *dev, u64 mask)
{
- dma_unmap_single(dev, dma_address, size, direction);
+ struct dma_map_ops *ops = get_dma_ops(dev);
+ return ops->dma_supported(dev, mask);
}
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
- dma_addr_t dma_handle, unsigned long offset, size_t size,
- enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
+static inline int dma_mapping_error(struct device *dev, u64 mask)
+{
+ struct dma_map_ops *ops = get_dma_ops(dev);
+ return ops->mapping_error(dev, mask);
+}
static inline int
dma_set_mask(struct device *dev, u64 mask)
extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction);
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp)
+{
+ void *ret;
+ struct dma_map_ops *ops = get_dma_ops(dev);
+
+ ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
+
+ debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
+
+ return ret;
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ struct dma_map_ops *ops = get_dma_ops(dev);
+
+ ops->free_coherent(dev, size, vaddr, dma_handle);
+
+ debug_dma_free_coherent(dev, size, vaddr, dma_handle);
+}
+
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle);
+
#endif /* _ASM_DMA_MAPPING_H */
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+
+#ifndef MAX_DMA32_PFN
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
+#endif
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define local_cmpxchg(l, o, n) \
((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+#define local_xchg(l, n) (atomic_long_xchg((&(l)->a), (n)))
/**
* local_add_unless - add unless the number is a given value
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
+/* Titan registers */
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)
+#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
+#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
+#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
+#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
+
#define AR7_RESET_PERIPHERAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
+#define TITAN_RESET_BIT_EPHY1 28
+
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0 0x0
+#define TITAN_GPIO_INPUT_1 0x4
+#define TITAN_GPIO_OUTPUT_0 0x8
+#define TITAN_GPIO_OUTPUT_1 0xc
+#define TITAN_GPIO_DIR_0 0x10
+#define TITAN_GPIO_DIR_1 0x14
+#define TITAN_GPIO_ENBL_0 0x18
+#define TITAN_GPIO_ENBL_1 0x1c
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
+#define AR7_CHIP_TITAN 0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
/* Interrupts */
#define AR7_IRQ_UART0 15
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+static inline int ar7_is_titan(void)
+{
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+ AR7_CHIP_TITAN;
+}
+
static inline u16 ar7_chip_id(void)
{
- return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+ return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+ KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
+}
+
+static inline u16 titan_chip_id(void)
+{
+ unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
+ TITAN_GPIO_INPUT_1));
+ return ((val >> 12) & 0x0f);
}
static inline u8 ar7_chip_rev(void)
{
- return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+ 0x14))) >> 16) & 0xff;
}
struct clk {
msleep(20);
}
+int __init ar7_gpio_init(void);
+
+int __init ar7_gpio_init(void);
+
#endif /* __AR7_H__ */
#include <asm/mach-ar7/ar7.h>
#define AR7_GPIO_MAX 32
-#define NR_BUILTIN_GPIO AR7_GPIO_MAX
+#define TITAN_GPIO_MAX 51
+#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
#define gpio_to_irq(gpio) -1
--- /dev/null
+#ifndef __BCM963XX_TAG_H
+#define __BCM963XX_TAG_H
+
+#define TAGVER_LEN 4 /* Length of Tag Version */
+#define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */
+#define SIG1_LEN 20 /* Company Signature 1 Length */
+#define SIG2_LEN 14 /* Company Signature 2 Lenght */
+#define BOARDID_LEN 16 /* Length of BoardId */
+#define ENDIANFLAG_LEN 2 /* Endian Flag Length */
+#define CHIPID_LEN 6 /* Chip Id Length */
+#define IMAGE_LEN 10 /* Length of Length Field */
+#define ADDRESS_LEN 12 /* Length of Address field */
+#define DUALFLAG_LEN 2 /* Dual Image flag Length */
+#define INACTIVEFLAG_LEN 2 /* Inactie Flag Length */
+#define RSASIG_LEN 20 /* Length of RSA Signature in tag */
+#define TAGINFO1_LEN 30 /* Length of vendor information field1 in tag */
+#define FLASHLAYOUTVER_LEN 4 /* Length of Flash Layout Version String tag */
+#define TAGINFO2_LEN 16 /* Length of vendor information field2 in tag */
+#define CRC_LEN 4 /* Length of CRC in bytes */
+#define ALTTAGINFO_LEN 54 /* Alternate length for vendor information; Pirelli */
+
+#define NUM_PIRELLI 2
+#define IMAGETAG_CRC_START 0xFFFFFFFF
+
+#define PIRELLI_BOARDS { \
+ "AGPF-S0", \
+ "DWV-S0", \
+}
+
+/*
+ * The broadcom firmware assumes the rootfs starts the image,
+ * therefore uses the rootfs start (flash_image_address)
+ * to determine where to flash the image. Since we have the kernel first
+ * we have to give it the kernel address, but the crc uses the length
+ * associated with this address (root_length), which is added to the kernel
+ * length (kernel_length) to determine the length of image to flash and thus
+ * needs to be rootfs + deadcode (jffs2 EOF marker)
+*/
+
+struct bcm_tag {
+ /* 0-3: Version of the image tag */
+ char tag_version[TAGVER_LEN];
+ /* 4-23: Company Line 1 */
+ char sig_1[SIG1_LEN];
+ /* 24-37: Company Line 2 */
+ char sig_2[SIG2_LEN];
+ /* 38-43: Chip this image is for */
+ char chip_id[CHIPID_LEN];
+ /* 44-59: Board name */
+ char board_id[BOARDID_LEN];
+ /* 60-61: Map endianness -- 1 BE 0 LE */
+ char big_endian[ENDIANFLAG_LEN];
+ /* 62-71: Total length of image */
+ char total_length[IMAGE_LEN];
+ /* 72-83: Address in memory of CFE */
+ char cfe__address[ADDRESS_LEN];
+ /* 84-93: Size of CFE */
+ char cfe_length[IMAGE_LEN];
+ /* 94-105: Address in memory of image start
+ * (kernel for OpenWRT, rootfs for stock firmware)
+ */
+ char flash_image_start[ADDRESS_LEN];
+ /* 106-115: Size of rootfs */
+ char root_length[IMAGE_LEN];
+ /* 116-127: Address in memory of kernel */
+ char kernel_address[ADDRESS_LEN];
+ /* 128-137: Size of kernel */
+ char kernel_length[IMAGE_LEN];
+ /* 138-139: Unused at the moment */
+ char dual_image[DUALFLAG_LEN];
+ /* 140-141: Unused at the moment */
+ char inactive_flag[INACTIVEFLAG_LEN];
+ /* 142-161: RSA Signature (not used; some vendors may use this) */
+ char rsa_signature[RSASIG_LEN];
+ /* 162-191: Compilation and related information (not used in OpenWrt) */
+ char information1[TAGINFO1_LEN];
+ /* 192-195: Version flash layout */
+ char flash_layout_ver[FLASHLAYOUTVER_LEN];
+ /* 196-199: kernel+rootfs CRC32 */
+ char fskernel_crc[CRC_LEN];
+ /* 200-215: Unused except on Alice Gate where is is information */
+ char information2[TAGINFO2_LEN];
+ /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */
+ char image_crc[CRC_LEN];
+ /* 220-223: CRC32 of rootfs partition */
+ char rootfs_crc[CRC_LEN];
+ /* 224-227: CRC32 of kernel partition */
+ char kernel_crc[CRC_LEN];
+ /* 228-235: Unused at present */
+ char reserved1[8];
+ /* 236-239: CRC32 of header excluding tagVersion */
+ char header_crc[CRC_LEN];
+ /* 240-255: Unused at present */
+ char reserved2[16];
+};
+
+#endif /* __BCM63XX_TAG_H */
#define cpu_has_veic 0
#define cpu_hwrena_impl_bits 0xc0000000
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
return id >= 0x000d0300;
}
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
#endif
struct device;
-dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
-void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+extern void octeon_pci_dma_init(void);
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
- return octeon_map_dma_mem(dev, addr, size);
+ BUG();
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
- return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+ BUG();
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
- return dma_addr;
+ BUG();
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
- octeon_unmap_dma_mem(dev, dma_addr);
+ BUG();
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
- return 1;
+ BUG();
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
- mb();
+ BUG();
}
static inline int plat_device_is_coherent(struct device *dev)
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
- return dma_addr == -1;
+ BUG();
}
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+struct dma_map_ops;
+extern struct dma_map_ops *octeon_pci_dma_map_ops;
+extern char *octeon_swiotlb;
+
#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
return pa;
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
return pa;
}
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_addr & ~(0xffUL << 56);
return pa;
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
dma_addr_t pa;
}
/* This is almost certainly wrong but it's what dma-ip32.c used to use */
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
unsigned long addr = dma_addr & RAM_OFFSET_MASK;
struct device;
-static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return vdma_alloc(virt_to_phys(addr), size);
}
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+ struct page *page)
{
return vdma_alloc(page_to_phys(page), PAGE_SIZE);
}
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return vdma_log2phys(dma_addr);
}
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
vdma_free(dma_addr);
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
+#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo() __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
+
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
+/* BMIPS3300 */
+#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS4380 */
+#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
+
/*
* Macros to access the floating point coprocessor control registers
*/
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_AGL_DEFS_H__
#define __CVMX_AGL_DEFS_H__
-#define CVMX_AGL_GMX_BAD_REG \
- CVMX_ADD_IO_SEG(0x00011800E0000518ull)
-#define CVMX_AGL_GMX_BIST \
- CVMX_ADD_IO_SEG(0x00011800E0000400ull)
-#define CVMX_AGL_GMX_DRV_CTL \
- CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
-#define CVMX_AGL_GMX_INF_MODE \
- CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
-#define CVMX_AGL_GMX_PRTX_CFG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_DECISION(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_IFG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_JABBER(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_PRT_INFO \
- CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
-#define CVMX_AGL_GMX_RX_TX_STATUS \
- CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
-#define CVMX_AGL_GMX_SMACX(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_STAT_BP \
- CVMX_ADD_IO_SEG(0x00011800E0000520ull)
-#define CVMX_AGL_GMX_TXX_APPEND(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT0(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT1(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT2(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT3(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT4(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT5(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT6(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT7(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT8(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT9(offset) \
- CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_THRESH(offset) \
- CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TX_BP \
- CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
-#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
- CVMX_ADD_IO_SEG(0x00011800E0000498ull)
-#define CVMX_AGL_GMX_TX_IFG \
- CVMX_ADD_IO_SEG(0x00011800E0000488ull)
-#define CVMX_AGL_GMX_TX_INT_EN \
- CVMX_ADD_IO_SEG(0x00011800E0000508ull)
-#define CVMX_AGL_GMX_TX_INT_REG \
- CVMX_ADD_IO_SEG(0x00011800E0000500ull)
-#define CVMX_AGL_GMX_TX_JAM \
- CVMX_ADD_IO_SEG(0x00011800E0000490ull)
-#define CVMX_AGL_GMX_TX_LFSR \
- CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
-#define CVMX_AGL_GMX_TX_OVR_BP \
- CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
- CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
- CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
union cvmx_agl_gmx_bad_reg {
uint64_t u64;
struct cvmx_agl_gmx_bad_reg_s {
+ uint64_t reserved_38_63:26;
+ uint64_t txpsh1:1;
+ uint64_t txpop1:1;
+ uint64_t ovrflw1:1;
+ uint64_t txpsh:1;
+ uint64_t txpop:1;
+ uint64_t ovrflw:1;
+ uint64_t reserved_27_31:5;
+ uint64_t statovr:1;
+ uint64_t reserved_24_25:2;
+ uint64_t loststat:2;
+ uint64_t reserved_4_21:18;
+ uint64_t out_ovr:2;
+ uint64_t reserved_0_1:2;
+ } s;
+ struct cvmx_agl_gmx_bad_reg_cn52xx {
uint64_t reserved_38_63:26;
uint64_t txpsh1:1;
uint64_t txpop1:1;
uint64_t reserved_4_21:18;
uint64_t out_ovr:2;
uint64_t reserved_0_1:2;
- } s;
- struct cvmx_agl_gmx_bad_reg_s cn52xx;
- struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_bad_reg_cn56xx {
uint64_t reserved_35_63:29;
uint64_t txpsh:1;
uint64_t reserved_0_1:2;
} cn56xx;
struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_bad_reg_s cn63xx;
+ struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
};
union cvmx_agl_gmx_bist {
uint64_t u64;
struct cvmx_agl_gmx_bist_s {
+ uint64_t reserved_25_63:39;
+ uint64_t status:25;
+ } s;
+ struct cvmx_agl_gmx_bist_cn52xx {
uint64_t reserved_10_63:54;
uint64_t status:10;
- } s;
- struct cvmx_agl_gmx_bist_s cn52xx;
- struct cvmx_agl_gmx_bist_s cn52xxp1;
- struct cvmx_agl_gmx_bist_s cn56xx;
- struct cvmx_agl_gmx_bist_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_bist_cn52xx cn56xx;
+ struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_bist_s cn63xx;
+ struct cvmx_agl_gmx_bist_s cn63xxp1;
};
union cvmx_agl_gmx_drv_ctl {
union cvmx_agl_gmx_prtx_cfg {
uint64_t u64;
struct cvmx_agl_gmx_prtx_cfg_s {
- uint64_t reserved_6_63:58;
+ uint64_t reserved_14_63:50;
+ uint64_t tx_idle:1;
+ uint64_t rx_idle:1;
+ uint64_t reserved_9_11:3;
+ uint64_t speed_msb:1;
+ uint64_t reserved_7_7:1;
+ uint64_t burst:1;
uint64_t tx_en:1;
uint64_t rx_en:1;
uint64_t slottime:1;
uint64_t speed:1;
uint64_t en:1;
} s;
- struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
- struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+ uint64_t reserved_6_63:58;
+ uint64_t tx_en:1;
+ uint64_t rx_en:1;
+ uint64_t slottime:1;
+ uint64_t duplex:1;
+ uint64_t speed:1;
+ uint64_t en:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
+ struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
+ struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam0 {
struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam1 {
struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam2 {
struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam3 {
struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam4 {
struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam5 {
struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam_en {
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_adr_ctl {
struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_decision {
struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
struct cvmx_agl_gmx_rxx_decision_s cn56xx;
struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_decision_s cn63xx;
+ struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_chk {
uint64_t u64;
struct cvmx_agl_gmx_rxx_frm_chk_s {
+ uint64_t reserved_10_63:54;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
uint64_t reserved_9_63:55;
uint64_t skperr:1;
uint64_t rcverr:1;
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_ctl {
uint64_t u64;
struct cvmx_agl_gmx_rxx_frm_ctl_s {
- uint64_t reserved_10_63:54;
+ uint64_t reserved_13_63:51;
+ uint64_t ptp_mode:1;
+ uint64_t reserved_11_11:1;
+ uint64_t null_dis:1;
uint64_t pre_align:1;
uint64_t pad_len:1;
uint64_t vlan_len:1;
uint64_t pre_strp:1;
uint64_t pre_chk:1;
} s;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+ uint64_t reserved_10_63:54;
+ uint64_t pre_align:1;
+ uint64_t pad_len:1;
+ uint64_t vlan_len:1;
+ uint64_t pre_free:1;
+ uint64_t ctl_smac:1;
+ uint64_t ctl_mcst:1;
+ uint64_t ctl_bck:1;
+ uint64_t ctl_drp:1;
+ uint64_t pre_strp:1;
+ uint64_t pre_chk:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_max {
struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_frm_min {
struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
+ struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_ifg {
struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
+ struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_int_en {
uint64_t u64;
struct cvmx_agl_gmx_rxx_int_en_s {
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
+ struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_int_reg {
uint64_t u64;
struct cvmx_agl_gmx_rxx_int_reg_s {
+ uint64_t reserved_20_63:44;
+ uint64_t pause_drp:1;
+ uint64_t phy_dupx:1;
+ uint64_t phy_spd:1;
+ uint64_t phy_link:1;
+ uint64_t ifgerr:1;
+ uint64_t coldet:1;
+ uint64_t falerr:1;
+ uint64_t rsverr:1;
+ uint64_t pcterr:1;
+ uint64_t ovrerr:1;
+ uint64_t niberr:1;
+ uint64_t skperr:1;
+ uint64_t rcverr:1;
+ uint64_t lenerr:1;
+ uint64_t alnerr:1;
+ uint64_t fcserr:1;
+ uint64_t jabber:1;
+ uint64_t maxerr:1;
+ uint64_t carext:1;
+ uint64_t minerr:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
uint64_t reserved_20_63:44;
uint64_t pause_drp:1;
uint64_t reserved_16_18:3;
uint64_t maxerr:1;
uint64_t reserved_1_1:1;
uint64_t minerr:1;
- } s;
- struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
+ struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
+ struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_jabber {
struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
+ struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_pause_drop_time {
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_rxx_rx_inbnd {
+ uint64_t u64;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+ uint64_t reserved_4_63:60;
+ uint64_t duplex:1;
+ uint64_t speed:2;
+ uint64_t status:1;
+ } s;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
+ struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_ctl {
struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs {
struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_ctl {
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_dmac {
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_drp {
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts {
struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_bad {
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_ctl {
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_dmac {
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_drp {
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
};
union cvmx_agl_gmx_rxx_udd_skp {
struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
+ struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_dropx {
struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_offx {
struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_bp_onx {
struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
+ struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
};
union cvmx_agl_gmx_rx_prt_info {
uint64_t commit:1;
} cn56xx;
struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
+ struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
};
union cvmx_agl_gmx_rx_tx_status {
uint64_t rx:1;
} cn56xx;
struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
+ struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
};
union cvmx_agl_gmx_smacx {
struct cvmx_agl_gmx_smacx_s cn52xxp1;
struct cvmx_agl_gmx_smacx_s cn56xx;
struct cvmx_agl_gmx_smacx_s cn56xxp1;
+ struct cvmx_agl_gmx_smacx_s cn63xx;
+ struct cvmx_agl_gmx_smacx_s cn63xxp1;
};
union cvmx_agl_gmx_stat_bp {
struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
struct cvmx_agl_gmx_stat_bp_s cn56xx;
struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+ struct cvmx_agl_gmx_stat_bp_s cn63xx;
+ struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
};
union cvmx_agl_gmx_txx_append {
struct cvmx_agl_gmx_txx_append_s cn52xxp1;
struct cvmx_agl_gmx_txx_append_s cn56xx;
struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_append_s cn63xx;
+ struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_txx_clk {
+ uint64_t u64;
+ struct cvmx_agl_gmx_txx_clk_s {
+ uint64_t reserved_6_63:58;
+ uint64_t clk_cnt:6;
+ } s;
+ struct cvmx_agl_gmx_txx_clk_s cn63xx;
+ struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
};
union cvmx_agl_gmx_txx_ctl {
struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_ctl_s cn63xx;
+ struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_txx_min_pkt {
struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
+ struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_interval {
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_time {
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_togo {
struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
};
union cvmx_agl_gmx_txx_pause_zero {
struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
+ struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
};
union cvmx_agl_gmx_txx_soft_pause {
struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
+ struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat0 {
struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat0_s cn56xx;
struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat0_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat1 {
struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat1_s cn56xx;
struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat1_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat2 {
struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat2_s cn56xx;
struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat2_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat3 {
struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat3_s cn56xx;
struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat3_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat4 {
struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat4_s cn56xx;
struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat4_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat5 {
struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat5_s cn56xx;
struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat5_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat6 {
struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat6_s cn56xx;
struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat6_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat7 {
struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat7_s cn56xx;
struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat7_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat8 {
struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat8_s cn56xx;
struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat8_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stat9 {
struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
struct cvmx_agl_gmx_txx_stat9_s cn56xx;
struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stat9_s cn63xx;
+ struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
};
union cvmx_agl_gmx_txx_stats_ctl {
struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
+ struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
};
union cvmx_agl_gmx_txx_thresh {
struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
struct cvmx_agl_gmx_txx_thresh_s cn56xx;
struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+ struct cvmx_agl_gmx_txx_thresh_s cn63xx;
+ struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
};
union cvmx_agl_gmx_tx_bp {
uint64_t bp:1;
} cn56xx;
struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_bp_s cn63xx;
+ struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
};
union cvmx_agl_gmx_tx_col_attempt {
struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
+ struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
};
union cvmx_agl_gmx_tx_ifg {
struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
struct cvmx_agl_gmx_tx_ifg_s cn56xx;
struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_ifg_s cn63xx;
+ struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
};
union cvmx_agl_gmx_tx_int_en {
uint64_t u64;
struct cvmx_agl_gmx_tx_int_en_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_22_63:42;
+ uint64_t ptp_lost:2;
+ uint64_t reserved_18_19:2;
uint64_t late_col:2;
uint64_t reserved_14_15:2;
uint64_t xsdef:2;
uint64_t reserved_1_1:1;
uint64_t pko_nxa:1;
} s;
- struct cvmx_agl_gmx_tx_int_en_s cn52xx;
- struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_en_cn52xx {
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_en_cn56xx {
uint64_t reserved_17_63:47;
uint64_t late_col:1;
uint64_t pko_nxa:1;
} cn56xx;
struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_en_s cn63xx;
+ struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
};
union cvmx_agl_gmx_tx_int_reg {
uint64_t u64;
struct cvmx_agl_gmx_tx_int_reg_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_22_63:42;
+ uint64_t ptp_lost:2;
+ uint64_t reserved_18_19:2;
uint64_t late_col:2;
uint64_t reserved_14_15:2;
uint64_t xsdef:2;
uint64_t reserved_1_1:1;
uint64_t pko_nxa:1;
} s;
- struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+ uint64_t reserved_18_63:46;
+ uint64_t late_col:2;
+ uint64_t reserved_14_15:2;
+ uint64_t xsdef:2;
+ uint64_t reserved_10_11:2;
+ uint64_t xscol:2;
+ uint64_t reserved_4_7:4;
+ uint64_t undflw:2;
+ uint64_t reserved_1_1:1;
+ uint64_t pko_nxa:1;
+ } cn52xx;
+ struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_reg_cn56xx {
uint64_t reserved_17_63:47;
uint64_t late_col:1;
uint64_t pko_nxa:1;
} cn56xx;
struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
+ struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
};
union cvmx_agl_gmx_tx_jam {
struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
struct cvmx_agl_gmx_tx_jam_s cn56xx;
struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_jam_s cn63xx;
+ struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
};
union cvmx_agl_gmx_tx_lfsr {
struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
+ struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
};
union cvmx_agl_gmx_tx_ovr_bp {
uint64_t ign_full:1;
} cn56xx;
struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
+ struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_dmac {
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_type {
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+};
+
+union cvmx_agl_prtx_ctl {
+ uint64_t u64;
+ struct cvmx_agl_prtx_ctl_s {
+ uint64_t drv_byp:1;
+ uint64_t reserved_62_62:1;
+ uint64_t cmp_pctl:6;
+ uint64_t reserved_54_55:2;
+ uint64_t cmp_nctl:6;
+ uint64_t reserved_46_47:2;
+ uint64_t drv_pctl:6;
+ uint64_t reserved_38_39:2;
+ uint64_t drv_nctl:6;
+ uint64_t reserved_29_31:3;
+ uint64_t clk_set:5;
+ uint64_t clkrx_byp:1;
+ uint64_t reserved_21_22:2;
+ uint64_t clkrx_set:5;
+ uint64_t clktx_byp:1;
+ uint64_t reserved_13_14:2;
+ uint64_t clktx_set:5;
+ uint64_t reserved_5_7:3;
+ uint64_t dllrst:1;
+ uint64_t comp:1;
+ uint64_t enable:1;
+ uint64_t clkrst:1;
+ uint64_t mode:1;
+ } s;
+ struct cvmx_agl_prtx_ctl_s cn63xx;
+ struct cvmx_agl_prtx_ctl_s cn63xxp1;
};
#endif
#define CVMX_DCACHE_INVALIDATE \
{ CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
+#define CVMX_CACHE(op, address, offset) \
+ asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
+ : : [rbase] "d" (address) )
+/* fetch and lock the state. */
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
+/* unlock the state. */
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
+/* invalidate the cache block and clear the USED bits for the block */
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
+/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
#define CVMX_POP(result, input) \
asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_CIU_DEFS_H__
#define __CVMX_CIU_DEFS_H__
-#define CVMX_CIU_BIST \
- CVMX_ADD_IO_SEG(0x0001070000000730ull)
-#define CVMX_CIU_DINT \
- CVMX_ADD_IO_SEG(0x0001070000000720ull)
-#define CVMX_CIU_FUSE \
- CVMX_ADD_IO_SEG(0x0001070000000728ull)
-#define CVMX_CIU_GSTOP \
- CVMX_ADD_IO_SEG(0x0001070000000710ull)
-#define CVMX_CIU_INTX_EN0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN4_0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
- CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
- CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_SUM0(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
-#define CVMX_CIU_INTX_SUM4(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
-#define CVMX_CIU_INT_SUM1 \
- CVMX_ADD_IO_SEG(0x0001070000000108ull)
-#define CVMX_CIU_MBOX_CLRX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
-#define CVMX_CIU_MBOX_SETX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
-#define CVMX_CIU_NMI \
- CVMX_ADD_IO_SEG(0x0001070000000718ull)
-#define CVMX_CIU_PCI_INTA \
- CVMX_ADD_IO_SEG(0x0001070000000750ull)
-#define CVMX_CIU_PP_DBG \
- CVMX_ADD_IO_SEG(0x0001070000000708ull)
-#define CVMX_CIU_PP_POKEX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
-#define CVMX_CIU_PP_RST \
- CVMX_ADD_IO_SEG(0x0001070000000700ull)
-#define CVMX_CIU_QLM_DCOK \
- CVMX_ADD_IO_SEG(0x0001070000000760ull)
-#define CVMX_CIU_QLM_JTGC \
- CVMX_ADD_IO_SEG(0x0001070000000768ull)
-#define CVMX_CIU_QLM_JTGD \
- CVMX_ADD_IO_SEG(0x0001070000000770ull)
-#define CVMX_CIU_SOFT_BIST \
- CVMX_ADD_IO_SEG(0x0001070000000738ull)
-#define CVMX_CIU_SOFT_PRST \
- CVMX_ADD_IO_SEG(0x0001070000000748ull)
-#define CVMX_CIU_SOFT_PRST1 \
- CVMX_ADD_IO_SEG(0x0001070000000758ull)
-#define CVMX_CIU_SOFT_RST \
- CVMX_ADD_IO_SEG(0x0001070000000740ull)
-#define CVMX_CIU_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
-#define CVMX_CIU_WDOGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
+#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
+#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
+#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
+#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
+#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
+#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
+#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
+#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
+#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
+#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
+#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
+#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
+#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
+#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
+#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
union cvmx_ciu_bist {
uint64_t u64;
struct cvmx_ciu_bist_s {
+ uint64_t reserved_5_63:59;
+ uint64_t bist:5;
+ } s;
+ struct cvmx_ciu_bist_cn30xx {
uint64_t reserved_4_63:60;
uint64_t bist:4;
- } s;
- struct cvmx_ciu_bist_s cn30xx;
- struct cvmx_ciu_bist_s cn31xx;
- struct cvmx_ciu_bist_s cn38xx;
- struct cvmx_ciu_bist_s cn38xxp2;
+ } cn30xx;
+ struct cvmx_ciu_bist_cn30xx cn31xx;
+ struct cvmx_ciu_bist_cn30xx cn38xx;
+ struct cvmx_ciu_bist_cn30xx cn38xxp2;
struct cvmx_ciu_bist_cn50xx {
uint64_t reserved_2_63:62;
uint64_t bist:2;
uint64_t bist:3;
} cn52xx;
struct cvmx_ciu_bist_cn52xx cn52xxp1;
- struct cvmx_ciu_bist_s cn56xx;
- struct cvmx_ciu_bist_s cn56xxp1;
- struct cvmx_ciu_bist_s cn58xx;
- struct cvmx_ciu_bist_s cn58xxp1;
+ struct cvmx_ciu_bist_cn30xx cn56xx;
+ struct cvmx_ciu_bist_cn30xx cn56xxp1;
+ struct cvmx_ciu_bist_cn30xx cn58xx;
+ struct cvmx_ciu_bist_cn30xx cn58xxp1;
+ struct cvmx_ciu_bist_s cn63xx;
+ struct cvmx_ciu_bist_s cn63xxp1;
+};
+
+union cvmx_ciu_block_int {
+ uint64_t u64;
+ struct cvmx_ciu_block_int_s {
+ uint64_t reserved_43_63:21;
+ uint64_t ptp:1;
+ uint64_t dpi:1;
+ uint64_t dfm:1;
+ uint64_t reserved_34_39:6;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t reserved_31_31:1;
+ uint64_t iob:1;
+ uint64_t reserved_29_29:1;
+ uint64_t agl:1;
+ uint64_t reserved_27_27:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t reserved_23_24:2;
+ uint64_t asxpcs0:1;
+ uint64_t reserved_21_21:1;
+ uint64_t pip:1;
+ uint64_t reserved_18_19:2;
+ uint64_t lmc0:1;
+ uint64_t l2c:1;
+ uint64_t reserved_15_15:1;
+ uint64_t rad:1;
+ uint64_t usb:1;
+ uint64_t pow:1;
+ uint64_t tim:1;
+ uint64_t pko:1;
+ uint64_t ipd:1;
+ uint64_t reserved_8_8:1;
+ uint64_t zip:1;
+ uint64_t dfa:1;
+ uint64_t fpa:1;
+ uint64_t key:1;
+ uint64_t sli:1;
+ uint64_t reserved_2_2:1;
+ uint64_t gmx0:1;
+ uint64_t mio:1;
+ } s;
+ struct cvmx_ciu_block_int_s cn63xx;
+ struct cvmx_ciu_block_int_s cn63xxp1;
};
union cvmx_ciu_dint {
struct cvmx_ciu_dint_cn56xx cn56xxp1;
struct cvmx_ciu_dint_s cn58xx;
struct cvmx_ciu_dint_s cn58xxp1;
+ struct cvmx_ciu_dint_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t dint:6;
+ } cn63xx;
+ struct cvmx_ciu_dint_cn63xx cn63xxp1;
};
union cvmx_ciu_fuse {
struct cvmx_ciu_fuse_cn56xx cn56xxp1;
struct cvmx_ciu_fuse_s cn58xx;
struct cvmx_ciu_fuse_s cn58xxp1;
+ struct cvmx_ciu_fuse_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t fuse:6;
+ } cn63xx;
+ struct cvmx_ciu_fuse_cn63xx cn63xxp1;
};
union cvmx_ciu_gstop {
struct cvmx_ciu_gstop_s cn56xxp1;
struct cvmx_ciu_gstop_s cn58xx;
struct cvmx_ciu_gstop_s cn58xxp1;
+ struct cvmx_ciu_gstop_s cn63xx;
+ struct cvmx_ciu_gstop_s cn63xxp1;
};
union cvmx_ciu_intx_en0 {
struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en0_cn38xx cn58xx;
struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_en0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en0_w1c {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en0_w1s {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en1 {
uint64_t u64;
struct cvmx_ciu_intx_en1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
struct cvmx_ciu_intx_en1_cn38xx cn58xx;
struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_en1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en1_w1c {
uint64_t u64;
struct cvmx_ciu_intx_en1_w1c_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en1_w1c_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en1_w1s {
uint64_t u64;
struct cvmx_ciu_intx_en1_w1s_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en1_w1s_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0 {
uint64_t workq:16;
} cn58xx;
struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0_w1c {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_0_w1s {
uint64_t gpio:16;
uint64_t workq:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+ struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1 {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
uint64_t wdog:16;
} cn58xx;
struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_en4_1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1_w1c {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_w1c_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_en4_1_w1s {
uint64_t u64;
struct cvmx_ciu_intx_en4_1_w1s_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
uint64_t reserved_16_63:48;
uint64_t wdog:16;
} cn58xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
};
union cvmx_ciu_intx_sum0 {
struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+ struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
+ struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
};
union cvmx_ciu_intx_sum4 {
uint64_t workq:16;
} cn58xx;
struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+ struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
+ struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+};
+
+union cvmx_ciu_int33_sum0 {
+ uint64_t u64;
+ struct cvmx_ciu_int33_sum0_s {
+ uint64_t bootdma:1;
+ uint64_t mii:1;
+ uint64_t ipdppthr:1;
+ uint64_t powiq:1;
+ uint64_t twsi2:1;
+ uint64_t reserved_57_58:2;
+ uint64_t usb:1;
+ uint64_t timer:4;
+ uint64_t reserved_51_51:1;
+ uint64_t ipd_drp:1;
+ uint64_t reserved_49_49:1;
+ uint64_t gmx_drp:1;
+ uint64_t trace:1;
+ uint64_t rml:1;
+ uint64_t twsi:1;
+ uint64_t wdog_sum:1;
+ uint64_t pci_msi:4;
+ uint64_t pci_int:4;
+ uint64_t uart:2;
+ uint64_t mbox:2;
+ uint64_t gpio:16;
+ uint64_t workq:16;
+ } s;
+ struct cvmx_ciu_int33_sum0_s cn63xx;
+ struct cvmx_ciu_int33_sum0_s cn63xxp1;
+};
+
+union cvmx_ciu_int_dbg_sel {
+ uint64_t u64;
+ struct cvmx_ciu_int_dbg_sel_s {
+ uint64_t reserved_19_63:45;
+ uint64_t sel:3;
+ uint64_t reserved_10_15:6;
+ uint64_t irq:2;
+ uint64_t reserved_3_7:5;
+ uint64_t pp:3;
+ } s;
+ struct cvmx_ciu_int_dbg_sel_s cn63xx;
};
union cvmx_ciu_int_sum1 {
uint64_t u64;
struct cvmx_ciu_int_sum1_s {
- uint64_t reserved_20_63:44;
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
uint64_t nand:1;
uint64_t mii1:1;
uint64_t usb1:1;
struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
struct cvmx_ciu_int_sum1_cn38xx cn58xx;
struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+ struct cvmx_ciu_int_sum1_cn63xx {
+ uint64_t rst:1;
+ uint64_t reserved_57_62:6;
+ uint64_t dfm:1;
+ uint64_t reserved_53_55:3;
+ uint64_t lmc0:1;
+ uint64_t srio1:1;
+ uint64_t srio0:1;
+ uint64_t pem1:1;
+ uint64_t pem0:1;
+ uint64_t ptp:1;
+ uint64_t agl:1;
+ uint64_t reserved_37_45:9;
+ uint64_t agx0:1;
+ uint64_t dpi:1;
+ uint64_t sli:1;
+ uint64_t usb:1;
+ uint64_t dfa:1;
+ uint64_t key:1;
+ uint64_t rad:1;
+ uint64_t tim:1;
+ uint64_t zip:1;
+ uint64_t pko:1;
+ uint64_t pip:1;
+ uint64_t ipd:1;
+ uint64_t l2c:1;
+ uint64_t pow:1;
+ uint64_t fpa:1;
+ uint64_t iob:1;
+ uint64_t mio:1;
+ uint64_t nand:1;
+ uint64_t mii1:1;
+ uint64_t reserved_6_17:12;
+ uint64_t wdog:6;
+ } cn63xx;
+ struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
};
union cvmx_ciu_mbox_clrx {
struct cvmx_ciu_mbox_clrx_s cn56xxp1;
struct cvmx_ciu_mbox_clrx_s cn58xx;
struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+ struct cvmx_ciu_mbox_clrx_s cn63xx;
+ struct cvmx_ciu_mbox_clrx_s cn63xxp1;
};
union cvmx_ciu_mbox_setx {
struct cvmx_ciu_mbox_setx_s cn56xxp1;
struct cvmx_ciu_mbox_setx_s cn58xx;
struct cvmx_ciu_mbox_setx_s cn58xxp1;
+ struct cvmx_ciu_mbox_setx_s cn63xx;
+ struct cvmx_ciu_mbox_setx_s cn63xxp1;
};
union cvmx_ciu_nmi {
struct cvmx_ciu_nmi_cn56xx cn56xxp1;
struct cvmx_ciu_nmi_s cn58xx;
struct cvmx_ciu_nmi_s cn58xxp1;
+ struct cvmx_ciu_nmi_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t nmi:6;
+ } cn63xx;
+ struct cvmx_ciu_nmi_cn63xx cn63xxp1;
};
union cvmx_ciu_pci_inta {
struct cvmx_ciu_pci_inta_s cn56xxp1;
struct cvmx_ciu_pci_inta_s cn58xx;
struct cvmx_ciu_pci_inta_s cn58xxp1;
+ struct cvmx_ciu_pci_inta_s cn63xx;
+ struct cvmx_ciu_pci_inta_s cn63xxp1;
};
union cvmx_ciu_pp_dbg {
struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
struct cvmx_ciu_pp_dbg_s cn58xx;
struct cvmx_ciu_pp_dbg_s cn58xxp1;
+ struct cvmx_ciu_pp_dbg_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t ppdbg:6;
+ } cn63xx;
+ struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
};
union cvmx_ciu_pp_pokex {
uint64_t u64;
struct cvmx_ciu_pp_pokex_s {
- uint64_t reserved_0_63:64;
+ uint64_t poke:64;
} s;
struct cvmx_ciu_pp_pokex_s cn30xx;
struct cvmx_ciu_pp_pokex_s cn31xx;
struct cvmx_ciu_pp_pokex_s cn56xxp1;
struct cvmx_ciu_pp_pokex_s cn58xx;
struct cvmx_ciu_pp_pokex_s cn58xxp1;
+ struct cvmx_ciu_pp_pokex_s cn63xx;
+ struct cvmx_ciu_pp_pokex_s cn63xxp1;
};
union cvmx_ciu_pp_rst {
struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
struct cvmx_ciu_pp_rst_s cn58xx;
struct cvmx_ciu_pp_rst_s cn58xxp1;
+ struct cvmx_ciu_pp_rst_cn63xx {
+ uint64_t reserved_6_63:58;
+ uint64_t rst:5;
+ uint64_t rst0:1;
+ } cn63xx;
+ struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+};
+
+union cvmx_ciu_qlm0 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm0_s {
+ uint64_t g2bypass:1;
+ uint64_t reserved_53_62:10;
+ uint64_t g2deemph:5;
+ uint64_t reserved_45_47:3;
+ uint64_t g2margin:5;
+ uint64_t reserved_32_39:8;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm0_s cn63xx;
+ struct cvmx_ciu_qlm0_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
+};
+
+union cvmx_ciu_qlm1 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm1_s {
+ uint64_t g2bypass:1;
+ uint64_t reserved_53_62:10;
+ uint64_t g2deemph:5;
+ uint64_t reserved_45_47:3;
+ uint64_t g2margin:5;
+ uint64_t reserved_32_39:8;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm1_s cn63xx;
+ struct cvmx_ciu_qlm1_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
+};
+
+union cvmx_ciu_qlm2 {
+ uint64_t u64;
+ struct cvmx_ciu_qlm2_s {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_21_30:10;
+ uint64_t txdeemph:5;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } s;
+ struct cvmx_ciu_qlm2_s cn63xx;
+ struct cvmx_ciu_qlm2_cn63xxp1 {
+ uint64_t reserved_32_63:32;
+ uint64_t txbypass:1;
+ uint64_t reserved_20_30:11;
+ uint64_t txdeemph:4;
+ uint64_t reserved_13_15:3;
+ uint64_t txmargin:5;
+ uint64_t reserved_4_7:4;
+ uint64_t lane_en:4;
+ } cn63xxp1;
};
union cvmx_ciu_qlm_dcok {
struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
struct cvmx_ciu_qlm_jtgc_s cn56xx;
struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+ struct cvmx_ciu_qlm_jtgc_cn63xx {
+ uint64_t reserved_11_63:53;
+ uint64_t clk_div:3;
+ uint64_t reserved_6_7:2;
+ uint64_t mux_sel:2;
+ uint64_t reserved_3_3:1;
+ uint64_t bypass:3;
+ } cn63xx;
+ struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
};
union cvmx_ciu_qlm_jtgd {
uint64_t shft_cnt:5;
uint64_t shft_reg:32;
} cn56xxp1;
+ struct cvmx_ciu_qlm_jtgd_cn63xx {
+ uint64_t capture:1;
+ uint64_t shift:1;
+ uint64_t update:1;
+ uint64_t reserved_43_60:18;
+ uint64_t select:3;
+ uint64_t reserved_37_39:3;
+ uint64_t shft_cnt:5;
+ uint64_t shft_reg:32;
+ } cn63xx;
+ struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
};
union cvmx_ciu_soft_bist {
struct cvmx_ciu_soft_bist_s cn56xxp1;
struct cvmx_ciu_soft_bist_s cn58xx;
struct cvmx_ciu_soft_bist_s cn58xxp1;
+ struct cvmx_ciu_soft_bist_s cn63xx;
+ struct cvmx_ciu_soft_bist_s cn63xxp1;
};
union cvmx_ciu_soft_prst {
struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
struct cvmx_ciu_soft_prst_s cn58xx;
struct cvmx_ciu_soft_prst_s cn58xxp1;
+ struct cvmx_ciu_soft_prst_cn52xx cn63xx;
+ struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
};
union cvmx_ciu_soft_prst1 {
struct cvmx_ciu_soft_prst1_s cn52xxp1;
struct cvmx_ciu_soft_prst1_s cn56xx;
struct cvmx_ciu_soft_prst1_s cn56xxp1;
+ struct cvmx_ciu_soft_prst1_s cn63xx;
+ struct cvmx_ciu_soft_prst1_s cn63xxp1;
};
union cvmx_ciu_soft_rst {
struct cvmx_ciu_soft_rst_s cn56xxp1;
struct cvmx_ciu_soft_rst_s cn58xx;
struct cvmx_ciu_soft_rst_s cn58xxp1;
+ struct cvmx_ciu_soft_rst_s cn63xx;
+ struct cvmx_ciu_soft_rst_s cn63xxp1;
};
union cvmx_ciu_timx {
struct cvmx_ciu_timx_s cn56xxp1;
struct cvmx_ciu_timx_s cn58xx;
struct cvmx_ciu_timx_s cn58xxp1;
+ struct cvmx_ciu_timx_s cn63xx;
+ struct cvmx_ciu_timx_s cn63xxp1;
};
union cvmx_ciu_wdogx {
struct cvmx_ciu_wdogx_s cn56xxp1;
struct cvmx_ciu_wdogx_s cn58xx;
struct cvmx_ciu_wdogx_s cn58xxp1;
+ struct cvmx_ciu_wdogx_s cn63xx;
+ struct cvmx_ciu_wdogx_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_GPIO_DEFS_H__
#define __CVMX_GPIO_DEFS_H__
-#define CVMX_GPIO_BIT_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
-#define CVMX_GPIO_BOOT_ENA \
- CVMX_ADD_IO_SEG(0x00010700000008A8ull)
-#define CVMX_GPIO_CLK_GENX(offset) \
- CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
-#define CVMX_GPIO_DBG_ENA \
- CVMX_ADD_IO_SEG(0x00010700000008A0ull)
-#define CVMX_GPIO_INT_CLR \
- CVMX_ADD_IO_SEG(0x0001070000000898ull)
-#define CVMX_GPIO_RX_DAT \
- CVMX_ADD_IO_SEG(0x0001070000000880ull)
-#define CVMX_GPIO_TX_CLR \
- CVMX_ADD_IO_SEG(0x0001070000000890ull)
-#define CVMX_GPIO_TX_SET \
- CVMX_ADD_IO_SEG(0x0001070000000888ull)
-#define CVMX_GPIO_XBIT_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
union cvmx_gpio_bit_cfgx {
uint64_t u64;
struct cvmx_gpio_bit_cfgx_s {
- uint64_t reserved_15_63:49;
+ uint64_t reserved_17_63:47;
+ uint64_t synce_sel:2;
uint64_t clk_gen:1;
uint64_t clk_sel:2;
uint64_t fil_sel:4;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
- struct cvmx_gpio_bit_cfgx_s cn52xx;
- struct cvmx_gpio_bit_cfgx_s cn52xxp1;
- struct cvmx_gpio_bit_cfgx_s cn56xx;
- struct cvmx_gpio_bit_cfgx_s cn56xxp1;
+ struct cvmx_gpio_bit_cfgx_cn52xx {
+ uint64_t reserved_15_63:49;
+ uint64_t clk_gen:1;
+ uint64_t clk_sel:2;
+ uint64_t fil_sel:4;
+ uint64_t fil_cnt:4;
+ uint64_t int_type:1;
+ uint64_t int_en:1;
+ uint64_t rx_xor:1;
+ uint64_t tx_oe:1;
+ } cn52xx;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
+ struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
+ struct cvmx_gpio_bit_cfgx_s cn63xx;
+ struct cvmx_gpio_bit_cfgx_s cn63xxp1;
};
union cvmx_gpio_boot_ena {
struct cvmx_gpio_clk_genx_s cn52xxp1;
struct cvmx_gpio_clk_genx_s cn56xx;
struct cvmx_gpio_clk_genx_s cn56xxp1;
+ struct cvmx_gpio_clk_genx_s cn63xx;
+ struct cvmx_gpio_clk_genx_s cn63xxp1;
+};
+
+union cvmx_gpio_clk_qlmx {
+ uint64_t u64;
+ struct cvmx_gpio_clk_qlmx_s {
+ uint64_t reserved_3_63:61;
+ uint64_t div:1;
+ uint64_t lane_sel:2;
+ } s;
+ struct cvmx_gpio_clk_qlmx_s cn63xx;
+ struct cvmx_gpio_clk_qlmx_s cn63xxp1;
};
union cvmx_gpio_dbg_ena {
struct cvmx_gpio_int_clr_s cn56xxp1;
struct cvmx_gpio_int_clr_s cn58xx;
struct cvmx_gpio_int_clr_s cn58xxp1;
+ struct cvmx_gpio_int_clr_s cn63xx;
+ struct cvmx_gpio_int_clr_s cn63xxp1;
};
union cvmx_gpio_rx_dat {
struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
struct cvmx_gpio_rx_dat_cn38xx cn58xx;
struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
+ struct cvmx_gpio_rx_dat_cn38xx cn63xx;
+ struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
};
union cvmx_gpio_tx_clr {
struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
struct cvmx_gpio_tx_clr_cn38xx cn58xx;
struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
+ struct cvmx_gpio_tx_clr_cn38xx cn63xx;
+ struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
};
union cvmx_gpio_tx_set {
struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
struct cvmx_gpio_tx_set_cn38xx cn58xx;
struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
+ struct cvmx_gpio_tx_set_cn38xx cn63xx;
+ struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
};
union cvmx_gpio_xbit_cfgx {
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_IOB_DEFS_H__
#define __CVMX_IOB_DEFS_H__
-#define CVMX_IOB_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
-#define CVMX_IOB_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011800F0000050ull)
-#define CVMX_IOB_DWB_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000028ull)
-#define CVMX_IOB_FAU_TIMEOUT \
- CVMX_ADD_IO_SEG(0x00011800F0000000ull)
-#define CVMX_IOB_I2C_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000010ull)
-#define CVMX_IOB_INB_CONTROL_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000078ull)
-#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000088ull)
-#define CVMX_IOB_INB_DATA_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000070ull)
-#define CVMX_IOB_INB_DATA_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000080ull)
-#define CVMX_IOB_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011800F0000060ull)
-#define CVMX_IOB_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011800F0000058ull)
-#define CVMX_IOB_N2C_L2C_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000020ull)
-#define CVMX_IOB_N2C_RSP_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000008ull)
-#define CVMX_IOB_OUTB_COM_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000040ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000098ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
-#define CVMX_IOB_OUTB_DATA_MATCH \
- CVMX_ADD_IO_SEG(0x00011800F0000090ull)
-#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
- CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
-#define CVMX_IOB_OUTB_FPA_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000048ull)
-#define CVMX_IOB_OUTB_REQ_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000038ull)
-#define CVMX_IOB_P2C_REQ_PRI_CNT \
- CVMX_ADD_IO_SEG(0x00011800F0000018ull)
-#define CVMX_IOB_PKT_ERR \
- CVMX_ADD_IO_SEG(0x00011800F0000068ull)
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
union cvmx_iob_bist_status {
uint64_t u64;
struct cvmx_iob_bist_status_s {
- uint64_t reserved_18_63:46;
+ uint64_t reserved_23_63:41;
+ uint64_t xmdfif:1;
+ uint64_t xmcfif:1;
+ uint64_t iorfif:1;
+ uint64_t rsdfif:1;
+ uint64_t iocfif:1;
uint64_t icnrcb:1;
uint64_t icr0:1;
uint64_t icr1:1;
uint64_t ibd:1;
uint64_t icd:1;
} s;
- struct cvmx_iob_bist_status_s cn30xx;
- struct cvmx_iob_bist_status_s cn31xx;
- struct cvmx_iob_bist_status_s cn38xx;
- struct cvmx_iob_bist_status_s cn38xxp2;
- struct cvmx_iob_bist_status_s cn50xx;
- struct cvmx_iob_bist_status_s cn52xx;
- struct cvmx_iob_bist_status_s cn52xxp1;
- struct cvmx_iob_bist_status_s cn56xx;
- struct cvmx_iob_bist_status_s cn56xxp1;
- struct cvmx_iob_bist_status_s cn58xx;
- struct cvmx_iob_bist_status_s cn58xxp1;
+ struct cvmx_iob_bist_status_cn30xx {
+ uint64_t reserved_18_63:46;
+ uint64_t icnrcb:1;
+ uint64_t icr0:1;
+ uint64_t icr1:1;
+ uint64_t icnr1:1;
+ uint64_t icnr0:1;
+ uint64_t ibdr0:1;
+ uint64_t ibdr1:1;
+ uint64_t ibr0:1;
+ uint64_t ibr1:1;
+ uint64_t icnrt:1;
+ uint64_t ibrq0:1;
+ uint64_t ibrq1:1;
+ uint64_t icrn0:1;
+ uint64_t icrn1:1;
+ uint64_t icrp0:1;
+ uint64_t icrp1:1;
+ uint64_t ibd:1;
+ uint64_t icd:1;
+ } cn30xx;
+ struct cvmx_iob_bist_status_cn30xx cn31xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+ struct cvmx_iob_bist_status_cn30xx cn50xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn56xx;
+ struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn58xx;
+ struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+ struct cvmx_iob_bist_status_s cn63xx;
+ struct cvmx_iob_bist_status_s cn63xxp1;
};
union cvmx_iob_ctl_status {
uint64_t u64;
struct cvmx_iob_ctl_status_s {
- uint64_t reserved_5_63:59;
+ uint64_t reserved_10_63:54;
+ uint64_t xmc_per:4;
+ uint64_t rr_mode:1;
uint64_t outb_mat:1;
uint64_t inb_mat:1;
uint64_t pko_enb:1;
uint64_t dwb_enb:1;
uint64_t fau_end:1;
} s;
- struct cvmx_iob_ctl_status_s cn30xx;
- struct cvmx_iob_ctl_status_s cn31xx;
- struct cvmx_iob_ctl_status_s cn38xx;
- struct cvmx_iob_ctl_status_s cn38xxp2;
- struct cvmx_iob_ctl_status_s cn50xx;
- struct cvmx_iob_ctl_status_s cn52xx;
- struct cvmx_iob_ctl_status_s cn52xxp1;
- struct cvmx_iob_ctl_status_s cn56xx;
- struct cvmx_iob_ctl_status_s cn56xxp1;
- struct cvmx_iob_ctl_status_s cn58xx;
- struct cvmx_iob_ctl_status_s cn58xxp1;
+ struct cvmx_iob_ctl_status_cn30xx {
+ uint64_t reserved_5_63:59;
+ uint64_t outb_mat:1;
+ uint64_t inb_mat:1;
+ uint64_t pko_enb:1;
+ uint64_t dwb_enb:1;
+ uint64_t fau_end:1;
+ } cn30xx;
+ struct cvmx_iob_ctl_status_cn30xx cn31xx;
+ struct cvmx_iob_ctl_status_cn30xx cn38xx;
+ struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
+ struct cvmx_iob_ctl_status_cn30xx cn50xx;
+ struct cvmx_iob_ctl_status_cn52xx {
+ uint64_t reserved_6_63:58;
+ uint64_t rr_mode:1;
+ uint64_t outb_mat:1;
+ uint64_t inb_mat:1;
+ uint64_t pko_enb:1;
+ uint64_t dwb_enb:1;
+ uint64_t fau_end:1;
+ } cn52xx;
+ struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
+ struct cvmx_iob_ctl_status_cn30xx cn56xx;
+ struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
+ struct cvmx_iob_ctl_status_cn30xx cn58xx;
+ struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
+ struct cvmx_iob_ctl_status_s cn63xx;
+ struct cvmx_iob_ctl_status_s cn63xxp1;
};
union cvmx_iob_dwb_pri_cnt {
struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
struct cvmx_iob_dwb_pri_cnt_s cn58xx;
struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_dwb_pri_cnt_s cn63xx;
+ struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
};
union cvmx_iob_fau_timeout {
struct cvmx_iob_fau_timeout_s cn56xxp1;
struct cvmx_iob_fau_timeout_s cn58xx;
struct cvmx_iob_fau_timeout_s cn58xxp1;
+ struct cvmx_iob_fau_timeout_s cn63xx;
+ struct cvmx_iob_fau_timeout_s cn63xxp1;
};
union cvmx_iob_i2c_pri_cnt {
struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
struct cvmx_iob_i2c_pri_cnt_s cn58xx;
struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_i2c_pri_cnt_s cn63xx;
+ struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
};
union cvmx_iob_inb_control_match {
struct cvmx_iob_inb_control_match_s cn56xxp1;
struct cvmx_iob_inb_control_match_s cn58xx;
struct cvmx_iob_inb_control_match_s cn58xxp1;
+ struct cvmx_iob_inb_control_match_s cn63xx;
+ struct cvmx_iob_inb_control_match_s cn63xxp1;
};
union cvmx_iob_inb_control_match_enb {
struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
struct cvmx_iob_inb_control_match_enb_s cn58xx;
struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+ struct cvmx_iob_inb_control_match_enb_s cn63xx;
+ struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
};
union cvmx_iob_inb_data_match {
struct cvmx_iob_inb_data_match_s cn56xxp1;
struct cvmx_iob_inb_data_match_s cn58xx;
struct cvmx_iob_inb_data_match_s cn58xxp1;
+ struct cvmx_iob_inb_data_match_s cn63xx;
+ struct cvmx_iob_inb_data_match_s cn63xxp1;
};
union cvmx_iob_inb_data_match_enb {
struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
struct cvmx_iob_inb_data_match_enb_s cn58xx;
struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+ struct cvmx_iob_inb_data_match_enb_s cn63xx;
+ struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
};
union cvmx_iob_int_enb {
struct cvmx_iob_int_enb_s cn56xxp1;
struct cvmx_iob_int_enb_s cn58xx;
struct cvmx_iob_int_enb_s cn58xxp1;
+ struct cvmx_iob_int_enb_s cn63xx;
+ struct cvmx_iob_int_enb_s cn63xxp1;
};
union cvmx_iob_int_sum {
struct cvmx_iob_int_sum_s cn56xxp1;
struct cvmx_iob_int_sum_s cn58xx;
struct cvmx_iob_int_sum_s cn58xxp1;
+ struct cvmx_iob_int_sum_s cn63xx;
+ struct cvmx_iob_int_sum_s cn63xxp1;
};
union cvmx_iob_n2c_l2c_pri_cnt {
struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
+ struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
};
union cvmx_iob_n2c_rsp_pri_cnt {
struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
+ struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_com_pri_cnt {
struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_control_match {
struct cvmx_iob_outb_control_match_s cn56xxp1;
struct cvmx_iob_outb_control_match_s cn58xx;
struct cvmx_iob_outb_control_match_s cn58xxp1;
+ struct cvmx_iob_outb_control_match_s cn63xx;
+ struct cvmx_iob_outb_control_match_s cn63xxp1;
};
union cvmx_iob_outb_control_match_enb {
struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
struct cvmx_iob_outb_control_match_enb_s cn58xx;
struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+ struct cvmx_iob_outb_control_match_enb_s cn63xx;
+ struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
};
union cvmx_iob_outb_data_match {
struct cvmx_iob_outb_data_match_s cn56xxp1;
struct cvmx_iob_outb_data_match_s cn58xx;
struct cvmx_iob_outb_data_match_s cn58xxp1;
+ struct cvmx_iob_outb_data_match_s cn63xx;
+ struct cvmx_iob_outb_data_match_s cn63xxp1;
};
union cvmx_iob_outb_data_match_enb {
struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
struct cvmx_iob_outb_data_match_enb_s cn58xx;
struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+ struct cvmx_iob_outb_data_match_enb_s cn63xx;
+ struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
};
union cvmx_iob_outb_fpa_pri_cnt {
struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
};
union cvmx_iob_outb_req_pri_cnt {
struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
+ struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
};
union cvmx_iob_p2c_req_pri_cnt {
struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
+ struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
};
union cvmx_iob_pkt_err {
uint64_t u64;
struct cvmx_iob_pkt_err_s {
+ uint64_t reserved_12_63:52;
+ uint64_t vport:6;
+ uint64_t port:6;
+ } s;
+ struct cvmx_iob_pkt_err_cn30xx {
uint64_t reserved_6_63:58;
uint64_t port:6;
+ } cn30xx;
+ struct cvmx_iob_pkt_err_cn30xx cn31xx;
+ struct cvmx_iob_pkt_err_cn30xx cn38xx;
+ struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
+ struct cvmx_iob_pkt_err_cn30xx cn50xx;
+ struct cvmx_iob_pkt_err_cn30xx cn52xx;
+ struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
+ struct cvmx_iob_pkt_err_cn30xx cn56xx;
+ struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
+ struct cvmx_iob_pkt_err_cn30xx cn58xx;
+ struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
+ struct cvmx_iob_pkt_err_s cn63xx;
+ struct cvmx_iob_pkt_err_s cn63xxp1;
+};
+
+union cvmx_iob_to_cmb_credits {
+ uint64_t u64;
+ struct cvmx_iob_to_cmb_credits_s {
+ uint64_t reserved_9_63:55;
+ uint64_t pko_rd:3;
+ uint64_t ncb_rd:3;
+ uint64_t ncb_wr:3;
} s;
- struct cvmx_iob_pkt_err_s cn30xx;
- struct cvmx_iob_pkt_err_s cn31xx;
- struct cvmx_iob_pkt_err_s cn38xx;
- struct cvmx_iob_pkt_err_s cn38xxp2;
- struct cvmx_iob_pkt_err_s cn50xx;
- struct cvmx_iob_pkt_err_s cn52xx;
- struct cvmx_iob_pkt_err_s cn52xxp1;
- struct cvmx_iob_pkt_err_s cn56xx;
- struct cvmx_iob_pkt_err_s cn56xxp1;
- struct cvmx_iob_pkt_err_s cn58xx;
- struct cvmx_iob_pkt_err_s cn58xxp1;
+ struct cvmx_iob_to_cmb_credits_s cn52xx;
+ struct cvmx_iob_to_cmb_credits_s cn63xx;
+ struct cvmx_iob_to_cmb_credits_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_IPD_DEFS_H__
#define __CVMX_IPD_DEFS_H__
-#define CVMX_IPD_1ST_MBUFF_SKIP \
- CVMX_ADD_IO_SEG(0x00014F0000000000ull)
-#define CVMX_IPD_1st_NEXT_PTR_BACK \
- CVMX_ADD_IO_SEG(0x00014F0000000150ull)
-#define CVMX_IPD_2nd_NEXT_PTR_BACK \
- CVMX_ADD_IO_SEG(0x00014F0000000158ull)
-#define CVMX_IPD_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
-#define CVMX_IPD_BP_PRT_RED_END \
- CVMX_ADD_IO_SEG(0x00014F0000000328ull)
-#define CVMX_IPD_CLK_COUNT \
- CVMX_ADD_IO_SEG(0x00014F0000000338ull)
-#define CVMX_IPD_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00014F0000000018ull)
-#define CVMX_IPD_INT_ENB \
- CVMX_ADD_IO_SEG(0x00014F0000000160ull)
-#define CVMX_IPD_INT_SUM \
- CVMX_ADD_IO_SEG(0x00014F0000000168ull)
-#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
- CVMX_ADD_IO_SEG(0x00014F0000000008ull)
-#define CVMX_IPD_PACKET_MBUFF_SIZE \
- CVMX_ADD_IO_SEG(0x00014F0000000010ull)
-#define CVMX_IPD_PKT_PTR_VALID \
- CVMX_ADD_IO_SEG(0x00014F0000000358ull)
-#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
- CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORT_QOS_INTX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
-#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000348ull)
-#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000350ull)
-#define CVMX_IPD_PTR_COUNT \
- CVMX_ADD_IO_SEG(0x00014F0000000320ull)
-#define CVMX_IPD_PWP_PTR_FIFO_CTL \
- CVMX_ADD_IO_SEG(0x00014F0000000340ull)
-#define CVMX_IPD_QOS0_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000178ull)
-#define CVMX_IPD_QOS1_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000180ull)
-#define CVMX_IPD_QOS2_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000188ull)
-#define CVMX_IPD_QOS3_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000190ull)
-#define CVMX_IPD_QOS4_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F0000000198ull)
-#define CVMX_IPD_QOS5_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
-#define CVMX_IPD_QOS6_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
-#define CVMX_IPD_QOS7_RED_MARKS \
- CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
-#define CVMX_IPD_QOSX_RED_MARKS(offset) \
- CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
-#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000330ull)
-#define CVMX_IPD_RED_PORT_ENABLE \
- CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
-#define CVMX_IPD_RED_PORT_ENABLE2 \
- CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
-#define CVMX_IPD_RED_QUE0_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
-#define CVMX_IPD_RED_QUE1_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
-#define CVMX_IPD_RED_QUE2_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
-#define CVMX_IPD_RED_QUE3_PARAM \
- CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
-#define CVMX_IPD_RED_QUE4_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000300ull)
-#define CVMX_IPD_RED_QUE5_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000308ull)
-#define CVMX_IPD_RED_QUE6_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000310ull)
-#define CVMX_IPD_RED_QUE7_PARAM \
- CVMX_ADD_IO_SEG(0x00014F0000000318ull)
-#define CVMX_IPD_RED_QUEX_PARAM(offset) \
- CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
-#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000148ull)
-#define CVMX_IPD_SUB_PORT_FCS \
- CVMX_ADD_IO_SEG(0x00014F0000000170ull)
-#define CVMX_IPD_SUB_PORT_QOS_CNT \
- CVMX_ADD_IO_SEG(0x00014F0000000800ull)
-#define CVMX_IPD_WQE_FPA_QUEUE \
- CVMX_ADD_IO_SEG(0x00014F0000000020ull)
-#define CVMX_IPD_WQE_PTR_VALID \
- CVMX_ADD_IO_SEG(0x00014F0000000360ull)
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
union cvmx_ipd_1st_mbuff_skip {
uint64_t u64;
struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
+ struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
+ struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
};
union cvmx_ipd_1st_next_ptr_back {
struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
+ struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
+ struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
};
union cvmx_ipd_2nd_next_ptr_back {
struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
+ struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
};
union cvmx_ipd_bist_status {
struct cvmx_ipd_bist_status_s cn56xxp1;
struct cvmx_ipd_bist_status_cn30xx cn58xx;
struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
+ struct cvmx_ipd_bist_status_s cn63xx;
+ struct cvmx_ipd_bist_status_s cn63xxp1;
};
union cvmx_ipd_bp_prt_red_end {
uint64_t u64;
struct cvmx_ipd_bp_prt_red_end_s {
- uint64_t reserved_40_63:24;
- uint64_t prt_enb:40;
+ uint64_t reserved_44_63:20;
+ uint64_t prt_enb:44;
} s;
struct cvmx_ipd_bp_prt_red_end_cn30xx {
uint64_t reserved_36_63:28;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
- struct cvmx_ipd_bp_prt_red_end_s cn52xx;
- struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
- struct cvmx_ipd_bp_prt_red_end_s cn56xx;
- struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx {
+ uint64_t reserved_40_63:24;
+ uint64_t prt_enb:40;
+ } cn52xx;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
+ struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+ struct cvmx_ipd_bp_prt_red_end_s cn63xx;
+ struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
};
union cvmx_ipd_clk_count {
struct cvmx_ipd_clk_count_s cn56xxp1;
struct cvmx_ipd_clk_count_s cn58xx;
struct cvmx_ipd_clk_count_s cn58xxp1;
+ struct cvmx_ipd_clk_count_s cn63xx;
+ struct cvmx_ipd_clk_count_s cn63xxp1;
};
union cvmx_ipd_ctl_status {
uint64_t u64;
struct cvmx_ipd_ctl_status_s {
- uint64_t reserved_15_63:49;
+ uint64_t reserved_18_63:46;
+ uint64_t use_sop:1;
+ uint64_t rst_done:1;
+ uint64_t clken:1;
uint64_t no_wptr:1;
uint64_t pq_apkt:1;
uint64_t pq_nabuf:1;
uint64_t opc_mode:2;
uint64_t ipd_en:1;
} cn38xxp2;
- struct cvmx_ipd_ctl_status_s cn50xx;
- struct cvmx_ipd_ctl_status_s cn52xx;
- struct cvmx_ipd_ctl_status_s cn52xxp1;
- struct cvmx_ipd_ctl_status_s cn56xx;
- struct cvmx_ipd_ctl_status_s cn56xxp1;
+ struct cvmx_ipd_ctl_status_cn50xx {
+ uint64_t reserved_15_63:49;
+ uint64_t no_wptr:1;
+ uint64_t pq_apkt:1;
+ uint64_t pq_nabuf:1;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ uint64_t opc_mode:2;
+ uint64_t ipd_en:1;
+ } cn50xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn52xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
+ struct cvmx_ipd_ctl_status_cn50xx cn56xx;
+ struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
struct cvmx_ipd_ctl_status_cn58xx {
uint64_t reserved_12_63:52;
uint64_t ipd_full:1;
uint64_t ipd_en:1;
} cn58xx;
struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
+ struct cvmx_ipd_ctl_status_s cn63xx;
+ struct cvmx_ipd_ctl_status_cn63xxp1 {
+ uint64_t reserved_16_63:48;
+ uint64_t clken:1;
+ uint64_t no_wptr:1;
+ uint64_t pq_apkt:1;
+ uint64_t pq_nabuf:1;
+ uint64_t ipd_full:1;
+ uint64_t pkt_off:1;
+ uint64_t len_m8:1;
+ uint64_t reset:1;
+ uint64_t addpkt:1;
+ uint64_t naddbuf:1;
+ uint64_t pkt_lend:1;
+ uint64_t wqe_lend:1;
+ uint64_t pbp_en:1;
+ uint64_t opc_mode:2;
+ uint64_t ipd_en:1;
+ } cn63xxp1;
};
union cvmx_ipd_int_enb {
struct cvmx_ipd_int_enb_s cn56xxp1;
struct cvmx_ipd_int_enb_cn38xx cn58xx;
struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
+ struct cvmx_ipd_int_enb_s cn63xx;
+ struct cvmx_ipd_int_enb_s cn63xxp1;
};
union cvmx_ipd_int_sum {
struct cvmx_ipd_int_sum_s cn56xxp1;
struct cvmx_ipd_int_sum_cn38xx cn58xx;
struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
+ struct cvmx_ipd_int_sum_s cn63xx;
+ struct cvmx_ipd_int_sum_s cn63xxp1;
};
union cvmx_ipd_not_1st_mbuff_skip {
struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
+ struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
};
union cvmx_ipd_packet_mbuff_size {
struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
struct cvmx_ipd_packet_mbuff_size_s cn58xx;
struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
+ struct cvmx_ipd_packet_mbuff_size_s cn63xx;
+ struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
};
union cvmx_ipd_pkt_ptr_valid {
struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
+ struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
+ struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
};
union cvmx_ipd_portx_bp_page_cnt {
struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
};
union cvmx_ipd_portx_bp_page_cnt2 {
struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
+};
+
+union cvmx_ipd_portx_bp_page_cnt3 {
+ uint64_t u64;
+ struct cvmx_ipd_portx_bp_page_cnt3_s {
+ uint64_t reserved_18_63:46;
+ uint64_t bp_enb:1;
+ uint64_t page_cnt:17;
+ } s;
+ struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
+ struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
};
union cvmx_ipd_port_bp_counters2_pairx {
struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+};
+
+union cvmx_ipd_port_bp_counters3_pairx {
+ uint64_t u64;
+ struct cvmx_ipd_port_bp_counters3_pairx_s {
+ uint64_t reserved_25_63:39;
+ uint64_t cnt_val:25;
+ } s;
+ struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
};
union cvmx_ipd_port_bp_counters_pairx {
struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
+ struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
};
union cvmx_ipd_port_qos_x_cnt {
struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
+ struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
+ struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
};
union cvmx_ipd_port_qos_intx {
struct cvmx_ipd_port_qos_intx_s cn52xxp1;
struct cvmx_ipd_port_qos_intx_s cn56xx;
struct cvmx_ipd_port_qos_intx_s cn56xxp1;
+ struct cvmx_ipd_port_qos_intx_s cn63xx;
+ struct cvmx_ipd_port_qos_intx_s cn63xxp1;
};
union cvmx_ipd_port_qos_int_enbx {
struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
+ struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
+ struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
};
union cvmx_ipd_prc_hold_ptr_fifo_ctl {
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_prc_port_ptr_fifo_ctl {
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_ptr_count {
struct cvmx_ipd_ptr_count_s cn56xxp1;
struct cvmx_ipd_ptr_count_s cn58xx;
struct cvmx_ipd_ptr_count_s cn58xxp1;
+ struct cvmx_ipd_ptr_count_s cn63xx;
+ struct cvmx_ipd_ptr_count_s cn63xxp1;
};
union cvmx_ipd_pwp_ptr_fifo_ctl {
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
+ struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
};
union cvmx_ipd_qosx_red_marks {
struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
struct cvmx_ipd_qosx_red_marks_s cn58xx;
struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
+ struct cvmx_ipd_qosx_red_marks_s cn63xx;
+ struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
};
union cvmx_ipd_que0_free_page_cnt {
struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
+ struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
};
union cvmx_ipd_red_port_enable {
struct cvmx_ipd_red_port_enable_s cn56xxp1;
struct cvmx_ipd_red_port_enable_s cn58xx;
struct cvmx_ipd_red_port_enable_s cn58xxp1;
+ struct cvmx_ipd_red_port_enable_s cn63xx;
+ struct cvmx_ipd_red_port_enable_s cn63xxp1;
};
union cvmx_ipd_red_port_enable2 {
uint64_t u64;
struct cvmx_ipd_red_port_enable2_s {
+ uint64_t reserved_8_63:56;
+ uint64_t prt_enb:8;
+ } s;
+ struct cvmx_ipd_red_port_enable2_cn52xx {
uint64_t reserved_4_63:60;
uint64_t prt_enb:4;
- } s;
- struct cvmx_ipd_red_port_enable2_s cn52xx;
- struct cvmx_ipd_red_port_enable2_s cn52xxp1;
- struct cvmx_ipd_red_port_enable2_s cn56xx;
- struct cvmx_ipd_red_port_enable2_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
+ struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
+ struct cvmx_ipd_red_port_enable2_s cn63xx;
+ struct cvmx_ipd_red_port_enable2_s cn63xxp1;
};
union cvmx_ipd_red_quex_param {
struct cvmx_ipd_red_quex_param_s cn56xxp1;
struct cvmx_ipd_red_quex_param_s cn58xx;
struct cvmx_ipd_red_quex_param_s cn58xxp1;
+ struct cvmx_ipd_red_quex_param_s cn63xx;
+ struct cvmx_ipd_red_quex_param_s cn63xxp1;
};
union cvmx_ipd_sub_port_bp_page_cnt {
struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
+ struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
};
union cvmx_ipd_sub_port_fcs {
struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
+ struct cvmx_ipd_sub_port_fcs_s cn63xx;
+ struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
};
union cvmx_ipd_sub_port_qos_cnt {
struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
+ struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
};
union cvmx_ipd_wqe_fpa_queue {
struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
+ struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
+ struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
};
union cvmx_ipd_wqe_ptr_valid {
struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
+ struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
+ struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_L2C_DEFS_H__
#define __CVMX_L2C_DEFS_H__
-#define CVMX_L2C_BST0 \
- CVMX_ADD_IO_SEG(0x00011800800007F8ull)
-#define CVMX_L2C_BST1 \
- CVMX_ADD_IO_SEG(0x00011800800007F0ull)
-#define CVMX_L2C_BST2 \
- CVMX_ADD_IO_SEG(0x00011800800007E8ull)
-#define CVMX_L2C_CFG \
- CVMX_ADD_IO_SEG(0x0001180080000000ull)
-#define CVMX_L2C_DBG \
- CVMX_ADD_IO_SEG(0x0001180080000030ull)
-#define CVMX_L2C_DUT \
- CVMX_ADD_IO_SEG(0x0001180080000050ull)
-#define CVMX_L2C_GRPWRR0 \
- CVMX_ADD_IO_SEG(0x00011800800000C8ull)
-#define CVMX_L2C_GRPWRR1 \
- CVMX_ADD_IO_SEG(0x00011800800000D0ull)
-#define CVMX_L2C_INT_EN \
- CVMX_ADD_IO_SEG(0x0001180080000100ull)
-#define CVMX_L2C_INT_STAT \
- CVMX_ADD_IO_SEG(0x00011800800000F8ull)
-#define CVMX_L2C_LCKBASE \
- CVMX_ADD_IO_SEG(0x0001180080000058ull)
-#define CVMX_L2C_LCKOFF \
- CVMX_ADD_IO_SEG(0x0001180080000060ull)
-#define CVMX_L2C_LFB0 \
- CVMX_ADD_IO_SEG(0x0001180080000038ull)
-#define CVMX_L2C_LFB1 \
- CVMX_ADD_IO_SEG(0x0001180080000040ull)
-#define CVMX_L2C_LFB2 \
- CVMX_ADD_IO_SEG(0x0001180080000048ull)
-#define CVMX_L2C_LFB3 \
- CVMX_ADD_IO_SEG(0x00011800800000B8ull)
-#define CVMX_L2C_OOB \
- CVMX_ADD_IO_SEG(0x00011800800000D8ull)
-#define CVMX_L2C_OOB1 \
- CVMX_ADD_IO_SEG(0x00011800800000E0ull)
-#define CVMX_L2C_OOB2 \
- CVMX_ADD_IO_SEG(0x00011800800000E8ull)
-#define CVMX_L2C_OOB3 \
- CVMX_ADD_IO_SEG(0x00011800800000F0ull)
-#define CVMX_L2C_PFC0 \
- CVMX_ADD_IO_SEG(0x0001180080000098ull)
-#define CVMX_L2C_PFC1 \
- CVMX_ADD_IO_SEG(0x00011800800000A0ull)
-#define CVMX_L2C_PFC2 \
- CVMX_ADD_IO_SEG(0x00011800800000A8ull)
-#define CVMX_L2C_PFC3 \
- CVMX_ADD_IO_SEG(0x00011800800000B0ull)
-#define CVMX_L2C_PFCTL \
- CVMX_ADD_IO_SEG(0x0001180080000090ull)
-#define CVMX_L2C_PFCX(offset) \
- CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
-#define CVMX_L2C_PPGRP \
- CVMX_ADD_IO_SEG(0x00011800800000C0ull)
-#define CVMX_L2C_SPAR0 \
- CVMX_ADD_IO_SEG(0x0001180080000068ull)
-#define CVMX_L2C_SPAR1 \
- CVMX_ADD_IO_SEG(0x0001180080000070ull)
-#define CVMX_L2C_SPAR2 \
- CVMX_ADD_IO_SEG(0x0001180080000078ull)
-#define CVMX_L2C_SPAR3 \
- CVMX_ADD_IO_SEG(0x0001180080000080ull)
-#define CVMX_L2C_SPAR4 \
- CVMX_ADD_IO_SEG(0x0001180080000088ull)
+#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
+#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
+#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
+#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
+#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
+#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
+#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
+#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
+#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
+#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
+#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
+#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
+#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
+#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
+#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
+#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
+#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
+#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
+#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
+#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
+#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
+#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
+#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
+#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
+#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+
+union cvmx_l2c_big_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_big_ctl_s {
+ uint64_t reserved_8_63:56;
+ uint64_t maxdram:4;
+ uint64_t reserved_1_3:3;
+ uint64_t disable:1;
+ } s;
+ struct cvmx_l2c_big_ctl_s cn63xx;
+};
+
+union cvmx_l2c_bst {
+ uint64_t u64;
+ struct cvmx_l2c_bst_s {
+ uint64_t reserved_38_63:26;
+ uint64_t dutfl:6;
+ uint64_t reserved_17_31:15;
+ uint64_t ioccmdfl:1;
+ uint64_t reserved_13_15:3;
+ uint64_t iocdatfl:1;
+ uint64_t reserved_9_11:3;
+ uint64_t dutresfl:1;
+ uint64_t reserved_5_7:3;
+ uint64_t vrtfl:1;
+ uint64_t reserved_1_3:3;
+ uint64_t tdffl:1;
+ } s;
+ struct cvmx_l2c_bst_s cn63xx;
+ struct cvmx_l2c_bst_s cn63xxp1;
+};
union cvmx_l2c_bst0 {
uint64_t u64;
struct cvmx_l2c_bst2_cn56xx cn58xxp1;
};
+union cvmx_l2c_bst_memx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_memx_s {
+ uint64_t start_bist:1;
+ uint64_t clear_bist:1;
+ uint64_t reserved_5_61:57;
+ uint64_t rdffl:1;
+ uint64_t vbffl:4;
+ } s;
+ struct cvmx_l2c_bst_memx_s cn63xx;
+ struct cvmx_l2c_bst_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_bst_tdtx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_tdtx_s {
+ uint64_t reserved_32_63:32;
+ uint64_t fbfrspfl:8;
+ uint64_t sbffl:8;
+ uint64_t fbffl:8;
+ uint64_t l2dfl:8;
+ } s;
+ struct cvmx_l2c_bst_tdtx_s cn63xx;
+ struct cvmx_l2c_bst_tdtx_cn63xxp1 {
+ uint64_t reserved_24_63:40;
+ uint64_t sbffl:8;
+ uint64_t fbffl:8;
+ uint64_t l2dfl:8;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_bst_ttgx {
+ uint64_t u64;
+ struct cvmx_l2c_bst_ttgx_s {
+ uint64_t reserved_17_63:47;
+ uint64_t lrufl:1;
+ uint64_t tagfl:16;
+ } s;
+ struct cvmx_l2c_bst_ttgx_s cn63xx;
+ struct cvmx_l2c_bst_ttgx_s cn63xxp1;
+};
+
union cvmx_l2c_cfg {
uint64_t u64;
struct cvmx_l2c_cfg_s {
} cn58xxp1;
};
+union cvmx_l2c_cop0_mapx {
+ uint64_t u64;
+ struct cvmx_l2c_cop0_mapx_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_l2c_cop0_mapx_s cn63xx;
+ struct cvmx_l2c_cop0_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_ctl_s {
+ uint64_t reserved_28_63:36;
+ uint64_t disstgl2i:1;
+ uint64_t l2dfsbe:1;
+ uint64_t l2dfdbe:1;
+ uint64_t discclk:1;
+ uint64_t maxvab:4;
+ uint64_t maxlfb:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t xmc_arb_mode:1;
+ uint64_t ef_ena:1;
+ uint64_t ef_cnt:7;
+ uint64_t vab_thresh:4;
+ uint64_t disecc:1;
+ uint64_t disidxalias:1;
+ } s;
+ struct cvmx_l2c_ctl_s cn63xx;
+ struct cvmx_l2c_ctl_cn63xxp1 {
+ uint64_t reserved_25_63:39;
+ uint64_t discclk:1;
+ uint64_t maxvab:4;
+ uint64_t maxlfb:4;
+ uint64_t rsp_arb_mode:1;
+ uint64_t xmc_arb_mode:1;
+ uint64_t ef_ena:1;
+ uint64_t ef_cnt:7;
+ uint64_t vab_thresh:4;
+ uint64_t disecc:1;
+ uint64_t disidxalias:1;
+ } cn63xxp1;
+};
+
union cvmx_l2c_dbg {
uint64_t u64;
struct cvmx_l2c_dbg_s {
uint64_t reserved_13_63:51;
uint64_t lfb_enum:2;
uint64_t lfb_dmp:1;
- uint64_t reserved_5_9:5;
+ uint64_t reserved_7_9:3;
+ uint64_t ppnum:1;
+ uint64_t reserved_5_5:1;
uint64_t set:2;
uint64_t finv:1;
uint64_t l2d:1;
struct cvmx_l2c_dut_s cn58xxp1;
};
+union cvmx_l2c_dut_mapx {
+ uint64_t u64;
+ struct cvmx_l2c_dut_mapx_s {
+ uint64_t reserved_38_63:26;
+ uint64_t tag:28;
+ uint64_t reserved_1_9:9;
+ uint64_t valid:1;
+ } s;
+ struct cvmx_l2c_dut_mapx_s cn63xx;
+ struct cvmx_l2c_dut_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_tdtx {
+ uint64_t u64;
+ struct cvmx_l2c_err_tdtx_s {
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+ uint64_t vdbe:1;
+ uint64_t vsbe:1;
+ uint64_t syn:10;
+ uint64_t reserved_21_49:29;
+ uint64_t wayidx:17;
+ uint64_t reserved_2_3:2;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_tdtx_s cn63xx;
+ struct cvmx_l2c_err_tdtx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_ttgx {
+ uint64_t u64;
+ struct cvmx_l2c_err_ttgx_s {
+ uint64_t dbe:1;
+ uint64_t sbe:1;
+ uint64_t noway:1;
+ uint64_t reserved_56_60:5;
+ uint64_t syn:6;
+ uint64_t reserved_21_49:29;
+ uint64_t wayidx:14;
+ uint64_t reserved_2_6:5;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_ttgx_s cn63xx;
+ struct cvmx_l2c_err_ttgx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_vbfx {
+ uint64_t u64;
+ struct cvmx_l2c_err_vbfx_s {
+ uint64_t reserved_62_63:2;
+ uint64_t vdbe:1;
+ uint64_t vsbe:1;
+ uint64_t vsyn:10;
+ uint64_t reserved_2_49:48;
+ uint64_t type:2;
+ } s;
+ struct cvmx_l2c_err_vbfx_s cn63xx;
+ struct cvmx_l2c_err_vbfx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_xmc {
+ uint64_t u64;
+ struct cvmx_l2c_err_xmc_s {
+ uint64_t cmd:6;
+ uint64_t reserved_52_57:6;
+ uint64_t sid:4;
+ uint64_t reserved_38_47:10;
+ uint64_t addr:38;
+ } s;
+ struct cvmx_l2c_err_xmc_s cn63xx;
+ struct cvmx_l2c_err_xmc_s cn63xxp1;
+};
+
union cvmx_l2c_grpwrr0 {
uint64_t u64;
struct cvmx_l2c_grpwrr0_s {
struct cvmx_l2c_int_en_s cn56xxp1;
};
+union cvmx_l2c_int_ena {
+ uint64_t u64;
+ struct cvmx_l2c_int_ena_s {
+ uint64_t reserved_8_63:56;
+ uint64_t bigrd:1;
+ uint64_t bigwr:1;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } s;
+ struct cvmx_l2c_int_ena_s cn63xx;
+ struct cvmx_l2c_int_ena_cn63xxp1 {
+ uint64_t reserved_6_63:58;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_int_reg {
+ uint64_t u64;
+ struct cvmx_l2c_int_reg_s {
+ uint64_t reserved_17_63:47;
+ uint64_t tad0:1;
+ uint64_t reserved_8_15:8;
+ uint64_t bigrd:1;
+ uint64_t bigwr:1;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } s;
+ struct cvmx_l2c_int_reg_s cn63xx;
+ struct cvmx_l2c_int_reg_cn63xxp1 {
+ uint64_t reserved_17_63:47;
+ uint64_t tad0:1;
+ uint64_t reserved_6_15:10;
+ uint64_t vrtpe:1;
+ uint64_t vrtadrng:1;
+ uint64_t vrtidrng:1;
+ uint64_t vrtwr:1;
+ uint64_t holewr:1;
+ uint64_t holerd:1;
+ } cn63xxp1;
+};
+
union cvmx_l2c_int_stat {
uint64_t u64;
struct cvmx_l2c_int_stat_s {
struct cvmx_l2c_int_stat_s cn56xxp1;
};
+union cvmx_l2c_iocx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_iocx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_iocx_pfc_s cn63xx;
+ struct cvmx_l2c_iocx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_iorx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_iorx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_iorx_pfc_s cn63xx;
+ struct cvmx_l2c_iorx_pfc_s cn63xxp1;
+};
+
union cvmx_l2c_lckbase {
uint64_t u64;
struct cvmx_l2c_lckbase_s {
struct cvmx_l2c_ppgrp_s cn56xxp1;
};
+union cvmx_l2c_qos_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_qos_iobx_s {
+ uint64_t reserved_6_63:58;
+ uint64_t dwblvl:2;
+ uint64_t reserved_2_3:2;
+ uint64_t lvl:2;
+ } s;
+ struct cvmx_l2c_qos_iobx_s cn63xx;
+ struct cvmx_l2c_qos_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_qos_ppx_s {
+ uint64_t reserved_2_63:62;
+ uint64_t lvl:2;
+ } s;
+ struct cvmx_l2c_qos_ppx_s cn63xx;
+ struct cvmx_l2c_qos_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_wgt {
+ uint64_t u64;
+ struct cvmx_l2c_qos_wgt_s {
+ uint64_t reserved_32_63:32;
+ uint64_t wgt3:8;
+ uint64_t wgt2:8;
+ uint64_t wgt1:8;
+ uint64_t wgt0:8;
+ } s;
+ struct cvmx_l2c_qos_wgt_s cn63xx;
+ struct cvmx_l2c_qos_wgt_s cn63xxp1;
+};
+
+union cvmx_l2c_rscx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_rscx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_rscx_pfc_s cn63xx;
+ struct cvmx_l2c_rscx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_rsdx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_rsdx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_rsdx_pfc_s cn63xx;
+ struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
+};
+
union cvmx_l2c_spar0 {
uint64_t u64;
struct cvmx_l2c_spar0_s {
struct cvmx_l2c_spar4_s cn58xxp1;
};
+union cvmx_l2c_tadx_ecc0 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ecc0_s {
+ uint64_t reserved_58_63:6;
+ uint64_t ow3ecc:10;
+ uint64_t reserved_42_47:6;
+ uint64_t ow2ecc:10;
+ uint64_t reserved_26_31:6;
+ uint64_t ow1ecc:10;
+ uint64_t reserved_10_15:6;
+ uint64_t ow0ecc:10;
+ } s;
+ struct cvmx_l2c_tadx_ecc0_s cn63xx;
+ struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ecc1 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ecc1_s {
+ uint64_t reserved_58_63:6;
+ uint64_t ow7ecc:10;
+ uint64_t reserved_42_47:6;
+ uint64_t ow6ecc:10;
+ uint64_t reserved_26_31:6;
+ uint64_t ow5ecc:10;
+ uint64_t reserved_10_15:6;
+ uint64_t ow4ecc:10;
+ } s;
+ struct cvmx_l2c_tadx_ecc1_s cn63xx;
+ struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ien {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_ien_s {
+ uint64_t reserved_9_63:55;
+ uint64_t wrdislmc:1;
+ uint64_t rddislmc:1;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } s;
+ struct cvmx_l2c_tadx_ien_s cn63xx;
+ struct cvmx_l2c_tadx_ien_cn63xxp1 {
+ uint64_t reserved_7_63:57;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } cn63xxp1;
+};
+
+union cvmx_l2c_tadx_int {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_int_s {
+ uint64_t reserved_9_63:55;
+ uint64_t wrdislmc:1;
+ uint64_t rddislmc:1;
+ uint64_t noway:1;
+ uint64_t vbfdbe:1;
+ uint64_t vbfsbe:1;
+ uint64_t tagdbe:1;
+ uint64_t tagsbe:1;
+ uint64_t l2ddbe:1;
+ uint64_t l2dsbe:1;
+ } s;
+ struct cvmx_l2c_tadx_int_s cn63xx;
+};
+
+union cvmx_l2c_tadx_pfc0 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc0_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc0_s cn63xx;
+ struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc1 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc1_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc1_s cn63xx;
+ struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc2 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc2_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc2_s cn63xx;
+ struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc3 {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_pfc3_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_tadx_pfc3_s cn63xx;
+ struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_prf {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_prf_s {
+ uint64_t reserved_32_63:32;
+ uint64_t cnt3sel:8;
+ uint64_t cnt2sel:8;
+ uint64_t cnt1sel:8;
+ uint64_t cnt0sel:8;
+ } s;
+ struct cvmx_l2c_tadx_prf_s cn63xx;
+ struct cvmx_l2c_tadx_prf_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_tag {
+ uint64_t u64;
+ struct cvmx_l2c_tadx_tag_s {
+ uint64_t reserved_46_63:18;
+ uint64_t ecc:6;
+ uint64_t reserved_36_39:4;
+ uint64_t tag:19;
+ uint64_t reserved_4_16:13;
+ uint64_t use:1;
+ uint64_t valid:1;
+ uint64_t dirty:1;
+ uint64_t lock:1;
+ } s;
+ struct cvmx_l2c_tadx_tag_s cn63xx;
+ struct cvmx_l2c_tadx_tag_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_id {
+ uint64_t u64;
+ struct cvmx_l2c_ver_id_s {
+ uint64_t mask:64;
+ } s;
+ struct cvmx_l2c_ver_id_s cn63xx;
+ struct cvmx_l2c_ver_id_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_iob {
+ uint64_t u64;
+ struct cvmx_l2c_ver_iob_s {
+ uint64_t reserved_1_63:63;
+ uint64_t mask:1;
+ } s;
+ struct cvmx_l2c_ver_iob_s cn63xx;
+ struct cvmx_l2c_ver_iob_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_msc {
+ uint64_t u64;
+ struct cvmx_l2c_ver_msc_s {
+ uint64_t reserved_2_63:62;
+ uint64_t invl2:1;
+ uint64_t dwb:1;
+ } s;
+ struct cvmx_l2c_ver_msc_s cn63xx;
+};
+
+union cvmx_l2c_ver_pp {
+ uint64_t u64;
+ struct cvmx_l2c_ver_pp_s {
+ uint64_t reserved_6_63:58;
+ uint64_t mask:6;
+ } s;
+ struct cvmx_l2c_ver_pp_s cn63xx;
+ struct cvmx_l2c_ver_pp_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_virtid_iobx_s {
+ uint64_t reserved_14_63:50;
+ uint64_t dwbid:6;
+ uint64_t reserved_6_7:2;
+ uint64_t id:6;
+ } s;
+ struct cvmx_l2c_virtid_iobx_s cn63xx;
+ struct cvmx_l2c_virtid_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_virtid_ppx_s {
+ uint64_t reserved_6_63:58;
+ uint64_t id:6;
+ } s;
+ struct cvmx_l2c_virtid_ppx_s cn63xx;
+ struct cvmx_l2c_virtid_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_ctl {
+ uint64_t u64;
+ struct cvmx_l2c_vrt_ctl_s {
+ uint64_t reserved_9_63:55;
+ uint64_t ooberr:1;
+ uint64_t reserved_7_7:1;
+ uint64_t memsz:3;
+ uint64_t numid:3;
+ uint64_t enable:1;
+ } s;
+ struct cvmx_l2c_vrt_ctl_s cn63xx;
+ struct cvmx_l2c_vrt_ctl_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_memx {
+ uint64_t u64;
+ struct cvmx_l2c_vrt_memx_s {
+ uint64_t reserved_36_63:28;
+ uint64_t parity:4;
+ uint64_t data:32;
+ } s;
+ struct cvmx_l2c_vrt_memx_s cn63xx;
+ struct cvmx_l2c_vrt_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_iobx {
+ uint64_t u64;
+ struct cvmx_l2c_wpar_iobx_s {
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+ } s;
+ struct cvmx_l2c_wpar_iobx_s cn63xx;
+ struct cvmx_l2c_wpar_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_ppx {
+ uint64_t u64;
+ struct cvmx_l2c_wpar_ppx_s {
+ uint64_t reserved_16_63:48;
+ uint64_t mask:16;
+ } s;
+ struct cvmx_l2c_wpar_ppx_s cn63xx;
+ struct cvmx_l2c_wpar_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_xmcx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_xmcx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_xmcx_pfc_s cn63xx;
+ struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_xmc_cmd {
+ uint64_t u64;
+ struct cvmx_l2c_xmc_cmd_s {
+ uint64_t inuse:1;
+ uint64_t cmd:6;
+ uint64_t reserved_38_56:19;
+ uint64_t addr:38;
+ } s;
+ struct cvmx_l2c_xmc_cmd_s cn63xx;
+ struct cvmx_l2c_xmc_cmd_s cn63xxp1;
+};
+
+union cvmx_l2c_xmdx_pfc {
+ uint64_t u64;
+ struct cvmx_l2c_xmdx_pfc_s {
+ uint64_t count:64;
+ } s;
+ struct cvmx_l2c_xmdx_pfc_s cn63xx;
+ struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
+};
+
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
***********************license end**************************************/
/*
- *
* Interface to the Level 2 Cache (L2C) control, measurement, and debugging
* facilities.
*/
#ifndef __CVMX_L2C_H__
#define __CVMX_L2C_H__
-/* Deprecated macro, use function */
-#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
-
-/* Deprecated macro, use function */
-#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
+#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */
+#define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */
-/* Deprecated macro, use function */
-#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
/* Defines for index aliasing computations */
-#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
- (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
-#define CVMX_L2C_ALIAS_MASK \
- (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+/* Defines for Virtualizations, valid only from Octeon II onwards. */
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
+#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
union cvmx_l2c_tag {
uint64_t u64;
struct {
uint64_t reserved:28;
- uint64_t V:1; /* Line valid */
- uint64_t D:1; /* Line dirty */
- uint64_t L:1; /* Line locked */
- uint64_t U:1; /* Use, LRU eviction */
+ uint64_t V:1; /* Line valid */
+ uint64_t D:1; /* Line dirty */
+ uint64_t L:1; /* Line locked */
+ uint64_t U:1; /* Use, LRU eviction */
uint64_t addr:32; /* Phys mem (not all bits valid) */
} s;
};
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS 1
+
/* L2C Performance Counter events. */
enum cvmx_l2c_event {
- CVMX_L2C_EVENT_CYCLES = 0,
- CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
- CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
- CVMX_L2C_EVENT_DATA_MISS = 3,
- CVMX_L2C_EVENT_DATA_HIT = 4,
- CVMX_L2C_EVENT_MISS = 5,
- CVMX_L2C_EVENT_HIT = 6,
- CVMX_L2C_EVENT_VICTIM_HIT = 7,
- CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
- CVMX_L2C_EVENT_TAG_PROBE = 9,
- CVMX_L2C_EVENT_TAG_UPDATE = 10,
- CVMX_L2C_EVENT_TAG_COMPLETE = 11,
- CVMX_L2C_EVENT_TAG_DIRTY = 12,
- CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
- CVMX_L2C_EVENT_DATA_STORE_READ = 14,
+ CVMX_L2C_EVENT_CYCLES = 0,
+ CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
+ CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
+ CVMX_L2C_EVENT_DATA_MISS = 3,
+ CVMX_L2C_EVENT_DATA_HIT = 4,
+ CVMX_L2C_EVENT_MISS = 5,
+ CVMX_L2C_EVENT_HIT = 6,
+ CVMX_L2C_EVENT_VICTIM_HIT = 7,
+ CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
+ CVMX_L2C_EVENT_TAG_PROBE = 9,
+ CVMX_L2C_EVENT_TAG_UPDATE = 10,
+ CVMX_L2C_EVENT_TAG_COMPLETE = 11,
+ CVMX_L2C_EVENT_TAG_DIRTY = 12,
+ CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
+ CVMX_L2C_EVENT_DATA_STORE_READ = 14,
CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
- CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
- CVMX_L2C_EVENT_WRITE_REQUEST = 17,
- CVMX_L2C_EVENT_READ_REQUEST = 18,
+ CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
+ CVMX_L2C_EVENT_WRITE_REQUEST = 17,
+ CVMX_L2C_EVENT_READ_REQUEST = 18,
CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
- CVMX_L2C_EVENT_XMC_NOP = 20,
- CVMX_L2C_EVENT_XMC_LDT = 21,
- CVMX_L2C_EVENT_XMC_LDI = 22,
- CVMX_L2C_EVENT_XMC_LDD = 23,
- CVMX_L2C_EVENT_XMC_STF = 24,
- CVMX_L2C_EVENT_XMC_STT = 25,
- CVMX_L2C_EVENT_XMC_STP = 26,
- CVMX_L2C_EVENT_XMC_STC = 27,
- CVMX_L2C_EVENT_XMC_DWB = 28,
- CVMX_L2C_EVENT_XMC_PL2 = 29,
- CVMX_L2C_EVENT_XMC_PSL1 = 30,
- CVMX_L2C_EVENT_XMC_IOBLD = 31,
- CVMX_L2C_EVENT_XMC_IOBST = 32,
- CVMX_L2C_EVENT_XMC_IOBDMA = 33,
- CVMX_L2C_EVENT_XMC_IOBRSP = 34,
- CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
- CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
- CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
- CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
- CVMX_L2C_EVENT_RSC_NOP = 39,
- CVMX_L2C_EVENT_RSC_STDN = 40,
- CVMX_L2C_EVENT_RSC_FILL = 41,
- CVMX_L2C_EVENT_RSC_REFL = 42,
- CVMX_L2C_EVENT_RSC_STIN = 43,
- CVMX_L2C_EVENT_RSC_SCIN = 44,
- CVMX_L2C_EVENT_RSC_SCFL = 45,
- CVMX_L2C_EVENT_RSC_SCDN = 46,
- CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
- CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
- CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
- CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
- CVMX_L2C_EVENT_LRF_REQ = 51,
- CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
- CVMX_L2C_EVENT_DT_WR_INVAL = 53
+ CVMX_L2C_EVENT_XMC_NOP = 20,
+ CVMX_L2C_EVENT_XMC_LDT = 21,
+ CVMX_L2C_EVENT_XMC_LDI = 22,
+ CVMX_L2C_EVENT_XMC_LDD = 23,
+ CVMX_L2C_EVENT_XMC_STF = 24,
+ CVMX_L2C_EVENT_XMC_STT = 25,
+ CVMX_L2C_EVENT_XMC_STP = 26,
+ CVMX_L2C_EVENT_XMC_STC = 27,
+ CVMX_L2C_EVENT_XMC_DWB = 28,
+ CVMX_L2C_EVENT_XMC_PL2 = 29,
+ CVMX_L2C_EVENT_XMC_PSL1 = 30,
+ CVMX_L2C_EVENT_XMC_IOBLD = 31,
+ CVMX_L2C_EVENT_XMC_IOBST = 32,
+ CVMX_L2C_EVENT_XMC_IOBDMA = 33,
+ CVMX_L2C_EVENT_XMC_IOBRSP = 34,
+ CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
+ CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
+ CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
+ CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
+ CVMX_L2C_EVENT_RSC_NOP = 39,
+ CVMX_L2C_EVENT_RSC_STDN = 40,
+ CVMX_L2C_EVENT_RSC_FILL = 41,
+ CVMX_L2C_EVENT_RSC_REFL = 42,
+ CVMX_L2C_EVENT_RSC_STIN = 43,
+ CVMX_L2C_EVENT_RSC_SCIN = 44,
+ CVMX_L2C_EVENT_RSC_SCFL = 45,
+ CVMX_L2C_EVENT_RSC_SCDN = 46,
+ CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
+ CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
+ CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
+ CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
+ CVMX_L2C_EVENT_LRF_REQ = 51,
+ CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
+ CVMX_L2C_EVENT_DT_WR_INVAL = 53,
+ CVMX_L2C_EVENT_MAX
+};
+
+/* L2C Performance Counter events for Octeon2. */
+enum cvmx_l2c_tad_event {
+ CVMX_L2C_TAD_EVENT_NONE = 0,
+ CVMX_L2C_TAD_EVENT_TAG_HIT = 1,
+ CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
+ CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3,
+ CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4,
+ CVMX_L2C_TAD_EVENT_SC_FAIL = 5,
+ CVMX_L2C_TAD_EVENT_SC_PASS = 6,
+ CVMX_L2C_TAD_EVENT_LFB_VALID = 7,
+ CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8,
+ CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9,
+ CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128,
+ CVMX_L2C_TAD_EVENT_QUAD0_READ = 129,
+ CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130,
+ CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131,
+ CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144,
+ CVMX_L2C_TAD_EVENT_QUAD1_READ = 145,
+ CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146,
+ CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147,
+ CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160,
+ CVMX_L2C_TAD_EVENT_QUAD2_READ = 161,
+ CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162,
+ CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163,
+ CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176,
+ CVMX_L2C_TAD_EVENT_QUAD3_READ = 177,
+ CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178,
+ CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179,
+ CVMX_L2C_TAD_EVENT_MAX
};
/**
* @clear_on_read: When asserted, any read of the performance counter
* clears the counter.
*
- * The routine does not clear the counter.
+ * @note The routine does not clear the counter.
*/
-void cvmx_l2c_config_perf(uint32_t counter,
- enum cvmx_l2c_event event, uint32_t clear_on_read);
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
+
/**
* Read the given L2 Cache performance counter. The counter must be configured
* before reading, but this routine does not enforce this requirement.
/**
* Partitions the L2 cache for a core
*
- * @core: The core that the partitioning applies to.
+ * @core: The core that the partitioning applies to.
+ * @mask: The partitioning of the ways expressed as a binary
+ * mask. A 0 bit allows the core to evict cache lines from
+ * a way, while a 1 bit blocks the core from evicting any
+ * lines from that way. There must be at least one allowed
+ * way (0 bit) in the mask.
*
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- * bit allows the core to evict cache lines from a way, while a
- * 1 bit blocks the core from evicting any lines from that
- * way. There must be at least one allowed way (0 bit) in the
- * mask.
- *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them. All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ * those ways will never have any cache lines evicted from them.
+ * All cores and the hardware blocks are free to read from all
+ * ways regardless of the partitioning.
*/
int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
/**
* Partitions the L2 cache for the hardware blocks.
*
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- * bit allows the core to evict cache lines from a way, while a
- * 1 bit blocks the core from evicting any lines from that
- * way. There must be at least one allowed way (0 bit) in the
- * mask.
+ * @mask: The partitioning of the ways expressed as a binary
+ * mask. A 0 bit allows the core to evict cache lines from
+ * a way, while a 1 bit blocks the core from evicting any
+ * lines from that way. There must be at least one allowed
+ * way (0 bit) in the mask.
*
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them. All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ * those ways will never have any cache lines evicted from them.
+ * All cores and the hardware blocks are free to read from all
+ * ways regardless of the partitioning.
*/
int cvmx_l2c_set_hw_way_partition(uint32_t mask);
+
/**
* Locks a line in the L2 cache at the specified physical address
*
*/
union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
-/* Wrapper around deprecated old function name */
-static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
- uint32_t index)
+/* Wrapper providing a deprecated old function name */
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
{
return cvmx_l2c_get_tag(association, index);
}
+
/**
* Returns the cache index for a given physical address
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_L2D_DEFS_H__
#define __CVMX_L2D_DEFS_H__
-#define CVMX_L2D_BST0 \
- CVMX_ADD_IO_SEG(0x0001180080000780ull)
-#define CVMX_L2D_BST1 \
- CVMX_ADD_IO_SEG(0x0001180080000788ull)
-#define CVMX_L2D_BST2 \
- CVMX_ADD_IO_SEG(0x0001180080000790ull)
-#define CVMX_L2D_BST3 \
- CVMX_ADD_IO_SEG(0x0001180080000798ull)
-#define CVMX_L2D_ERR \
- CVMX_ADD_IO_SEG(0x0001180080000010ull)
-#define CVMX_L2D_FADR \
- CVMX_ADD_IO_SEG(0x0001180080000018ull)
-#define CVMX_L2D_FSYN0 \
- CVMX_ADD_IO_SEG(0x0001180080000020ull)
-#define CVMX_L2D_FSYN1 \
- CVMX_ADD_IO_SEG(0x0001180080000028ull)
-#define CVMX_L2D_FUS0 \
- CVMX_ADD_IO_SEG(0x00011800800007A0ull)
-#define CVMX_L2D_FUS1 \
- CVMX_ADD_IO_SEG(0x00011800800007A8ull)
-#define CVMX_L2D_FUS2 \
- CVMX_ADD_IO_SEG(0x00011800800007B0ull)
-#define CVMX_L2D_FUS3 \
- CVMX_ADD_IO_SEG(0x00011800800007B8ull)
+#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
+#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
+#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
+#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
+#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
+#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
+#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
+#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
+#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
+#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
+#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
union cvmx_l2d_bst0 {
uint64_t u64;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_L2T_DEFS_H__
#define __CVMX_L2T_DEFS_H__
-#define CVMX_L2T_ERR \
- CVMX_ADD_IO_SEG(0x0001180080000008ull)
+#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
union cvmx_l2t_err {
uint64_t u64;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_LED_DEFS_H__
#define __CVMX_LED_DEFS_H__
-#define CVMX_LED_BLINK \
- CVMX_ADD_IO_SEG(0x0001180000001A48ull)
-#define CVMX_LED_CLK_PHASE \
- CVMX_ADD_IO_SEG(0x0001180000001A08ull)
-#define CVMX_LED_CYLON \
- CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
-#define CVMX_LED_DBG \
- CVMX_ADD_IO_SEG(0x0001180000001A18ull)
-#define CVMX_LED_EN \
- CVMX_ADD_IO_SEG(0x0001180000001A00ull)
-#define CVMX_LED_POLARITY \
- CVMX_ADD_IO_SEG(0x0001180000001A50ull)
-#define CVMX_LED_PRT \
- CVMX_ADD_IO_SEG(0x0001180000001A10ull)
-#define CVMX_LED_PRT_FMT \
- CVMX_ADD_IO_SEG(0x0001180000001A30ull)
-#define CVMX_LED_PRT_STATUSX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
-#define CVMX_LED_UDD_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DATX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DAT_CLRX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
-#define CVMX_LED_UDD_DAT_SETX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
union cvmx_led_blink {
uint64_t u64;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_MIO_DEFS_H__
#define __CVMX_MIO_DEFS_H__
-#define CVMX_MIO_BOOT_BIST_STAT \
- CVMX_ADD_IO_SEG(0x00011800000000F8ull)
-#define CVMX_MIO_BOOT_COMP \
- CVMX_ADD_IO_SEG(0x00011800000000B8ull)
-#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_ERR \
- CVMX_ADD_IO_SEG(0x00011800000000A0ull)
-#define CVMX_MIO_BOOT_INT \
- CVMX_ADD_IO_SEG(0x00011800000000A8ull)
-#define CVMX_MIO_BOOT_LOC_ADR \
- CVMX_ADD_IO_SEG(0x0001180000000090ull)
-#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
-#define CVMX_MIO_BOOT_LOC_DAT \
- CVMX_ADD_IO_SEG(0x0001180000000098ull)
-#define CVMX_MIO_BOOT_PIN_DEFS \
- CVMX_ADD_IO_SEG(0x00011800000000C0ull)
-#define CVMX_MIO_BOOT_REG_CFGX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_REG_TIMX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_THR \
- CVMX_ADD_IO_SEG(0x00011800000000B0ull)
-#define CVMX_MIO_FUS_BNK_DATX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
-#define CVMX_MIO_FUS_DAT0 \
- CVMX_ADD_IO_SEG(0x0001180000001400ull)
-#define CVMX_MIO_FUS_DAT1 \
- CVMX_ADD_IO_SEG(0x0001180000001408ull)
-#define CVMX_MIO_FUS_DAT2 \
- CVMX_ADD_IO_SEG(0x0001180000001410ull)
-#define CVMX_MIO_FUS_DAT3 \
- CVMX_ADD_IO_SEG(0x0001180000001418ull)
-#define CVMX_MIO_FUS_EMA \
- CVMX_ADD_IO_SEG(0x0001180000001550ull)
-#define CVMX_MIO_FUS_PDF \
- CVMX_ADD_IO_SEG(0x0001180000001420ull)
-#define CVMX_MIO_FUS_PLL \
- CVMX_ADD_IO_SEG(0x0001180000001580ull)
-#define CVMX_MIO_FUS_PROG \
- CVMX_ADD_IO_SEG(0x0001180000001510ull)
-#define CVMX_MIO_FUS_PROG_TIMES \
- CVMX_ADD_IO_SEG(0x0001180000001518ull)
-#define CVMX_MIO_FUS_RCMD \
- CVMX_ADD_IO_SEG(0x0001180000001500ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_RES \
- CVMX_ADD_IO_SEG(0x0001180000001548ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
- CVMX_ADD_IO_SEG(0x0001180000001540ull)
-#define CVMX_MIO_FUS_UNLOCK \
- CVMX_ADD_IO_SEG(0x0001180000001578ull)
-#define CVMX_MIO_FUS_WADR \
- CVMX_ADD_IO_SEG(0x0001180000001508ull)
-#define CVMX_MIO_NDF_DMA_CFG \
- CVMX_ADD_IO_SEG(0x0001180000000168ull)
-#define CVMX_MIO_NDF_DMA_INT \
- CVMX_ADD_IO_SEG(0x0001180000000170ull)
-#define CVMX_MIO_NDF_DMA_INT_EN \
- CVMX_ADD_IO_SEG(0x0001180000000178ull)
-#define CVMX_MIO_PLL_CTL \
- CVMX_ADD_IO_SEG(0x0001180000001448ull)
-#define CVMX_MIO_PLL_SETTING \
- CVMX_ADD_IO_SEG(0x0001180000001440ull)
-#define CVMX_MIO_TWSX_INT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_TWSI_SW(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
-#define CVMX_MIO_UART2_DLH \
- CVMX_ADD_IO_SEG(0x0001180000000488ull)
-#define CVMX_MIO_UART2_DLL \
- CVMX_ADD_IO_SEG(0x0001180000000480ull)
-#define CVMX_MIO_UART2_FAR \
- CVMX_ADD_IO_SEG(0x0001180000000520ull)
-#define CVMX_MIO_UART2_FCR \
- CVMX_ADD_IO_SEG(0x0001180000000450ull)
-#define CVMX_MIO_UART2_HTX \
- CVMX_ADD_IO_SEG(0x0001180000000708ull)
-#define CVMX_MIO_UART2_IER \
- CVMX_ADD_IO_SEG(0x0001180000000408ull)
-#define CVMX_MIO_UART2_IIR \
- CVMX_ADD_IO_SEG(0x0001180000000410ull)
-#define CVMX_MIO_UART2_LCR \
- CVMX_ADD_IO_SEG(0x0001180000000418ull)
-#define CVMX_MIO_UART2_LSR \
- CVMX_ADD_IO_SEG(0x0001180000000428ull)
-#define CVMX_MIO_UART2_MCR \
- CVMX_ADD_IO_SEG(0x0001180000000420ull)
-#define CVMX_MIO_UART2_MSR \
- CVMX_ADD_IO_SEG(0x0001180000000430ull)
-#define CVMX_MIO_UART2_RBR \
- CVMX_ADD_IO_SEG(0x0001180000000400ull)
-#define CVMX_MIO_UART2_RFL \
- CVMX_ADD_IO_SEG(0x0001180000000608ull)
-#define CVMX_MIO_UART2_RFW \
- CVMX_ADD_IO_SEG(0x0001180000000530ull)
-#define CVMX_MIO_UART2_SBCR \
- CVMX_ADD_IO_SEG(0x0001180000000620ull)
-#define CVMX_MIO_UART2_SCR \
- CVMX_ADD_IO_SEG(0x0001180000000438ull)
-#define CVMX_MIO_UART2_SFE \
- CVMX_ADD_IO_SEG(0x0001180000000630ull)
-#define CVMX_MIO_UART2_SRR \
- CVMX_ADD_IO_SEG(0x0001180000000610ull)
-#define CVMX_MIO_UART2_SRT \
- CVMX_ADD_IO_SEG(0x0001180000000638ull)
-#define CVMX_MIO_UART2_SRTS \
- CVMX_ADD_IO_SEG(0x0001180000000618ull)
-#define CVMX_MIO_UART2_STT \
- CVMX_ADD_IO_SEG(0x0001180000000700ull)
-#define CVMX_MIO_UART2_TFL \
- CVMX_ADD_IO_SEG(0x0001180000000600ull)
-#define CVMX_MIO_UART2_TFR \
- CVMX_ADD_IO_SEG(0x0001180000000528ull)
-#define CVMX_MIO_UART2_THR \
- CVMX_ADD_IO_SEG(0x0001180000000440ull)
-#define CVMX_MIO_UART2_USR \
- CVMX_ADD_IO_SEG(0x0001180000000538ull)
-#define CVMX_MIO_UARTX_DLH(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_DLL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FAR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_HTX(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IER(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IIR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LSR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MSR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RBR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFW(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SBCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SCR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SFE(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRTS(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_STT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFL(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_THR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_USR(offset) \
- CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
union cvmx_mio_boot_bist_stat {
uint64_t u64;
struct cvmx_mio_boot_bist_stat_s {
- uint64_t reserved_2_63:62;
- uint64_t loc:1;
- uint64_t ncbi:1;
+ uint64_t reserved_0_63:64;
} s;
struct cvmx_mio_boot_bist_stat_cn30xx {
uint64_t reserved_4_63:60;
struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+ struct cvmx_mio_boot_bist_stat_cn63xx {
+ uint64_t reserved_9_63:55;
+ uint64_t stat:9;
+ } cn63xx;
+ struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
};
union cvmx_mio_boot_comp {
uint64_t u64;
struct cvmx_mio_boot_comp_s {
+ uint64_t reserved_0_63:64;
+ } s;
+ struct cvmx_mio_boot_comp_cn50xx {
uint64_t reserved_10_63:54;
uint64_t pctl:5;
uint64_t nctl:5;
- } s;
- struct cvmx_mio_boot_comp_s cn50xx;
- struct cvmx_mio_boot_comp_s cn52xx;
- struct cvmx_mio_boot_comp_s cn52xxp1;
- struct cvmx_mio_boot_comp_s cn56xx;
- struct cvmx_mio_boot_comp_s cn56xxp1;
+ } cn50xx;
+ struct cvmx_mio_boot_comp_cn50xx cn52xx;
+ struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
+ struct cvmx_mio_boot_comp_cn50xx cn56xx;
+ struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
+ struct cvmx_mio_boot_comp_cn63xx {
+ uint64_t reserved_12_63:52;
+ uint64_t pctl:6;
+ uint64_t nctl:6;
+ } cn63xx;
+ struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
};
union cvmx_mio_boot_dma_cfgx {
struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
struct cvmx_mio_boot_dma_cfgx_s cn56xx;
struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_cfgx_s cn63xx;
+ struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_dma_intx {
struct cvmx_mio_boot_dma_intx_s cn52xxp1;
struct cvmx_mio_boot_dma_intx_s cn56xx;
struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_intx_s cn63xx;
+ struct cvmx_mio_boot_dma_intx_s cn63xxp1;
};
union cvmx_mio_boot_dma_int_enx {
struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
struct cvmx_mio_boot_dma_int_enx_s cn56xx;
struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_int_enx_s cn63xx;
+ struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
};
union cvmx_mio_boot_dma_timx {
struct cvmx_mio_boot_dma_timx_s cn52xxp1;
struct cvmx_mio_boot_dma_timx_s cn56xx;
struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+ struct cvmx_mio_boot_dma_timx_s cn63xx;
+ struct cvmx_mio_boot_dma_timx_s cn63xxp1;
};
union cvmx_mio_boot_err {
struct cvmx_mio_boot_err_s cn56xxp1;
struct cvmx_mio_boot_err_s cn58xx;
struct cvmx_mio_boot_err_s cn58xxp1;
+ struct cvmx_mio_boot_err_s cn63xx;
+ struct cvmx_mio_boot_err_s cn63xxp1;
};
union cvmx_mio_boot_int {
struct cvmx_mio_boot_int_s cn56xxp1;
struct cvmx_mio_boot_int_s cn58xx;
struct cvmx_mio_boot_int_s cn58xxp1;
+ struct cvmx_mio_boot_int_s cn63xx;
+ struct cvmx_mio_boot_int_s cn63xxp1;
};
union cvmx_mio_boot_loc_adr {
struct cvmx_mio_boot_loc_adr_s cn56xxp1;
struct cvmx_mio_boot_loc_adr_s cn58xx;
struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+ struct cvmx_mio_boot_loc_adr_s cn63xx;
+ struct cvmx_mio_boot_loc_adr_s cn63xxp1;
};
union cvmx_mio_boot_loc_cfgx {
struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
struct cvmx_mio_boot_loc_cfgx_s cn58xx;
struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+ struct cvmx_mio_boot_loc_cfgx_s cn63xx;
+ struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_loc_dat {
struct cvmx_mio_boot_loc_dat_s cn56xxp1;
struct cvmx_mio_boot_loc_dat_s cn58xx;
struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+ struct cvmx_mio_boot_loc_dat_s cn63xx;
+ struct cvmx_mio_boot_loc_dat_s cn63xxp1;
};
union cvmx_mio_boot_pin_defs {
uint64_t term:2;
uint64_t reserved_0_8:9;
} cn56xx;
+ struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
+ struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
};
union cvmx_mio_boot_reg_cfgx {
struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+ struct cvmx_mio_boot_reg_cfgx_s cn63xx;
+ struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
};
union cvmx_mio_boot_reg_timx {
struct cvmx_mio_boot_reg_timx_s cn56xxp1;
struct cvmx_mio_boot_reg_timx_s cn58xx;
struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+ struct cvmx_mio_boot_reg_timx_s cn63xx;
+ struct cvmx_mio_boot_reg_timx_s cn63xxp1;
};
union cvmx_mio_boot_thr {
struct cvmx_mio_boot_thr_s cn56xxp1;
struct cvmx_mio_boot_thr_cn30xx cn58xx;
struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+ struct cvmx_mio_boot_thr_s cn63xx;
+ struct cvmx_mio_boot_thr_s cn63xxp1;
};
union cvmx_mio_fus_bnk_datx {
struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
struct cvmx_mio_fus_bnk_datx_s cn58xx;
struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+ struct cvmx_mio_fus_bnk_datx_s cn63xx;
+ struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
};
union cvmx_mio_fus_dat0 {
struct cvmx_mio_fus_dat0_s cn56xxp1;
struct cvmx_mio_fus_dat0_s cn58xx;
struct cvmx_mio_fus_dat0_s cn58xxp1;
+ struct cvmx_mio_fus_dat0_s cn63xx;
+ struct cvmx_mio_fus_dat0_s cn63xxp1;
};
union cvmx_mio_fus_dat1 {
struct cvmx_mio_fus_dat1_s cn56xxp1;
struct cvmx_mio_fus_dat1_s cn58xx;
struct cvmx_mio_fus_dat1_s cn58xxp1;
+ struct cvmx_mio_fus_dat1_s cn63xx;
+ struct cvmx_mio_fus_dat1_s cn63xxp1;
};
union cvmx_mio_fus_dat2 {
uint64_t u64;
struct cvmx_mio_fus_dat2_s {
- uint64_t reserved_34_63:30;
+ uint64_t reserved_35_63:29;
+ uint64_t dorm_crypto:1;
uint64_t fus318:1;
uint64_t raid_en:1;
uint64_t reserved_30_31:2;
uint64_t pp_dis:16;
} cn58xx;
struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+ struct cvmx_mio_fus_dat2_cn63xx {
+ uint64_t reserved_35_63:29;
+ uint64_t dorm_crypto:1;
+ uint64_t fus318:1;
+ uint64_t raid_en:1;
+ uint64_t reserved_29_31:3;
+ uint64_t nodfa_cp2:1;
+ uint64_t nomul:1;
+ uint64_t nocrypto:1;
+ uint64_t reserved_24_25:2;
+ uint64_t chip_id:8;
+ uint64_t reserved_6_15:10;
+ uint64_t pp_dis:6;
+ } cn63xx;
+ struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
};
union cvmx_mio_fus_dat3 {
uint64_t u64;
struct cvmx_mio_fus_dat3_s {
- uint64_t reserved_32_63:32;
+ uint64_t reserved_58_63:6;
+ uint64_t pll_ctl:10;
+ uint64_t dfa_info_dte:3;
+ uint64_t dfa_info_clm:4;
+ uint64_t reserved_40_40:1;
+ uint64_t ema:2;
+ uint64_t efus_lck_rsv:1;
+ uint64_t efus_lck_man:1;
+ uint64_t pll_half_dis:1;
+ uint64_t l2c_crip:3;
uint64_t pll_div4:1;
- uint64_t zip_crip:2;
+ uint64_t reserved_29_30:2;
uint64_t bar2_en:1;
uint64_t efus_lck:1;
uint64_t efus_ign:1;
uint64_t nodfa_dte:1;
uint64_t icache:24;
} cn30xx;
- struct cvmx_mio_fus_dat3_s cn31xx;
+ struct cvmx_mio_fus_dat3_cn31xx {
+ uint64_t reserved_32_63:32;
+ uint64_t pll_div4:1;
+ uint64_t zip_crip:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t icache:24;
+ } cn31xx;
struct cvmx_mio_fus_dat3_cn38xx {
uint64_t reserved_31_63:33;
uint64_t zip_crip:2;
struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
struct cvmx_mio_fus_dat3_cn38xx cn58xx;
struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
+ struct cvmx_mio_fus_dat3_cn63xx {
+ uint64_t reserved_58_63:6;
+ uint64_t pll_ctl:10;
+ uint64_t dfa_info_dte:3;
+ uint64_t dfa_info_clm:4;
+ uint64_t reserved_40_40:1;
+ uint64_t ema:2;
+ uint64_t efus_lck_rsv:1;
+ uint64_t efus_lck_man:1;
+ uint64_t pll_half_dis:1;
+ uint64_t l2c_crip:3;
+ uint64_t reserved_31_31:1;
+ uint64_t zip_info:2;
+ uint64_t bar2_en:1;
+ uint64_t efus_lck:1;
+ uint64_t efus_ign:1;
+ uint64_t nozip:1;
+ uint64_t nodfa_dte:1;
+ uint64_t reserved_0_23:24;
+ } cn63xx;
+ struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
};
union cvmx_mio_fus_ema {
uint64_t ema:2;
} cn58xx;
struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+ struct cvmx_mio_fus_ema_s cn63xx;
+ struct cvmx_mio_fus_ema_s cn63xxp1;
};
union cvmx_mio_fus_pdf {
struct cvmx_mio_fus_pdf_s cn56xx;
struct cvmx_mio_fus_pdf_s cn56xxp1;
struct cvmx_mio_fus_pdf_s cn58xx;
+ struct cvmx_mio_fus_pdf_s cn63xx;
+ struct cvmx_mio_fus_pdf_s cn63xxp1;
};
union cvmx_mio_fus_pll {
uint64_t u64;
struct cvmx_mio_fus_pll_s {
- uint64_t reserved_2_63:62;
+ uint64_t reserved_8_63:56;
+ uint64_t c_cout_rst:1;
+ uint64_t c_cout_sel:2;
+ uint64_t pnr_cout_rst:1;
+ uint64_t pnr_cout_sel:2;
uint64_t rfslip:1;
uint64_t fbslip:1;
} s;
- struct cvmx_mio_fus_pll_s cn50xx;
- struct cvmx_mio_fus_pll_s cn52xx;
- struct cvmx_mio_fus_pll_s cn52xxp1;
- struct cvmx_mio_fus_pll_s cn56xx;
- struct cvmx_mio_fus_pll_s cn56xxp1;
- struct cvmx_mio_fus_pll_s cn58xx;
- struct cvmx_mio_fus_pll_s cn58xxp1;
+ struct cvmx_mio_fus_pll_cn50xx {
+ uint64_t reserved_2_63:62;
+ uint64_t rfslip:1;
+ uint64_t fbslip:1;
+ } cn50xx;
+ struct cvmx_mio_fus_pll_cn50xx cn52xx;
+ struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
+ struct cvmx_mio_fus_pll_cn50xx cn56xx;
+ struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
+ struct cvmx_mio_fus_pll_cn50xx cn58xx;
+ struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_pll_s cn63xx;
+ struct cvmx_mio_fus_pll_s cn63xxp1;
};
union cvmx_mio_fus_prog {
uint64_t u64;
struct cvmx_mio_fus_prog_s {
- uint64_t reserved_1_63:63;
+ uint64_t reserved_2_63:62;
+ uint64_t soft:1;
uint64_t prog:1;
} s;
- struct cvmx_mio_fus_prog_s cn30xx;
- struct cvmx_mio_fus_prog_s cn31xx;
- struct cvmx_mio_fus_prog_s cn38xx;
- struct cvmx_mio_fus_prog_s cn38xxp2;
- struct cvmx_mio_fus_prog_s cn50xx;
- struct cvmx_mio_fus_prog_s cn52xx;
- struct cvmx_mio_fus_prog_s cn52xxp1;
- struct cvmx_mio_fus_prog_s cn56xx;
- struct cvmx_mio_fus_prog_s cn56xxp1;
- struct cvmx_mio_fus_prog_s cn58xx;
- struct cvmx_mio_fus_prog_s cn58xxp1;
+ struct cvmx_mio_fus_prog_cn30xx {
+ uint64_t reserved_1_63:63;
+ uint64_t prog:1;
+ } cn30xx;
+ struct cvmx_mio_fus_prog_cn30xx cn31xx;
+ struct cvmx_mio_fus_prog_cn30xx cn38xx;
+ struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
+ struct cvmx_mio_fus_prog_cn30xx cn50xx;
+ struct cvmx_mio_fus_prog_cn30xx cn52xx;
+ struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
+ struct cvmx_mio_fus_prog_cn30xx cn56xx;
+ struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
+ struct cvmx_mio_fus_prog_cn30xx cn58xx;
+ struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+ struct cvmx_mio_fus_prog_s cn63xx;
+ struct cvmx_mio_fus_prog_s cn63xxp1;
};
union cvmx_mio_fus_prog_times {
uint64_t u64;
struct cvmx_mio_fus_prog_times_s {
+ uint64_t reserved_35_63:29;
+ uint64_t vgate_pin:1;
+ uint64_t fsrc_pin:1;
+ uint64_t prog_pin:1;
+ uint64_t reserved_6_31:26;
+ uint64_t setup:6;
+ } s;
+ struct cvmx_mio_fus_prog_times_cn50xx {
uint64_t reserved_33_63:31;
uint64_t prog_pin:1;
uint64_t out:8;
uint64_t sclk_lo:4;
uint64_t sclk_hi:12;
uint64_t setup:8;
- } s;
- struct cvmx_mio_fus_prog_times_s cn50xx;
- struct cvmx_mio_fus_prog_times_s cn52xx;
- struct cvmx_mio_fus_prog_times_s cn52xxp1;
- struct cvmx_mio_fus_prog_times_s cn56xx;
- struct cvmx_mio_fus_prog_times_s cn56xxp1;
- struct cvmx_mio_fus_prog_times_s cn58xx;
- struct cvmx_mio_fus_prog_times_s cn58xxp1;
+ } cn50xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
+ struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
+ struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
+ struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_prog_times_cn63xx {
+ uint64_t reserved_35_63:29;
+ uint64_t vgate_pin:1;
+ uint64_t fsrc_pin:1;
+ uint64_t prog_pin:1;
+ uint64_t out:7;
+ uint64_t sclk_lo:4;
+ uint64_t sclk_hi:15;
+ uint64_t setup:6;
+ } cn63xx;
+ struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
};
union cvmx_mio_fus_rcmd {
struct cvmx_mio_fus_rcmd_s cn56xxp1;
struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+ struct cvmx_mio_fus_rcmd_s cn63xx;
+ struct cvmx_mio_fus_rcmd_s cn63xxp1;
+};
+
+union cvmx_mio_fus_read_times {
+ uint64_t u64;
+ struct cvmx_mio_fus_read_times_s {
+ uint64_t reserved_26_63:38;
+ uint64_t sch:4;
+ uint64_t fsh:4;
+ uint64_t prh:4;
+ uint64_t sdh:4;
+ uint64_t setup:10;
+ } s;
+ struct cvmx_mio_fus_read_times_s cn63xx;
+ struct cvmx_mio_fus_read_times_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res0 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res0_s {
+ uint64_t reserved_55_63:9;
+ uint64_t too_many:1;
+ uint64_t repair2:18;
+ uint64_t repair1:18;
+ uint64_t repair0:18;
+ } s;
+ struct cvmx_mio_fus_repair_res0_s cn63xx;
+ struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res1 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res1_s {
+ uint64_t reserved_54_63:10;
+ uint64_t repair5:18;
+ uint64_t repair4:18;
+ uint64_t repair3:18;
+ } s;
+ struct cvmx_mio_fus_repair_res1_s cn63xx;
+ struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res2 {
+ uint64_t u64;
+ struct cvmx_mio_fus_repair_res2_s {
+ uint64_t reserved_18_63:46;
+ uint64_t repair6:18;
+ } s;
+ struct cvmx_mio_fus_repair_res2_s cn63xx;
+ struct cvmx_mio_fus_repair_res2_s cn63xxp1;
};
union cvmx_mio_fus_spr_repair_res {
struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
struct cvmx_mio_fus_spr_repair_res_s cn58xx;
struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+ struct cvmx_mio_fus_spr_repair_res_s cn63xx;
+ struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
};
union cvmx_mio_fus_spr_repair_sum {
struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+ struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
+ struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
};
union cvmx_mio_fus_unlock {
struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
struct cvmx_mio_fus_wadr_cn50xx cn58xx;
struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
+ struct cvmx_mio_fus_wadr_cn63xx {
+ uint64_t reserved_4_63:60;
+ uint64_t addr:4;
+ } cn63xx;
+ struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+};
+
+union cvmx_mio_gpio_comp {
+ uint64_t u64;
+ struct cvmx_mio_gpio_comp_s {
+ uint64_t reserved_12_63:52;
+ uint64_t pctl:6;
+ uint64_t nctl:6;
+ } s;
+ struct cvmx_mio_gpio_comp_s cn63xx;
+ struct cvmx_mio_gpio_comp_s cn63xxp1;
};
union cvmx_mio_ndf_dma_cfg {
uint64_t adr:36;
} s;
struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+ struct cvmx_mio_ndf_dma_cfg_s cn63xx;
+ struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
};
union cvmx_mio_ndf_dma_int {
uint64_t done:1;
} s;
struct cvmx_mio_ndf_dma_int_s cn52xx;
+ struct cvmx_mio_ndf_dma_int_s cn63xx;
+ struct cvmx_mio_ndf_dma_int_s cn63xxp1;
};
union cvmx_mio_ndf_dma_int_en {
uint64_t done:1;
} s;
struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+ struct cvmx_mio_ndf_dma_int_en_s cn63xx;
+ struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
};
union cvmx_mio_pll_ctl {
struct cvmx_mio_pll_setting_s cn31xx;
};
+union cvmx_mio_ptp_clock_cfg {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_cfg_s {
+ uint64_t reserved_24_63:40;
+ uint64_t evcnt_in:6;
+ uint64_t evcnt_edge:1;
+ uint64_t evcnt_en:1;
+ uint64_t tstmp_in:6;
+ uint64_t tstmp_edge:1;
+ uint64_t tstmp_en:1;
+ uint64_t ext_clk_in:6;
+ uint64_t ext_clk_en:1;
+ uint64_t ptp_en:1;
+ } s;
+ struct cvmx_mio_ptp_clock_cfg_s cn63xx;
+ struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_comp {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_comp_s {
+ uint64_t nanosec:32;
+ uint64_t frnanosec:32;
+ } s;
+ struct cvmx_mio_ptp_clock_comp_s cn63xx;
+ struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_hi {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_hi_s {
+ uint64_t nanosec:64;
+ } s;
+ struct cvmx_mio_ptp_clock_hi_s cn63xx;
+ struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_lo {
+ uint64_t u64;
+ struct cvmx_mio_ptp_clock_lo_s {
+ uint64_t reserved_32_63:32;
+ uint64_t frnanosec:32;
+ } s;
+ struct cvmx_mio_ptp_clock_lo_s cn63xx;
+ struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_evt_cnt {
+ uint64_t u64;
+ struct cvmx_mio_ptp_evt_cnt_s {
+ uint64_t cntr:64;
+ } s;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xx;
+ struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_timestamp {
+ uint64_t u64;
+ struct cvmx_mio_ptp_timestamp_s {
+ uint64_t nanosec:64;
+ } s;
+ struct cvmx_mio_ptp_timestamp_s cn63xx;
+ struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+};
+
+union cvmx_mio_rst_boot {
+ uint64_t u64;
+ struct cvmx_mio_rst_boot_s {
+ uint64_t reserved_36_63:28;
+ uint64_t c_mul:6;
+ uint64_t pnr_mul:6;
+ uint64_t qlm2_spd:4;
+ uint64_t qlm1_spd:4;
+ uint64_t qlm0_spd:4;
+ uint64_t lboot:10;
+ uint64_t rboot:1;
+ uint64_t rboot_pin:1;
+ } s;
+ struct cvmx_mio_rst_boot_s cn63xx;
+ struct cvmx_mio_rst_boot_s cn63xxp1;
+};
+
+union cvmx_mio_rst_cfg {
+ uint64_t u64;
+ struct cvmx_mio_rst_cfg_s {
+ uint64_t bist_delay:58;
+ uint64_t reserved_3_5:3;
+ uint64_t cntl_clr_bist:1;
+ uint64_t warm_clr_bist:1;
+ uint64_t soft_clr_bist:1;
+ } s;
+ struct cvmx_mio_rst_cfg_s cn63xx;
+ struct cvmx_mio_rst_cfg_cn63xxp1 {
+ uint64_t bist_delay:58;
+ uint64_t reserved_2_5:4;
+ uint64_t warm_clr_bist:1;
+ uint64_t soft_clr_bist:1;
+ } cn63xxp1;
+};
+
+union cvmx_mio_rst_ctlx {
+ uint64_t u64;
+ struct cvmx_mio_rst_ctlx_s {
+ uint64_t reserved_10_63:54;
+ uint64_t prst_link:1;
+ uint64_t rst_done:1;
+ uint64_t rst_link:1;
+ uint64_t host_mode:1;
+ uint64_t prtmode:2;
+ uint64_t rst_drv:1;
+ uint64_t rst_rcv:1;
+ uint64_t rst_chip:1;
+ uint64_t rst_val:1;
+ } s;
+ struct cvmx_mio_rst_ctlx_s cn63xx;
+ struct cvmx_mio_rst_ctlx_cn63xxp1 {
+ uint64_t reserved_9_63:55;
+ uint64_t rst_done:1;
+ uint64_t rst_link:1;
+ uint64_t host_mode:1;
+ uint64_t prtmode:2;
+ uint64_t rst_drv:1;
+ uint64_t rst_rcv:1;
+ uint64_t rst_chip:1;
+ uint64_t rst_val:1;
+ } cn63xxp1;
+};
+
+union cvmx_mio_rst_delay {
+ uint64_t u64;
+ struct cvmx_mio_rst_delay_s {
+ uint64_t reserved_32_63:32;
+ uint64_t soft_rst_dly:16;
+ uint64_t warm_rst_dly:16;
+ } s;
+ struct cvmx_mio_rst_delay_s cn63xx;
+ struct cvmx_mio_rst_delay_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int {
+ uint64_t u64;
+ struct cvmx_mio_rst_int_s {
+ uint64_t reserved_10_63:54;
+ uint64_t perst1:1;
+ uint64_t perst0:1;
+ uint64_t reserved_2_7:6;
+ uint64_t rst_link1:1;
+ uint64_t rst_link0:1;
+ } s;
+ struct cvmx_mio_rst_int_s cn63xx;
+ struct cvmx_mio_rst_int_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int_en {
+ uint64_t u64;
+ struct cvmx_mio_rst_int_en_s {
+ uint64_t reserved_10_63:54;
+ uint64_t perst1:1;
+ uint64_t perst0:1;
+ uint64_t reserved_2_7:6;
+ uint64_t rst_link1:1;
+ uint64_t rst_link0:1;
+ } s;
+ struct cvmx_mio_rst_int_en_s cn63xx;
+ struct cvmx_mio_rst_int_en_s cn63xxp1;
+};
+
union cvmx_mio_twsx_int {
uint64_t u64;
struct cvmx_mio_twsx_int_s {
struct cvmx_mio_twsx_int_s cn56xxp1;
struct cvmx_mio_twsx_int_s cn58xx;
struct cvmx_mio_twsx_int_s cn58xxp1;
+ struct cvmx_mio_twsx_int_s cn63xx;
+ struct cvmx_mio_twsx_int_s cn63xxp1;
};
union cvmx_mio_twsx_sw_twsi {
struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
struct cvmx_mio_twsx_sw_twsi_s cn58xx;
struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+ struct cvmx_mio_twsx_sw_twsi_s cn63xx;
+ struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
};
union cvmx_mio_twsx_sw_twsi_ext {
struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
+ struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
};
union cvmx_mio_twsx_twsi_sw {
struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
struct cvmx_mio_twsx_twsi_sw_s cn58xx;
struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+ struct cvmx_mio_twsx_twsi_sw_s cn63xx;
+ struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
};
union cvmx_mio_uartx_dlh {
struct cvmx_mio_uartx_dlh_s cn56xxp1;
struct cvmx_mio_uartx_dlh_s cn58xx;
struct cvmx_mio_uartx_dlh_s cn58xxp1;
+ struct cvmx_mio_uartx_dlh_s cn63xx;
+ struct cvmx_mio_uartx_dlh_s cn63xxp1;
};
union cvmx_mio_uartx_dll {
struct cvmx_mio_uartx_dll_s cn56xxp1;
struct cvmx_mio_uartx_dll_s cn58xx;
struct cvmx_mio_uartx_dll_s cn58xxp1;
+ struct cvmx_mio_uartx_dll_s cn63xx;
+ struct cvmx_mio_uartx_dll_s cn63xxp1;
};
union cvmx_mio_uartx_far {
struct cvmx_mio_uartx_far_s cn56xxp1;
struct cvmx_mio_uartx_far_s cn58xx;
struct cvmx_mio_uartx_far_s cn58xxp1;
+ struct cvmx_mio_uartx_far_s cn63xx;
+ struct cvmx_mio_uartx_far_s cn63xxp1;
};
union cvmx_mio_uartx_fcr {
struct cvmx_mio_uartx_fcr_s cn56xxp1;
struct cvmx_mio_uartx_fcr_s cn58xx;
struct cvmx_mio_uartx_fcr_s cn58xxp1;
+ struct cvmx_mio_uartx_fcr_s cn63xx;
+ struct cvmx_mio_uartx_fcr_s cn63xxp1;
};
union cvmx_mio_uartx_htx {
struct cvmx_mio_uartx_htx_s cn56xxp1;
struct cvmx_mio_uartx_htx_s cn58xx;
struct cvmx_mio_uartx_htx_s cn58xxp1;
+ struct cvmx_mio_uartx_htx_s cn63xx;
+ struct cvmx_mio_uartx_htx_s cn63xxp1;
};
union cvmx_mio_uartx_ier {
struct cvmx_mio_uartx_ier_s cn56xxp1;
struct cvmx_mio_uartx_ier_s cn58xx;
struct cvmx_mio_uartx_ier_s cn58xxp1;
+ struct cvmx_mio_uartx_ier_s cn63xx;
+ struct cvmx_mio_uartx_ier_s cn63xxp1;
};
union cvmx_mio_uartx_iir {
struct cvmx_mio_uartx_iir_s cn56xxp1;
struct cvmx_mio_uartx_iir_s cn58xx;
struct cvmx_mio_uartx_iir_s cn58xxp1;
+ struct cvmx_mio_uartx_iir_s cn63xx;
+ struct cvmx_mio_uartx_iir_s cn63xxp1;
};
union cvmx_mio_uartx_lcr {
struct cvmx_mio_uartx_lcr_s cn56xxp1;
struct cvmx_mio_uartx_lcr_s cn58xx;
struct cvmx_mio_uartx_lcr_s cn58xxp1;
+ struct cvmx_mio_uartx_lcr_s cn63xx;
+ struct cvmx_mio_uartx_lcr_s cn63xxp1;
};
union cvmx_mio_uartx_lsr {
struct cvmx_mio_uartx_lsr_s cn56xxp1;
struct cvmx_mio_uartx_lsr_s cn58xx;
struct cvmx_mio_uartx_lsr_s cn58xxp1;
+ struct cvmx_mio_uartx_lsr_s cn63xx;
+ struct cvmx_mio_uartx_lsr_s cn63xxp1;
};
union cvmx_mio_uartx_mcr {
struct cvmx_mio_uartx_mcr_s cn56xxp1;
struct cvmx_mio_uartx_mcr_s cn58xx;
struct cvmx_mio_uartx_mcr_s cn58xxp1;
+ struct cvmx_mio_uartx_mcr_s cn63xx;
+ struct cvmx_mio_uartx_mcr_s cn63xxp1;
};
union cvmx_mio_uartx_msr {
struct cvmx_mio_uartx_msr_s cn56xxp1;
struct cvmx_mio_uartx_msr_s cn58xx;
struct cvmx_mio_uartx_msr_s cn58xxp1;
+ struct cvmx_mio_uartx_msr_s cn63xx;
+ struct cvmx_mio_uartx_msr_s cn63xxp1;
};
union cvmx_mio_uartx_rbr {
struct cvmx_mio_uartx_rbr_s cn56xxp1;
struct cvmx_mio_uartx_rbr_s cn58xx;
struct cvmx_mio_uartx_rbr_s cn58xxp1;
+ struct cvmx_mio_uartx_rbr_s cn63xx;
+ struct cvmx_mio_uartx_rbr_s cn63xxp1;
};
union cvmx_mio_uartx_rfl {
struct cvmx_mio_uartx_rfl_s cn56xxp1;
struct cvmx_mio_uartx_rfl_s cn58xx;
struct cvmx_mio_uartx_rfl_s cn58xxp1;
+ struct cvmx_mio_uartx_rfl_s cn63xx;
+ struct cvmx_mio_uartx_rfl_s cn63xxp1;
};
union cvmx_mio_uartx_rfw {
struct cvmx_mio_uartx_rfw_s cn56xxp1;
struct cvmx_mio_uartx_rfw_s cn58xx;
struct cvmx_mio_uartx_rfw_s cn58xxp1;
+ struct cvmx_mio_uartx_rfw_s cn63xx;
+ struct cvmx_mio_uartx_rfw_s cn63xxp1;
};
union cvmx_mio_uartx_sbcr {
struct cvmx_mio_uartx_sbcr_s cn56xxp1;
struct cvmx_mio_uartx_sbcr_s cn58xx;
struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+ struct cvmx_mio_uartx_sbcr_s cn63xx;
+ struct cvmx_mio_uartx_sbcr_s cn63xxp1;
};
union cvmx_mio_uartx_scr {
struct cvmx_mio_uartx_scr_s cn56xxp1;
struct cvmx_mio_uartx_scr_s cn58xx;
struct cvmx_mio_uartx_scr_s cn58xxp1;
+ struct cvmx_mio_uartx_scr_s cn63xx;
+ struct cvmx_mio_uartx_scr_s cn63xxp1;
};
union cvmx_mio_uartx_sfe {
struct cvmx_mio_uartx_sfe_s cn56xxp1;
struct cvmx_mio_uartx_sfe_s cn58xx;
struct cvmx_mio_uartx_sfe_s cn58xxp1;
+ struct cvmx_mio_uartx_sfe_s cn63xx;
+ struct cvmx_mio_uartx_sfe_s cn63xxp1;
};
union cvmx_mio_uartx_srr {
struct cvmx_mio_uartx_srr_s cn56xxp1;
struct cvmx_mio_uartx_srr_s cn58xx;
struct cvmx_mio_uartx_srr_s cn58xxp1;
+ struct cvmx_mio_uartx_srr_s cn63xx;
+ struct cvmx_mio_uartx_srr_s cn63xxp1;
};
union cvmx_mio_uartx_srt {
struct cvmx_mio_uartx_srt_s cn56xxp1;
struct cvmx_mio_uartx_srt_s cn58xx;
struct cvmx_mio_uartx_srt_s cn58xxp1;
+ struct cvmx_mio_uartx_srt_s cn63xx;
+ struct cvmx_mio_uartx_srt_s cn63xxp1;
};
union cvmx_mio_uartx_srts {
struct cvmx_mio_uartx_srts_s cn56xxp1;
struct cvmx_mio_uartx_srts_s cn58xx;
struct cvmx_mio_uartx_srts_s cn58xxp1;
+ struct cvmx_mio_uartx_srts_s cn63xx;
+ struct cvmx_mio_uartx_srts_s cn63xxp1;
};
union cvmx_mio_uartx_stt {
struct cvmx_mio_uartx_stt_s cn56xxp1;
struct cvmx_mio_uartx_stt_s cn58xx;
struct cvmx_mio_uartx_stt_s cn58xxp1;
+ struct cvmx_mio_uartx_stt_s cn63xx;
+ struct cvmx_mio_uartx_stt_s cn63xxp1;
};
union cvmx_mio_uartx_tfl {
struct cvmx_mio_uartx_tfl_s cn56xxp1;
struct cvmx_mio_uartx_tfl_s cn58xx;
struct cvmx_mio_uartx_tfl_s cn58xxp1;
+ struct cvmx_mio_uartx_tfl_s cn63xx;
+ struct cvmx_mio_uartx_tfl_s cn63xxp1;
};
union cvmx_mio_uartx_tfr {
struct cvmx_mio_uartx_tfr_s cn56xxp1;
struct cvmx_mio_uartx_tfr_s cn58xx;
struct cvmx_mio_uartx_tfr_s cn58xxp1;
+ struct cvmx_mio_uartx_tfr_s cn63xx;
+ struct cvmx_mio_uartx_tfr_s cn63xxp1;
};
union cvmx_mio_uartx_thr {
struct cvmx_mio_uartx_thr_s cn56xxp1;
struct cvmx_mio_uartx_thr_s cn58xx;
struct cvmx_mio_uartx_thr_s cn58xxp1;
+ struct cvmx_mio_uartx_thr_s cn63xx;
+ struct cvmx_mio_uartx_thr_s cn63xxp1;
};
union cvmx_mio_uartx_usr {
struct cvmx_mio_uartx_usr_s cn56xxp1;
struct cvmx_mio_uartx_usr_s cn58xx;
struct cvmx_mio_uartx_usr_s cn58xxp1;
+ struct cvmx_mio_uartx_usr_s cn63xx;
+ struct cvmx_mio_uartx_usr_s cn63xxp1;
};
union cvmx_mio_uart2_dlh {
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_MIXX_DEFS_H__
#define __CVMX_MIXX_DEFS_H__
-#define CVMX_MIXX_BIST(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_CTL(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_INTENA(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRHWM(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING2(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ISR(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORHWM(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING1(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING2(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_REMCNT(offset) \
- CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
union cvmx_mixx_bist {
uint64_t u64;
struct cvmx_mixx_bist_s {
- uint64_t reserved_4_63:60;
+ uint64_t reserved_6_63:58;
+ uint64_t opfdat:1;
+ uint64_t mrgdat:1;
uint64_t mrqdat:1;
uint64_t ipfdat:1;
uint64_t irfdat:1;
uint64_t orfdat:1;
} s;
- struct cvmx_mixx_bist_s cn52xx;
- struct cvmx_mixx_bist_s cn52xxp1;
- struct cvmx_mixx_bist_s cn56xx;
- struct cvmx_mixx_bist_s cn56xxp1;
+ struct cvmx_mixx_bist_cn52xx {
+ uint64_t reserved_4_63:60;
+ uint64_t mrqdat:1;
+ uint64_t ipfdat:1;
+ uint64_t irfdat:1;
+ uint64_t orfdat:1;
+ } cn52xx;
+ struct cvmx_mixx_bist_cn52xx cn52xxp1;
+ struct cvmx_mixx_bist_cn52xx cn56xx;
+ struct cvmx_mixx_bist_cn52xx cn56xxp1;
+ struct cvmx_mixx_bist_s cn63xx;
+ struct cvmx_mixx_bist_s cn63xxp1;
};
union cvmx_mixx_ctl {
uint64_t u64;
struct cvmx_mixx_ctl_s {
- uint64_t reserved_8_63:56;
+ uint64_t reserved_12_63:52;
+ uint64_t ts_thresh:4;
uint64_t crc_strip:1;
uint64_t busy:1;
uint64_t en:1;
uint64_t nbtarb:1;
uint64_t mrq_hwm:2;
} s;
- struct cvmx_mixx_ctl_s cn52xx;
- struct cvmx_mixx_ctl_s cn52xxp1;
- struct cvmx_mixx_ctl_s cn56xx;
- struct cvmx_mixx_ctl_s cn56xxp1;
+ struct cvmx_mixx_ctl_cn52xx {
+ uint64_t reserved_8_63:56;
+ uint64_t crc_strip:1;
+ uint64_t busy:1;
+ uint64_t en:1;
+ uint64_t reset:1;
+ uint64_t lendian:1;
+ uint64_t nbtarb:1;
+ uint64_t mrq_hwm:2;
+ } cn52xx;
+ struct cvmx_mixx_ctl_cn52xx cn52xxp1;
+ struct cvmx_mixx_ctl_cn52xx cn56xx;
+ struct cvmx_mixx_ctl_cn52xx cn56xxp1;
+ struct cvmx_mixx_ctl_s cn63xx;
+ struct cvmx_mixx_ctl_s cn63xxp1;
};
union cvmx_mixx_intena {
uint64_t u64;
struct cvmx_mixx_intena_s {
- uint64_t reserved_7_63:57;
+ uint64_t reserved_8_63:56;
+ uint64_t tsena:1;
uint64_t orunena:1;
uint64_t irunena:1;
uint64_t data_drpena:1;
uint64_t ivfena:1;
uint64_t ovfena:1;
} s;
- struct cvmx_mixx_intena_s cn52xx;
- struct cvmx_mixx_intena_s cn52xxp1;
- struct cvmx_mixx_intena_s cn56xx;
- struct cvmx_mixx_intena_s cn56xxp1;
+ struct cvmx_mixx_intena_cn52xx {
+ uint64_t reserved_7_63:57;
+ uint64_t orunena:1;
+ uint64_t irunena:1;
+ uint64_t data_drpena:1;
+ uint64_t ithena:1;
+ uint64_t othena:1;
+ uint64_t ivfena:1;
+ uint64_t ovfena:1;
+ } cn52xx;
+ struct cvmx_mixx_intena_cn52xx cn52xxp1;
+ struct cvmx_mixx_intena_cn52xx cn56xx;
+ struct cvmx_mixx_intena_cn52xx cn56xxp1;
+ struct cvmx_mixx_intena_s cn63xx;
+ struct cvmx_mixx_intena_s cn63xxp1;
};
union cvmx_mixx_ircnt {
struct cvmx_mixx_ircnt_s cn52xxp1;
struct cvmx_mixx_ircnt_s cn56xx;
struct cvmx_mixx_ircnt_s cn56xxp1;
+ struct cvmx_mixx_ircnt_s cn63xx;
+ struct cvmx_mixx_ircnt_s cn63xxp1;
};
union cvmx_mixx_irhwm {
struct cvmx_mixx_irhwm_s cn52xxp1;
struct cvmx_mixx_irhwm_s cn56xx;
struct cvmx_mixx_irhwm_s cn56xxp1;
+ struct cvmx_mixx_irhwm_s cn63xx;
+ struct cvmx_mixx_irhwm_s cn63xxp1;
};
union cvmx_mixx_iring1 {
uint64_t u64;
struct cvmx_mixx_iring1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t isize:20;
+ uint64_t ibase:37;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_mixx_iring1_cn52xx {
uint64_t reserved_60_63:4;
uint64_t isize:20;
uint64_t reserved_36_39:4;
uint64_t ibase:33;
uint64_t reserved_0_2:3;
- } s;
- struct cvmx_mixx_iring1_s cn52xx;
- struct cvmx_mixx_iring1_s cn52xxp1;
- struct cvmx_mixx_iring1_s cn56xx;
- struct cvmx_mixx_iring1_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_mixx_iring1_cn52xx cn52xxp1;
+ struct cvmx_mixx_iring1_cn52xx cn56xx;
+ struct cvmx_mixx_iring1_cn52xx cn56xxp1;
+ struct cvmx_mixx_iring1_s cn63xx;
+ struct cvmx_mixx_iring1_s cn63xxp1;
};
union cvmx_mixx_iring2 {
struct cvmx_mixx_iring2_s cn52xxp1;
struct cvmx_mixx_iring2_s cn56xx;
struct cvmx_mixx_iring2_s cn56xxp1;
+ struct cvmx_mixx_iring2_s cn63xx;
+ struct cvmx_mixx_iring2_s cn63xxp1;
};
union cvmx_mixx_isr {
uint64_t u64;
struct cvmx_mixx_isr_s {
- uint64_t reserved_7_63:57;
+ uint64_t reserved_8_63:56;
+ uint64_t ts:1;
uint64_t orun:1;
uint64_t irun:1;
uint64_t data_drp:1;
uint64_t idblovf:1;
uint64_t odblovf:1;
} s;
- struct cvmx_mixx_isr_s cn52xx;
- struct cvmx_mixx_isr_s cn52xxp1;
- struct cvmx_mixx_isr_s cn56xx;
- struct cvmx_mixx_isr_s cn56xxp1;
+ struct cvmx_mixx_isr_cn52xx {
+ uint64_t reserved_7_63:57;
+ uint64_t orun:1;
+ uint64_t irun:1;
+ uint64_t data_drp:1;
+ uint64_t irthresh:1;
+ uint64_t orthresh:1;
+ uint64_t idblovf:1;
+ uint64_t odblovf:1;
+ } cn52xx;
+ struct cvmx_mixx_isr_cn52xx cn52xxp1;
+ struct cvmx_mixx_isr_cn52xx cn56xx;
+ struct cvmx_mixx_isr_cn52xx cn56xxp1;
+ struct cvmx_mixx_isr_s cn63xx;
+ struct cvmx_mixx_isr_s cn63xxp1;
};
union cvmx_mixx_orcnt {
struct cvmx_mixx_orcnt_s cn52xxp1;
struct cvmx_mixx_orcnt_s cn56xx;
struct cvmx_mixx_orcnt_s cn56xxp1;
+ struct cvmx_mixx_orcnt_s cn63xx;
+ struct cvmx_mixx_orcnt_s cn63xxp1;
};
union cvmx_mixx_orhwm {
struct cvmx_mixx_orhwm_s cn52xxp1;
struct cvmx_mixx_orhwm_s cn56xx;
struct cvmx_mixx_orhwm_s cn56xxp1;
+ struct cvmx_mixx_orhwm_s cn63xx;
+ struct cvmx_mixx_orhwm_s cn63xxp1;
};
union cvmx_mixx_oring1 {
uint64_t u64;
struct cvmx_mixx_oring1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t osize:20;
+ uint64_t obase:37;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_mixx_oring1_cn52xx {
uint64_t reserved_60_63:4;
uint64_t osize:20;
uint64_t reserved_36_39:4;
uint64_t obase:33;
uint64_t reserved_0_2:3;
- } s;
- struct cvmx_mixx_oring1_s cn52xx;
- struct cvmx_mixx_oring1_s cn52xxp1;
- struct cvmx_mixx_oring1_s cn56xx;
- struct cvmx_mixx_oring1_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_mixx_oring1_cn52xx cn52xxp1;
+ struct cvmx_mixx_oring1_cn52xx cn56xx;
+ struct cvmx_mixx_oring1_cn52xx cn56xxp1;
+ struct cvmx_mixx_oring1_s cn63xx;
+ struct cvmx_mixx_oring1_s cn63xxp1;
};
union cvmx_mixx_oring2 {
struct cvmx_mixx_oring2_s cn52xxp1;
struct cvmx_mixx_oring2_s cn56xx;
struct cvmx_mixx_oring2_s cn56xxp1;
+ struct cvmx_mixx_oring2_s cn63xx;
+ struct cvmx_mixx_oring2_s cn63xxp1;
};
union cvmx_mixx_remcnt {
struct cvmx_mixx_remcnt_s cn52xxp1;
struct cvmx_mixx_remcnt_s cn56xx;
struct cvmx_mixx_remcnt_s cn56xxp1;
+ struct cvmx_mixx_remcnt_s cn63xx;
+ struct cvmx_mixx_remcnt_s cn63xxp1;
+};
+
+union cvmx_mixx_tsctl {
+ uint64_t u64;
+ struct cvmx_mixx_tsctl_s {
+ uint64_t reserved_21_63:43;
+ uint64_t tsavl:5;
+ uint64_t reserved_13_15:3;
+ uint64_t tstot:5;
+ uint64_t reserved_5_7:3;
+ uint64_t tscnt:5;
+ } s;
+ struct cvmx_mixx_tsctl_s cn63xx;
+ struct cvmx_mixx_tsctl_s cn63xxp1;
+};
+
+union cvmx_mixx_tstamp {
+ uint64_t u64;
+ struct cvmx_mixx_tstamp_s {
+ uint64_t tstamp:64;
+ } s;
+ struct cvmx_mixx_tstamp_s cn63xx;
+ struct cvmx_mixx_tstamp_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_NPEI_DEFS_H__
#define __CVMX_NPEI_DEFS_H__
-#define CVMX_NPEI_BAR1_INDEXX(offset) \
- (0x0000000000000000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_BIST_STATUS \
- (0x0000000000000580ull)
-#define CVMX_NPEI_BIST_STATUS2 \
- (0x0000000000000680ull)
-#define CVMX_NPEI_CTL_PORT0 \
- (0x0000000000000250ull)
-#define CVMX_NPEI_CTL_PORT1 \
- (0x0000000000000260ull)
-#define CVMX_NPEI_CTL_STATUS \
- (0x0000000000000570ull)
-#define CVMX_NPEI_CTL_STATUS2 \
- (0x0000000000003C00ull)
-#define CVMX_NPEI_DATA_OUT_CNT \
- (0x00000000000005F0ull)
-#define CVMX_NPEI_DBG_DATA \
- (0x0000000000000510ull)
-#define CVMX_NPEI_DBG_SELECT \
- (0x0000000000000500ull)
-#define CVMX_NPEI_DMA0_INT_LEVEL \
- (0x00000000000005C0ull)
-#define CVMX_NPEI_DMA1_INT_LEVEL \
- (0x00000000000005D0ull)
-#define CVMX_NPEI_DMAX_COUNTS(offset) \
- (0x0000000000000450ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_DBELL(offset) \
- (0x00000000000003B0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
- (0x0000000000000400ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_NADDR(offset) \
- (0x00000000000004A0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMA_CNTS \
- (0x00000000000005E0ull)
-#define CVMX_NPEI_DMA_CONTROL \
- (0x00000000000003A0ull)
-#define CVMX_NPEI_INT_A_ENB \
- (0x0000000000000560ull)
-#define CVMX_NPEI_INT_A_ENB2 \
- (0x0000000000003CE0ull)
-#define CVMX_NPEI_INT_A_SUM \
- (0x0000000000000550ull)
-#define CVMX_NPEI_INT_ENB \
- (0x0000000000000540ull)
-#define CVMX_NPEI_INT_ENB2 \
- (0x0000000000003CD0ull)
-#define CVMX_NPEI_INT_INFO \
- (0x0000000000000590ull)
-#define CVMX_NPEI_INT_SUM \
- (0x0000000000000530ull)
-#define CVMX_NPEI_INT_SUM2 \
- (0x0000000000003CC0ull)
-#define CVMX_NPEI_LAST_WIN_RDATA0 \
- (0x0000000000000600ull)
-#define CVMX_NPEI_LAST_WIN_RDATA1 \
- (0x0000000000000610ull)
-#define CVMX_NPEI_MEM_ACCESS_CTL \
- (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
- (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_NPEI_MSI_ENB0 \
- (0x0000000000003C50ull)
-#define CVMX_NPEI_MSI_ENB1 \
- (0x0000000000003C60ull)
-#define CVMX_NPEI_MSI_ENB2 \
- (0x0000000000003C70ull)
-#define CVMX_NPEI_MSI_ENB3 \
- (0x0000000000003C80ull)
-#define CVMX_NPEI_MSI_RCV0 \
- (0x0000000000003C10ull)
-#define CVMX_NPEI_MSI_RCV1 \
- (0x0000000000003C20ull)
-#define CVMX_NPEI_MSI_RCV2 \
- (0x0000000000003C30ull)
-#define CVMX_NPEI_MSI_RCV3 \
- (0x0000000000003C40ull)
-#define CVMX_NPEI_MSI_RD_MAP \
- (0x0000000000003CA0ull)
-#define CVMX_NPEI_MSI_W1C_ENB0 \
- (0x0000000000003CF0ull)
-#define CVMX_NPEI_MSI_W1C_ENB1 \
- (0x0000000000003D00ull)
-#define CVMX_NPEI_MSI_W1C_ENB2 \
- (0x0000000000003D10ull)
-#define CVMX_NPEI_MSI_W1C_ENB3 \
- (0x0000000000003D20ull)
-#define CVMX_NPEI_MSI_W1S_ENB0 \
- (0x0000000000003D30ull)
-#define CVMX_NPEI_MSI_W1S_ENB1 \
- (0x0000000000003D40ull)
-#define CVMX_NPEI_MSI_W1S_ENB2 \
- (0x0000000000003D50ull)
-#define CVMX_NPEI_MSI_W1S_ENB3 \
- (0x0000000000003D60ull)
-#define CVMX_NPEI_MSI_WR_MAP \
- (0x0000000000003C90ull)
-#define CVMX_NPEI_PCIE_CREDIT_CNT \
- (0x0000000000003D70ull)
-#define CVMX_NPEI_PCIE_MSI_RCV \
- (0x0000000000003CB0ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
- (0x0000000000000650ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
- (0x0000000000000660ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
- (0x0000000000000670ull)
-#define CVMX_NPEI_PKTX_CNTS(offset) \
- (0x0000000000002400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
- (0x0000000000002800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
- (0x0000000000002C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
- (0x0000000000003000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
- (0x0000000000003400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_IN_BP(offset) \
- (0x0000000000003800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
- (0x0000000000001400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
- (0x0000000000001800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
- (0x0000000000001C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_CNT_INT \
- (0x0000000000001110ull)
-#define CVMX_NPEI_PKT_CNT_INT_ENB \
- (0x0000000000001130ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ES \
- (0x00000000000010B0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_NS \
- (0x00000000000010A0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ROR \
- (0x0000000000001090ull)
-#define CVMX_NPEI_PKT_DPADDR \
- (0x0000000000001080ull)
-#define CVMX_NPEI_PKT_INPUT_CONTROL \
- (0x0000000000001150ull)
-#define CVMX_NPEI_PKT_INSTR_ENB \
- (0x0000000000001000ull)
-#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
- (0x0000000000001190ull)
-#define CVMX_NPEI_PKT_INSTR_SIZE \
- (0x0000000000001020ull)
-#define CVMX_NPEI_PKT_INT_LEVELS \
- (0x0000000000001100ull)
-#define CVMX_NPEI_PKT_IN_BP \
- (0x00000000000006B0ull)
-#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
- (0x0000000000002000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
- (0x00000000000006A0ull)
-#define CVMX_NPEI_PKT_IN_PCIE_PORT \
- (0x00000000000011A0ull)
-#define CVMX_NPEI_PKT_IPTR \
- (0x0000000000001070ull)
-#define CVMX_NPEI_PKT_OUTPUT_WMARK \
- (0x0000000000001160ull)
-#define CVMX_NPEI_PKT_OUT_BMODE \
- (0x00000000000010D0ull)
-#define CVMX_NPEI_PKT_OUT_ENB \
- (0x0000000000001010ull)
-#define CVMX_NPEI_PKT_PCIE_PORT \
- (0x00000000000010E0ull)
-#define CVMX_NPEI_PKT_PORT_IN_RST \
- (0x0000000000000690ull)
-#define CVMX_NPEI_PKT_SLIST_ES \
- (0x0000000000001050ull)
-#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
- (0x0000000000001180ull)
-#define CVMX_NPEI_PKT_SLIST_NS \
- (0x0000000000001040ull)
-#define CVMX_NPEI_PKT_SLIST_ROR \
- (0x0000000000001030ull)
-#define CVMX_NPEI_PKT_TIME_INT \
- (0x0000000000001120ull)
-#define CVMX_NPEI_PKT_TIME_INT_ENB \
- (0x0000000000001140ull)
-#define CVMX_NPEI_RSL_INT_BLOCKS \
- (0x0000000000000520ull)
-#define CVMX_NPEI_SCRATCH_1 \
- (0x0000000000000270ull)
-#define CVMX_NPEI_STATE1 \
- (0x0000000000000620ull)
-#define CVMX_NPEI_STATE2 \
- (0x0000000000000630ull)
-#define CVMX_NPEI_STATE3 \
- (0x0000000000000640ull)
-#define CVMX_NPEI_WINDOW_CTL \
- (0x0000000000000380ull)
-#define CVMX_NPEI_WIN_RD_ADDR \
- (0x0000000000000210ull)
-#define CVMX_NPEI_WIN_RD_DATA \
- (0x0000000000000240ull)
-#define CVMX_NPEI_WIN_WR_ADDR \
- (0x0000000000000200ull)
-#define CVMX_NPEI_WIN_WR_DATA \
- (0x0000000000000220ull)
-#define CVMX_NPEI_WIN_WR_MASK \
- (0x0000000000000230ull)
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
union cvmx_npei_bar1_indexx {
uint32_t u32;
uint64_t u64;
struct cvmx_npei_bist_status_s {
uint64_t pkt_rdf:1;
- uint64_t pkt_pmem:1;
- uint64_t pkt_p1:1;
- uint64_t reserved_60_60:1;
+ uint64_t reserved_60_62:3;
uint64_t pcr_gim:1;
uint64_t pkt_pif:1;
uint64_t pcsr_int:1;
} s;
struct cvmx_npei_bist_status_cn52xx {
uint64_t pkt_rdf:1;
- uint64_t pkt_pmem:1;
- uint64_t pkt_p1:1;
- uint64_t reserved_60_60:1;
+ uint64_t reserved_60_62:3;
uint64_t pcr_gim:1;
uint64_t pkt_pif:1;
uint64_t pcsr_int:1;
uint64_t msi:1;
uint64_t ncb_cmd:1;
} cn52xxp1;
- struct cvmx_npei_bist_status_cn56xx {
- uint64_t pkt_rdf:1;
- uint64_t reserved_60_62:3;
- uint64_t pcr_gim:1;
- uint64_t pkt_pif:1;
- uint64_t pcsr_int:1;
- uint64_t pcsr_im:1;
- uint64_t pcsr_cnt:1;
- uint64_t pcsr_id:1;
- uint64_t pcsr_sl:1;
- uint64_t pkt_imem:1;
- uint64_t pkt_pfm:1;
- uint64_t pkt_pof:1;
- uint64_t reserved_48_49:2;
- uint64_t pkt_pop0:1;
- uint64_t pkt_pop1:1;
- uint64_t d0_mem:1;
- uint64_t d1_mem:1;
- uint64_t d2_mem:1;
- uint64_t d3_mem:1;
- uint64_t d4_mem:1;
- uint64_t ds_mem:1;
- uint64_t reserved_36_39:4;
- uint64_t d0_pst:1;
- uint64_t d1_pst:1;
- uint64_t d2_pst:1;
- uint64_t d3_pst:1;
- uint64_t d4_pst:1;
- uint64_t n2p0_c:1;
- uint64_t n2p0_o:1;
- uint64_t n2p1_c:1;
- uint64_t n2p1_o:1;
- uint64_t cpl_p0:1;
- uint64_t cpl_p1:1;
- uint64_t p2n1_po:1;
- uint64_t p2n1_no:1;
- uint64_t p2n1_co:1;
- uint64_t p2n0_po:1;
- uint64_t p2n0_no:1;
- uint64_t p2n0_co:1;
- uint64_t p2n0_c0:1;
- uint64_t p2n0_c1:1;
- uint64_t p2n0_n:1;
- uint64_t p2n0_p0:1;
- uint64_t p2n0_p1:1;
- uint64_t p2n1_c0:1;
- uint64_t p2n1_c1:1;
- uint64_t p2n1_n:1;
- uint64_t p2n1_p0:1;
- uint64_t p2n1_p1:1;
- uint64_t csm0:1;
- uint64_t csm1:1;
- uint64_t dif0:1;
- uint64_t dif1:1;
- uint64_t dif2:1;
- uint64_t dif3:1;
- uint64_t dif4:1;
- uint64_t msi:1;
- uint64_t ncb_cmd:1;
- } cn56xx;
+ struct cvmx_npei_bist_status_cn52xx cn56xx;
struct cvmx_npei_bist_status_cn56xxp1 {
uint64_t reserved_58_63:6;
uint64_t pcsr_int:1;
union cvmx_npei_bist_status2 {
uint64_t u64;
struct cvmx_npei_bist_status2_s {
- uint64_t reserved_5_63:59;
+ uint64_t reserved_14_63:50;
+ uint64_t prd_tag:1;
+ uint64_t prd_st0:1;
+ uint64_t prd_st1:1;
+ uint64_t prd_err:1;
+ uint64_t nrd_st:1;
+ uint64_t nwe_st:1;
+ uint64_t nwe_wr0:1;
+ uint64_t nwe_wr1:1;
+ uint64_t pkt_rd:1;
uint64_t psc_p0:1;
uint64_t psc_p1:1;
uint64_t pkt_gd:1;
} cn52xxp1;
struct cvmx_npei_ctl_status_s cn56xx;
struct cvmx_npei_ctl_status_cn56xxp1 {
- uint64_t reserved_16_63:48;
- uint64_t ring_en:1;
+ uint64_t reserved_15_63:49;
uint64_t lnk_rst:1;
uint64_t arb:1;
uint64_t pkt_bp:4;
uint64_t saddr:29;
uint64_t reserved_0_6:7;
} s;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+ struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
uint64_t reserved_36_63:28;
uint64_t saddr:29;
uint64_t reserved_0_6:7;
- } cn52xx;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+ } cn52xxp1;
struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+ struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
};
union cvmx_npei_dmax_naddr {
union cvmx_npei_dma_control {
uint64_t u64;
struct cvmx_npei_dma_control_s {
- uint64_t reserved_39_63:25;
+ uint64_t reserved_40_63:24;
+ uint64_t p_32b_m:1;
uint64_t dma4_enb:1;
uint64_t dma3_enb:1;
uint64_t dma2_enb:1;
uint64_t csize:14;
} cn52xxp1;
struct cvmx_npei_dma_control_s cn56xx;
- struct cvmx_npei_dma_control_s cn56xxp1;
+ struct cvmx_npei_dma_control_cn56xxp1 {
+ uint64_t reserved_39_63:25;
+ uint64_t dma4_enb:1;
+ uint64_t dma3_enb:1;
+ uint64_t dma2_enb:1;
+ uint64_t dma1_enb:1;
+ uint64_t dma0_enb:1;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t csize:14;
+ } cn56xxp1;
+};
+
+union cvmx_npei_dma_pcie_req_num {
+ uint64_t u64;
+ struct cvmx_npei_dma_pcie_req_num_s {
+ uint64_t dma_arb:1;
+ uint64_t reserved_53_62:10;
+ uint64_t pkt_cnt:5;
+ uint64_t reserved_45_47:3;
+ uint64_t dma4_cnt:5;
+ uint64_t reserved_37_39:3;
+ uint64_t dma3_cnt:5;
+ uint64_t reserved_29_31:3;
+ uint64_t dma2_cnt:5;
+ uint64_t reserved_21_23:3;
+ uint64_t dma1_cnt:5;
+ uint64_t reserved_13_15:3;
+ uint64_t dma0_cnt:5;
+ uint64_t reserved_5_7:3;
+ uint64_t dma_cnt:5;
+ } s;
+ struct cvmx_npei_dma_pcie_req_num_s cn52xx;
+ struct cvmx_npei_dma_pcie_req_num_s cn56xx;
+};
+
+union cvmx_npei_dma_state1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state1_s {
+ uint64_t reserved_40_63:24;
+ uint64_t d4_dwe:8;
+ uint64_t d3_dwe:8;
+ uint64_t d2_dwe:8;
+ uint64_t d1_dwe:8;
+ uint64_t d0_dwe:8;
+ } s;
+ struct cvmx_npei_dma_state1_s cn52xx;
+};
+
+union cvmx_npei_dma_state1_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state1_p1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_difst:7;
+ uint64_t d1_difst:7;
+ uint64_t d2_difst:7;
+ uint64_t d3_difst:7;
+ uint64_t d4_difst:7;
+ uint64_t d0_reqst:5;
+ uint64_t d1_reqst:5;
+ uint64_t d2_reqst:5;
+ uint64_t d3_reqst:5;
+ uint64_t d4_reqst:5;
+ } s;
+ struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_difst:7;
+ uint64_t d1_difst:7;
+ uint64_t d2_difst:7;
+ uint64_t d3_difst:7;
+ uint64_t reserved_25_31:7;
+ uint64_t d0_reqst:5;
+ uint64_t d1_reqst:5;
+ uint64_t d2_reqst:5;
+ uint64_t d3_reqst:5;
+ uint64_t reserved_0_4:5;
+ } cn52xxp1;
+ struct cvmx_npei_dma_state1_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state2 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state2_s {
+ uint64_t reserved_28_63:36;
+ uint64_t ndwe:4;
+ uint64_t reserved_21_23:3;
+ uint64_t ndre:5;
+ uint64_t reserved_10_15:6;
+ uint64_t prd:10;
+ } s;
+ struct cvmx_npei_dma_state2_s cn52xx;
+};
+
+union cvmx_npei_dma_state2_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state2_p1_s {
+ uint64_t reserved_45_63:19;
+ uint64_t d0_dffst:9;
+ uint64_t d1_dffst:9;
+ uint64_t d2_dffst:9;
+ uint64_t d3_dffst:9;
+ uint64_t d4_dffst:9;
+ } s;
+ struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+ uint64_t reserved_45_63:19;
+ uint64_t d0_dffst:9;
+ uint64_t d1_dffst:9;
+ uint64_t d2_dffst:9;
+ uint64_t d3_dffst:9;
+ uint64_t reserved_0_8:9;
+ } cn52xxp1;
+ struct cvmx_npei_dma_state2_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state3_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state3_p1_s {
+ uint64_t reserved_60_63:4;
+ uint64_t d0_drest:15;
+ uint64_t d1_drest:15;
+ uint64_t d2_drest:15;
+ uint64_t d3_drest:15;
+ } s;
+ struct cvmx_npei_dma_state3_p1_s cn52xxp1;
+ struct cvmx_npei_dma_state3_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state4_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state4_p1_s {
+ uint64_t reserved_52_63:12;
+ uint64_t d0_dwest:13;
+ uint64_t d1_dwest:13;
+ uint64_t d2_dwest:13;
+ uint64_t d3_dwest:13;
+ } s;
+ struct cvmx_npei_dma_state4_p1_s cn52xxp1;
+ struct cvmx_npei_dma_state4_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state5_p1 {
+ uint64_t u64;
+ struct cvmx_npei_dma_state5_p1_s {
+ uint64_t reserved_28_63:36;
+ uint64_t d4_drest:15;
+ uint64_t d4_dwest:13;
+ } s;
+ struct cvmx_npei_dma_state5_p1_s cn56xxp1;
};
union cvmx_npei_int_a_enb {
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_enb_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t dma1_cpl:1;
- uint64_t dma0_cpl:1;
- } cn52xx;
+ struct cvmx_npei_int_a_enb_s cn52xx;
struct cvmx_npei_int_a_enb_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_enb2_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t reserved_0_1:2;
- } cn52xx;
+ struct cvmx_npei_int_a_enb2_s cn52xx;
struct cvmx_npei_int_a_enb2_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
uint64_t dma1_cpl:1;
uint64_t dma0_cpl:1;
} s;
- struct cvmx_npei_int_a_sum_cn52xx {
- uint64_t reserved_8_63:56;
- uint64_t p1_rdlk:1;
- uint64_t p0_rdlk:1;
- uint64_t pgl_err:1;
- uint64_t pdi_err:1;
- uint64_t pop_err:1;
- uint64_t pins_err:1;
- uint64_t dma1_cpl:1;
- uint64_t dma0_cpl:1;
- } cn52xx;
+ struct cvmx_npei_int_a_sum_s cn52xx;
struct cvmx_npei_int_a_sum_cn52xxp1 {
uint64_t reserved_2_63:62;
uint64_t dma1_cpl:1;
uint64_t c0_se:1;
uint64_t reserved_20_20:1;
uint64_t c0_aeri:1;
- uint64_t ptime:1;
- uint64_t pcnt:1;
- uint64_t pidbof:1;
- uint64_t psldbof:1;
+ uint64_t reserved_15_18:4;
uint64_t dtime1:1;
uint64_t dtime0:1;
uint64_t dcnt1:1;
} s;
struct cvmx_npei_pktx_cnts_s cn52xx;
struct cvmx_npei_pktx_cnts_s cn56xx;
- struct cvmx_npei_pktx_cnts_s cn56xxp1;
};
union cvmx_npei_pktx_in_bp {
} s;
struct cvmx_npei_pktx_in_bp_s cn52xx;
struct cvmx_npei_pktx_in_bp_s cn56xx;
- struct cvmx_npei_pktx_in_bp_s cn56xxp1;
};
union cvmx_npei_pktx_instr_baddr {
} s;
struct cvmx_npei_pktx_instr_baddr_s cn52xx;
struct cvmx_npei_pktx_instr_baddr_s cn56xx;
- struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
};
union cvmx_npei_pktx_instr_baoff_dbell {
} s;
struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
- struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
};
union cvmx_npei_pktx_instr_fifo_rsize {
} s;
struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
- struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
};
union cvmx_npei_pktx_instr_header {
struct cvmx_npei_pktx_instr_header_s {
uint64_t reserved_44_63:20;
uint64_t pbp:1;
- uint64_t rsv_f:5;
+ uint64_t reserved_38_42:5;
uint64_t rparmode:2;
- uint64_t rsv_e:1;
+ uint64_t reserved_35_35:1;
uint64_t rskp_len:7;
- uint64_t rsv_d:6;
+ uint64_t reserved_22_27:6;
uint64_t use_ihdr:1;
- uint64_t rsv_c:5;
+ uint64_t reserved_16_20:5;
uint64_t par_mode:2;
- uint64_t rsv_b:1;
+ uint64_t reserved_13_13:1;
uint64_t skp_len:7;
- uint64_t rsv_a:6;
+ uint64_t reserved_0_5:6;
} s;
struct cvmx_npei_pktx_instr_header_s cn52xx;
struct cvmx_npei_pktx_instr_header_s cn56xx;
- struct cvmx_npei_pktx_instr_header_s cn56xxp1;
};
union cvmx_npei_pktx_slist_baddr {
} s;
struct cvmx_npei_pktx_slist_baddr_s cn52xx;
struct cvmx_npei_pktx_slist_baddr_s cn56xx;
- struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
};
union cvmx_npei_pktx_slist_baoff_dbell {
} s;
struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
- struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
};
union cvmx_npei_pktx_slist_fifo_rsize {
} s;
struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
- struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
};
union cvmx_npei_pkt_cnt_int {
} s;
struct cvmx_npei_pkt_cnt_int_s cn52xx;
struct cvmx_npei_pkt_cnt_int_s cn56xx;
- struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
};
union cvmx_npei_pkt_cnt_int_enb {
} s;
struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
- struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_es {
} s;
struct cvmx_npei_pkt_data_out_es_s cn52xx;
struct cvmx_npei_pkt_data_out_es_s cn56xx;
- struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_ns {
} s;
struct cvmx_npei_pkt_data_out_ns_s cn52xx;
struct cvmx_npei_pkt_data_out_ns_s cn56xx;
- struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
};
union cvmx_npei_pkt_data_out_ror {
} s;
struct cvmx_npei_pkt_data_out_ror_s cn52xx;
struct cvmx_npei_pkt_data_out_ror_s cn56xx;
- struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
};
union cvmx_npei_pkt_dpaddr {
} s;
struct cvmx_npei_pkt_dpaddr_s cn52xx;
struct cvmx_npei_pkt_dpaddr_s cn56xx;
- struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
};
union cvmx_npei_pkt_in_bp {
uint64_t reserved_32_63:32;
uint64_t bp:32;
} s;
+ struct cvmx_npei_pkt_in_bp_s cn52xx;
struct cvmx_npei_pkt_in_bp_s cn56xx;
};
} s;
struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
- struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
};
union cvmx_npei_pkt_in_instr_counts {
} s;
struct cvmx_npei_pkt_input_control_s cn52xx;
struct cvmx_npei_pkt_input_control_s cn56xx;
- struct cvmx_npei_pkt_input_control_s cn56xxp1;
};
union cvmx_npei_pkt_instr_enb {
} s;
struct cvmx_npei_pkt_instr_enb_s cn52xx;
struct cvmx_npei_pkt_instr_enb_s cn56xx;
- struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
};
union cvmx_npei_pkt_instr_rd_size {
} s;
struct cvmx_npei_pkt_instr_size_s cn52xx;
struct cvmx_npei_pkt_instr_size_s cn56xx;
- struct cvmx_npei_pkt_instr_size_s cn56xxp1;
};
union cvmx_npei_pkt_int_levels {
} s;
struct cvmx_npei_pkt_int_levels_s cn52xx;
struct cvmx_npei_pkt_int_levels_s cn56xx;
- struct cvmx_npei_pkt_int_levels_s cn56xxp1;
};
union cvmx_npei_pkt_iptr {
} s;
struct cvmx_npei_pkt_iptr_s cn52xx;
struct cvmx_npei_pkt_iptr_s cn56xx;
- struct cvmx_npei_pkt_iptr_s cn56xxp1;
};
union cvmx_npei_pkt_out_bmode {
} s;
struct cvmx_npei_pkt_out_bmode_s cn52xx;
struct cvmx_npei_pkt_out_bmode_s cn56xx;
- struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
};
union cvmx_npei_pkt_out_enb {
} s;
struct cvmx_npei_pkt_out_enb_s cn52xx;
struct cvmx_npei_pkt_out_enb_s cn56xx;
- struct cvmx_npei_pkt_out_enb_s cn56xxp1;
};
union cvmx_npei_pkt_output_wmark {
} s;
struct cvmx_npei_pkt_pcie_port_s cn52xx;
struct cvmx_npei_pkt_pcie_port_s cn56xx;
- struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
};
union cvmx_npei_pkt_port_in_rst {
} s;
struct cvmx_npei_pkt_slist_es_s cn52xx;
struct cvmx_npei_pkt_slist_es_s cn56xx;
- struct cvmx_npei_pkt_slist_es_s cn56xxp1;
};
union cvmx_npei_pkt_slist_id_size {
} s;
struct cvmx_npei_pkt_slist_id_size_s cn52xx;
struct cvmx_npei_pkt_slist_id_size_s cn56xx;
- struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
};
union cvmx_npei_pkt_slist_ns {
} s;
struct cvmx_npei_pkt_slist_ns_s cn52xx;
struct cvmx_npei_pkt_slist_ns_s cn56xx;
- struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
};
union cvmx_npei_pkt_slist_ror {
} s;
struct cvmx_npei_pkt_slist_ror_s cn52xx;
struct cvmx_npei_pkt_slist_ror_s cn56xx;
- struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
};
union cvmx_npei_pkt_time_int {
} s;
struct cvmx_npei_pkt_time_int_s cn52xx;
struct cvmx_npei_pkt_time_int_s cn56xx;
- struct cvmx_npei_pkt_time_int_s cn56xxp1;
};
union cvmx_npei_pkt_time_int_enb {
} s;
struct cvmx_npei_pkt_time_int_enb_s cn52xx;
struct cvmx_npei_pkt_time_int_enb_s cn56xx;
- struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
};
union cvmx_npei_rsl_int_blocks {
uint64_t asxpcs0:1;
uint64_t reserved_21_21:1;
uint64_t pip:1;
- uint64_t reserved_18_19:2;
+ uint64_t spx1:1;
+ uint64_t spx0:1;
uint64_t lmc0:1;
uint64_t l2c:1;
uint64_t usb1:1;
uint64_t ipd:1;
uint64_t reserved_8_8:1;
uint64_t zip:1;
- uint64_t reserved_6_6:1;
+ uint64_t dfa:1;
uint64_t fpa:1;
uint64_t key:1;
uint64_t npei:1;
} s;
struct cvmx_npei_rsl_int_blocks_s cn52xx;
struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
- struct cvmx_npei_rsl_int_blocks_cn56xx {
- uint64_t reserved_31_63:33;
- uint64_t iob:1;
- uint64_t lmc1:1;
- uint64_t agl:1;
- uint64_t reserved_24_27:4;
- uint64_t asxpcs1:1;
- uint64_t asxpcs0:1;
- uint64_t reserved_21_21:1;
- uint64_t pip:1;
- uint64_t reserved_18_19:2;
- uint64_t lmc0:1;
- uint64_t l2c:1;
- uint64_t reserved_15_15:1;
- uint64_t rad:1;
- uint64_t usb:1;
- uint64_t pow:1;
- uint64_t tim:1;
- uint64_t pko:1;
- uint64_t ipd:1;
- uint64_t reserved_8_8:1;
- uint64_t zip:1;
- uint64_t reserved_6_6:1;
- uint64_t fpa:1;
- uint64_t key:1;
- uint64_t npei:1;
- uint64_t gmx1:1;
- uint64_t gmx0:1;
- uint64_t mio:1;
- } cn56xx;
- struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+ struct cvmx_npei_rsl_int_blocks_s cn56xx;
+ struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
};
union cvmx_npei_scratch_1 {
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_NPI_DEFS_H__
#define __CVMX_NPI_DEFS_H__
-#define CVMX_NPI_BASE_ADDR_INPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000070ull)
-#define CVMX_NPI_BASE_ADDR_INPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000080ull)
-#define CVMX_NPI_BASE_ADDR_INPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000090ull)
-#define CVMX_NPI_BASE_ADDR_INPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
-#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
-#define CVMX_NPI_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_COMP_CTL \
- CVMX_ADD_IO_SEG(0x00011F0000000218ull)
-#define CVMX_NPI_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000000010ull)
-#define CVMX_NPI_DBG_SELECT \
- CVMX_ADD_IO_SEG(0x00011F0000000008ull)
-#define CVMX_NPI_DMA_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000128ull)
-#define CVMX_NPI_DMA_HIGHP_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000148ull)
-#define CVMX_NPI_DMA_HIGHP_NADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000158ull)
-#define CVMX_NPI_DMA_LOWP_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000140ull)
-#define CVMX_NPI_DMA_LOWP_NADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000150ull)
-#define CVMX_NPI_HIGHP_DBELL \
- CVMX_ADD_IO_SEG(0x00011F0000000120ull)
-#define CVMX_NPI_HIGHP_IBUFF_SADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000110ull)
-#define CVMX_NPI_INPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000138ull)
-#define CVMX_NPI_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000000020ull)
-#define CVMX_NPI_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000000018ull)
-#define CVMX_NPI_LOWP_DBELL \
- CVMX_ADD_IO_SEG(0x00011F0000000118ull)
-#define CVMX_NPI_LOWP_IBUFF_SADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000108ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID3 \
- CVMX_ADD_IO_SEG(0x00011F0000000028ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID4 \
- CVMX_ADD_IO_SEG(0x00011F0000000030ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID5 \
- CVMX_ADD_IO_SEG(0x00011F0000000038ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID6 \
- CVMX_ADD_IO_SEG(0x00011F0000000040ull)
-#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
-#define CVMX_NPI_MSI_RCV \
- (0x0000000000000190ull)
-#define CVMX_NPI_NPI_MSI_RCV \
- CVMX_ADD_IO_SEG(0x00011F0000001190ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000050ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000058ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000060ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT3 \
- CVMX_ADD_IO_SEG(0x00011F0000000068ull)
-#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
-#define CVMX_NPI_OUTPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000000100ull)
-#define CVMX_NPI_P0_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000180ull)
-#define CVMX_NPI_P0_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
-#define CVMX_NPI_P0_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
-#define CVMX_NPI_P0_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000160ull)
-#define CVMX_NPI_P1_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000188ull)
-#define CVMX_NPI_P1_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
-#define CVMX_NPI_P1_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
-#define CVMX_NPI_P1_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000168ull)
-#define CVMX_NPI_P2_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000190ull)
-#define CVMX_NPI_P2_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
-#define CVMX_NPI_P2_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
-#define CVMX_NPI_P2_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000170ull)
-#define CVMX_NPI_P3_DBPAIR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F0000000198ull)
-#define CVMX_NPI_P3_INSTR_ADDR \
- CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
-#define CVMX_NPI_P3_INSTR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
-#define CVMX_NPI_P3_PAIR_CNTS \
- CVMX_ADD_IO_SEG(0x00011F0000000178ull)
-#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-#define CVMX_NPI_PCI_BIST_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-#define CVMX_NPI_PCI_BURST_SIZE \
- CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-#define CVMX_NPI_PCI_CFG00 \
- CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-#define CVMX_NPI_PCI_CFG01 \
- CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-#define CVMX_NPI_PCI_CFG02 \
- CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-#define CVMX_NPI_PCI_CFG03 \
- CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-#define CVMX_NPI_PCI_CFG04 \
- CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-#define CVMX_NPI_PCI_CFG05 \
- CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-#define CVMX_NPI_PCI_CFG06 \
- CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-#define CVMX_NPI_PCI_CFG07 \
- CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-#define CVMX_NPI_PCI_CFG08 \
- CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-#define CVMX_NPI_PCI_CFG09 \
- CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-#define CVMX_NPI_PCI_CFG10 \
- CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-#define CVMX_NPI_PCI_CFG11 \
- CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-#define CVMX_NPI_PCI_CFG12 \
- CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-#define CVMX_NPI_PCI_CFG13 \
- CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-#define CVMX_NPI_PCI_CFG15 \
- CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-#define CVMX_NPI_PCI_CFG16 \
- CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-#define CVMX_NPI_PCI_CFG17 \
- CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-#define CVMX_NPI_PCI_CFG18 \
- CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-#define CVMX_NPI_PCI_CFG19 \
- CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-#define CVMX_NPI_PCI_CFG20 \
- CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-#define CVMX_NPI_PCI_CFG21 \
- CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-#define CVMX_NPI_PCI_CFG22 \
- CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-#define CVMX_NPI_PCI_CFG56 \
- CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-#define CVMX_NPI_PCI_CFG57 \
- CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-#define CVMX_NPI_PCI_CFG58 \
- CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-#define CVMX_NPI_PCI_CFG59 \
- CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-#define CVMX_NPI_PCI_CFG60 \
- CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-#define CVMX_NPI_PCI_CFG61 \
- CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-#define CVMX_NPI_PCI_CFG62 \
- CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-#define CVMX_NPI_PCI_CFG63 \
- CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-#define CVMX_NPI_PCI_CNT_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-#define CVMX_NPI_PCI_CTL_STATUS_2 \
- CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-#define CVMX_NPI_PCI_INT_ARB_CFG \
- CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-#define CVMX_NPI_PCI_INT_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-#define CVMX_NPI_PCI_INT_SUM2 \
- CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-#define CVMX_NPI_PCI_READ_CMD \
- CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-#define CVMX_NPI_PCI_READ_CMD_6 \
- CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-#define CVMX_NPI_PCI_READ_CMD_C \
- CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-#define CVMX_NPI_PCI_READ_CMD_E \
- CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-#define CVMX_NPI_PCI_SCM_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-#define CVMX_NPI_PCI_TSR_REG \
- CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-#define CVMX_NPI_PORT32_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-#define CVMX_NPI_PORT33_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-#define CVMX_NPI_PORT34_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-#define CVMX_NPI_PORT35_INSTR_HDR \
- CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-#define CVMX_NPI_PORT_BP_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_ADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_PAIR_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-#define CVMX_NPI_RSL_INT_BLOCKS \
- CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-#define CVMX_NPI_SIZE_INPUT0 \
- CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-#define CVMX_NPI_SIZE_INPUT1 \
- CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-#define CVMX_NPI_SIZE_INPUT2 \
- CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-#define CVMX_NPI_SIZE_INPUT3 \
- CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-#define CVMX_NPI_SIZE_INPUTX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-#define CVMX_NPI_WIN_READ_TO \
- CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
union cvmx_npi_base_addr_inputx {
uint64_t u64;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_PCI_DEFS_H__
#define __CVMX_PCI_DEFS_H__
-#define CVMX_PCI_BAR1_INDEXX(offset) \
- (0x0000000000000100ull + (((offset) & 31) * 4))
-#define CVMX_PCI_BIST_REG \
- (0x00000000000001C0ull)
-#define CVMX_PCI_CFG00 \
- (0x0000000000000000ull)
-#define CVMX_PCI_CFG01 \
- (0x0000000000000004ull)
-#define CVMX_PCI_CFG02 \
- (0x0000000000000008ull)
-#define CVMX_PCI_CFG03 \
- (0x000000000000000Cull)
-#define CVMX_PCI_CFG04 \
- (0x0000000000000010ull)
-#define CVMX_PCI_CFG05 \
- (0x0000000000000014ull)
-#define CVMX_PCI_CFG06 \
- (0x0000000000000018ull)
-#define CVMX_PCI_CFG07 \
- (0x000000000000001Cull)
-#define CVMX_PCI_CFG08 \
- (0x0000000000000020ull)
-#define CVMX_PCI_CFG09 \
- (0x0000000000000024ull)
-#define CVMX_PCI_CFG10 \
- (0x0000000000000028ull)
-#define CVMX_PCI_CFG11 \
- (0x000000000000002Cull)
-#define CVMX_PCI_CFG12 \
- (0x0000000000000030ull)
-#define CVMX_PCI_CFG13 \
- (0x0000000000000034ull)
-#define CVMX_PCI_CFG15 \
- (0x000000000000003Cull)
-#define CVMX_PCI_CFG16 \
- (0x0000000000000040ull)
-#define CVMX_PCI_CFG17 \
- (0x0000000000000044ull)
-#define CVMX_PCI_CFG18 \
- (0x0000000000000048ull)
-#define CVMX_PCI_CFG19 \
- (0x000000000000004Cull)
-#define CVMX_PCI_CFG20 \
- (0x0000000000000050ull)
-#define CVMX_PCI_CFG21 \
- (0x0000000000000054ull)
-#define CVMX_PCI_CFG22 \
- (0x0000000000000058ull)
-#define CVMX_PCI_CFG56 \
- (0x00000000000000E0ull)
-#define CVMX_PCI_CFG57 \
- (0x00000000000000E4ull)
-#define CVMX_PCI_CFG58 \
- (0x00000000000000E8ull)
-#define CVMX_PCI_CFG59 \
- (0x00000000000000ECull)
-#define CVMX_PCI_CFG60 \
- (0x00000000000000F0ull)
-#define CVMX_PCI_CFG61 \
- (0x00000000000000F4ull)
-#define CVMX_PCI_CFG62 \
- (0x00000000000000F8ull)
-#define CVMX_PCI_CFG63 \
- (0x00000000000000FCull)
-#define CVMX_PCI_CNT_REG \
- (0x00000000000001B8ull)
-#define CVMX_PCI_CTL_STATUS_2 \
- (0x000000000000018Cull)
-#define CVMX_PCI_DBELL_0 \
- (0x0000000000000080ull)
-#define CVMX_PCI_DBELL_1 \
- (0x0000000000000088ull)
-#define CVMX_PCI_DBELL_2 \
- (0x0000000000000090ull)
-#define CVMX_PCI_DBELL_3 \
- (0x0000000000000098ull)
-#define CVMX_PCI_DBELL_X(offset) \
- (0x0000000000000080ull + (((offset) & 3) * 8))
-#define CVMX_PCI_DMA_CNT0 \
- (0x00000000000000A0ull)
-#define CVMX_PCI_DMA_CNT1 \
- (0x00000000000000A8ull)
-#define CVMX_PCI_DMA_CNTX(offset) \
- (0x00000000000000A0ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_INT_LEV0 \
- (0x00000000000000A4ull)
-#define CVMX_PCI_DMA_INT_LEV1 \
- (0x00000000000000ACull)
-#define CVMX_PCI_DMA_INT_LEVX(offset) \
- (0x00000000000000A4ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_TIME0 \
- (0x00000000000000B0ull)
-#define CVMX_PCI_DMA_TIME1 \
- (0x00000000000000B4ull)
-#define CVMX_PCI_DMA_TIMEX(offset) \
- (0x00000000000000B0ull + (((offset) & 1) * 4))
-#define CVMX_PCI_INSTR_COUNT0 \
- (0x0000000000000084ull)
-#define CVMX_PCI_INSTR_COUNT1 \
- (0x000000000000008Cull)
-#define CVMX_PCI_INSTR_COUNT2 \
- (0x0000000000000094ull)
-#define CVMX_PCI_INSTR_COUNT3 \
- (0x000000000000009Cull)
-#define CVMX_PCI_INSTR_COUNTX(offset) \
- (0x0000000000000084ull + (((offset) & 3) * 8))
-#define CVMX_PCI_INT_ENB \
- (0x0000000000000038ull)
-#define CVMX_PCI_INT_ENB2 \
- (0x00000000000001A0ull)
-#define CVMX_PCI_INT_SUM \
- (0x0000000000000030ull)
-#define CVMX_PCI_INT_SUM2 \
- (0x0000000000000198ull)
-#define CVMX_PCI_MSI_RCV \
- (0x00000000000000F0ull)
-#define CVMX_PCI_PKTS_SENT0 \
- (0x0000000000000040ull)
-#define CVMX_PCI_PKTS_SENT1 \
- (0x0000000000000050ull)
-#define CVMX_PCI_PKTS_SENT2 \
- (0x0000000000000060ull)
-#define CVMX_PCI_PKTS_SENT3 \
- (0x0000000000000070ull)
-#define CVMX_PCI_PKTS_SENTX(offset) \
- (0x0000000000000040ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
- (0x0000000000000048ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
- (0x0000000000000058ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
- (0x0000000000000068ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
- (0x0000000000000078ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
- (0x0000000000000048ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_TIME0 \
- (0x000000000000004Cull)
-#define CVMX_PCI_PKTS_SENT_TIME1 \
- (0x000000000000005Cull)
-#define CVMX_PCI_PKTS_SENT_TIME2 \
- (0x000000000000006Cull)
-#define CVMX_PCI_PKTS_SENT_TIME3 \
- (0x000000000000007Cull)
-#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
- (0x000000000000004Cull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKT_CREDITS0 \
- (0x0000000000000044ull)
-#define CVMX_PCI_PKT_CREDITS1 \
- (0x0000000000000054ull)
-#define CVMX_PCI_PKT_CREDITS2 \
- (0x0000000000000064ull)
-#define CVMX_PCI_PKT_CREDITS3 \
- (0x0000000000000074ull)
-#define CVMX_PCI_PKT_CREDITSX(offset) \
- (0x0000000000000044ull + (((offset) & 3) * 16))
-#define CVMX_PCI_READ_CMD_6 \
- (0x0000000000000180ull)
-#define CVMX_PCI_READ_CMD_C \
- (0x0000000000000184ull)
-#define CVMX_PCI_READ_CMD_E \
- (0x0000000000000188ull)
-#define CVMX_PCI_READ_TIMEOUT \
- CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
-#define CVMX_PCI_SCM_REG \
- (0x00000000000001A8ull)
-#define CVMX_PCI_TSR_REG \
- (0x00000000000001B0ull)
-#define CVMX_PCI_WIN_RD_ADDR \
- (0x0000000000000008ull)
-#define CVMX_PCI_WIN_RD_DATA \
- (0x0000000000000020ull)
-#define CVMX_PCI_WIN_WR_ADDR \
- (0x0000000000000000ull)
-#define CVMX_PCI_WIN_WR_DATA \
- (0x0000000000000010ull)
-#define CVMX_PCI_WIN_WR_MASK \
- (0x0000000000000018ull)
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
union cvmx_pci_bar1_indexx {
uint32_t u32;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_PCIERCX_DEFS_H__
#define __CVMX_PCIERCX_DEFS_H__
-#define CVMX_PCIERCX_CFG000(offset) \
- (0x0000000000000000ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG001(offset) \
- (0x0000000000000004ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG002(offset) \
- (0x0000000000000008ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG003(offset) \
- (0x000000000000000Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG004(offset) \
- (0x0000000000000010ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG005(offset) \
- (0x0000000000000014ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG006(offset) \
- (0x0000000000000018ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG007(offset) \
- (0x000000000000001Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG008(offset) \
- (0x0000000000000020ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG009(offset) \
- (0x0000000000000024ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG010(offset) \
- (0x0000000000000028ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG011(offset) \
- (0x000000000000002Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG012(offset) \
- (0x0000000000000030ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG013(offset) \
- (0x0000000000000034ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG014(offset) \
- (0x0000000000000038ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG015(offset) \
- (0x000000000000003Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG016(offset) \
- (0x0000000000000040ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG017(offset) \
- (0x0000000000000044ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG020(offset) \
- (0x0000000000000050ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG021(offset) \
- (0x0000000000000054ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG022(offset) \
- (0x0000000000000058ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG023(offset) \
- (0x000000000000005Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG028(offset) \
- (0x0000000000000070ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG029(offset) \
- (0x0000000000000074ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG030(offset) \
- (0x0000000000000078ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG031(offset) \
- (0x000000000000007Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG032(offset) \
- (0x0000000000000080ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG033(offset) \
- (0x0000000000000084ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG034(offset) \
- (0x0000000000000088ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG035(offset) \
- (0x000000000000008Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG036(offset) \
- (0x0000000000000090ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG037(offset) \
- (0x0000000000000094ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG038(offset) \
- (0x0000000000000098ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG039(offset) \
- (0x000000000000009Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG040(offset) \
- (0x00000000000000A0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG041(offset) \
- (0x00000000000000A4ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG042(offset) \
- (0x00000000000000A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG064(offset) \
- (0x0000000000000100ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG065(offset) \
- (0x0000000000000104ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG066(offset) \
- (0x0000000000000108ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG067(offset) \
- (0x000000000000010Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG068(offset) \
- (0x0000000000000110ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG069(offset) \
- (0x0000000000000114ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG070(offset) \
- (0x0000000000000118ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG071(offset) \
- (0x000000000000011Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG072(offset) \
- (0x0000000000000120ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG073(offset) \
- (0x0000000000000124ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG074(offset) \
- (0x0000000000000128ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG075(offset) \
- (0x000000000000012Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG076(offset) \
- (0x0000000000000130ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG077(offset) \
- (0x0000000000000134ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG448(offset) \
- (0x0000000000000700ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG449(offset) \
- (0x0000000000000704ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG450(offset) \
- (0x0000000000000708ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG451(offset) \
- (0x000000000000070Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG452(offset) \
- (0x0000000000000710ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG453(offset) \
- (0x0000000000000714ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG454(offset) \
- (0x0000000000000718ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG455(offset) \
- (0x000000000000071Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG456(offset) \
- (0x0000000000000720ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG458(offset) \
- (0x0000000000000728ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG459(offset) \
- (0x000000000000072Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG460(offset) \
- (0x0000000000000730ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG461(offset) \
- (0x0000000000000734ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG462(offset) \
- (0x0000000000000738ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG463(offset) \
- (0x000000000000073Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG464(offset) \
- (0x0000000000000740ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG465(offset) \
- (0x0000000000000744ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG466(offset) \
- (0x0000000000000748ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG467(offset) \
- (0x000000000000074Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG468(offset) \
- (0x0000000000000750ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG490(offset) \
- (0x00000000000007A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG491(offset) \
- (0x00000000000007ACull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG492(offset) \
- (0x00000000000007B0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG516(offset) \
- (0x0000000000000810ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG517(offset) \
- (0x0000000000000814ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
+#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
+#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
+#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
+#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
+#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
+#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
+#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
+#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
+#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
+#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
+#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
+#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
+#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
+#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
+#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
+#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
+#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
+#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
+#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
+#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
+#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
+#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
+#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
+#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
+#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
+#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
+#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
+#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
+#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
+#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
+#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
+#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
+#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
+#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
+#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
+#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
+#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
+#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
+#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
+#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
+#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
+#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
+#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
union cvmx_pciercx_cfg000 {
uint32_t u32;
struct cvmx_pciercx_cfg000_s cn52xxp1;
struct cvmx_pciercx_cfg000_s cn56xx;
struct cvmx_pciercx_cfg000_s cn56xxp1;
+ struct cvmx_pciercx_cfg000_s cn63xx;
+ struct cvmx_pciercx_cfg000_s cn63xxp1;
};
union cvmx_pciercx_cfg001 {
struct cvmx_pciercx_cfg001_s cn52xxp1;
struct cvmx_pciercx_cfg001_s cn56xx;
struct cvmx_pciercx_cfg001_s cn56xxp1;
+ struct cvmx_pciercx_cfg001_s cn63xx;
+ struct cvmx_pciercx_cfg001_s cn63xxp1;
};
union cvmx_pciercx_cfg002 {
struct cvmx_pciercx_cfg002_s cn52xxp1;
struct cvmx_pciercx_cfg002_s cn56xx;
struct cvmx_pciercx_cfg002_s cn56xxp1;
+ struct cvmx_pciercx_cfg002_s cn63xx;
+ struct cvmx_pciercx_cfg002_s cn63xxp1;
};
union cvmx_pciercx_cfg003 {
struct cvmx_pciercx_cfg003_s cn52xxp1;
struct cvmx_pciercx_cfg003_s cn56xx;
struct cvmx_pciercx_cfg003_s cn56xxp1;
+ struct cvmx_pciercx_cfg003_s cn63xx;
+ struct cvmx_pciercx_cfg003_s cn63xxp1;
};
union cvmx_pciercx_cfg004 {
struct cvmx_pciercx_cfg004_s cn52xxp1;
struct cvmx_pciercx_cfg004_s cn56xx;
struct cvmx_pciercx_cfg004_s cn56xxp1;
+ struct cvmx_pciercx_cfg004_s cn63xx;
+ struct cvmx_pciercx_cfg004_s cn63xxp1;
};
union cvmx_pciercx_cfg005 {
struct cvmx_pciercx_cfg005_s cn52xxp1;
struct cvmx_pciercx_cfg005_s cn56xx;
struct cvmx_pciercx_cfg005_s cn56xxp1;
+ struct cvmx_pciercx_cfg005_s cn63xx;
+ struct cvmx_pciercx_cfg005_s cn63xxp1;
};
union cvmx_pciercx_cfg006 {
struct cvmx_pciercx_cfg006_s cn52xxp1;
struct cvmx_pciercx_cfg006_s cn56xx;
struct cvmx_pciercx_cfg006_s cn56xxp1;
+ struct cvmx_pciercx_cfg006_s cn63xx;
+ struct cvmx_pciercx_cfg006_s cn63xxp1;
};
union cvmx_pciercx_cfg007 {
struct cvmx_pciercx_cfg007_s cn52xxp1;
struct cvmx_pciercx_cfg007_s cn56xx;
struct cvmx_pciercx_cfg007_s cn56xxp1;
+ struct cvmx_pciercx_cfg007_s cn63xx;
+ struct cvmx_pciercx_cfg007_s cn63xxp1;
};
union cvmx_pciercx_cfg008 {
struct cvmx_pciercx_cfg008_s cn52xxp1;
struct cvmx_pciercx_cfg008_s cn56xx;
struct cvmx_pciercx_cfg008_s cn56xxp1;
+ struct cvmx_pciercx_cfg008_s cn63xx;
+ struct cvmx_pciercx_cfg008_s cn63xxp1;
};
union cvmx_pciercx_cfg009 {
struct cvmx_pciercx_cfg009_s cn52xxp1;
struct cvmx_pciercx_cfg009_s cn56xx;
struct cvmx_pciercx_cfg009_s cn56xxp1;
+ struct cvmx_pciercx_cfg009_s cn63xx;
+ struct cvmx_pciercx_cfg009_s cn63xxp1;
};
union cvmx_pciercx_cfg010 {
struct cvmx_pciercx_cfg010_s cn52xxp1;
struct cvmx_pciercx_cfg010_s cn56xx;
struct cvmx_pciercx_cfg010_s cn56xxp1;
+ struct cvmx_pciercx_cfg010_s cn63xx;
+ struct cvmx_pciercx_cfg010_s cn63xxp1;
};
union cvmx_pciercx_cfg011 {
struct cvmx_pciercx_cfg011_s cn52xxp1;
struct cvmx_pciercx_cfg011_s cn56xx;
struct cvmx_pciercx_cfg011_s cn56xxp1;
+ struct cvmx_pciercx_cfg011_s cn63xx;
+ struct cvmx_pciercx_cfg011_s cn63xxp1;
};
union cvmx_pciercx_cfg012 {
struct cvmx_pciercx_cfg012_s cn52xxp1;
struct cvmx_pciercx_cfg012_s cn56xx;
struct cvmx_pciercx_cfg012_s cn56xxp1;
+ struct cvmx_pciercx_cfg012_s cn63xx;
+ struct cvmx_pciercx_cfg012_s cn63xxp1;
};
union cvmx_pciercx_cfg013 {
struct cvmx_pciercx_cfg013_s cn52xxp1;
struct cvmx_pciercx_cfg013_s cn56xx;
struct cvmx_pciercx_cfg013_s cn56xxp1;
+ struct cvmx_pciercx_cfg013_s cn63xx;
+ struct cvmx_pciercx_cfg013_s cn63xxp1;
};
union cvmx_pciercx_cfg014 {
struct cvmx_pciercx_cfg014_s cn52xxp1;
struct cvmx_pciercx_cfg014_s cn56xx;
struct cvmx_pciercx_cfg014_s cn56xxp1;
+ struct cvmx_pciercx_cfg014_s cn63xx;
+ struct cvmx_pciercx_cfg014_s cn63xxp1;
};
union cvmx_pciercx_cfg015 {
struct cvmx_pciercx_cfg015_s cn52xxp1;
struct cvmx_pciercx_cfg015_s cn56xx;
struct cvmx_pciercx_cfg015_s cn56xxp1;
+ struct cvmx_pciercx_cfg015_s cn63xx;
+ struct cvmx_pciercx_cfg015_s cn63xxp1;
};
union cvmx_pciercx_cfg016 {
struct cvmx_pciercx_cfg016_s cn52xxp1;
struct cvmx_pciercx_cfg016_s cn56xx;
struct cvmx_pciercx_cfg016_s cn56xxp1;
+ struct cvmx_pciercx_cfg016_s cn63xx;
+ struct cvmx_pciercx_cfg016_s cn63xxp1;
};
union cvmx_pciercx_cfg017 {
struct cvmx_pciercx_cfg017_s cn52xxp1;
struct cvmx_pciercx_cfg017_s cn56xx;
struct cvmx_pciercx_cfg017_s cn56xxp1;
+ struct cvmx_pciercx_cfg017_s cn63xx;
+ struct cvmx_pciercx_cfg017_s cn63xxp1;
};
union cvmx_pciercx_cfg020 {
struct cvmx_pciercx_cfg020_s cn52xxp1;
struct cvmx_pciercx_cfg020_s cn56xx;
struct cvmx_pciercx_cfg020_s cn56xxp1;
+ struct cvmx_pciercx_cfg020_s cn63xx;
+ struct cvmx_pciercx_cfg020_s cn63xxp1;
};
union cvmx_pciercx_cfg021 {
struct cvmx_pciercx_cfg021_s cn52xxp1;
struct cvmx_pciercx_cfg021_s cn56xx;
struct cvmx_pciercx_cfg021_s cn56xxp1;
+ struct cvmx_pciercx_cfg021_s cn63xx;
+ struct cvmx_pciercx_cfg021_s cn63xxp1;
};
union cvmx_pciercx_cfg022 {
struct cvmx_pciercx_cfg022_s cn52xxp1;
struct cvmx_pciercx_cfg022_s cn56xx;
struct cvmx_pciercx_cfg022_s cn56xxp1;
+ struct cvmx_pciercx_cfg022_s cn63xx;
+ struct cvmx_pciercx_cfg022_s cn63xxp1;
};
union cvmx_pciercx_cfg023 {
struct cvmx_pciercx_cfg023_s cn52xxp1;
struct cvmx_pciercx_cfg023_s cn56xx;
struct cvmx_pciercx_cfg023_s cn56xxp1;
+ struct cvmx_pciercx_cfg023_s cn63xx;
+ struct cvmx_pciercx_cfg023_s cn63xxp1;
};
union cvmx_pciercx_cfg028 {
struct cvmx_pciercx_cfg028_s cn52xxp1;
struct cvmx_pciercx_cfg028_s cn56xx;
struct cvmx_pciercx_cfg028_s cn56xxp1;
+ struct cvmx_pciercx_cfg028_s cn63xx;
+ struct cvmx_pciercx_cfg028_s cn63xxp1;
};
union cvmx_pciercx_cfg029 {
struct cvmx_pciercx_cfg029_s cn52xxp1;
struct cvmx_pciercx_cfg029_s cn56xx;
struct cvmx_pciercx_cfg029_s cn56xxp1;
+ struct cvmx_pciercx_cfg029_s cn63xx;
+ struct cvmx_pciercx_cfg029_s cn63xxp1;
};
union cvmx_pciercx_cfg030 {
struct cvmx_pciercx_cfg030_s cn52xxp1;
struct cvmx_pciercx_cfg030_s cn56xx;
struct cvmx_pciercx_cfg030_s cn56xxp1;
+ struct cvmx_pciercx_cfg030_s cn63xx;
+ struct cvmx_pciercx_cfg030_s cn63xxp1;
};
union cvmx_pciercx_cfg031 {
struct cvmx_pciercx_cfg031_s cn52xxp1;
struct cvmx_pciercx_cfg031_s cn56xx;
struct cvmx_pciercx_cfg031_s cn56xxp1;
+ struct cvmx_pciercx_cfg031_s cn63xx;
+ struct cvmx_pciercx_cfg031_s cn63xxp1;
};
union cvmx_pciercx_cfg032 {
struct cvmx_pciercx_cfg032_s cn52xxp1;
struct cvmx_pciercx_cfg032_s cn56xx;
struct cvmx_pciercx_cfg032_s cn56xxp1;
+ struct cvmx_pciercx_cfg032_s cn63xx;
+ struct cvmx_pciercx_cfg032_s cn63xxp1;
};
union cvmx_pciercx_cfg033 {
struct cvmx_pciercx_cfg033_s cn52xxp1;
struct cvmx_pciercx_cfg033_s cn56xx;
struct cvmx_pciercx_cfg033_s cn56xxp1;
+ struct cvmx_pciercx_cfg033_s cn63xx;
+ struct cvmx_pciercx_cfg033_s cn63xxp1;
};
union cvmx_pciercx_cfg034 {
struct cvmx_pciercx_cfg034_s cn52xxp1;
struct cvmx_pciercx_cfg034_s cn56xx;
struct cvmx_pciercx_cfg034_s cn56xxp1;
+ struct cvmx_pciercx_cfg034_s cn63xx;
+ struct cvmx_pciercx_cfg034_s cn63xxp1;
};
union cvmx_pciercx_cfg035 {
struct cvmx_pciercx_cfg035_s cn52xxp1;
struct cvmx_pciercx_cfg035_s cn56xx;
struct cvmx_pciercx_cfg035_s cn56xxp1;
+ struct cvmx_pciercx_cfg035_s cn63xx;
+ struct cvmx_pciercx_cfg035_s cn63xxp1;
};
union cvmx_pciercx_cfg036 {
struct cvmx_pciercx_cfg036_s cn52xxp1;
struct cvmx_pciercx_cfg036_s cn56xx;
struct cvmx_pciercx_cfg036_s cn56xxp1;
+ struct cvmx_pciercx_cfg036_s cn63xx;
+ struct cvmx_pciercx_cfg036_s cn63xxp1;
};
union cvmx_pciercx_cfg037 {
struct cvmx_pciercx_cfg037_s cn52xxp1;
struct cvmx_pciercx_cfg037_s cn56xx;
struct cvmx_pciercx_cfg037_s cn56xxp1;
+ struct cvmx_pciercx_cfg037_s cn63xx;
+ struct cvmx_pciercx_cfg037_s cn63xxp1;
};
union cvmx_pciercx_cfg038 {
struct cvmx_pciercx_cfg038_s cn52xxp1;
struct cvmx_pciercx_cfg038_s cn56xx;
struct cvmx_pciercx_cfg038_s cn56xxp1;
+ struct cvmx_pciercx_cfg038_s cn63xx;
+ struct cvmx_pciercx_cfg038_s cn63xxp1;
};
union cvmx_pciercx_cfg039 {
uint32_t u32;
struct cvmx_pciercx_cfg039_s {
- uint32_t reserved_0_31:32;
+ uint32_t reserved_9_31:23;
+ uint32_t cls:1;
+ uint32_t slsv:7;
+ uint32_t reserved_0_0:1;
} s;
- struct cvmx_pciercx_cfg039_s cn52xx;
- struct cvmx_pciercx_cfg039_s cn52xxp1;
- struct cvmx_pciercx_cfg039_s cn56xx;
- struct cvmx_pciercx_cfg039_s cn56xxp1;
+ struct cvmx_pciercx_cfg039_cn52xx {
+ uint32_t reserved_0_31:32;
+ } cn52xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg039_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg039_s cn63xx;
+ struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
};
union cvmx_pciercx_cfg040 {
uint32_t u32;
struct cvmx_pciercx_cfg040_s {
+ uint32_t reserved_17_31:15;
+ uint32_t cdl:1;
+ uint32_t reserved_13_15:3;
+ uint32_t cde:1;
+ uint32_t csos:1;
+ uint32_t emc:1;
+ uint32_t tm:3;
+ uint32_t sde:1;
+ uint32_t hasd:1;
+ uint32_t ec:1;
+ uint32_t tls:4;
+ } s;
+ struct cvmx_pciercx_cfg040_cn52xx {
uint32_t reserved_0_31:32;
- } s;
- struct cvmx_pciercx_cfg040_s cn52xx;
- struct cvmx_pciercx_cfg040_s cn52xxp1;
- struct cvmx_pciercx_cfg040_s cn56xx;
- struct cvmx_pciercx_cfg040_s cn56xxp1;
+ } cn52xx;
+ struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg040_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg040_s cn63xx;
+ struct cvmx_pciercx_cfg040_s cn63xxp1;
};
union cvmx_pciercx_cfg041 {
struct cvmx_pciercx_cfg041_s cn52xxp1;
struct cvmx_pciercx_cfg041_s cn56xx;
struct cvmx_pciercx_cfg041_s cn56xxp1;
+ struct cvmx_pciercx_cfg041_s cn63xx;
+ struct cvmx_pciercx_cfg041_s cn63xxp1;
};
union cvmx_pciercx_cfg042 {
struct cvmx_pciercx_cfg042_s cn52xxp1;
struct cvmx_pciercx_cfg042_s cn56xx;
struct cvmx_pciercx_cfg042_s cn56xxp1;
+ struct cvmx_pciercx_cfg042_s cn63xx;
+ struct cvmx_pciercx_cfg042_s cn63xxp1;
};
union cvmx_pciercx_cfg064 {
struct cvmx_pciercx_cfg064_s cn52xxp1;
struct cvmx_pciercx_cfg064_s cn56xx;
struct cvmx_pciercx_cfg064_s cn56xxp1;
+ struct cvmx_pciercx_cfg064_s cn63xx;
+ struct cvmx_pciercx_cfg064_s cn63xxp1;
};
union cvmx_pciercx_cfg065 {
struct cvmx_pciercx_cfg065_s cn52xxp1;
struct cvmx_pciercx_cfg065_s cn56xx;
struct cvmx_pciercx_cfg065_s cn56xxp1;
+ struct cvmx_pciercx_cfg065_s cn63xx;
+ struct cvmx_pciercx_cfg065_s cn63xxp1;
};
union cvmx_pciercx_cfg066 {
struct cvmx_pciercx_cfg066_s cn52xxp1;
struct cvmx_pciercx_cfg066_s cn56xx;
struct cvmx_pciercx_cfg066_s cn56xxp1;
+ struct cvmx_pciercx_cfg066_s cn63xx;
+ struct cvmx_pciercx_cfg066_s cn63xxp1;
};
union cvmx_pciercx_cfg067 {
struct cvmx_pciercx_cfg067_s cn52xxp1;
struct cvmx_pciercx_cfg067_s cn56xx;
struct cvmx_pciercx_cfg067_s cn56xxp1;
+ struct cvmx_pciercx_cfg067_s cn63xx;
+ struct cvmx_pciercx_cfg067_s cn63xxp1;
};
union cvmx_pciercx_cfg068 {
struct cvmx_pciercx_cfg068_s cn52xxp1;
struct cvmx_pciercx_cfg068_s cn56xx;
struct cvmx_pciercx_cfg068_s cn56xxp1;
+ struct cvmx_pciercx_cfg068_s cn63xx;
+ struct cvmx_pciercx_cfg068_s cn63xxp1;
};
union cvmx_pciercx_cfg069 {
struct cvmx_pciercx_cfg069_s cn52xxp1;
struct cvmx_pciercx_cfg069_s cn56xx;
struct cvmx_pciercx_cfg069_s cn56xxp1;
+ struct cvmx_pciercx_cfg069_s cn63xx;
+ struct cvmx_pciercx_cfg069_s cn63xxp1;
};
union cvmx_pciercx_cfg070 {
struct cvmx_pciercx_cfg070_s cn52xxp1;
struct cvmx_pciercx_cfg070_s cn56xx;
struct cvmx_pciercx_cfg070_s cn56xxp1;
+ struct cvmx_pciercx_cfg070_s cn63xx;
+ struct cvmx_pciercx_cfg070_s cn63xxp1;
};
union cvmx_pciercx_cfg071 {
struct cvmx_pciercx_cfg071_s cn52xxp1;
struct cvmx_pciercx_cfg071_s cn56xx;
struct cvmx_pciercx_cfg071_s cn56xxp1;
+ struct cvmx_pciercx_cfg071_s cn63xx;
+ struct cvmx_pciercx_cfg071_s cn63xxp1;
};
union cvmx_pciercx_cfg072 {
struct cvmx_pciercx_cfg072_s cn52xxp1;
struct cvmx_pciercx_cfg072_s cn56xx;
struct cvmx_pciercx_cfg072_s cn56xxp1;
+ struct cvmx_pciercx_cfg072_s cn63xx;
+ struct cvmx_pciercx_cfg072_s cn63xxp1;
};
union cvmx_pciercx_cfg073 {
struct cvmx_pciercx_cfg073_s cn52xxp1;
struct cvmx_pciercx_cfg073_s cn56xx;
struct cvmx_pciercx_cfg073_s cn56xxp1;
+ struct cvmx_pciercx_cfg073_s cn63xx;
+ struct cvmx_pciercx_cfg073_s cn63xxp1;
};
union cvmx_pciercx_cfg074 {
struct cvmx_pciercx_cfg074_s cn52xxp1;
struct cvmx_pciercx_cfg074_s cn56xx;
struct cvmx_pciercx_cfg074_s cn56xxp1;
+ struct cvmx_pciercx_cfg074_s cn63xx;
+ struct cvmx_pciercx_cfg074_s cn63xxp1;
};
union cvmx_pciercx_cfg075 {
struct cvmx_pciercx_cfg075_s cn52xxp1;
struct cvmx_pciercx_cfg075_s cn56xx;
struct cvmx_pciercx_cfg075_s cn56xxp1;
+ struct cvmx_pciercx_cfg075_s cn63xx;
+ struct cvmx_pciercx_cfg075_s cn63xxp1;
};
union cvmx_pciercx_cfg076 {
struct cvmx_pciercx_cfg076_s cn52xxp1;
struct cvmx_pciercx_cfg076_s cn56xx;
struct cvmx_pciercx_cfg076_s cn56xxp1;
+ struct cvmx_pciercx_cfg076_s cn63xx;
+ struct cvmx_pciercx_cfg076_s cn63xxp1;
};
union cvmx_pciercx_cfg077 {
struct cvmx_pciercx_cfg077_s cn52xxp1;
struct cvmx_pciercx_cfg077_s cn56xx;
struct cvmx_pciercx_cfg077_s cn56xxp1;
+ struct cvmx_pciercx_cfg077_s cn63xx;
+ struct cvmx_pciercx_cfg077_s cn63xxp1;
};
union cvmx_pciercx_cfg448 {
struct cvmx_pciercx_cfg448_s cn52xxp1;
struct cvmx_pciercx_cfg448_s cn56xx;
struct cvmx_pciercx_cfg448_s cn56xxp1;
+ struct cvmx_pciercx_cfg448_s cn63xx;
+ struct cvmx_pciercx_cfg448_s cn63xxp1;
};
union cvmx_pciercx_cfg449 {
struct cvmx_pciercx_cfg449_s cn52xxp1;
struct cvmx_pciercx_cfg449_s cn56xx;
struct cvmx_pciercx_cfg449_s cn56xxp1;
+ struct cvmx_pciercx_cfg449_s cn63xx;
+ struct cvmx_pciercx_cfg449_s cn63xxp1;
};
union cvmx_pciercx_cfg450 {
struct cvmx_pciercx_cfg450_s cn52xxp1;
struct cvmx_pciercx_cfg450_s cn56xx;
struct cvmx_pciercx_cfg450_s cn56xxp1;
+ struct cvmx_pciercx_cfg450_s cn63xx;
+ struct cvmx_pciercx_cfg450_s cn63xxp1;
};
union cvmx_pciercx_cfg451 {
struct cvmx_pciercx_cfg451_s cn52xxp1;
struct cvmx_pciercx_cfg451_s cn56xx;
struct cvmx_pciercx_cfg451_s cn56xxp1;
+ struct cvmx_pciercx_cfg451_s cn63xx;
+ struct cvmx_pciercx_cfg451_s cn63xxp1;
};
union cvmx_pciercx_cfg452 {
struct cvmx_pciercx_cfg452_s cn52xxp1;
struct cvmx_pciercx_cfg452_s cn56xx;
struct cvmx_pciercx_cfg452_s cn56xxp1;
+ struct cvmx_pciercx_cfg452_s cn63xx;
+ struct cvmx_pciercx_cfg452_s cn63xxp1;
};
union cvmx_pciercx_cfg453 {
struct cvmx_pciercx_cfg453_s cn52xxp1;
struct cvmx_pciercx_cfg453_s cn56xx;
struct cvmx_pciercx_cfg453_s cn56xxp1;
+ struct cvmx_pciercx_cfg453_s cn63xx;
+ struct cvmx_pciercx_cfg453_s cn63xxp1;
};
union cvmx_pciercx_cfg454 {
struct cvmx_pciercx_cfg454_s cn52xxp1;
struct cvmx_pciercx_cfg454_s cn56xx;
struct cvmx_pciercx_cfg454_s cn56xxp1;
+ struct cvmx_pciercx_cfg454_s cn63xx;
+ struct cvmx_pciercx_cfg454_s cn63xxp1;
};
union cvmx_pciercx_cfg455 {
struct cvmx_pciercx_cfg455_s cn52xxp1;
struct cvmx_pciercx_cfg455_s cn56xx;
struct cvmx_pciercx_cfg455_s cn56xxp1;
+ struct cvmx_pciercx_cfg455_s cn63xx;
+ struct cvmx_pciercx_cfg455_s cn63xxp1;
};
union cvmx_pciercx_cfg456 {
struct cvmx_pciercx_cfg456_s cn52xxp1;
struct cvmx_pciercx_cfg456_s cn56xx;
struct cvmx_pciercx_cfg456_s cn56xxp1;
+ struct cvmx_pciercx_cfg456_s cn63xx;
+ struct cvmx_pciercx_cfg456_s cn63xxp1;
};
union cvmx_pciercx_cfg458 {
struct cvmx_pciercx_cfg458_s cn52xxp1;
struct cvmx_pciercx_cfg458_s cn56xx;
struct cvmx_pciercx_cfg458_s cn56xxp1;
+ struct cvmx_pciercx_cfg458_s cn63xx;
+ struct cvmx_pciercx_cfg458_s cn63xxp1;
};
union cvmx_pciercx_cfg459 {
struct cvmx_pciercx_cfg459_s cn52xxp1;
struct cvmx_pciercx_cfg459_s cn56xx;
struct cvmx_pciercx_cfg459_s cn56xxp1;
+ struct cvmx_pciercx_cfg459_s cn63xx;
+ struct cvmx_pciercx_cfg459_s cn63xxp1;
};
union cvmx_pciercx_cfg460 {
struct cvmx_pciercx_cfg460_s cn52xxp1;
struct cvmx_pciercx_cfg460_s cn56xx;
struct cvmx_pciercx_cfg460_s cn56xxp1;
+ struct cvmx_pciercx_cfg460_s cn63xx;
+ struct cvmx_pciercx_cfg460_s cn63xxp1;
};
union cvmx_pciercx_cfg461 {
struct cvmx_pciercx_cfg461_s cn52xxp1;
struct cvmx_pciercx_cfg461_s cn56xx;
struct cvmx_pciercx_cfg461_s cn56xxp1;
+ struct cvmx_pciercx_cfg461_s cn63xx;
+ struct cvmx_pciercx_cfg461_s cn63xxp1;
};
union cvmx_pciercx_cfg462 {
struct cvmx_pciercx_cfg462_s cn52xxp1;
struct cvmx_pciercx_cfg462_s cn56xx;
struct cvmx_pciercx_cfg462_s cn56xxp1;
+ struct cvmx_pciercx_cfg462_s cn63xx;
+ struct cvmx_pciercx_cfg462_s cn63xxp1;
};
union cvmx_pciercx_cfg463 {
struct cvmx_pciercx_cfg463_s cn52xxp1;
struct cvmx_pciercx_cfg463_s cn56xx;
struct cvmx_pciercx_cfg463_s cn56xxp1;
+ struct cvmx_pciercx_cfg463_s cn63xx;
+ struct cvmx_pciercx_cfg463_s cn63xxp1;
};
union cvmx_pciercx_cfg464 {
struct cvmx_pciercx_cfg464_s cn52xxp1;
struct cvmx_pciercx_cfg464_s cn56xx;
struct cvmx_pciercx_cfg464_s cn56xxp1;
+ struct cvmx_pciercx_cfg464_s cn63xx;
+ struct cvmx_pciercx_cfg464_s cn63xxp1;
};
union cvmx_pciercx_cfg465 {
struct cvmx_pciercx_cfg465_s cn52xxp1;
struct cvmx_pciercx_cfg465_s cn56xx;
struct cvmx_pciercx_cfg465_s cn56xxp1;
+ struct cvmx_pciercx_cfg465_s cn63xx;
+ struct cvmx_pciercx_cfg465_s cn63xxp1;
};
union cvmx_pciercx_cfg466 {
struct cvmx_pciercx_cfg466_s cn52xxp1;
struct cvmx_pciercx_cfg466_s cn56xx;
struct cvmx_pciercx_cfg466_s cn56xxp1;
+ struct cvmx_pciercx_cfg466_s cn63xx;
+ struct cvmx_pciercx_cfg466_s cn63xxp1;
};
union cvmx_pciercx_cfg467 {
struct cvmx_pciercx_cfg467_s cn52xxp1;
struct cvmx_pciercx_cfg467_s cn56xx;
struct cvmx_pciercx_cfg467_s cn56xxp1;
+ struct cvmx_pciercx_cfg467_s cn63xx;
+ struct cvmx_pciercx_cfg467_s cn63xxp1;
};
union cvmx_pciercx_cfg468 {
struct cvmx_pciercx_cfg468_s cn52xxp1;
struct cvmx_pciercx_cfg468_s cn56xx;
struct cvmx_pciercx_cfg468_s cn56xxp1;
+ struct cvmx_pciercx_cfg468_s cn63xx;
+ struct cvmx_pciercx_cfg468_s cn63xxp1;
};
union cvmx_pciercx_cfg490 {
struct cvmx_pciercx_cfg490_s cn52xxp1;
struct cvmx_pciercx_cfg490_s cn56xx;
struct cvmx_pciercx_cfg490_s cn56xxp1;
+ struct cvmx_pciercx_cfg490_s cn63xx;
+ struct cvmx_pciercx_cfg490_s cn63xxp1;
};
union cvmx_pciercx_cfg491 {
struct cvmx_pciercx_cfg491_s cn52xxp1;
struct cvmx_pciercx_cfg491_s cn56xx;
struct cvmx_pciercx_cfg491_s cn56xxp1;
+ struct cvmx_pciercx_cfg491_s cn63xx;
+ struct cvmx_pciercx_cfg491_s cn63xxp1;
};
union cvmx_pciercx_cfg492 {
struct cvmx_pciercx_cfg492_s cn52xxp1;
struct cvmx_pciercx_cfg492_s cn56xx;
struct cvmx_pciercx_cfg492_s cn56xxp1;
+ struct cvmx_pciercx_cfg492_s cn63xx;
+ struct cvmx_pciercx_cfg492_s cn63xxp1;
+};
+
+union cvmx_pciercx_cfg515 {
+ uint32_t u32;
+ struct cvmx_pciercx_cfg515_s {
+ uint32_t reserved_21_31:11;
+ uint32_t s_d_e:1;
+ uint32_t ctcrb:1;
+ uint32_t cpyts:1;
+ uint32_t dsc:1;
+ uint32_t le:9;
+ uint32_t n_fts:8;
+ } s;
+ struct cvmx_pciercx_cfg515_s cn63xx;
+ struct cvmx_pciercx_cfg515_s cn63xxp1;
};
union cvmx_pciercx_cfg516 {
struct cvmx_pciercx_cfg516_s cn52xxp1;
struct cvmx_pciercx_cfg516_s cn56xx;
struct cvmx_pciercx_cfg516_s cn56xxp1;
+ struct cvmx_pciercx_cfg516_s cn63xx;
+ struct cvmx_pciercx_cfg516_s cn63xxp1;
};
union cvmx_pciercx_cfg517 {
struct cvmx_pciercx_cfg517_s cn52xxp1;
struct cvmx_pciercx_cfg517_s cn56xx;
struct cvmx_pciercx_cfg517_s cn56xxp1;
+ struct cvmx_pciercx_cfg517_s cn63xx;
+ struct cvmx_pciercx_cfg517_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_PESCX_DEFS_H__
#define __CVMX_PESCX_DEFS_H__
-#define CVMX_PESCX_BIST_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_BIST_STATUS2(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_RD(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_WR(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS2(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO_EN(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DIAG_STATUS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR0_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR1_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR2_START(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_TLP_CREDITS(block_id) \
- CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_pescx_bist_status {
uint64_t u64;
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_PEXP_DEFS_H__
#define __CVMX_PEXP_DEFS_H__
-#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000008580ull)
-#define CVMX_PEXP_NPEI_BIST_STATUS2 \
- CVMX_ADD_IO_SEG(0x00011F0000008680ull)
-#define CVMX_PEXP_NPEI_CTL_PORT0 \
- CVMX_ADD_IO_SEG(0x00011F0000008250ull)
-#define CVMX_PEXP_NPEI_CTL_PORT1 \
- CVMX_ADD_IO_SEG(0x00011F0000008260ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x00011F0000008570ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
-#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
- CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
-#define CVMX_PEXP_NPEI_DBG_DATA \
- CVMX_ADD_IO_SEG(0x00011F0000008510ull)
-#define CVMX_PEXP_NPEI_DBG_SELECT \
- CVMX_ADD_IO_SEG(0x00011F0000008500ull)
-#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
- CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
-#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
- CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
-#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMA_CNTS \
- CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
-#define CVMX_PEXP_NPEI_DMA_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000008560ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
-#define CVMX_PEXP_NPEI_INT_A_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000008550ull)
-#define CVMX_PEXP_NPEI_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000008540ull)
-#define CVMX_PEXP_NPEI_INT_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
-#define CVMX_PEXP_NPEI_INT_INFO \
- CVMX_ADD_IO_SEG(0x00011F0000008590ull)
-#define CVMX_PEXP_NPEI_INT_SUM \
- CVMX_ADD_IO_SEG(0x00011F0000008530ull)
-#define CVMX_PEXP_NPEI_INT_SUM2 \
- CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
- CVMX_ADD_IO_SEG(0x00011F0000008600ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
- CVMX_ADD_IO_SEG(0x00011F0000008610ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
- CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_PEXP_NPEI_MSI_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
-#define CVMX_PEXP_NPEI_MSI_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
-#define CVMX_PEXP_NPEI_MSI_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
-#define CVMX_PEXP_NPEI_MSI_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
-#define CVMX_PEXP_NPEI_MSI_RCV0 \
- CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
-#define CVMX_PEXP_NPEI_MSI_RCV1 \
- CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
-#define CVMX_PEXP_NPEI_MSI_RCV2 \
- CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
-#define CVMX_PEXP_NPEI_MSI_RCV3 \
- CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
-#define CVMX_PEXP_NPEI_MSI_RD_MAP \
- CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
- CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
- CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
- CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
- CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
-#define CVMX_PEXP_NPEI_MSI_WR_MAP \
- CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
-#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
- CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
- CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
- CVMX_ADD_IO_SEG(0x00011F0000008650ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
- CVMX_ADD_IO_SEG(0x00011F0000008660ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
- CVMX_ADD_IO_SEG(0x00011F0000008670ull)
-#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
- CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_CNT_INT \
- CVMX_ADD_IO_SEG(0x00011F0000009110ull)
-#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009130ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
- CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
- CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
- CVMX_ADD_IO_SEG(0x00011F0000009090ull)
-#define CVMX_PEXP_NPEI_PKT_DPADDR \
- CVMX_ADD_IO_SEG(0x00011F0000009080ull)
-#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
- CVMX_ADD_IO_SEG(0x00011F0000009150ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009000ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009190ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009020ull)
-#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
- CVMX_ADD_IO_SEG(0x00011F0000009100ull)
-#define CVMX_PEXP_NPEI_PKT_IN_BP \
- CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
- CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
- CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
- CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
-#define CVMX_PEXP_NPEI_PKT_IPTR \
- CVMX_ADD_IO_SEG(0x00011F0000009070ull)
-#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
- CVMX_ADD_IO_SEG(0x00011F0000009160ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
- CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009010ull)
-#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
- CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
-#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
- CVMX_ADD_IO_SEG(0x00011F0000008690ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
- CVMX_ADD_IO_SEG(0x00011F0000009050ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
- CVMX_ADD_IO_SEG(0x00011F0000009180ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
- CVMX_ADD_IO_SEG(0x00011F0000009040ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
- CVMX_ADD_IO_SEG(0x00011F0000009030ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT \
- CVMX_ADD_IO_SEG(0x00011F0000009120ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
- CVMX_ADD_IO_SEG(0x00011F0000009140ull)
-#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
- CVMX_ADD_IO_SEG(0x00011F0000008520ull)
-#define CVMX_PEXP_NPEI_SCRATCH_1 \
- CVMX_ADD_IO_SEG(0x00011F0000008270ull)
-#define CVMX_PEXP_NPEI_STATE1 \
- CVMX_ADD_IO_SEG(0x00011F0000008620ull)
-#define CVMX_PEXP_NPEI_STATE2 \
- CVMX_ADD_IO_SEG(0x00011F0000008630ull)
-#define CVMX_PEXP_NPEI_STATE3 \
- CVMX_ADD_IO_SEG(0x00011F0000008640ull)
-#define CVMX_PEXP_NPEI_WINDOW_CTL \
- CVMX_ADD_IO_SEG(0x00011F0000008380ull)
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_POW_DEFS_H__
#define __CVMX_POW_DEFS_H__
-#define CVMX_POW_BIST_STAT \
- CVMX_ADD_IO_SEG(0x00016700000003F8ull)
-#define CVMX_POW_DS_PC \
- CVMX_ADD_IO_SEG(0x0001670000000398ull)
-#define CVMX_POW_ECC_ERR \
- CVMX_ADD_IO_SEG(0x0001670000000218ull)
-#define CVMX_POW_INT_CTL \
- CVMX_ADD_IO_SEG(0x0001670000000220ull)
-#define CVMX_POW_IQ_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
-#define CVMX_POW_IQ_COM_CNT \
- CVMX_ADD_IO_SEG(0x0001670000000388ull)
-#define CVMX_POW_IQ_INT \
- CVMX_ADD_IO_SEG(0x0001670000000238ull)
-#define CVMX_POW_IQ_INT_EN \
- CVMX_ADD_IO_SEG(0x0001670000000240ull)
-#define CVMX_POW_IQ_THRX(offset) \
- CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
-#define CVMX_POW_NOS_CNT \
- CVMX_ADD_IO_SEG(0x0001670000000228ull)
-#define CVMX_POW_NW_TIM \
- CVMX_ADD_IO_SEG(0x0001670000000210ull)
-#define CVMX_POW_PF_RST_MSK \
- CVMX_ADD_IO_SEG(0x0001670000000230ull)
-#define CVMX_POW_PP_GRP_MSKX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
-#define CVMX_POW_QOS_RNDX(offset) \
- CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
-#define CVMX_POW_QOS_THRX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
-#define CVMX_POW_TS_PC \
- CVMX_ADD_IO_SEG(0x0001670000000390ull)
-#define CVMX_POW_WA_COM_PC \
- CVMX_ADD_IO_SEG(0x0001670000000380ull)
-#define CVMX_POW_WA_PCX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
-#define CVMX_POW_WQ_INT \
- CVMX_ADD_IO_SEG(0x0001670000000200ull)
-#define CVMX_POW_WQ_INT_CNTX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
-#define CVMX_POW_WQ_INT_PC \
- CVMX_ADD_IO_SEG(0x0001670000000208ull)
-#define CVMX_POW_WQ_INT_THRX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
-#define CVMX_POW_WS_PCX(offset) \
- CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
union cvmx_pow_bist_stat {
uint64_t u64;
struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
struct cvmx_pow_bist_stat_cn38xx cn58xx;
struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
+ struct cvmx_pow_bist_stat_cn63xx {
+ uint64_t reserved_22_63:42;
+ uint64_t pp:6;
+ uint64_t reserved_12_15:4;
+ uint64_t cam:1;
+ uint64_t nbr:3;
+ uint64_t nbt:4;
+ uint64_t index:1;
+ uint64_t fidx:1;
+ uint64_t pend:1;
+ uint64_t adr:1;
+ } cn63xx;
+ struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
};
union cvmx_pow_ds_pc {
struct cvmx_pow_ds_pc_s cn56xxp1;
struct cvmx_pow_ds_pc_s cn58xx;
struct cvmx_pow_ds_pc_s cn58xxp1;
+ struct cvmx_pow_ds_pc_s cn63xx;
+ struct cvmx_pow_ds_pc_s cn63xxp1;
};
union cvmx_pow_ecc_err {
struct cvmx_pow_ecc_err_s cn56xxp1;
struct cvmx_pow_ecc_err_s cn58xx;
struct cvmx_pow_ecc_err_s cn58xxp1;
+ struct cvmx_pow_ecc_err_s cn63xx;
+ struct cvmx_pow_ecc_err_s cn63xxp1;
};
union cvmx_pow_int_ctl {
struct cvmx_pow_int_ctl_s cn56xxp1;
struct cvmx_pow_int_ctl_s cn58xx;
struct cvmx_pow_int_ctl_s cn58xxp1;
+ struct cvmx_pow_int_ctl_s cn63xx;
+ struct cvmx_pow_int_ctl_s cn63xxp1;
};
union cvmx_pow_iq_cntx {
struct cvmx_pow_iq_cntx_s cn56xxp1;
struct cvmx_pow_iq_cntx_s cn58xx;
struct cvmx_pow_iq_cntx_s cn58xxp1;
+ struct cvmx_pow_iq_cntx_s cn63xx;
+ struct cvmx_pow_iq_cntx_s cn63xxp1;
};
union cvmx_pow_iq_com_cnt {
struct cvmx_pow_iq_com_cnt_s cn56xxp1;
struct cvmx_pow_iq_com_cnt_s cn58xx;
struct cvmx_pow_iq_com_cnt_s cn58xxp1;
+ struct cvmx_pow_iq_com_cnt_s cn63xx;
+ struct cvmx_pow_iq_com_cnt_s cn63xxp1;
};
union cvmx_pow_iq_int {
struct cvmx_pow_iq_int_s cn52xxp1;
struct cvmx_pow_iq_int_s cn56xx;
struct cvmx_pow_iq_int_s cn56xxp1;
+ struct cvmx_pow_iq_int_s cn63xx;
+ struct cvmx_pow_iq_int_s cn63xxp1;
};
union cvmx_pow_iq_int_en {
struct cvmx_pow_iq_int_en_s cn52xxp1;
struct cvmx_pow_iq_int_en_s cn56xx;
struct cvmx_pow_iq_int_en_s cn56xxp1;
+ struct cvmx_pow_iq_int_en_s cn63xx;
+ struct cvmx_pow_iq_int_en_s cn63xxp1;
};
union cvmx_pow_iq_thrx {
struct cvmx_pow_iq_thrx_s cn52xxp1;
struct cvmx_pow_iq_thrx_s cn56xx;
struct cvmx_pow_iq_thrx_s cn56xxp1;
+ struct cvmx_pow_iq_thrx_s cn63xx;
+ struct cvmx_pow_iq_thrx_s cn63xxp1;
};
union cvmx_pow_nos_cnt {
struct cvmx_pow_nos_cnt_s cn56xxp1;
struct cvmx_pow_nos_cnt_s cn58xx;
struct cvmx_pow_nos_cnt_s cn58xxp1;
+ struct cvmx_pow_nos_cnt_cn63xx {
+ uint64_t reserved_11_63:53;
+ uint64_t nos_cnt:11;
+ } cn63xx;
+ struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
};
union cvmx_pow_nw_tim {
struct cvmx_pow_nw_tim_s cn56xxp1;
struct cvmx_pow_nw_tim_s cn58xx;
struct cvmx_pow_nw_tim_s cn58xxp1;
+ struct cvmx_pow_nw_tim_s cn63xx;
+ struct cvmx_pow_nw_tim_s cn63xxp1;
};
union cvmx_pow_pf_rst_msk {
struct cvmx_pow_pf_rst_msk_s cn56xxp1;
struct cvmx_pow_pf_rst_msk_s cn58xx;
struct cvmx_pow_pf_rst_msk_s cn58xxp1;
+ struct cvmx_pow_pf_rst_msk_s cn63xx;
+ struct cvmx_pow_pf_rst_msk_s cn63xxp1;
};
union cvmx_pow_pp_grp_mskx {
struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
struct cvmx_pow_pp_grp_mskx_s cn58xx;
struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
+ struct cvmx_pow_pp_grp_mskx_s cn63xx;
+ struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
};
union cvmx_pow_qos_rndx {
struct cvmx_pow_qos_rndx_s cn56xxp1;
struct cvmx_pow_qos_rndx_s cn58xx;
struct cvmx_pow_qos_rndx_s cn58xxp1;
+ struct cvmx_pow_qos_rndx_s cn63xx;
+ struct cvmx_pow_qos_rndx_s cn63xxp1;
};
union cvmx_pow_qos_thrx {
struct cvmx_pow_qos_thrx_s cn56xxp1;
struct cvmx_pow_qos_thrx_s cn58xx;
struct cvmx_pow_qos_thrx_s cn58xxp1;
+ struct cvmx_pow_qos_thrx_cn63xx {
+ uint64_t reserved_59_63:5;
+ uint64_t des_cnt:11;
+ uint64_t reserved_47_47:1;
+ uint64_t buf_cnt:11;
+ uint64_t reserved_35_35:1;
+ uint64_t free_cnt:11;
+ uint64_t reserved_22_23:2;
+ uint64_t max_thr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t min_thr:10;
+ } cn63xx;
+ struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
};
union cvmx_pow_ts_pc {
struct cvmx_pow_ts_pc_s cn56xxp1;
struct cvmx_pow_ts_pc_s cn58xx;
struct cvmx_pow_ts_pc_s cn58xxp1;
+ struct cvmx_pow_ts_pc_s cn63xx;
+ struct cvmx_pow_ts_pc_s cn63xxp1;
};
union cvmx_pow_wa_com_pc {
struct cvmx_pow_wa_com_pc_s cn56xxp1;
struct cvmx_pow_wa_com_pc_s cn58xx;
struct cvmx_pow_wa_com_pc_s cn58xxp1;
+ struct cvmx_pow_wa_com_pc_s cn63xx;
+ struct cvmx_pow_wa_com_pc_s cn63xxp1;
};
union cvmx_pow_wa_pcx {
struct cvmx_pow_wa_pcx_s cn56xxp1;
struct cvmx_pow_wa_pcx_s cn58xx;
struct cvmx_pow_wa_pcx_s cn58xxp1;
+ struct cvmx_pow_wa_pcx_s cn63xx;
+ struct cvmx_pow_wa_pcx_s cn63xxp1;
};
union cvmx_pow_wq_int {
struct cvmx_pow_wq_int_s cn56xxp1;
struct cvmx_pow_wq_int_s cn58xx;
struct cvmx_pow_wq_int_s cn58xxp1;
+ struct cvmx_pow_wq_int_s cn63xx;
+ struct cvmx_pow_wq_int_s cn63xxp1;
};
union cvmx_pow_wq_int_cntx {
struct cvmx_pow_wq_int_cntx_s cn56xxp1;
struct cvmx_pow_wq_int_cntx_s cn58xx;
struct cvmx_pow_wq_int_cntx_s cn58xxp1;
+ struct cvmx_pow_wq_int_cntx_cn63xx {
+ uint64_t reserved_28_63:36;
+ uint64_t tc_cnt:4;
+ uint64_t reserved_23_23:1;
+ uint64_t ds_cnt:11;
+ uint64_t reserved_11_11:1;
+ uint64_t iq_cnt:11;
+ } cn63xx;
+ struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
};
union cvmx_pow_wq_int_pc {
struct cvmx_pow_wq_int_pc_s cn56xxp1;
struct cvmx_pow_wq_int_pc_s cn58xx;
struct cvmx_pow_wq_int_pc_s cn58xxp1;
+ struct cvmx_pow_wq_int_pc_s cn63xx;
+ struct cvmx_pow_wq_int_pc_s cn63xxp1;
};
union cvmx_pow_wq_int_thrx {
struct cvmx_pow_wq_int_thrx_s cn56xxp1;
struct cvmx_pow_wq_int_thrx_s cn58xx;
struct cvmx_pow_wq_int_thrx_s cn58xxp1;
+ struct cvmx_pow_wq_int_thrx_cn63xx {
+ uint64_t reserved_29_63:35;
+ uint64_t tc_en:1;
+ uint64_t tc_thr:4;
+ uint64_t reserved_22_23:2;
+ uint64_t ds_thr:10;
+ uint64_t reserved_10_11:2;
+ uint64_t iq_thr:10;
+ } cn63xx;
+ struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
};
union cvmx_pow_ws_pcx {
struct cvmx_pow_ws_pcx_s cn56xxp1;
struct cvmx_pow_ws_pcx_s cn58xx;
struct cvmx_pow_ws_pcx_s cn58xxp1;
+ struct cvmx_pow_ws_pcx_s cn63xx;
+ struct cvmx_pow_ws_pcx_s cn63xxp1;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#include <linux/types.h>
-#define CVMX_RNM_BIST_STATUS \
- CVMX_ADD_IO_SEG(0x0001180040000008ull)
-#define CVMX_RNM_CTL_STATUS \
- CVMX_ADD_IO_SEG(0x0001180040000000ull)
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
union cvmx_rnm_bist_status {
uint64_t u64;
struct cvmx_rnm_bist_status_s cn56xxp1;
struct cvmx_rnm_bist_status_s cn58xx;
struct cvmx_rnm_bist_status_s cn58xxp1;
+ struct cvmx_rnm_bist_status_s cn63xx;
+ struct cvmx_rnm_bist_status_s cn63xxp1;
};
union cvmx_rnm_ctl_status {
uint64_t u64;
struct cvmx_rnm_ctl_status_s {
- uint64_t reserved_9_63:55;
+ uint64_t reserved_11_63:53;
+ uint64_t eer_lck:1;
+ uint64_t eer_val:1;
uint64_t ent_sel:4;
uint64_t exp_ent:1;
uint64_t rng_rst:1;
struct cvmx_rnm_ctl_status_cn30xx cn31xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xx;
struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
- struct cvmx_rnm_ctl_status_s cn50xx;
- struct cvmx_rnm_ctl_status_s cn52xx;
- struct cvmx_rnm_ctl_status_s cn52xxp1;
- struct cvmx_rnm_ctl_status_s cn56xx;
- struct cvmx_rnm_ctl_status_s cn56xxp1;
- struct cvmx_rnm_ctl_status_s cn58xx;
- struct cvmx_rnm_ctl_status_s cn58xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx {
+ uint64_t reserved_9_63:55;
+ uint64_t ent_sel:4;
+ uint64_t exp_ent:1;
+ uint64_t rng_rst:1;
+ uint64_t rnm_rst:1;
+ uint64_t rng_en:1;
+ uint64_t ent_en:1;
+ } cn50xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn52xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx cn56xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
+ struct cvmx_rnm_ctl_status_cn50xx cn58xx;
+ struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
+ struct cvmx_rnm_ctl_status_s cn63xx;
+ struct cvmx_rnm_ctl_status_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_dbg {
+ uint64_t u64;
+ struct cvmx_rnm_eer_dbg_s {
+ uint64_t dat:64;
+ } s;
+ struct cvmx_rnm_eer_dbg_s cn63xx;
+ struct cvmx_rnm_eer_dbg_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_key {
+ uint64_t u64;
+ struct cvmx_rnm_eer_key_s {
+ uint64_t key:64;
+ } s;
+ struct cvmx_rnm_eer_key_s cn63xx;
+ struct cvmx_rnm_eer_key_s cn63xxp1;
+};
+
+union cvmx_rnm_serial_num {
+ uint64_t u64;
+ struct cvmx_rnm_serial_num_s {
+ uint64_t dat:64;
+ } s;
+ struct cvmx_rnm_serial_num_s cn63xx;
};
#endif
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
#ifndef __CVMX_SMIX_DEFS_H__
#define __CVMX_SMIX_DEFS_H__
-#define CVMX_SMIX_CLK(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
- CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
union cvmx_smix_clk {
uint64_t u64;
struct cvmx_smix_clk_cn30xx {
uint64_t reserved_21_63:43;
uint64_t sample_hi:5;
- uint64_t reserved_14_15:2;
+ uint64_t sample_mode:1;
+ uint64_t reserved_14_14:1;
uint64_t clk_idle:1;
uint64_t preamble:1;
uint64_t sample:4;
struct cvmx_smix_clk_cn30xx cn31xx;
struct cvmx_smix_clk_cn30xx cn38xx;
struct cvmx_smix_clk_cn30xx cn38xxp2;
- struct cvmx_smix_clk_cn50xx {
- uint64_t reserved_25_63:39;
- uint64_t mode:1;
- uint64_t reserved_21_23:3;
- uint64_t sample_hi:5;
- uint64_t reserved_14_15:2;
- uint64_t clk_idle:1;
- uint64_t preamble:1;
- uint64_t sample:4;
- uint64_t phase:8;
- } cn50xx;
+ struct cvmx_smix_clk_s cn50xx;
struct cvmx_smix_clk_s cn52xx;
- struct cvmx_smix_clk_cn50xx cn52xxp1;
+ struct cvmx_smix_clk_s cn52xxp1;
struct cvmx_smix_clk_s cn56xx;
- struct cvmx_smix_clk_cn50xx cn56xxp1;
+ struct cvmx_smix_clk_s cn56xxp1;
struct cvmx_smix_clk_cn30xx cn58xx;
struct cvmx_smix_clk_cn30xx cn58xxp1;
+ struct cvmx_smix_clk_s cn63xx;
+ struct cvmx_smix_clk_s cn63xxp1;
};
union cvmx_smix_cmd {
struct cvmx_smix_cmd_s cn56xxp1;
struct cvmx_smix_cmd_cn30xx cn58xx;
struct cvmx_smix_cmd_cn30xx cn58xxp1;
+ struct cvmx_smix_cmd_s cn63xx;
+ struct cvmx_smix_cmd_s cn63xxp1;
};
union cvmx_smix_en {
struct cvmx_smix_en_s cn56xxp1;
struct cvmx_smix_en_s cn58xx;
struct cvmx_smix_en_s cn58xxp1;
+ struct cvmx_smix_en_s cn63xx;
+ struct cvmx_smix_en_s cn63xxp1;
};
union cvmx_smix_rd_dat {
struct cvmx_smix_rd_dat_s cn56xxp1;
struct cvmx_smix_rd_dat_s cn58xx;
struct cvmx_smix_rd_dat_s cn58xxp1;
+ struct cvmx_smix_rd_dat_s cn63xx;
+ struct cvmx_smix_rd_dat_s cn63xxp1;
};
union cvmx_smix_wr_dat {
struct cvmx_smix_wr_dat_s cn56xxp1;
struct cvmx_smix_wr_dat_s cn58xx;
struct cvmx_smix_wr_dat_s cn58xxp1;
+ struct cvmx_smix_wr_dat_s cn63xx;
+ struct cvmx_smix_wr_dat_s cn63xxp1;
};
#endif
--- /dev/null
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2010 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
+
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+
+union cvmx_uctlx_bist_status {
+ uint64_t u64;
+ struct cvmx_uctlx_bist_status_s {
+ uint64_t reserved_6_63:58;
+ uint64_t data_bis:1;
+ uint64_t desc_bis:1;
+ uint64_t erbm_bis:1;
+ uint64_t orbm_bis:1;
+ uint64_t wrbm_bis:1;
+ uint64_t ppaf_bis:1;
+ } s;
+ struct cvmx_uctlx_bist_status_s cn63xx;
+ struct cvmx_uctlx_bist_status_s cn63xxp1;
+};
+
+union cvmx_uctlx_clk_rst_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_clk_rst_ctl_s {
+ uint64_t reserved_25_63:39;
+ uint64_t clear_bist:1;
+ uint64_t start_bist:1;
+ uint64_t ehci_sm:1;
+ uint64_t ohci_clkcktrst:1;
+ uint64_t ohci_sm:1;
+ uint64_t ohci_susp_lgcy:1;
+ uint64_t app_start_clk:1;
+ uint64_t o_clkdiv_rst:1;
+ uint64_t h_clkdiv_byp:1;
+ uint64_t h_clkdiv_rst:1;
+ uint64_t h_clkdiv_en:1;
+ uint64_t o_clkdiv_en:1;
+ uint64_t h_div:4;
+ uint64_t p_refclk_sel:2;
+ uint64_t p_refclk_div:2;
+ uint64_t reserved_4_4:1;
+ uint64_t p_com_on:1;
+ uint64_t p_por:1;
+ uint64_t p_prst:1;
+ uint64_t hrst:1;
+ } s;
+ struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
+ struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_ehci_ctl_s {
+ uint64_t reserved_20_63:44;
+ uint64_t desc_rbm:1;
+ uint64_t reg_nb:1;
+ uint64_t l2c_dc:1;
+ uint64_t l2c_bc:1;
+ uint64_t l2c_0pag:1;
+ uint64_t l2c_stt:1;
+ uint64_t l2c_buff_emod:2;
+ uint64_t l2c_desc_emod:2;
+ uint64_t inv_reg_a2:1;
+ uint64_t ehci_64b_addr_en:1;
+ uint64_t l2c_addr_msb:8;
+ } s;
+ struct cvmx_uctlx_ehci_ctl_s cn63xx;
+ struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_fla {
+ uint64_t u64;
+ struct cvmx_uctlx_ehci_fla_s {
+ uint64_t reserved_6_63:58;
+ uint64_t fla:6;
+ } s;
+ struct cvmx_uctlx_ehci_fla_s cn63xx;
+ struct cvmx_uctlx_ehci_fla_s cn63xxp1;
+};
+
+union cvmx_uctlx_erto_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_erto_ctl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t to_val:27;
+ uint64_t reserved_0_4:5;
+ } s;
+ struct cvmx_uctlx_erto_ctl_s cn63xx;
+ struct cvmx_uctlx_erto_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_if_ena {
+ uint64_t u64;
+ struct cvmx_uctlx_if_ena_s {
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+ } s;
+ struct cvmx_uctlx_if_ena_s cn63xx;
+ struct cvmx_uctlx_if_ena_s cn63xxp1;
+};
+
+union cvmx_uctlx_int_ena {
+ uint64_t u64;
+ struct cvmx_uctlx_int_ena_s {
+ uint64_t reserved_8_63:56;
+ uint64_t ec_ovf_e:1;
+ uint64_t oc_ovf_e:1;
+ uint64_t wb_pop_e:1;
+ uint64_t wb_psh_f:1;
+ uint64_t cf_psh_f:1;
+ uint64_t or_psh_f:1;
+ uint64_t er_psh_f:1;
+ uint64_t pp_psh_f:1;
+ } s;
+ struct cvmx_uctlx_int_ena_s cn63xx;
+ struct cvmx_uctlx_int_ena_s cn63xxp1;
+};
+
+union cvmx_uctlx_int_reg {
+ uint64_t u64;
+ struct cvmx_uctlx_int_reg_s {
+ uint64_t reserved_8_63:56;
+ uint64_t ec_ovf_e:1;
+ uint64_t oc_ovf_e:1;
+ uint64_t wb_pop_e:1;
+ uint64_t wb_psh_f:1;
+ uint64_t cf_psh_f:1;
+ uint64_t or_psh_f:1;
+ uint64_t er_psh_f:1;
+ uint64_t pp_psh_f:1;
+ } s;
+ struct cvmx_uctlx_int_reg_s cn63xx;
+ struct cvmx_uctlx_int_reg_s cn63xxp1;
+};
+
+union cvmx_uctlx_ohci_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_ohci_ctl_s {
+ uint64_t reserved_19_63:45;
+ uint64_t reg_nb:1;
+ uint64_t l2c_dc:1;
+ uint64_t l2c_bc:1;
+ uint64_t l2c_0pag:1;
+ uint64_t l2c_stt:1;
+ uint64_t l2c_buff_emod:2;
+ uint64_t l2c_desc_emod:2;
+ uint64_t inv_reg_a2:1;
+ uint64_t reserved_8_8:1;
+ uint64_t l2c_addr_msb:8;
+ } s;
+ struct cvmx_uctlx_ohci_ctl_s cn63xx;
+ struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_orto_ctl {
+ uint64_t u64;
+ struct cvmx_uctlx_orto_ctl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t to_val:24;
+ uint64_t reserved_0_7:8;
+ } s;
+ struct cvmx_uctlx_orto_ctl_s cn63xx;
+ struct cvmx_uctlx_orto_ctl_s cn63xxp1;
+};
+
+union cvmx_uctlx_ppaf_wm {
+ uint64_t u64;
+ struct cvmx_uctlx_ppaf_wm_s {
+ uint64_t reserved_5_63:59;
+ uint64_t wm:5;
+ } s;
+ struct cvmx_uctlx_ppaf_wm_s cn63xx;
+ struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_ctl_status {
+ uint64_t u64;
+ struct cvmx_uctlx_uphy_ctl_status_s {
+ uint64_t reserved_10_63:54;
+ uint64_t bist_done:1;
+ uint64_t bist_err:1;
+ uint64_t hsbist:1;
+ uint64_t fsbist:1;
+ uint64_t lsbist:1;
+ uint64_t siddq:1;
+ uint64_t vtest_en:1;
+ uint64_t uphy_bist:1;
+ uint64_t bist_en:1;
+ uint64_t ate_reset:1;
+ } s;
+ struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
+ struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_portx_ctl_status {
+ uint64_t u64;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s {
+ uint64_t reserved_43_63:21;
+ uint64_t tdata_out:4;
+ uint64_t txbiststuffenh:1;
+ uint64_t txbiststuffen:1;
+ uint64_t dmpulldown:1;
+ uint64_t dppulldown:1;
+ uint64_t vbusvldext:1;
+ uint64_t portreset:1;
+ uint64_t txhsvxtune:2;
+ uint64_t txvreftune:4;
+ uint64_t txrisetune:1;
+ uint64_t txpreemphasistune:1;
+ uint64_t txfslstune:4;
+ uint64_t sqrxtune:3;
+ uint64_t compdistune:3;
+ uint64_t loop_en:1;
+ uint64_t tclk:1;
+ uint64_t tdata_sel:1;
+ uint64_t taddr_in:4;
+ uint64_t tdata_in:8;
+ } s;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
+ struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+};
+
+#endif
#ifndef __OCTEON_MODEL_H__
#define __OCTEON_MODEL_H__
-/* NOTE: These must match what is checked in common-config.mk */
-/* Defines to represent the different versions of Octeon. */
-
-/*
- * IMPORTANT: When the default pass is updated for an Octeon Model,
- * the corresponding change must also be made in the oct-sim script.
- */
-
/*
* The defines below should be used with the OCTEON_IS_MODEL() macro
* to determine what model of chip the software is running on. Models
#define OM_IGNORE_MINOR_REVISION 0x08000000
#define OM_FLAG_MASK 0xff000000
+#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN63XX_PASS1_0 0x000d9000
+#define OCTEON_CN63XX_PASS1_1 0x000d9001
+#define OCTEON_CN63XX_PASS1_2 0x000d9002
+#define OCTEON_CN63XX_PASS2_0 0x000d9008
+
+#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
/*
* CN5XXX models with new revision encoding
*/
| OM_MATCH_PREVIOUS_MODELS \
| OM_IGNORE_REVISION)
+#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+
/* The revision byte (low byte) has two different encodings.
* CN3XXX:
*
| OCTEON_58XX_MODEL_MASK)
#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
& 0x00fffff8)
+#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
__OCTEON_MATCH_MASK__((chip_model), (arg_model),
OCTEON_58XX_MODEL_REV_MASK))
return 1;
+
+ if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
+ ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
+ return 1;
+
+ if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
+ ((chip_model) >= OCTEON_CN63XX_PASS1_0))
+ return 1;
+
if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
((chip_model & OCTEON_58XX_MODEL_MASK) <
(arg_model & OCTEON_58XX_MODEL_MASK)))
extern int octeon_is_pci_host(void);
extern int octeon_usb_is_ref_clk(void);
extern uint64_t octeon_get_clock_rate(void);
+extern u64 octeon_get_io_clock_rate(void);
extern const char *octeon_board_type_string(void);
extern const char *octeon_get_pci_interrupts(void);
extern int octeon_get_southbridge_interrupt(void);
extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
u8 slot, u8 pin);
+/*
+ * For PCI (not PCIe) the BAR2 base address.
+ */
+#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
+
+/*
+ * For PCI (not PCIe) the base of the memory mapped by BAR1
+ */
+extern u64 octeon_bar1_pci_phys;
+
/*
* The following defines are used when octeon_dma_bar_type =
* OCTEON_DMA_BAR_TYPE_BIG
--- /dev/null
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+
+/*
+ * MIPS performance counters do not raise NMI upon overflow, a regular
+ * interrupt will be signaled. Hence we can do the pending perf event
+ * work at the tail of the irq handler.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+#endif /* __MIPS_PERF_EVENT_H__ */
#endif
#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-#if PGDIR_SIZE >= TASK_SIZE
+#if PGDIR_SIZE >= TASK_SIZE64
#define USER_PTRS_PER_PGD (1)
#else
-#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
+#define USER_PTRS_PER_PGD (TASK_SIZE64 / PGDIR_SIZE)
#endif
#define FIRST_USER_ADDRESS 0UL
* so don't change it unless you know what you are doing.
*/
#define TASK_SIZE 0x7fff8000UL
-#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+#ifdef __KERNEL__
+#define STACK_TOP_MAX TASK_SIZE
+#endif
#define TASK_IS_32BIT_ADDR 1
* 8192EB ...
*/
#define TASK_SIZE32 0x7fff8000UL
-#define TASK_SIZE 0x10000000000UL
-#define STACK_TOP \
- (((test_thread_flag(TIF_32BIT_ADDR) ? \
- TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+#define TASK_SIZE64 0x10000000000UL
+#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX TASK_SIZE64
+#endif
+
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE \
- (test_thread_flag(TIF_32BIT_ADDR) ? \
- PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
#define TASK_SIZE_OF(tsk) \
- (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+ (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
#endif
-#ifdef __KERNEL__
-#define STACK_TOP_MAX TASK_SIZE
-#endif
+#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
#define NUM_FPU_REGS 32
} else if (kernel_uses_llsc) {
unsigned long dummy;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: ll %0, %3 # xchg_u32 \n"
- " .set mips0 \n"
- " move %2, %z4 \n"
- " .set mips3 \n"
- " sc %2, %1 \n"
- " beqz %2, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " ll %0, %3 # xchg_u32 \n"
+ " .set mips0 \n"
+ " move %2, %z4 \n"
+ " .set mips3 \n"
+ " sc %2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+ : "R" (*m), "Jr" (val)
+ : "memory");
+ } while (unlikely(!dummy));
} else {
unsigned long flags;
} else if (kernel_uses_llsc) {
unsigned long dummy;
- __asm__ __volatile__(
- " .set mips3 \n"
- "1: lld %0, %3 # xchg_u64 \n"
- " move %2, %z4 \n"
- " scd %2, %1 \n"
- " beqz %2, 2f \n"
- " .subsection 2 \n"
- "2: b 1b \n"
- " .previous \n"
- " .set mips0 \n"
- : "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
- : "memory");
+ do {
+ __asm__ __volatile__(
+ " .set mips3 \n"
+ " lld %0, %3 # xchg_u64 \n"
+ " move %2, %z4 \n"
+ " scd %2, %1 \n"
+ " .set mips0 \n"
+ : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+ : "R" (*m), "Jr" (val)
+ : "memory");
+ } while (unlikely(!dummy));
} else {
unsigned long flags;
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
#define THREAD_MASK (THREAD_SIZE - 1UL)
+#define STACK_WARN (THREAD_SIZE / 8)
+
#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
#ifdef CONFIG_DEBUG_STACK_USAGE
#ifdef CONFIG_64BIT
-#define __UA_LIMIT (- TASK_SIZE)
+extern u64 __ua_limit;
+
+#define __UA_LIMIT __ua_limit
#define __UA_ADDR ".dword"
#define __UA_LA "dla"
obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
+obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
+
CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
#include <asm/system.h>
#include <asm/watch.h>
#include <asm/spram.h>
+#include <asm/uaccess.h>
+
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
* the implementation of the "wait" feature differs between CPU families. This
case CPU_5KC:
case CPU_25KF:
case CPU_PR4450:
- case CPU_BCM3302:
- case CPU_BCM6338:
- case CPU_BCM6348:
- case CPU_BCM6358:
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4350:
+ case CPU_BMIPS4380:
+ case CPU_BMIPS5000:
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
+ case CPU_CAVIUM_OCTEON2:
case CPU_JZRISC:
cpu_wait = r4k_wait;
break;
{
decode_configs(c);
switch (c->processor_id & 0xff00) {
- case PRID_IMP_BCM3302:
- /* same as PRID_IMP_BCM6338 */
- c->cputype = CPU_BCM3302;
- __cpu_name[cpu] = "Broadcom BCM3302";
- break;
- case PRID_IMP_BCM4710:
- c->cputype = CPU_BCM4710;
- __cpu_name[cpu] = "Broadcom BCM4710";
- break;
- case PRID_IMP_BCM6345:
- c->cputype = CPU_BCM6345;
- __cpu_name[cpu] = "Broadcom BCM6345";
+ case PRID_IMP_BMIPS32:
+ c->cputype = CPU_BMIPS32;
+ __cpu_name[cpu] = "Broadcom BMIPS32";
+ break;
+ case PRID_IMP_BMIPS3300:
+ case PRID_IMP_BMIPS3300_ALT:
+ case PRID_IMP_BMIPS3300_BUG:
+ c->cputype = CPU_BMIPS3300;
+ __cpu_name[cpu] = "Broadcom BMIPS3300";
+ break;
+ case PRID_IMP_BMIPS43XX: {
+ int rev = c->processor_id & 0xff;
+
+ if (rev >= PRID_REV_BMIPS4380_LO &&
+ rev <= PRID_REV_BMIPS4380_HI) {
+ c->cputype = CPU_BMIPS4380;
+ __cpu_name[cpu] = "Broadcom BMIPS4380";
+ } else {
+ c->cputype = CPU_BMIPS4350;
+ __cpu_name[cpu] = "Broadcom BMIPS4350";
+ }
break;
- case PRID_IMP_BCM6348:
- c->cputype = CPU_BCM6348;
- __cpu_name[cpu] = "Broadcom BCM6348";
+ }
+ case PRID_IMP_BMIPS5000:
+ c->cputype = CPU_BMIPS5000;
+ __cpu_name[cpu] = "Broadcom BMIPS5000";
+ c->options |= MIPS_CPU_ULRI;
break;
- case PRID_IMP_BCM4350:
- switch (c->processor_id & 0xf0) {
- case PRID_REV_BCM6358:
- c->cputype = CPU_BCM6358;
- __cpu_name[cpu] = "Broadcom BCM6358";
- break;
- default:
- c->cputype = CPU_UNKNOWN;
- break;
- }
+ case PRID_IMP_BMIPS4KC:
+ c->cputype = CPU_4KC;
+ __cpu_name[cpu] = "MIPS 4Kc";
break;
}
}
if (cpu == 0)
__elf_platform = "octeon";
break;
+ case PRID_IMP_CAVIUM_CN63XX:
+ c->cputype = CPU_CAVIUM_OCTEON2;
+ __cpu_name[cpu] = "Cavium Octeon II";
+ if (cpu == 0)
+ __elf_platform = "octeon2";
+ break;
default:
printk(KERN_INFO "Unknown Octeon chip!\n");
c->cputype = CPU_UNKNOWN;
}
}
+#ifdef CONFIG_64BIT
+/* For use by uaccess.h */
+u64 __ua_limit;
+EXPORT_SYMBOL(__ua_limit);
+#endif
+
const char *__cpu_name[NR_CPUS];
const char *__elf_platform;
c->srsets = 1;
cpu_probe_vmbits(c);
+
+#ifdef CONFIG_64BIT
+ if (cpu == 0)
+ __ua_limit = ~((1ull << cpu_vmbits) - 1);
+#endif
}
__cpuinit void cpu_report(void)
#endif
}
+#ifdef DEBUG_STACKOVERFLOW
+static inline void check_stack_overflow(void)
+{
+ unsigned long sp;
+
+ __asm__ __volatile__("move %0, $sp" : "=r" (sp));
+ sp &= THREAD_MASK;
+
+ /*
+ * Check for stack overflow: is there less than STACK_WARN free?
+ * STACK_WARN is defined as 1/8 of THREAD_SIZE by default.
+ */
+ if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
+ printk("do_IRQ: stack overflow: %ld\n",
+ sp - sizeof(struct thread_info));
+ dump_stack();
+ }
+}
+#else
+static inline void check_stack_overflow(void) {}
+#endif
+
+
/*
* do_IRQ handles all normal device IRQ's (the special
* SMP cross-CPU interrupts have their own specific
void __irq_entry do_IRQ(unsigned int irq)
{
irq_enter();
+ check_stack_overflow();
__DO_IRQ_SMTC_HOOK(irq);
generic_handle_irq(irq);
irq_exit();
--- /dev/null
+/*
+ * Linux performance counter support for MIPS.
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This code is based on the implementation for ARM, which is in turn
+ * based on the sparc64 perf event code and the x86 code. Performance
+ * counter access is based on the MIPS Oprofile code. And the callchain
+ * support references the code of MIPS stacktrace.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/uaccess.h>
+
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/stacktrace.h>
+#include <asm/time.h> /* For perf_irq */
+
+/* These are for 32bit counters. For 64bit ones, define them accordingly. */
+#define MAX_PERIOD ((1ULL << 32) - 1)
+#define VALID_COUNT 0x7fffffff
+#define TOTAL_BITS 32
+#define HIGHEST_BIT 31
+
+#define MIPS_MAX_HWEVENTS 4
+
+struct cpu_hw_events {
+ /* Array of events on this cpu. */
+ struct perf_event *events[MIPS_MAX_HWEVENTS];
+
+ /*
+ * Set the bit (indexed by the counter number) when the counter
+ * is used for an event.
+ */
+ unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+ /*
+ * The borrowed MSB for the performance counter. A MIPS performance
+ * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
+ * counters) as a factor of determining whether a counter overflow
+ * should be signaled. So here we use a separate MSB for each
+ * counter to make things easy.
+ */
+ unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+ /*
+ * Software copy of the control register for each performance counter.
+ * MIPS CPUs vary in performance counters. They use this differently,
+ * and even may not use it.
+ */
+ unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+ .saved_ctrl = {0},
+};
+
+/* The description of MIPS performance events. */
+struct mips_perf_event {
+ unsigned int event_id;
+ /*
+ * MIPS performance counters are indexed starting from 0.
+ * CNTR_EVEN indicates the indexes of the counters to be used are
+ * even numbers.
+ */
+ unsigned int cntr_mask;
+ #define CNTR_EVEN 0x55555555
+ #define CNTR_ODD 0xaaaaaaaa
+#ifdef CONFIG_MIPS_MT_SMP
+ enum {
+ T = 0,
+ V = 1,
+ P = 2,
+ } range;
+#else
+ #define T
+ #define V
+ #define P
+#endif
+};
+
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
+#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+struct mips_pmu {
+ const char *name;
+ int irq;
+ irqreturn_t (*handle_irq)(int irq, void *dev);
+ int (*handle_shared_irq)(void);
+ void (*start)(void);
+ void (*stop)(void);
+ int (*alloc_counter)(struct cpu_hw_events *cpuc,
+ struct hw_perf_event *hwc);
+ u64 (*read_counter)(unsigned int idx);
+ void (*write_counter)(unsigned int idx, u64 val);
+ void (*enable_event)(struct hw_perf_event *evt, int idx);
+ void (*disable_event)(int idx);
+ const struct mips_perf_event *(*map_raw_event)(u64 config);
+ const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
+ const struct mips_perf_event (*cache_event_map)
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX];
+ unsigned int num_counters;
+};
+
+static const struct mips_pmu *mipspmu;
+
+static int
+mipspmu_event_set_period(struct perf_event *event,
+ struct hw_perf_event *hwc,
+ int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ s64 left = local64_read(&hwc->period_left);
+ s64 period = hwc->sample_period;
+ int ret = 0;
+ u64 uleft;
+ unsigned long flags;
+
+ if (unlikely(left <= -period)) {
+ left = period;
+ local64_set(&hwc->period_left, left);
+ hwc->last_period = period;
+ ret = 1;
+ }
+
+ if (unlikely(left <= 0)) {
+ left += period;
+ local64_set(&hwc->period_left, left);
+ hwc->last_period = period;
+ ret = 1;
+ }
+
+ if (left > (s64)MAX_PERIOD)
+ left = MAX_PERIOD;
+
+ local64_set(&hwc->prev_count, (u64)-left);
+
+ local_irq_save(flags);
+ uleft = (u64)(-left) & MAX_PERIOD;
+ uleft > VALID_COUNT ?
+ set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
+ mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
+ local_irq_restore(flags);
+
+ perf_event_update_userpage(event);
+
+ return ret;
+}
+
+static int mipspmu_enable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx;
+ int err = 0;
+
+ /* To look for a free counter for this event. */
+ idx = mipspmu->alloc_counter(cpuc, hwc);
+ if (idx < 0) {
+ err = idx;
+ goto out;
+ }
+
+ /*
+ * If there is an event in the counter we are going to use then
+ * make sure it is disabled.
+ */
+ event->hw.idx = idx;
+ mipspmu->disable_event(idx);
+ cpuc->events[idx] = event;
+
+ /* Set the period for the event. */
+ mipspmu_event_set_period(event, hwc, idx);
+
+ /* Enable the event. */
+ mipspmu->enable_event(hwc, idx);
+
+ /* Propagate our changes to the userspace mapping. */
+ perf_event_update_userpage(event);
+
+out:
+ return err;
+}
+
+static void mipspmu_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc,
+ int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+ int shift = 64 - TOTAL_BITS;
+ s64 prev_raw_count, new_raw_count;
+ s64 delta;
+
+again:
+ prev_raw_count = local64_read(&hwc->prev_count);
+ local_irq_save(flags);
+ /* Make the counter value be a "real" one. */
+ new_raw_count = mipspmu->read_counter(idx);
+ if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
+ new_raw_count &= VALID_COUNT;
+ clear_bit(idx, cpuc->msbs);
+ } else
+ new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
+ local_irq_restore(flags);
+
+ if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count)
+ goto again;
+
+ delta = (new_raw_count << shift) - (prev_raw_count << shift);
+ delta >>= shift;
+
+ local64_add(delta, &event->count);
+ local64_sub(delta, &hwc->period_left);
+
+ return;
+}
+
+static void mipspmu_disable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ /* We are working on a local event. */
+ mipspmu->disable_event(idx);
+
+ barrier();
+
+ mipspmu_event_update(event, hwc, idx);
+ cpuc->events[idx] = NULL;
+ clear_bit(idx, cpuc->used_mask);
+
+ perf_event_update_userpage(event);
+}
+
+static void mipspmu_unthrottle(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ mipspmu->enable_event(hwc, hwc->idx);
+}
+
+static void mipspmu_read(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ /* Don't read disabled counters! */
+ if (hwc->idx < 0)
+ return;
+
+ mipspmu_event_update(event, hwc, hwc->idx);
+}
+
+static struct pmu pmu = {
+ .enable = mipspmu_enable,
+ .disable = mipspmu_disable,
+ .unthrottle = mipspmu_unthrottle,
+ .read = mipspmu_read,
+};
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+static int (*save_perf_irq)(void);
+
+static int mipspmu_get_irq(void)
+{
+ int err;
+
+ if (mipspmu->irq >= 0) {
+ /* Request my own irq handler. */
+ err = request_irq(mipspmu->irq, mipspmu->handle_irq,
+ IRQF_DISABLED | IRQF_NOBALANCING,
+ "mips_perf_pmu", NULL);
+ if (err) {
+ pr_warning("Unable to request IRQ%d for MIPS "
+ "performance counters!\n", mipspmu->irq);
+ }
+ } else if (cp0_perfcount_irq < 0) {
+ /*
+ * We are sharing the irq number with the timer interrupt.
+ */
+ save_perf_irq = perf_irq;
+ perf_irq = mipspmu->handle_shared_irq;
+ err = 0;
+ } else {
+ pr_warning("The platform hasn't properly defined its "
+ "interrupt controller.\n");
+ err = -ENOENT;
+ }
+
+ return err;
+}
+
+static void mipspmu_free_irq(void)
+{
+ if (mipspmu->irq >= 0)
+ free_irq(mipspmu->irq, NULL);
+ else if (cp0_perfcount_irq < 0)
+ perf_irq = save_perf_irq;
+}
+
+static inline unsigned int
+mipspmu_perf_event_encode(const struct mips_perf_event *pev)
+{
+/*
+ * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
+ * event_id.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+ return ((unsigned int)pev->range << 24) |
+ (pev->cntr_mask & 0xffff00) |
+ (pev->event_id & 0xff);
+#else
+ return (pev->cntr_mask & 0xffff00) |
+ (pev->event_id & 0xff);
+#endif
+}
+
+static const struct mips_perf_event *
+mipspmu_map_general_event(int idx)
+{
+ const struct mips_perf_event *pev;
+
+ pev = ((*mipspmu->general_event_map)[idx].event_id ==
+ UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
+ &(*mipspmu->general_event_map)[idx]);
+
+ return pev;
+}
+
+static const struct mips_perf_event *
+mipspmu_map_cache_event(u64 config)
+{
+ unsigned int cache_type, cache_op, cache_result;
+ const struct mips_perf_event *pev;
+
+ cache_type = (config >> 0) & 0xff;
+ if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+ return ERR_PTR(-EINVAL);
+
+ cache_op = (config >> 8) & 0xff;
+ if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+ return ERR_PTR(-EINVAL);
+
+ cache_result = (config >> 16) & 0xff;
+ if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+ return ERR_PTR(-EINVAL);
+
+ pev = &((*mipspmu->cache_event_map)
+ [cache_type]
+ [cache_op]
+ [cache_result]);
+
+ if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+ return ERR_PTR(-EOPNOTSUPP);
+
+ return pev;
+
+}
+
+static int validate_event(struct cpu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ struct hw_perf_event fake_hwc = event->hw;
+
+ if (event->pmu && event->pmu != &pmu)
+ return 0;
+
+ return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
+}
+
+static int validate_group(struct perf_event *event)
+{
+ struct perf_event *sibling, *leader = event->group_leader;
+ struct cpu_hw_events fake_cpuc;
+
+ memset(&fake_cpuc, 0, sizeof(fake_cpuc));
+
+ if (!validate_event(&fake_cpuc, leader))
+ return -ENOSPC;
+
+ list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ if (!validate_event(&fake_cpuc, sibling))
+ return -ENOSPC;
+ }
+
+ if (!validate_event(&fake_cpuc, event))
+ return -ENOSPC;
+
+ return 0;
+}
+
+/*
+ * mipsxx/rm9000/loongson2 have different performance counters, they have
+ * specific low-level init routines.
+ */
+static void reset_counters(void *arg);
+static int __hw_perf_event_init(struct perf_event *event);
+
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+ if (atomic_dec_and_mutex_lock(&active_events,
+ &pmu_reserve_mutex)) {
+ /*
+ * We must not call the destroy function with interrupts
+ * disabled.
+ */
+ on_each_cpu(reset_counters,
+ (void *)(long)mipspmu->num_counters, 1);
+ mipspmu_free_irq();
+ mutex_unlock(&pmu_reserve_mutex);
+ }
+}
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+ int err = 0;
+
+ if (!mipspmu || event->cpu >= nr_cpumask_bits ||
+ (event->cpu >= 0 && !cpu_online(event->cpu)))
+ return ERR_PTR(-ENODEV);
+
+ if (!atomic_inc_not_zero(&active_events)) {
+ if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
+ atomic_dec(&active_events);
+ return ERR_PTR(-ENOSPC);
+ }
+
+ mutex_lock(&pmu_reserve_mutex);
+ if (atomic_read(&active_events) == 0)
+ err = mipspmu_get_irq();
+
+ if (!err)
+ atomic_inc(&active_events);
+ mutex_unlock(&pmu_reserve_mutex);
+ }
+
+ if (err)
+ return ERR_PTR(err);
+
+ err = __hw_perf_event_init(event);
+ if (err)
+ hw_perf_event_destroy(event);
+
+ return err ? ERR_PTR(err) : &pmu;
+}
+
+void hw_perf_enable(void)
+{
+ if (mipspmu)
+ mipspmu->start();
+}
+
+void hw_perf_disable(void)
+{
+ if (mipspmu)
+ mipspmu->stop();
+}
+
+/* This is needed by specific irq handlers in perf_event_*.c */
+static void
+handle_associated_event(struct cpu_hw_events *cpuc,
+ int idx, struct perf_sample_data *data, struct pt_regs *regs)
+{
+ struct perf_event *event = cpuc->events[idx];
+ struct hw_perf_event *hwc = &event->hw;
+
+ mipspmu_event_update(event, hwc, idx);
+ data->period = event->hw.last_period;
+ if (!mipspmu_event_set_period(event, hwc, idx))
+ return;
+
+ if (perf_event_overflow(event, 0, data, regs))
+ mipspmu->disable_event(idx);
+}
+
+#include "perf_event_mipsxx.c"
+
+/* Callchain handling code. */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+ u64 ip)
+{
+ if (entry->nr < PERF_MAX_STACK_DEPTH)
+ entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * Leave userspace callchain empty for now. When we find a way to trace
+ * the user stack callchains, we add here.
+ */
+static void
+perf_callchain_user(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+}
+
+static void save_raw_perf_callchain(struct perf_callchain_entry *entry,
+ unsigned long reg29)
+{
+ unsigned long *sp = (unsigned long *)reg29;
+ unsigned long addr;
+
+ while (!kstack_end(sp)) {
+ addr = *sp++;
+ if (__kernel_text_address(addr)) {
+ callchain_store(entry, addr);
+ if (entry->nr >= PERF_MAX_STACK_DEPTH)
+ break;
+ }
+ }
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+ unsigned long sp = regs->regs[29];
+#ifdef CONFIG_KALLSYMS
+ unsigned long ra = regs->regs[31];
+ unsigned long pc = regs->cp0_epc;
+
+ callchain_store(entry, PERF_CONTEXT_KERNEL);
+ if (raw_show_trace || !__kernel_text_address(pc)) {
+ unsigned long stack_page =
+ (unsigned long)task_stack_page(current);
+ if (stack_page && sp >= stack_page &&
+ sp <= stack_page + THREAD_SIZE - 32)
+ save_raw_perf_callchain(entry, sp);
+ return;
+ }
+ do {
+ callchain_store(entry, pc);
+ if (entry->nr >= PERF_MAX_STACK_DEPTH)
+ break;
+ pc = unwind_stack(current, &sp, pc, &ra);
+ } while (pc);
+#else
+ callchain_store(entry, PERF_CONTEXT_KERNEL);
+ save_raw_perf_callchain(entry, sp);
+#endif
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+ struct perf_callchain_entry *entry)
+{
+ int is_user;
+
+ if (!regs)
+ return;
+
+ is_user = user_mode(regs);
+
+ if (!current || !current->pid)
+ return;
+
+ if (is_user && current->state != TASK_RUNNING)
+ return;
+
+ if (!is_user) {
+ perf_callchain_kernel(regs, entry);
+ if (current->mm)
+ regs = task_pt_regs(current);
+ else
+ regs = NULL;
+ }
+ if (regs)
+ perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+ struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+ entry->nr = 0;
+ perf_do_callchain(regs, entry);
+ return entry;
+}
--- /dev/null
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+ defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_CONFIG1_PC (1 << 4)
+
+#define M_PERFCTL_EXL (1UL << 0)
+#define M_PERFCTL_KERNEL (1UL << 1)
+#define M_PERFCTL_SUPERVISOR (1UL << 2)
+#define M_PERFCTL_USER (1UL << 3)
+#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
+#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
+#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
+#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
+#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
+#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
+#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
+#define M_PERFCTL_WIDE (1UL << 30)
+#define M_PERFCTL_MORE (1UL << 31)
+
+#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
+ M_PERFCTL_KERNEL | \
+ M_PERFCTL_USER | \
+ M_PERFCTL_SUPERVISOR | \
+ M_PERFCTL_INTERRUPT_ENABLE)
+
+#ifdef CONFIG_MIPS_MT_SMP
+#define M_PERFCTL_CONFIG_MASK 0x3fff801f
+#else
+#define M_PERFCTL_CONFIG_MASK 0x1f
+#endif
+#define M_PERFCTL_EVENT_MASK 0xfe0
+
+#define M_COUNTER_OVERFLOW (1UL << 31)
+
+#ifdef CONFIG_MIPS_MT_SMP
+static int cpu_has_mipsmt_pertccounters;
+
+/*
+ * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
+ * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
+ */
+#if defined(CONFIG_HW_PERF_EVENTS)
+#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
+ 0 : smp_processor_id())
+#else
+#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
+ 0 : cpu_data[smp_processor_id()].vpe_id)
+#endif
+
+/* Copied from op_model_mipsxx.c */
+static inline unsigned int vpe_shift(void)
+{
+ if (num_possible_cpus() > 1)
+ return 1;
+
+ return 0;
+}
+#else /* !CONFIG_MIPS_MT_SMP */
+#define vpe_id() 0
+
+static inline unsigned int vpe_shift(void)
+{
+ return 0;
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+ return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+ return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np) \
+ \
+static inline unsigned int r_c0_ ## r ## n(void) \
+{ \
+ unsigned int cpu = vpe_id(); \
+ \
+ switch (cpu) { \
+ case 0: \
+ return read_c0_ ## r ## n(); \
+ case 1: \
+ return read_c0_ ## r ## np(); \
+ default: \
+ BUG(); \
+ } \
+ return 0; \
+} \
+ \
+static inline void w_c0_ ## r ## n(unsigned int value) \
+{ \
+ unsigned int cpu = vpe_id(); \
+ \
+ switch (cpu) { \
+ case 0: \
+ write_c0_ ## r ## n(value); \
+ return; \
+ case 1: \
+ write_c0_ ## r ## np(value); \
+ return; \
+ default: \
+ BUG(); \
+ } \
+ return; \
+} \
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+ if (!(read_c0_config1() & M_CONFIG1_PC))
+ return 0;
+ if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+ return 1;
+ if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+ return 2;
+ if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+ return 3;
+
+ return 4;
+}
+
+static inline int n_counters(void)
+{
+ int counters;
+
+ switch (current_cpu_type()) {
+ case CPU_R10000:
+ counters = 2;
+ break;
+
+ case CPU_R12000:
+ case CPU_R14000:
+ counters = 4;
+ break;
+
+ default:
+ counters = __n_counters();
+ }
+
+ return counters;
+}
+
+static void reset_counters(void *arg)
+{
+ int counters = (int)(long)arg;
+ switch (counters) {
+ case 4:
+ w_c0_perfctrl3(0);
+ w_c0_perfcntr3(0);
+ case 3:
+ w_c0_perfctrl2(0);
+ w_c0_perfcntr2(0);
+ case 2:
+ w_c0_perfctrl1(0);
+ w_c0_perfcntr1(0);
+ case 1:
+ w_c0_perfctrl0(0);
+ w_c0_perfcntr0(0);
+ }
+}
+
+static inline u64
+mipsxx_pmu_read_counter(unsigned int idx)
+{
+ switch (idx) {
+ case 0:
+ return r_c0_perfcntr0();
+ case 1:
+ return r_c0_perfcntr1();
+ case 2:
+ return r_c0_perfcntr2();
+ case 3:
+ return r_c0_perfcntr3();
+ default:
+ WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+ return 0;
+ }
+}
+
+static inline void
+mipsxx_pmu_write_counter(unsigned int idx, u64 val)
+{
+ switch (idx) {
+ case 0:
+ w_c0_perfcntr0(val);
+ return;
+ case 1:
+ w_c0_perfcntr1(val);
+ return;
+ case 2:
+ w_c0_perfcntr2(val);
+ return;
+ case 3:
+ w_c0_perfcntr3(val);
+ return;
+ }
+}
+
+static inline unsigned int
+mipsxx_pmu_read_control(unsigned int idx)
+{
+ switch (idx) {
+ case 0:
+ return r_c0_perfctrl0();
+ case 1:
+ return r_c0_perfctrl1();
+ case 2:
+ return r_c0_perfctrl2();
+ case 3:
+ return r_c0_perfctrl3();
+ default:
+ WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+ return 0;
+ }
+}
+
+static inline void
+mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
+{
+ switch (idx) {
+ case 0:
+ w_c0_perfctrl0(val);
+ return;
+ case 1:
+ w_c0_perfctrl1(val);
+ return;
+ case 2:
+ w_c0_perfctrl2(val);
+ return;
+ case 3:
+ w_c0_perfctrl3(val);
+ return;
+ }
+}
+
+#ifdef CONFIG_MIPS_MT_SMP
+static DEFINE_RWLOCK(pmuint_rwlock);
+#endif
+
+/* 24K/34K/1004K cores can share the same event map. */
+static const struct mips_perf_event mipsxxcore_event_map
+ [PERF_COUNT_HW_MAX] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+ [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+ [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
+ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+ [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 74K core has different branch event code. */
+static const struct mips_perf_event mipsxx74Kcore_event_map
+ [PERF_COUNT_HW_MAX] = {
+ [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+ [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+ [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
+ [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
+ [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 24K/34K/1004K cores can share the same cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+ /*
+ * Like some other architectures (e.g. ARM), the performance
+ * counters don't differentiate between read and write
+ * accesses/misses, so this isn't strictly correct, but it's the
+ * best we can do. Writes and reads get combined.
+ */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
+ /*
+ * Note that MIPS has only "hit" events countable for
+ * the prefetch operation.
+ */
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(DTLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(BPU)] = {
+ /* Using the same code for *HW_BRANCH* */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+};
+
+/* 74K core has completely different cache event map. */
+static const struct mips_perf_event mipsxx74Kcore_cache_map
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+ /*
+ * Like some other architectures (e.g. ARM), the performance
+ * counters don't differentiate between read and write
+ * accesses/misses, so this isn't strictly correct, but it's the
+ * best we can do. Writes and reads get combined.
+ */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
+ [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
+ [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
+ /*
+ * Note that MIPS has only "hit" events countable for
+ * the prefetch operation.
+ */
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
+ [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(DTLB)] = {
+ /* 74K core does not have specific DTLB events. */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+[C(BPU)] = {
+ /* Using the same code for *HW_BRANCH* */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
+ [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
+ },
+},
+};
+
+#ifdef CONFIG_MIPS_MT_SMP
+static void
+check_and_calc_range(struct perf_event *event,
+ const struct mips_perf_event *pev)
+{
+ struct hw_perf_event *hwc = &event->hw;
+
+ if (event->cpu >= 0) {
+ if (pev->range > V) {
+ /*
+ * The user selected an event that is processor
+ * wide, while expecting it to be VPE wide.
+ */
+ hwc->config_base |= M_TC_EN_ALL;
+ } else {
+ /*
+ * FIXME: cpu_data[event->cpu].vpe_id reports 0
+ * for both CPUs.
+ */
+ hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
+ hwc->config_base |= M_TC_EN_VPE;
+ }
+ } else
+ hwc->config_base |= M_TC_EN_ALL;
+}
+#else
+static void
+check_and_calc_range(struct perf_event *event,
+ const struct mips_perf_event *pev)
+{
+}
+#endif
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ struct hw_perf_event *hwc = &event->hw;
+ const struct mips_perf_event *pev;
+ int err;
+
+ /* Returning MIPS event descriptor for generic perf event. */
+ if (PERF_TYPE_HARDWARE == event->attr.type) {
+ if (event->attr.config >= PERF_COUNT_HW_MAX)
+ return -EINVAL;
+ pev = mipspmu_map_general_event(event->attr.config);
+ } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+ pev = mipspmu_map_cache_event(event->attr.config);
+ } else if (PERF_TYPE_RAW == event->attr.type) {
+ /* We are working on the global raw event. */
+ mutex_lock(&raw_event_mutex);
+ pev = mipspmu->map_raw_event(event->attr.config);
+ } else {
+ /* The event type is not (yet) supported. */
+ return -EOPNOTSUPP;
+ }
+
+ if (IS_ERR(pev)) {
+ if (PERF_TYPE_RAW == event->attr.type)
+ mutex_unlock(&raw_event_mutex);
+ return PTR_ERR(pev);
+ }
+
+ /*
+ * We allow max flexibility on how each individual counter shared
+ * by the single CPU operates (the mode exclusion and the range).
+ */
+ hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
+
+ /* Calculate range bits and validate it. */
+ if (num_possible_cpus() > 1)
+ check_and_calc_range(event, pev);
+
+ hwc->event_base = mipspmu_perf_event_encode(pev);
+ if (PERF_TYPE_RAW == event->attr.type)
+ mutex_unlock(&raw_event_mutex);
+
+ if (!attr->exclude_user)
+ hwc->config_base |= M_PERFCTL_USER;
+ if (!attr->exclude_kernel) {
+ hwc->config_base |= M_PERFCTL_KERNEL;
+ /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
+ hwc->config_base |= M_PERFCTL_EXL;
+ }
+ if (!attr->exclude_hv)
+ hwc->config_base |= M_PERFCTL_SUPERVISOR;
+
+ hwc->config_base &= M_PERFCTL_CONFIG_MASK;
+ /*
+ * The event can belong to another cpu. We do not assign a local
+ * counter for it for now.
+ */
+ hwc->idx = -1;
+ hwc->config = 0;
+
+ if (!hwc->sample_period) {
+ hwc->sample_period = MAX_PERIOD;
+ hwc->last_period = hwc->sample_period;
+ local64_set(&hwc->period_left, hwc->sample_period);
+ }
+
+ err = 0;
+ if (event->group_leader != event) {
+ err = validate_group(event);
+ if (err)
+ return -EINVAL;
+ }
+
+ event->destroy = hw_perf_event_destroy;
+
+ return err;
+}
+
+static void pause_local_counters(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ int counters = mipspmu->num_counters;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ switch (counters) {
+ case 4:
+ cpuc->saved_ctrl[3] = r_c0_perfctrl3();
+ w_c0_perfctrl3(cpuc->saved_ctrl[3] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 3:
+ cpuc->saved_ctrl[2] = r_c0_perfctrl2();
+ w_c0_perfctrl2(cpuc->saved_ctrl[2] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 2:
+ cpuc->saved_ctrl[1] = r_c0_perfctrl1();
+ w_c0_perfctrl1(cpuc->saved_ctrl[1] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ case 1:
+ cpuc->saved_ctrl[0] = r_c0_perfctrl0();
+ w_c0_perfctrl0(cpuc->saved_ctrl[0] &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+ }
+ local_irq_restore(flags);
+}
+
+static void resume_local_counters(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ int counters = mipspmu->num_counters;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ switch (counters) {
+ case 4:
+ w_c0_perfctrl3(cpuc->saved_ctrl[3]);
+ case 3:
+ w_c0_perfctrl2(cpuc->saved_ctrl[2]);
+ case 2:
+ w_c0_perfctrl1(cpuc->saved_ctrl[1]);
+ case 1:
+ w_c0_perfctrl0(cpuc->saved_ctrl[0]);
+ }
+ local_irq_restore(flags);
+}
+
+static int mipsxx_pmu_handle_shared_irq(void)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct perf_sample_data data;
+ unsigned int counters = mipspmu->num_counters;
+ unsigned int counter;
+ int handled = IRQ_NONE;
+ struct pt_regs *regs;
+
+ if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+ return handled;
+
+ /*
+ * First we pause the local counters, so that when we are locked
+ * here, the counters are all paused. When it gets locked due to
+ * perf_disable(), the timer interrupt handler will be delayed.
+ *
+ * See also mipsxx_pmu_start().
+ */
+ pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+ read_lock(&pmuint_rwlock);
+#endif
+
+ regs = get_irq_regs();
+
+ perf_sample_data_init(&data, 0);
+
+ switch (counters) {
+#define HANDLE_COUNTER(n) \
+ case n + 1: \
+ if (test_bit(n, cpuc->used_mask)) { \
+ counter = r_c0_perfcntr ## n(); \
+ if (counter & M_COUNTER_OVERFLOW) { \
+ w_c0_perfcntr ## n(counter & \
+ VALID_COUNT); \
+ if (test_and_change_bit(n, cpuc->msbs)) \
+ handle_associated_event(cpuc, \
+ n, &data, regs); \
+ handled = IRQ_HANDLED; \
+ } \
+ }
+ HANDLE_COUNTER(3)
+ HANDLE_COUNTER(2)
+ HANDLE_COUNTER(1)
+ HANDLE_COUNTER(0)
+ }
+
+ /*
+ * Do all the work for the pending perf events. We can do this
+ * in here because the performance counter interrupt is a regular
+ * interrupt, not NMI.
+ */
+ if (handled == IRQ_HANDLED)
+ perf_event_do_pending();
+
+#ifdef CONFIG_MIPS_MT_SMP
+ read_unlock(&pmuint_rwlock);
+#endif
+ resume_local_counters();
+ return handled;
+}
+
+static irqreturn_t
+mipsxx_pmu_handle_irq(int irq, void *dev)
+{
+ return mipsxx_pmu_handle_shared_irq();
+}
+
+static void mipsxx_pmu_start(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+ write_unlock(&pmuint_rwlock);
+#endif
+ resume_local_counters();
+}
+
+/*
+ * MIPS performance counters can be per-TC. The control registers can
+ * not be directly accessed accross CPUs. Hence if we want to do global
+ * control, we need cross CPU calls. on_each_cpu() can help us, but we
+ * can not make sure this function is called with interrupts enabled. So
+ * here we pause local counters and then grab a rwlock and leave the
+ * counters on other CPUs alone. If any counter interrupt raises while
+ * we own the write lock, simply pause local counters on that CPU and
+ * spin in the handler. Also we know we won't be switched to another
+ * CPU after pausing local counters and before grabbing the lock.
+ */
+static void mipsxx_pmu_stop(void)
+{
+ pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+ write_lock(&pmuint_rwlock);
+#endif
+}
+
+static int
+mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
+ struct hw_perf_event *hwc)
+{
+ int i;
+
+ /*
+ * We only need to care the counter mask. The range has been
+ * checked definitely.
+ */
+ unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
+
+ for (i = mipspmu->num_counters - 1; i >= 0; i--) {
+ /*
+ * Note that some MIPS perf events can be counted by both
+ * even and odd counters, wheresas many other are only by
+ * even _or_ odd counters. This introduces an issue that
+ * when the former kind of event takes the counter the
+ * latter kind of event wants to use, then the "counter
+ * allocation" for the latter event will fail. In fact if
+ * they can be dynamically swapped, they both feel happy.
+ * But here we leave this issue alone for now.
+ */
+ if (test_bit(i, &cntr_mask) &&
+ !test_and_set_bit(i, cpuc->used_mask))
+ return i;
+ }
+
+ return -EAGAIN;
+}
+
+static void
+mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ local_irq_save(flags);
+ cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
+ (evt->config_base & M_PERFCTL_CONFIG_MASK) |
+ /* Make sure interrupt enabled. */
+ M_PERFCTL_INTERRUPT_ENABLE;
+ /*
+ * We do not actually let the counter run. Leave it until start().
+ */
+ local_irq_restore(flags);
+}
+
+static void
+mipsxx_pmu_disable_event(int idx)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ unsigned long flags;
+
+ WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+ local_irq_save(flags);
+ cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
+ ~M_PERFCTL_COUNT_EVENT_WHENEVER;
+ mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
+ local_irq_restore(flags);
+}
+
+/* 24K */
+#define IS_UNSUPPORTED_24K_EVENT(r, b) \
+ ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
+ (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
+ (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
+ (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
+ ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_24K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+
+/* 34K */
+#define IS_UNSUPPORTED_34K_EVENT(r, b) \
+ ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
+ (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
+ ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_34K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_34K_EVENT(r, b) \
+ ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
+ (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
+ (r) == 176 || ((b) >= 50 && (b) <= 55) || \
+ ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
+#endif
+
+/* 74K */
+#define IS_UNSUPPORTED_74K_EVENT(r, b) \
+ ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
+ ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
+ (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
+ (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
+ (b) == 61 || (r) == 62 || (r) == 191 || \
+ ((b) >= 64 && (b) <= 127))
+#define IS_BOTH_COUNTERS_74K_EVENT(b) \
+ ((b) == 0 || (b) == 1)
+
+/* 1004K */
+#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
+ ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
+ (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
+ ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_1004K_EVENT(r, b) \
+ ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
+ (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
+ (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
+ (r) == 188 || (b) == 61 || (b) == 62 || \
+ ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
+#endif
+
+/*
+ * User can use 0-255 raw events, where 0-127 for the events of even
+ * counters, and 128-255 for odd counters. Note that bit 7 is used to
+ * indicate the parity. So, for example, when user wants to take the
+ * Event Num of 15 for odd counters (by referring to the user manual),
+ * then 128 needs to be added to 15 as the input for the event config,
+ * i.e., 143 (0x8F) to be used.
+ */
+static const struct mips_perf_event *
+mipsxx_pmu_map_raw_event(u64 config)
+{
+ unsigned int raw_id = config & 0xff;
+ unsigned int base_id = raw_id & 0x7f;
+
+ switch (current_cpu_type()) {
+ case CPU_24K:
+ if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ /*
+ * This is actually doing nothing. Non-multithreading
+ * CPUs will not check and calculate the range.
+ */
+ raw_event.range = P;
+#endif
+ break;
+ case CPU_34K:
+ if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
+ raw_event.range = P;
+ else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
+ raw_event.range = V;
+ else
+ raw_event.range = T;
+#endif
+ break;
+ case CPU_74K:
+ if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ raw_event.range = P;
+#endif
+ break;
+ case CPU_1004K:
+ if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
+ return ERR_PTR(-EOPNOTSUPP);
+ raw_event.event_id = base_id;
+ if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ else
+ raw_event.cntr_mask =
+ raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+ if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
+ raw_event.range = P;
+ else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
+ raw_event.range = V;
+ else
+ raw_event.range = T;
+#endif
+ break;
+ }
+
+ return &raw_event;
+}
+
+static struct mips_pmu mipsxxcore_pmu = {
+ .handle_irq = mipsxx_pmu_handle_irq,
+ .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+ .start = mipsxx_pmu_start,
+ .stop = mipsxx_pmu_stop,
+ .alloc_counter = mipsxx_pmu_alloc_counter,
+ .read_counter = mipsxx_pmu_read_counter,
+ .write_counter = mipsxx_pmu_write_counter,
+ .enable_event = mipsxx_pmu_enable_event,
+ .disable_event = mipsxx_pmu_disable_event,
+ .map_raw_event = mipsxx_pmu_map_raw_event,
+ .general_event_map = &mipsxxcore_event_map,
+ .cache_event_map = &mipsxxcore_cache_map,
+};
+
+static struct mips_pmu mipsxx74Kcore_pmu = {
+ .handle_irq = mipsxx_pmu_handle_irq,
+ .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+ .start = mipsxx_pmu_start,
+ .stop = mipsxx_pmu_stop,
+ .alloc_counter = mipsxx_pmu_alloc_counter,
+ .read_counter = mipsxx_pmu_read_counter,
+ .write_counter = mipsxx_pmu_write_counter,
+ .enable_event = mipsxx_pmu_enable_event,
+ .disable_event = mipsxx_pmu_disable_event,
+ .map_raw_event = mipsxx_pmu_map_raw_event,
+ .general_event_map = &mipsxx74Kcore_event_map,
+ .cache_event_map = &mipsxx74Kcore_cache_map,
+};
+
+static int __init
+init_hw_perf_events(void)
+{
+ int counters, irq;
+
+ pr_info("Performance counters: ");
+
+ counters = n_counters();
+ if (counters == 0) {
+ pr_cont("No available PMU.\n");
+ return -ENODEV;
+ }
+
+#ifdef CONFIG_MIPS_MT_SMP
+ cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
+ if (!cpu_has_mipsmt_pertccounters)
+ counters = counters_total_to_per_cpu(counters);
+#endif
+
+#ifdef MSC01E_INT_BASE
+ if (cpu_has_veic) {
+ /*
+ * Using platform specific interrupt controller defines.
+ */
+ irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+ } else {
+#endif
+ if (cp0_perfcount_irq >= 0)
+ irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+ else
+ irq = -1;
+#ifdef MSC01E_INT_BASE
+ }
+#endif
+
+ on_each_cpu(reset_counters, (void *)(long)counters, 1);
+
+ switch (current_cpu_type()) {
+ case CPU_24K:
+ mipsxxcore_pmu.name = "mips/24K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ case CPU_34K:
+ mipsxxcore_pmu.name = "mips/34K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ case CPU_74K:
+ mipsxx74Kcore_pmu.name = "mips/74K";
+ mipsxx74Kcore_pmu.num_counters = counters;
+ mipsxx74Kcore_pmu.irq = irq;
+ mipspmu = &mipsxx74Kcore_pmu;
+ break;
+ case CPU_1004K:
+ mipsxxcore_pmu.name = "mips/1004K";
+ mipsxxcore_pmu.num_counters = counters;
+ mipsxxcore_pmu.irq = irq;
+ mipspmu = &mipsxxcore_pmu;
+ break;
+ default:
+ pr_cont("Either hardware does not support performance "
+ "counters, or not yet implemented.\n");
+ return -ENODEV;
+ }
+
+ if (mipspmu)
+ pr_cont("%s PMU enabled, %d counters available to each "
+ "CPU, irq %d%s\n", mipspmu->name, counters, irq,
+ irq < 0 ? " (share with timer interrupt)" : "");
+
+ return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+#endif /* defined(CONFIG_CPU_MIPS32)... */
bootmem_init();
device_tree_init();
sparse_init();
+ plat_swiotlb_setup();
paging_init();
}
#include <linux/notifier.h>
#include <linux/kdb.h>
#include <linux/irq.h>
+#include <linux/perf_event.h>
#include <asm/bootinfo.h>
#include <asm/branch.h>
*/
static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
{
- if ((opcode & OPCODE) == LL)
+ if ((opcode & OPCODE) == LL) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return simulate_ll(regs, opcode);
- if ((opcode & OPCODE) == SC)
+ }
+ if ((opcode & OPCODE) == SC) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return simulate_sc(regs, opcode);
+ }
return -1; /* Must be something else ... */
}
if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
int rd = (opcode & RD) >> 11;
int rt = (opcode & RT) >> 16;
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
switch (rd) {
case 0: /* CPU number */
regs->regs[rt] = smp_processor_id();
static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
{
- if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+ if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
return 0;
+ }
return -1; /* Must be something else ... */
}
{
unsigned int cpu = smp_processor_id();
unsigned int status_set = ST0_CU0;
+ unsigned int hwrena = cpu_hwrena_impl_bits;
#ifdef CONFIG_MIPS_MT_SMTC
int secondaryTC = 0;
int bootTC = (cpu == 0);
change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
status_set);
- if (cpu_has_mips_r2) {
- unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
+ if (cpu_has_mips_r2)
+ hwrena |= 0x0000000f;
- if (!noulri && cpu_has_userlocal)
- enable |= (1 << 29);
+ if (!noulri && cpu_has_userlocal)
+ hwrena |= (1 << 29);
- write_c0_hwrena(enable);
- }
+ if (hwrena)
+ write_c0_hwrena(hwrena);
#ifdef CONFIG_MIPS_MT_SMTC
if (!secondaryTC) {
#include <linux/smp.h>
#include <linux/sched.h>
#include <linux/debugfs.h>
+#include <linux/perf_event.h>
+
#include <asm/asm.h>
#include <asm/branch.h>
#include <asm/byteorder.h>
unsigned long value;
unsigned int res;
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, regs, 0);
+
/*
* This load never faults.
*/
unsigned int __user *pc;
mm_segment_t seg;
+ perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+ 1, 0, regs, regs->cp0_badvaddr);
/*
* Did we catch a fault trying to load an instruction?
* Or are we running in MIPS16 mode?
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
select LOONGSON_MC146818
select CS5536
select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
select DMA_NONCOHERENT
- select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select HW_HAS_PCI
select I8259
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/debugfs.h>
+#include <linux/perf_event.h>
#include <asm/inst.h>
#include <asm/bootinfo.h>
}
emul:
+ perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+ 1, 0, xcp, 0);
MIPS_FPU_EMU_INC_STATS(emulated);
switch (MIPSInst_OPCODE(ir)) {
case ldc1_op:{
unsigned int config1;
struct cpuinfo_mips *c = ¤t_cpu_data;
+ config1 = read_c0_config1();
switch (c->cputype) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
- config1 = read_c0_config1();
c->icache.linesz = 2 << ((config1 >> 19) & 7);
c->icache.sets = 64 << ((config1 >> 22) & 7);
c->icache.ways = 1 + ((config1 >> 16) & 7);
c->options |= MIPS_CPU_PREFETCH;
break;
+ case CPU_CAVIUM_OCTEON2:
+ c->icache.linesz = 2 << ((config1 >> 19) & 7);
+ c->icache.sets = 8;
+ c->icache.ways = 37;
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+ c->dcache.linesz = 128;
+ c->dcache.ways = 32;
+ c->dcache.sets = 8;
+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
default:
panic("Unsupported Cavium Networks CPU type\n");
break;
* o collapses to normal function call on UP kernels
* o collapses to normal function call on systems with a single shared
* primary cache.
+ * o doesn't disable interrupts on the local CPU
*/
-static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
- int wait)
+static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
{
preempt_disable();
#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
- smp_call_function(func, info, wait);
+ smp_call_function(func, info, 1);
#endif
func(info);
preempt_enable();
static void r4k___flush_cache_all(void)
{
- r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
+ r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
}
static inline int has_valid_asid(const struct mm_struct *mm)
int exec = vma->vm_flags & VM_EXEC;
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
- r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
}
static inline void local_r4k_flush_cache_mm(void * args)
if (!cpu_has_dc_aliases)
return;
- r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
}
struct flush_cache_page_args {
args.addr = addr;
args.pfn = pfn;
- r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
}
static inline void local_r4k_flush_data_cache_page(void * addr)
if (in_atomic())
local_r4k_flush_data_cache_page((void *)addr);
else
- r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
- 1);
+ r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
}
struct flush_icache_range_args {
args.start = start;
args.end = end;
- r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
+ r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
instruction_hazard();
}
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
- r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
+ r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
}
static void r4k_flush_icache_all(void)
return ret;
}
-
EXPORT_SYMBOL(dma_alloc_noncoherent);
-void *dma_alloc_coherent(struct device *dev, size_t size,
+static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, gfp_t gfp)
{
void *ret;
return ret;
}
-EXPORT_SYMBOL(dma_alloc_coherent);
void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
free_pages((unsigned long) vaddr, get_order(size));
}
-
EXPORT_SYMBOL(dma_free_noncoherent);
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
unsigned long addr = (unsigned long) vaddr;
free_pages(addr, get_order(size));
}
-EXPORT_SYMBOL(dma_free_coherent);
-
static inline void __dma_sync(unsigned long addr, size_t size,
enum dma_data_direction direction)
{
}
}
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
- enum dma_data_direction direction)
-{
- unsigned long addr = (unsigned long) ptr;
-
- if (!plat_device_is_coherent(dev))
- __dma_sync(addr, size, direction);
-
- return plat_map_dma_mem(dev, ptr, size);
-}
-
-EXPORT_SYMBOL(dma_map_single);
-
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
- enum dma_data_direction direction)
+static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+ size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
{
if (cpu_is_noncoherent_r10000(dev))
__dma_sync(dma_addr_to_virt(dev, dma_addr), size,
plat_unmap_dma_mem(dev, dma_addr, size, direction);
}
-EXPORT_SYMBOL(dma_unmap_single);
-
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction direction)
+static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
for (i = 0; i < nents; i++, sg++) {
unsigned long addr;
return nents;
}
-EXPORT_SYMBOL(dma_map_sg);
-
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction direction)
+static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
{
- BUG_ON(direction == DMA_NONE);
+ unsigned long addr;
- if (!plat_device_is_coherent(dev)) {
- unsigned long addr;
+ addr = (unsigned long) page_address(page) + offset;
- addr = (unsigned long) page_address(page) + offset;
+ if (!plat_device_is_coherent(dev))
__dma_sync(addr, size, direction);
- }
- return plat_map_dma_mem_page(dev, page) + offset;
+ return plat_map_dma_mem(dev, (void *)addr, size);
}
-EXPORT_SYMBOL(dma_map_page);
-
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
- enum dma_data_direction direction)
+static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nhwentries, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
{
unsigned long addr;
int i;
- BUG_ON(direction == DMA_NONE);
-
for (i = 0; i < nhwentries; i++, sg++) {
if (!plat_device_is_coherent(dev) &&
direction != DMA_TO_DEVICE) {
}
}
-EXPORT_SYMBOL(dma_unmap_sg);
-
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_cpu(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
- BUG_ON(direction == DMA_NONE);
-
if (cpu_is_noncoherent_r10000(dev)) {
unsigned long addr;
}
}
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_device(struct device *dev,
+ dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
{
- BUG_ON(direction == DMA_NONE);
-
plat_extra_sync_for_device(dev);
if (!plat_device_is_coherent(dev)) {
unsigned long addr;
}
}
-EXPORT_SYMBOL(dma_sync_single_for_device);
-
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, enum dma_data_direction direction)
-{
- BUG_ON(direction == DMA_NONE);
-
- if (cpu_is_noncoherent_r10000(dev)) {
- unsigned long addr;
-
- addr = dma_addr_to_virt(dev, dma_handle);
- __dma_sync(addr + offset, size, direction);
- }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
- unsigned long offset, size_t size, enum dma_data_direction direction)
-{
- BUG_ON(direction == DMA_NONE);
-
- plat_extra_sync_for_device(dev);
- if (!plat_device_is_coherent(dev)) {
- unsigned long addr;
-
- addr = dma_addr_to_virt(dev, dma_handle);
- __dma_sync(addr + offset, size, direction);
- }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_cpu(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nelems; i++, sg++) {
if (cpu_is_noncoherent_r10000(dev))
}
}
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg, int nelems, enum dma_data_direction direction)
{
int i;
- BUG_ON(direction == DMA_NONE);
-
/* Make sure that gcc doesn't leave the empty loop body. */
for (i = 0; i < nelems; i++, sg++) {
if (!plat_device_is_coherent(dev))
}
}
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return plat_dma_mapping_error(dev, dma_addr);
}
-EXPORT_SYMBOL(dma_mapping_error);
-
-int dma_supported(struct device *dev, u64 mask)
+int mips_dma_supported(struct device *dev, u64 mask)
{
return plat_dma_supported(dev, mask);
}
-EXPORT_SYMBOL(dma_supported);
-
-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
- enum dma_data_direction direction)
+void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+ enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
__dma_sync((unsigned long)vaddr, size, direction);
}
-EXPORT_SYMBOL(dma_cache_sync);
+static struct dma_map_ops mips_default_dma_map_ops = {
+ .alloc_coherent = mips_dma_alloc_coherent,
+ .free_coherent = mips_dma_free_coherent,
+ .map_page = mips_dma_map_page,
+ .unmap_page = mips_dma_unmap_page,
+ .map_sg = mips_dma_map_sg,
+ .unmap_sg = mips_dma_unmap_sg,
+ .sync_single_for_cpu = mips_dma_sync_single_for_cpu,
+ .sync_single_for_device = mips_dma_sync_single_for_device,
+ .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
+ .sync_sg_for_device = mips_dma_sync_sg_for_device,
+ .mapping_error = mips_dma_mapping_error,
+ .dma_supported = mips_dma_supported
+};
+
+struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
+EXPORT_SYMBOL(mips_dma_map_ops);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init mips_dma_init(void)
+{
+ dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+ return 0;
+}
+fs_initcall(mips_dma_init);
#include <linux/smp.h>
#include <linux/module.h>
#include <linux/kprobes.h>
+#include <linux/perf_event.h>
#include <asm/branch.h>
#include <asm/mmu_context.h>
* the fault.
*/
fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
if (unlikely(fault & VM_FAULT_ERROR)) {
if (fault & VM_FAULT_OOM)
goto out_of_memory;
goto do_sigbus;
BUG();
}
- if (fault & VM_FAULT_MAJOR)
+ if (fault & VM_FAULT_MAJOR) {
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
+ 1, 0, regs, address);
tsk->maj_flt++;
- else
+ } else {
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+ 1, 0, regs, address);
tsk->min_flt++;
+ }
up_read(&mm->mmap_sem);
return;
.bc_inv = mips_sc_inv
};
+/*
+ * Check if the L2 cache controller is activated on a particular platform.
+ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
+ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
+ * cache being disabled. However there is no guarantee for this to be
+ * true on all platforms. In an act of stupidity the spec defined bits
+ * 12..15 as implementation defined so below function will eventually have
+ * to be replaced by a platform specific probe.
+ */
+static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
+{
+ /* Check the bypass bit (L2B) */
+ switch (c->cputype) {
+ case CPU_34K:
+ case CPU_74K:
+ case CPU_1004K:
+ case CPU_BMIPS5000:
+ if (config2 & (1 << 12))
+ return 0;
+ }
+
+ tmp = (config2 >> 4) & 0x0f;
+ if (0 < tmp && tmp <= 7)
+ c->scache.linesz = 2 << tmp;
+ else
+ return 0;
+}
+
static inline int __init mips_sc_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
return 0;
config2 = read_c0_config2();
- tmp = (config2 >> 4) & 0x0f;
- if (0 < tmp && tmp <= 7)
- c->scache.linesz = 2 << tmp;
- else
+
+ if (!mips_sc_is_activated(c))
return 0;
tmp = (config2 >> 8) & 0x0f;
case CPU_4KSC:
case CPU_20KC:
case CPU_25KF:
- case CPU_BCM3302:
- case CPU_BCM4710:
+ case CPU_BMIPS32:
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4350:
+ case CPU_BMIPS4380:
+ case CPU_BMIPS5000:
case CPU_LOONGSON2:
- case CPU_BCM6338:
- case CPU_BCM6345:
- case CPU_BCM6348:
- case CPU_BCM6358:
case CPU_R5500:
if (m4kc_tlbp_war())
uasm_i_nop(p);
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u3u1u2(_or)
-I_u2s3u1(_pref)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#include <asm/octeon/octeon.h>
+void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
+ unsigned int c)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
+ /*
+ * As per erratum Core-14449, replace prefetches 0-4,
+ * 6-24 with 'pref 28'.
+ */
+ build_insn(buf, insn_pref, c, 28, b);
+ else
+ build_insn(buf, insn_pref, c, a, b);
+}
+UASM_EXPORT_SYMBOL(uasm_i_pref);
+#else
+I_u2s3u1(_pref)
+#endif
+
/* Handle labels. */
void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
+#include <linux/swiotlb.h>
#include <asm/time.h>
#include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/pci-octeon.h>
+#include <dma-coherence.h>
+
#define USE_OCTEON_INTERNAL_ARBITER
/*
/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
+u64 octeon_bar1_pci_phys;
+
/**
* This is the bit decoding used for the Octeon PCI controller addresses
*/
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
}
+ dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
+
return 0;
}
* before the readl()'s below. We don't want BAR2 overlapping
* with BAR0/BAR1 during these reads.
*/
- octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
- octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
-
- /* Disable the BAR1 movable mappings */
- for (index = 0; index < 32; index++)
- octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+ octeon_npi_write32(CVMX_NPI_PCI_CFG08,
+ (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
+ octeon_npi_write32(CVMX_NPI_PCI_CFG09,
+ (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
/* Remap the Octeon BAR 0 to 0-2GB */
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+ /* BAR1 movable mappings set for identity mapping */
+ octeon_bar1_pci_phys = 0x80000000ull;
+ for (index = 0; index < 32; index++) {
+ union cvmx_pci_bar1_indexx bar1_index;
+
+ bar1_index.u32 = 0;
+ /* Address bits[35:22] sent to L2C */
+ bar1_index.s.addr_idx =
+ (octeon_bar1_pci_phys >> 22) + index;
+ /* Don't put PCI accesses in L2. */
+ bar1_index.s.ca = 1;
+ /* Endian Swap Mode */
+ bar1_index.s.end_swp = 1;
+ /* Set '1' when the selected address range is valid. */
+ bar1_index.s.addr_v = 1;
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+ bar1_index.u32);
+ }
+
/* Devices go after BAR1 */
octeon_pci_mem_resource.start =
OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+ /* BAR1 movable regions contiguous to cover the swiotlb */
+ octeon_bar1_pci_phys =
+ virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
+
+ for (index = 0; index < 32; index++) {
+ union cvmx_pci_bar1_indexx bar1_index;
+
+ bar1_index.u32 = 0;
+ /* Address bits[35:22] sent to L2C */
+ bar1_index.s.addr_idx =
+ (octeon_bar1_pci_phys >> 22) + index;
+ /* Don't put PCI accesses in L2. */
+ bar1_index.s.ca = 1;
+ /* Endian Swap Mode */
+ bar1_index.s.end_swp = 1;
+ /* Set '1' when the selected address range is valid. */
+ bar1_index.s.addr_v = 1;
+ octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+ bar1_index.u32);
+ }
+
/* Devices go after BAR0 */
octeon_pci_mem_resource.start =
OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
* was setup properly.
*/
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+
+ octeon_pci_dma_init();
+
return 0;
}
} mem;
};
+#include <dma-coherence.h>
+
/**
* Return the Core virtual base address for PCIe IO access. IOs are
* read/written as an offset from this address.
cvmx_pcie_get_io_size(1) - 1;
register_pci_controller(&octeon_pcie1_controller);
}
+
+ octeon_pci_dma_init();
+
return 0;
}
bool
config FSL_LBC
- bool
+ bool "Freescale Local Bus support"
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence <nick.spence@freescale.com>,
* Scott Wood <scottwood@freescale.com>
+ * Jack Lan <jack.lan@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
struct fsl_lbc_bank {
__be32 br; /**< Base Register */
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_CS 0x00080000
+#define LTESR_UPM 0x00000002
#define LTESR_CC 0x00000001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+ | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+ | LTESR_CC)
+#define LTESR_CLEAR 0xFFFFFFFF
+#define LTECCR_CLEAR 0xFFFFFFFF
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x00000000
__be32 ltedr; /**< Transfer Error Disable Register */
__be32 lteir; /**< Transfer Error Interrupt Register */
__be32 lteatr; /**< Transfer Error Attributes Register */
__be32 ltear; /**< Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /**< Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr; /**< Configuration Register */
#define LBCR_LDIS 0x80000000
#define LBCR_LDIS_SHIFT 31
int width;
};
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void *nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned int irq_status;
+};
+
extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
#endif /* __ASM_FSL_LBC_H */
asm(".long 0x7d821008"); /* twge r2, r2 */
}
#define CACHE_FLUSH_IS_SAFE 1
+#define DBG_MAX_REG_NUM 70
/* The number bytes of registers we have to save depends on a few
* things. For 64bit we default to not including vector registers and
ptr = (unsigned long *)ptr32; \
} while (0)
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- unsigned long *ptr = gdb_regs;
- int reg;
-
- memset(gdb_regs, 0, NUMREGBYTES);
-
- for (reg = 0; reg < 32; reg++)
- PACK64(ptr, regs->gpr[reg]);
-
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
- for (reg = 0; reg < 32; reg++)
- PACK64(ptr, current->thread.evr[reg]);
-#else
- ptr += 32;
-#endif
-#else
- /* fp registers not used by kernel, leave zero */
- ptr += 32 * 8 / sizeof(long);
-#endif
-
- PACK64(ptr, regs->nip);
- PACK64(ptr, regs->msr);
- PACK32(ptr, regs->ccr);
- PACK64(ptr, regs->link);
- PACK64(ptr, regs->ctr);
- PACK32(ptr, regs->xer);
-
- BUG_ON((unsigned long)ptr >
- (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
-}
-
void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
{
struct pt_regs *regs = (struct pt_regs *)(p->thread.ksp +
(unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
}
-#define UNPACK64(dest, ptr) do { dest = *(ptr++); } while (0)
+#define GDB_SIZEOF_REG sizeof(unsigned long)
+#define GDB_SIZEOF_REG_U32 sizeof(u32)
-#define UNPACK32(dest, ptr) do { \
- u32 *ptr32; \
- ptr32 = (u32 *)ptr; \
- dest = *(ptr32++); \
- ptr = (unsigned long *)ptr32; \
- } while (0)
+#ifdef CONFIG_FSL_BOOKE
+#define GDB_SIZEOF_FLOAT_REG sizeof(unsigned long)
+#else
+#define GDB_SIZEOF_FLOAT_REG sizeof(u64)
+#endif
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
{
- unsigned long *ptr = gdb_regs;
- int reg;
-
- for (reg = 0; reg < 32; reg++)
- UNPACK64(regs->gpr[reg], ptr);
+ { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[0]) },
+ { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[1]) },
+ { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[2]) },
+ { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[3]) },
+ { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[4]) },
+ { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[5]) },
+ { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[6]) },
+ { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[7]) },
+ { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[8]) },
+ { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[9]) },
+ { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[10]) },
+ { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[11]) },
+ { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[12]) },
+ { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[13]) },
+ { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[14]) },
+ { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[15]) },
+ { "r16", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[16]) },
+ { "r17", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[17]) },
+ { "r18", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[18]) },
+ { "r19", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[19]) },
+ { "r20", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[20]) },
+ { "r21", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[21]) },
+ { "r22", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[22]) },
+ { "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[23]) },
+ { "r24", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[24]) },
+ { "r25", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[25]) },
+ { "r26", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[26]) },
+ { "r27", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[27]) },
+ { "r28", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[28]) },
+ { "r29", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[29]) },
+ { "r30", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[30]) },
+ { "r31", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[31]) },
+
+ { "f0", GDB_SIZEOF_FLOAT_REG, 0 },
+ { "f1", GDB_SIZEOF_FLOAT_REG, 1 },
+ { "f2", GDB_SIZEOF_FLOAT_REG, 2 },
+ { "f3", GDB_SIZEOF_FLOAT_REG, 3 },
+ { "f4", GDB_SIZEOF_FLOAT_REG, 4 },
+ { "f5", GDB_SIZEOF_FLOAT_REG, 5 },
+ { "f6", GDB_SIZEOF_FLOAT_REG, 6 },
+ { "f7", GDB_SIZEOF_FLOAT_REG, 7 },
+ { "f8", GDB_SIZEOF_FLOAT_REG, 8 },
+ { "f9", GDB_SIZEOF_FLOAT_REG, 9 },
+ { "f10", GDB_SIZEOF_FLOAT_REG, 10 },
+ { "f11", GDB_SIZEOF_FLOAT_REG, 11 },
+ { "f12", GDB_SIZEOF_FLOAT_REG, 12 },
+ { "f13", GDB_SIZEOF_FLOAT_REG, 13 },
+ { "f14", GDB_SIZEOF_FLOAT_REG, 14 },
+ { "f15", GDB_SIZEOF_FLOAT_REG, 15 },
+ { "f16", GDB_SIZEOF_FLOAT_REG, 16 },
+ { "f17", GDB_SIZEOF_FLOAT_REG, 17 },
+ { "f18", GDB_SIZEOF_FLOAT_REG, 18 },
+ { "f19", GDB_SIZEOF_FLOAT_REG, 19 },
+ { "f20", GDB_SIZEOF_FLOAT_REG, 20 },
+ { "f21", GDB_SIZEOF_FLOAT_REG, 21 },
+ { "f22", GDB_SIZEOF_FLOAT_REG, 22 },
+ { "f23", GDB_SIZEOF_FLOAT_REG, 23 },
+ { "f24", GDB_SIZEOF_FLOAT_REG, 24 },
+ { "f25", GDB_SIZEOF_FLOAT_REG, 25 },
+ { "f26", GDB_SIZEOF_FLOAT_REG, 26 },
+ { "f27", GDB_SIZEOF_FLOAT_REG, 27 },
+ { "f28", GDB_SIZEOF_FLOAT_REG, 28 },
+ { "f29", GDB_SIZEOF_FLOAT_REG, 29 },
+ { "f30", GDB_SIZEOF_FLOAT_REG, 30 },
+ { "f31", GDB_SIZEOF_FLOAT_REG, 31 },
+
+ { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, nip) },
+ { "msr", GDB_SIZEOF_REG, offsetof(struct pt_regs, msr) },
+ { "cr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ccr) },
+ { "lr", GDB_SIZEOF_REG, offsetof(struct pt_regs, link) },
+ { "ctr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ctr) },
+ { "xer", GDB_SIZEOF_REG, offsetof(struct pt_regs, xer) },
+};
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
- for (reg = 0; reg < 32; reg++)
- UNPACK64(current->thread.evr[reg], ptr);
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+ if (regno >= DBG_MAX_REG_NUM || regno < 0)
+ return NULL;
+
+ if (regno < 32 || regno >= 64)
+ /* First 0 -> 31 gpr registers*/
+ /* pc, msr, ls... registers 64 -> 69 */
+ memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+ dbg_reg_def[regno].size);
+
+ if (regno >= 32 && regno < 64) {
+ /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+ if (current)
+ memcpy(mem, current->thread.evr[regno-32],
+ dbg_reg_def[regno].size);
#else
- ptr += 32;
+ /* fp registers not used by kernel, leave zero */
+ memset(mem, 0, dbg_reg_def[regno].size);
#endif
+ }
+
+ return dbg_reg_def[regno].name;
+}
+
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
+{
+ if (regno >= DBG_MAX_REG_NUM || regno < 0)
+ return -EINVAL;
+
+ if (regno < 32 || regno >= 64)
+ /* First 0 -> 31 gpr registers*/
+ /* pc, msr, ls... registers 64 -> 69 */
+ memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+ dbg_reg_def[regno].size);
+
+ if (regno >= 32 && regno < 64) {
+ /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+ memcpy(current->thread.evr[regno-32], mem,
+ dbg_reg_def[regno].size);
#else
- /* fp registers not used by kernel, leave zero */
- ptr += 32 * 8 / sizeof(int);
+ /* fp registers not used by kernel, leave zero */
+ return 0;
#endif
+ }
- UNPACK64(regs->nip, ptr);
- UNPACK64(regs->msr, ptr);
- UNPACK32(regs->ccr, ptr);
- UNPACK64(regs->link, ptr);
- UNPACK64(regs->ctr, ptr);
- UNPACK32(regs->xer, ptr);
-
- BUG_ON((unsigned long)ptr >
- (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
+ return 0;
}
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
return spufs_create_root(sb, data);
}
-static int
-spufs_get_sb(struct file_system_type *fstype, int flags,
- const char *name, void *data, struct vfsmount *mnt)
+static struct dentry *
+spufs_mount(struct file_system_type *fstype, int flags,
+ const char *name, void *data)
{
- return get_sb_single(fstype, flags, data, spufs_fill_super, mnt);
+ return mount_single(fstype, flags, data, spufs_fill_super);
}
static struct file_system_type spufs_type = {
.owner = THIS_MODULE,
.name = "spufs",
- .get_sb = spufs_get_sb,
+ .mount = spufs_mount,
.kill_sb = kill_litter_super,
};
/*
* Freescale LBC and UPM routines.
*
- * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ * Copyright © 2007-2008 MontaVista Software, Inc.
+ * Copyright © 2010 Freescale Semiconductor
*
* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ * Author: Jack Lan <Jack.Lan@freescale.com>
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/types.h>
#include <linux/io.h>
#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mod_devicetable.h>
#include <asm/prom.h>
#include <asm/fsl_lbc.h>
static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
+EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
-static char __initdata *compat_lbc[] = {
- "fsl,pq2-localbus",
- "fsl,pq2pro-localbus",
- "fsl,pq3-localbus",
- "fsl,elbc",
-};
-
-static int __init fsl_lbc_init(void)
+/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
+ * BR register. If the SOC has eLBC then it returns 32bit physical address
+ * else it convers a 34bit local bus physical address to correct format of
+ * 32bit address for BR register (Example: MPC8641).
+ */
+u32 fsl_lbc_addr(phys_addr_t addr_base)
{
- struct device_node *lbus;
- int i;
+ struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
+ u32 addr = addr_base & 0xffff8000;
- for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
- lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
- if (lbus)
- goto found;
- }
- return -ENODEV;
+ if (of_device_is_compatible(np, "fsl,elbc"))
+ return addr;
-found:
- fsl_lbc_regs = of_iomap(lbus, 0);
- of_node_put(lbus);
- if (!fsl_lbc_regs)
- return -ENOMEM;
- return 0;
+ return addr | ((addr_base & 0x300000000ull) >> 19);
}
-arch_initcall(fsl_lbc_init);
+EXPORT_SYMBOL(fsl_lbc_addr);
/**
* fsl_lbc_find - find Localbus bank
int fsl_lbc_find(phys_addr_t addr_base)
{
int i;
+ struct fsl_lbc_regs __iomem *lbc;
- if (!fsl_lbc_regs)
+ if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
return -ENODEV;
- for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
- __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
- __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
+ lbc = fsl_lbc_ctrl_dev->regs;
+ for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
+ __be32 br = in_be32(&lbc->bank[i].br);
+ __be32 or = in_be32(&lbc->bank[i].or);
- if (br & BR_V && (br & or & BR_BA) == addr_base)
+ if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
return i;
}
{
int bank;
__be32 br;
+ struct fsl_lbc_regs __iomem *lbc;
bank = fsl_lbc_find(addr_base);
if (bank < 0)
return bank;
- br = in_be32(&fsl_lbc_regs->bank[bank].br);
+ if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
+ return -ENODEV;
+
+ lbc = fsl_lbc_ctrl_dev->regs;
+ br = in_be32(&lbc->bank[bank].br);
switch (br & BR_MSEL) {
case BR_MS_UPMA:
- upm->mxmr = &fsl_lbc_regs->mamr;
+ upm->mxmr = &lbc->mamr;
break;
case BR_MS_UPMB:
- upm->mxmr = &fsl_lbc_regs->mbmr;
+ upm->mxmr = &lbc->mbmr;
break;
case BR_MS_UPMC:
- upm->mxmr = &fsl_lbc_regs->mcmr;
+ upm->mxmr = &lbc->mcmr;
break;
default:
return -EINVAL;
int ret = 0;
unsigned long flags;
+ if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
+ return -ENODEV;
+
spin_lock_irqsave(&fsl_lbc_lock, flags);
- out_be32(&fsl_lbc_regs->mar, mar);
+ out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
switch (upm->width) {
case 8:
return ret;
}
EXPORT_SYMBOL(fsl_upm_run_pattern);
+
+static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
+{
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+
+ /* clear event registers */
+ setbits32(&lbc->ltesr, LTESR_CLEAR);
+ out_be32(&lbc->lteatr, 0);
+ out_be32(&lbc->ltear, 0);
+ out_be32(&lbc->lteccr, LTECCR_CLEAR);
+ out_be32(&lbc->ltedr, LTEDR_ENABLE);
+
+ /* Enable interrupts for any detected events */
+ out_be32(&lbc->lteir, LTEIR_ENABLE);
+
+ return 0;
+}
+
+/*
+ * NOTE: This interrupt is used to report localbus events of various kinds,
+ * such as transaction errors on the chipselects.
+ */
+
+static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
+{
+ struct fsl_lbc_ctrl *ctrl = data;
+ struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+ u32 status;
+
+ status = in_be32(&lbc->ltesr);
+ if (!status)
+ return IRQ_NONE;
+
+ out_be32(&lbc->ltesr, LTESR_CLEAR);
+ out_be32(&lbc->lteatr, 0);
+ out_be32(&lbc->ltear, 0);
+ ctrl->irq_status = status;
+
+ if (status & LTESR_BM)
+ dev_err(ctrl->dev, "Local bus monitor time-out: "
+ "LTESR 0x%08X\n", status);
+ if (status & LTESR_WP)
+ dev_err(ctrl->dev, "Write protect error: "
+ "LTESR 0x%08X\n", status);
+ if (status & LTESR_ATMW)
+ dev_err(ctrl->dev, "Atomic write error: "
+ "LTESR 0x%08X\n", status);
+ if (status & LTESR_ATMR)
+ dev_err(ctrl->dev, "Atomic read error: "
+ "LTESR 0x%08X\n", status);
+ if (status & LTESR_CS)
+ dev_err(ctrl->dev, "Chip select error: "
+ "LTESR 0x%08X\n", status);
+ if (status & LTESR_UPM)
+ ;
+ if (status & LTESR_FCT) {
+ dev_err(ctrl->dev, "FCM command time-out: "
+ "LTESR 0x%08X\n", status);
+ smp_wmb();
+ wake_up(&ctrl->irq_wait);
+ }
+ if (status & LTESR_PAR) {
+ dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
+ "LTESR 0x%08X\n", status);
+ smp_wmb();
+ wake_up(&ctrl->irq_wait);
+ }
+ if (status & LTESR_CC) {
+ smp_wmb();
+ wake_up(&ctrl->irq_wait);
+ }
+ if (status & ~LTESR_MASK)
+ dev_err(ctrl->dev, "Unknown error: "
+ "LTESR 0x%08X\n", status);
+ return IRQ_HANDLED;
+}
+
+/*
+ * fsl_lbc_ctrl_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code allocates all of
+ * the resources needed for the controller only. The
+ * resources for the NAND banks themselves are allocated
+ * in the chip probe function.
+*/
+
+static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
+{
+ int ret;
+
+ if (!dev->dev.of_node) {
+ dev_err(&dev->dev, "Device OF-Node is NULL");
+ return -EFAULT;
+ }
+
+ fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
+ if (!fsl_lbc_ctrl_dev)
+ return -ENOMEM;
+
+ dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
+
+ spin_lock_init(&fsl_lbc_ctrl_dev->lock);
+ init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
+
+ fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
+ if (!fsl_lbc_ctrl_dev->regs) {
+ dev_err(&dev->dev, "failed to get memory region\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+ if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
+ dev_err(&dev->dev, "failed to get irq resource\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ fsl_lbc_ctrl_dev->dev = &dev->dev;
+
+ ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
+ if (ret < 0)
+ goto err;
+
+ ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
+ "fsl-lbc", fsl_lbc_ctrl_dev);
+ if (ret != 0) {
+ dev_err(&dev->dev, "failed to install irq (%d)\n",
+ fsl_lbc_ctrl_dev->irq);
+ ret = fsl_lbc_ctrl_dev->irq;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ iounmap(fsl_lbc_ctrl_dev->regs);
+ kfree(fsl_lbc_ctrl_dev);
+ return ret;
+}
+
+static const struct of_device_id fsl_lbc_match[] = {
+ { .compatible = "fsl,elbc", },
+ { .compatible = "fsl,pq3-localbus", },
+ { .compatible = "fsl,pq2-localbus", },
+ { .compatible = "fsl,pq2pro-localbus", },
+ {},
+};
+
+static struct platform_driver fsl_lbc_ctrl_driver = {
+ .driver = {
+ .name = "fsl-lbc",
+ .of_match_table = fsl_lbc_match,
+ },
+ .probe = fsl_lbc_ctrl_probe,
+};
+
+static int __init fsl_lbc_init(void)
+{
+ return platform_driver_register(&fsl_lbc_ctrl_driver);
+}
+module_init(fsl_lbc_init);
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_FTRACE_MCOUNT_RECORD
+ select HAVE_C_RECORDMCOUNT
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_DYNAMIC_FTRACE
select HAVE_FUNCTION_GRAPH_TRACER
config 64BIT
bool "64 bit kernel"
help
- Select this option if you have a 64 bit IBM zSeries machine
+ Select this option if you have an IBM z/Architecture machine
and want to use the 64 bit addressing mode.
config 32BIT
can be controlled through /sys/devices/system/cpu/cpu#.
Say N if you want to disable CPU hotplug.
+config SCHED_MC
+ def_bool y
+ prompt "Multi-core scheduler support"
+ depends on SMP
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places.
+
config SCHED_BOOK
bool "Book scheduler support"
- depends on SMP
+ depends on SMP && SCHED_MC
help
Book scheduler support improves the CPU scheduler's decision making
when dealing with machines that have several books.
depends on MARCH_G5
help
This option is required for IEEE compliant floating point arithmetic
- on older S/390 machines. Say Y unless you know your machine doesn't
+ on older ESA/390 machines. Say Y unless you know your machine doesn't
need this.
config COMPAT
space programs and it also selects the addressing mode option above.
The kernel parameter noexec=on will enable this feature and also
switch the addressing modes, default is disabled. Enabling this (via
- kernel parameter) on machines earlier than IBM System z9-109 EC/BC
- will reduce system performance.
+ kernel parameter) on machines earlier than IBM System z9 this will
+ reduce system performance.
comment "Code generation options"
default MARCH_G5
config MARCH_G5
- bool "S/390 model G5 and G6"
+ bool "System/390 model G5 and G6"
depends on !64BIT
help
Select this to build a 31 bit kernel that works
- on all S/390 and zSeries machines.
+ on all ESA/390 and z/Architecture machines.
config MARCH_Z900
- bool "IBM eServer zSeries model z800 and z900"
+ bool "IBM zSeries model z800 and z900"
help
- Select this to optimize for zSeries machines. This
- will enable some optimizations that are not available
- on older 31 bit only CPUs.
+ Select this to enable optimizations for model z800/z900 (2064 and
+ 2066 series). This will enable some optimizations that are not
+ available on older ESA/390 (31 Bit) only CPUs.
config MARCH_Z990
- bool "IBM eServer zSeries model z890 and z990"
+ bool "IBM zSeries model z890 and z990"
help
- Select this enable optimizations for model z890/z990.
- This will be slightly faster but does not work on
- older machines such as the z900.
+ Select this to enable optimizations for model z890/z990 (2084 and
+ 2086 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z9_109
bool "IBM System z9"
help
- Select this to enable optimizations for IBM System z9-109, IBM
- System z9 Enterprise Class (z9 EC), and IBM System z9 Business
- Class (z9 BC). The kernel will be slightly faster but will not
- work on older machines such as the z990, z890, z900, and z800.
+ Select this to enable optimizations for IBM System z9 (2094 and
+ 2096 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z10
bool "IBM System z10"
help
- Select this to enable optimizations for IBM System z10. The
- kernel will be slightly faster but will not work on older
- machines such as the z990, z890, z900, z800, z9-109, z9-ec
- and z9-bc.
+ Select this to enable optimizations for IBM System z10 (2097 and
+ 2098 series). The kernel will be slightly faster but will not work
+ on older machines.
config MARCH_Z196
bool "IBM zEnterprise 196"
help
- Select this to enable optimizations for IBM zEnterprise 196.
- The kernel will be slightly faster but will not work on older
- machines such as the z990, z890, z900, z800, z9-109, z9-ec,
- z9-bc, z10-ec and z10-bc.
+ Select this to enable optimizations for IBM zEnterprise 196
+ (2817 series). The kernel will be slightly faster but will not work
+ on older machines.
endchoice
pr_err("The hardware system does not support hypfs\n");
return -ENODATA;
}
- rc = diag224_get_name_table();
- if (rc) {
- diag204_free_buffer();
- pr_err("The hardware system does not provide all "
- "functions required by hypfs\n");
- }
if (diag204_info_type == INFO_EXT) {
rc = hypfs_dbfs_init();
if (rc)
- diag204_free_buffer();
+ return rc;
}
- return rc;
+ if (MACHINE_IS_LPAR) {
+ rc = diag224_get_name_table();
+ if (rc) {
+ pr_err("The hardware system does not provide all "
+ "functions required by hypfs\n");
+ debugfs_remove(dbfs_d204_file);
+ return rc;
+ }
+ }
+ return 0;
}
void hypfs_diag_exit(void)
return 0;
}
-static int hypfs_get_super(struct file_system_type *fst, int flags,
- const char *devname, void *data, struct vfsmount *mnt)
+static struct dentry *hypfs_mount(struct file_system_type *fst, int flags,
+ const char *devname, void *data)
{
- return get_sb_single(fst, flags, data, hypfs_fill_super, mnt);
+ return mount_single(fst, flags, data, hypfs_fill_super);
}
static void hypfs_kill_super(struct super_block *sb)
static struct file_system_type hypfs_type = {
.owner = THIS_MODULE,
.name = "s390_hypfs",
- .get_sb = hypfs_get_super,
+ .mount = hypfs_mount,
.kill_sb = hypfs_kill_super
};
int rssd_result_len;
} __attribute__ ((packed)) dasd_symmio_parms_t;
+/*
+ * Data returned by Sense Path Group ID (SNID)
+ */
+struct dasd_snid_data {
+ struct {
+ __u8 group:2;
+ __u8 reserve:2;
+ __u8 mode:1;
+ __u8 res:3;
+ } __attribute__ ((packed)) path_state;
+ __u8 pgid[11];
+} __attribute__ ((packed));
+
+struct dasd_snid_ioctl_data {
+ struct dasd_snid_data data;
+ __u8 path_mask;
+} __attribute__ ((packed));
+
+
/********************************************************************************
* SECTION: Definition of IOCTLs
*
/* Set Attributes (cache operations) */
#define BIODASDSATTR _IOW(DASD_IOCTL_LETTER,2,attrib_data_t)
+/* Get Sense Path Group ID (SNID) data */
+#define BIODASDSNID _IOWR(DASD_IOCTL_LETTER, 1, struct dasd_snid_ioctl_data)
+
#define BIODASDSYMMIO _IOWR(DASD_IOCTL_LETTER, 240, dasd_symmio_parms_t)
#endif /* DASD_H */
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only. This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-indent-level: 4
- * c-brace-imaginary-offset: 0
- * c-brace-offset: -4
- * c-argdecl-indent: 4
- * c-label-offset: -4
- * c-continued-statement-offset: 4
- * c-continued-brace-offset: 0
- * indent-tabs-mode: nil
- * tab-width: 8
- * End:
- */
DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base));
DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time));
/* constants used by the vdso */
- DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
- DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
- DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+ DEFINE(__CLOCK_REALTIME, CLOCK_REALTIME);
+ DEFINE(__CLOCK_MONOTONIC, CLOCK_MONOTONIC);
+ DEFINE(__CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
BLANK();
/* constants for SIGP */
DEFINE(__SIGP_STOP, sigp_stop);
static noinline __init void setup_hpage(void)
{
#ifndef CONFIG_DEBUG_PAGEALLOC
- unsigned int facilities;
-
if (!test_facility(2) || !test_facility(8))
return;
S390_lowcore.machine_flags |= MACHINE_FLAG_HPAGE;
# per was called from kernel, must be kprobes
#
kernel_per:
+ REENABLE_IRQS
mvi SP_SVCNR(%r15),0xff # set trap indication to pgm check
mvi SP_SVCNR+1(%r15),0xff
la %r2,SP_PTREGS(%r15) # address of register-save area
# per was called from kernel, must be kprobes
#
kernel_per:
+ REENABLE_IRQS
xc SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
la %r2,SP_PTREGS(%r15) # address of register-save area
brasl %r14,do_single_step
return 1;
ss_probe:
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_disable();
prepare_singlestep(p, regs);
kcb->kprobe_status = KPROBE_HIT_SS;
return 1;
goto out;
}
reset_current_kprobe();
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_enable();
out:
preempt_enable_no_resched();
regs->psw.mask |= kcb->kprobe_saved_imask;
if (kcb->kprobe_status == KPROBE_REENTER)
restore_previous_kprobe(kcb);
- else
+ else {
reset_current_kprobe();
+ if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+ local_irq_enable();
+ }
preempt_enable_no_resched();
break;
case KPROBE_HIT_ACTIVE:
case 0x2098:
strcpy(elf_platform, "z10");
break;
+ case 0x2817:
+ strcpy(elf_platform, "z196");
+ break;
}
}
for (i = 0; i < TOPOLOGY_NR_MAG; i++)
len += sprintf(page + len, " %d", info->mag[i]);
len += sprintf(page + len, "\n");
+#ifdef CONFIG_SCHED_MC
store_topology(info);
len += sprintf(page + len, "CPU Topology SW: ");
for (i = 0; i < TOPOLOGY_NR_MAG; i++)
len += sprintf(page + len, " %d", info->mag[i]);
len += sprintf(page + len, "\n");
+#endif
return len;
}
cpumask_t mask;
cpus_clear(mask);
- if (!topology_enabled || !MACHINE_HAS_TOPOLOGY)
- return cpu_possible_map;
+ if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) {
+ cpumask_copy(&mask, cpumask_of(cpu));
+ return mask;
+ }
while (info) {
if (cpu_isset(cpu, info->mask)) {
mask = info->mask;
.type __kernel_clock_getres,@function
__kernel_clock_getres:
.cfi_startproc
- chi %r2,CLOCK_REALTIME
+ chi %r2,__CLOCK_REALTIME
je 0f
- chi %r2,CLOCK_MONOTONIC
+ chi %r2,__CLOCK_MONOTONIC
jne 3f
0: ltr %r3,%r3
jz 2f /* res == NULL */
3: lhi %r1,__NR_clock_getres /* fallback to svc */
svc 0
br %r14
-4: .long CLOCK_REALTIME_RES
+4: .long __CLOCK_REALTIME_RES
.cfi_endproc
.size __kernel_clock_getres,.-__kernel_clock_getres
.cfi_startproc
basr %r5,0
0: al %r5,21f-0b(%r5) /* get &_vdso_data */
- chi %r2,CLOCK_REALTIME
+ chi %r2,__CLOCK_REALTIME
je 10f
- chi %r2,CLOCK_MONOTONIC
+ chi %r2,__CLOCK_MONOTONIC
jne 19f
/* CLOCK_MONOTONIC */
.type __kernel_clock_getres,@function
__kernel_clock_getres:
.cfi_startproc
- cghi %r2,CLOCK_REALTIME
+ cghi %r2,__CLOCK_REALTIME
je 0f
- cghi %r2,CLOCK_MONOTONIC
+ cghi %r2,__CLOCK_MONOTONIC
je 0f
cghi %r2,-2 /* CLOCK_THREAD_CPUTIME_ID for this thread */
jne 2f
2: lghi %r1,__NR_clock_getres /* fallback to svc */
svc 0
br %r14
-3: .quad CLOCK_REALTIME_RES
+3: .quad __CLOCK_REALTIME_RES
.cfi_endproc
.size __kernel_clock_getres,.-__kernel_clock_getres
__kernel_clock_gettime:
.cfi_startproc
larl %r5,_vdso_data
- cghi %r2,CLOCK_REALTIME
+ cghi %r2,__CLOCK_REALTIME
je 4f
cghi %r2,-2 /* CLOCK_THREAD_CPUTIME_ID for this thread */
je 9f
- cghi %r2,CLOCK_MONOTONIC
+ cghi %r2,__CLOCK_MONOTONIC
jne 12f
/* CLOCK_MONOTONIC */
__raw_writew(0, FPGA_LCDREG);
}
+const static struct fb_videomode ap325rxa_lcdc_modes[] = {
+ {
+ .name = "LB070WV1",
+ .xres = 800,
+ .yres = 480,
+ .left_margin = 32,
+ .right_margin = 160,
+ .hsync_len = 8,
+ .upper_margin = 63,
+ .lower_margin = 80,
+ .vsync_len = 1,
+ .sync = 0, /* hsync and vsync are active low */
+ },
+};
+
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.bpp = 16,
.interface_type = RGB18,
.clock_divider = 1,
- .lcd_cfg = {
- .name = "LB070WV1",
- .xres = 800,
- .yres = 480,
- .left_margin = 32,
- .right_margin = 160,
- .hsync_len = 8,
- .upper_margin = 63,
- .lower_margin = 80,
- .vsync_len = 1,
- .sync = 0, /* hsync and vsync are active low */
- },
+ .lcd_cfg = ap325rxa_lcdc_modes,
+ .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
};
/* LCDC */
+const static struct fb_videomode ecovec_lcd_modes[] = {
+ {
+ .name = "Panel",
+ .xres = 800,
+ .yres = 480,
+ .left_margin = 220,
+ .right_margin = 110,
+ .hsync_len = 70,
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+ .sync = 0, /* hsync and vsync are active low */
+ },
+};
+
+const static struct fb_videomode ecovec_dvi_modes[] = {
+ {
+ .name = "DVI",
+ .xres = 1280,
+ .yres = 720,
+ .left_margin = 220,
+ .right_margin = 110,
+ .hsync_len = 40,
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+ .sync = 0, /* hsync and vsync are active low */
+ },
+};
+
static struct sh_mobile_lcdc_info lcdc_info = {
.ch[0] = {
.interface_type = RGB18,
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
- .lcd_cfg = {
- .sync = 0, /* hsync and vsync are active low */
- },
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
- lcdc_info.ch[0].clock_divider = 1,
- lcdc_info.ch[0].lcd_cfg.name = "DVI";
- lcdc_info.ch[0].lcd_cfg.xres = 1280;
- lcdc_info.ch[0].lcd_cfg.yres = 720;
- lcdc_info.ch[0].lcd_cfg.left_margin = 220;
- lcdc_info.ch[0].lcd_cfg.right_margin = 110;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
+ lcdc_info.ch[0].clock_divider = 1;
+ lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes;
+ lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes);
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
} else {
/* Panel */
-
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
- lcdc_info.ch[0].clock_divider = 2,
- lcdc_info.ch[0].lcd_cfg.name = "Panel";
- lcdc_info.ch[0].lcd_cfg.xres = 800;
- lcdc_info.ch[0].lcd_cfg.yres = 480;
- lcdc_info.ch[0].lcd_cfg.left_margin = 220;
- lcdc_info.ch[0].lcd_cfg.right_margin = 110;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
+ lcdc_info.ch[0].clock_divider = 2;
+ lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes;
+ lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes);
gpio_set_value(GPIO_PTR1, 1);
},
};
+const static struct fb_videomode kfr2r09_lcdc_modes[] = {
+ {
+ .name = "TX07D34VM0AAA",
+ .xres = 240,
+ .yres = 400,
+ .left_margin = 0,
+ .right_margin = 16,
+ .hsync_len = 8,
+ .upper_margin = 0,
+ .lower_margin = 1,
+ .vsync_len = 1,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ },
+};
+
static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.interface_type = SYS18,
.clock_divider = 6,
.flags = LCDC_FLAGS_DWPOL,
- .lcd_cfg = {
- .name = "TX07D34VM0AAA",
- .xres = 240,
- .yres = 400,
- .left_margin = 0,
- .right_margin = 16,
- .hsync_len = 8,
- .upper_margin = 0,
- .lower_margin = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- },
+ .lcd_cfg = kfr2r09_lcdc_modes,
+ .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
.lcd_size_cfg = {
.width = 35,
.height = 58,
}
};
+const static struct fb_videomode migor_lcd_modes[] = {
+ {
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
+ .name = "LB070WV1",
+ .xres = 800,
+ .yres = 480,
+ .left_margin = 64,
+ .right_margin = 16,
+ .hsync_len = 120,
+ .sync = 0,
+#elif defined(CONFIG_SH_MIGOR_QVGA)
+ .name = "PH240320T",
+ .xres = 320,
+ .yres = 240,
+ .left_margin = 0,
+ .right_margin = 16,
+ .hsync_len = 8,
+ .sync = FB_SYNC_HOR_HIGH_ACT,
+#endif
+ .upper_margin = 1,
+ .lower_margin = 17,
+ .vsync_len = 2,
+ },
+};
+
static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
-#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
.interface_type = RGB16,
.clock_divider = 2,
- .lcd_cfg = {
- .name = "LB070WV1",
- .xres = 800,
- .yres = 480,
- .left_margin = 64,
- .right_margin = 16,
- .hsync_len = 120,
- .upper_margin = 1,
- .lower_margin = 17,
- .vsync_len = 2,
- .sync = 0,
- },
+ .lcd_cfg = migor_lcd_modes,
+ .num_cfg = ARRAY_SIZE(migor_lcd_modes),
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
},
}
-#endif
-#ifdef CONFIG_SH_MIGOR_QVGA
+#elif defined(CONFIG_SH_MIGOR_QVGA)
.clock_source = LCDC_CLK_PERIPHERAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
.interface_type = SYS16A,
.clock_divider = 10,
- .lcd_cfg = {
- .name = "PH240320T",
- .xres = 320,
- .yres = 240,
- .left_margin = 0,
- .right_margin = 16,
- .hsync_len = 8,
- .upper_margin = 1,
- .lower_margin = 17,
- .vsync_len = 2,
- .sync = FB_SYNC_HOR_HIGH_ACT,
- },
+ .lcd_cfg = migor_lcd_modes,
+ .num_cfg = ARRAY_SIZE(migor_lcd_modes),
.lcd_size_cfg = { /* 2.4 inch */
.width = 49,
.height = 37,
};
/* LCDC */
+const static struct fb_videomode lcdc_720p_modes[] = {
+ {
+ .name = "LB070WV1",
+ .sync = 0, /* hsync and vsync are active low */
+ .xres = 1280,
+ .yres = 720,
+ .left_margin = 220,
+ .right_margin = 110,
+ .hsync_len = 40,
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+ },
+};
+
+const static struct fb_videomode lcdc_vga_modes[] = {
+ {
+ .name = "LB070WV1",
+ .sync = 0, /* hsync and vsync are active low */
+ .xres = 640,
+ .yres = 480,
+ .left_margin = 105,
+ .right_margin = 50,
+ .hsync_len = 96,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .vsync_len = 2,
+ },
+};
+
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.bpp = 16,
.clock_divider = 1,
- .lcd_cfg = {
- .name = "LB070WV1",
- .sync = 0, /* hsync and vsync are active low */
- },
.lcd_size_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
if (sw & SW41_B) {
/* 720p */
- lcdc_info.ch[0].lcd_cfg.xres = 1280;
- lcdc_info.ch[0].lcd_cfg.yres = 720;
- lcdc_info.ch[0].lcd_cfg.left_margin = 220;
- lcdc_info.ch[0].lcd_cfg.right_margin = 110;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
+ lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
+ lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
} else {
/* VGA */
- lcdc_info.ch[0].lcd_cfg.xres = 640;
- lcdc_info.ch[0].lcd_cfg.yres = 480;
- lcdc_info.ch[0].lcd_cfg.left_margin = 105;
- lcdc_info.ch[0].lcd_cfg.right_margin = 50;
- lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
- lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
- lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
- lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
+ lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
+ lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
}
if (sw & SW41_A) {
select RTC_CLASS
select RTC_DRV_M48T59
select HAVE_IRQ_WORK
- select HAVE_PERF_EVENTS
- select PERF_USE_VMALLOC
select HAVE_DMA_ATTRS
select HAVE_DMA_API_DEBUG
select HAVE_ARCH_JUMP_LABEL
select RTC_DRV_BQ4802
select RTC_DRV_SUN4V
select RTC_DRV_STARFIRE
- select HAVE_IRQ_WORK
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
#ifdef __KERNEL__
#include <linux/types.h>
-#include <asm/system.h>
#define JUMP_LABEL_NOP_SIZE 4
"nop\n\t" \
"nop\n\t" \
".pushsection __jump_table, \"a\"\n\t"\
+ ".align 4\n\t" \
".word 1b, %l[" #label "], %c0\n\t" \
".popsection \n\t" \
: : "i" (key) : : label);\
unsigned long flags;
unsigned int cpu_irq;
int ret;
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
struct tt_entry *trap_table;
extern struct tt_entry trapbase_cpu1, trapbase_cpu2, trapbase_cpu3;
#endif
table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
INSTANTIATE(sparc_ttable)
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
trap_table = &trapbase_cpu1; INSTANTIATE(trap_table)
trap_table = &trapbase_cpu2; INSTANTIATE(trap_table)
trap_table = &trapbase_cpu3; INSTANTIATE(trap_table)
static inline unsigned long do_swap(volatile unsigned long *ptr,
unsigned long val)
{
- __asm__ __volatile__("swapa [%1] %2, %0\n\t" : "=&r"(val)
- : "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
+ __asm__ __volatile__("swapa [%2] %3, %0\n\t" : "=&r"(val)
+ : "0"(val), "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
: "memory");
return val;
}
call do_notify_resume
add %sp, STACKFRAME_SZ, %o0 ! pt_regs ptr
- /* Fall through. */
- ld [%sp + STACKFRAME_SZ + PT_PSR], %t_psr
- clr %l6
+ b signal_p
+ ld [%curptr + TI_FLAGS], %g2
+
ret_trap_continue:
sethi %hi(PSR_SYSCALL), %g1
andn %t_psr, %g1, %t_psr
__handle_user_windows:
call fault_in_user_windows
wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- /* Redo sched+sig checks */
- ldx [%g6 + TI_FLAGS], %l0
- andcc %l0, _TIF_NEED_RESCHED, %g0
-
- be,pt %xcc, 1f
- nop
- call schedule
- wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- ldx [%g6 + TI_FLAGS], %l0
-
-1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
- be,pt %xcc, __handle_user_windows_continue
- nop
- mov %l5, %o1
- add %sp, PTREGS_OFF, %o0
- mov %l0, %o2
-
- call do_notify_resume
- wrpr %g0, RTRAP_PSTATE, %pstate
- wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- /* Signal delivery can modify pt_regs tstate, so we must
- * reload it.
- */
- ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
- sethi %hi(0xf << 20), %l4
- and %l1, %l4, %l4
- ba,pt %xcc, __handle_user_windows_continue
+ ba,pt %xcc, __handle_preemption_continue
+ wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
- andn %l1, %l4, %l1
__handle_userfpu:
rd %fprs, %l5
andcc %l5, FPRS_FEF, %g0
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
sethi %hi(0xf << 20), %l4
and %l1, %l4, %l4
- ba,pt %xcc, __handle_signal_continue
+ ba,pt %xcc, __handle_preemption_continue
andn %l1, %l4, %l1
/* When returning from a NMI (%pil==15) interrupt we want to
bne,pn %xcc, __handle_preemption
andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
bne,pn %xcc, __handle_signal
-__handle_signal_continue:
ldub [%g6 + TI_WSAVED], %o2
brnz,pn %o2, __handle_user_windows
nop
-__handle_user_windows_continue:
sethi %hi(TSTATE_PEF), %o0
andcc %l1, %o0, %g0
__do_fault_siginfo(BUS_ADRERR, SIGBUS, tsk->thread.kregs, address);
}
+static void check_stack_aligned(unsigned long sp)
+{
+ if (sp & 0x7UL)
+ force_sig(SIGILL, current);
+}
+
void window_overflow_fault(void)
{
unsigned long sp;
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 1);
force_user_fault(sp, 1);
+
+ check_stack_aligned(sp);
}
void window_underflow_fault(unsigned long sp)
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 0);
force_user_fault(sp, 0);
+
+ check_stack_aligned(sp);
}
void window_ret_fault(struct pt_regs *regs)
if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
force_user_fault(sp + 0x38, 0);
force_user_fault(sp, 0);
+
+ check_stack_aligned(sp);
}
# prologue (push %ebp, mov %esp, %ebp) which breaks the function graph
# tracer assumptions. For i686, generic, core2 this is set by the
# compiler anyway
-cflags-$(CONFIG_FUNCTION_GRAPH_TRACER) += $(call cc-option,-maccumulate-outgoing-args)
+ifeq ($(CONFIG_FUNCTION_GRAPH_TRACER), y)
+ADD_ACCUMULATE_OUTGOING_ARGS := y
+endif
+
+# Work around to a bug with asm goto with first implementations of it
+# in gcc causing gcc to mess up the push and pop of the stack in some
+# uses of asm goto.
+ifeq ($(CONFIG_JUMP_LABEL), y)
+ADD_ACCUMULATE_OUTGOING_ARGS := y
+endif
+
+cflags-$(ADD_ACCUMULATE_OUTGOING_ARGS) += $(call cc-option,-maccumulate-outgoing-args)
# Bug fix for binutils: this option is required in order to keep
# binutils from generating NOPL instructions against our will.
*
* SGI UV architectural definitions
*
- * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_X86_UV_UV_HUB_H
*
* 1111110000000000
* 5432109876543210
- * pppppppppplc0cch
+ * pppppppppplc0cch Nehalem-EX
+ * ppppppppplcc0cch Westmere-EX
* sssssssssss
*
* p = pnode bits
unsigned char m_val;
unsigned char n_val;
struct uv_scir_s scir;
+ unsigned char apic_pnode_shift;
};
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
+union uvh_apicid {
+ unsigned long v;
+ struct uvh_apicid_s {
+ unsigned long local_apic_mask : 24;
+ unsigned long local_apic_shift : 5;
+ unsigned long unused1 : 3;
+ unsigned long pnode_mask : 24;
+ unsigned long pnode_shift : 5;
+ unsigned long unused2 : 3;
+ } s;
+};
+
/*
* Local & Global MMR space macros.
* Note: macros are intended to be used ONLY by inline functions
#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
+#define UVH_APICID 0x002D0E00L
#define UV_APIC_PNODE_SHIFT 6
/* Local Bus from cpu's perspective */
*/
static inline int uv_apicid_to_pnode(int apicid)
{
- return (apicid >> UV_APIC_PNODE_SHIFT);
+ return (apicid >> uv_hub_info->apic_pnode_shift);
}
/*
atomic_set(&stop_machine_first, 1);
wrote_text = 0;
/* Use __stop_machine() because the caller already got online_cpus. */
- __stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
+ __stop_machine(stop_machine_text_poke, (void *)&tpp, cpu_online_mask);
return addr;
}
#if defined(CONFIG_DYNAMIC_FTRACE) || defined(HAVE_JUMP_LABEL)
-unsigned char ideal_nop5[IDEAL_NOP_SIZE_5];
+#ifdef CONFIG_X86_64
+unsigned char ideal_nop5[5] = { 0x66, 0x66, 0x66, 0x66, 0x90 };
+#else
+unsigned char ideal_nop5[5] = { 0x3e, 0x8d, 0x74, 0x26, 0x00 };
+#endif
void __init arch_init_ideal_nop5(void)
{
- extern const unsigned char ftrace_test_p6nop[];
- extern const unsigned char ftrace_test_nop5[];
- extern const unsigned char ftrace_test_jmp[];
- int faulted = 0;
-
/*
- * There is no good nop for all x86 archs.
- * We will default to using the P6_NOP5, but first we
- * will test to make sure that the nop will actually
- * work on this CPU. If it faults, we will then
- * go to a lesser efficient 5 byte nop. If that fails
- * we then just use a jmp as our nop. This isn't the most
- * efficient nop, but we can not use a multi part nop
- * since we would then risk being preempted in the middle
- * of that nop, and if we enabled tracing then, it might
- * cause a system crash.
+ * There is no good nop for all x86 archs. This selection
+ * algorithm should be unified with the one in find_nop_table(),
+ * but this should be good enough for now.
*
- * TODO: check the cpuid to determine the best nop.
+ * For cases other than the ones below, use the safe (as in
+ * always functional) defaults above.
*/
- asm volatile (
- "ftrace_test_jmp:"
- "jmp ftrace_test_p6nop\n"
- "nop\n"
- "nop\n"
- "nop\n" /* 2 byte jmp + 3 bytes */
- "ftrace_test_p6nop:"
- P6_NOP5
- "jmp 1f\n"
- "ftrace_test_nop5:"
- ".byte 0x66,0x66,0x66,0x66,0x90\n"
- "1:"
- ".section .fixup, \"ax\"\n"
- "2: movl $1, %0\n"
- " jmp ftrace_test_nop5\n"
- "3: movl $2, %0\n"
- " jmp 1b\n"
- ".previous\n"
- _ASM_EXTABLE(ftrace_test_p6nop, 2b)
- _ASM_EXTABLE(ftrace_test_nop5, 3b)
- : "=r"(faulted) : "0" (faulted));
-
- switch (faulted) {
- case 0:
- pr_info("converting mcount calls to 0f 1f 44 00 00\n");
- memcpy(ideal_nop5, ftrace_test_p6nop, IDEAL_NOP_SIZE_5);
- break;
- case 1:
- pr_info("converting mcount calls to 66 66 66 66 90\n");
- memcpy(ideal_nop5, ftrace_test_nop5, IDEAL_NOP_SIZE_5);
- break;
- case 2:
- pr_info("converting mcount calls to jmp . + 5\n");
- memcpy(ideal_nop5, ftrace_test_jmp, IDEAL_NOP_SIZE_5);
- break;
- }
-
+#ifdef CONFIG_X86_64
+ /* Don't use these on 32 bits due to broken virtualizers */
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ memcpy(ideal_nop5, p6_nops[5], 5);
+#endif
}
#endif
irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
- if (intr_remapping_enabled)
+ if (irq_remapped(cfg))
free_irte(irq);
raw_spin_lock_irqsave(&vector_lock, flags);
__clear_irq_vector(irq, cfg);
*
* SGI UV APIC functions (note: not an Intel compatible APIC)
*
- * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
*/
#include <linux/cpumask.h>
#include <linux/hardirq.h>
static enum uv_system_type uv_system_type;
static u64 gru_start_paddr, gru_end_paddr;
+static union uvh_apicid uvh_apicid;
int uv_min_hub_revision_id;
EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
static DEFINE_SPINLOCK(uv_nmi_lock);
return node_id.s.node_id;
}
+static void __init early_get_apic_pnode_shift(void)
+{
+ unsigned long *mmr;
+
+ mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
+ uvh_apicid.v = *mmr;
+ early_iounmap(mmr, sizeof(*mmr));
+ if (!uvh_apicid.v)
+ /*
+ * Old bios, use default value
+ */
+ uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
+}
+
static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
int nodeid;
if (!strcmp(oem_id, "SGI")) {
nodeid = early_get_nodeid();
+ early_get_apic_pnode_shift();
x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
x86_platform.nmi_init = uv_nmi_init;
if (!strcmp(oem_table_id, "UVL"))
uv_system_type = UV_X2APIC;
else if (!strcmp(oem_table_id, "UVH")) {
__get_cpu_var(x2apic_extra_bits) =
- nodeid << (UV_APIC_PNODE_SHIFT - 1);
+ nodeid << (uvh_apicid.s.pnode_shift - 1);
uv_system_type = UV_NON_UNIQUE_APIC;
return 1;
}
int apicid = per_cpu(x86_cpu_to_apicid, cpu);
nid = cpu_to_node(cpu);
+ /*
+ * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
+ */
+ uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
pnode = uv_apicid_to_pnode(apicid);
blade = boot_pnode_to_blade(pnode);
lcpu = uv_blade_info[blade].nr_possible_cpus;
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/percpu.h>
+#include <linux/mm.h>
#include <asm/apic.h>
if (per_cpu(hardirq_ctx, cpu))
return;
- irqctx = (union irq_ctx *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER);
+ irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
+ THREAD_FLAGS,
+ THREAD_ORDER));
irqctx->tinfo.task = NULL;
irqctx->tinfo.exec_domain = NULL;
irqctx->tinfo.cpu = cpu;
per_cpu(hardirq_ctx, cpu) = irqctx;
- irqctx = (union irq_ctx *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER);
+ irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
+ THREAD_FLAGS,
+ THREAD_ORDER));
irqctx->tinfo.task = NULL;
irqctx->tinfo.exec_domain = NULL;
irqctx->tinfo.cpu = cpu;
* disable hardware debugging while it is processing gdb packets or
* handling exception.
*/
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void kgdb_disable_hw_debug(struct pt_regs *regs)
{
int i;
int cpu = raw_smp_processor_id();
.flags = KGDB_HW_BREAKPOINT,
.set_hw_breakpoint = kgdb_set_hw_break,
.remove_hw_breakpoint = kgdb_remove_hw_break,
+ .disable_hw_break = kgdb_disable_hw_debug,
.remove_all_hw_break = kgdb_remove_all_hw_break,
.correct_hw_break = kgdb_correct_hw_break,
};
/* extend the search scope */
end = max_pfn_mapped << PAGE_SHIFT;
- if (end > (MAX_DMA32_PFN<<PAGE_SHIFT))
- start = MAX_DMA32_PFN<<PAGE_SHIFT;
- else
- start = MAX_DMA_PFN<<PAGE_SHIFT;
- mem = memblock_x86_find_in_range_node(nodeid, start, end, size, align);
+ start = MAX_DMA_PFN << PAGE_SHIFT;
+ mem = memblock_find_in_range(start, end, size, align);
if (mem != MEMBLOCK_ERROR)
return __va(mem);
* Compute # of eclock periods to get desired duration in
* nanoseconds.
*/
- val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000),
+ val = DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
1000 * tim_mult);
return val;
static struct vfsmount *dev_mnt;
#if defined CONFIG_DEVTMPFS_MOUNT
-static int dev_mount = 1;
+static int mount_dev = 1;
#else
-static int dev_mount;
+static int mount_dev;
#endif
static DEFINE_MUTEX(dirlock);
static int __init mount_param(char *str)
{
- dev_mount = simple_strtoul(str, NULL, 0);
+ mount_dev = simple_strtoul(str, NULL, 0);
return 1;
}
__setup("devtmpfs.mount=", mount_param);
-static int dev_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *dev_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
#ifdef CONFIG_TMPFS
- return get_sb_single(fs_type, flags, data, shmem_fill_super, mnt);
+ return mount_single(fs_type, flags, data, shmem_fill_super);
#else
- return get_sb_single(fs_type, flags, data, ramfs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, ramfs_fill_super);
#endif
}
static struct file_system_type dev_fs_type = {
.name = "devtmpfs",
- .get_sb = dev_get_sb,
+ .mount = dev_mount,
.kill_sb = kill_litter_super,
};
{
int err;
- if (!dev_mount)
+ if (!mount_dev)
return 0;
if (!dev_mnt)
/* Pending resume requests take precedence over suspends. */
else if ((dev->power.deferred_resume
- && dev->power.status == RPM_SUSPENDING)
+ && dev->power.runtime_status == RPM_SUSPENDING)
|| (dev->power.request_pending
&& dev->power.request == RPM_REQ_RESUME))
retval = -EAGAIN;
#include <linux/klist.h>
#include <linux/agp_backend.h>
#include <linux/log2.h>
+#include <linux/slab.h>
#include <asm/parisc-device.h>
#include <asm/ropes.h>
}
/**
- * tty_audit_push_task - Flush task's pending audit data
+ * tty_audit_push_task - Flush task's pending audit data
+ * @tsk: task pointer
+ * @loginuid: sender login uid
+ * @sessionid: sender session id
+ *
+ * Called with a ref on @tsk held. Try to lock sighand and get a
+ * reference to the tty audit buffer if available.
+ * Flush the buffer or return an appropriate error code.
*/
-void tty_audit_push_task(struct task_struct *tsk, uid_t loginuid, u32 sessionid)
+int tty_audit_push_task(struct task_struct *tsk, uid_t loginuid, u32 sessionid)
{
- struct tty_audit_buf *buf;
+ struct tty_audit_buf *buf = ERR_PTR(-EPERM);
+ unsigned long flags;
- spin_lock_irq(&tsk->sighand->siglock);
- buf = tsk->signal->tty_audit_buf;
- if (buf)
- atomic_inc(&buf->count);
- spin_unlock_irq(&tsk->sighand->siglock);
- if (!buf)
- return;
+ if (!lock_task_sighand(tsk, &flags))
+ return -ESRCH;
+
+ if (tsk->signal->audit_tty) {
+ buf = tsk->signal->tty_audit_buf;
+ if (buf)
+ atomic_inc(&buf->count);
+ }
+ unlock_task_sighand(tsk, &flags);
+
+ /*
+ * Return 0 when signal->audit_tty set
+ * but tsk->signal->tty_audit_buf == NULL.
+ */
+ if (!buf || IS_ERR(buf))
+ return PTR_ERR(buf);
mutex_lock(&buf->mutex);
tty_audit_buf_push(tsk, loginuid, sessionid, buf);
mutex_unlock(&buf->mutex);
tty_audit_buf_put(buf);
+ return 0;
}
/**
platform_data for a dma-pl330 device.
config PCH_DMA
- tristate "Topcliff PCH DMA support"
+ tristate "Topcliff (Intel EG20T) PCH DMA support"
depends on PCI && X86
select DMA_ENGINE
help
- Enable support for the Topcliff PCH DMA engine.
+ Enable support for the Topcliff (Intel EG20T) PCH DMA engine.
config IMX_SDMA
tristate "i.MX SDMA support"
This driver can also be built as a module. If so, the module
will be called i2c-imx.
+config I2C_INTEL_MID
+ tristate "Intel Moorestown/Medfield Platform I2C controller"
+ depends on PCI
+ help
+ Say Y here if you have an Intel Moorestown/Medfield platform I2C
+ controller.
+
+ This support is also available as a module. If so, the module
+ will be called i2c-intel-mid.
+
config I2C_IOP3XX
tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
+obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
--- /dev/null
+/*
+ * Support for Moorestown/Medfield I2C chip
+ *
+ * Copyright (c) 2009 Intel Corporation.
+ * Copyright (c) 2009 Synopsys. Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License, version
+ * 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 51
+ * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
+#include <linux/io.h>
+
+#define DRIVER_NAME "i2c-intel-mid"
+#define VERSION "Version 0.5ac2"
+#define PLATFORM "Moorestown/Medfield"
+
+/* Tables use: 0 Moorestown, 1 Medfield */
+#define NUM_PLATFORMS 2
+enum platform_enum {
+ MOORESTOWN = 0,
+ MEDFIELD = 1,
+};
+
+enum mid_i2c_status {
+ STATUS_IDLE = 0,
+ STATUS_READ_START,
+ STATUS_READ_IN_PROGRESS,
+ STATUS_READ_SUCCESS,
+ STATUS_WRITE_START,
+ STATUS_WRITE_SUCCESS,
+ STATUS_XFER_ABORT,
+ STATUS_STANDBY
+};
+
+/**
+ * struct intel_mid_i2c_private - per device I²C context
+ * @adap: core i2c layer adapter information
+ * @dev: device reference for power management
+ * @base: register base
+ * @speed: speed mode for this port
+ * @complete: completion object for transaction wait
+ * @abort: reason for last abort
+ * @rx_buf: pointer into working receive buffer
+ * @rx_buf_len: receive buffer length
+ * @status: adapter state machine
+ * @msg: the message we are currently processing
+ * @platform: the MID device type we are part of
+ * @lock: transaction serialization
+ *
+ * We allocate one of these per device we discover, it holds the core
+ * i2c layer objects and the data we need to track privately.
+ */
+struct intel_mid_i2c_private {
+ struct i2c_adapter adap;
+ struct device *dev;
+ void __iomem *base;
+ int speed;
+ struct completion complete;
+ int abort;
+ u8 *rx_buf;
+ int rx_buf_len;
+ enum mid_i2c_status status;
+ struct i2c_msg *msg;
+ enum platform_enum platform;
+ struct mutex lock;
+};
+
+#define NUM_SPEEDS 3
+
+#define ACTIVE 0
+#define STANDBY 1
+
+
+/* Control register */
+#define IC_CON 0x00
+#define SLV_DIS (1 << 6) /* Disable slave mode */
+#define RESTART (1 << 5) /* Send a Restart condition */
+#define ADDR_10BIT (1 << 4) /* 10-bit addressing */
+#define STANDARD_MODE (1 << 1) /* standard mode */
+#define FAST_MODE (2 << 1) /* fast mode */
+#define HIGH_MODE (3 << 1) /* high speed mode */
+#define MASTER_EN (1 << 0) /* Master mode */
+
+/* Target address register */
+#define IC_TAR 0x04
+#define IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */
+#define IC_TAR_SPECIAL (1 << 11) /* Perform special I2C cmd */
+#define IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */
+ /* 1: START BYTE */
+/* Slave Address Register */
+#define IC_SAR 0x08 /* Not used in Master mode */
+
+/* High Speed Master Mode Code Address Register */
+#define IC_HS_MADDR 0x0c
+
+/* Rx/Tx Data Buffer and Command Register */
+#define IC_DATA_CMD 0x10
+#define IC_RD (1 << 8) /* 1: Read 0: Write */
+
+/* Standard Speed Clock SCL High Count Register */
+#define IC_SS_SCL_HCNT 0x14
+
+/* Standard Speed Clock SCL Low Count Register */
+#define IC_SS_SCL_LCNT 0x18
+
+/* Fast Speed Clock SCL High Count Register */
+#define IC_FS_SCL_HCNT 0x1c
+
+/* Fast Spedd Clock SCL Low Count Register */
+#define IC_FS_SCL_LCNT 0x20
+
+/* High Speed Clock SCL High Count Register */
+#define IC_HS_SCL_HCNT 0x24
+
+/* High Speed Clock SCL Low Count Register */
+#define IC_HS_SCL_LCNT 0x28
+
+/* Interrupt Status Register */
+#define IC_INTR_STAT 0x2c /* Read only */
+#define R_GEN_CALL (1 << 11)
+#define R_START_DET (1 << 10)
+#define R_STOP_DET (1 << 9)
+#define R_ACTIVITY (1 << 8)
+#define R_RX_DONE (1 << 7)
+#define R_TX_ABRT (1 << 6)
+#define R_RD_REQ (1 << 5)
+#define R_TX_EMPTY (1 << 4)
+#define R_TX_OVER (1 << 3)
+#define R_RX_FULL (1 << 2)
+#define R_RX_OVER (1 << 1)
+#define R_RX_UNDER (1 << 0)
+
+/* Interrupt Mask Register */
+#define IC_INTR_MASK 0x30 /* Read and Write */
+#define M_GEN_CALL (1 << 11)
+#define M_START_DET (1 << 10)
+#define M_STOP_DET (1 << 9)
+#define M_ACTIVITY (1 << 8)
+#define M_RX_DONE (1 << 7)
+#define M_TX_ABRT (1 << 6)
+#define M_RD_REQ (1 << 5)
+#define M_TX_EMPTY (1 << 4)
+#define M_TX_OVER (1 << 3)
+#define M_RX_FULL (1 << 2)
+#define M_RX_OVER (1 << 1)
+#define M_RX_UNDER (1 << 0)
+
+/* Raw Interrupt Status Register */
+#define IC_RAW_INTR_STAT 0x34 /* Read Only */
+#define GEN_CALL (1 << 11) /* General call */
+#define START_DET (1 << 10) /* (RE)START occured */
+#define STOP_DET (1 << 9) /* STOP occured */
+#define ACTIVITY (1 << 8) /* Bus busy */
+#define RX_DONE (1 << 7) /* Not used in Master mode */
+#define TX_ABRT (1 << 6) /* Transmit Abort */
+#define RD_REQ (1 << 5) /* Not used in Master mode */
+#define TX_EMPTY (1 << 4) /* TX FIFO <= threshold */
+#define TX_OVER (1 << 3) /* TX FIFO overflow */
+#define RX_FULL (1 << 2) /* RX FIFO >= threshold */
+#define RX_OVER (1 << 1) /* RX FIFO overflow */
+#define RX_UNDER (1 << 0) /* RX FIFO empty */
+
+/* Receive FIFO Threshold Register */
+#define IC_RX_TL 0x38
+
+/* Transmit FIFO Treshold Register */
+#define IC_TX_TL 0x3c
+
+/* Clear Combined and Individual Interrupt Register */
+#define IC_CLR_INTR 0x40
+#define CLR_INTR (1 << 0)
+
+/* Clear RX_UNDER Interrupt Register */
+#define IC_CLR_RX_UNDER 0x44
+#define CLR_RX_UNDER (1 << 0)
+
+/* Clear RX_OVER Interrupt Register */
+#define IC_CLR_RX_OVER 0x48
+#define CLR_RX_OVER (1 << 0)
+
+/* Clear TX_OVER Interrupt Register */
+#define IC_CLR_TX_OVER 0x4c
+#define CLR_TX_OVER (1 << 0)
+
+#define IC_CLR_RD_REQ 0x50
+
+/* Clear TX_ABRT Interrupt Register */
+#define IC_CLR_TX_ABRT 0x54
+#define CLR_TX_ABRT (1 << 0)
+#define IC_CLR_RX_DONE 0x58
+
+/* Clear ACTIVITY Interrupt Register */
+#define IC_CLR_ACTIVITY 0x5c
+#define CLR_ACTIVITY (1 << 0)
+
+/* Clear STOP_DET Interrupt Register */
+#define IC_CLR_STOP_DET 0x60
+#define CLR_STOP_DET (1 << 0)
+
+/* Clear START_DET Interrupt Register */
+#define IC_CLR_START_DET 0x64
+#define CLR_START_DET (1 << 0)
+
+/* Clear GEN_CALL Interrupt Register */
+#define IC_CLR_GEN_CALL 0x68
+#define CLR_GEN_CALL (1 << 0)
+
+/* Enable Register */
+#define IC_ENABLE 0x6c
+#define ENABLE (1 << 0)
+
+/* Status Register */
+#define IC_STATUS 0x70 /* Read Only */
+#define STAT_SLV_ACTIVITY (1 << 6) /* Slave not in idle */
+#define STAT_MST_ACTIVITY (1 << 5) /* Master not in idle */
+#define STAT_RFF (1 << 4) /* RX FIFO Full */
+#define STAT_RFNE (1 << 3) /* RX FIFO Not Empty */
+#define STAT_TFE (1 << 2) /* TX FIFO Empty */
+#define STAT_TFNF (1 << 1) /* TX FIFO Not Full */
+#define STAT_ACTIVITY (1 << 0) /* Activity Status */
+
+/* Transmit FIFO Level Register */
+#define IC_TXFLR 0x74 /* Read Only */
+#define TXFLR (1 << 0) /* TX FIFO level */
+
+/* Receive FIFO Level Register */
+#define IC_RXFLR 0x78 /* Read Only */
+#define RXFLR (1 << 0) /* RX FIFO level */
+
+/* Transmit Abort Source Register */
+#define IC_TX_ABRT_SOURCE 0x80
+#define ABRT_SLVRD_INTX (1 << 15)
+#define ABRT_SLV_ARBLOST (1 << 14)
+#define ABRT_SLVFLUSH_TXFIFO (1 << 13)
+#define ARB_LOST (1 << 12)
+#define ABRT_MASTER_DIS (1 << 11)
+#define ABRT_10B_RD_NORSTRT (1 << 10)
+#define ABRT_SBYTE_NORSTRT (1 << 9)
+#define ABRT_HS_NORSTRT (1 << 8)
+#define ABRT_SBYTE_ACKDET (1 << 7)
+#define ABRT_HS_ACKDET (1 << 6)
+#define ABRT_GCALL_READ (1 << 5)
+#define ABRT_GCALL_NOACK (1 << 4)
+#define ABRT_TXDATA_NOACK (1 << 3)
+#define ABRT_10ADDR2_NOACK (1 << 2)
+#define ABRT_10ADDR1_NOACK (1 << 1)
+#define ABRT_7B_ADDR_NOACK (1 << 0)
+
+/* Enable Status Register */
+#define IC_ENABLE_STATUS 0x9c
+#define IC_EN (1 << 0) /* I2C in an enabled state */
+
+/* Component Parameter Register 1*/
+#define IC_COMP_PARAM_1 0xf4
+#define APB_DATA_WIDTH (0x3 << 0)
+
+/* added by xiaolin --begin */
+#define SS_MIN_SCL_HIGH 4000
+#define SS_MIN_SCL_LOW 4700
+#define FS_MIN_SCL_HIGH 600
+#define FS_MIN_SCL_LOW 1300
+#define HS_MIN_SCL_HIGH_100PF 60
+#define HS_MIN_SCL_LOW_100PF 120
+
+#define STANDARD 0
+#define FAST 1
+#define HIGH 2
+
+#define NUM_SPEEDS 3
+
+static int speed_mode[6] = {
+ FAST,
+ FAST,
+ FAST,
+ STANDARD,
+ FAST,
+ FAST
+};
+
+static int ctl_num = 6;
+module_param_array(speed_mode, int, &ctl_num, S_IRUGO);
+MODULE_PARM_DESC(speed_mode, "Set the speed of the i2c interface (0-2)");
+
+/**
+ * intel_mid_i2c_disable - Disable I2C controller
+ * @adap: struct pointer to i2c_adapter
+ *
+ * Return Value:
+ * 0 success
+ * -EBUSY if device is busy
+ * -ETIMEDOUT if i2c cannot be disabled within the given time
+ *
+ * I2C bus state should be checked prior to disabling the hardware. If bus is
+ * not in idle state, an errno is returned. Write "0" to IC_ENABLE to disable
+ * I2C controller.
+ */
+static int intel_mid_i2c_disable(struct i2c_adapter *adap)
+{
+ struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
+ int err = 0;
+ int count = 0;
+ int ret1, ret2;
+ static const u16 delay[NUM_SPEEDS] = {100, 25, 3};
+
+ /* Set IC_ENABLE to 0 */
+ writel(0, i2c->base + IC_ENABLE);
+
+ /* Check if device is busy */
+ dev_dbg(&adap->dev, "mrst i2c disable\n");
+ while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1)
+ || (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) {
+ udelay(delay[i2c->speed]);
+ writel(0, i2c->base + IC_ENABLE);
+ dev_dbg(&adap->dev, "i2c is busy, count is %d speed %d\n",
+ count, i2c->speed);
+ if (count++ > 10) {
+ err = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ /* Clear all interrupts */
+ readl(i2c->base + IC_CLR_INTR);
+ readl(i2c->base + IC_CLR_STOP_DET);
+ readl(i2c->base + IC_CLR_START_DET);
+ readl(i2c->base + IC_CLR_ACTIVITY);
+ readl(i2c->base + IC_CLR_TX_ABRT);
+ readl(i2c->base + IC_CLR_RX_OVER);
+ readl(i2c->base + IC_CLR_RX_UNDER);
+ readl(i2c->base + IC_CLR_TX_OVER);
+ readl(i2c->base + IC_CLR_RX_DONE);
+ readl(i2c->base + IC_CLR_GEN_CALL);
+
+ /* Disable all interupts */
+ writel(0x0000, i2c->base + IC_INTR_MASK);
+
+ return err;
+}
+
+/**
+ * intel_mid_i2c_hwinit - Initialize the I2C hardware registers
+ * @dev: pci device struct pointer
+ *
+ * This function will be called in intel_mid_i2c_probe() before device
+ * registration.
+ *
+ * Return Values:
+ * 0 success
+ * -EBUSY i2c cannot be disabled
+ * -ETIMEDOUT i2c cannot be disabled
+ * -EFAULT If APB data width is not 32-bit wide
+ *
+ * I2C should be disabled prior to other register operation. If failed, an
+ * errno is returned. Mask and Clear all interrpts, this should be done at
+ * first. Set common registers which will not be modified during normal
+ * transfers, including: controll register, FIFO threshold and clock freq.
+ * Check APB data width at last.
+ */
+static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c)
+{
+ int err;
+
+ static const u16 hcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
+ { 0x75, 0x15, 0x07 },
+ { 0x04c, 0x10, 0x06 }
+ };
+ static const u16 lcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
+ { 0x7C, 0x21, 0x0E },
+ { 0x053, 0x19, 0x0F }
+ };
+
+ /* Disable i2c first */
+ err = intel_mid_i2c_disable(&i2c->adap);
+ if (err)
+ return err;
+
+ /*
+ * Setup clock frequency and speed mode
+ * Enable restart condition,
+ * enable master FSM, disable slave FSM,
+ * use target address when initiating transfer
+ */
+
+ writel((i2c->speed + 1) << 1 | SLV_DIS | RESTART | MASTER_EN,
+ i2c->base + IC_CON);
+ writel(hcnt[i2c->platform][i2c->speed],
+ i2c->base + (IC_SS_SCL_HCNT + (i2c->speed << 3)));
+ writel(lcnt[i2c->platform][i2c->speed],
+ i2c->base + (IC_SS_SCL_LCNT + (i2c->speed << 3)));
+
+ /* Set tranmit & receive FIFO threshold to zero */
+ writel(0x0, i2c->base + IC_RX_TL);
+ writel(0x0, i2c->base + IC_TX_TL);
+
+ return 0;
+}
+
+/**
+ * intel_mid_i2c_func - Return the supported three I2C operations.
+ * @adapter: i2c_adapter struct pointer
+ */
+static u32 intel_mid_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
+}
+
+/**
+ * intel_mid_i2c_address_neq - To check if the addresses for different i2c messages
+ * are equal.
+ * @p1: first i2c_msg
+ * @p2: second i2c_msg
+ *
+ * Return Values:
+ * 0 if addresses are equal
+ * 1 if not equal
+ *
+ * Within a single transfer, the I2C client may need to send its address more
+ * than once. So a check if the addresses match is needed.
+ */
+static inline bool intel_mid_i2c_address_neq(const struct i2c_msg *p1,
+ const struct i2c_msg *p2)
+{
+ if (p1->addr != p2->addr)
+ return 1;
+ if ((p1->flags ^ p2->flags) & I2C_M_TEN)
+ return 1;
+ return 0;
+}
+
+/**
+ * intel_mid_i2c_abort - To handle transfer abortions and print error messages.
+ * @adap: i2c_adapter struct pointer
+ *
+ * By reading register IC_TX_ABRT_SOURCE, various transfer errors can be
+ * distingushed. At present, no circumstances have been found out that
+ * multiple errors would be occured simutaneously, so we simply use the
+ * register value directly.
+ *
+ * At last the error bits are cleared. (Note clear ABRT_SBYTE_NORSTRT bit need
+ * a few extra steps)
+ */
+static void intel_mid_i2c_abort(struct intel_mid_i2c_private *i2c)
+{
+ /* Read about source register */
+ int abort = i2c->abort;
+ struct i2c_adapter *adap = &i2c->adap;
+
+ /* Single transfer error check:
+ * According to databook, TX/RX FIFOs would be flushed when
+ * the abort interrupt occured.
+ */
+ if (abort & ABRT_MASTER_DIS)
+ dev_err(&adap->dev,
+ "initiate master operation with master mode disabled.\n");
+ if (abort & ABRT_10B_RD_NORSTRT)
+ dev_err(&adap->dev,
+ "RESTART disabled and master sent READ cmd in 10-bit addressing.\n");
+
+ if (abort & ABRT_SBYTE_NORSTRT) {
+ dev_err(&adap->dev,
+ "RESTART disabled and user is trying to send START byte.\n");
+ writel(~ABRT_SBYTE_NORSTRT, i2c->base + IC_TX_ABRT_SOURCE);
+ writel(RESTART, i2c->base + IC_CON);
+ writel(~IC_TAR_SPECIAL, i2c->base + IC_TAR);
+ }
+
+ if (abort & ABRT_SBYTE_ACKDET)
+ dev_err(&adap->dev,
+ "START byte was not acknowledged.\n");
+ if (abort & ABRT_TXDATA_NOACK)
+ dev_dbg(&adap->dev,
+ "No acknowledgement received from slave.\n");
+ if (abort & ABRT_10ADDR2_NOACK)
+ dev_dbg(&adap->dev,
+ "The 2nd address byte of the 10-bit address was not acknowledged.\n");
+ if (abort & ABRT_10ADDR1_NOACK)
+ dev_dbg(&adap->dev,
+ "The 1st address byte of 10-bit address was not acknowledged.\n");
+ if (abort & ABRT_7B_ADDR_NOACK)
+ dev_dbg(&adap->dev,
+ "I2C slave device not acknowledged.\n");
+
+ /* Clear TX_ABRT bit */
+ readl(i2c->base + IC_CLR_TX_ABRT);
+ i2c->status = STATUS_XFER_ABORT;
+}
+
+/**
+ * xfer_read - Internal function to implement master read transfer.
+ * @adap: i2c_adapter struct pointer
+ * @buf: buffer in i2c_msg
+ * @length: number of bytes to be read
+ *
+ * Return Values:
+ * 0 if the read transfer succeeds
+ * -ETIMEDOUT if cannot read the "raw" interrupt register
+ * -EINVAL if a transfer abort occurred
+ *
+ * For every byte, a "READ" command will be loaded into IC_DATA_CMD prior to
+ * data transfer. The actual "read" operation will be performed if an RX_FULL
+ * interrupt occurred.
+ *
+ * Note there may be two interrupt signals captured, one should read
+ * IC_RAW_INTR_STAT to separate between errors and actual data.
+ */
+static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
+{
+ struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
+ int i = length;
+ int err;
+
+ if (length >= 256) {
+ dev_err(&adap->dev,
+ "I2C FIFO cannot support larger than 256 bytes\n");
+ return -EMSGSIZE;
+ }
+
+ INIT_COMPLETION(i2c->complete);
+
+ readl(i2c->base + IC_CLR_INTR);
+ writel(0x0044, i2c->base + IC_INTR_MASK);
+
+ i2c->status = STATUS_READ_START;
+
+ while (i--)
+ writel(IC_RD, i2c->base + IC_DATA_CMD);
+
+ i2c->status = STATUS_READ_START;
+ err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
+ if (!err) {
+ dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
+ intel_mid_i2c_hwinit(i2c);
+ return -ETIMEDOUT;
+ }
+ if (i2c->status == STATUS_READ_SUCCESS)
+ return 0;
+ else
+ return -EIO;
+}
+
+/**
+ * xfer_write - Internal function to implement master write transfer.
+ * @adap: i2c_adapter struct pointer
+ * @buf: buffer in i2c_msg
+ * @length: number of bytes to be read
+ *
+ * Return Values:
+ * 0 if the read transfer succeeds
+ * -ETIMEDOUT if we cannot read the "raw" interrupt register
+ * -EINVAL if a transfer abort occured
+ *
+ * For every byte, a "WRITE" command will be loaded into IC_DATA_CMD prior to
+ * data transfer. The actual "write" operation will be performed when the
+ * RX_FULL interrupt signal occurs.
+ *
+ * Note there may be two interrupt signals captured, one should read
+ * IC_RAW_INTR_STAT to separate between errors and actual data.
+ */
+static int xfer_write(struct i2c_adapter *adap,
+ unsigned char *buf, int length)
+{
+ struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
+ int i, err;
+
+ if (length >= 256) {
+ dev_err(&adap->dev,
+ "I2C FIFO cannot support larger than 256 bytes\n");
+ return -EMSGSIZE;
+ }
+
+ INIT_COMPLETION(i2c->complete);
+
+ readl(i2c->base + IC_CLR_INTR);
+ writel(0x0050, i2c->base + IC_INTR_MASK);
+
+ i2c->status = STATUS_WRITE_START;
+ for (i = 0; i < length; i++)
+ writel((u16)(*(buf + i)), i2c->base + IC_DATA_CMD);
+
+ i2c->status = STATUS_WRITE_START;
+ err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
+ if (!err) {
+ dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
+ intel_mid_i2c_hwinit(i2c);
+ return -ETIMEDOUT;
+ } else {
+ if (i2c->status == STATUS_WRITE_SUCCESS)
+ return 0;
+ else
+ return -EIO;
+ }
+}
+
+static int intel_mid_i2c_setup(struct i2c_adapter *adap, struct i2c_msg *pmsg)
+{
+ struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
+ int err;
+ u32 reg;
+ u32 bit_mask;
+ u32 mode;
+
+ /* Disable device first */
+ err = intel_mid_i2c_disable(adap);
+ if (err) {
+ dev_err(&adap->dev,
+ "Cannot disable i2c controller, timeout\n");
+ return err;
+ }
+
+ mode = (1 + i2c->speed) << 1;
+ /* set the speed mode */
+ reg = readl(i2c->base + IC_CON);
+ if ((reg & 0x06) != mode) {
+ dev_dbg(&adap->dev, "set mode %d\n", i2c->speed);
+ writel((reg & ~0x6) | mode, i2c->base + IC_CON);
+ }
+
+ reg = readl(i2c->base + IC_CON);
+ /* use 7-bit addressing */
+ if (pmsg->flags & I2C_M_TEN) {
+ if ((reg & ADDR_10BIT) != ADDR_10BIT) {
+ dev_dbg(&adap->dev, "set i2c 10 bit address mode\n");
+ writel(reg | ADDR_10BIT, i2c->base + IC_CON);
+ }
+ } else {
+ if ((reg & ADDR_10BIT) != 0x0) {
+ dev_dbg(&adap->dev, "set i2c 7 bit address mode\n");
+ writel(reg & ~ADDR_10BIT, i2c->base + IC_CON);
+ }
+ }
+ /* enable restart conditions */
+ reg = readl(i2c->base + IC_CON);
+ if ((reg & RESTART) != RESTART) {
+ dev_dbg(&adap->dev, "enable restart conditions\n");
+ writel(reg | RESTART, i2c->base + IC_CON);
+ }
+
+ /* enable master FSM */
+ reg = readl(i2c->base + IC_CON);
+ dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
+ writel(reg | MASTER_EN, i2c->base + IC_CON);
+ if ((reg & SLV_DIS) != SLV_DIS) {
+ dev_dbg(&adap->dev, "enable master FSM\n");
+ writel(reg | SLV_DIS, i2c->base + IC_CON);
+ dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
+ }
+
+ /* use target address when initiating transfer */
+ reg = readl(i2c->base + IC_TAR);
+ bit_mask = IC_TAR_SPECIAL | IC_TAR_GC_OR_START;
+
+ if ((reg & bit_mask) != 0x0) {
+ dev_dbg(&adap->dev,
+ "WR: use target address when intiating transfer, i2c_tx_target\n");
+ writel(reg & ~bit_mask, i2c->base + IC_TAR);
+ }
+
+ /* set target address to the I2C slave address */
+ dev_dbg(&adap->dev,
+ "set target address to the I2C slave address, addr is %x\n",
+ pmsg->addr);
+ writel(pmsg->addr | (pmsg->flags & I2C_M_TEN ? IC_TAR_10BIT_ADDR : 0),
+ i2c->base + IC_TAR);
+
+ /* Enable I2C controller */
+ writel(ENABLE, i2c->base + IC_ENABLE);
+
+ return 0;
+}
+
+/**
+ * intel_mid_i2c_xfer - Main master transfer routine.
+ * @adap: i2c_adapter struct pointer
+ * @pmsg: i2c_msg struct pointer
+ * @num: number of i2c_msg
+ *
+ * Return Values:
+ * + number of messages transfered
+ * -ETIMEDOUT If cannot disable I2C controller or read IC_STATUS
+ * -EINVAL If the address in i2c_msg is invalid
+ *
+ * This function will be registered in i2c-core and exposed to external
+ * I2C clients.
+ * 1. Disable I2C controller
+ * 2. Unmask three interrupts: RX_FULL, TX_EMPTY, TX_ABRT
+ * 3. Check if address in i2c_msg is valid
+ * 4. Enable I2C controller
+ * 5. Perform real transfer (call xfer_read or xfer_write)
+ * 6. Wait until the current transfer is finished (check bus state)
+ * 7. Mask and clear all interrupts
+ */
+static int intel_mid_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *pmsg,
+ int num)
+{
+ struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
+ int i, err = 0;
+
+ /* if number of messages equal 0*/
+ if (num == 0)
+ return 0;
+
+ pm_runtime_get(i2c->dev);
+
+ mutex_lock(&i2c->lock);
+ dev_dbg(&adap->dev, "intel_mid_i2c_xfer, process %d msg(s)\n", num);
+ dev_dbg(&adap->dev, "slave address is %x\n", pmsg->addr);
+
+
+ if (i2c->status != STATUS_IDLE) {
+ dev_err(&adap->dev, "Adapter %d in transfer/standby\n",
+ adap->nr);
+ mutex_unlock(&i2c->lock);
+ pm_runtime_put(i2c->dev);
+ return -1;
+ }
+
+
+ for (i = 1; i < num; i++) {
+ /* Message address equal? */
+ if (unlikely(intel_mid_i2c_address_neq(&pmsg[0], &pmsg[i]))) {
+ dev_err(&adap->dev, "Invalid address in msg[%d]\n", i);
+ mutex_unlock(&i2c->lock);
+ pm_runtime_put(i2c->dev);
+ return -EINVAL;
+ }
+ }
+
+ if (intel_mid_i2c_setup(adap, pmsg)) {
+ mutex_unlock(&i2c->lock);
+ pm_runtime_put(i2c->dev);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num; i++) {
+ i2c->msg = pmsg;
+ i2c->status = STATUS_IDLE;
+ /* Read or Write */
+ if (pmsg->flags & I2C_M_RD) {
+ dev_dbg(&adap->dev, "I2C_M_RD\n");
+ err = xfer_read(adap, pmsg->buf, pmsg->len);
+ } else {
+ dev_dbg(&adap->dev, "I2C_M_WR\n");
+ err = xfer_write(adap, pmsg->buf, pmsg->len);
+ }
+ if (err < 0)
+ break;
+ dev_dbg(&adap->dev, "msg[%d] transfer complete\n", i);
+ pmsg++; /* next message */
+ }
+
+ /* Mask interrupts */
+ writel(0x0000, i2c->base + IC_INTR_MASK);
+ /* Clear all interrupts */
+ readl(i2c->base + IC_CLR_INTR);
+
+ i2c->status = STATUS_IDLE;
+ mutex_unlock(&i2c->lock);
+ pm_runtime_put(i2c->dev);
+
+ return err;
+}
+
+static int intel_mid_i2c_runtime_suspend(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
+ struct i2c_adapter *adap = to_i2c_adapter(dev);
+ int err;
+
+ if (i2c->status != STATUS_IDLE)
+ return -1;
+
+ intel_mid_i2c_disable(adap);
+
+ err = pci_save_state(pdev);
+ if (err) {
+ dev_err(dev, "pci_save_state failed\n");
+ return err;
+ }
+
+ err = pci_set_power_state(pdev, PCI_D3hot);
+ if (err) {
+ dev_err(dev, "pci_set_power_state failed\n");
+ return err;
+ }
+ i2c->status = STATUS_STANDBY;
+
+ return 0;
+}
+
+static int intel_mid_i2c_runtime_resume(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
+ int err;
+
+ if (i2c->status != STATUS_STANDBY)
+ return 0;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(dev, "pci_enable_device failed\n");
+ return err;
+ }
+
+ i2c->status = STATUS_IDLE;
+
+ intel_mid_i2c_hwinit(i2c);
+ return err;
+}
+
+static void i2c_isr_read(struct intel_mid_i2c_private *i2c)
+{
+ struct i2c_msg *msg = i2c->msg;
+ int rx_num;
+ u32 len;
+ u8 *buf;
+
+ if (!(msg->flags & I2C_M_RD))
+ return;
+
+ if (i2c->status != STATUS_READ_IN_PROGRESS) {
+ len = msg->len;
+ buf = msg->buf;
+ } else {
+ len = i2c->rx_buf_len;
+ buf = i2c->rx_buf;
+ }
+
+ rx_num = readl(i2c->base + IC_RXFLR);
+
+ for (; len > 0 && rx_num > 0; len--, rx_num--)
+ *buf++ = readl(i2c->base + IC_DATA_CMD);
+
+ if (len > 0) {
+ i2c->status = STATUS_READ_IN_PROGRESS;
+ i2c->rx_buf_len = len;
+ i2c->rx_buf = buf;
+ } else
+ i2c->status = STATUS_READ_SUCCESS;
+
+ return;
+}
+
+static irqreturn_t intel_mid_i2c_isr(int this_irq, void *dev)
+{
+ struct intel_mid_i2c_private *i2c = dev;
+ u32 stat = readl(i2c->base + IC_INTR_STAT);
+
+ if (!stat)
+ return IRQ_NONE;
+
+ dev_dbg(&i2c->adap.dev, "%s, stat = 0x%x\n", __func__, stat);
+ stat &= 0x54;
+
+ if (i2c->status != STATUS_WRITE_START &&
+ i2c->status != STATUS_READ_START &&
+ i2c->status != STATUS_READ_IN_PROGRESS)
+ goto err;
+
+ if (stat & TX_ABRT)
+ i2c->abort = readl(i2c->base + IC_TX_ABRT_SOURCE);
+
+ readl(i2c->base + IC_CLR_INTR);
+
+ if (stat & TX_ABRT) {
+ intel_mid_i2c_abort(i2c);
+ goto exit;
+ }
+
+ if (stat & RX_FULL) {
+ i2c_isr_read(i2c);
+ goto exit;
+ }
+
+ if (stat & TX_EMPTY) {
+ if (readl(i2c->base + IC_STATUS) & 0x4)
+ i2c->status = STATUS_WRITE_SUCCESS;
+ }
+
+exit:
+ if (i2c->status == STATUS_READ_SUCCESS ||
+ i2c->status == STATUS_WRITE_SUCCESS ||
+ i2c->status == STATUS_XFER_ABORT) {
+ /* Clear all interrupts */
+ readl(i2c->base + IC_CLR_INTR);
+ /* Mask interrupts */
+ writel(0, i2c->base + IC_INTR_MASK);
+ complete(&i2c->complete);
+ }
+err:
+ return IRQ_HANDLED;
+}
+
+static struct i2c_algorithm intel_mid_i2c_algorithm = {
+ .master_xfer = intel_mid_i2c_xfer,
+ .functionality = intel_mid_i2c_func,
+};
+
+
+static const struct dev_pm_ops intel_mid_i2c_pm_ops = {
+ .runtime_suspend = intel_mid_i2c_runtime_suspend,
+ .runtime_resume = intel_mid_i2c_runtime_resume,
+};
+
+/**
+ * intel_mid_i2c_probe - I2C controller initialization routine
+ * @dev: pci device
+ * @id: device id
+ *
+ * Return Values:
+ * 0 success
+ * -ENODEV If cannot allocate pci resource
+ * -ENOMEM If the register base remapping failed, or
+ * if kzalloc failed
+ *
+ * Initialization steps:
+ * 1. Request for PCI resource
+ * 2. Remap the start address of PCI resource to register base
+ * 3. Request for device memory region
+ * 4. Fill in the struct members of intel_mid_i2c_private
+ * 5. Call intel_mid_i2c_hwinit() for hardware initialization
+ * 6. Register I2C adapter in i2c-core
+ */
+static int __devinit intel_mid_i2c_probe(struct pci_dev *dev,
+ const struct pci_device_id *id)
+{
+ struct intel_mid_i2c_private *mrst;
+ unsigned long start, len;
+ int err, busnum;
+ void __iomem *base = NULL;
+
+ dev_dbg(&dev->dev, "Get into probe function for I2C\n");
+ err = pci_enable_device(dev);
+ if (err) {
+ dev_err(&dev->dev, "Failed to enable I2C PCI device (%d)\n",
+ err);
+ goto exit;
+ }
+
+ /* Determine the address of the I2C area */
+ start = pci_resource_start(dev, 0);
+ len = pci_resource_len(dev, 0);
+ if (!start || len == 0) {
+ dev_err(&dev->dev, "base address not set\n");
+ err = -ENODEV;
+ goto exit;
+ }
+ dev_dbg(&dev->dev, "%s i2c resource start 0x%lx, len=%ld\n",
+ PLATFORM, start, len);
+
+ err = pci_request_region(dev, 0, DRIVER_NAME);
+ if (err) {
+ dev_err(&dev->dev, "failed to request I2C region "
+ "0x%lx-0x%lx\n", start,
+ (unsigned long)pci_resource_end(dev, 0));
+ goto exit;
+ }
+
+ base = ioremap_nocache(start, len);
+ if (!base) {
+ dev_err(&dev->dev, "I/O memory remapping failed\n");
+ err = -ENOMEM;
+ goto fail0;
+ }
+
+ /* Allocate the per-device data structure, intel_mid_i2c_private */
+ mrst = kzalloc(sizeof(struct intel_mid_i2c_private), GFP_KERNEL);
+ if (mrst == NULL) {
+ dev_err(&dev->dev, "can't allocate interface\n");
+ err = -ENOMEM;
+ goto fail1;
+ }
+
+ /* Initialize struct members */
+ snprintf(mrst->adap.name, sizeof(mrst->adap.name),
+ "MRST/Medfield I2C at %lx", start);
+ mrst->adap.owner = THIS_MODULE;
+ mrst->adap.algo = &intel_mid_i2c_algorithm;
+ mrst->adap.dev.parent = &dev->dev;
+ mrst->dev = &dev->dev;
+ mrst->base = base;
+ mrst->speed = STANDARD;
+ mrst->abort = 0;
+ mrst->rx_buf_len = 0;
+ mrst->status = STATUS_IDLE;
+
+ pci_set_drvdata(dev, mrst);
+ i2c_set_adapdata(&mrst->adap, mrst);
+
+ mrst->adap.nr = busnum = id->driver_data;
+ if (dev->device <= 0x0804)
+ mrst->platform = MOORESTOWN;
+ else
+ mrst->platform = MEDFIELD;
+
+ dev_dbg(&dev->dev, "I2C%d\n", busnum);
+
+ if (ctl_num > busnum) {
+ if (speed_mode[busnum] < 0 || speed_mode[busnum] >= NUM_SPEEDS)
+ dev_warn(&dev->dev, "invalid speed %d ignored.\n",
+ speed_mode[busnum]);
+ else
+ mrst->speed = speed_mode[busnum];
+ }
+
+ /* Initialize i2c controller */
+ err = intel_mid_i2c_hwinit(mrst);
+ if (err < 0) {
+ dev_err(&dev->dev, "I2C interface initialization failed\n");
+ goto fail2;
+ }
+
+ mutex_init(&mrst->lock);
+ init_completion(&mrst->complete);
+
+ /* Clear all interrupts */
+ readl(mrst->base + IC_CLR_INTR);
+ writel(0x0000, mrst->base + IC_INTR_MASK);
+
+ err = request_irq(dev->irq, intel_mid_i2c_isr, IRQF_SHARED,
+ mrst->adap.name, mrst);
+ if (err) {
+ dev_err(&dev->dev, "Failed to request IRQ for I2C controller: "
+ "%s", mrst->adap.name);
+ goto fail2;
+ }
+
+ /* Adapter registration */
+ err = i2c_add_numbered_adapter(&mrst->adap);
+ if (err) {
+ dev_err(&dev->dev, "Adapter %s registration failed\n",
+ mrst->adap.name);
+ goto fail3;
+ }
+
+ dev_dbg(&dev->dev, "%s I2C bus %d driver bind success.\n",
+ (mrst->platform == MOORESTOWN) ? "Moorestown" : "Medfield",
+ busnum);
+
+ pm_runtime_enable(&dev->dev);
+ return 0;
+
+fail3:
+ free_irq(dev->irq, mrst);
+fail2:
+ pci_set_drvdata(dev, NULL);
+ kfree(mrst);
+fail1:
+ iounmap(base);
+fail0:
+ pci_release_region(dev, 0);
+exit:
+ return err;
+}
+
+static void __devexit intel_mid_i2c_remove(struct pci_dev *dev)
+{
+ struct intel_mid_i2c_private *mrst = pci_get_drvdata(dev);
+ intel_mid_i2c_disable(&mrst->adap);
+ if (i2c_del_adapter(&mrst->adap))
+ dev_err(&dev->dev, "Failed to delete i2c adapter");
+
+ free_irq(dev->irq, mrst);
+ pci_set_drvdata(dev, NULL);
+ iounmap(mrst->base);
+ kfree(mrst);
+ pci_release_region(dev, 0);
+}
+
+static struct pci_device_id intel_mid_i2c_ids[] = {
+ /* Moorestown */
+ { PCI_VDEVICE(INTEL, 0x0802), 0 },
+ { PCI_VDEVICE(INTEL, 0x0803), 1 },
+ { PCI_VDEVICE(INTEL, 0x0804), 2 },
+ /* Medfield */
+ { PCI_VDEVICE(INTEL, 0x0817), 3,},
+ { PCI_VDEVICE(INTEL, 0x0818), 4 },
+ { PCI_VDEVICE(INTEL, 0x0819), 5 },
+ { PCI_VDEVICE(INTEL, 0x082C), 0 },
+ { PCI_VDEVICE(INTEL, 0x082D), 1 },
+ { PCI_VDEVICE(INTEL, 0x082E), 2 },
+ { 0,}
+};
+MODULE_DEVICE_TABLE(pci, intel_mid_i2c_ids);
+
+static struct pci_driver intel_mid_i2c_driver = {
+ .name = DRIVER_NAME,
+ .id_table = intel_mid_i2c_ids,
+ .probe = intel_mid_i2c_probe,
+ .remove = __devexit_p(intel_mid_i2c_remove),
+};
+
+static int __init intel_mid_i2c_init(void)
+{
+ return pci_register_driver(&intel_mid_i2c_driver);
+}
+
+static void __exit intel_mid_i2c_exit(void)
+{
+ pci_unregister_driver(&intel_mid_i2c_driver);
+}
+
+module_init(intel_mid_i2c_init);
+module_exit(intel_mid_i2c_exit);
+
+MODULE_AUTHOR("Ba Zheng <zheng.ba@intel.com>");
+MODULE_DESCRIPTION("I2C driver for Moorestown Platform");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(VERSION);
/*
- * Copyright (C) 2009 ST-Ericsson
+ * Copyright (C) 2009 ST-Ericsson SA
* Copyright (C) 2009 STMicroelectronics
*
* I2C master mode controller driver, used in Nomadik 8815
/* maximum threshold value */
#define MAX_I2C_FIFO_THRESHOLD 15
+/* per-transfer delay, required for the hardware to stabilize */
+#define I2C_DELAY 150
+
enum i2c_status {
I2C_NOP,
I2C_ON_GOING,
};
/* controller response timeout in ms */
-#define I2C_TIMEOUT_MS 500
+#define I2C_TIMEOUT_MS 2000
/**
* struct i2c_nmk_client - client specific data
{
int stat;
+ clk_enable(dev->clk);
+
stat = flush_i2c_fifo(dev);
if (stat)
return stat;
dev->cli.operation = I2C_NO_OPERATION;
+ clk_disable(dev->clk);
+
+ udelay(I2C_DELAY);
return 0;
}
(void) init_hw(dev);
status = -ETIMEDOUT;
}
-
return status;
}
/**
* nmk_i2c_xfer() - I2C transfer function used by kernel framework
- * @i2c_adap - Adapter pointer to the controller
- * @msgs[] - Pointer to data to be written.
- * @num_msgs - Number of messages to be executed
+ * @i2c_adap: Adapter pointer to the controller
+ * @msgs: Pointer to data to be written.
+ * @num_msgs: Number of messages to be executed
*
* This is the function called by the generic kernel i2c_transfer()
* or i2c_smbus...() API calls. Note that this code is protected by the
if (status)
return status;
+ clk_enable(dev->clk);
+
/* setup the i2c controller */
setup_i2c_controller(dev);
dev_err(&dev->pdev->dev, "%s\n",
cause >= ARRAY_SIZE(abort_causes)
? "unknown reason" : abort_causes[cause]);
+ clk_disable(dev->clk);
return status;
}
- mdelay(1);
+ udelay(I2C_DELAY);
}
+ clk_disable(dev->clk);
+
/* return the no. messages processed */
if (status)
return status;
/**
* disable_interrupts() - disable the interrupts
* @dev: private data of controller
+ * @irq: interrupt number
*/
static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
{
static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
{
- return I2C_FUNC_I2C
- | I2C_FUNC_SMBUS_BYTE_DATA
- | I2C_FUNC_SMBUS_WORD_DATA
- | I2C_FUNC_SMBUS_I2C_BLOCK;
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm nmk_i2c_algo = {
goto err_no_clk;
}
- clk_enable(dev->clk);
-
adap = &dev->adap;
adap->dev.parent = &pdev->dev;
adap->owner = THIS_MODULE;
return 0;
err_init_hw:
- clk_disable(dev->clk);
err_add_adap:
clk_put(dev->clk);
err_no_clk:
iounmap(dev->virtbase);
if (res)
release_mem_region(res->start, resource_size(res));
- clk_disable(dev->clk);
clk_put(dev->clk);
platform_set_drvdata(pdev, NULL);
kfree(dev);
int retry;
int ret;
+ clk_enable(i2c->clk);
+
for (retry = 0; retry < adap->retries; retry++) {
ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
- if (ret != -EAGAIN)
+ if (ret != -EAGAIN) {
+ clk_disable(i2c->clk);
return ret;
+ }
dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
udelay(100);
}
+ clk_disable(i2c->clk);
return -EREMOTEIO;
}
platform_set_drvdata(pdev, i2c);
dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
+ clk_disable(i2c->clk);
return 0;
err_cpufreq:
struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
i2c->suspended = 0;
+ clk_enable(i2c->clk);
s3c24xx_i2c_init(i2c);
+ clk_disable(i2c->clk);
return 0;
}
static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
{
- hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x23 : 0x21);
+ hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
}
/**
u16 mcr;
pci_read_config_word(dev, mcr_addr, &mcr);
- pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
- /* now read cable id register */
+ pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
+ /* Debounce, then read cable ID register */
+ udelay(10);
pci_read_config_byte(dev, 0x5a, &scr1);
pci_write_config_word(dev, mcr_addr, mcr);
} else if (chip_type >= HPT370) {
u8 scr2 = 0;
pci_read_config_byte(dev, 0x5b, &scr2);
- pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
- /* now read cable id register */
+ pci_write_config_byte(dev, 0x5b, scr2 & ~1);
+ /* Debounce, then read cable ID register */
+ udelay(10);
pci_read_config_byte(dev, 0x5a, &scr1);
- pci_write_config_byte(dev, 0x5b, scr2);
+ pci_write_config_byte(dev, 0x5b, scr2);
} else
pci_read_config_byte(dev, 0x5a, &scr1);
ide_hwif_t *hwif = drive->hwif;
const struct ide_dma_ops *dma_ops = hwif->dma_ops;
struct ide_cmd *cmd = &hwif->cmd;
- struct request *rq;
ide_startstop_t ret = ide_stopped;
/*
ide_dma_off_quietly(drive);
/*
- * un-busy drive etc and make sure request is sane
+ * make sure request is sane
*/
- rq = hwif->rq;
- if (rq) {
- hwif->rq = NULL;
- rq->errors = 0;
- ide_requeue_and_plug(drive, rq);
- }
+ if (hwif->rq)
+ hwif->rq->errors = 0;
return ret;
}
return ret;
}
-static int ipathfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ipathfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- int ret = get_sb_single(fs_type, flags, data,
- ipathfs_fill_super, mnt);
- if (ret >= 0)
- ipath_super = mnt->mnt_sb;
+ struct dentry *ret;
+ ret = mount_single(fs_type, flags, data, ipathfs_fill_super);
+ if (!IS_ERR(ret))
+ ipath_super = ret->d_sb;
return ret;
}
static struct file_system_type ipathfs_fs_type = {
.owner = THIS_MODULE,
.name = "ipathfs",
- .get_sb = ipathfs_get_sb,
+ .mount = ipathfs_mount,
.kill_sb = ipathfs_kill_super,
};
return ret;
}
-static int qibfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *qibfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
- int ret = get_sb_single(fs_type, flags, data,
- qibfs_fill_super, mnt);
- if (ret >= 0)
- qib_super = mnt->mnt_sb;
+ struct dentry *ret;
+ ret = mount_single(fs_type, flags, data, qibfs_fill_super);
+ if (!IS_ERR(ret))
+ qib_super = ret->d_sb;
return ret;
}
static struct file_system_type qibfs_fs_type = {
.owner = THIS_MODULE,
.name = "ipathfs",
- .get_sb = qibfs_get_sb,
+ .mount = qibfs_mount,
.kill_sb = qibfs_kill_super,
};
return -ENOMEM;
}
-static int capifs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *capifs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, capifs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, capifs_fill_super);
}
static struct file_system_type capifs_fs_type = {
.owner = THIS_MODULE,
.name = "capifs",
- .get_sb = capifs_get_sb,
+ .mount = capifs_mount,
.kill_sb = kill_anon_super,
};
if (dev) {
struct mISDN_devinfo di;
+ memset(&di, 0, sizeof(di));
di.id = dev->id;
di.Dprotocols = dev->Dprotocols;
di.Bprotocols = dev->Bprotocols | get_all_Bprotocols();
if (dev) {
struct mISDN_devinfo di;
+ memset(&di, 0, sizeof(di));
di.id = dev->id;
di.Dprotocols = dev->Dprotocols;
di.Bprotocols = dev->Bprotocols | get_all_Bprotocols();
target = rdev->sb_start + offset + index * (PAGE_SIZE/512);
- if (sync_page_io(rdev->bdev, target,
+ if (sync_page_io(rdev, target,
roundup(size, bdev_logical_block_size(rdev->bdev)),
page, READ)) {
page->index = index;
atomic_inc(&bitmap->pending_writes);
set_buffer_locked(bh);
set_buffer_mapped(bh);
- submit_bh(WRITE, bh);
+ submit_bh(WRITE | REQ_UNPLUG | REQ_SYNC, bh);
bh = bh->b_this_page;
}
bitmap_checkfree(bitmap, page);
}
static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
- sector_t offset, int *blocks,
+ sector_t offset, sector_t *blocks,
int create);
/*
unsigned long j;
unsigned long flags;
struct page *page = NULL, *lastpage = NULL;
- int blocks;
+ sector_t blocks;
void *paddr;
struct dm_dirty_log *log = mddev->bitmap_info.log;
}
static bitmap_counter_t *bitmap_get_counter(struct bitmap *bitmap,
- sector_t offset, int *blocks,
+ sector_t offset, sector_t *blocks,
int create)
__releases(bitmap->lock)
__acquires(bitmap->lock)
}
while (sectors) {
- int blocks;
+ sector_t blocks;
bitmap_counter_t *bmc;
spin_lock_irq(&bitmap->lock);
success = 0;
while (sectors) {
- int blocks;
+ sector_t blocks;
unsigned long flags;
bitmap_counter_t *bmc;
}
EXPORT_SYMBOL(bitmap_endwrite);
-static int __bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
+static int __bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks,
int degraded)
{
bitmap_counter_t *bmc;
return rv;
}
-int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks,
+int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks,
int degraded)
{
/* bitmap_start_sync must always report on multiples of whole
* Return the 'or' of the result.
*/
int rv = 0;
- int blocks1;
+ sector_t blocks1;
*blocks = 0;
while (*blocks < (PAGE_SIZE>>9)) {
}
EXPORT_SYMBOL(bitmap_start_sync);
-void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted)
+void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int aborted)
{
bitmap_counter_t *bmc;
unsigned long flags;
* RESYNC bit wherever it is still on
*/
sector_t sector = 0;
- int blocks;
+ sector_t blocks;
if (!bitmap)
return;
while (sector < bitmap->mddev->resync_max_sectors) {
void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector)
{
sector_t s = 0;
- int blocks;
+ sector_t blocks;
if (!bitmap)
return;
* be 0 at this point
*/
- int secs;
+ sector_t secs;
bitmap_counter_t *bmc;
spin_lock_irq(&bitmap->lock);
bmc = bitmap_get_counter(bitmap, offset, &secs, 1);
* All chunks should be clean, but some might need_sync.
*/
while (sector < mddev->resync_max_sectors) {
- int blocks;
+ sector_t blocks;
bitmap_start_sync(bitmap, sector, &blocks, 0);
sector += blocks;
}
unsigned long sectors, int behind);
void bitmap_endwrite(struct bitmap *bitmap, sector_t offset,
unsigned long sectors, int success, int behind);
-int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int degraded);
-void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, int *blocks, int aborted);
+int bitmap_start_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int degraded);
+void bitmap_end_sync(struct bitmap *bitmap, sector_t offset, sector_t *blocks, int aborted);
void bitmap_close_sync(struct bitmap *bitmap);
void bitmap_cond_end_sync(struct bitmap *bitmap, sector_t sector);
}
}
if (failit) {
- struct bio *b = bio_clone(bio, GFP_NOIO);
+ struct bio *b = bio_clone_mddev(bio, GFP_NOIO, mddev);
b->bi_bdev = conf->rdev->bdev;
b->bi_private = bio;
b->bi_end_io = faulty_fail;
#define DEBUG 0
#define dprintk(x...) ((void)(DEBUG && printk(x)))
-static DEFINE_MUTEX(md_mutex);
-
#ifndef MODULE
static void autostart_arrays(int part);
#endif
static void md_print_devices(void);
static DECLARE_WAIT_QUEUE_HEAD(resync_wait);
+static struct workqueue_struct *md_wq;
+static struct workqueue_struct *md_misc_wq;
#define MD_BUG(x...) { printk("md: bug in file %s, line %d\n", __FILE__, __LINE__); md_print_devices(); }
static int start_readonly;
+/* bio_clone_mddev
+ * like bio_clone, but with a local bio set
+ */
+
+static void mddev_bio_destructor(struct bio *bio)
+{
+ mddev_t *mddev, **mddevp;
+
+ mddevp = (void*)bio;
+ mddev = mddevp[-1];
+
+ bio_free(bio, mddev->bio_set);
+}
+
+struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,
+ mddev_t *mddev)
+{
+ struct bio *b;
+ mddev_t **mddevp;
+
+ if (!mddev || !mddev->bio_set)
+ return bio_alloc(gfp_mask, nr_iovecs);
+
+ b = bio_alloc_bioset(gfp_mask, nr_iovecs,
+ mddev->bio_set);
+ if (!b)
+ return NULL;
+ mddevp = (void*)b;
+ mddevp[-1] = mddev;
+ b->bi_destructor = mddev_bio_destructor;
+ return b;
+}
+EXPORT_SYMBOL_GPL(bio_alloc_mddev);
+
+struct bio *bio_clone_mddev(struct bio *bio, gfp_t gfp_mask,
+ mddev_t *mddev)
+{
+ struct bio *b;
+ mddev_t **mddevp;
+
+ if (!mddev || !mddev->bio_set)
+ return bio_clone(bio, gfp_mask);
+
+ b = bio_alloc_bioset(gfp_mask, bio->bi_max_vecs,
+ mddev->bio_set);
+ if (!b)
+ return NULL;
+ mddevp = (void*)b;
+ mddevp[-1] = mddev;
+ b->bi_destructor = mddev_bio_destructor;
+ __bio_clone(b, bio);
+ if (bio_integrity(bio)) {
+ int ret;
+
+ ret = bio_integrity_clone(b, bio, gfp_mask, mddev->bio_set);
+
+ if (ret < 0) {
+ bio_put(b);
+ return NULL;
+ }
+ }
+
+ return b;
+}
+EXPORT_SYMBOL_GPL(bio_clone_mddev);
+
/*
* We have a system wide 'event count' that is incremented
* on any 'interesting' event, and readers of /proc/mdstat
if (atomic_dec_and_test(&mddev->flush_pending)) {
/* The pre-request flush has finished */
- schedule_work(&mddev->flush_work);
+ queue_work(md_wq, &mddev->flush_work);
}
bio_put(bio);
}
atomic_inc(&rdev->nr_pending);
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- bi = bio_alloc(GFP_KERNEL, 0);
+ bi = bio_alloc_mddev(GFP_KERNEL, 0, mddev);
bi->bi_end_io = md_end_flush;
bi->bi_private = rdev;
bi->bi_bdev = rdev->bdev;
submit_flushes(mddev);
if (atomic_dec_and_test(&mddev->flush_pending))
- schedule_work(&mddev->flush_work);
+ queue_work(md_wq, &mddev->flush_work);
}
EXPORT_SYMBOL(md_flush_request);
static void mddev_put(mddev_t *mddev)
{
+ struct bio_set *bs = NULL;
+
if (!atomic_dec_and_lock(&mddev->active, &all_mddevs_lock))
return;
if (!mddev->raid_disks && list_empty(&mddev->disks) &&
/* Array is not configured at all, and not held active,
* so destroy it */
list_del(&mddev->all_mddevs);
+ bs = mddev->bio_set;
+ mddev->bio_set = NULL;
if (mddev->gendisk) {
- /* we did a probe so need to clean up.
- * Call schedule_work inside the spinlock
- * so that flush_scheduled_work() after
- * mddev_find will succeed in waiting for the
- * work to be done.
+ /* We did a probe so need to clean up. Call
+ * queue_work inside the spinlock so that
+ * flush_workqueue() after mddev_find will
+ * succeed in waiting for the work to be done.
*/
INIT_WORK(&mddev->del_work, mddev_delayed_delete);
- schedule_work(&mddev->del_work);
+ queue_work(md_misc_wq, &mddev->del_work);
} else
kfree(mddev);
}
spin_unlock(&all_mddevs_lock);
+ if (bs)
+ bioset_free(bs);
}
void mddev_init(mddev_t *mddev)
* if zero is reached.
* If an error occurred, call md_error
*/
- struct bio *bio = bio_alloc(GFP_NOIO, 1);
+ struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, mddev);
bio->bi_bdev = rdev->bdev;
bio->bi_sector = sector;
complete((struct completion*)bio->bi_private);
}
-int sync_page_io(struct block_device *bdev, sector_t sector, int size,
- struct page *page, int rw)
+int sync_page_io(mdk_rdev_t *rdev, sector_t sector, int size,
+ struct page *page, int rw)
{
- struct bio *bio = bio_alloc(GFP_NOIO, 1);
+ struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, rdev->mddev);
struct completion event;
int ret;
rw |= REQ_SYNC | REQ_UNPLUG;
- bio->bi_bdev = bdev;
+ bio->bi_bdev = rdev->bdev;
bio->bi_sector = sector;
bio_add_page(bio, page, size, 0);
init_completion(&event);
return 0;
- if (!sync_page_io(rdev->bdev, rdev->sb_start, size, rdev->sb_page, READ))
+ if (!sync_page_io(rdev, rdev->sb_start, size, rdev->sb_page, READ))
goto fail;
rdev->sb_loaded = 1;
return 0;
synchronize_rcu();
INIT_WORK(&rdev->del_work, md_delayed_delete);
kobject_get(&rdev->kobj);
- schedule_work(&rdev->del_work);
+ queue_work(md_misc_wq, &rdev->del_work);
}
/*
if (!mddev->persistent) {
clear_bit(MD_CHANGE_CLEAN, &mddev->flags);
clear_bit(MD_CHANGE_DEVS, &mddev->flags);
+ if (!mddev->external)
+ clear_bit(MD_CHANGE_PENDING, &mddev->flags);
wake_up(&mddev->sb_wait);
return;
}
shift = partitioned ? MdpMinorShift : 0;
unit = MINOR(mddev->unit) >> shift;
- /* wait for any previous instance if this device
- * to be completed removed (mddev_delayed_delete).
+ /* wait for any previous instance of this device to be
+ * completely removed (mddev_delayed_delete).
*/
- flush_scheduled_work();
+ flush_workqueue(md_misc_wq);
mutex_lock(&disks_mutex);
error = -EEXIST;
sysfs_notify_dirent_safe(rdev->sysfs_state);
}
+ if (mddev->bio_set == NULL)
+ mddev->bio_set = bioset_create(BIO_POOL_SIZE, sizeof(mddev));
+
spin_lock(&pers_lock);
pers = find_pers(mddev->level, mddev->clevel);
if (!pers || !try_module_get(pers->owner)) {
mddev_t *mddev = mddev_find(bdev->bd_dev);
int err;
- mutex_lock(&md_mutex);
if (mddev->gendisk != bdev->bd_disk) {
/* we are racing with mddev_put which is discarding this
* bd_disk.
*/
mddev_put(mddev);
/* Wait until bdev->bd_disk is definitely gone */
- flush_scheduled_work();
+ flush_workqueue(md_misc_wq);
/* Then retry the open from the top */
- mutex_unlock(&md_mutex);
return -ERESTARTSYS;
}
BUG_ON(mddev != bdev->bd_disk->private_data);
check_disk_size_change(mddev->gendisk, bdev);
out:
- mutex_unlock(&md_mutex);
return err;
}
mddev_t *mddev = disk->private_data;
BUG_ON(!mddev);
- mutex_lock(&md_mutex);
atomic_dec(&mddev->openers);
mddev_put(mddev);
- mutex_unlock(&md_mutex);
return 0;
}
set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
md_wakeup_thread(mddev->thread);
if (mddev->event_work.func)
- schedule_work(&mddev->event_work);
+ queue_work(md_misc_wq, &mddev->event_work);
md_new_event_inintr(mddev);
}
static int __init md_init(void)
{
- if (register_blkdev(MD_MAJOR, "md"))
- return -1;
- if ((mdp_major=register_blkdev(0, "mdp"))<=0) {
- unregister_blkdev(MD_MAJOR, "md");
- return -1;
- }
+ int ret = -ENOMEM;
+
+ md_wq = alloc_workqueue("md", WQ_RESCUER, 0);
+ if (!md_wq)
+ goto err_wq;
+
+ md_misc_wq = alloc_workqueue("md_misc", 0, 0);
+ if (!md_misc_wq)
+ goto err_misc_wq;
+
+ if ((ret = register_blkdev(MD_MAJOR, "md")) < 0)
+ goto err_md;
+
+ if ((ret = register_blkdev(0, "mdp")) < 0)
+ goto err_mdp;
+ mdp_major = ret;
+
blk_register_region(MKDEV(MD_MAJOR, 0), 1UL<<MINORBITS, THIS_MODULE,
md_probe, NULL, NULL);
blk_register_region(MKDEV(mdp_major, 0), 1UL<<MINORBITS, THIS_MODULE,
md_geninit();
return 0;
-}
+err_mdp:
+ unregister_blkdev(MD_MAJOR, "md");
+err_md:
+ destroy_workqueue(md_misc_wq);
+err_misc_wq:
+ destroy_workqueue(md_wq);
+err_wq:
+ return ret;
+}
#ifndef MODULE
export_array(mddev);
mddev->hold_active = 0;
}
+ destroy_workqueue(md_misc_wq);
+ destroy_workqueue(md_wq);
}
subsys_initcall(md_init);
struct attribute_group *to_remove;
struct plug_handle *plug; /* if used by personality */
+ struct bio_set *bio_set;
+
/* Generic flush handling.
* The last to finish preflush schedules a worker to submit
* the rest of the request (without the REQ_FLUSH flag).
extern void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
sector_t sector, int size, struct page *page);
extern void md_super_wait(mddev_t *mddev);
-extern int sync_page_io(struct block_device *bdev, sector_t sector, int size,
+extern int sync_page_io(mdk_rdev_t *rdev, sector_t sector, int size,
struct page *page, int rw);
extern void md_do_sync(mddev_t *mddev);
extern void md_new_event(mddev_t *mddev);
extern void mddev_suspend(mddev_t *mddev);
extern void mddev_resume(mddev_t *mddev);
+extern struct bio *bio_clone_mddev(struct bio *bio, gfp_t gfp_mask,
+ mddev_t *mddev);
+extern struct bio *bio_alloc_mddev(gfp_t gfp_mask, int nr_iovecs,
+ mddev_t *mddev);
#endif /* _MD_MD_H */
* Allocate bios : 1 for reading, n-1 for writing
*/
for (j = pi->raid_disks ; j-- ; ) {
- bio = bio_alloc(gfp_flags, RESYNC_PAGES);
+ bio = bio_kmalloc(gfp_flags, RESYNC_PAGES);
if (!bio)
goto out_free_bio;
r1_bio->bios[j] = bio;
rdev_dec_pending(conf->mirrors[mirror].rdev, conf->mddev);
}
+static void r1_bio_write_done(r1bio_t *r1_bio, int vcnt, struct bio_vec *bv,
+ int behind)
+{
+ if (atomic_dec_and_test(&r1_bio->remaining))
+ {
+ /* it really is the end of this request */
+ if (test_bit(R1BIO_BehindIO, &r1_bio->state)) {
+ /* free extra copy of the data pages */
+ int i = vcnt;
+ while (i--)
+ safe_put_page(bv[i].bv_page);
+ }
+ /* clear the bitmap if all writes complete successfully */
+ bitmap_endwrite(r1_bio->mddev->bitmap, r1_bio->sector,
+ r1_bio->sectors,
+ !test_bit(R1BIO_Degraded, &r1_bio->state),
+ behind);
+ md_write_end(r1_bio->mddev);
+ raid_end_bio_io(r1_bio);
+ }
+}
+
static void raid1_end_write_request(struct bio *bio, int error)
{
int uptodate = test_bit(BIO_UPTODATE, &bio->bi_flags);
* Let's see if all mirrored write operations have finished
* already.
*/
- if (atomic_dec_and_test(&r1_bio->remaining)) {
- if (test_bit(R1BIO_BehindIO, &r1_bio->state)) {
- /* free extra copy of the data pages */
- int i = bio->bi_vcnt;
- while (i--)
- safe_put_page(bio->bi_io_vec[i].bv_page);
- }
- /* clear the bitmap if all writes complete successfully */
- bitmap_endwrite(r1_bio->mddev->bitmap, r1_bio->sector,
- r1_bio->sectors,
- !test_bit(R1BIO_Degraded, &r1_bio->state),
- behind);
- md_write_end(r1_bio->mddev);
- raid_end_bio_io(r1_bio);
- }
+ r1_bio_write_done(r1_bio, bio->bi_vcnt, bio->bi_io_vec, behind);
if (to_put)
bio_put(to_put);
static int read_balance(conf_t *conf, r1bio_t *r1_bio)
{
const sector_t this_sector = r1_bio->sector;
- int new_disk = conf->last_used, disk = new_disk;
- int wonly_disk = -1;
const int sectors = r1_bio->sectors;
+ int new_disk = -1;
+ int start_disk;
+ int i;
sector_t new_distance, current_distance;
mdk_rdev_t *rdev;
+ int choose_first;
rcu_read_lock();
/*
retry:
if (conf->mddev->recovery_cp < MaxSector &&
(this_sector + sectors >= conf->next_resync)) {
- /* Choose the first operational device, for consistancy */
- new_disk = 0;
-
- for (rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
- r1_bio->bios[new_disk] == IO_BLOCKED ||
- !rdev || !test_bit(In_sync, &rdev->flags)
- || test_bit(WriteMostly, &rdev->flags);
- rdev = rcu_dereference(conf->mirrors[++new_disk].rdev)) {
-
- if (rdev && test_bit(In_sync, &rdev->flags) &&
- r1_bio->bios[new_disk] != IO_BLOCKED)
- wonly_disk = new_disk;
-
- if (new_disk == conf->raid_disks - 1) {
- new_disk = wonly_disk;
- break;
- }
- }
- goto rb_out;
+ choose_first = 1;
+ start_disk = 0;
+ } else {
+ choose_first = 0;
+ start_disk = conf->last_used;
}
-
/* make sure the disk is operational */
- for (rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
- r1_bio->bios[new_disk] == IO_BLOCKED ||
- !rdev || !test_bit(In_sync, &rdev->flags) ||
- test_bit(WriteMostly, &rdev->flags);
- rdev = rcu_dereference(conf->mirrors[new_disk].rdev)) {
-
- if (rdev && test_bit(In_sync, &rdev->flags) &&
- r1_bio->bios[new_disk] != IO_BLOCKED)
- wonly_disk = new_disk;
-
- if (new_disk <= 0)
- new_disk = conf->raid_disks;
- new_disk--;
- if (new_disk == disk) {
- new_disk = wonly_disk;
+ for (i = 0 ; i < conf->raid_disks ; i++) {
+ int disk = start_disk + i;
+ if (disk >= conf->raid_disks)
+ disk -= conf->raid_disks;
+
+ rdev = rcu_dereference(conf->mirrors[disk].rdev);
+ if (r1_bio->bios[disk] == IO_BLOCKED
+ || rdev == NULL
+ || !test_bit(In_sync, &rdev->flags))
+ continue;
+
+ new_disk = disk;
+ if (!test_bit(WriteMostly, &rdev->flags))
break;
- }
}
- if (new_disk < 0)
+ if (new_disk < 0 || choose_first)
goto rb_out;
- disk = new_disk;
- /* now disk == new_disk == starting point for search */
-
/*
* Don't change to another disk for sequential reads:
*/
if (this_sector == conf->mirrors[new_disk].head_position)
goto rb_out;
- current_distance = abs(this_sector - conf->mirrors[disk].head_position);
-
- /* Find the disk whose head is closest */
+ current_distance = abs(this_sector
+ - conf->mirrors[new_disk].head_position);
- do {
- if (disk <= 0)
- disk = conf->raid_disks;
- disk--;
+ /* look for a better disk - i.e. head is closer */
+ start_disk = new_disk;
+ for (i = 1; i < conf->raid_disks; i++) {
+ int disk = start_disk + 1;
+ if (disk >= conf->raid_disks)
+ disk -= conf->raid_disks;
rdev = rcu_dereference(conf->mirrors[disk].rdev);
-
- if (!rdev || r1_bio->bios[disk] == IO_BLOCKED ||
- !test_bit(In_sync, &rdev->flags) ||
- test_bit(WriteMostly, &rdev->flags))
+ if (r1_bio->bios[disk] == IO_BLOCKED
+ || rdev == NULL
+ || !test_bit(In_sync, &rdev->flags)
+ || test_bit(WriteMostly, &rdev->flags))
continue;
if (!atomic_read(&rdev->nr_pending)) {
current_distance = new_distance;
new_disk = disk;
}
- } while (disk != conf->last_used);
+ }
rb_out:
-
-
if (new_disk >= 0) {
rdev = rcu_dereference(conf->mirrors[new_disk].rdev);
if (!rdev)
/* block any new IO from starting */
conf->barrier++;
- /* No wait for all pending IO to complete */
+ /* Now wait for all pending IO to complete */
wait_event_lock_irq(conf->wait_barrier,
!conf->nr_pending && conf->barrier < RESYNC_DEPTH,
conf->resync_lock,
}
-/* duplicate the data pages for behind I/O */
-static struct page **alloc_behind_pages(struct bio *bio)
+/* duplicate the data pages for behind I/O
+ * We return a list of bio_vec rather than just page pointers
+ * as it makes freeing easier
+ */
+static struct bio_vec *alloc_behind_pages(struct bio *bio)
{
int i;
struct bio_vec *bvec;
- struct page **pages = kzalloc(bio->bi_vcnt * sizeof(struct page *),
+ struct bio_vec *pages = kzalloc(bio->bi_vcnt * sizeof(struct bio_vec),
GFP_NOIO);
if (unlikely(!pages))
goto do_sync_io;
bio_for_each_segment(bvec, bio, i) {
- pages[i] = alloc_page(GFP_NOIO);
- if (unlikely(!pages[i]))
+ pages[i].bv_page = alloc_page(GFP_NOIO);
+ if (unlikely(!pages[i].bv_page))
goto do_sync_io;
- memcpy(kmap(pages[i]) + bvec->bv_offset,
+ memcpy(kmap(pages[i].bv_page) + bvec->bv_offset,
kmap(bvec->bv_page) + bvec->bv_offset, bvec->bv_len);
- kunmap(pages[i]);
+ kunmap(pages[i].bv_page);
kunmap(bvec->bv_page);
}
do_sync_io:
if (pages)
- for (i = 0; i < bio->bi_vcnt && pages[i]; i++)
- put_page(pages[i]);
+ for (i = 0; i < bio->bi_vcnt && pages[i].bv_page; i++)
+ put_page(pages[i].bv_page);
kfree(pages);
PRINTK("%dB behind alloc failed, doing sync I/O\n", bio->bi_size);
return NULL;
int i, targets = 0, disks;
struct bitmap *bitmap;
unsigned long flags;
- struct bio_list bl;
- struct page **behind_pages = NULL;
+ struct bio_vec *behind_pages = NULL;
const int rw = bio_data_dir(bio);
const unsigned long do_sync = (bio->bi_rw & REQ_SYNC);
const unsigned long do_flush_fua = (bio->bi_rw & (REQ_FLUSH | REQ_FUA));
}
r1_bio->read_disk = rdisk;
- read_bio = bio_clone(bio, GFP_NOIO);
+ read_bio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r1_bio->bios[rdisk] = read_bio;
* bios[x] to bio
*/
disks = conf->raid_disks;
-#if 0
- { static int first=1;
- if (first) printk("First Write sector %llu disks %d\n",
- (unsigned long long)r1_bio->sector, disks);
- first = 0;
- }
-#endif
retry_write:
blocked_rdev = NULL;
rcu_read_lock();
(behind_pages = alloc_behind_pages(bio)) != NULL)
set_bit(R1BIO_BehindIO, &r1_bio->state);
- atomic_set(&r1_bio->remaining, 0);
+ atomic_set(&r1_bio->remaining, 1);
atomic_set(&r1_bio->behind_remaining, 0);
- bio_list_init(&bl);
+ bitmap_startwrite(bitmap, bio->bi_sector, r1_bio->sectors,
+ test_bit(R1BIO_BehindIO, &r1_bio->state));
for (i = 0; i < disks; i++) {
struct bio *mbio;
if (!r1_bio->bios[i])
continue;
- mbio = bio_clone(bio, GFP_NOIO);
+ mbio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r1_bio->bios[i] = mbio;
mbio->bi_sector = r1_bio->sector + conf->mirrors[i].rdev->data_offset;
* we clear any unused pointer in the io_vec, rather
* than leave them unchanged. This is important
* because when we come to free the pages, we won't
- * know the originial bi_idx, so we just free
+ * know the original bi_idx, so we just free
* them all
*/
__bio_for_each_segment(bvec, mbio, j, 0)
- bvec->bv_page = behind_pages[j];
+ bvec->bv_page = behind_pages[j].bv_page;
if (test_bit(WriteMostly, &conf->mirrors[i].rdev->flags))
atomic_inc(&r1_bio->behind_remaining);
}
atomic_inc(&r1_bio->remaining);
-
- bio_list_add(&bl, mbio);
+ spin_lock_irqsave(&conf->device_lock, flags);
+ bio_list_add(&conf->pending_bio_list, mbio);
+ blk_plug_device(mddev->queue);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
}
+ r1_bio_write_done(r1_bio, bio->bi_vcnt, behind_pages, behind_pages != NULL);
kfree(behind_pages); /* the behind pages are attached to the bios now */
- bitmap_startwrite(bitmap, bio->bi_sector, r1_bio->sectors,
- test_bit(R1BIO_BehindIO, &r1_bio->state));
- spin_lock_irqsave(&conf->device_lock, flags);
- bio_list_merge(&conf->pending_bio_list, &bl);
- bio_list_init(&bl);
-
- blk_plug_device(mddev->queue);
- spin_unlock_irqrestore(&conf->device_lock, flags);
-
- /* In case raid1d snuck into freeze_array */
+ /* In case raid1d snuck in to freeze_array */
wake_up(&conf->wait_barrier);
if (do_sync)
md_wakeup_thread(mddev->thread);
-#if 0
- while ((bio = bio_list_pop(&bl)) != NULL)
- generic_make_request(bio);
-#endif
return 0;
}
err = -EBUSY;
goto abort;
}
- /* Only remove non-faulty devices is recovery
+ /* Only remove non-faulty devices if recovery
* is not possible.
*/
if (!test_bit(Faulty, &rdev->flags) &&
break;
}
if (!uptodate) {
- int sync_blocks = 0;
+ sector_t sync_blocks = 0;
sector_t s = r1_bio->sector;
long sectors_to_go = r1_bio->sectors;
/* make sure these bits doesn't get cleared. */
* active, and resync is currently active
*/
rdev = conf->mirrors[d].rdev;
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
continue;
rdev = conf->mirrors[d].rdev;
atomic_add(s, &rdev->corrected_errors);
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
if (r1_bio->bios[d]->bi_end_io != end_sync_read)
continue;
rdev = conf->mirrors[d].rdev;
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
bio->bi_io_vec[idx].bv_page,
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags) &&
- sync_page_io(rdev->bdev,
+ sync_page_io(rdev,
sect + rdev->data_offset,
s<<9,
conf->tmppage, READ))
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags)) {
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9, conf->tmppage, WRITE)
== 0)
rdev = conf->mirrors[d].rdev;
if (rdev &&
test_bit(In_sync, &rdev->flags)) {
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
sect + rdev->data_offset,
s<<9, conf->tmppage, READ)
== 0)
mddev->ro ? IO_BLOCKED : NULL;
r1_bio->read_disk = disk;
bio_put(bio);
- bio = bio_clone(r1_bio->master_bio, GFP_NOIO);
+ bio = bio_clone_mddev(r1_bio->master_bio,
+ GFP_NOIO, mddev);
r1_bio->bios[r1_bio->read_disk] = bio;
rdev = conf->mirrors[disk].rdev;
if (printk_ratelimit())
int i;
int wonly = -1;
int write_targets = 0, read_targets = 0;
- int sync_blocks;
+ sector_t sync_blocks;
int still_degraded = 0;
if (!conf->r1buf_pool)
msleep_interruptible(1000);
bitmap_cond_end_sync(mddev->bitmap, sector_nr);
+ r1_bio = mempool_alloc(conf->r1buf_pool, GFP_NOIO);
raise_barrier(conf);
conf->next_resync = sector_nr;
- r1_bio = mempool_alloc(conf->r1buf_pool, GFP_NOIO);
rcu_read_lock();
/*
* If we get a correctably read error during resync or recovery,
init_waitqueue_head(&conf->wait_barrier);
bio_list_init(&conf->pending_bio_list);
- bio_list_init(&conf->flushing_bio_list);
conf->last_used = -1;
for (i = 0; i < conf->raid_disks; i++) {
struct list_head retry_list;
/* queue pending writes and submit them on unplug */
struct bio_list pending_bio_list;
- /* queue of writes that have been unplugged */
- struct bio_list flushing_bio_list;
/* for use when syncing mirrors: */
* Allocate bios.
*/
for (j = nalloc ; j-- ; ) {
- bio = bio_alloc(gfp_flags, RESYNC_PAGES);
+ bio = bio_kmalloc(gfp_flags, RESYNC_PAGES);
if (!bio)
goto out_free_bio;
r10_bio->devs[j].bio = bio;
const int rw = bio_data_dir(bio);
const unsigned long do_sync = (bio->bi_rw & REQ_SYNC);
const unsigned long do_fua = (bio->bi_rw & REQ_FUA);
- struct bio_list bl;
unsigned long flags;
mdk_rdev_t *blocked_rdev;
}
mirror = conf->mirrors + disk;
- read_bio = bio_clone(bio, GFP_NOIO);
+ read_bio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r10_bio->devs[slot].bio = read_bio;
goto retry_write;
}
- atomic_set(&r10_bio->remaining, 0);
+ atomic_set(&r10_bio->remaining, 1);
+ bitmap_startwrite(mddev->bitmap, bio->bi_sector, r10_bio->sectors, 0);
- bio_list_init(&bl);
for (i = 0; i < conf->copies; i++) {
struct bio *mbio;
int d = r10_bio->devs[i].devnum;
if (!r10_bio->devs[i].bio)
continue;
- mbio = bio_clone(bio, GFP_NOIO);
+ mbio = bio_clone_mddev(bio, GFP_NOIO, mddev);
r10_bio->devs[i].bio = mbio;
mbio->bi_sector = r10_bio->devs[i].addr+
mbio->bi_private = r10_bio;
atomic_inc(&r10_bio->remaining);
- bio_list_add(&bl, mbio);
+ spin_lock_irqsave(&conf->device_lock, flags);
+ bio_list_add(&conf->pending_bio_list, mbio);
+ blk_plug_device(mddev->queue);
+ spin_unlock_irqrestore(&conf->device_lock, flags);
}
- if (unlikely(!atomic_read(&r10_bio->remaining))) {
- /* the array is dead */
+ if (atomic_dec_and_test(&r10_bio->remaining)) {
+ /* This matches the end of raid10_end_write_request() */
+ bitmap_endwrite(r10_bio->mddev->bitmap, r10_bio->sector,
+ r10_bio->sectors,
+ !test_bit(R10BIO_Degraded, &r10_bio->state),
+ 0);
md_write_end(mddev);
raid_end_bio_io(r10_bio);
- return 0;
}
- bitmap_startwrite(mddev->bitmap, bio->bi_sector, r10_bio->sectors, 0);
- spin_lock_irqsave(&conf->device_lock, flags);
- bio_list_merge(&conf->pending_bio_list, &bl);
- blk_plug_device(mddev->queue);
- spin_unlock_irqrestore(&conf->device_lock, flags);
-
/* In case raid10d snuck in to freeze_array */
wake_up(&conf->wait_barrier);
test_bit(In_sync, &rdev->flags)) {
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- success = sync_page_io(rdev->bdev,
+ success = sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9,
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
atomic_add(s, &rdev->corrected_errors);
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9, conf->tmppage, WRITE)
char b[BDEVNAME_SIZE];
atomic_inc(&rdev->nr_pending);
rcu_read_unlock();
- if (sync_page_io(rdev->bdev,
+ if (sync_page_io(rdev,
r10_bio->devs[sl].addr +
sect + rdev->data_offset,
s<<9, conf->tmppage,
mdname(mddev),
bdevname(rdev->bdev,b),
(unsigned long long)r10_bio->sector);
- bio = bio_clone(r10_bio->master_bio, GFP_NOIO);
+ bio = bio_clone_mddev(r10_bio->master_bio,
+ GFP_NOIO, mddev);
r10_bio->devs[r10_bio->read_slot].bio = bio;
bio->bi_sector = r10_bio->devs[r10_bio->read_slot].addr
+ rdev->data_offset;
int disk;
int i;
int max_sync;
- int sync_blocks;
+ sector_t sync_blocks;
sector_t sectors_skipped = 0;
int chunks_skipped = 0;
return 0;
}
/*
- * use bio_clone to make a copy of the bio
+ * use bio_clone_mddev to make a copy of the bio
*/
- align_bi = bio_clone(raid_bio, GFP_NOIO);
+ align_bi = bio_clone_mddev(raid_bio, GFP_NOIO, mddev);
if (!align_bi)
return 0;
/*
raid5_conf_t *conf = mddev->private;
struct stripe_head *sh;
sector_t max_sector = mddev->dev_sectors;
- int sync_blocks;
+ sector_t sync_blocks;
int still_degraded = 0;
int i;
static unsigned int ir_lookup_by_scancode(const struct ir_scancode_table *rc_tab,
unsigned int scancode)
{
- unsigned int start = 0;
- unsigned int end = rc_tab->len - 1;
- unsigned int mid;
+ int start = 0;
+ int end = rc_tab->len - 1;
+ int mid;
while (start <= end) {
mid = (start + end) / 2;
static int ibmasmfs_fill_super (struct super_block *sb, void *data, int silent);
-static int ibmasmfs_get_super(struct file_system_type *fst,
- int flags, const char *name, void *data,
- struct vfsmount *mnt)
+static struct dentry *ibmasmfs_mount(struct file_system_type *fst,
+ int flags, const char *name, void *data)
{
- return get_sb_single(fst, flags, data, ibmasmfs_fill_super, mnt);
+ return mount_single(fst, flags, data, ibmasmfs_fill_super);
}
static const struct super_operations ibmasmfs_s_ops = {
static struct file_system_type ibmasmfs_type = {
.owner = THIS_MODULE,
.name = "ibmasmfs",
- .get_sb = ibmasmfs_get_super,
+ .mount = ibmasmfs_mount,
.kill_sb = kill_litter_super,
};
return configure_kgdbts();
}
-static void cleanup_kgdbts(void)
-{
- if (configured == 1)
- kgdb_unregister_io_module(&kgdbts_io_ops);
-}
-
static int kgdbts_get_char(void)
{
int val = 0;
return 0;
}
- if (kgdb_connected) {
- printk(KERN_ERR
- "kgdbts: Cannot reconfigure while KGDB is connected.\n");
-
+ if (configured == 1) {
+ printk(KERN_ERR "kgdbts: ERROR: Already configured and running.\n");
return -EBUSY;
}
if (config[len - 1] == '\n')
config[len - 1] = '\0';
- if (configured == 1)
- cleanup_kgdbts();
-
/* Go and configure with the new params. */
return configure_kgdbts();
}
};
module_init(init_kgdbts);
-module_exit(cleanup_kgdbts);
module_param_call(kgdbts, param_set_kgdbts_var, param_get_string, &kps, 0644);
MODULE_PARM_DESC(kgdbts, "<A|V1|V2>[F#|S#][N#]");
MODULE_DESCRIPTION("KGDB Test Suite");
switch (mode) {
case FL_WRITING:
- write_cmd = (cfi->cfiq->P_ID != 0x0200) ? CMD(0x40) : CMD(0x41);
+ write_cmd = (cfi->cfiq->P_ID != P_ID_INTEL_PERFORMANCE) ? CMD(0x40) : CMD(0x41);
break;
case FL_OTP_WRITE:
write_cmd = CMD(0xc0);
cmd_adr = adr & ~(wbufsize-1);
/* Let's determine this according to the interleave only once */
- write_cmd = (cfi->cfiq->P_ID != 0x0200) ? CMD(0xe8) : CMD(0xe9);
+ write_cmd = (cfi->cfiq->P_ID != P_ID_INTEL_PERFORMANCE) ? CMD(0xe8) : CMD(0xe9);
mutex_lock(&chip->mutex);
ret = get_chip(map, chip, cmd_adr, FL_WRITING);
cfi->addr_unlock1 = 0x555;
cfi->addr_unlock2 = 0x2AA;
+
+ cfi->sector_erase_cmd = CMD(0x50);
+}
+
+static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd, void *param)
+{
+ struct map_info *map = mtd->priv;
+ struct cfi_private *cfi = map->fldrv_priv;
+
+ fixup_sst39vf_rev_b(mtd, param);
+
+ /*
+ * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
+ * it should report a size of 8KBytes (0x0020*256).
+ */
+ cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
+ pr_warning("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", mtd->name);
}
static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
/* Used to fix CFI-Tables of chips without Extended Query Tables */
static struct cfi_fixup cfi_nopri_fixup_table[] = {
- { CFI_MFR_SST, 0x234A, fixup_sst39vf, NULL, }, // SST39VF1602
- { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601
- { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202
- { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201
- { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, // SST39VF3202B
- { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, // SST39VF3201B
- { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, // SST39VF6402B
- { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, // SST39VF6401B
+ { CFI_MFR_SST, 0x234A, fixup_sst39vf, NULL, }, /* SST39VF1602 */
+ { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, /* SST39VF1601 */
+ { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, /* SST39VF3202 */
+ { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, /* SST39VF3201 */
+ { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, /* SST39VF3202B */
+ { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, /* SST39VF3201B */
+ { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, /* SST39VF6402B */
+ { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, /* SST39VF6401B */
{ 0, 0, NULL, NULL }
};
{ CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
{ CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
{ CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
+ { CFI_MFR_SST, 0x536A, fixup_sst38vf640x_sectorsize, NULL, }, /* SST38VF6402 */
+ { CFI_MFR_SST, 0x536B, fixup_sst38vf640x_sectorsize, NULL, }, /* SST38VF6401 */
+ { CFI_MFR_SST, 0x536C, fixup_sst38vf640x_sectorsize, NULL, }, /* SST38VF6404 */
+ { CFI_MFR_SST, 0x536D, fixup_sst38vf640x_sectorsize, NULL, }, /* SST38VF6403 */
#if !FORCE_WORD_WRITE
{ CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
#endif
if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e &&
extp->MajorVersion == '0')
extp->MajorVersion = '1';
+ /*
+ * SST 38VF640x chips report major=0xFF / minor=0xFF.
+ */
+ if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
+ extp->MajorVersion = '1';
+ extp->MinorVersion = '0';
+ }
}
struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
goto setup_err;
}
-#if 0
- // debug
- for (i=0; i<mtd->numeraseregions;i++){
- printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
- i,mtd->eraseregions[i].offset,
- mtd->eraseregions[i].erasesize,
- mtd->eraseregions[i].numblocks);
- }
-#endif
__module_get(THIS_MODULE);
register_reboot_notifier(&mtd->reboot_notifier);
* there was an error (so leave the erase
* routine to recover from it) or we trying to
* use the erase-in-progress sector. */
- map_write(map, CMD(0x30), chip->in_progress_block_addr);
+ map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
chip->state = FL_ERASING;
chip->oldstate = FL_READY;
printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
switch(chip->oldstate) {
case FL_ERASING:
chip->state = chip->oldstate;
- map_write(map, CMD(0x30), chip->in_progress_block_addr);
+ map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
chip->oldstate = FL_READY;
chip->state = FL_ERASING;
break;
local_irq_disable();
/* Resume the write or erase operation */
- map_write(map, CMD(0x30), adr);
+ map_write(map, cfi->sector_erase_cmd, adr);
chip->state = oldstate;
start = xip_currtime();
} else if (usec >= 1000000/HZ) {
mutex_lock(&chip->mutex);
if (chip->state != FL_READY){
-#if 0
- printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
-#endif
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&chip->wq, &wait);
schedule();
remove_wait_queue(&chip->wq, &wait);
-#if 0
- if(signal_pending(current))
- return -EINTR;
-#endif
timeo = jiffies + HZ;
goto retry;
mutex_lock(&cfi->chips[chipnum].mutex);
if (cfi->chips[chipnum].state != FL_READY) {
-#if 0
- printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
-#endif
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&cfi->chips[chipnum].wq, &wait);
schedule();
remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
-#if 0
- if(signal_pending(current))
- return -EINTR;
-#endif
goto retry;
}
mutex_lock(&cfi->chips[chipnum].mutex);
if (cfi->chips[chipnum].state != FL_READY) {
-#if 0
- printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
-#endif
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&cfi->chips[chipnum].wq, &wait);
schedule();
remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
-#if 0
- if(signal_pending(current))
- return -EINTR;
-#endif
goto retry1;
}
cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
- //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
/* Write Buffer Load */
map_write(map, CMD(0x25), cmd_adr);
cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
- map_write(map, CMD(0x30), adr);
+ map_write(map, cfi->sector_erase_cmd, adr);
chip->state = FL_ERASING;
chip->erase_suspended = 0;
cfi->cfi_mode = CFI_MODE_CFI;
+ cfi->sector_erase_cmd = CMD(0x30);
+
/* Read the CFI info structure */
xip_disable_qry(base, map, cfi);
for (i=0; i<(sizeof(struct cfi_ident) + num_erase_regions * 4); i++)
cfi_send_gen_cmd(0xAA, 0x5555, base, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, 0x2AAA, base, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x98, 0x5555, base, map, cfi, cfi->device_type, NULL);
+ if (cfi_qry_present(map, base, cfi))
+ return 1;
+ /* SST 39VF640xB */
+ cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL);
+ cfi_send_gen_cmd(0xAA, 0x555, base, map, cfi, cfi->device_type, NULL);
+ cfi_send_gen_cmd(0x55, 0x2AA, base, map, cfi, cfi->device_type, NULL);
+ cfi_send_gen_cmd(0x98, 0x555, base, map, cfi, cfi->device_type, NULL);
if (cfi_qry_present(map, base, cfi))
return 1;
/* QRY not found */
} else
instr->state = MTD_ERASE_DONE;
- instr->state = MTD_ERASE_DONE;
mtd_erase_callback(instr);
return err;
}
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
+ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
+ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
+ { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
+ { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
/* Catalyst / On Semiconductor -- non-JEDEC */
{ "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
nr_parts = data->nr_parts;
}
-#ifdef CONFIG_OF
+#ifdef CONFIG_MTD_OF_PARTS
if (nr_parts <= 0 && spi->dev.of_node) {
nr_parts = of_mtd_parse_partitions(&spi->dev,
spi->dev.of_node, &parts);
* phram=swap,64Mi,128Mi phram=test,900Mi,1Mi
*/
-#define pr_fmt(fmt) "phram: " fmt
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <asm/io.h>
#include <linux/init.h>
help
Support for flash chips on NETtel/SecureEdge/SnapGear boards.
+config MTD_BCM963XX
+ tristate "Map driver for Broadcom BCM963xx boards"
+ depends on BCM63XX
+ select MTD_MAP_BANK_WIDTH_2
+ select MTD_CFI_I1
+ help
+ Support for parsing CFE image tag and creating MTD partitions on
+ Broadcom BCM63xx boards.
+
config MTD_DILNETPC
tristate "CFI Flash device mapped on DIL/Net PC"
depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
obj-$(CONFIG_MTD_VMU) += vmu-flash.o
obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
+obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o
--- /dev/null
+/*
+ * Copyright © 2006-2008 Florian Fainelli <florian@openwrt.org>
+ * Mike Albon <malbon@openwrt.org>
+ * Copyright © 2009-2010 Daniel Dickinson <openwrt@cshore.neomailbox.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/vmalloc.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/mach-bcm63xx/bcm963xx_tag.h>
+
+#define BCM63XX_BUSWIDTH 2 /* Buswidth */
+#define BCM63XX_EXTENDED_SIZE 0xBFC00000 /* Extended flash address */
+
+#define PFX KBUILD_MODNAME ": "
+
+static struct mtd_partition *parsed_parts;
+
+static struct mtd_info *bcm963xx_mtd_info;
+
+static struct map_info bcm963xx_map = {
+ .name = "bcm963xx",
+ .bankwidth = BCM63XX_BUSWIDTH,
+};
+
+static int parse_cfe_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts)
+{
+ /* CFE, NVRAM and global Linux are always present */
+ int nrparts = 3, curpart = 0;
+ struct bcm_tag *buf;
+ struct mtd_partition *parts;
+ int ret;
+ size_t retlen;
+ unsigned int rootfsaddr, kerneladdr, spareaddr;
+ unsigned int rootfslen, kernellen, sparelen, totallen;
+ int namelen = 0;
+ int i;
+ char *boardid;
+ char *tagversion;
+
+ /* Allocate memory for buffer */
+ buf = vmalloc(sizeof(struct bcm_tag));
+ if (!buf)
+ return -ENOMEM;
+
+ /* Get the tag */
+ ret = master->read(master, master->erasesize, sizeof(struct bcm_tag),
+ &retlen, (void *)buf);
+ if (retlen != sizeof(struct bcm_tag)) {
+ vfree(buf);
+ return -EIO;
+ }
+
+ sscanf(buf->kernel_address, "%u", &kerneladdr);
+ sscanf(buf->kernel_length, "%u", &kernellen);
+ sscanf(buf->total_length, "%u", &totallen);
+ tagversion = &(buf->tag_version[0]);
+ boardid = &(buf->board_id[0]);
+
+ printk(KERN_INFO PFX "CFE boot tag found with version %s "
+ "and board type %s\n", tagversion, boardid);
+
+ kerneladdr = kerneladdr - BCM63XX_EXTENDED_SIZE;
+ rootfsaddr = kerneladdr + kernellen;
+ spareaddr = roundup(totallen, master->erasesize) + master->erasesize;
+ sparelen = master->size - spareaddr - master->erasesize;
+ rootfslen = spareaddr - rootfsaddr;
+
+ /* Determine number of partitions */
+ namelen = 8;
+ if (rootfslen > 0) {
+ nrparts++;
+ namelen += 6;
+ };
+ if (kernellen > 0) {
+ nrparts++;
+ namelen += 6;
+ };
+
+ /* Ask kernel for more memory */
+ parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL);
+ if (!parts) {
+ vfree(buf);
+ return -ENOMEM;
+ };
+
+ /* Start building partition list */
+ parts[curpart].name = "CFE";
+ parts[curpart].offset = 0;
+ parts[curpart].size = master->erasesize;
+ curpart++;
+
+ if (kernellen > 0) {
+ parts[curpart].name = "kernel";
+ parts[curpart].offset = kerneladdr;
+ parts[curpart].size = kernellen;
+ curpart++;
+ };
+
+ if (rootfslen > 0) {
+ parts[curpart].name = "rootfs";
+ parts[curpart].offset = rootfsaddr;
+ parts[curpart].size = rootfslen;
+ if (sparelen > 0)
+ parts[curpart].size += sparelen;
+ curpart++;
+ };
+
+ parts[curpart].name = "nvram";
+ parts[curpart].offset = master->size - master->erasesize;
+ parts[curpart].size = master->erasesize;
+
+ /* Global partition "linux" to make easy firmware upgrade */
+ curpart++;
+ parts[curpart].name = "linux";
+ parts[curpart].offset = parts[0].size;
+ parts[curpart].size = master->size - parts[0].size - parts[3].size;
+
+ for (i = 0; i < nrparts; i++)
+ printk(KERN_INFO PFX "Partition %d is %s offset %lx and "
+ "length %lx\n", i, parts[i].name,
+ (long unsigned int)(parts[i].offset),
+ (long unsigned int)(parts[i].size));
+
+ printk(KERN_INFO PFX "Spare partition is %x offset and length %x\n",
+ spareaddr, sparelen);
+ *pparts = parts;
+ vfree(buf);
+
+ return nrparts;
+};
+
+static int bcm963xx_detect_cfe(struct mtd_info *master)
+{
+ int idoffset = 0x4e0;
+ static char idstring[8] = "CFE1CFE1";
+ char buf[9];
+ int ret;
+ size_t retlen;
+
+ ret = master->read(master, idoffset, 8, &retlen, (void *)buf);
+ buf[retlen] = 0;
+ printk(KERN_INFO PFX "Read Signature value of %s\n", buf);
+
+ return strncmp(idstring, buf, 8);
+}
+
+static int bcm963xx_probe(struct platform_device *pdev)
+{
+ int err = 0;
+ int parsed_nr_parts = 0;
+ char *part_type;
+ struct resource *r;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!r) {
+ dev_err(&pdev->dev, "no resource supplied\n");
+ return -ENODEV;
+ }
+
+ bcm963xx_map.phys = r->start;
+ bcm963xx_map.size = resource_size(r);
+ bcm963xx_map.virt = ioremap(r->start, resource_size(r));
+ if (!bcm963xx_map.virt) {
+ dev_err(&pdev->dev, "failed to ioremap\n");
+ return -EIO;
+ }
+
+ dev_info(&pdev->dev, "0x%08lx at 0x%08x\n",
+ bcm963xx_map.size, bcm963xx_map.phys);
+
+ simple_map_init(&bcm963xx_map);
+
+ bcm963xx_mtd_info = do_map_probe("cfi_probe", &bcm963xx_map);
+ if (!bcm963xx_mtd_info) {
+ dev_err(&pdev->dev, "failed to probe using CFI\n");
+ err = -EIO;
+ goto err_probe;
+ }
+
+ bcm963xx_mtd_info->owner = THIS_MODULE;
+
+ /* This is mutually exclusive */
+ if (bcm963xx_detect_cfe(bcm963xx_mtd_info) == 0) {
+ dev_info(&pdev->dev, "CFE bootloader detected\n");
+ if (parsed_nr_parts == 0) {
+ int ret = parse_cfe_partitions(bcm963xx_mtd_info,
+ &parsed_parts);
+ if (ret > 0) {
+ part_type = "CFE";
+ parsed_nr_parts = ret;
+ }
+ }
+ } else {
+ dev_info(&pdev->dev, "unsupported bootloader\n");
+ err = -ENODEV;
+ goto err_probe;
+ }
+
+ return add_mtd_partitions(bcm963xx_mtd_info, parsed_parts,
+ parsed_nr_parts);
+
+err_probe:
+ iounmap(bcm963xx_map.virt);
+ return err;
+}
+
+static int bcm963xx_remove(struct platform_device *pdev)
+{
+ if (bcm963xx_mtd_info) {
+ del_mtd_partitions(bcm963xx_mtd_info);
+ map_destroy(bcm963xx_mtd_info);
+ }
+
+ if (bcm963xx_map.virt) {
+ iounmap(bcm963xx_map.virt);
+ bcm963xx_map.virt = 0;
+ }
+
+ return 0;
+}
+
+static struct platform_driver bcm63xx_mtd_dev = {
+ .probe = bcm963xx_probe,
+ .remove = bcm963xx_remove,
+ .driver = {
+ .name = "bcm963xx-flash",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init bcm963xx_mtd_init(void)
+{
+ return platform_driver_register(&bcm63xx_mtd_dev);
+}
+
+static void __exit bcm963xx_mtd_exit(void)
+{
+ platform_driver_unregister(&bcm63xx_mtd_dev);
+}
+
+module_init(bcm963xx_mtd_init);
+module_exit(bcm963xx_mtd_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Broadcom BCM63xx MTD driver for CFE and RedBoot");
+MODULE_AUTHOR("Daniel Dickinson <openwrt@cshore.neomailbox.net>");
+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
+MODULE_AUTHOR("Mike Albon <malbon@openwrt.org>");
if (!state)
return -ENOMEM;
+ /*
+ * We cast start/end to known types in the boards file, so cast
+ * away their pointer types here to the known types (gpios->xxx).
+ */
state->gpio_count = gpios->end;
- state->gpio_addrs = (void *)gpios->start;
+ state->gpio_addrs = (void *)(unsigned long)gpios->start;
state->gpio_values = (void *)(state + 1);
- state->win_size = memory->end - memory->start + 1;
+ state->win_size = resource_size(memory);
memset(state->gpio_values, 0xff, arr_size);
state->map.name = DRIVER_NAME;
state->map.copy_to = gf_copy_to;
state->map.bankwidth = pdata->width;
state->map.size = state->win_size * (1 << state->gpio_count);
- state->map.virt = (void __iomem *)memory->start;
+ state->map.virt = ioremap_nocache(memory->start, state->map.size);
state->map.phys = NO_XIP;
state->map.map_priv_1 = (unsigned long)state;
}
dev_info(&dev->p_dev->dev, "mtd%d: %s\n", mtd->index, mtd->name);
return 0;
-
- dev_err(&dev->p_dev->dev, "CS Error, exiting\n");
- pcmciamtd_release(link);
- return -ENODEV;
}
{
int i, plen, nr_parts;
const struct {
- u32 offset, len;
+ __be32 offset, len;
} *part;
const char *names;
names = of_get_property(dp, "partition-names", &plen);
for (i = 0; i < nr_parts; i++) {
- info->parts[i].offset = part->offset;
- info->parts[i].size = part->len & ~1;
- if (part->len & 1) /* bit 0 set signifies read only partition */
+ info->parts[i].offset = be32_to_cpu(part->offset);
+ info->parts[i].size = be32_to_cpu(part->len) & ~1;
+ if (be32_to_cpu(part->len) & 1) /* bit 0 set signifies read only partition */
info->parts[i].mask_flags = MTD_WRITEABLE;
if (names && (plen > 0)) {
struct resource res;
struct of_flash *info;
const char *probe_type = match->data;
- const u32 *width;
+ const __be32 *width;
int err;
int i;
int count;
- const u32 *p;
+ const __be32 *p;
int reg_tuple_size;
struct mtd_info **mtd_list = NULL;
resource_size_t res_size;
for (i = 0; i < count; i++) {
err = -ENXIO;
if (of_address_to_resource(dp, i, &res)) {
- dev_err(&dev->dev, "Can't get IO address from device"
- " tree\n");
- goto err_out;
+ /*
+ * Continue with next register tuple if this
+ * one is not mappable
+ */
+ continue;
}
dev_dbg(&dev->dev, "of_flash device: %.8llx-%.8llx\n",
#include "mtdcore.h"
-static DEFINE_MUTEX(mtd_blkdevs_mutex);
static LIST_HEAD(blktrans_majors);
static DEFINE_MUTEX(blktrans_ref_mutex);
if (!req && !(req = blk_fetch_request(rq))) {
set_current_state(TASK_INTERRUPTIBLE);
+
+ if (kthread_should_stop())
+ set_current_state(TASK_RUNNING);
+
spin_unlock_irq(rq->queue_lock);
schedule();
spin_lock_irq(rq->queue_lock);
static int blktrans_open(struct block_device *bdev, fmode_t mode)
{
struct mtd_blktrans_dev *dev = blktrans_dev_get(bdev->bd_disk);
- int ret;
+ int ret = 0;
if (!dev)
return -ERESTARTSYS; /* FIXME: busy loop! -arnd*/
- mutex_lock(&mtd_blkdevs_mutex);
mutex_lock(&dev->lock);
- if (!dev->mtd) {
- ret = -ENXIO;
+ if (dev->open++)
goto unlock;
- }
- ret = !dev->open++ && dev->tr->open ? dev->tr->open(dev) : 0;
+ kref_get(&dev->ref);
+ __module_get(dev->tr->owner);
+
+ if (dev->mtd) {
+ ret = dev->tr->open ? dev->tr->open(dev) : 0;
+ __get_mtd_device(dev->mtd);
+ }
- /* Take another reference on the device so it won't go away till
- last release */
- if (!ret)
- kref_get(&dev->ref);
unlock:
mutex_unlock(&dev->lock);
blktrans_dev_put(dev);
- mutex_unlock(&mtd_blkdevs_mutex);
return ret;
}
static int blktrans_release(struct gendisk *disk, fmode_t mode)
{
struct mtd_blktrans_dev *dev = blktrans_dev_get(disk);
- int ret = -ENXIO;
+ int ret = 0;
if (!dev)
return ret;
- mutex_lock(&mtd_blkdevs_mutex);
mutex_lock(&dev->lock);
- /* Release one reference, we sure its not the last one here*/
- kref_put(&dev->ref, blktrans_dev_release);
-
- if (!dev->mtd)
+ if (--dev->open)
goto unlock;
- ret = !--dev->open && dev->tr->release ? dev->tr->release(dev) : 0;
+ kref_put(&dev->ref, blktrans_dev_release);
+ module_put(dev->tr->owner);
+
+ if (dev->mtd) {
+ ret = dev->tr->release ? dev->tr->release(dev) : 0;
+ __put_mtd_device(dev->mtd);
+ }
unlock:
mutex_unlock(&dev->lock);
blktrans_dev_put(dev);
- mutex_unlock(&mtd_blkdevs_mutex);
return ret;
}
if (!dev)
return ret;
- mutex_lock(&mtd_blkdevs_mutex);
mutex_lock(&dev->lock);
if (!dev->mtd)
}
unlock:
mutex_unlock(&dev->lock);
- mutex_unlock(&mtd_blkdevs_mutex);
blktrans_dev_put(dev);
return ret;
}
gd->queue = new->rq;
- __get_mtd_device(new->mtd);
- __module_get(tr->owner);
-
/* Create processing thread */
/* TODO: workqueue ? */
new->thread = kthread_run(mtd_blktrans_thread, new,
}
return 0;
error4:
- module_put(tr->owner);
- __put_mtd_device(new->mtd);
blk_cleanup_queue(new->rq);
error3:
put_disk(new->disk);
blk_start_queue(old->rq);
spin_unlock_irqrestore(&old->queue_lock, flags);
- /* Ask trans driver for release to the mtd device */
+ /* If the device is currently open, tell trans driver to close it,
+ then put mtd device, and don't touch it again */
mutex_lock(&old->lock);
- if (old->open && old->tr->release) {
- old->tr->release(old);
- old->open = 0;
+ if (old->open) {
+ if (old->tr->release)
+ old->tr->release(old);
+ __put_mtd_device(old->mtd);
}
- __put_mtd_device(old->mtd);
- module_put(old->tr->owner);
-
- /* At that point, we don't touch the mtd anymore */
old->mtd = NULL;
mutex_unlock(&old->lock);
mutex_lock(&mtd_table_mutex);
ret = register_blkdev(tr->major, tr->name);
- if (ret) {
+ if (ret < 0) {
printk(KERN_WARNING "Unable to register %s block device on major %d: %d\n",
tr->name, tr->major, ret);
mutex_unlock(&mtd_table_mutex);
return ret;
}
+ if (ret)
+ tr->major = ret;
+
tr->blkshift = ffs(tr->blksize) - 1;
INIT_LIST_HEAD(&tr->devs);
#include <linux/backing-dev.h>
#include <linux/compat.h>
#include <linux/mount.h>
-
+#include <linux/blkpg.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/mtd/map.h>
#include <asm/uaccess.h>
return ret;
}
+/*
+ * Copies (and truncates, if necessary) data from the larger struct,
+ * nand_ecclayout, to the smaller, deprecated layout struct,
+ * nand_ecclayout_user. This is necessary only to suppport the deprecated
+ * API ioctl ECCGETLAYOUT while allowing all new functionality to use
+ * nand_ecclayout flexibly (i.e. the struct may change size in new
+ * releases without requiring major rewrites).
+ */
+static int shrink_ecclayout(const struct nand_ecclayout *from,
+ struct nand_ecclayout_user *to)
+{
+ int i;
+
+ if (!from || !to)
+ return -EINVAL;
+
+ memset(to, 0, sizeof(*to));
+
+ to->eccbytes = min((int)from->eccbytes, MTD_MAX_ECCPOS_ENTRIES);
+ for (i = 0; i < to->eccbytes; i++)
+ to->eccpos[i] = from->eccpos[i];
+
+ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) {
+ if (from->oobfree[i].length == 0 &&
+ from->oobfree[i].offset == 0)
+ break;
+ to->oobavail += from->oobfree[i].length;
+ to->oobfree[i] = from->oobfree[i];
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_MTD_PARTITIONS
+static int mtd_blkpg_ioctl(struct mtd_info *mtd,
+ struct blkpg_ioctl_arg __user *arg)
+{
+ struct blkpg_ioctl_arg a;
+ struct blkpg_partition p;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+
+ /* Only master mtd device must be used to control partitions */
+ if (!mtd_is_master(mtd))
+ return -EINVAL;
+
+ if (copy_from_user(&a, arg, sizeof(struct blkpg_ioctl_arg)))
+ return -EFAULT;
+
+ if (copy_from_user(&p, a.data, sizeof(struct blkpg_partition)))
+ return -EFAULT;
+
+ switch (a.op) {
+ case BLKPG_ADD_PARTITION:
+
+ return mtd_add_partition(mtd, p.devname, p.start, p.length);
+
+ case BLKPG_DEL_PARTITION:
+
+ if (p.pno < 0)
+ return -EINVAL;
+
+ return mtd_del_partition(mtd, p.pno);
+
+ default:
+ return -EINVAL;
+ }
+}
+#endif
+
+
static int mtd_ioctl(struct file *file, u_int cmd, u_long arg)
{
struct mtd_file_info *mfi = file->private_data;
if (get_user(ur_idx, &(ur->regionindex)))
return -EFAULT;
+ if (ur_idx >= mtd->numeraseregions)
+ return -EINVAL;
+
kr = &(mtd->eraseregions[ur_idx]);
if (put_user(kr->offset, &(ur->offset))
}
#endif
+ /* This ioctl is being deprecated - it truncates the ecc layout */
case ECCGETLAYOUT:
{
+ struct nand_ecclayout_user *usrlay;
+
if (!mtd->ecclayout)
return -EOPNOTSUPP;
- if (copy_to_user(argp, mtd->ecclayout,
- sizeof(struct nand_ecclayout)))
- return -EFAULT;
+ usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL);
+ if (!usrlay)
+ return -ENOMEM;
+
+ shrink_ecclayout(mtd->ecclayout, usrlay);
+
+ if (copy_to_user(argp, usrlay, sizeof(*usrlay)))
+ ret = -EFAULT;
+ kfree(usrlay);
break;
}
break;
}
+#ifdef CONFIG_MTD_PARTITIONS
+ case BLKPG:
+ {
+ ret = mtd_blkpg_ioctl(mtd,
+ (struct blkpg_ioctl_arg __user *)arg);
+ break;
+ }
+
+ case BLKRRPART:
+ {
+ /* No reread partition feature. Just return ok */
+ ret = 0;
+ break;
+ }
+#endif
+
default:
ret = -ENOTTY;
}
#endif
};
-static int mtd_inodefs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *mtd_inodefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "mtd_inode:", NULL, MTD_INODE_FS_MAGIC,
- mnt);
+ return mount_pseudo(fs_type, "mtd_inode:", NULL, MTD_INODE_FS_MAGIC);
}
static struct file_system_type mtd_inodefs_type = {
.name = "mtd_inodefs",
- .get_sb = mtd_inodefs_get_sb,
+ .mount = mtd_inodefs_mount,
.kill_sb = kill_anon_super,
};
#include <linux/kmod.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/err.h>
/* Our partition linked list */
static LIST_HEAD(mtd_partitions);
+static DEFINE_MUTEX(mtd_partitions_mutex);
/* Our partition node structure */
struct mtd_part {
return res;
}
+static inline void free_partition(struct mtd_part *p)
+{
+ kfree(p->mtd.name);
+ kfree(p);
+}
+
/*
* This function unregisters and destroy all slave MTD objects which are
* attached to the given master MTD object.
int del_mtd_partitions(struct mtd_info *master)
{
struct mtd_part *slave, *next;
+ int ret, err = 0;
+ mutex_lock(&mtd_partitions_mutex);
list_for_each_entry_safe(slave, next, &mtd_partitions, list)
if (slave->master == master) {
+ ret = del_mtd_device(&slave->mtd);
+ if (ret < 0) {
+ err = ret;
+ continue;
+ }
list_del(&slave->list);
- del_mtd_device(&slave->mtd);
- kfree(slave);
+ free_partition(slave);
}
+ mutex_unlock(&mtd_partitions_mutex);
- return 0;
+ return err;
}
EXPORT_SYMBOL(del_mtd_partitions);
-static struct mtd_part *add_one_partition(struct mtd_info *master,
- const struct mtd_partition *part, int partno,
- uint64_t cur_offset)
+static struct mtd_part *allocate_partition(struct mtd_info *master,
+ const struct mtd_partition *part, int partno,
+ uint64_t cur_offset)
{
struct mtd_part *slave;
+ char *name;
/* allocate the partition structure */
slave = kzalloc(sizeof(*slave), GFP_KERNEL);
- if (!slave) {
+ name = kstrdup(part->name, GFP_KERNEL);
+ if (!name || !slave) {
printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
- master->name);
- del_mtd_partitions(master);
- return NULL;
+ master->name);
+ kfree(name);
+ kfree(slave);
+ return ERR_PTR(-ENOMEM);
}
- list_add(&slave->list, &mtd_partitions);
/* set up the MTD object for this partition */
slave->mtd.type = master->type;
slave->mtd.oobavail = master->oobavail;
slave->mtd.subpage_sft = master->subpage_sft;
- slave->mtd.name = part->name;
+ slave->mtd.name = name;
slave->mtd.owner = master->owner;
slave->mtd.backing_dev_info = master->backing_dev_info;
}
out_register:
- /* register our partition */
- add_mtd_device(&slave->mtd);
-
return slave;
}
+int mtd_add_partition(struct mtd_info *master, char *name,
+ long long offset, long long length)
+{
+ struct mtd_partition part;
+ struct mtd_part *p, *new;
+ uint64_t start, end;
+ int ret = 0;
+
+ /* the direct offset is expected */
+ if (offset == MTDPART_OFS_APPEND ||
+ offset == MTDPART_OFS_NXTBLK)
+ return -EINVAL;
+
+ if (length == MTDPART_SIZ_FULL)
+ length = master->size - offset;
+
+ if (length <= 0)
+ return -EINVAL;
+
+ part.name = name;
+ part.size = length;
+ part.offset = offset;
+ part.mask_flags = 0;
+ part.ecclayout = NULL;
+
+ new = allocate_partition(master, &part, -1, offset);
+ if (IS_ERR(new))
+ return PTR_ERR(new);
+
+ start = offset;
+ end = offset + length;
+
+ mutex_lock(&mtd_partitions_mutex);
+ list_for_each_entry(p, &mtd_partitions, list)
+ if (p->master == master) {
+ if ((start >= p->offset) &&
+ (start < (p->offset + p->mtd.size)))
+ goto err_inv;
+
+ if ((end >= p->offset) &&
+ (end < (p->offset + p->mtd.size)))
+ goto err_inv;
+ }
+
+ list_add(&new->list, &mtd_partitions);
+ mutex_unlock(&mtd_partitions_mutex);
+
+ add_mtd_device(&new->mtd);
+
+ return ret;
+err_inv:
+ mutex_unlock(&mtd_partitions_mutex);
+ free_partition(new);
+ return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mtd_add_partition);
+
+int mtd_del_partition(struct mtd_info *master, int partno)
+{
+ struct mtd_part *slave, *next;
+ int ret = -EINVAL;
+
+ mutex_lock(&mtd_partitions_mutex);
+ list_for_each_entry_safe(slave, next, &mtd_partitions, list)
+ if ((slave->master == master) &&
+ (slave->mtd.index == partno)) {
+ ret = del_mtd_device(&slave->mtd);
+ if (ret < 0)
+ break;
+
+ list_del(&slave->list);
+ free_partition(slave);
+ break;
+ }
+ mutex_unlock(&mtd_partitions_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_del_partition);
+
/*
* This function, given a master MTD object and a partition table, creates
* and registers slave MTD objects which are bound to the master according to
printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name);
for (i = 0; i < nbparts; i++) {
- slave = add_one_partition(master, parts + i, i, cur_offset);
- if (!slave)
- return -ENOMEM;
+ slave = allocate_partition(master, parts + i, i, cur_offset);
+ if (IS_ERR(slave))
+ return PTR_ERR(slave);
+
+ mutex_lock(&mtd_partitions_mutex);
+ list_add(&slave->list, &mtd_partitions);
+ mutex_unlock(&mtd_partitions_mutex);
+
+ add_mtd_device(&slave->mtd);
+
cur_offset = slave->offset + slave->mtd.size;
}
return ret;
}
EXPORT_SYMBOL_GPL(parse_mtd_partitions);
+
+int mtd_is_master(struct mtd_info *mtd)
+{
+ struct mtd_part *part;
+ int nopart = 0;
+
+ mutex_lock(&mtd_partitions_mutex);
+ list_for_each_entry(part, &mtd_partitions, list)
+ if (&part->mtd == mtd) {
+ nopart = 1;
+ break;
+ }
+ mutex_unlock(&mtd_partitions_mutex);
+
+ return nopart;
+}
+EXPORT_SYMBOL_GPL(mtd_is_master);
/*
* get a superblock on an MTD-backed filesystem
*/
-static int get_sb_mtd_aux(struct file_system_type *fs_type, int flags,
+static struct dentry *mount_mtd_aux(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
struct mtd_info *mtd,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct super_block *sb;
int ret;
ret = fill_super(sb, data, flags & MS_SILENT ? 1 : 0);
if (ret < 0) {
deactivate_locked_super(sb);
- return ret;
+ return ERR_PTR(ret);
}
/* go */
sb->s_flags |= MS_ACTIVE;
- simple_set_mnt(mnt, sb);
-
- return 0;
+ return dget(sb->s_root);
/* new mountpoint for an already mounted superblock */
already_mounted:
DEBUG(1, "MTDSB: Device %d (\"%s\") is already mounted\n",
mtd->index, mtd->name);
- simple_set_mnt(mnt, sb);
- ret = 0;
- goto out_put;
+ put_mtd_device(mtd);
+ return dget(sb->s_root);
out_error:
- ret = PTR_ERR(sb);
-out_put:
put_mtd_device(mtd);
- return ret;
+ return ERR_CAST(sb);
}
/*
* get a superblock on an MTD-backed filesystem by MTD device number
*/
-static int get_sb_mtd_nr(struct file_system_type *fs_type, int flags,
+static struct dentry *mount_mtd_nr(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data, int mtdnr,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct mtd_info *mtd;
mtd = get_mtd_device(NULL, mtdnr);
if (IS_ERR(mtd)) {
DEBUG(0, "MTDSB: Device #%u doesn't appear to exist\n", mtdnr);
- return PTR_ERR(mtd);
+ return ERR_CAST(mtd);
}
- return get_sb_mtd_aux(fs_type, flags, dev_name, data, mtd, fill_super,
- mnt);
+ return mount_mtd_aux(fs_type, flags, dev_name, data, mtd, fill_super);
}
/*
* set up an MTD-based superblock
*/
-int get_sb_mtd(struct file_system_type *fs_type, int flags,
+struct dentry *mount_mtd(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
#ifdef CONFIG_BLOCK
struct block_device *bdev;
int mtdnr;
if (!dev_name)
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
DEBUG(2, "MTDSB: dev_name \"%s\"\n", dev_name);
mtd = get_mtd_device_nm(dev_name + 4);
if (!IS_ERR(mtd))
- return get_sb_mtd_aux(
+ return mount_mtd_aux(
fs_type, flags,
dev_name, data, mtd,
- fill_super, mnt);
+ fill_super);
printk(KERN_NOTICE "MTD:"
" MTD device with name \"%s\" not found.\n",
/* It was a valid number */
DEBUG(1, "MTDSB: mtd%%d, mtdnr %d\n",
mtdnr);
- return get_sb_mtd_nr(fs_type, flags,
+ return mount_mtd_nr(fs_type, flags,
dev_name, data,
- mtdnr, fill_super, mnt);
+ mtdnr, fill_super);
}
}
}
if (IS_ERR(bdev)) {
ret = PTR_ERR(bdev);
DEBUG(1, "MTDSB: lookup_bdev() returned %d\n", ret);
- return ret;
+ return ERR_PTR(ret);
}
DEBUG(1, "MTDSB: lookup_bdev() returned 0\n");
if (major != MTD_BLOCK_MAJOR)
goto not_an_MTD_device;
- return get_sb_mtd_nr(fs_type, flags, dev_name, data, mtdnr, fill_super,
- mnt);
+ return mount_mtd_nr(fs_type, flags, dev_name, data, mtdnr, fill_super);
not_an_MTD_device:
#endif /* CONFIG_BLOCK */
printk(KERN_NOTICE
"MTD: Attempt to mount non-MTD device \"%s\"\n",
dev_name);
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
}
-EXPORT_SYMBOL_GPL(get_sb_mtd);
+EXPORT_SYMBOL_GPL(mount_mtd);
/*
* destroy an MTD-based superblock
This enables the driver for the NAND flash device found on
PXA3xx processors
-config MTD_NAND_PXA3xx_BUILTIN
- bool "Use builtin definitions for some NAND chips (deprecated)"
- depends on MTD_NAND_PXA3xx
- help
- This enables builtin definitions for some NAND chips. This
- is deprecated in favor of platform specific data.
-
config MTD_NAND_CM_X270
tristate "Support for NAND Flash on CM-X270 modules"
depends on MACH_ARMCORE
config MTD_NAND_FSL_ELBC
tristate "NAND support for Freescale eLBC controllers"
depends on PPC_OF
+ select FSL_LBC
help
Various Freescale chips, including the 8313, include a NAND Flash
Controller Module with built-in hardware ECC capabilities.
help
Enables support for NAND Flash on JZ4740 SoC based boards.
+config MTD_NAND_FSMC
+ tristate "Support for NAND on ST Micros FSMC"
+ depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300
+ help
+ Enables support for NAND Flash chips on the ST Microelectronics
+ Flexible Static Memory Controller (FSMC)
+
endif # MTD_NAND
obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
+obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o
obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
0};
#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
-static uint8_t bbt_pattern[] = { 0xff };
-
-static struct nand_bbt_descr bootrom_bbt = {
- .options = 0,
- .offs = 63,
- .len = 1,
- .pattern = bbt_pattern,
-};
-
static struct nand_ecclayout bootrom_ecclayout = {
.eccbytes = 24,
.eccpos = {
/* setup hardware ECC data struct */
if (hardware_ecc) {
#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
- chip->badblock_pattern = &bootrom_bbt;
chip->ecc.layout = &bootrom_ecclayout;
#endif
chip->read_buf = bf5xx_nand_dma_read_buf;
goto out_err_nand_scan;
}
+#ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
+ chip->badblockpos = 63;
+#endif
+
/* add NAND partition */
bf5xx_nand_add_partition(info);
u32 syndrome[4];
u32 ecc_state;
unsigned num_errors, corrected;
- unsigned long timeo = jiffies + msecs_to_jiffies(100);
+ unsigned long timeo;
/* All bytes 0xff? It's an erased page; ignore its ECC. */
for (i = 0; i < 10; i++) {
* after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
* begin trying to poll for the state, you may fall right out of your
* loop without any of the correction calculations having taken place.
- * The recommendation from the hardware team is to wait till ECC_STATE
- * reads less than 4, which means ECC HW has entered correction state.
+ * The recommendation from the hardware team is to initially delay as
+ * long as ECC_STATE reads less than 4. After that, ECC HW has entered
+ * correction state.
*/
+ timeo = jiffies + usecs_to_jiffies(100);
do {
ecc_state = (davinci_nand_readl(info,
NANDFSR_OFFSET) >> 8) & 0x0f;
* breaks userspace ioctl interface with mtd-utils. Once we
* resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
* for the 4KiB page chips.
+ *
+ * TODO: Note that nand_ecclayout has now been expanded and can
+ * hold plenty of OOB entries.
*/
dev_warn(&pdev->dev, "no 4-bit ECC support yet "
"for 4KiB-page NAND\n");
read_status(denali);
break;
case NAND_CMD_READID:
+ case NAND_CMD_PARAM:
reset_buf(denali);
/*sometimes ManufactureId read from register is not right
* e.g. some of Micron MT29F32G08QAA MLC NAND chips
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence <nick.spence@freescale.com>,
* Scott Wood <scottwood@freescale.com>
+ * Jack Lan <jack.lan@freescale.com>
+ * Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/of_platform.h>
+#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct fsl_elbc_ctrl;
-
/* mtd information per set */
struct fsl_elbc_mtd {
struct mtd_info mtd;
struct nand_chip chip;
- struct fsl_elbc_ctrl *ctrl;
+ struct fsl_lbc_ctrl *ctrl;
struct device *dev;
int bank; /* Chip select bank number */
unsigned int fmr; /* FCM Flash Mode Register value */
};
-/* overview of the fsl elbc controller */
+/* Freescale eLBC FCM controller infomation */
-struct fsl_elbc_ctrl {
+struct fsl_elbc_fcm_ctrl {
struct nand_hw_control controller;
struct fsl_elbc_mtd *chips[MAX_BANKS];
- /* device info */
- struct device *dev;
- struct fsl_lbc_regs __iomem *regs;
- int irq;
- wait_queue_head_t irq_wait;
- unsigned int irq_status; /* status read from LTESR by irq handler */
u8 __iomem *addr; /* Address of assigned FCM buffer */
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
unsigned int mdr; /* UPM/FCM Data Register value */
unsigned int use_mdr; /* Non zero if the MDR is to be set */
unsigned int oob; /* Non zero if operating on OOB data */
+ unsigned int counter; /* counter for the initializations */
char *oob_poi; /* Place to write ECC after read back */
};
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
int buf_num;
- ctrl->page = page_addr;
+ elbc_fcm_ctrl->page = page_addr;
out_be32(&lbc->fbar,
page_addr >> (chip->phys_erase_shift - chip->page_shift));
buf_num = page_addr & 7;
}
- ctrl->addr = priv->vbase + buf_num * 1024;
- ctrl->index = column;
+ elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
+ elbc_fcm_ctrl->index = column;
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl->index += priv->page_size ? 2048 : 512;
+ elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
- dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
+ dev_vdbg(priv->dev, "set_addr: bank=%d, "
+ "elbc_fcm_ctrl->addr=0x%p (0x%p), "
"index %x, pes %d ps %d\n",
- buf_num, ctrl->addr, priv->vbase, ctrl->index,
+ buf_num, elbc_fcm_ctrl->addr, priv->vbase,
+ elbc_fcm_ctrl->index,
chip->phys_erase_shift, chip->page_shift);
}
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* Setup the FMR[OP] to execute without write protection */
out_be32(&lbc->fmr, priv->fmr | 3);
- if (ctrl->use_mdr)
- out_be32(&lbc->mdr, ctrl->mdr);
+ if (elbc_fcm_ctrl->use_mdr)
+ out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
- dev_vdbg(ctrl->dev,
+ dev_vdbg(priv->dev,
"fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
- dev_vdbg(ctrl->dev,
+ dev_vdbg(priv->dev,
"fsl_elbc_run_command: fbar=%08x fpar=%08x "
"fbcr=%08x bank=%d\n",
in_be32(&lbc->fbar), in_be32(&lbc->fpar),
/* wait for FCM complete flag or timeout */
wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
FCM_TIMEOUT_MSECS * HZ/1000);
- ctrl->status = ctrl->irq_status;
-
+ elbc_fcm_ctrl->status = ctrl->irq_status;
/* store mdr value in case it was needed */
- if (ctrl->use_mdr)
- ctrl->mdr = in_be32(&lbc->mdr);
+ if (elbc_fcm_ctrl->use_mdr)
+ elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
- ctrl->use_mdr = 0;
+ elbc_fcm_ctrl->use_mdr = 0;
- if (ctrl->status != LTESR_CC) {
- dev_info(ctrl->dev,
+ if (elbc_fcm_ctrl->status != LTESR_CC) {
+ dev_info(priv->dev,
"command failed: fir %x fcr %x status %x mdr %x\n",
in_be32(&lbc->fir), in_be32(&lbc->fcr),
- ctrl->status, ctrl->mdr);
+ elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
return -EIO;
}
static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
{
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
if (priv->page_size) {
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
- ctrl->use_mdr = 0;
+ elbc_fcm_ctrl->use_mdr = 0;
/* clear the read buffer */
- ctrl->read_bytes = 0;
+ elbc_fcm_ctrl->read_bytes = 0;
if (command != NAND_CMD_PAGEPROG)
- ctrl->index = 0;
+ elbc_fcm_ctrl->index = 0;
switch (command) {
/* READ0 and READ1 read the entire buffer to use hardware ECC. */
/* fall-through */
case NAND_CMD_READ0:
- dev_dbg(ctrl->dev,
+ dev_dbg(priv->dev,
"fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
" 0x%x, column: 0x%x.\n", page_addr, column);
out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
set_addr(mtd, 0, page_addr, 0);
- ctrl->read_bytes = mtd->writesize + mtd->oobsize;
- ctrl->index += column;
+ elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
+ elbc_fcm_ctrl->index += column;
fsl_elbc_do_read(chip, 0);
fsl_elbc_run_command(mtd);
/* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB:
- dev_vdbg(ctrl->dev,
+ dev_vdbg(priv->dev,
"fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
" 0x%x, column: 0x%x.\n", page_addr, column);
out_be32(&lbc->fbcr, mtd->oobsize - column);
set_addr(mtd, column, page_addr, 1);
- ctrl->read_bytes = mtd->writesize + mtd->oobsize;
+ elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
fsl_elbc_do_read(chip, 1);
fsl_elbc_run_command(mtd);
/* READID must read all 5 possible bytes while CEB is active */
case NAND_CMD_READID:
- dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
+ dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
(FIR_OP_UA << FIR_OP1_SHIFT) |
out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
/* 5 bytes for manuf, device and exts */
out_be32(&lbc->fbcr, 5);
- ctrl->read_bytes = 5;
- ctrl->use_mdr = 1;
- ctrl->mdr = 0;
+ elbc_fcm_ctrl->read_bytes = 5;
+ elbc_fcm_ctrl->use_mdr = 1;
+ elbc_fcm_ctrl->mdr = 0;
set_addr(mtd, 0, 0, 0);
fsl_elbc_run_command(mtd);
/* ERASE1 stores the block and page address */
case NAND_CMD_ERASE1:
- dev_vdbg(ctrl->dev,
+ dev_vdbg(priv->dev,
"fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
"page_addr: 0x%x.\n", page_addr);
set_addr(mtd, 0, page_addr, 0);
/* ERASE2 uses the block and page address from ERASE1 */
case NAND_CMD_ERASE2:
- dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
+ dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
out_be32(&lbc->fir,
(FIR_OP_CM0 << FIR_OP0_SHIFT) |
(NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
out_be32(&lbc->fbcr, 0);
- ctrl->read_bytes = 0;
- ctrl->use_mdr = 1;
+ elbc_fcm_ctrl->read_bytes = 0;
+ elbc_fcm_ctrl->use_mdr = 1;
fsl_elbc_run_command(mtd);
return;
/* SEQIN sets up the addr buffer and all registers except the length */
case NAND_CMD_SEQIN: {
__be32 fcr;
- dev_vdbg(ctrl->dev,
- "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
+ dev_vdbg(priv->dev,
+ "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
"page_addr: 0x%x, column: 0x%x.\n",
page_addr, column);
- ctrl->column = column;
- ctrl->oob = 0;
- ctrl->use_mdr = 1;
+ elbc_fcm_ctrl->use_mdr = 1;
fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
(NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
/* OOB area --> READOOB */
column -= mtd->writesize;
fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
- ctrl->oob = 1;
+ elbc_fcm_ctrl->oob = 1;
} else {
WARN_ON(column != 0);
/* First 256 bytes --> READ0 */
}
out_be32(&lbc->fcr, fcr);
- set_addr(mtd, column, page_addr, ctrl->oob);
+ set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
return;
}
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
case NAND_CMD_PAGEPROG: {
int full_page;
- dev_vdbg(ctrl->dev,
+ dev_vdbg(priv->dev,
"fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
- "writing %d bytes.\n", ctrl->index);
+ "writing %d bytes.\n", elbc_fcm_ctrl->index);
/* if the write did not start at 0 or is not a full page
* then set the exact length, otherwise use a full page
* write so the HW generates the ECC.
*/
- if (ctrl->oob || ctrl->column != 0 ||
- ctrl->index != mtd->writesize + mtd->oobsize) {
- out_be32(&lbc->fbcr, ctrl->index);
+ if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
+ elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) {
+ out_be32(&lbc->fbcr, elbc_fcm_ctrl->index);
full_page = 0;
} else {
out_be32(&lbc->fbcr, 0);
/* Read back the page in order to fill in the ECC for the
* caller. Is this really needed?
*/
- if (full_page && ctrl->oob_poi) {
+ if (full_page && elbc_fcm_ctrl->oob_poi) {
out_be32(&lbc->fbcr, 3);
set_addr(mtd, 6, page_addr, 1);
- ctrl->read_bytes = mtd->writesize + 9;
+ elbc_fcm_ctrl->read_bytes = mtd->writesize + 9;
fsl_elbc_do_read(chip, 1);
fsl_elbc_run_command(mtd);
- memcpy_fromio(ctrl->oob_poi + 6,
- &ctrl->addr[ctrl->index], 3);
- ctrl->index += 3;
+ memcpy_fromio(elbc_fcm_ctrl->oob_poi + 6,
+ &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], 3);
+ elbc_fcm_ctrl->index += 3;
}
- ctrl->oob_poi = NULL;
+ elbc_fcm_ctrl->oob_poi = NULL;
return;
}
out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
out_be32(&lbc->fbcr, 1);
set_addr(mtd, 0, 0, 0);
- ctrl->read_bytes = 1;
+ elbc_fcm_ctrl->read_bytes = 1;
fsl_elbc_run_command(mtd);
/* The chip always seems to report that it is
* write-protected, even when it is not.
*/
- setbits8(ctrl->addr, NAND_STATUS_WP);
+ setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
return;
/* RESET without waiting for the ready line */
case NAND_CMD_RESET:
- dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
+ dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
fsl_elbc_run_command(mtd);
return;
default:
- dev_err(ctrl->dev,
+ dev_err(priv->dev,
"fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
command);
}
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
unsigned int bufsize = mtd->writesize + mtd->oobsize;
if (len <= 0) {
- dev_err(ctrl->dev, "write_buf of %d bytes", len);
- ctrl->status = 0;
+ dev_err(priv->dev, "write_buf of %d bytes", len);
+ elbc_fcm_ctrl->status = 0;
return;
}
- if ((unsigned int)len > bufsize - ctrl->index) {
- dev_err(ctrl->dev,
+ if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
+ dev_err(priv->dev,
"write_buf beyond end of buffer "
"(%d requested, %u available)\n",
- len, bufsize - ctrl->index);
- len = bufsize - ctrl->index;
+ len, bufsize - elbc_fcm_ctrl->index);
+ len = bufsize - elbc_fcm_ctrl->index;
}
- memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
+ memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
/*
* This is workaround for the weird elbc hangs during nand write,
* Scott Wood says: "...perhaps difference in how long it takes a
* is causing problems, and sync isn't helping for some reason."
* Reading back the last byte helps though.
*/
- in_8(&ctrl->addr[ctrl->index] + len - 1);
+ in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
- ctrl->index += len;
+ elbc_fcm_ctrl->index += len;
}
/*
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
/* If there are still bytes in the FCM, then use the next byte. */
- if (ctrl->index < ctrl->read_bytes)
- return in_8(&ctrl->addr[ctrl->index++]);
+ if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
+ return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
- dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
+ dev_err(priv->dev, "read_byte beyond end of buffer\n");
return ERR_BYTE;
}
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
int avail;
if (len < 0)
return;
- avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
- memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
- ctrl->index += avail;
+ avail = min((unsigned int)len,
+ elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
+ memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
+ elbc_fcm_ctrl->index += avail;
if (len > avail)
- dev_err(ctrl->dev,
+ dev_err(priv->dev,
"read_buf beyond end of buffer "
"(%d requested, %d available)\n",
len, avail);
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
int i;
if (len < 0) {
- dev_err(ctrl->dev, "write_buf of %d bytes", len);
+ dev_err(priv->dev, "write_buf of %d bytes", len);
return -EINVAL;
}
- if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
- dev_err(ctrl->dev,
- "verify_buf beyond end of buffer "
- "(%d requested, %u available)\n",
- len, ctrl->read_bytes - ctrl->index);
+ if ((unsigned int)len >
+ elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
+ dev_err(priv->dev,
+ "verify_buf beyond end of buffer "
+ "(%d requested, %u available)\n",
+ len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
- ctrl->index = ctrl->read_bytes;
+ elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
return -EINVAL;
}
for (i = 0; i < len; i++)
- if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
+ if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
+ != buf[i])
break;
- ctrl->index += len;
- return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
+ elbc_fcm_ctrl->index += len;
+ return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
}
/* This function is called after Program and Erase Operations to
static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
- if (ctrl->status != LTESR_CC)
+ if (elbc_fcm_ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
/* The chip always seems to report that it is
* write-protected, even when it is not.
*/
- return (ctrl->mdr & 0xff) | NAND_STATUS_WP;
+ return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
}
static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
unsigned int al;
priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */
(al << FMR_AL_SHIFT);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
chip->numchips);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
chip->chipsize);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
chip->pagemask);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
chip->chip_delay);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
chip->badblockpos);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
chip->chip_shift);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
chip->page_shift);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
chip->phys_erase_shift);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
chip->ecclayout);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
chip->ecc.mode);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
chip->ecc.steps);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
chip->ecc.bytes);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
chip->ecc.total);
- dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
chip->ecc.layout);
- dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
- dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
- dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
+ dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
+ dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
mtd->erasesize);
- dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
mtd->writesize);
- dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
+ dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
mtd->oobsize);
/* adjust Option Register and ECC to match Flash page size */
chip->badblock_pattern = &largepage_memorybased;
}
} else {
- dev_err(ctrl->dev,
+ dev_err(priv->dev,
"fsl_elbc_init: page size %d is not supported\n",
mtd->writesize);
return -1;
const uint8_t *buf)
{
struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
fsl_elbc_write_buf(mtd, buf, mtd->writesize);
fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
- ctrl->oob_poi = chip->oob_poi;
+ elbc_fcm_ctrl->oob_poi = chip->oob_poi;
}
static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
{
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
struct nand_chip *chip = &priv->chip;
dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
NAND_USE_FLASH_BBT;
- chip->controller = &ctrl->controller;
+ chip->controller = &elbc_fcm_ctrl->controller;
chip->priv = priv;
chip->ecc.read_page = fsl_elbc_read_page;
static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
{
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
-
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
nand_release(&priv->mtd);
kfree(priv->mtd.name);
if (priv->vbase)
iounmap(priv->vbase);
- ctrl->chips[priv->bank] = NULL;
+ elbc_fcm_ctrl->chips[priv->bank] = NULL;
kfree(priv);
-
+ kfree(elbc_fcm_ctrl);
return 0;
}
-static int __devinit fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
- struct device_node *node)
+static DEFINE_MUTEX(fsl_elbc_nand_mutex);
+
+static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
{
- struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+ struct fsl_lbc_regs __iomem *lbc;
struct fsl_elbc_mtd *priv;
struct resource res;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
+
#ifdef CONFIG_MTD_PARTITIONS
static const char *part_probe_types[]
= { "cmdlinepart", "RedBoot", NULL };
#endif
int ret;
int bank;
+ struct device *dev;
+ struct device_node *node = pdev->dev.of_node;
+
+ if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
+ return -ENODEV;
+ lbc = fsl_lbc_ctrl_dev->regs;
+ dev = fsl_lbc_ctrl_dev->dev;
/* get, allocate and map the memory resource */
ret = of_address_to_resource(node, 0, &res);
if (ret) {
- dev_err(ctrl->dev, "failed to get resource\n");
+ dev_err(dev, "failed to get resource\n");
return ret;
}
(in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
(in_be32(&lbc->bank[bank].br) &
in_be32(&lbc->bank[bank].or) & BR_BA)
- == res.start)
+ == fsl_lbc_addr(res.start))
break;
if (bank >= MAX_BANKS) {
- dev_err(ctrl->dev, "address did not match any chip selects\n");
+ dev_err(dev, "address did not match any chip selects\n");
return -ENODEV;
}
if (!priv)
return -ENOMEM;
- ctrl->chips[bank] = priv;
+ mutex_lock(&fsl_elbc_nand_mutex);
+ if (!fsl_lbc_ctrl_dev->nand) {
+ elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
+ if (!elbc_fcm_ctrl) {
+ dev_err(dev, "failed to allocate memory\n");
+ mutex_unlock(&fsl_elbc_nand_mutex);
+ ret = -ENOMEM;
+ goto err;
+ }
+ elbc_fcm_ctrl->counter++;
+
+ spin_lock_init(&elbc_fcm_ctrl->controller.lock);
+ init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
+ fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
+ } else {
+ elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
+ }
+ mutex_unlock(&fsl_elbc_nand_mutex);
+
+ elbc_fcm_ctrl->chips[bank] = priv;
priv->bank = bank;
- priv->ctrl = ctrl;
- priv->dev = ctrl->dev;
+ priv->ctrl = fsl_lbc_ctrl_dev;
+ priv->dev = dev;
priv->vbase = ioremap(res.start, resource_size(&res));
if (!priv->vbase) {
- dev_err(ctrl->dev, "failed to map chip region\n");
+ dev_err(dev, "failed to map chip region\n");
ret = -ENOMEM;
goto err;
}
return ret;
}
-static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
+static int fsl_elbc_nand_remove(struct platform_device *pdev)
{
- struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
-
- /*
- * NAND transactions can tie up the bus for a long time, so set the
- * bus timeout to max by clearing LBCR[BMT] (highest base counter
- * value) and setting LBCR[BMTPS] to the highest prescaler value.
- */
- clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
-
- /* clear event registers */
- setbits32(&lbc->ltesr, LTESR_NAND_MASK);
- out_be32(&lbc->lteatr, 0);
-
- /* Enable interrupts for any detected events */
- out_be32(&lbc->lteir, LTESR_NAND_MASK);
-
- ctrl->read_bytes = 0;
- ctrl->index = 0;
- ctrl->addr = NULL;
-
- return 0;
-}
-
-static int fsl_elbc_ctrl_remove(struct platform_device *ofdev)
-{
- struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
int i;
-
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
for (i = 0; i < MAX_BANKS; i++)
- if (ctrl->chips[i])
- fsl_elbc_chip_remove(ctrl->chips[i]);
-
- if (ctrl->irq)
- free_irq(ctrl->irq, ctrl);
-
- if (ctrl->regs)
- iounmap(ctrl->regs);
-
- dev_set_drvdata(&ofdev->dev, NULL);
- kfree(ctrl);
- return 0;
-}
-
-/* NOTE: This interrupt is also used to report other localbus events,
- * such as transaction errors on other chipselects. If we want to
- * capture those, we'll need to move the IRQ code into a shared
- * LBC driver.
- */
-
-static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
-{
- struct fsl_elbc_ctrl *ctrl = data;
- struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
- __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
-
- if (status) {
- out_be32(&lbc->ltesr, status);
- out_be32(&lbc->lteatr, 0);
-
- ctrl->irq_status = status;
- smp_wmb();
- wake_up(&ctrl->irq_wait);
-
- return IRQ_HANDLED;
+ if (elbc_fcm_ctrl->chips[i])
+ fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
+
+ mutex_lock(&fsl_elbc_nand_mutex);
+ elbc_fcm_ctrl->counter--;
+ if (!elbc_fcm_ctrl->counter) {
+ fsl_lbc_ctrl_dev->nand = NULL;
+ kfree(elbc_fcm_ctrl);
}
-
- return IRQ_NONE;
-}
-
-/* fsl_elbc_ctrl_probe
- *
- * called by device layer when it finds a device matching
- * one our driver can handled. This code allocates all of
- * the resources needed for the controller only. The
- * resources for the NAND banks themselves are allocated
- * in the chip probe function.
-*/
-
-static int __devinit fsl_elbc_ctrl_probe(struct platform_device *ofdev,
- const struct of_device_id *match)
-{
- struct device_node *child;
- struct fsl_elbc_ctrl *ctrl;
- int ret;
-
- ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
- if (!ctrl)
- return -ENOMEM;
-
- dev_set_drvdata(&ofdev->dev, ctrl);
-
- spin_lock_init(&ctrl->controller.lock);
- init_waitqueue_head(&ctrl->controller.wq);
- init_waitqueue_head(&ctrl->irq_wait);
-
- ctrl->regs = of_iomap(ofdev->dev.of_node, 0);
- if (!ctrl->regs) {
- dev_err(&ofdev->dev, "failed to get memory region\n");
- ret = -ENODEV;
- goto err;
- }
-
- ctrl->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
- if (ctrl->irq == NO_IRQ) {
- dev_err(&ofdev->dev, "failed to get irq resource\n");
- ret = -ENODEV;
- goto err;
- }
-
- ctrl->dev = &ofdev->dev;
-
- ret = fsl_elbc_ctrl_init(ctrl);
- if (ret < 0)
- goto err;
-
- ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
- if (ret != 0) {
- dev_err(&ofdev->dev, "failed to install irq (%d)\n",
- ctrl->irq);
- ret = ctrl->irq;
- goto err;
- }
-
- for_each_child_of_node(ofdev->dev.of_node, child)
- if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
- fsl_elbc_chip_probe(ctrl, child);
+ mutex_unlock(&fsl_elbc_nand_mutex);
return 0;
-err:
- fsl_elbc_ctrl_remove(ofdev);
- return ret;
}
-static const struct of_device_id fsl_elbc_match[] = {
- {
- .compatible = "fsl,elbc",
- },
+static const struct of_device_id fsl_elbc_nand_match[] = {
+ { .compatible = "fsl,elbc-fcm-nand", },
{}
};
-static struct of_platform_driver fsl_elbc_ctrl_driver = {
+static struct platform_driver fsl_elbc_nand_driver = {
.driver = {
- .name = "fsl-elbc",
+ .name = "fsl,elbc-fcm-nand",
.owner = THIS_MODULE,
- .of_match_table = fsl_elbc_match,
+ .of_match_table = fsl_elbc_nand_match,
},
- .probe = fsl_elbc_ctrl_probe,
- .remove = fsl_elbc_ctrl_remove,
+ .probe = fsl_elbc_nand_probe,
+ .remove = fsl_elbc_nand_remove,
};
-static int __init fsl_elbc_init(void)
+static int __init fsl_elbc_nand_init(void)
{
- return of_register_platform_driver(&fsl_elbc_ctrl_driver);
+ return platform_driver_register(&fsl_elbc_nand_driver);
}
-static void __exit fsl_elbc_exit(void)
+static void __exit fsl_elbc_nand_exit(void)
{
- of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
+ platform_driver_unregister(&fsl_elbc_nand_driver);
}
-module_init(fsl_elbc_init);
-module_exit(fsl_elbc_exit);
+module_init(fsl_elbc_nand_init);
+module_exit(fsl_elbc_nand_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Freescale");
if (!flash_np)
return -ENODEV;
- fun->mtd.name = kasprintf(GFP_KERNEL, "%x.%s", io_res->start,
+ fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
flash_np->name);
if (!fun->mtd.name) {
ret = -ENOMEM;
{
struct fsl_upm_nand *fun;
struct resource io_res;
- const uint32_t *prop;
+ const __be32 *prop;
int rnb_gpio;
int ret;
int size;
goto err1;
}
for (i = 0; i < fun->mchip_count; i++)
- fun->mchip_offsets[i] = prop[i];
+ fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
} else {
fun->mchip_count = 1;
}
prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
if (prop)
- fun->chip_delay = *prop;
+ fun->chip_delay = be32_to_cpup(prop);
else
fun->chip_delay = 50;
prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
if (prop && size == sizeof(uint32_t))
- fun->wait_flags = *prop;
+ fun->wait_flags = be32_to_cpup(prop);
else
fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
FSL_UPM_WAIT_WRITE_BYTE;
--- /dev/null
+/*
+ * drivers/mtd/nand/fsmc_nand.c
+ *
+ * ST Microelectronics
+ * Flexible Static Memory Controller (FSMC)
+ * Driver for NAND portions
+ *
+ * Copyright © 2010 ST Microelectronics
+ * Vipin Kumar <vipin.kumar@st.com>
+ * Ashish Priyadarshi
+ *
+ * Based on drivers/mtd/nand/nomadik_nand.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/resource.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mtd/fsmc.h>
+#include <mtd/mtd-abi.h>
+
+static struct nand_ecclayout fsmc_ecc1_layout = {
+ .eccbytes = 24,
+ .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
+ 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
+ .oobfree = {
+ {.offset = 8, .length = 8},
+ {.offset = 24, .length = 8},
+ {.offset = 40, .length = 8},
+ {.offset = 56, .length = 8},
+ {.offset = 72, .length = 8},
+ {.offset = 88, .length = 8},
+ {.offset = 104, .length = 8},
+ {.offset = 120, .length = 8}
+ }
+};
+
+static struct nand_ecclayout fsmc_ecc4_lp_layout = {
+ .eccbytes = 104,
+ .eccpos = { 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14,
+ 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30,
+ 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43, 44, 45, 46,
+ 50, 51, 52, 53, 54, 55, 56,
+ 57, 58, 59, 60, 61, 62,
+ 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78,
+ 82, 83, 84, 85, 86, 87, 88,
+ 89, 90, 91, 92, 93, 94,
+ 98, 99, 100, 101, 102, 103, 104,
+ 105, 106, 107, 108, 109, 110,
+ 114, 115, 116, 117, 118, 119, 120,
+ 121, 122, 123, 124, 125, 126
+ },
+ .oobfree = {
+ {.offset = 15, .length = 3},
+ {.offset = 31, .length = 3},
+ {.offset = 47, .length = 3},
+ {.offset = 63, .length = 3},
+ {.offset = 79, .length = 3},
+ {.offset = 95, .length = 3},
+ {.offset = 111, .length = 3},
+ {.offset = 127, .length = 1}
+ }
+};
+
+/*
+ * ECC placement definitions in oobfree type format.
+ * There are 13 bytes of ecc for every 512 byte block and it has to be read
+ * consecutively and immediately after the 512 byte data block for hardware to
+ * generate the error bit offsets in 512 byte data.
+ * Managing the ecc bytes in the following way makes it easier for software to
+ * read ecc bytes consecutive to data bytes. This way is similar to
+ * oobfree structure maintained already in generic nand driver
+ */
+static struct fsmc_eccplace fsmc_ecc4_lp_place = {
+ .eccplace = {
+ {.offset = 2, .length = 13},
+ {.offset = 18, .length = 13},
+ {.offset = 34, .length = 13},
+ {.offset = 50, .length = 13},
+ {.offset = 66, .length = 13},
+ {.offset = 82, .length = 13},
+ {.offset = 98, .length = 13},
+ {.offset = 114, .length = 13}
+ }
+};
+
+static struct nand_ecclayout fsmc_ecc4_sp_layout = {
+ .eccbytes = 13,
+ .eccpos = { 0, 1, 2, 3, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14
+ },
+ .oobfree = {
+ {.offset = 15, .length = 1},
+ }
+};
+
+static struct fsmc_eccplace fsmc_ecc4_sp_place = {
+ .eccplace = {
+ {.offset = 0, .length = 4},
+ {.offset = 6, .length = 9}
+ }
+};
+
+/*
+ * Default partition tables to be used if the partition information not
+ * provided through platform data
+ */
+#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
+
+/*
+ * Default partition layout for small page(= 512 bytes) devices
+ * Size for "Root file system" is updated in driver based on actual device size
+ */
+static struct mtd_partition partition_info_16KB_blk[] = {
+ PARTITION("X-loader", 0, 4 * 0x4000),
+ PARTITION("U-Boot", 0x10000, 20 * 0x4000),
+ PARTITION("Kernel", 0x60000, 256 * 0x4000),
+ PARTITION("Root File System", 0x460000, 0),
+};
+
+/*
+ * Default partition layout for large page(> 512 bytes) devices
+ * Size for "Root file system" is updated in driver based on actual device size
+ */
+static struct mtd_partition partition_info_128KB_blk[] = {
+ PARTITION("X-loader", 0, 4 * 0x20000),
+ PARTITION("U-Boot", 0x80000, 12 * 0x20000),
+ PARTITION("Kernel", 0x200000, 48 * 0x20000),
+ PARTITION("Root File System", 0x800000, 0),
+};
+
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+const char *part_probes[] = { "cmdlinepart", NULL };
+#endif
+
+/**
+ * struct fsmc_nand_data - atructure for FSMC NAND device state
+ *
+ * @mtd: MTD info for a NAND flash.
+ * @nand: Chip related info for a NAND flash.
+ * @partitions: Partition info for a NAND Flash.
+ * @nr_partitions: Total number of partition of a NAND flash.
+ *
+ * @ecc_place: ECC placing locations in oobfree type format.
+ * @bank: Bank number for probed device.
+ * @clk: Clock structure for FSMC.
+ *
+ * @data_va: NAND port for Data.
+ * @cmd_va: NAND port for Command.
+ * @addr_va: NAND port for Address.
+ * @regs_va: FSMC regs base address.
+ */
+struct fsmc_nand_data {
+ struct mtd_info mtd;
+ struct nand_chip nand;
+ struct mtd_partition *partitions;
+ unsigned int nr_partitions;
+
+ struct fsmc_eccplace *ecc_place;
+ unsigned int bank;
+ struct clk *clk;
+
+ struct resource *resregs;
+ struct resource *rescmd;
+ struct resource *resaddr;
+ struct resource *resdata;
+
+ void __iomem *data_va;
+ void __iomem *cmd_va;
+ void __iomem *addr_va;
+ void __iomem *regs_va;
+
+ void (*select_chip)(uint32_t bank, uint32_t busw);
+};
+
+/* Assert CS signal based on chipnr */
+static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsmc_nand_data *host;
+
+ host = container_of(mtd, struct fsmc_nand_data, mtd);
+
+ switch (chipnr) {
+ case -1:
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+ break;
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ if (host->select_chip)
+ host->select_chip(chipnr,
+ chip->options & NAND_BUSWIDTH_16);
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+/*
+ * fsmc_cmd_ctrl - For facilitaing Hardware access
+ * This routine allows hardware specific access to control-lines(ALE,CLE)
+ */
+static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_regs *regs = host->regs_va;
+ unsigned int bank = host->bank;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_CLE) {
+ this->IO_ADDR_R = (void __iomem *)host->cmd_va;
+ this->IO_ADDR_W = (void __iomem *)host->cmd_va;
+ } else if (ctrl & NAND_ALE) {
+ this->IO_ADDR_R = (void __iomem *)host->addr_va;
+ this->IO_ADDR_W = (void __iomem *)host->addr_va;
+ } else {
+ this->IO_ADDR_R = (void __iomem *)host->data_va;
+ this->IO_ADDR_W = (void __iomem *)host->data_va;
+ }
+
+ if (ctrl & NAND_NCE) {
+ writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
+ ®s->bank_regs[bank].pc);
+ } else {
+ writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
+ ®s->bank_regs[bank].pc);
+ }
+ }
+
+ mb();
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+/*
+ * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
+ *
+ * This routine initializes timing parameters related to NAND memory access in
+ * FSMC registers
+ */
+static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
+ uint32_t busw)
+{
+ uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
+
+ if (busw)
+ writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
+ else
+ writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
+
+ writel(readl(®s->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
+ ®s->bank_regs[bank].pc);
+ writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+ ®s->bank_regs[bank].comm);
+ writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+ ®s->bank_regs[bank].attrib);
+}
+
+/*
+ * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
+ */
+static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_regs *regs = host->regs_va;
+ uint32_t bank = host->bank;
+
+ writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
+ ®s->bank_regs[bank].pc);
+ writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
+ ®s->bank_regs[bank].pc);
+ writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
+ ®s->bank_regs[bank].pc);
+}
+
+/*
+ * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
+ * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction upto
+ * max of 8-bits)
+ */
+static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
+ uint8_t *ecc)
+{
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_regs *regs = host->regs_va;
+ uint32_t bank = host->bank;
+ uint32_t ecc_tmp;
+ unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
+
+ do {
+ if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
+ break;
+ else
+ cond_resched();
+ } while (!time_after_eq(jiffies, deadline));
+
+ ecc_tmp = readl(®s->bank_regs[bank].ecc1);
+ ecc[0] = (uint8_t) (ecc_tmp >> 0);
+ ecc[1] = (uint8_t) (ecc_tmp >> 8);
+ ecc[2] = (uint8_t) (ecc_tmp >> 16);
+ ecc[3] = (uint8_t) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(®s->bank_regs[bank].ecc2);
+ ecc[4] = (uint8_t) (ecc_tmp >> 0);
+ ecc[5] = (uint8_t) (ecc_tmp >> 8);
+ ecc[6] = (uint8_t) (ecc_tmp >> 16);
+ ecc[7] = (uint8_t) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(®s->bank_regs[bank].ecc3);
+ ecc[8] = (uint8_t) (ecc_tmp >> 0);
+ ecc[9] = (uint8_t) (ecc_tmp >> 8);
+ ecc[10] = (uint8_t) (ecc_tmp >> 16);
+ ecc[11] = (uint8_t) (ecc_tmp >> 24);
+
+ ecc_tmp = readl(®s->bank_regs[bank].sts);
+ ecc[12] = (uint8_t) (ecc_tmp >> 16);
+
+ return 0;
+}
+
+/*
+ * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
+ * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction upto
+ * max of 1-bit)
+ */
+static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
+ uint8_t *ecc)
+{
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_regs *regs = host->regs_va;
+ uint32_t bank = host->bank;
+ uint32_t ecc_tmp;
+
+ ecc_tmp = readl(®s->bank_regs[bank].ecc1);
+ ecc[0] = (uint8_t) (ecc_tmp >> 0);
+ ecc[1] = (uint8_t) (ecc_tmp >> 8);
+ ecc[2] = (uint8_t) (ecc_tmp >> 16);
+
+ return 0;
+}
+
+/*
+ * fsmc_read_page_hwecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
+ * performed in a strict sequence as follows:
+ * data(512 byte) -> ecc(13 byte)
+ * After this read, fsmc hardware generates and reports error data bits(upto a
+ * max of 8 bits)
+ */
+static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_eccplace *ecc_place = host->ecc_place;
+ int i, j, s, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ int off, len, group = 0;
+ /*
+ * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
+ * end up reading 14 bytes (7 words) from oob. The local array is
+ * to maintain word alignment
+ */
+ uint16_t ecc_oob[7];
+ uint8_t *oob = (uint8_t *)&ecc_oob[0];
+
+ for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+
+ for (j = 0; j < eccbytes;) {
+ off = ecc_place->eccplace[group].offset;
+ len = ecc_place->eccplace[group].length;
+ group++;
+
+ /*
+ * length is intentionally kept a higher multiple of 2
+ * to read at least 13 bytes even in case of 16 bit NAND
+ * devices
+ */
+ len = roundup(len, 2);
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
+ chip->read_buf(mtd, oob + j, len);
+ j += len;
+ }
+
+ memcpy(&ecc_code[i], oob, 13);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+
+ return 0;
+}
+
+/*
+ * fsmc_correct_data
+ * @mtd: mtd info structure
+ * @dat: buffer of read data
+ * @read_ecc: ecc read from device spare area
+ * @calc_ecc: ecc calculated from read data
+ *
+ * calc_ecc is a 104 bit information containing maximum of 8 error
+ * offset informations of 13 bits each in 512 bytes of read data.
+ */
+static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct fsmc_nand_data *host = container_of(mtd,
+ struct fsmc_nand_data, mtd);
+ struct fsmc_regs *regs = host->regs_va;
+ unsigned int bank = host->bank;
+ uint16_t err_idx[8];
+ uint64_t ecc_data[2];
+ uint32_t num_err, i;
+
+ /* The calculated ecc is actually the correction index in data */
+ memcpy(ecc_data, calc_ecc, 13);
+
+ /*
+ * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
+ * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
+ *
+ * calc_ecc is a 104 bit information containing maximum of 8 error
+ * offset informations of 13 bits each. calc_ecc is copied into a
+ * uint64_t array and error offset indexes are populated in err_idx
+ * array
+ */
+ for (i = 0; i < 8; i++) {
+ if (i == 4) {
+ err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
+ ecc_data[1] >>= 1;
+ continue;
+ }
+ err_idx[i] = (ecc_data[i/4] & 0x1FFF);
+ ecc_data[i/4] >>= 13;
+ }
+
+ num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
+
+ if (num_err == 0xF)
+ return -EBADMSG;
+
+ i = 0;
+ while (num_err--) {
+ change_bit(0, (unsigned long *)&err_idx[i]);
+ change_bit(1, (unsigned long *)&err_idx[i]);
+
+ if (err_idx[i] <= 512 * 8) {
+ change_bit(err_idx[i], (unsigned long *)dat);
+ i++;
+ }
+ }
+ return i;
+}
+
+/*
+ * fsmc_nand_probe - Probe function
+ * @pdev: platform device structure
+ */
+static int __init fsmc_nand_probe(struct platform_device *pdev)
+{
+ struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
+ struct fsmc_nand_data *host;
+ struct mtd_info *mtd;
+ struct nand_chip *nand;
+ struct fsmc_regs *regs;
+ struct resource *res;
+ int nr_parts, ret = 0;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "platform data is NULL\n");
+ return -EINVAL;
+ }
+
+ /* Allocate memory for the device structure (and zero it) */
+ host = kzalloc(sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ dev_err(&pdev->dev, "failed to allocate device structure\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
+ if (!res) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->resdata = request_mem_region(res->start, resource_size(res),
+ pdev->name);
+ if (!host->resdata) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->data_va = ioremap(res->start, resource_size(res));
+ if (!host->data_va) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
+ resource_size(res), pdev->name);
+ if (!host->resaddr) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
+ if (!host->addr_va) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
+ resource_size(res), pdev->name);
+ if (!host->rescmd) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
+ if (!host->cmd_va) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
+ if (!res) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->resregs = request_mem_region(res->start, resource_size(res),
+ pdev->name);
+ if (!host->resregs) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->regs_va = ioremap(res->start, resource_size(res));
+ if (!host->regs_va) {
+ ret = -EIO;
+ goto err_probe1;
+ }
+
+ host->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(host->clk)) {
+ dev_err(&pdev->dev, "failed to fetch block clock\n");
+ ret = PTR_ERR(host->clk);
+ host->clk = NULL;
+ goto err_probe1;
+ }
+
+ ret = clk_enable(host->clk);
+ if (ret)
+ goto err_probe1;
+
+ host->bank = pdata->bank;
+ host->select_chip = pdata->select_bank;
+ regs = host->regs_va;
+
+ /* Link all private pointers */
+ mtd = &host->mtd;
+ nand = &host->nand;
+ mtd->priv = nand;
+ nand->priv = host;
+
+ host->mtd.owner = THIS_MODULE;
+ nand->IO_ADDR_R = host->data_va;
+ nand->IO_ADDR_W = host->data_va;
+ nand->cmd_ctrl = fsmc_cmd_ctrl;
+ nand->chip_delay = 30;
+
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.hwctl = fsmc_enable_hwecc;
+ nand->ecc.size = 512;
+ nand->options = pdata->options;
+ nand->select_chip = fsmc_select_chip;
+
+ if (pdata->width == FSMC_NAND_BW16)
+ nand->options |= NAND_BUSWIDTH_16;
+
+ fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
+
+ if (get_fsmc_version(host->regs_va) == FSMC_VER8) {
+ nand->ecc.read_page = fsmc_read_page_hwecc;
+ nand->ecc.calculate = fsmc_read_hwecc_ecc4;
+ nand->ecc.correct = fsmc_correct_data;
+ nand->ecc.bytes = 13;
+ } else {
+ nand->ecc.calculate = fsmc_read_hwecc_ecc1;
+ nand->ecc.correct = nand_correct_data;
+ nand->ecc.bytes = 3;
+ }
+
+ /*
+ * Scan to find existance of the device
+ */
+ if (nand_scan_ident(&host->mtd, 1, NULL)) {
+ ret = -ENXIO;
+ dev_err(&pdev->dev, "No NAND Device found!\n");
+ goto err_probe;
+ }
+
+ if (get_fsmc_version(host->regs_va) == FSMC_VER8) {
+ if (host->mtd.writesize == 512) {
+ nand->ecc.layout = &fsmc_ecc4_sp_layout;
+ host->ecc_place = &fsmc_ecc4_sp_place;
+ } else {
+ nand->ecc.layout = &fsmc_ecc4_lp_layout;
+ host->ecc_place = &fsmc_ecc4_lp_place;
+ }
+ } else {
+ nand->ecc.layout = &fsmc_ecc1_layout;
+ }
+
+ /* Second stage of scan to fill MTD data-structures */
+ if (nand_scan_tail(&host->mtd)) {
+ ret = -ENXIO;
+ goto err_probe;
+ }
+
+ /*
+ * The partition information can is accessed by (in the same precedence)
+ *
+ * command line through Bootloader,
+ * platform data,
+ * default partition information present in driver.
+ */
+#ifdef CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+ /*
+ * Check if partition info passed via command line
+ */
+ host->mtd.name = "nand";
+ nr_parts = parse_mtd_partitions(&host->mtd, part_probes,
+ &host->partitions, 0);
+ if (nr_parts > 0) {
+ host->nr_partitions = nr_parts;
+ } else {
+#endif
+ /*
+ * Check if partition info passed via command line
+ */
+ if (pdata->partitions) {
+ host->partitions = pdata->partitions;
+ host->nr_partitions = pdata->nr_partitions;
+ } else {
+ struct mtd_partition *partition;
+ int i;
+
+ /* Select the default partitions info */
+ switch (host->mtd.size) {
+ case 0x01000000:
+ case 0x02000000:
+ case 0x04000000:
+ host->partitions = partition_info_16KB_blk;
+ host->nr_partitions =
+ sizeof(partition_info_16KB_blk) /
+ sizeof(struct mtd_partition);
+ break;
+ case 0x08000000:
+ case 0x10000000:
+ case 0x20000000:
+ case 0x40000000:
+ host->partitions = partition_info_128KB_blk;
+ host->nr_partitions =
+ sizeof(partition_info_128KB_blk) /
+ sizeof(struct mtd_partition);
+ break;
+ default:
+ ret = -ENXIO;
+ pr_err("Unsupported NAND size\n");
+ goto err_probe;
+ }
+
+ partition = host->partitions;
+ for (i = 0; i < host->nr_partitions; i++, partition++) {
+ if (partition->size == 0) {
+ partition->size = host->mtd.size -
+ partition->offset;
+ break;
+ }
+ }
+ }
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+ }
+#endif
+
+ if (host->partitions) {
+ ret = add_mtd_partitions(&host->mtd, host->partitions,
+ host->nr_partitions);
+ if (ret)
+ goto err_probe;
+ }
+#else
+ dev_info(&pdev->dev, "Registering %s as whole device\n", mtd->name);
+ if (!add_mtd_device(mtd)) {
+ ret = -ENXIO;
+ goto err_probe;
+ }
+#endif
+
+ platform_set_drvdata(pdev, host);
+ dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
+ return 0;
+
+err_probe:
+ clk_disable(host->clk);
+err_probe1:
+ if (host->clk)
+ clk_put(host->clk);
+ if (host->regs_va)
+ iounmap(host->regs_va);
+ if (host->resregs)
+ release_mem_region(host->resregs->start,
+ resource_size(host->resregs));
+ if (host->cmd_va)
+ iounmap(host->cmd_va);
+ if (host->rescmd)
+ release_mem_region(host->rescmd->start,
+ resource_size(host->rescmd));
+ if (host->addr_va)
+ iounmap(host->addr_va);
+ if (host->resaddr)
+ release_mem_region(host->resaddr->start,
+ resource_size(host->resaddr));
+ if (host->data_va)
+ iounmap(host->data_va);
+ if (host->resdata)
+ release_mem_region(host->resdata->start,
+ resource_size(host->resdata));
+
+ kfree(host);
+ return ret;
+}
+
+/*
+ * Clean up routine
+ */
+static int fsmc_nand_remove(struct platform_device *pdev)
+{
+ struct fsmc_nand_data *host = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+
+ if (host) {
+#ifdef CONFIG_MTD_PARTITIONS
+ del_mtd_partitions(&host->mtd);
+#else
+ del_mtd_device(&host->mtd);
+#endif
+ clk_disable(host->clk);
+ clk_put(host->clk);
+
+ iounmap(host->regs_va);
+ release_mem_region(host->resregs->start,
+ resource_size(host->resregs));
+ iounmap(host->cmd_va);
+ release_mem_region(host->rescmd->start,
+ resource_size(host->rescmd));
+ iounmap(host->addr_va);
+ release_mem_region(host->resaddr->start,
+ resource_size(host->resaddr));
+ iounmap(host->data_va);
+ release_mem_region(host->resdata->start,
+ resource_size(host->resdata));
+
+ kfree(host);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int fsmc_nand_suspend(struct device *dev)
+{
+ struct fsmc_nand_data *host = dev_get_drvdata(dev);
+ if (host)
+ clk_disable(host->clk);
+ return 0;
+}
+
+static int fsmc_nand_resume(struct device *dev)
+{
+ struct fsmc_nand_data *host = dev_get_drvdata(dev);
+ if (host)
+ clk_enable(host->clk);
+ return 0;
+}
+
+static const struct dev_pm_ops fsmc_nand_pm_ops = {
+ .suspend = fsmc_nand_suspend,
+ .resume = fsmc_nand_resume,
+};
+#endif
+
+static struct platform_driver fsmc_nand_driver = {
+ .remove = fsmc_nand_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "fsmc-nand",
+#ifdef CONFIG_PM
+ .pm = &fsmc_nand_pm_ops,
+#endif
+ },
+};
+
+static int __init fsmc_nand_init(void)
+{
+ return platform_driver_probe(&fsmc_nand_driver,
+ fsmc_nand_probe);
+}
+module_init(fsmc_nand_init);
+
+static void __exit fsmc_nand_exit(void)
+{
+ platform_driver_unregister(&fsmc_nand_driver);
+}
+module_exit(fsmc_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
+MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
uint rcw_width;
uint rcwh;
uint romloc, ps;
+ int ret = 0;
rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
if (!rmnode) {
rm = of_iomap(rmnode, 0);
if (!rm) {
dev_err(prv->dev, "Error mapping reset module node!\n");
- return -EBUSY;
+ ret = -EBUSY;
+ goto out;
}
rcwh = in_be32(&rm->rcwhr);
rcw_width * 8, rcw_pagesize,
rcw_sparesize);
iounmap(rm);
+out:
of_node_put(rmnode);
- return 0;
+ return ret;
}
/* Free driver resources */
#endif
struct nand_chip *chip;
unsigned long regs_paddr, regs_size;
- const uint *chips_no;
+ const __be32 *chips_no;
int resettime = 0;
int retval = 0;
int rev, len;
}
/* Detect NAND chips */
- if (nand_scan(mtd, *chips_no)) {
+ if (nand_scan(mtd, be32_to_cpup(chips_no))) {
dev_err(dev, "NAND Flash not found !\n");
devm_free_irq(dev, prv->irq, mtd);
retval = -ENXIO;
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/leds.h>
-#include <asm/io.h>
+#include <linux/io.h>
#ifdef CONFIG_MTD_PARTITIONS
#include <linux/mtd/partitions.h>
{.offset = 3,
.length = 2},
{.offset = 6,
- .length = 2}}
+ .length = 2} }
};
static struct nand_ecclayout nand_oob_16 = {
.eccpos = {0, 1, 2, 3, 6, 7},
.oobfree = {
{.offset = 8,
- . length = 8}}
+ . length = 8} }
};
static struct nand_ecclayout nand_oob_64 = {
56, 57, 58, 59, 60, 61, 62, 63},
.oobfree = {
{.offset = 2,
- .length = 38}}
+ .length = 38} }
};
static struct nand_ecclayout nand_oob_128 = {
120, 121, 122, 123, 124, 125, 126, 127},
.oobfree = {
{.offset = 2,
- .length = 78}}
+ .length = 78} }
};
static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd,
NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+ while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
+ ;
return;
/* This applies to read commands */
NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd, NAND_CMD_NONE,
NAND_NCE | NAND_CTRL_CHANGE);
- while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
+ while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
+ ;
return;
case NAND_CMD_RNDOUT:
spinlock_t *lock = &chip->controller->lock;
wait_queue_head_t *wq = &chip->controller->wq;
DECLARE_WAITQUEUE(wait, current);
- retry:
+retry:
spin_lock(lock);
/* Hardware controller shared among independent devices */
break;
}
mdelay(1);
- }
+ }
}
/**
return ret;
}
+EXPORT_SYMBOL(nand_unlock);
/**
* nand_lock - [REPLACEABLE] locks all blocks present in the device
return ret;
}
+EXPORT_SYMBOL(nand_lock);
/**
* nand_read_page_raw - [Intern] read raw page data without ecc
*
* We need a special oob layout and handling even when OOB isn't used.
*/
-static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int page)
+static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ uint8_t *buf, int page)
{
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
* @readlen: data length
* @bufpoi: buffer to store read data
*/
-static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
+static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
{
int start_step, end_step, num_steps;
uint32_t *eccpos = chip->ecc.layout->eccpos;
int data_col_addr, i, gaps = 0;
int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
+ int index = 0;
/* Column address wihin the page aligned to ECC size (256bytes). */
start_step = data_offs / chip->ecc.size;
} else {
/* send the command to read the particular ecc bytes */
/* take care about buswidth alignment in read_buf */
- aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
+ index = start_step * chip->ecc.bytes;
+
+ aligned_pos = eccpos[index] & ~(busw - 1);
aligned_len = eccfrag_len;
- if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
+ if (eccpos[index] & (busw - 1))
aligned_len++;
- if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
+ if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
aligned_len++;
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
+ mtd->writesize + aligned_pos, -1);
chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
}
for (i = 0; i < eccfrag_len; i++)
- chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
+ chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
p = bufpoi + data_col_addr;
for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
int stat;
- stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
- if (stat == -1)
+ stat = chip->ecc.correct(mtd, p,
+ &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
+ if (stat < 0)
mtd->ecc_stats.failed++;
else
mtd->ecc_stats.corrected += stat;
static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
struct mtd_oob_ops *ops, size_t len)
{
- switch(ops->mode) {
+ switch (ops->mode) {
case MTD_OOB_PLACE:
case MTD_OOB_RAW:
uint32_t boffs = 0, roffs = ops->ooboffs;
size_t bytes = 0;
- for(; free->length && len; free++, len -= bytes) {
+ for (; free->length && len; free++, len -= bytes) {
/* Read request not from offset 0 ? */
if (unlikely(roffs)) {
if (roffs >= free->length) {
buf = ops->datbuf;
oob = ops->oobbuf;
- while(1) {
+ while (1) {
bytes = min(mtd->writesize - col, readlen);
aligned = (bytes == mtd->writesize);
ret = chip->ecc.read_page_raw(mtd, chip,
bufpoi, page);
else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
- ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
+ ret = chip->ecc.read_subpage(mtd, chip,
+ col, bytes, bufpoi);
else
ret = chip->ecc.read_page(mtd, chip, bufpoi,
page);
/* Transfer not aligned data */
if (!aligned) {
- if (!NAND_SUBPAGE_READ(chip) && !oob)
+ if (!NAND_SUBPAGE_READ(chip) && !oob &&
+ !(mtd->ecc_stats.failed - stats.failed))
chip->pagebuf = realpage;
memcpy(buf, chip->buffers->databuf + col, bytes);
}
realpage = (int)(from >> chip->page_shift);
page = realpage & chip->pagemask;
- while(1) {
+ while (1) {
sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
len = min(len, readlen);
nand_get_device(chip, mtd, FL_READING);
- switch(ops->mode) {
+ switch (ops->mode) {
case MTD_OOB_PLACE:
case MTD_OOB_AUTO:
case MTD_OOB_RAW:
else
ret = nand_do_read_ops(mtd, from, ops);
- out:
+out:
nand_release_device(mtd);
return ret;
}
*
* We need a special oob layout and handling even when ECC isn't checked.
*/
-static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf)
+static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ const uint8_t *buf)
{
int eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
struct mtd_oob_ops *ops)
{
- switch(ops->mode) {
+ switch (ops->mode) {
case MTD_OOB_PLACE:
case MTD_OOB_RAW:
uint32_t boffs = 0, woffs = ops->ooboffs;
size_t bytes = 0;
- for(; free->length && len; free++, len -= bytes) {
+ for (; free->length && len; free++, len -= bytes) {
/* Write request not from offset 0 ? */
if (unlikely(woffs)) {
if (woffs >= free->length) {
return NULL;
}
-#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
+#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
/**
* nand_do_write_ops - [Internal] NAND write with ECC
memset(chip->oob_poi, 0xff, mtd->oobsize);
/* Don't allow multipage oob writes with offset */
- if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
+ if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
return -EINVAL;
- while(1) {
+ while (1) {
int bytes = mtd->writesize;
int cached = writelen > bytes && page != blockmask;
uint8_t *wbuf = buf;
nand_get_device(chip, mtd, FL_WRITING);
- switch(ops->mode) {
+ switch (ops->mode) {
case MTD_OOB_PLACE:
case MTD_OOB_AUTO:
case MTD_OOB_RAW:
else
ret = nand_do_write_ops(mtd, to, ops);
- out:
+out:
nand_release_device(mtd);
return ret;
}
{
int page, status, pages_per_block, ret, chipnr;
struct nand_chip *chip = mtd->priv;
- loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
+ loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
unsigned int bbt_masked_page = 0xffffffff;
loff_t len;
}
instr->state = MTD_ERASE_DONE;
- erase_exit:
+erase_exit:
ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
struct nand_chip *chip = mtd->priv;
int ret;
- if ((ret = nand_block_isbad(mtd, ofs))) {
+ ret = nand_block_isbad(mtd, ofs);
+ if (ret) {
/* If it was bad already, return success and do nothing. */
if (ret > 0)
return 0;
}
+/*
+ * sanitize ONFI strings so we can safely print them
+ */
+static void sanitize_string(uint8_t *s, size_t len)
+{
+ ssize_t i;
+
+ /* null terminate */
+ s[len - 1] = 0;
+
+ /* remove non printable chars */
+ for (i = 0; i < len - 1; i++) {
+ if (s[i] < ' ' || s[i] > 127)
+ s[i] = '?';
+ }
+
+ /* remove trailing spaces */
+ strim(s);
+}
+
+static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++ << 8;
+ for (i = 0; i < 8; i++)
+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+ }
+
+ return crc;
+}
+
+/*
+ * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
+ */
+static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
+ int busw)
+{
+ struct nand_onfi_params *p = &chip->onfi_params;
+ int i;
+ int val;
+
+ /* try ONFI for unknow chip or LP */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+ chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
+ return 0;
+
+ printk(KERN_INFO "ONFI flash detected\n");
+ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ for (i = 0; i < 3; i++) {
+ chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
+ le16_to_cpu(p->crc)) {
+ printk(KERN_INFO "ONFI param page %d valid\n", i);
+ break;
+ }
+ }
+
+ if (i == 3)
+ return 0;
+
+ /* check version */
+ val = le16_to_cpu(p->revision);
+ if (val == 1 || val > (1 << 4)) {
+ printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
+ __func__, val);
+ return 0;
+ }
+
+ if (val & (1 << 4))
+ chip->onfi_version = 22;
+ else if (val & (1 << 3))
+ chip->onfi_version = 21;
+ else if (val & (1 << 2))
+ chip->onfi_version = 20;
+ else
+ chip->onfi_version = 10;
+
+ sanitize_string(p->manufacturer, sizeof(p->manufacturer));
+ sanitize_string(p->model, sizeof(p->model));
+ if (!mtd->name)
+ mtd->name = p->model;
+ mtd->writesize = le32_to_cpu(p->byte_per_page);
+ mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
+ mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
+ chip->chipsize = le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
+ busw = 0;
+ if (le16_to_cpu(p->features) & 1)
+ busw = NAND_BUSWIDTH_16;
+
+ chip->options &= ~NAND_CHIPOPTIONS_MSK;
+ chip->options |= (NAND_NO_READRDY |
+ NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
+
+ return 1;
+}
+
/*
* Get the flash and manufacturer id and lookup if the type is supported
*/
static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
struct nand_chip *chip,
- int busw, int *maf_id,
+ int busw,
+ int *maf_id, int *dev_id,
struct nand_flash_dev *type)
{
- int i, dev_id, maf_idx;
+ int i, maf_idx;
u8 id_data[8];
+ int ret;
/* Select the device */
chip->select_chip(mtd, 0);
/* Read manufacturer and device IDs */
*maf_id = chip->read_byte(mtd);
- dev_id = chip->read_byte(mtd);
+ *dev_id = chip->read_byte(mtd);
/* Try again to make sure, as some systems the bus-hold or other
* interface concerns can cause random data which looks like a
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
- /* Read entire ID string */
-
- for (i = 0; i < 8; i++)
+ for (i = 0; i < 2; i++)
id_data[i] = chip->read_byte(mtd);
- if (id_data[0] != *maf_id || id_data[1] != dev_id) {
+ if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
printk(KERN_INFO "%s: second ID read did not match "
"%02x,%02x against %02x,%02x\n", __func__,
- *maf_id, dev_id, id_data[0], id_data[1]);
+ *maf_id, *dev_id, id_data[0], id_data[1]);
return ERR_PTR(-ENODEV);
}
type = nand_flash_ids;
for (; type->name != NULL; type++)
- if (dev_id == type->id)
- break;
+ if (*dev_id == type->id)
+ break;
+
+ chip->onfi_version = 0;
+ if (!type->name || !type->pagesize) {
+ /* Check is chip is ONFI compliant */
+ ret = nand_flash_detect_onfi(mtd, chip, busw);
+ if (ret)
+ goto ident_done;
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read entire ID string */
+
+ for (i = 0; i < 8; i++)
+ id_data[i] = chip->read_byte(mtd);
if (!type->name)
return ERR_PTR(-ENODEV);
chip->chipsize = (uint64_t)type->chipsize << 20;
- /* Newer devices have all the information in additional id bytes */
- if (!type->pagesize) {
+ if (!type->pagesize && chip->init_size) {
+ /* set the pagesize, oobsize, erasesize by the driver*/
+ busw = chip->init_size(mtd, chip, id_data);
+ } else if (!type->pagesize) {
int extid;
/* The 3rd id byte holds MLC / multichip data */
chip->cellinfo = id_data[2];
/*
* Field definitions are in the following datasheets:
* Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
- * New style (6 byte ID): Samsung K9GAG08U0D (p.40)
+ * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
*
* Check for wraparound + Samsung ID + nonzero 6th byte
* to decide what to do.
mtd->writesize = 2048 << (extid & 0x03);
extid >>= 2;
/* Calc oobsize */
- mtd->oobsize = (extid & 0x03) == 0x01 ? 128 : 218;
+ switch (extid & 0x03) {
+ case 1:
+ mtd->oobsize = 128;
+ break;
+ case 2:
+ mtd->oobsize = 218;
+ break;
+ case 3:
+ mtd->oobsize = 400;
+ break;
+ default:
+ mtd->oobsize = 436;
+ break;
+ }
extid >>= 2;
/* Calc blocksize */
mtd->erasesize = (128 * 1024) <<
mtd->writesize = type->pagesize;
mtd->oobsize = mtd->writesize / 32;
busw = type->options & NAND_BUSWIDTH_16;
+
+ /*
+ * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+ * some Spansion chips have erasesize that conflicts with size
+ * listed in nand_ids table
+ * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
+ */
+ if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
+ id_data[5] == 0x00 && id_data[6] == 0x00 &&
+ id_data[7] == 0x00 && mtd->writesize == 512) {
+ mtd->erasesize = 128 * 1024;
+ mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
+ }
}
+ /* Get chip options, preserve non chip based options */
+ chip->options &= ~NAND_CHIPOPTIONS_MSK;
+ chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
+
+ /* Check if chip is a not a samsung device. Do not clear the
+ * options for chips which are not having an extended id.
+ */
+ if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
+ chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
+ident_done:
+
+ /*
+ * Set chip as a default. Board drivers can override it, if necessary
+ */
+ chip->options |= NAND_NO_AUTOINCR;
/* Try to identify manufacturer */
for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
if (busw != (chip->options & NAND_BUSWIDTH_16)) {
printk(KERN_INFO "NAND device: Manufacturer ID:"
" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
- dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
+ *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
(chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
busw ? 16 : 8);
ffs(mtd->erasesize) - 1;
if (chip->chipsize & 0xffffffff)
chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
- else
- chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
+ else {
+ chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
+ chip->chip_shift += 32 - 1;
+ }
/* Set the bad block position */
if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
else
chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
- /* Get chip options, preserve non chip based options */
- chip->options &= ~NAND_CHIPOPTIONS_MSK;
- chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
-
- /*
- * Set chip as a default. Board drivers can override it, if necessary
- */
- chip->options |= NAND_NO_AUTOINCR;
-
- /* Check if chip is a not a samsung device. Do not clear the
- * options for chips which are not having an extended id.
- */
- if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
- chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
-
/*
* Bad block marker is stored in the last page of each block
* on Samsung and Hynix MLC devices; stored in first two pages
* of each block on Micron devices with 2KiB pages and on
- * SLC Samsung, Hynix, and AMD/Spansion. All others scan only
- * the first page.
+ * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
+ * only the first page.
*/
if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
(*maf_id == NAND_MFR_SAMSUNG ||
else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
(*maf_id == NAND_MFR_SAMSUNG ||
*maf_id == NAND_MFR_HYNIX ||
+ *maf_id == NAND_MFR_TOSHIBA ||
*maf_id == NAND_MFR_AMD)) ||
(mtd->writesize == 2048 &&
*maf_id == NAND_MFR_MICRON))
if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
chip->cmdfunc = nand_command_lp;
+ /* TODO onfi flash name */
printk(KERN_INFO "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
- nand_manuf_ids[maf_idx].name, type->name);
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
+ nand_manuf_ids[maf_idx].name,
+ chip->onfi_version ? type->name : chip->onfi_params.model);
return type;
}
int nand_scan_ident(struct mtd_info *mtd, int maxchips,
struct nand_flash_dev *table)
{
- int i, busw, nand_maf_id;
+ int i, busw, nand_maf_id, nand_dev_id;
struct nand_chip *chip = mtd->priv;
struct nand_flash_dev *type;
nand_set_defaults(chip, busw);
/* Read the flash type */
- type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table);
+ type = nand_get_flash_type(mtd, chip, busw,
+ &nand_maf_id, &nand_dev_id, table);
if (IS_ERR(type)) {
if (!(chip->options & NAND_SCAN_SILENT_NODEV))
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
/* Read manufacturer and device IDs */
if (nand_maf_id != chip->read_byte(mtd) ||
- type->id != chip->read_byte(mtd))
+ nand_dev_id != chip->read_byte(mtd))
break;
}
if (i > 1)
return 0;
}
+EXPORT_SYMBOL(nand_scan_ident);
/**
* mode
*/
chip->ecc.steps = mtd->writesize / chip->ecc.size;
- if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
+ if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
printk(KERN_WARNING "Invalid ecc parameters\n");
BUG();
}
*/
if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
!(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
- switch(chip->ecc.steps) {
+ switch (chip->ecc.steps) {
case 2:
mtd->subpage_sft = 1;
break;
/* Build bad block table */
return chip->scan_bbt(mtd);
}
+EXPORT_SYMBOL(nand_scan_tail);
/* is_module_text_address() isn't exported, and it's mostly a pointless
- test if this is a module _anyway_ -- they'd have to try _really_ hard
- to call us from in-kernel code if the core NAND support is modular. */
+ * test if this is a module _anyway_ -- they'd have to try _really_ hard
+ * to call us from in-kernel code if the core NAND support is modular. */
#ifdef MODULE
#define caller_is_module() (1)
#else
ret = nand_scan_tail(mtd);
return ret;
}
+EXPORT_SYMBOL(nand_scan);
/**
* nand_release - [NAND Interface] Free resources held by the NAND device
& NAND_BBT_DYNAMICSTRUCT)
kfree(chip->badblock_pattern);
}
-
-EXPORT_SYMBOL_GPL(nand_lock);
-EXPORT_SYMBOL_GPL(nand_unlock);
-EXPORT_SYMBOL_GPL(nand_scan);
-EXPORT_SYMBOL_GPL(nand_scan_ident);
-EXPORT_SYMBOL_GPL(nand_scan_tail);
EXPORT_SYMBOL_GPL(nand_release);
static int __init nand_base_init(void)
module_exit(nand_base_exit);
MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
+MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
+MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
MODULE_DESCRIPTION("Generic NAND flash driver code");
* Description:
*
* When nand_scan_bbt is called, then it tries to find the bad block table
- * depending on the options in the bbt descriptor(s). If a bbt is found
- * then the contents are read and the memory based bbt is created. If a
- * mirrored bbt is selected then the mirror is searched too and the
- * versions are compared. If the mirror has a greater version number
- * than the mirror bbt is used to build the memory based bbt.
+ * depending on the options in the BBT descriptor(s). If no flash based BBT
+ * (NAND_USE_FLASH_BBT) is specified then the device is scanned for factory
+ * marked good / bad blocks. This information is used to create a memory BBT.
+ * Once a new bad block is discovered then the "factory" information is updated
+ * on the device.
+ * If a flash based BBT is specified then the function first tries to find the
+ * BBT on flash. If a BBT is found then the contents are read and the memory
+ * based BBT is created. If a mirrored BBT is selected then the mirror is
+ * searched too and the versions are compared. If the mirror has a greater
+ * version number than the mirror BBT is used to build the memory based BBT.
* If the tables are not versioned, then we "or" the bad block information.
- * If one of the bbt's is out of date or does not exist it is (re)created.
- * If no bbt exists at all then the device is scanned for factory marked
+ * If one of the BBTs is out of date or does not exist it is (re)created.
+ * If no BBT exists at all then the device is scanned for factory marked
* good / bad blocks and the bad block tables are created.
*
- * For manufacturer created bbts like the one found on M-SYS DOC devices
- * the bbt is searched and read but never created
+ * For manufacturer created BBTs like the one found on M-SYS DOC devices
+ * the BBT is searched and read but never created
*
- * The autogenerated bad block table is located in the last good blocks
+ * The auto generated bad block table is located in the last good blocks
* of the device. The table is mirrored, so it can be updated eventually.
- * The table is marked in the oob area with an ident pattern and a version
- * number which indicates which of both tables is more up to date.
+ * The table is marked in the OOB area with an ident pattern and a version
+ * number which indicates which of both tables is more up to date. If the NAND
+ * controller needs the complete OOB area for the ECC information then the
+ * option NAND_USE_FLASH_BBT_NO_OOB should be used: it moves the ident pattern
+ * and the version byte into the data area and the OOB area will remain
+ * untouched.
*
* The table uses 2 bits per block
- * 11b: block is good
- * 00b: block is factory marked bad
- * 01b, 10b: block is marked bad due to wear
+ * 11b: block is good
+ * 00b: block is factory marked bad
+ * 01b, 10b: block is marked bad due to wear
*
* The memory bad block table uses the following scheme:
* 00b: block is good
#include <linux/delay.h>
#include <linux/vmalloc.h>
+static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td)
+{
+ int ret;
+
+ ret = memcmp(buf, td->pattern, td->len);
+ if (!ret)
+ return ret;
+ return -1;
+}
+
/**
* check_pattern - [GENERIC] check if a pattern is in the buffer
* @buf: the buffer to search
int i, end = 0;
uint8_t *p = buf;
+ if (td->options & NAND_BBT_NO_OOB)
+ return check_pattern_no_oob(buf, td);
+
end = paglen + td->offs;
if (td->options & NAND_BBT_SCANEMPTY) {
for (i = 0; i < end; i++) {
return 0;
}
+/**
+ * add_marker_len - compute the length of the marker in data area
+ * @td: BBT descriptor used for computation
+ *
+ * The length will be 0 if the markeris located in OOB area.
+ */
+static u32 add_marker_len(struct nand_bbt_descr *td)
+{
+ u32 len;
+
+ if (!(td->options & NAND_BBT_NO_OOB))
+ return 0;
+
+ len = td->len;
+ if (td->options & NAND_BBT_VERSION)
+ len++;
+ return len;
+}
+
/**
* read_bbt - [GENERIC] Read the bad block table starting from page
* @mtd: MTD device structure
* @buf: temporary buffer
* @page: the starting page
* @num: the number of bbt descriptors to read
- * @bits: number of bits per block
+ * @td: the bbt describtion table
* @offs: offset in the memory table
- * @reserved_block_code: Pattern to identify reserved blocks
*
* Read the bad block table starting from page.
*
*/
static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
- int bits, int offs, int reserved_block_code)
+ struct nand_bbt_descr *td, int offs)
{
int res, i, j, act = 0;
struct nand_chip *this = mtd->priv;
size_t retlen, len, totlen;
loff_t from;
+ int bits = td->options & NAND_BBT_NRBITS_MSK;
uint8_t msk = (uint8_t) ((1 << bits) - 1);
+ u32 marker_len;
+ int reserved_block_code = td->reserved_block_code;
totlen = (num * bits) >> 3;
+ marker_len = add_marker_len(td);
from = ((loff_t) page) << this->page_shift;
while (totlen) {
len = min(totlen, (size_t) (1 << this->bbt_erase_shift));
+ if (marker_len) {
+ /*
+ * In case the BBT marker is not in the OOB area it
+ * will be just in the first page.
+ */
+ len -= marker_len;
+ from += marker_len;
+ marker_len = 0;
+ }
res = mtd->read(mtd, from, len, &retlen, buf);
if (res < 0) {
if (retlen != len) {
{
struct nand_chip *this = mtd->priv;
int res = 0, i;
- int bits;
- bits = td->options & NAND_BBT_NRBITS_MSK;
if (td->options & NAND_BBT_PERCHIP) {
int offs = 0;
for (i = 0; i < this->numchips; i++) {
if (chip == -1 || chip == i)
- res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code);
+ res = read_bbt(mtd, buf, td->pages[i],
+ this->chipsize >> this->bbt_erase_shift,
+ td, offs);
if (res)
return res;
offs += this->chipsize >> (this->bbt_erase_shift + 2);
}
} else {
- res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code);
+ res = read_bbt(mtd, buf, td->pages[0],
+ mtd->size >> this->bbt_erase_shift, td, 0);
if (res)
return res;
}
return 0;
}
+/*
+ * BBT marker is in the first page, no OOB.
+ */
+static int scan_read_raw_data(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+ struct nand_bbt_descr *td)
+{
+ size_t retlen;
+ size_t len;
+
+ len = td->len;
+ if (td->options & NAND_BBT_VERSION)
+ len++;
+
+ return mtd->read(mtd, offs, len, &retlen, buf);
+}
+
/*
* Scan read raw data from flash
*/
-static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+static int scan_read_raw_oob(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
size_t len)
{
struct mtd_oob_ops ops;
return 0;
}
+static int scan_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t offs,
+ size_t len, struct nand_bbt_descr *td)
+{
+ if (td->options & NAND_BBT_NO_OOB)
+ return scan_read_raw_data(mtd, buf, offs, td);
+ else
+ return scan_read_raw_oob(mtd, buf, offs, len);
+}
+
/*
* Scan write data with oob to flash
*/
return mtd->write_oob(mtd, offs, &ops);
}
+static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td)
+{
+ u32 ver_offs = td->veroffs;
+
+ if (!(td->options & NAND_BBT_NO_OOB))
+ ver_offs += mtd->writesize;
+ return ver_offs;
+}
+
/**
* read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page
* @mtd: MTD device structure
/* Read the primary version, if available */
if (td->options & NAND_BBT_VERSION) {
scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
- mtd->writesize);
- td->version[0] = buf[mtd->writesize + td->veroffs];
+ mtd->writesize, td);
+ td->version[0] = buf[bbt_get_ver_offs(mtd, td)];
printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
td->pages[0], td->version[0]);
}
/* Read the mirror version, if available */
if (md && (md->options & NAND_BBT_VERSION)) {
scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
- mtd->writesize);
- md->version[0] = buf[mtd->writesize + md->veroffs];
+ mtd->writesize, td);
+ md->version[0] = buf[bbt_get_ver_offs(mtd, md)];
printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
md->pages[0], md->version[0]);
}
{
int ret, j;
- ret = scan_read_raw(mtd, buf, offs, readlen);
+ ret = scan_read_raw_oob(mtd, buf, offs, readlen);
if (ret)
return ret;
for (i = startblock; i < numblocks;) {
int ret;
+ BUG_ON(bd->options & NAND_BBT_NO_OOB);
+
if (bd->options & NAND_BBT_SCANALLPAGES)
ret = scan_block_full(mtd, bd, from, buf, readlen,
scanlen, len);
loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
/* Read first page */
- scan_read_raw(mtd, buf, offs, mtd->writesize);
+ scan_read_raw(mtd, buf, offs, mtd->writesize, td);
if (!check_pattern(buf, scanlen, mtd->writesize, td)) {
td->pages[i] = actblock << blocktopage;
if (td->options & NAND_BBT_VERSION) {
- td->version[i] = buf[mtd->writesize + td->veroffs];
+ offs = bbt_get_ver_offs(mtd, td);
+ td->version[i] = buf[offs];
}
break;
}
memset(&buf[offs], 0xff, (size_t) (numblocks >> sft));
ooboffs = len + (pageoffs * mtd->oobsize);
+ } else if (td->options & NAND_BBT_NO_OOB) {
+ ooboffs = 0;
+ offs = td->len;
+ /* the version byte */
+ if (td->options & NAND_BBT_VERSION)
+ offs++;
+ /* Calc length */
+ len = (size_t) (numblocks >> sft);
+ len += offs;
+ /* Make it page aligned ! */
+ len = ALIGN(len, mtd->writesize);
+ /* Preset the buffer with 0xff */
+ memset(buf, 0xff, len);
+ /* Pattern is located at the begin of first page */
+ memcpy(buf, td->pattern, td->len);
} else {
/* Calc length */
len = (size_t) (numblocks >> sft);
/* Make it page aligned ! */
- len = (len + (mtd->writesize - 1)) &
- ~(mtd->writesize - 1);
+ len = ALIGN(len, mtd->writesize);
/* Preset the buffer with 0xff */
memset(buf, 0xff, len +
(len >> this->page_shift)* mtd->oobsize);
if (res < 0)
goto outerr;
- res = scan_write_bbt(mtd, to, len, buf, &buf[len]);
+ res = scan_write_bbt(mtd, to, len, buf,
+ td->options & NAND_BBT_NO_OOB ? NULL :
+ &buf[len]);
if (res < 0)
goto outerr;
continue;
/* Create the table in memory by scanning the chip(s) */
- create_bbt(mtd, buf, bd, chipsel);
+ if (!(this->options & NAND_CREATE_EMPTY_BBT))
+ create_bbt(mtd, buf, bd, chipsel);
td->version[i] = 1;
if (md)
}
}
+/**
+ * verify_bbt_descr - verify the bad block description
+ * @bd: the table to verify
+ *
+ * This functions performs a few sanity checks on the bad block description
+ * table.
+ */
+static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+ struct nand_chip *this = mtd->priv;
+ u32 pattern_len = bd->len;
+ u32 bits = bd->options & NAND_BBT_NRBITS_MSK;
+ u32 table_size;
+
+ if (!bd)
+ return;
+ BUG_ON((this->options & NAND_USE_FLASH_BBT_NO_OOB) &&
+ !(this->options & NAND_USE_FLASH_BBT));
+ BUG_ON(!bits);
+
+ if (bd->options & NAND_BBT_VERSION)
+ pattern_len++;
+
+ if (bd->options & NAND_BBT_NO_OOB) {
+ BUG_ON(!(this->options & NAND_USE_FLASH_BBT));
+ BUG_ON(!(this->options & NAND_USE_FLASH_BBT_NO_OOB));
+ BUG_ON(bd->offs);
+ if (bd->options & NAND_BBT_VERSION)
+ BUG_ON(bd->veroffs != bd->len);
+ BUG_ON(bd->options & NAND_BBT_SAVECONTENT);
+ }
+
+ if (bd->options & NAND_BBT_PERCHIP)
+ table_size = this->chipsize >> this->bbt_erase_shift;
+ else
+ table_size = mtd->size >> this->bbt_erase_shift;
+ table_size >>= 3;
+ table_size *= bits;
+ if (bd->options & NAND_BBT_NO_OOB)
+ table_size += pattern_len;
+ BUG_ON(table_size > (1 << this->bbt_erase_shift));
+}
+
/**
* nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s)
* @mtd: MTD device structure
}
return res;
}
+ verify_bbt_descr(mtd, td);
+ verify_bbt_descr(mtd, md);
/* Allocate a temporary buffer for one eraseblock incl. oob */
len = (1 << this->bbt_erase_shift);
.pattern = mirror_pattern
};
+static struct nand_bbt_descr bbt_main_no_bbt_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
+ | NAND_BBT_NO_OOB,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_no_bbt_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+ | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP
+ | NAND_BBT_NO_OOB,
+ .len = 4,
+ .veroffs = 4,
+ .maxblocks = 4,
+ .pattern = mirror_pattern
+};
+
#define BBT_SCAN_OPTIONS (NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE | \
NAND_BBT_SCANBYTE1AND6)
/**
if (this->options & NAND_USE_FLASH_BBT) {
/* Use the default pattern descriptors */
if (!this->bbt_td) {
- this->bbt_td = &bbt_main_descr;
- this->bbt_md = &bbt_mirror_descr;
+ if (this->options & NAND_USE_FLASH_BBT_NO_OOB) {
+ this->bbt_td = &bbt_main_no_bbt_descr;
+ this->bbt_md = &bbt_mirror_no_bbt_descr;
+ } else {
+ this->bbt_td = &bbt_main_descr;
+ this->bbt_md = &bbt_mirror_descr;
+ }
}
if (!this->badblock_pattern) {
this->badblock_pattern = (mtd->writesize > 512) ? &largepage_flashbased : &smallpage_flashbased;
/*512 Megabit */
{"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
+ {"NAND 64MiB 1,8V 8-bit", 0xA0, 0, 64, 0, LP_OPTIONS},
{"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
+ {"NAND 64MiB 3,3V 8-bit", 0xD0, 0, 64, 0, LP_OPTIONS},
{"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
+ {"NAND 64MiB 1,8V 16-bit", 0xB0, 0, 64, 0, LP_OPTIONS16},
{"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
+ {"NAND 64MiB 3,3V 16-bit", 0xC0, 0, 64, 0, LP_OPTIONS16},
/* 1 Gigabit */
{"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
{"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
/* 32 Gigabit */
+ {"NAND 4GiB 1,8V 8-bit", 0xA7, 0, 4096, 0, LP_OPTIONS},
{"NAND 4GiB 3,3V 8-bit", 0xD7, 0, 4096, 0, LP_OPTIONS},
+ {"NAND 4GiB 1,8V 16-bit", 0xB7, 0, 4096, 0, LP_OPTIONS16},
+ {"NAND 4GiB 3,3V 16-bit", 0xC7, 0, 4096, 0, LP_OPTIONS16},
+
+ /* 64 Gigabit */
+ {"NAND 8GiB 1,8V 8-bit", 0xAE, 0, 8192, 0, LP_OPTIONS},
+ {"NAND 8GiB 3,3V 8-bit", 0xDE, 0, 8192, 0, LP_OPTIONS},
+ {"NAND 8GiB 1,8V 16-bit", 0xBE, 0, 8192, 0, LP_OPTIONS16},
+ {"NAND 8GiB 3,3V 16-bit", 0xCE, 0, 8192, 0, LP_OPTIONS16},
+
+ /* 128 Gigabit */
+ {"NAND 16GiB 1,8V 8-bit", 0x1A, 0, 16384, 0, LP_OPTIONS},
+ {"NAND 16GiB 3,3V 8-bit", 0x3A, 0, 16384, 0, LP_OPTIONS},
+ {"NAND 16GiB 1,8V 16-bit", 0x2A, 0, 16384, 0, LP_OPTIONS16},
+ {"NAND 16GiB 3,3V 16-bit", 0x4A, 0, 16384, 0, LP_OPTIONS16},
+
+ /* 256 Gigabit */
+ {"NAND 32GiB 1,8V 8-bit", 0x1C, 0, 32768, 0, LP_OPTIONS},
+ {"NAND 32GiB 3,3V 8-bit", 0x3C, 0, 32768, 0, LP_OPTIONS},
+ {"NAND 32GiB 1,8V 16-bit", 0x2C, 0, 32768, 0, LP_OPTIONS16},
+ {"NAND 32GiB 3,3V 16-bit", 0x4C, 0, 32768, 0, LP_OPTIONS16},
+
+ /* 512 Gigabit */
+ {"NAND 64GiB 1,8V 8-bit", 0x1E, 0, 65536, 0, LP_OPTIONS},
+ {"NAND 64GiB 3,3V 8-bit", 0x3E, 0, 65536, 0, LP_OPTIONS},
+ {"NAND 64GiB 1,8V 16-bit", 0x2E, 0, 65536, 0, LP_OPTIONS16},
+ {"NAND 64GiB 3,3V 16-bit", 0x4E, 0, 65536, 0, LP_OPTIONS16},
/*
* Renesas AND 1 Gigabit. Those chips do not support extended id and
static unsigned int rptwear = 0;
static unsigned int overridesize = 0;
static char *cache_file = NULL;
+static unsigned int bbt;
module_param(first_id_byte, uint, 0400);
module_param(second_id_byte, uint, 0400);
module_param(rptwear, uint, 0400);
module_param(overridesize, uint, 0400);
module_param(cache_file, charp, 0400);
+module_param(bbt, uint, 0400);
MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
"The size is specified in erase blocks and as the exponent of a power of two"
" e.g. 5 means a size of 32 erase blocks");
MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
+MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
/* The largest possible page size */
#define NS_LARGEST_PAGE_SIZE 4096
/* and 'badblocks' parameters to work */
chip->options |= NAND_SKIP_BBTSCAN;
+ switch (bbt) {
+ case 2:
+ chip->options |= NAND_USE_FLASH_BBT_NO_OOB;
+ case 1:
+ chip->options |= NAND_USE_FLASH_BBT;
+ case 0:
+ break;
+ default:
+ NS_ERR("bbt has to be 0..2\n");
+ retval = -EINVAL;
+ goto error;
+ }
/*
* Perform minimum nandsim structure initialization to handle
* the initial ID read command correctly
if ((retval = init_nandsim(nsmtd)) != 0)
goto err_exit;
- if ((retval = parse_badblocks(nand, nsmtd)) != 0)
+ if ((retval = nand_default_bbt(nsmtd)) != 0)
goto err_exit;
- if ((retval = nand_default_bbt(nsmtd)) != 0)
+ if ((retval = parse_badblocks(nand, nsmtd)) != 0)
goto err_exit;
/* Register NAND partitions */
const struct of_device_id *match)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
- const u32 *reg;
+ const __be32 *reg;
u32 ccr;
int err, len;
dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
return -ENOENT;
}
- ndfc->chip_select = reg[0];
+ ndfc->chip_select = be32_to_cpu(reg[0]);
ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
if (!ndfc->ndfcbase) {
/* It is ok if ccr does not exist - just default to 0 */
reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
if (reg)
- ccr |= *reg;
+ ccr |= be32_to_cpup(reg);
out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
if (reg) {
int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
- out_be32(ndfc->ndfcbase + offset, *reg);
+ out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
}
err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
module_param(use_dma, bool, 0);
MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
#else
-const int use_dma;
+static const int use_dma;
#endif
#else
const int use_prefetch;
-const int use_dma;
+static const int use_dma;
#endif
struct omap_nand_info {
struct nand_chip nand_chip;
struct platform_device *pdev;
- const struct pxa3xx_nand_flash *flash_info;
+ struct pxa3xx_nand_cmdset *cmdset;
struct clk *clk;
void __iomem *mmio_base;
int drcmr_cmd;
unsigned char *data_buff;
+ unsigned char *oob_buff;
dma_addr_t data_buff_phys;
size_t data_buff_size;
int data_dma_ch;
int use_ecc; /* use HW ECC ? */
int use_dma; /* use DMA ? */
- size_t data_size; /* data size in FIFO */
+ unsigned int page_size; /* page size of attached chip */
+ unsigned int data_size; /* data size in FIFO */
int retcode;
struct completion cmd_complete;
uint32_t ndcb1;
uint32_t ndcb2;
+ /* timing calcuted from setting */
+ uint32_t ndtr0cs0;
+ uint32_t ndtr1cs0;
+
/* calculated from pxa3xx_nand_flash data */
size_t oob_size;
size_t read_id_bytes;
* Default NAND flash controller configuration setup by the
* bootloader. This configuration is used only when pdata->keep_config is set
*/
-static struct pxa3xx_nand_timing default_timing;
-static struct pxa3xx_nand_flash default_flash;
-
-static struct pxa3xx_nand_cmdset smallpage_cmdset = {
- .read1 = 0x0000,
- .read2 = 0x0050,
- .program = 0x1080,
- .read_status = 0x0070,
- .read_id = 0x0090,
- .erase = 0xD060,
- .reset = 0x00FF,
- .lock = 0x002A,
- .unlock = 0x2423,
- .lock_status = 0x007A,
-};
-
-static struct pxa3xx_nand_cmdset largepage_cmdset = {
+static struct pxa3xx_nand_cmdset default_cmdset = {
.read1 = 0x3000,
.read2 = 0x0050,
.program = 0x1080,
.lock_status = 0x007A,
};
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
-static struct pxa3xx_nand_timing samsung512MbX16_timing = {
- .tCH = 10,
- .tCS = 0,
- .tWH = 20,
- .tWP = 40,
- .tRH = 30,
- .tRP = 40,
- .tR = 11123,
- .tWHR = 110,
- .tAR = 10,
-};
-
-static struct pxa3xx_nand_flash samsung512MbX16 = {
- .timing = &samsung512MbX16_timing,
- .cmdset = &smallpage_cmdset,
- .page_per_block = 32,
- .page_size = 512,
- .flash_width = 16,
- .dfc_width = 16,
- .num_blocks = 4096,
- .chip_id = 0x46ec,
-};
-
-static struct pxa3xx_nand_flash samsung2GbX8 = {
- .timing = &samsung512MbX16_timing,
- .cmdset = &smallpage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 8,
- .dfc_width = 8,
- .num_blocks = 2048,
- .chip_id = 0xdaec,
+static struct pxa3xx_nand_timing timing[] = {
+ { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
+ { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
+ { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
+ { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
};
-static struct pxa3xx_nand_flash samsung32GbX8 = {
- .timing = &samsung512MbX16_timing,
- .cmdset = &smallpage_cmdset,
- .page_per_block = 128,
- .page_size = 4096,
- .flash_width = 8,
- .dfc_width = 8,
- .num_blocks = 8192,
- .chip_id = 0xd7ec,
+static struct pxa3xx_nand_flash builtin_flash_types[] = {
+ { 0, 0, 2048, 8, 8, 0, &default_cmdset, &timing[0] },
+ { 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[1] },
+ { 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[1] },
+ { 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[1] },
+ { 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[2] },
+ { 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
+ { 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[2] },
+ { 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
+ { 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
};
-static struct pxa3xx_nand_timing micron_timing = {
- .tCH = 10,
- .tCS = 25,
- .tWH = 15,
- .tWP = 25,
- .tRH = 15,
- .tRP = 30,
- .tR = 25000,
- .tWHR = 60,
- .tAR = 10,
-};
-
-static struct pxa3xx_nand_flash micron1GbX8 = {
- .timing = µn_timing,
- .cmdset = &largepage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 8,
- .dfc_width = 8,
- .num_blocks = 1024,
- .chip_id = 0xa12c,
-};
-
-static struct pxa3xx_nand_flash micron1GbX16 = {
- .timing = µn_timing,
- .cmdset = &largepage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 16,
- .dfc_width = 16,
- .num_blocks = 1024,
- .chip_id = 0xb12c,
-};
-
-static struct pxa3xx_nand_flash micron4GbX8 = {
- .timing = µn_timing,
- .cmdset = &largepage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 8,
- .dfc_width = 8,
- .num_blocks = 4096,
- .chip_id = 0xdc2c,
-};
-
-static struct pxa3xx_nand_flash micron4GbX16 = {
- .timing = µn_timing,
- .cmdset = &largepage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 16,
- .dfc_width = 16,
- .num_blocks = 4096,
- .chip_id = 0xcc2c,
-};
-
-static struct pxa3xx_nand_timing stm2GbX16_timing = {
- .tCH = 10,
- .tCS = 35,
- .tWH = 15,
- .tWP = 25,
- .tRH = 15,
- .tRP = 25,
- .tR = 25000,
- .tWHR = 60,
- .tAR = 10,
-};
-
-static struct pxa3xx_nand_flash stm2GbX16 = {
- .timing = &stm2GbX16_timing,
- .cmdset = &largepage_cmdset,
- .page_per_block = 64,
- .page_size = 2048,
- .flash_width = 16,
- .dfc_width = 16,
- .num_blocks = 2048,
- .chip_id = 0xba20,
-};
-
-static struct pxa3xx_nand_flash *builtin_flash_types[] = {
- &samsung512MbX16,
- &samsung2GbX8,
- &samsung32GbX8,
- µn1GbX8,
- µn1GbX16,
- µn4GbX8,
- µn4GbX16,
- &stm2GbX16,
-};
-#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
+/* Define a default flash type setting serve as flash detecting only */
+#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
#define NDTR0_tCH(c) (min((c), 7) << 19)
#define NDTR0_tCS(c) (min((c), 7) << 16)
#define NDTR1_tWHR(c) (min((c), 15) << 4)
#define NDTR1_tAR(c) (min((c), 15) << 0)
-#define tCH_NDTR0(r) (((r) >> 19) & 0x7)
-#define tCS_NDTR0(r) (((r) >> 16) & 0x7)
-#define tWH_NDTR0(r) (((r) >> 11) & 0x7)
-#define tWP_NDTR0(r) (((r) >> 8) & 0x7)
-#define tRH_NDTR0(r) (((r) >> 3) & 0x7)
-#define tRP_NDTR0(r) (((r) >> 0) & 0x7)
-
-#define tR_NDTR1(r) (((r) >> 16) & 0xffff)
-#define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
-#define tAR_NDTR1(r) (((r) >> 0) & 0xf)
-
/* convert nano-seconds to nand flash controller clock cycles */
#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
-/* convert nand flash controller clock cycles to nano-seconds */
-#define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
-
static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
const struct pxa3xx_nand_timing *t)
{
NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
+ info->ndtr0cs0 = ndtr0;
+ info->ndtr1cs0 = ndtr1;
nand_writel(info, NDTR0CS0, ndtr0);
nand_writel(info, NDTR1CS0, ndtr1);
}
return -ETIMEDOUT;
}
-static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
- uint16_t cmd, int column, int page_addr)
+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
{
- const struct pxa3xx_nand_flash *f = info->flash_info;
- const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
+ int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
- /* calculate data size */
- switch (f->page_size) {
+ info->data_size = info->page_size;
+ if (!oob_enable) {
+ info->oob_size = 0;
+ return;
+ }
+
+ switch (info->page_size) {
case 2048:
- info->data_size = (info->use_ecc) ? 2088 : 2112;
+ info->oob_size = (info->use_ecc) ? 40 : 64;
break;
case 512:
- info->data_size = (info->use_ecc) ? 520 : 528;
+ info->oob_size = (info->use_ecc) ? 8 : 16;
break;
- default:
- return -EINVAL;
}
+}
+
+static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
+ uint16_t cmd, int column, int page_addr)
+{
+ const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
+ pxa3xx_set_datasize(info);
/* generate values for NDCBx registers */
info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
{
- const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
+ const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
info->ndcb1 = 0;
info->ndcb2 = 0;
+ info->oob_size = 0;
if (cmd == cmdset->read_id) {
info->ndcb0 |= NDCB0_CMD_TYPE(3);
info->data_size = 8;
case STATE_PIO_WRITING:
__raw_writesl(info->mmio_base + NDDB, info->data_buff,
DIV_ROUND_UP(info->data_size, 4));
+ if (info->oob_size > 0)
+ __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
+ DIV_ROUND_UP(info->oob_size, 4));
enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
case STATE_PIO_READING:
__raw_readsl(info->mmio_base + NDDB, info->data_buff,
DIV_ROUND_UP(info->data_size, 4));
+ if (info->oob_size > 0)
+ __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
+ DIV_ROUND_UP(info->oob_size, 4));
break;
default:
printk(KERN_ERR "%s: invalid state %d\n", __func__,
static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
{
struct pxa_dma_desc *desc = info->data_desc;
- int dma_len = ALIGN(info->data_size, 32);
+ int dma_len = ALIGN(info->data_size + info->oob_size, 32);
desc->ddadr = DDADR_STOP;
desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
int column, int page_addr)
{
struct pxa3xx_nand_info *info = mtd->priv;
- const struct pxa3xx_nand_flash *flash_info = info->flash_info;
- const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
+ const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
int ret;
info->use_dma = (use_dma) ? 1 : 0;
static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
{
- const struct pxa3xx_nand_flash *f = info->flash_info;
- const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
+ const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
uint32_t ndcr;
uint8_t id_buff[8];
return -EINVAL;
/* calculate flash information */
- info->oob_size = (f->page_size == 2048) ? 64 : 16;
+ info->cmdset = f->cmdset;
+ info->page_size = f->page_size;
+ info->oob_buff = info->data_buff + f->page_size;
info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
/* calculate addressing information */
info->reg_ndcr = ndcr;
pxa3xx_nand_set_timing(info, f->timing);
- info->flash_info = f;
return 0;
}
-static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
- struct pxa3xx_nand_timing *t)
-{
- unsigned long nand_clk = clk_get_rate(info->clk);
- uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
- uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
-
- t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
- t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
- t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
- t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
- t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
- t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
-
- t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
- t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
- t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
-}
-
static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
{
uint32_t ndcr = nand_readl(info, NDCR);
struct nand_flash_dev *type = NULL;
- uint32_t id = -1;
+ uint32_t id = -1, page_per_block, num_blocks;
int i;
- default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
- default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
- default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
- default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
-
- if (default_flash.page_size == 2048)
- default_flash.cmdset = &largepage_cmdset;
- else
- default_flash.cmdset = &smallpage_cmdset;
-
+ page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
+ info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
/* set info fields needed to __readid */
- info->flash_info = &default_flash;
- info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
+ info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
info->reg_ndcr = ndcr;
if (__readid(info, &id))
return -ENODEV;
/* fill the missing flash information */
- i = __ffs(default_flash.page_per_block * default_flash.page_size);
- default_flash.num_blocks = type->chipsize << (20 - i);
-
- info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
+ i = __ffs(page_per_block * info->page_size);
+ num_blocks = type->chipsize << (20 - i);
/* calculate addressing information */
- info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
+ info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
- if (default_flash.num_blocks * default_flash.page_per_block > 65536)
+ if (num_blocks * page_per_block > 65536)
info->row_addr_cycles = 3;
else
info->row_addr_cycles = 2;
- pxa3xx_nand_detect_timing(info, &default_timing);
- default_flash.timing = &default_timing;
+ info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
+ info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
+ info->cmdset = &default_cmdset;
return 0;
}
if (pxa3xx_nand_detect_config(info) == 0)
return 0;
- for (i = 0; i<pdata->num_flash; ++i) {
- f = pdata->flash + i;
-
- if (pxa3xx_nand_config_flash(info, f))
- continue;
-
- if (__readid(info, &id))
- continue;
-
- if (id == f->chip_id)
- return 0;
- }
-
-#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
- for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
-
- f = builtin_flash_types[i];
-
- if (pxa3xx_nand_config_flash(info, f))
- continue;
-
- if (__readid(info, &id))
- continue;
-
- if (id == f->chip_id)
+ /* we use default timing to detect id */
+ f = DEFAULT_FLASH_TYPE;
+ pxa3xx_nand_config_flash(info, f);
+ if (__readid(info, &id))
+ goto fail_detect;
+
+ for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+ /* we first choose the flash definition from platfrom */
+ if (i < pdata->num_flash)
+ f = pdata->flash + i;
+ else
+ f = &builtin_flash_types[i - pdata->num_flash + 1];
+ if (f->chip_id == id) {
+ dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
+ pxa3xx_nand_config_flash(info, f);
return 0;
+ }
}
-#endif
dev_warn(&info->pdev->dev,
"failed to detect configured nand flash; found %04x instead of\n",
id);
+fail_detect:
return -ENODEV;
}
static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
struct pxa3xx_nand_info *info)
{
- const struct pxa3xx_nand_flash *f = info->flash_info;
struct nand_chip *this = &info->nand_chip;
- this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+ this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
this->waitfunc = pxa3xx_nand_waitfunc;
this->select_chip = pxa3xx_nand_select_chip;
this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
this->ecc.calculate = pxa3xx_nand_ecc_calculate;
this->ecc.correct = pxa3xx_nand_ecc_correct;
- this->ecc.size = f->page_size;
+ this->ecc.size = info->page_size;
- if (f->page_size == 2048)
+ if (info->page_size == 2048)
this->ecc.layout = &hw_largepage_ecclayout;
else
this->ecc.layout = &hw_smallpage_ecclayout;
struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
struct pxa3xx_nand_info *info = mtd->priv;
+ nand_writel(info, NDTR0CS0, info->ndtr0cs0);
+ nand_writel(info, NDTR1CS0, info->ndtr1cs0);
clk_enable(info->clk);
- return pxa3xx_nand_config_flash(info, info->flash_info);
+ return 0;
}
#else
#define pxa3xx_nand_suspend NULL
spin_lock_irqsave(&dev->irqlock, flags);
- /* We can recieve shared interrupt while pci is suspended
- in that case reads will return 0xFFFFFFFF.... */
- if (dev->insuspend)
- goto out;
-
/* handle card detection interrupts first */
card_status = r852_read_reg(dev, R852_CARD_IRQ_STA);
r852_write_reg(dev, R852_CARD_IRQ_STA, card_status);
int r852_suspend(struct device *device)
{
struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
- unsigned long flags;
if (dev->ctlreg & R852_CTL_CARDENABLE)
return -EBUSY;
r852_disable_irqs(dev);
r852_engine_disable(dev);
- spin_lock_irqsave(&dev->irqlock, flags);
- dev->insuspend = 1;
- spin_unlock_irqrestore(&dev->irqlock, flags);
-
- /* At that point, even if interrupt handler is running, it will quit */
- /* So wait for this to happen explictly */
- synchronize_irq(dev->irq);
-
/* If card was pulled off just during the suspend, which is very
unlikely, we will remove it on resume, it too late now
anyway... */
dev->card_unstable = 0;
-
- pci_save_state(to_pci_dev(device));
- return pci_prepare_to_sleep(to_pci_dev(device));
+ return 0;
}
int r852_resume(struct device *device)
{
struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
- unsigned long flags;
-
- /* Turn on the hardware */
- pci_back_from_sleep(to_pci_dev(device));
- pci_restore_state(to_pci_dev(device));
r852_disable_irqs(dev);
r852_card_update_present(dev);
r852_engine_disable(dev);
- /* Now its safe for IRQ to run */
- spin_lock_irqsave(&dev->irqlock, flags);
- dev->insuspend = 0;
- spin_unlock_irqrestore(&dev->irqlock, flags);
-
-
/* If card status changed, just do the work */
if (dev->card_detected != dev->card_registred) {
dbg("card was %s during low power state",
SIMPLE_DEV_PM_OPS(r852_pm_ops, r852_suspend, r852_resume);
-
static struct pci_driver r852_pci_driver = {
.name = DRV_NAME,
.id_table = r852_pci_id_tbl,
/* interrupt handling */
spinlock_t irqlock; /* IRQ protecting lock */
int irq; /* irq num */
- int insuspend; /* device is suspended */
-
/* misc */
void *tmp_buffer; /* temporary buffer */
uint8_t ctlreg; /* cached contents of control reg */
pp = NULL;
i = 0;
while ((pp = of_get_next_child(node, pp))) {
- const u32 *reg;
+ const __be32 *reg;
int len;
reg = of_get_property(pp, "reg", &len);
config MTD_ONENAND_SAMSUNG
tristate "OneNAND on Samsung SOC controller support"
- depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210
+ depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310
help
- Support for a OneNAND flash device connected to an Samsung SOC
- S3C64XX/S5PC1XX controller.
+ Support for a OneNAND flash device connected to an Samsung SOC.
+ S3C64XX/S5PC100 use command mapping method.
+ S5PC110/S5PC210 use generic OneNAND method.
config MTD_ONENAND_OTP
bool "OneNAND OTP Support"
static void onenand_check_features(struct mtd_info *mtd)
{
struct onenand_chip *this = mtd->priv;
- unsigned int density, process;
+ unsigned int density, process, numbufs;
/* Lock scheme depends on density and process */
density = onenand_get_density(this->device_id);
process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
+ numbufs = this->read_word(this->base + ONENAND_REG_NUM_BUFFERS) >> 8;
/* Lock scheme */
switch (density) {
case ONENAND_DEVICE_DENSITY_4Gb:
if (ONENAND_IS_DDP(this))
this->options |= ONENAND_HAS_2PLANE;
- else
+ else if (numbufs == 1)
this->options |= ONENAND_HAS_4KB_PAGE;
case ONENAND_DEVICE_DENSITY_2Gb:
mtd->ecclayout = this->ecclayout;
/* Fill in remaining MTD driver data */
- mtd->type = MTD_NANDFLASH;
+ mtd->type = ONENAND_IS_MLC(this) ? MTD_MLCNANDFLASH : MTD_NANDFLASH;
mtd->flags = MTD_CAP_NANDFLASH;
mtd->erase = onenand_erase;
mtd->point = NULL;
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
#include <asm/mach/flash.h>
#include <plat/regs-onenand.h>
#define MAP_11 (0x3)
#define S3C64XX_CMD_MAP_SHIFT 24
-#define S5PC1XX_CMD_MAP_SHIFT 26
+#define S5PC100_CMD_MAP_SHIFT 26
#define S3C6400_FBA_SHIFT 10
#define S3C6400_FPA_SHIFT 4
#define S5PC110_DMA_TRANS_CMD 0x418
#define S5PC110_DMA_TRANS_STATUS 0x41C
#define S5PC110_DMA_TRANS_DIR 0x420
+#define S5PC110_INTC_DMA_CLR 0x1004
+#define S5PC110_INTC_ONENAND_CLR 0x1008
+#define S5PC110_INTC_DMA_MASK 0x1024
+#define S5PC110_INTC_ONENAND_MASK 0x1028
+#define S5PC110_INTC_DMA_PEND 0x1044
+#define S5PC110_INTC_ONENAND_PEND 0x1048
+#define S5PC110_INTC_DMA_STATUS 0x1064
+#define S5PC110_INTC_ONENAND_STATUS 0x1068
+
+#define S5PC110_INTC_DMA_TD (1 << 24)
+#define S5PC110_INTC_DMA_TE (1 << 16)
#define S5PC110_DMA_CFG_SINGLE (0x0 << 16)
#define S5PC110_DMA_CFG_4BURST (0x2 << 16)
void __iomem *dma_addr;
struct resource *dma_res;
unsigned long phys_base;
+ struct completion complete;
#ifdef CONFIG_MTD_PARTITIONS
struct mtd_partition *parts;
#endif
static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
{
- return (type << S5PC1XX_CMD_MAP_SHIFT) | val;
+ return (type << S5PC100_CMD_MAP_SHIFT) | val;
}
static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
return 0;
}
-static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction)
+static int (*s5pc110_dma_ops)(void *dst, void *src, size_t count, int direction);
+
+static int s5pc110_dma_poll(void *dst, void *src, size_t count, int direction)
{
void __iomem *base = onenand->dma_addr;
int status;
+ unsigned long timeout;
writel(src, base + S5PC110_DMA_SRC_ADDR);
writel(dst, base + S5PC110_DMA_DST_ADDR);
writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
+ /*
+ * There's no exact timeout values at Spec.
+ * In real case it takes under 1 msec.
+ * So 20 msecs are enough.
+ */
+ timeout = jiffies + msecs_to_jiffies(20);
+
do {
status = readl(base + S5PC110_DMA_TRANS_STATUS);
if (status & S5PC110_DMA_TRANS_STATUS_TE) {
base + S5PC110_DMA_TRANS_CMD);
return -EIO;
}
- } while (!(status & S5PC110_DMA_TRANS_STATUS_TD));
+ } while (!(status & S5PC110_DMA_TRANS_STATUS_TD) &&
+ time_before(jiffies, timeout));
writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
return 0;
}
+static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
+{
+ void __iomem *base = onenand->dma_addr;
+ int status, cmd = 0;
+
+ status = readl(base + S5PC110_INTC_DMA_STATUS);
+
+ if (likely(status & S5PC110_INTC_DMA_TD))
+ cmd = S5PC110_DMA_TRANS_CMD_TDC;
+
+ if (unlikely(status & S5PC110_INTC_DMA_TE))
+ cmd = S5PC110_DMA_TRANS_CMD_TEC;
+
+ writel(cmd, base + S5PC110_DMA_TRANS_CMD);
+ writel(status, base + S5PC110_INTC_DMA_CLR);
+
+ if (!onenand->complete.done)
+ complete(&onenand->complete);
+
+ return IRQ_HANDLED;
+}
+
+static int s5pc110_dma_irq(void *dst, void *src, size_t count, int direction)
+{
+ void __iomem *base = onenand->dma_addr;
+ int status;
+
+ status = readl(base + S5PC110_INTC_DMA_MASK);
+ if (status) {
+ status &= ~(S5PC110_INTC_DMA_TD | S5PC110_INTC_DMA_TE);
+ writel(status, base + S5PC110_INTC_DMA_MASK);
+ }
+
+ writel(src, base + S5PC110_DMA_SRC_ADDR);
+ writel(dst, base + S5PC110_DMA_DST_ADDR);
+
+ if (direction == S5PC110_DMA_DIR_READ) {
+ writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
+ writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
+ } else {
+ writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
+ writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
+ }
+
+ writel(count, base + S5PC110_DMA_TRANS_SIZE);
+ writel(direction, base + S5PC110_DMA_TRANS_DIR);
+
+ writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
+
+ wait_for_completion_timeout(&onenand->complete, msecs_to_jiffies(20));
+
+ return 0;
+}
+
static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
unsigned char *buffer, int offset, size_t count)
{
void __iomem *p;
void *buf = (void *) buffer;
dma_addr_t dma_src, dma_dst;
- int err;
+ int err, page_dma = 0;
+ struct device *dev = &onenand->pdev->dev;
p = this->base + area;
if (ONENAND_CURRENT_BUFFERRAM(this)) {
page = vmalloc_to_page(buf);
if (!page)
goto normal;
- buf = page_address(page) + ((size_t) buf & ~PAGE_MASK);
- }
- /* DMA routine */
- dma_src = onenand->phys_base + (p - this->base);
- dma_dst = dma_map_single(&onenand->pdev->dev,
- buf, count, DMA_FROM_DEVICE);
- if (dma_mapping_error(&onenand->pdev->dev, dma_dst)) {
- dev_err(&onenand->pdev->dev,
- "Couldn't map a %d byte buffer for DMA\n", count);
+ page_dma = 1;
+ /* DMA routine */
+ dma_src = onenand->phys_base + (p - this->base);
+ dma_dst = dma_map_page(dev, page, 0, count, DMA_FROM_DEVICE);
+ } else {
+ /* DMA routine */
+ dma_src = onenand->phys_base + (p - this->base);
+ dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
+ }
+ if (dma_mapping_error(dev, dma_dst)) {
+ dev_err(dev, "Couldn't map a %d byte buffer for DMA\n", count);
goto normal;
}
err = s5pc110_dma_ops((void *) dma_dst, (void *) dma_src,
count, S5PC110_DMA_DIR_READ);
- dma_unmap_single(&onenand->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
+
+ if (page_dma)
+ dma_unmap_page(dev, dma_dst, count, DMA_FROM_DEVICE);
+ else
+ dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
if (!err)
return 0;
onenand->cmd_map = s5pc1xx_cmd_map;
} else if (onenand->type == TYPE_S5PC110) {
/* Use generic onenand functions */
- onenand->cmd_map = s5pc1xx_cmd_map;
this->read_bufferram = s5pc110_read_bufferram;
this->chip_probe = s5pc110_chip_probe;
return;
}
onenand->phys_base = onenand->base_res->start;
+
+ s5pc110_dma_ops = s5pc110_dma_poll;
+ /* Interrupt support */
+ r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (r) {
+ init_completion(&onenand->complete);
+ s5pc110_dma_ops = s5pc110_dma_irq;
+ err = request_irq(r->start, s5pc110_onenand_irq,
+ IRQF_SHARED, "onenand", &onenand);
+ if (err) {
+ dev_err(&pdev->dev, "failed to get irq\n");
+ goto scan_failed;
+ }
+ }
}
if (onenand_scan(mtd, 1)) {
struct onenand_chip *this = mtd->priv;
this->wait(mtd, FL_PM_SUSPENDED);
- return mtd->suspend(mtd);
+ return 0;
}
static int s3c_pm_ops_resume(struct device *dev)
struct mtd_info *mtd = platform_get_drvdata(pdev);
struct onenand_chip *this = mtd->priv;
- mtd->resume(mtd);
this->unlock_all(mtd);
return 0;
}
struct ftl_zone {
- int initialized;
+ bool initialized;
int16_t *lba_to_phys_table; /* LBA to physical table */
struct kfifo free_sectors; /* queue of free sectors */
};
int zone_count; /* number of zones */
int max_lba; /* maximum lba in a zone */
int smallpagenand; /* 256 bytes/page nand */
- int readonly; /* is FS readonly */
- int unstable;
+ bool readonly; /* is FS readonly */
+ bool unstable;
int cis_block; /* CIS block location */
int cis_boffset; /* CIS offset in the block */
int cis_page_offset; /* CIS offset in the page */
int cache_zone; /* zone of cached block */
unsigned char *cache_data; /* cached block data */
long unsigned int cache_data_invalid_bitmap;
- int cache_clean;
+ bool cache_clean;
struct work_struct flush_work;
struct timer_list timer;
config PCH_GBE
tristate "PCH Gigabit Ethernet"
depends on PCI
+ select MII
---help---
This is a gigabit ethernet driver for Topcliff PCH.
Topcliff PCH is the platform controller hub that is used in Intel's
int writeflag)
{
int ret;
- long flags;
+ unsigned long flags;
long *vbr, save_berr;
local_irq_save(flags);
/*
* at91_can.c - CAN network driver for AT91 SoC CAN controller
*
- * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
+ * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
* (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de>
*
* This software may be distributed under the terms of the GNU General
};
MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
-static inline void pch_can_bit_set(u32 *addr, u32 mask)
+static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
{
iowrite32(ioread32(addr) | mask, addr);
}
-static inline void pch_can_bit_clear(u32 *addr, u32 mask)
+static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
{
iowrite32(ioread32(addr) & ~mask, addr);
}
return rc;
}
-static struct pci_driver pch_can_pcidev = {
+static struct pci_driver pch_can_pci_driver = {
.name = "pch_can",
.id_table = pch_pci_tbl,
.probe = pch_can_probe,
static int __init pch_can_pci_init(void)
{
- return pci_register_driver(&pch_can_pcidev);
+ return pci_register_driver(&pch_can_pci_driver);
}
module_init(pch_can_pci_init);
static void __exit pch_can_pci_exit(void)
{
- pci_unregister_driver(&pch_can_pcidev);
+ pci_unregister_driver(&pch_can_pci_driver);
}
module_exit(pch_can_pci_exit);
pi->rx_offload = T3_RX_CSUM | T3_LRO;
pi->port_id = i;
netif_carrier_off(netdev);
- netif_tx_stop_all_queues(netdev);
netdev->irq = pdev->irq;
netdev->mem_start = mmio_start;
netdev->mem_end = mmio_start + mmio_len - 1;
adapter->name = adapter->port[i]->name;
__set_bit(i, &adapter->registered_device_map);
+ netif_tx_stop_all_queues(adapter->port[i]);
}
}
if (!adapter->registered_device_map) {
if (d->skb) { /* an SGL is present */
if (need_unmap)
unmap_skb(d->skb, q, cidx, pdev);
- if (d->eop)
+ if (d->eop) {
kfree_skb(d->skb);
+ d->skb = NULL;
+ }
}
++d;
if (++cidx == q->size) {
(ID_LED_DEF1_DEF2))
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+#define E1000_BASE1000T_STATUS 10
+#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
+#define E1000_RECEIVE_ERROR_COUNTER 21
+#define E1000_RECEIVE_ERROR_MAX 0xFFFF
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
return 0;
}
+/**
+ * e1000_check_phy_82574 - check 82574 phy hung state
+ * @hw: pointer to the HW structure
+ *
+ * Returns whether phy is hung or not
+ **/
+bool e1000_check_phy_82574(struct e1000_hw *hw)
+{
+ u16 status_1kbt = 0;
+ u16 receive_errors = 0;
+ bool phy_hung = false;
+ s32 ret_val = 0;
+
+ /*
+ * Read PHY Receive Error counter first, if its is max - all F's then
+ * read the Base1000T status register If both are max then PHY is hung.
+ */
+ ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
+
+ if (ret_val)
+ goto out;
+ if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
+ ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
+ if (ret_val)
+ goto out;
+ if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
+ E1000_IDLE_ERROR_COUNT_MASK)
+ phy_hung = true;
+ }
+out:
+ return phy_hung;
+}
+
/**
* e1000_setup_link_82571 - Setup flow control and link settings
* @hw: pointer to the HW structure
| FLAG_HAS_SMART_POWER_DOWN
| FLAG_HAS_AMT
| FLAG_HAS_CTRLEXT_ON_LOAD,
+ .flags2 = FLAG2_CHECK_PHY_HANG,
.pba = 36,
.max_hw_frame_size = DEFAULT_JUMBO,
.get_variants = e1000_get_variants_82571,
struct work_struct print_hang_task;
bool idle_check;
+ int phy_hang_count;
};
struct e1000_info {
#define FLAG2_HAS_EEE (1 << 5)
#define FLAG2_DMA_BURST (1 << 6)
#define FLAG2_DISABLE_AIM (1 << 8)
+#define FLAG2_CHECK_PHY_HANG (1 << 9)
#define E1000_RX_DESC_PS(R, i) \
(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
+extern bool e1000_check_phy_82574(struct e1000_hw *hw);
static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
{
}
}
+static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
+{
+ struct e1000_hw *hw = &adapter->hw;
+
+ /*
+ * With 82574 controllers, PHY needs to be checked periodically
+ * for hung state and reset, if two calls return true
+ */
+ if (e1000_check_phy_82574(hw))
+ adapter->phy_hang_count++;
+ else
+ adapter->phy_hang_count = 0;
+
+ if (adapter->phy_hang_count > 1) {
+ adapter->phy_hang_count = 0;
+ schedule_work(&adapter->reset_task);
+ }
+}
+
/**
* e1000_watchdog - Timer Call-back
* @data: pointer to adapter cast into an unsigned long
if (e1000e_get_laa_state_82571(hw))
e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
+ if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
+ e1000e_check_82574_phy_workaround(adapter);
+
/* Reset the timer */
if (!test_bit(__E1000_DOWN, &adapter->state))
mod_timer(&adapter->watchdog_timer,
struct e1000_adapter *adapter;
adapter = container_of(work, struct e1000_adapter, reset_task);
- e1000e_dump(adapter);
- e_err("Reset adapter\n");
+ if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
+ (adapter->flags & FLAG_RX_RESTART_NOW))) {
+ e1000e_dump(adapter);
+ e_err("Reset adapter\n");
+ }
e1000e_reinit_locked(adapter);
}
netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
struct igb_ring *tx_ring)
{
- struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
int tso = 0, count;
u32 tx_flags = 0;
u16 first;
/* reset the hardware with the new settings */
igbvf_reset(adapter);
- /* tell the stack to leave us alone until igbvf_open() is called */
- netif_carrier_off(netdev);
- netif_stop_queue(netdev);
-
strcpy(netdev->name, "eth%d");
err = register_netdev(netdev);
if (err)
goto err_hw_init;
+ /* tell the stack to leave us alone until igbvf_open() is called */
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
igbvf_print_device_info(adapter);
igbvf_initialize_last_counter_stats(adapter);
pci_release_regions(pdev);
free_netdev(netdev);
+ pci_disable_device(pdev);
}
/**
* ixgbe_dcb_check_config().
*/
s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
- u8 direction)
+ int max_frame, u8 direction)
{
struct tc_bw_alloc *p;
+ int min_credit;
+ int min_multiplier;
+ int min_percent = 100;
s32 ret_val = 0;
/* Initialization values default for Tx settings */
u32 credit_refill = 0;
goto out;
}
+ min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
+ DCB_CREDIT_QUANTUM;
+
+ /* Find smallest link percentage */
+ for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+ p = &dcb_config->tc_config[i].path[direction];
+ bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
+ link_percentage = p->bwg_percent;
+
+ link_percentage = (link_percentage * bw_percent) / 100;
+
+ if (link_percentage && link_percentage < min_percent)
+ min_percent = link_percentage;
+ }
+
+ /*
+ * The ratio between traffic classes will control the bandwidth
+ * percentages seen on the wire. To calculate this ratio we use
+ * a multiplier. It is required that the refill credits must be
+ * larger than the max frame size so here we find the smallest
+ * multiplier that will allow all bandwidth percentages to be
+ * greater than the max frame size.
+ */
+ min_multiplier = (min_credit / min_percent) + 1;
+
/* Find out the link percentage for each TC first */
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
p = &dcb_config->tc_config[i].path[direction];
/* Save link_percentage for reference */
p->link_percent = (u8)link_percentage;
- /* Calculate credit refill and save it */
- credit_refill = link_percentage * MINIMUM_CREDIT_REFILL;
+ /* Calculate credit refill ratio using multiplier */
+ credit_refill = min(link_percentage * min_multiplier,
+ MAX_CREDIT_REFILL);
p->data_credits_refill = (u16)credit_refill;
/* Calculate maximum credit for the TC */
* of a TC is too small, the maximum credit may not be
* enough to send out a jumbo frame in data plane arbitration.
*/
- if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_JUMBO))
- credit_max = MINIMUM_CREDIT_FOR_JUMBO;
+ if (credit_max && (credit_max < min_credit))
+ credit_max = min_credit;
if (direction == DCB_TX_CONFIG) {
/*
/* DCB driver APIs */
/* DCB credits calculation */
-s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8);
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, int, u8);
/* DCB hw initialization */
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
/* DCB definitions for credit calculation */
+#define DCB_CREDIT_QUANTUM 64 /* DCB Quantum */
#define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
-#define MINIMUM_CREDIT_REFILL 5 /* 5*64B = 320B */
-#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */
#define DCB_MAX_TSO_SIZE (32*1024) /* MAX TSO packet size supported in DCB mode */
#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */
reg &= ~IXGBE_RTTDCS_ARBDIS;
IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
+ /* Enable Security TX Buffer IFG for DCB */
+ reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
+ reg |= IXGBE_SECTX_DCB;
+ IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
+
return 0;
}
#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
+/* SECTXMINIFG DCB */
+#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
+
/* DCB hardware-specific driver APIs */
static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
{
struct ixgbe_hw *hw = &adapter->hw;
+ int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
u32 txdctl;
int i, j;
if (hw->mac.type == ixgbe_mac_82598EB)
netif_set_gso_max_size(adapter->netdev, 32768);
- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
- ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
+#ifdef CONFIG_FCOE
+ if (adapter->netdev->features & NETIF_F_FCOE_MTU)
+ max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
+#endif
+
+ ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+ DCB_TX_CONFIG);
+ ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+ DCB_RX_CONFIG);
/* reconfigure the hardware */
ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
ei_outb_p(ei_local->rx_start_page, e8390_base + EN1_CURPAG);
ei_outb_p(E8390_NODMA+E8390_PAGE0+E8390_STOP, e8390_base+E8390_CMD);
- netif_start_queue(dev);
ei_local->tx1 = ei_local->tx2 = 0;
ei_local->txing = 0;
return err;
}
-static void
-nx_fw_cmd_reset_ctx(struct netxen_adapter *adapter)
-{
-
- netxen_issue_cmd(adapter, adapter->ahw.pci_func, NXHAL_VERSION,
- adapter->ahw.pci_func, NX_DESTROY_CTX_RESET, 0,
- NX_CDRP_CMD_DESTROY_RX_CTX);
-
- netxen_issue_cmd(adapter, adapter->ahw.pci_func, NXHAL_VERSION,
- adapter->ahw.pci_func, NX_DESTROY_CTX_RESET, 0,
- NX_CDRP_CMD_DESTROY_TX_CTX);
-}
-
static void
nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
{
if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
goto done;
- if (reset_devices)
- nx_fw_cmd_reset_ctx(adapter);
err = nx_fw_cmd_create_rx_ctx(adapter);
if (err)
goto err_out_free;
dev_warn(&pdev->dev, "failed to read mac addr\n");
netif_carrier_off(netdev);
- netif_stop_queue(netdev);
err = register_netdev(netdev);
if (err) {
break;
}
+ if (reset_devices) {
+ if (adapter->portnum == 0) {
+ NXWR32(adapter, NX_CRB_DEV_REF_COUNT, 0);
+ adapter->need_fw_reset = 1;
+ }
+ }
+
err = netxen_start_firmware(adapter);
if (err)
goto err_out_decr_ref;
PCMCIA_DEVICE_PROD_ID12("COMPU-SHACK", "FASTline PCMCIA 10/100 Fast-Ethernet", 0xfa2e424d, 0x3953d9b9),
PCMCIA_DEVICE_PROD_ID12("CONTEC", "C-NET(PC)C-10L", 0x21cab552, 0xf6f90722),
PCMCIA_DEVICE_PROD_ID12("corega", "FEther PCC-TXF", 0x0a21501a, 0xa51564a2),
+ PCMCIA_DEVICE_PROD_ID12("corega", "Ether CF-TD", 0x0a21501a, 0x6589340a),
PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-T", 0x5261440f, 0xfa9d85bd),
PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-TD", 0x5261440f, 0xc49bd73d),
PCMCIA_DEVICE_PROD_ID12("Corega K.K.", "corega EtherII PCC-TD", 0xd4fdcbd8, 0xc49bd73d),
#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
-#define MII_88EC048_PHY_MSCR1_REG 16
-#define MII_88EC048_PHY_MSCR1_PAD_ODD BIT(6)
+#define MII_88E1318S_PHY_MSCR1_REG 16
+#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
#define MII_88E1121_PHY_LED_CTRL 16
#define MII_88E1121_PHY_LED_PAGE 3
return err;
}
-static int m88ec048_config_aneg(struct phy_device *phydev)
+static int m88e1318_config_aneg(struct phy_device *phydev)
{
int err, oldpage, mscr;
if (err < 0)
return err;
- mscr = phy_read(phydev, MII_88EC048_PHY_MSCR1_REG);
- mscr |= MII_88EC048_PHY_MSCR1_PAD_ODD;
+ mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
+ mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
- err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
+ err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
if (err < 0)
return err;
.driver = { .owner = THIS_MODULE },
},
{
- .phy_id = MARVELL_PHY_ID_88EC048,
+ .phy_id = MARVELL_PHY_ID_88E1318S,
.phy_id_mask = MARVELL_PHY_ID_MASK,
- .name = "Marvell 88EC048",
+ .name = "Marvell 88E1318S",
.features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT,
- .config_aneg = &m88ec048_config_aneg,
+ .config_aneg = &m88e1318_config_aneg,
.read_status = &marvell_read_status,
.ack_interrupt = &marvell_ack_interrupt,
.config_intr = &marvell_config_intr,
return 0;
}
-static inline void stmmac_mac_enable_rx(void __iomem *ioaddr)
+static inline void stmmac_enable_mac(void __iomem *ioaddr)
{
u32 value = readl(ioaddr + MAC_CTRL_REG);
- value |= MAC_RNABLE_RX;
- /* Set the RE (receive enable bit into the MAC CTRL register). */
- writel(value, ioaddr + MAC_CTRL_REG);
-}
-static inline void stmmac_mac_enable_tx(void __iomem *ioaddr)
-{
- u32 value = readl(ioaddr + MAC_CTRL_REG);
- value |= MAC_ENABLE_TX;
- /* Set the TE (transmit enable bit into the MAC CTRL register). */
+ value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
writel(value, ioaddr + MAC_CTRL_REG);
}
-static inline void stmmac_mac_disable_rx(void __iomem *ioaddr)
+static inline void stmmac_disable_mac(void __iomem *ioaddr)
{
u32 value = readl(ioaddr + MAC_CTRL_REG);
- value &= ~MAC_RNABLE_RX;
- writel(value, ioaddr + MAC_CTRL_REG);
-}
-static inline void stmmac_mac_disable_tx(void __iomem *ioaddr)
-{
- u32 value = readl(ioaddr + MAC_CTRL_REG);
- value &= ~MAC_ENABLE_TX;
+ value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
writel(value, ioaddr + MAC_CTRL_REG);
}
writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
/* Enable the MAC Rx/Tx */
- stmmac_mac_enable_rx(priv->ioaddr);
- stmmac_mac_enable_tx(priv->ioaddr);
+ stmmac_enable_mac(priv->ioaddr);
/* Set the HW DMA mode and the COE */
stmmac_dma_operation_mode(priv);
/* Release and free the Rx/Tx resources */
free_dma_desc_resources(priv);
- /* Disable the MAC core */
- stmmac_mac_disable_tx(priv->ioaddr);
- stmmac_mac_disable_rx(priv->ioaddr);
+ /* Disable the MAC Rx/Tx */
+ stmmac_disable_mac(priv->ioaddr);
netif_carrier_off(dev);
priv->hw->dma->stop_rx(priv->ioaddr);
priv->hw->dma->stop_tx(priv->ioaddr);
- stmmac_mac_disable_rx(priv->ioaddr);
- stmmac_mac_disable_tx(priv->ioaddr);
+ stmmac_disable_mac(priv->ioaddr);
netif_carrier_off(ndev);
dis_ic);
priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
- stmmac_mac_disable_tx(priv->ioaddr);
-
/* Enable Power down mode by programming the PMT regs */
if (device_can_wakeup(priv->device))
priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
else
- stmmac_mac_disable_rx(priv->ioaddr);
+ stmmac_disable_mac(priv->ioaddr);
} else {
priv->shutdown = 1;
/* Although this can appear slightly redundant it actually
netif_device_attach(dev);
/* Enable the MAC and DMA */
- stmmac_mac_enable_rx(priv->ioaddr);
- stmmac_mac_enable_tx(priv->ioaddr);
+ stmmac_enable_mac(priv->ioaddr);
priv->hw->dma->start_tx(priv->ioaddr);
priv->hw->dma->start_rx(priv->ioaddr);
count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
skb_shinfo(skb)->nr_frags + 1;
- ctx.ipv4 = (skb->protocol == __constant_ntohs(ETH_P_IP));
+ ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP));
ctx.mss = skb_shinfo(skb)->gso_size;
if (ctx.mss) {
};
#define VMXNET3_WRITE_BAR0_REG(adapter, reg, val) \
- writel(cpu_to_le32(val), (adapter)->hw_addr0 + (reg))
+ writel((val), (adapter)->hw_addr0 + (reg))
#define VMXNET3_READ_BAR0_REG(adapter, reg) \
- le32_to_cpu(readl((adapter)->hw_addr0 + (reg)))
+ readl((adapter)->hw_addr0 + (reg))
#define VMXNET3_WRITE_BAR1_REG(adapter, reg, val) \
- writel(cpu_to_le32(val), (adapter)->hw_addr1 + (reg))
+ writel((val), (adapter)->hw_addr1 + (reg))
#define VMXNET3_READ_BAR1_REG(adapter, reg) \
- le32_to_cpu(readl((adapter)->hw_addr1 + (reg)))
+ readl((adapter)->hw_addr1 + (reg))
#define VMXNET3_WAKE_QUEUE_THRESHOLD(tq) (5)
#define VMXNET3_RX_ALLOC_THRESHOLD(rq, ring_idx, adapter) \
/* Fill the ath5k_hw struct with the needed functions */
ret = ath5k_hw_init_desc_functions(ah);
if (ret)
- goto err_free;
+ goto err;
/* Bring device out of sleep and reset its units */
ret = ath5k_hw_nic_wakeup(ah, 0, true);
if (ret)
- goto err_free;
+ goto err;
/* Get MAC, PHY and RADIO revisions */
ah->ah_mac_srev = srev;
} else {
ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
ret = -ENODEV;
- goto err_free;
+ goto err;
}
}
(srev < AR5K_SREV_AR2425)) {
ATH5K_ERR(sc, "Device not yet supported.\n");
ret = -ENODEV;
- goto err_free;
+ goto err;
}
/*
*/
ret = ath5k_hw_post(ah);
if (ret)
- goto err_free;
+ goto err;
/* Enable pci core retry fix on Hainan (5213A) and later chips */
if (srev >= AR5K_SREV_AR5213A)
ret = ath5k_eeprom_init(ah);
if (ret) {
ATH5K_ERR(sc, "unable to init EEPROM\n");
- goto err_free;
+ goto err;
}
ee = &ah->ah_capabilities.cap_eeprom;
if (ret) {
ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
sc->pdev->device);
- goto err_free;
+ goto err;
}
/* Crypto settings */
ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
return 0;
-err_free:
- kfree(ah);
+err:
return ret;
}
u8 rxotherant;
u32 *rxlink;
unsigned int rxfilter;
- spinlock_t rxflushlock;
+ spinlock_t pcu_lock;
spinlock_t rxbuflock;
struct list_head rxbuf;
struct ath_descdma rxdma;
}
kfree(buf);
- if ((hif_dev->device_id == 0x7010) || (hif_dev->device_id == 0x7015))
+ switch (hif_dev->device_id) {
+ case 0x7010:
+ case 0x7015:
+ case 0x9018:
firm_offset = AR7010_FIRMWARE_TEXT;
- else
+ break;
+ default:
firm_offset = AR9271_FIRMWARE_TEXT;
+ break;
+ }
/*
* Issue FW download complete command to firmware.
*/
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, false);
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
stopped = ath_stoprecv(sc);
/* XXX: do not flush receive queue here. We don't want
"reset status %d\n",
channel->center_freq, r);
spin_unlock_bh(&sc->sc_resetlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto ps_restore;
}
spin_unlock_bh(&sc->sc_resetlock);
ath_print(common, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
r = -EIO;
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto ps_restore;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
ath_update_txpow(sc);
ath9k_hw_set_interrupts(ah, ah->imask);
rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
if (status & rxmask) {
- spin_lock_bh(&sc->rx.rxflushlock);
+ spin_lock_bh(&sc->rx.pcu_lock);
/* Check for high priority Rx first */
if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
ath_rx_tasklet(sc, 0, true);
ath_rx_tasklet(sc, 0, false);
- spin_unlock_bh(&sc->rx.rxflushlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
}
if (status & ATH9K_INT_TX) {
if (!ah->curchan)
ah->curchan = ath_get_curchannel(sc, sc->hw);
+ spin_lock_bh(&sc->rx.pcu_lock);
spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
if (r) {
if (ath_startrecv(sc) != 0) {
ath_print(common, ATH_DBG_FATAL,
"Unable to restart recv logic\n");
+ spin_unlock_bh(&sc->rx.pcu_lock);
return;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
if (sc->sc_flags & SC_OP_BEACONS)
ath_beacon_config(sc, NULL); /* restart beacons */
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, false); /* clear pending tx frames */
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
ath_stoprecv(sc); /* turn off frame recv */
ath_flushrecv(sc); /* flush recv queue */
spin_unlock_bh(&sc->sc_resetlock);
ath9k_hw_phy_disable(ah);
+
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
ath9k_hw_configpcipowersave(ah, 1, 1);
ath9k_ps_restore(sc);
ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ath9k_hw_set_interrupts(ah, 0);
ath_drain_all_txq(sc, retry_tx);
+
+ spin_lock_bh(&sc->rx.pcu_lock);
+
ath_stoprecv(sc);
ath_flushrecv(sc);
ath_print(common, ATH_DBG_FATAL,
"Unable to start recv logic\n");
+ spin_unlock_bh(&sc->rx.pcu_lock);
+
/*
* We may be doing a reset in response to a request
* that changes the channel so update any state that
* be followed by initialization of the appropriate bits
* and then setup of the interrupt mask.
*/
+ spin_lock_bh(&sc->rx.pcu_lock);
spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
if (r) {
"(freq %u MHz)\n", r,
curchan->center_freq);
spin_unlock_bh(&sc->sc_resetlock);
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto mutex_unlock;
}
spin_unlock_bh(&sc->sc_resetlock);
ath_print(common, ATH_DBG_FATAL,
"Unable to start recv logic\n");
r = -EIO;
+ spin_unlock_bh(&sc->rx.pcu_lock);
goto mutex_unlock;
}
+ spin_unlock_bh(&sc->rx.pcu_lock);
/* Setup our intr mask. */
ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
* before setting the invalid flag. */
ath9k_hw_set_interrupts(ah, 0);
+ spin_lock_bh(&sc->rx.pcu_lock);
if (!(sc->sc_flags & SC_OP_INVALID)) {
ath_drain_all_txq(sc, false);
ath_stoprecv(sc);
ath9k_hw_phy_disable(ah);
} else
sc->rx.rxlink = NULL;
+ spin_unlock_bh(&sc->rx.pcu_lock);
/* disable HAL and put h/w to sleep */
ath9k_hw_disable(ah);
for (i = 0; i < rateset->rs_nrates; i++) {
for (j = 0; j < rate_table->rate_cnt; j++) {
u32 phy = rate_table->info[j].phy;
- u16 rate_flags = rate_table->info[i].rate_flags;
+ u16 rate_flags = rate_table->info[j].rate_flags;
u8 rate = rateset->rs_rates[i];
u8 dot11rate = rate_table->info[j].dot11rate;
ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
- spin_unlock_bh(&sc->rx.rxbuflock);
-
ath_opmode_init(sc);
ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+
+ spin_unlock_bh(&sc->rx.rxbuflock);
}
static void ath_edma_stop_recv(struct ath_softc *sc)
{
- spin_lock_bh(&sc->rx.rxbuflock);
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
- spin_unlock_bh(&sc->rx.rxbuflock);
}
int ath_rx_init(struct ath_softc *sc, int nbufs)
struct ath_buf *bf;
int error = 0;
- spin_lock_init(&sc->rx.rxflushlock);
+ spin_lock_init(&sc->rx.pcu_lock);
sc->sc_flags &= ~SC_OP_RXFLUSH;
spin_lock_init(&sc->rx.rxbuflock);
ath9k_hw_rxena(ah);
start_recv:
- spin_unlock_bh(&sc->rx.rxbuflock);
ath_opmode_init(sc);
ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
+ spin_unlock_bh(&sc->rx.rxbuflock);
+
return 0;
}
struct ath_hw *ah = sc->sc_ah;
bool stopped;
+ spin_lock_bh(&sc->rx.rxbuflock);
ath9k_hw_stoppcurecv(ah);
ath9k_hw_setrxfilter(ah, 0);
stopped = ath9k_hw_stopdmarecv(ah);
ath_edma_stop_recv(sc);
else
sc->rx.rxlink = NULL;
+ spin_unlock_bh(&sc->rx.rxbuflock);
return stopped;
}
void ath_flushrecv(struct ath_softc *sc)
{
- spin_lock_bh(&sc->rx.rxflushlock);
sc->sc_flags |= SC_OP_RXFLUSH;
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
ath_rx_tasklet(sc, 1, true);
ath_rx_tasklet(sc, 1, false);
sc->sc_flags &= ~SC_OP_RXFLUSH;
- spin_unlock_bh(&sc->rx.rxflushlock);
}
static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
txq->axq_tx_inprogress = false;
spin_unlock_bh(&txq->axq_lock);
- /* flush any pending frames if aggregation is enabled */
- if (sc->sc_flags & SC_OP_TXAGGR) {
- if (!retry_tx) {
- spin_lock_bh(&txq->axq_lock);
- ath_txq_drain_pending_buffers(sc, txq);
- spin_unlock_bh(&txq->axq_lock);
- }
- }
-
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
spin_lock_bh(&txq->axq_lock);
while (!list_empty(&txq->txq_fifo_pending)) {
}
spin_unlock_bh(&txq->axq_lock);
}
+
+ /* flush any pending frames if aggregation is enabled */
+ if (sc->sc_flags & SC_OP_TXAGGR) {
+ if (!retry_tx) {
+ spin_lock_bh(&txq->axq_lock);
+ ath_txq_drain_pending_buffers(sc, txq);
+ spin_unlock_bh(&txq->axq_lock);
+ }
+ }
}
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
struct b43_sdio *sdio = sdio_get_drvdata(func);
ssb_bus_unregister(&sdio->ssb);
+ sdio_claim_host(func);
sdio_disable_func(func);
+ sdio_release_host(func);
kfree(sdio);
sdio_set_drvdata(func, NULL);
}
lbs_deb_enter(LBS_DEB_SDIO);
+ /*
+ * Disable interrupts
+ */
+ sdio_claim_host(card->func);
+ sdio_writeb(card->func, 0x00, IF_SDIO_H_INT_MASK, &ret);
+ sdio_release_host(card->func);
+
sdio_claim_host(card->func);
scratch = if_sdio_read_scratch(card, &ret);
sdio_release_host(card->func);
+ lbs_deb_sdio("firmware status = %#x\n", scratch);
+ lbs_deb_sdio("scratch ret = %d\n", ret);
+
if (ret)
goto out;
- lbs_deb_sdio("firmware status = %#x\n", scratch);
+ /*
+ * The manual clearly describes that FEDC is the right code to use
+ * to detect firmware presence, but for SD8686 it is not that simple.
+ * Scratch is also used to store the RX packet length, so we lose
+ * the FEDC value early on. So we use a non-zero check in order
+ * to validate firmware presence.
+ * Additionally, the SD8686 in the Gumstix always has the high scratch
+ * bit set, even when the firmware is not loaded. So we have to
+ * exclude that from the test.
+ */
if (scratch == IF_SDIO_FIRMWARE_OK) {
lbs_deb_sdio("firmware already loaded\n");
goto success;
+ } else if ((card->model == MODEL_8686) && (scratch & 0x7fff)) {
+ lbs_deb_sdio("firmware may be running\n");
+ goto success;
}
ret = lbs_get_firmware(&card->func->dev, lbs_helper_name, lbs_fw_name,
if (ret)
goto out;
+ lbs_deb_sdio("Helper firmware loaded\n");
+
ret = if_sdio_prog_real(card, mainfw);
if (ret)
goto out;
+ lbs_deb_sdio("Firmware loaded\n");
+
success:
sdio_claim_host(card->func);
sdio_set_block_size(card->func, IF_SDIO_BLOCK_SIZE);
priv->exit_deep_sleep = if_sdio_exit_deep_sleep;
priv->reset_deep_sleep_wakeup = if_sdio_reset_deep_sleep_wakeup;
- priv->fw_ready = 1;
-
sdio_claim_host(func);
/*
if (ret)
goto reclaim;
+ priv->fw_ready = 1;
+
/*
* FUNC_INIT is required for SD8688 WLAN/BT multiple functions
*/
profile_event_unregister(PROFILE_TASK_EXIT, &task_exit_nb);
task_handoff_unregister(&task_free_nb);
mutex_unlock(&buffer_mutex);
- flush_scheduled_work();
+ flush_cpu_work();
/* make sure we don't leak task structs */
process_task_mortuary();
void end_cpu_work(void)
{
- int i;
-
work_enabled = 0;
+}
+
+void flush_cpu_work(void)
+{
+ int i;
for_each_online_cpu(i) {
struct oprofile_cpu_buffer *b = &per_cpu(op_cpu_buffer, i);
- cancel_delayed_work(&b->work);
+ /* these works are per-cpu, no need for flush_sync */
+ flush_delayed_work(&b->work);
}
}
void start_cpu_work(void);
void end_cpu_work(void);
+void flush_cpu_work(void);
/* CPU buffer is composed of such entries (which are
* also used for context switch notes)
}
-static int oprofilefs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *oprofilefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, oprofilefs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, oprofilefs_fill_super);
}
static struct file_system_type oprofilefs_type = {
.owner = THIS_MODULE,
.name = "oprofilefs",
- .get_sb = oprofilefs_get_sb,
+ .mount = oprofilefs_mount,
.kill_sb = kill_litter_super,
};
#include "oprof.h"
static DEFINE_PER_CPU(struct hrtimer, oprofile_hrtimer);
+static int ctr_running;
static enum hrtimer_restart oprofile_hrtimer_notify(struct hrtimer *hrtimer)
{
{
struct hrtimer *hrtimer = &__get_cpu_var(oprofile_hrtimer);
+ if (!ctr_running)
+ return;
+
hrtimer_init(hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
hrtimer->function = oprofile_hrtimer_notify;
static int oprofile_hrtimer_start(void)
{
+ get_online_cpus();
+ ctr_running = 1;
on_each_cpu(__oprofile_hrtimer_start, NULL, 1);
+ put_online_cpus();
return 0;
}
{
struct hrtimer *hrtimer = &per_cpu(oprofile_hrtimer, cpu);
+ if (!ctr_running)
+ return;
+
hrtimer_cancel(hrtimer);
}
{
int cpu;
+ get_online_cpus();
for_each_online_cpu(cpu)
__oprofile_hrtimer_stop(cpu);
+ ctr_running = 0;
+ put_online_cpus();
}
static int __cpuinit oprofile_cpu_notify(struct notifier_block *self,
return rc;
}
+/*
+ * SNID - Sense Path Group ID
+ * This ioctl may be used in situations where I/O is stalled due to
+ * a reserve, so if the normal dasd_smalloc_request fails, we use the
+ * preallocated dasd_reserve_req.
+ */
+static int dasd_eckd_snid(struct dasd_device *device,
+ void __user *argp)
+{
+ struct dasd_ccw_req *cqr;
+ int rc;
+ struct ccw1 *ccw;
+ int useglobal;
+ struct dasd_snid_ioctl_data usrparm;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EACCES;
+
+ if (copy_from_user(&usrparm, argp, sizeof(usrparm)))
+ return -EFAULT;
+
+ useglobal = 0;
+ cqr = dasd_smalloc_request(DASD_ECKD_MAGIC, 1,
+ sizeof(struct dasd_snid_data), device);
+ if (IS_ERR(cqr)) {
+ mutex_lock(&dasd_reserve_mutex);
+ useglobal = 1;
+ cqr = &dasd_reserve_req->cqr;
+ memset(cqr, 0, sizeof(*cqr));
+ memset(&dasd_reserve_req->ccw, 0,
+ sizeof(dasd_reserve_req->ccw));
+ cqr->cpaddr = &dasd_reserve_req->ccw;
+ cqr->data = &dasd_reserve_req->data;
+ cqr->magic = DASD_ECKD_MAGIC;
+ }
+ ccw = cqr->cpaddr;
+ ccw->cmd_code = DASD_ECKD_CCW_SNID;
+ ccw->flags |= CCW_FLAG_SLI;
+ ccw->count = 12;
+ ccw->cda = (__u32)(addr_t) cqr->data;
+ cqr->startdev = device;
+ cqr->memdev = device;
+ clear_bit(DASD_CQR_FLAGS_USE_ERP, &cqr->flags);
+ set_bit(DASD_CQR_FLAGS_FAILFAST, &cqr->flags);
+ cqr->retries = 5;
+ cqr->expires = 10 * HZ;
+ cqr->buildclk = get_clock();
+ cqr->status = DASD_CQR_FILLED;
+ cqr->lpm = usrparm.path_mask;
+
+ rc = dasd_sleep_on_immediatly(cqr);
+ /* verify that I/O processing didn't modify the path mask */
+ if (!rc && usrparm.path_mask && (cqr->lpm != usrparm.path_mask))
+ rc = -EIO;
+ if (!rc) {
+ usrparm.data = *((struct dasd_snid_data *)cqr->data);
+ if (copy_to_user(argp, &usrparm, sizeof(usrparm)))
+ rc = -EFAULT;
+ }
+
+ if (useglobal)
+ mutex_unlock(&dasd_reserve_mutex);
+ else
+ dasd_sfree_request(cqr, cqr->memdev);
+ return rc;
+}
+
/*
* Read performance statistics
*/
return dasd_eckd_reserve(device);
case BIODASDSLCK:
return dasd_eckd_steal_lock(device);
+ case BIODASDSNID:
+ return dasd_eckd_snid(device, argp);
case BIODASDSYMMIO:
return dasd_symm_io(device, argp);
default:
#define DASD_ECKD_CCW_WRITE_CKD 0x1d
#define DASD_ECKD_CCW_READ_CKD 0x1e
#define DASD_ECKD_CCW_PSF 0x27
+#define DASD_ECKD_CCW_SNID 0x34
#define DASD_ECKD_CCW_RSSD 0x3e
#define DASD_ECKD_CCW_LOCATE_RECORD 0x47
#define DASD_ECKD_CCW_SNSS 0x54
/* FIXME: What to do with the request? */
switch (PTR_ERR(irb)) {
case -ETIMEDOUT:
- DBF_LH(1, "(%s): Request timed out\n",
- dev_name(&cdev->dev));
+ DBF_LH(1, "(%08x): Request timed out\n",
+ device->cdev_id);
case -EIO:
__tape_end_request(device, request, -EIO);
break;
default:
- DBF_LH(1, "(%s): Unexpected i/o error %li\n",
- dev_name(&cdev->dev),
- PTR_ERR(irb));
+ DBF_LH(1, "(%08x): Unexpected i/o error %li\n",
+ device->cdev_id, PTR_ERR(irb));
}
return;
}
device->cdev_id);
rc = tape_cancel_io(device, request);
if(rc)
- DBF_EVENT(3, "(%s): Assign timeout: Cancel failed with rc = %i\n",
- dev_name(&device->cdev->dev), rc);
+ DBF_EVENT(3, "(%08x): Assign timeout: Cancel failed with rc = "
+ "%i\n", device->cdev_id, rc);
}
int
source "drivers/staging/frontier/Kconfig"
-source "drivers/staging/dream/Kconfig"
-
source "drivers/staging/pohmelfs/Kconfig"
source "drivers/staging/autofs/Kconfig"
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_SPECTRA) += spectra/
obj-$(CONFIG_TRANZPORT) += frontier/
-obj-$(CONFIG_DREAM) += dream/
obj-$(CONFIG_POHMELFS) += pohmelfs/
obj-$(CONFIG_AUTOFS_FS) += autofs/
obj-$(CONFIG_IDE_PHISON) += phison/
#include <linux/init.h>
#include "autofs_i.h"
-static int autofs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *autofs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, autofs_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, autofs_fill_super);
}
static struct file_system_type autofs_fs_type = {
.owner = THIS_MODULE,
.name = "autofs",
- .get_sb = autofs_get_sb,
+ .mount = autofs_mount,
.kill_sb = autofs_kill_sb,
};
+++ /dev/null
-config DREAM
- tristate "HTC Dream support"
- depends on MACH_TROUT
-
-if DREAM
-
-source "drivers/staging/dream/camera/Kconfig"
-
-config INPUT_GPIO
- tristate "GPIO driver support"
- help
- Say Y here if you want to support gpio based keys, wheels etc...
-endif
+++ /dev/null
-ccflags-y:=-Idrivers/staging/dream/include
-obj-$(CONFIG_MSM_ADSP) += qdsp5/
-obj-$(CONFIG_MSM_CAMERA) += camera/
-obj-$(CONFIG_INPUT_GPIO) += gpio_axis.o gpio_event.o gpio_input.o gpio_matrix.o gpio_output.o
-
+++ /dev/null
-
-* camera driver uses old V4L API
-
-* coding style in some places is lacking
-
-* gpio_input.c has some features matrix_keypad lacks. They should be
-merged to gpio_input, with gpio_input.c removed
-
-* pmem provides interface for userspace. Needs to be reviewed at least.
-
-* it is probably possible to simplify touchscreen driver using threaded_irq's.
-
-* touchscreen driver should be switched to oficial multitouch API
+++ /dev/null
-comment "Qualcomm MSM Camera And Video"
-
-menuconfig MSM_CAMERA
- bool "Qualcomm MSM camera and video capture support"
- depends on ARCH_MSM && VIDEO_V4L2_COMMON
- help
- Say Y here to enable selecting the video adapters for
- Qualcomm msm camera and video encoding
-
-config MSM_CAMERA_DEBUG
- bool "Qualcomm MSM camera debugging with printk"
- depends on MSM_CAMERA
- help
- Enable printk() debug for msm camera
-
-config MSM_CAMERA_FLASH
- bool "Qualcomm MSM camera flash support"
- depends on MSM_CAMERA && BROKEN
- ---help---
- Enable support for LED flash for msm camera
-
-
-comment "Camera Sensor Selection"
-config MT9T013
- bool "Sensor mt9t013 (BAYER 3M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 3M Bayer Sensor with AutoFocus
-
-config MT9D112
- bool "Sensor mt9d112 (YUV 2M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 2M YUV Sensor
-
-config MT9P012
- bool "Sensor mt9p012 (BAYER 5M)"
- depends on MSM_CAMERA
- ---help---
- MICRON 5M Bayer Sensor with Autofocus
-
-config S5K3E2FX
- bool "Sensor s5k3e2fx (Samsung 5M)"
- depends on MSM_CAMERA
- ---help---
- Samsung 5M with Autofocus
+++ /dev/null
-ccflags-y:=-Idrivers/staging/dream/include
-obj-$(CONFIG_MT9T013) += mt9t013.o mt9t013_reg.o
-obj-$(CONFIG_MT9D112) += mt9d112.o mt9d112_reg.o
-obj-$(CONFIG_MT9P012) += mt9p012_fox.o mt9p012_reg.o
-obj-$(CONFIG_MSM_CAMERA) += msm_camera.o msm_v4l2.o
-obj-$(CONFIG_S5K3E2FX) += s5k3e2fx.o
-obj-$(CONFIG_ARCH_MSM) += msm_vfe7x.o msm_io7x.o
-obj-$(CONFIG_ARCH_QSD) += msm_vfe8x.o msm_vfe8x_proc.o msm_io8x.o
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-/* FIXME: most allocations need not be GFP_ATOMIC */
-/* FIXME: management of mutexes */
-/* FIXME: msm_pmem_region_lookup return values */
-/* FIXME: way too many copy to/from user */
-/* FIXME: does region->active mean free */
-/* FIXME: check limits on command lenghts passed from userspace */
-/* FIXME: __msm_release: which queues should we flush when opencnt != 0 */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <mach/board.h>
-
-#include <linux/fs.h>
-#include <linux/list.h>
-#include <linux/uaccess.h>
-#include <linux/android_pmem.h>
-#include <linux/poll.h>
-#include <media/msm_camera.h>
-#include <mach/camera.h>
-
-#define MSM_MAX_CAMERA_SENSORS 5
-
-#define ERR_USER_COPY(to) pr_err("%s(%d): copy %s user\n", \
- __func__, __LINE__, ((to) ? "to" : "from"))
-#define ERR_COPY_FROM_USER() ERR_USER_COPY(0)
-#define ERR_COPY_TO_USER() ERR_USER_COPY(1)
-
-static struct class *msm_class;
-static dev_t msm_devno;
-static LIST_HEAD(msm_sensors);
-
-#define __CONTAINS(r, v, l, field) ({ \
- typeof(r) __r = r; \
- typeof(v) __v = v; \
- typeof(v) __e = __v + l; \
- int res = __v >= __r->field && \
- __e <= __r->field + __r->len; \
- res; \
-})
-
-#define CONTAINS(r1, r2, field) ({ \
- typeof(r2) __r2 = r2; \
- __CONTAINS(r1, __r2->field, __r2->len, field); \
-})
-
-#define IN_RANGE(r, v, field) ({ \
- typeof(r) __r = r; \
- typeof(v) __vv = v; \
- int res = ((__vv >= __r->field) && \
- (__vv < (__r->field + __r->len))); \
- res; \
-})
-
-#define OVERLAPS(r1, r2, field) ({ \
- typeof(r1) __r1 = r1; \
- typeof(r2) __r2 = r2; \
- typeof(__r2->field) __v = __r2->field; \
- typeof(__v) __e = __v + __r2->len - 1; \
- int res = (IN_RANGE(__r1, __v, field) || \
- IN_RANGE(__r1, __e, field)); \
- res; \
-})
-
-#define MSM_DRAIN_QUEUE_NOSYNC(sync, name) do { \
- struct msm_queue_cmd *qcmd = NULL; \
- CDBG("%s: draining queue "#name"\n", __func__); \
- while (!list_empty(&(sync)->name)) { \
- qcmd = list_first_entry(&(sync)->name, \
- struct msm_queue_cmd, list); \
- list_del_init(&qcmd->list); \
- kfree(qcmd); \
- }; \
-} while (0)
-
-#define MSM_DRAIN_QUEUE(sync, name) do { \
- unsigned long flags; \
- spin_lock_irqsave(&(sync)->name##_lock, flags); \
- MSM_DRAIN_QUEUE_NOSYNC(sync, name); \
- spin_unlock_irqrestore(&(sync)->name##_lock, flags); \
-} while (0)
-
-static int check_overlap(struct hlist_head *ptype,
- unsigned long paddr,
- unsigned long len)
-{
- struct msm_pmem_region *region;
- struct msm_pmem_region t = { .paddr = paddr, .len = len };
- struct hlist_node *node;
-
- hlist_for_each_entry(region, node, ptype, list) {
- if (CONTAINS(region, &t, paddr) ||
- CONTAINS(&t, region, paddr) ||
- OVERLAPS(region, &t, paddr)) {
- printk(KERN_ERR
- " region (PHYS %p len %ld)"
- " clashes with registered region"
- " (paddr %p len %ld)\n",
- (void *)t.paddr, t.len,
- (void *)region->paddr, region->len);
- return -1;
- }
- }
-
- return 0;
-}
-
-static int msm_pmem_table_add(struct hlist_head *ptype,
- struct msm_pmem_info *info)
-{
- struct file *file;
- unsigned long paddr;
- unsigned long vstart;
- unsigned long len;
- int rc;
- struct msm_pmem_region *region;
-
- rc = get_pmem_file(info->fd, &paddr, &vstart, &len, &file);
- if (rc < 0) {
- pr_err("msm_pmem_table_add: get_pmem_file fd %d error %d\n",
- info->fd, rc);
- return rc;
- }
-
- if (check_overlap(ptype, paddr, len) < 0)
- return -EINVAL;
-
- CDBG("%s: type = %d, paddr = 0x%lx, vaddr = 0x%lx\n",
- __func__,
- info->type, paddr, (unsigned long)info->vaddr);
-
- region = kmalloc(sizeof(*region), GFP_KERNEL);
- if (!region)
- return -ENOMEM;
-
- INIT_HLIST_NODE(®ion->list);
-
- region->type = info->type;
- region->vaddr = info->vaddr;
- region->paddr = paddr;
- region->len = len;
- region->file = file;
- region->y_off = info->y_off;
- region->cbcr_off = info->cbcr_off;
- region->fd = info->fd;
- region->active = info->active;
-
- hlist_add_head(&(region->list), ptype);
-
- return 0;
-}
-
-/* return of 0 means failure */
-static uint8_t msm_pmem_region_lookup(struct hlist_head *ptype,
- int pmem_type, struct msm_pmem_region *reg, uint8_t maxcount)
-{
- struct msm_pmem_region *region;
- struct msm_pmem_region *regptr;
- struct hlist_node *node, *n;
-
- uint8_t rc = 0;
-
- regptr = reg;
-
- hlist_for_each_entry_safe(region, node, n, ptype, list) {
- if (region->type == pmem_type && region->active) {
- *regptr = *region;
- rc += 1;
- if (rc >= maxcount)
- break;
- regptr++;
- }
- }
-
- return rc;
-}
-
-static unsigned long msm_pmem_frame_ptov_lookup(struct msm_sync *sync,
- unsigned long pyaddr,
- unsigned long pcbcraddr,
- uint32_t *yoff, uint32_t *cbcroff, int *fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->frame, list) {
- if (pyaddr == (region->paddr + region->y_off) &&
- pcbcraddr == (region->paddr +
- region->cbcr_off) &&
- region->active) {
- /* offset since we could pass vaddr inside
- * a registerd pmem buffer
- */
- *yoff = region->y_off;
- *cbcroff = region->cbcr_off;
- *fd = region->fd;
- region->active = 0;
- return (unsigned long)(region->vaddr);
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_stats_ptov_lookup(struct msm_sync *sync,
- unsigned long addr, int *fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->stats, list) {
- if (addr == region->paddr && region->active) {
- /* offset since we could pass vaddr inside a
- * registered pmem buffer */
- *fd = region->fd;
- region->active = 0;
- return (unsigned long)(region->vaddr);
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_frame_vtop_lookup(struct msm_sync *sync,
- unsigned long buffer,
- uint32_t yoff, uint32_t cbcroff, int fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region,
- node, n, &sync->frame, list) {
- if (((unsigned long)(region->vaddr) == buffer) &&
- (region->y_off == yoff) &&
- (region->cbcr_off == cbcroff) &&
- (region->fd == fd) &&
- (region->active == 0)) {
-
- region->active = 1;
- return region->paddr;
- }
- }
-
- return 0;
-}
-
-static unsigned long msm_pmem_stats_vtop_lookup(
- struct msm_sync *sync,
- unsigned long buffer,
- int fd)
-{
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- hlist_for_each_entry_safe(region, node, n, &sync->stats, list) {
- if (((unsigned long)(region->vaddr) == buffer) &&
- (region->fd == fd) && region->active == 0) {
- region->active = 1;
- return region->paddr;
- }
- }
-
- return 0;
-}
-
-static int __msm_pmem_table_del(struct msm_sync *sync,
- struct msm_pmem_info *pinfo)
-{
- int rc = 0;
- struct msm_pmem_region *region;
- struct hlist_node *node, *n;
-
- switch (pinfo->type) {
- case MSM_PMEM_OUTPUT1:
- case MSM_PMEM_OUTPUT2:
- case MSM_PMEM_THUMBAIL:
- case MSM_PMEM_MAINIMG:
- case MSM_PMEM_RAW_MAINIMG:
- hlist_for_each_entry_safe(region, node, n,
- &sync->frame, list) {
-
- if (pinfo->type == region->type &&
- pinfo->vaddr == region->vaddr &&
- pinfo->fd == region->fd) {
- hlist_del(node);
- put_pmem_file(region->file);
- kfree(region);
- }
- }
- break;
-
- case MSM_PMEM_AEC_AWB:
- case MSM_PMEM_AF:
- hlist_for_each_entry_safe(region, node, n,
- &sync->stats, list) {
-
- if (pinfo->type == region->type &&
- pinfo->vaddr == region->vaddr &&
- pinfo->fd == region->fd) {
- hlist_del(node);
- put_pmem_file(region->file);
- kfree(region);
- }
- }
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int msm_pmem_table_del(struct msm_sync *sync, void __user *arg)
-{
- struct msm_pmem_info info;
-
- if (copy_from_user(&info, arg, sizeof(info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_pmem_table_del(sync, &info);
-}
-
-static int __msm_get_frame(struct msm_sync *sync,
- struct msm_frame *frame)
-{
- unsigned long flags;
- int rc = 0;
-
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_vfe_phy_info *pphy;
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- if (!list_empty(&sync->prev_frame_q)) {
- qcmd = list_first_entry(&sync->prev_frame_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- }
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
-
- if (!qcmd) {
- pr_err("%s: no preview frame.\n", __func__);
- return -EAGAIN;
- }
-
- pphy = (struct msm_vfe_phy_info *)(qcmd->command);
-
- frame->buffer =
- msm_pmem_frame_ptov_lookup(sync,
- pphy->y_phy,
- pphy->cbcr_phy, &(frame->y_off),
- &(frame->cbcr_off), &(frame->fd));
- if (!frame->buffer) {
- pr_err("%s: cannot get frame, invalid lookup address "
- "y=%x cbcr=%x offset=%d\n",
- __func__,
- pphy->y_phy,
- pphy->cbcr_phy,
- frame->y_off);
- rc = -EINVAL;
- }
-
- CDBG("__msm_get_frame: y=0x%x, cbcr=0x%x, qcmd=0x%x, virt_addr=0x%x\n",
- pphy->y_phy, pphy->cbcr_phy, (int) qcmd, (int) frame->buffer);
-
- kfree(qcmd);
- return rc;
-}
-
-static int msm_get_frame(struct msm_sync *sync, void __user *arg)
-{
- int rc = 0;
- struct msm_frame frame;
-
- if (copy_from_user(&frame,
- arg,
- sizeof(struct msm_frame))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- rc = __msm_get_frame(sync, &frame);
- if (rc < 0)
- return rc;
-
- if (sync->croplen) {
- if (frame.croplen > sync->croplen) {
- pr_err("msm_get_frame: invalid frame croplen %d\n",
- frame.croplen);
- return -EINVAL;
- }
-
- if (copy_to_user((void *)frame.cropinfo,
- sync->cropinfo,
- sync->croplen)) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- }
-
- if (copy_to_user((void *)arg,
- &frame, sizeof(struct msm_frame))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
- CDBG("Got frame!!!\n");
-
- return rc;
-}
-
-static int msm_enable_vfe(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
- struct camera_enable_cmd cfg;
-
- if (copy_from_user(&cfg,
- arg,
- sizeof(struct camera_enable_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (sync->vfefn.vfe_enable)
- rc = sync->vfefn.vfe_enable(&cfg);
-
- CDBG("msm_enable_vfe: returned rc = %d\n", rc);
- return rc;
-}
-
-static int msm_disable_vfe(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
- struct camera_enable_cmd cfg;
-
- if (copy_from_user(&cfg,
- arg,
- sizeof(struct camera_enable_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (sync->vfefn.vfe_disable)
- rc = sync->vfefn.vfe_disable(&cfg, NULL);
-
- CDBG("msm_disable_vfe: returned rc = %d\n", rc);
- return rc;
-}
-
-static struct msm_queue_cmd *__msm_control(struct msm_sync *sync,
- struct msm_control_device_queue *queue,
- struct msm_queue_cmd *qcmd,
- int timeout)
-{
- unsigned long flags;
- int rc;
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->msg_event_q);
- /* wake up config thread */
- wake_up(&sync->msg_event_wait);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-
- if (!queue)
- return NULL;
-
- /* wait for config status */
- rc = wait_event_interruptible_timeout(
- queue->ctrl_status_wait,
- !list_empty_careful(&queue->ctrl_status_q),
- timeout);
- if (list_empty_careful(&queue->ctrl_status_q)) {
- if (!rc)
- rc = -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_control: wait_event error %d\n", rc);
-#if 0
- /* This is a bit scary. If we time out too early, we
- * will free qcmd at the end of this function, and the
- * dsp may do the same when it does respond, so we
- * remove the message from the source queue.
- */
- pr_err("%s: error waiting for ctrl_status_q: %d\n",
- __func__, rc);
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-#endif
- return ERR_PTR(rc);
- }
- }
-
- /* control command status is ready */
- spin_lock_irqsave(&queue->ctrl_status_q_lock, flags);
- BUG_ON(list_empty(&queue->ctrl_status_q));
- qcmd = list_first_entry(&queue->ctrl_status_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&queue->ctrl_status_q_lock, flags);
-
- return qcmd;
-}
-
-static int msm_control(struct msm_control_device *ctrl_pmsm,
- int block,
- void __user *arg)
-{
- int rc = 0;
-
- struct msm_sync *sync = ctrl_pmsm->pmsm->sync;
- struct msm_ctrl_cmd udata, *ctrlcmd;
- struct msm_queue_cmd *qcmd = NULL, *qcmd_temp;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd) + udata.length,
- GFP_KERNEL);
- if (!qcmd) {
- pr_err("msm_control: cannot allocate buffer\n");
- rc = -ENOMEM;
- goto end;
- }
-
- qcmd->type = MSM_CAM_Q_CTRL;
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- *ctrlcmd = udata;
- ctrlcmd->value = ctrlcmd + 1;
-
- if (udata.length) {
- if (copy_from_user(ctrlcmd->value,
- udata.value, udata.length)) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
- }
-
- if (!block) {
- /* qcmd will be set to NULL */
- qcmd = __msm_control(sync, NULL, qcmd, 0);
- goto end;
- }
-
- qcmd_temp = __msm_control(sync,
- &ctrl_pmsm->ctrl_q,
- qcmd, MAX_SCHEDULE_TIMEOUT);
-
- if (IS_ERR(qcmd_temp)) {
- rc = PTR_ERR(qcmd_temp);
- goto end;
- }
- qcmd = qcmd_temp;
-
- if (qcmd->command) {
- void __user *to = udata.value;
- udata = *(struct msm_ctrl_cmd *)qcmd->command;
- if (udata.length > 0) {
- if (copy_to_user(to,
- udata.value,
- udata.length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto end;
- }
- }
- udata.value = to;
-
- if (copy_to_user((void *)arg, &udata,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto end;
- }
- }
-
-end:
- /* Note: if we get here as a result of an error, we will free the
- * qcmd that we kmalloc() in this function. When we come here as
- * a result of a successful completion, we are freeing the qcmd that
- * we dequeued from queue->ctrl_status_q.
- */
- kfree(qcmd);
-
- CDBG("msm_control: end rc = %d\n", rc);
- return rc;
-}
-
-static int msm_get_stats(struct msm_sync *sync, void __user *arg)
-{
- unsigned long flags;
- int timeout;
- int rc = 0;
-
- struct msm_stats_event_ctrl se;
-
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_ctrl_cmd *ctrl = NULL;
- struct msm_vfe_resp *data = NULL;
- struct msm_stats_buf stats;
-
- if (copy_from_user(&se, arg,
- sizeof(struct msm_stats_event_ctrl))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- timeout = (int)se.timeout_ms;
-
- CDBG("msm_get_stats timeout %d\n", timeout);
- rc = wait_event_interruptible_timeout(
- sync->msg_event_wait,
- !list_empty_careful(&sync->msg_event_q),
- msecs_to_jiffies(timeout));
- if (list_empty_careful(&sync->msg_event_q)) {
- if (rc == 0)
- rc = -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_get_stats error %d\n", rc);
- return rc;
- }
- }
- CDBG("msm_get_stats returned from wait: %d\n", rc);
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- BUG_ON(list_empty(&sync->msg_event_q));
- qcmd = list_first_entry(&sync->msg_event_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
-
- CDBG("=== received from DSP === %d\n", qcmd->type);
-
- switch (qcmd->type) {
- case MSM_CAM_Q_VFE_EVT:
- case MSM_CAM_Q_VFE_MSG:
- data = (struct msm_vfe_resp *)(qcmd->command);
-
- /* adsp event and message */
- se.resptype = MSM_CAM_RESP_STAT_EVT_MSG;
-
- /* 0 - msg from aDSP, 1 - event from mARM */
- se.stats_event.type = data->evt_msg.type;
- se.stats_event.msg_id = data->evt_msg.msg_id;
- se.stats_event.len = data->evt_msg.len;
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", se.stats_event.len);
- CDBG("msg_id = %d\n", se.stats_event.msg_id);
-
- if ((data->type == VFE_MSG_STATS_AF) ||
- (data->type == VFE_MSG_STATS_WE)) {
-
- stats.buffer =
- msm_pmem_stats_ptov_lookup(sync,
- data->phy.sbuf_phy,
- &(stats.fd));
- if (!stats.buffer) {
- pr_err("%s: msm_pmem_stats_ptov_lookup error\n",
- __func__);
- rc = -EINVAL;
- goto failure;
- }
-
- if (copy_to_user((void *)(se.stats_event.data),
- &stats,
- sizeof(struct msm_stats_buf))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- } else if ((data->evt_msg.len > 0) &&
- (data->type == VFE_MSG_GENERAL)) {
- if (copy_to_user((void *)(se.stats_event.data),
- data->evt_msg.data,
- data->evt_msg.len)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
- } else if (data->type == VFE_MSG_OUTPUT1 ||
- data->type == VFE_MSG_OUTPUT2) {
- if (copy_to_user((void *)(se.stats_event.data),
- data->extdata,
- data->extlen)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
- } else if (data->type == VFE_MSG_SNAPSHOT && sync->pict_pp) {
- struct msm_postproc buf;
- struct msm_pmem_region region;
- buf.fmnum = msm_pmem_region_lookup(&sync->frame,
- MSM_PMEM_MAINIMG,
- ®ion, 1);
- if (buf.fmnum == 1) {
- buf.fmain.buffer = (unsigned long)region.vaddr;
- buf.fmain.y_off = region.y_off;
- buf.fmain.cbcr_off = region.cbcr_off;
- buf.fmain.fd = region.fd;
- } else {
- buf.fmnum = msm_pmem_region_lookup(&sync->frame,
- MSM_PMEM_RAW_MAINIMG,
- ®ion, 1);
- if (buf.fmnum == 1) {
- buf.fmain.path = MSM_FRAME_PREV_2;
- buf.fmain.buffer =
- (unsigned long)region.vaddr;
- buf.fmain.fd = region.fd;
- } else {
- pr_err("%s: pmem lookup failed\n",
- __func__);
- rc = -EINVAL;
- }
- }
-
- if (copy_to_user((void *)(se.stats_event.data), &buf,
- sizeof(buf))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- CDBG("snapshot copy_to_user!\n");
- }
- break;
-
- case MSM_CAM_Q_CTRL:
- /* control command from control thread */
- ctrl = (struct msm_ctrl_cmd *)(qcmd->command);
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", ctrl->length);
-
- if (ctrl->length > 0) {
- if (copy_to_user((void *)(se.ctrl_cmd.value),
- ctrl->value,
- ctrl->length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- }
-
- se.resptype = MSM_CAM_RESP_CTRL;
-
- /* what to control */
- se.ctrl_cmd.type = ctrl->type;
- se.ctrl_cmd.length = ctrl->length;
- se.ctrl_cmd.resp_fd = ctrl->resp_fd;
- break;
-
- case MSM_CAM_Q_V4L2_REQ:
- /* control command from v4l2 client */
- ctrl = (struct msm_ctrl_cmd *)(qcmd->command);
-
- CDBG("msm_get_stats, qcmd->type = %d\n", qcmd->type);
- CDBG("length = %d\n", ctrl->length);
-
- if (ctrl->length > 0) {
- if (copy_to_user((void *)(se.ctrl_cmd.value),
- ctrl->value, ctrl->length)) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- goto failure;
- }
- }
-
- /* 2 tells config thread this is v4l2 request */
- se.resptype = MSM_CAM_RESP_V4L2;
-
- /* what to control */
- se.ctrl_cmd.type = ctrl->type;
- se.ctrl_cmd.length = ctrl->length;
- break;
-
- default:
- rc = -EFAULT;
- goto failure;
- } /* switch qcmd->type */
-
- if (copy_to_user((void *)arg, &se, sizeof(se))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
-failure:
- kfree(qcmd);
-
- CDBG("msm_get_stats: %d\n", rc);
- return rc;
-}
-
-static int msm_ctrl_cmd_done(struct msm_control_device *ctrl_pmsm,
- void __user *arg)
-{
- unsigned long flags;
- int rc = 0;
-
- struct msm_ctrl_cmd udata, *ctrlcmd;
- struct msm_queue_cmd *qcmd = NULL;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto end;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd) + udata.length,
- GFP_KERNEL);
- if (!qcmd) {
- rc = -ENOMEM;
- goto end;
- }
-
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- *ctrlcmd = udata;
- if (udata.length > 0) {
- ctrlcmd->value = ctrlcmd + 1;
- if (copy_from_user(ctrlcmd->value,
- (void *)udata.value,
- udata.length)) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- kfree(qcmd);
- goto end;
- }
- } else
- ctrlcmd->value = NULL;
-
-end:
- CDBG("msm_ctrl_cmd_done: end rc = %d\n", rc);
- if (rc == 0) {
- /* wake up control thread */
- spin_lock_irqsave(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock, flags);
- list_add_tail(&qcmd->list, &ctrl_pmsm->ctrl_q.ctrl_status_q);
- wake_up(&ctrl_pmsm->ctrl_q.ctrl_status_wait);
- spin_unlock_irqrestore(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock, flags);
- }
-
- return rc;
-}
-
-static int msm_config_vfe(struct msm_sync *sync, void __user *arg)
-{
- struct msm_vfe_cfg_cmd cfgcmd;
- struct msm_pmem_region region[8];
- struct axidata axi_data;
- void *data = NULL;
- int rc = -EIO;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- if (copy_from_user(&cfgcmd, arg, sizeof(cfgcmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- switch (cfgcmd.cmd_type) {
- case CMD_STATS_ENABLE:
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats,
- MSM_PMEM_AEC_AWB, ®ion[0],
- NUM_WB_EXP_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- data = &axi_data;
- break;
- case CMD_STATS_AF_ENABLE:
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats,
- MSM_PMEM_AF, ®ion[0],
- NUM_AF_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- data = &axi_data;
- break;
- case CMD_GENERAL:
- case CMD_STATS_DISABLE:
- break;
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd.cmd_type);
- return -EINVAL;
- }
-
-
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(&cfgcmd, data);
-
- return rc;
-}
-
-static int msm_frame_axi_cfg(struct msm_sync *sync,
- struct msm_vfe_cfg_cmd *cfgcmd)
-{
- int rc = -EIO;
- struct axidata axi_data;
- void *data = &axi_data;
- struct msm_pmem_region region[8];
- int pmem_type;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- switch (cfgcmd->cmd_type) {
- case CMD_AXI_CFG_OUT1:
- pmem_type = MSM_PMEM_OUTPUT1;
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- pmem_type = MSM_PMEM_OUTPUT2;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2:
- pmem_type = MSM_PMEM_THUMBAIL;
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
-
- pmem_type = MSM_PMEM_MAINIMG;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[axi_data.bufnum1], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_RAW_PICT_AXI_CFG:
- pmem_type = MSM_PMEM_RAW_MAINIMG;
- axi_data.bufnum2 =
- msm_pmem_region_lookup(&sync->frame, pmem_type,
- ®ion[0], 8);
- if (!axi_data.bufnum2) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- break;
-
- case CMD_GENERAL:
- data = NULL;
- break;
-
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd->cmd_type);
- return -EINVAL;
- }
-
- axi_data.region = ®ion[0];
-
- /* send the AXI configuration command to driver */
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(cfgcmd, data);
-
- return rc;
-}
-
-static int msm_get_sensor_info(struct msm_sync *sync, void __user *arg)
-{
- int rc = 0;
- struct msm_camsensor_info info;
- struct msm_camera_sensor_info *sdata;
-
- if (copy_from_user(&info,
- arg,
- sizeof(struct msm_camsensor_info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- sdata = sync->pdev->dev.platform_data;
- CDBG("sensor_name %s\n", sdata->sensor_name);
-
- memcpy(&info.name[0],
- sdata->sensor_name,
- MAX_SENSOR_NAME);
- info.flash_enabled = sdata->flash_type != MSM_CAMERA_FLASH_NONE;
-
- /* copy back to user space */
- if (copy_to_user((void *)arg,
- &info,
- sizeof(struct msm_camsensor_info))) {
- ERR_COPY_TO_USER();
- rc = -EFAULT;
- }
-
- return rc;
-}
-
-static int __msm_put_frame_buf(struct msm_sync *sync,
- struct msm_frame *pb)
-{
- unsigned long pphy;
- struct msm_vfe_cfg_cmd cfgcmd;
-
- int rc = -EIO;
-
- pphy = msm_pmem_frame_vtop_lookup(sync,
- pb->buffer,
- pb->y_off, pb->cbcr_off, pb->fd);
-
- if (pphy != 0) {
- CDBG("rel: vaddr = 0x%lx, paddr = 0x%lx\n",
- pb->buffer, pphy);
- cfgcmd.cmd_type = CMD_FRAME_BUF_RELEASE;
- cfgcmd.value = (void *)pb;
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(&cfgcmd, &pphy);
- } else {
- pr_err("%s: msm_pmem_frame_vtop_lookup failed\n",
- __func__);
- rc = -EINVAL;
- }
-
- return rc;
-}
-
-static int msm_put_frame_buffer(struct msm_sync *sync, void __user *arg)
-{
- struct msm_frame buf_t;
-
- if (copy_from_user(&buf_t,
- arg,
- sizeof(struct msm_frame))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_put_frame_buf(sync, &buf_t);
-}
-
-static int __msm_register_pmem(struct msm_sync *sync,
- struct msm_pmem_info *pinfo)
-{
- int rc = 0;
-
- switch (pinfo->type) {
- case MSM_PMEM_OUTPUT1:
- case MSM_PMEM_OUTPUT2:
- case MSM_PMEM_THUMBAIL:
- case MSM_PMEM_MAINIMG:
- case MSM_PMEM_RAW_MAINIMG:
- rc = msm_pmem_table_add(&sync->frame, pinfo);
- break;
-
- case MSM_PMEM_AEC_AWB:
- case MSM_PMEM_AF:
- rc = msm_pmem_table_add(&sync->stats, pinfo);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int msm_register_pmem(struct msm_sync *sync, void __user *arg)
-{
- struct msm_pmem_info info;
-
- if (copy_from_user(&info, arg, sizeof(info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- return __msm_register_pmem(sync, &info);
-}
-
-static int msm_stats_axi_cfg(struct msm_sync *sync,
- struct msm_vfe_cfg_cmd *cfgcmd)
-{
- int rc = -EIO;
- struct axidata axi_data;
- void *data = &axi_data;
-
- struct msm_pmem_region region[3];
- int pmem_type = MSM_PMEM_MAX;
-
- memset(&axi_data, 0, sizeof(axi_data));
-
- switch (cfgcmd->cmd_type) {
- case CMD_STATS_AXI_CFG:
- pmem_type = MSM_PMEM_AEC_AWB;
- break;
- case CMD_STATS_AF_AXI_CFG:
- pmem_type = MSM_PMEM_AF;
- break;
- case CMD_GENERAL:
- data = NULL;
- break;
- default:
- pr_err("%s: unknown command type %d\n",
- __func__, cfgcmd->cmd_type);
- return -EINVAL;
- }
-
- if (cfgcmd->cmd_type != CMD_GENERAL) {
- axi_data.bufnum1 =
- msm_pmem_region_lookup(&sync->stats, pmem_type,
- ®ion[0], NUM_WB_EXP_STAT_OUTPUT_BUFFERS);
- if (!axi_data.bufnum1) {
- pr_err("%s: pmem region lookup error\n", __func__);
- return -EINVAL;
- }
- axi_data.region = ®ion[0];
- }
-
- /* send the AEC/AWB STATS configuration command to driver */
- if (sync->vfefn.vfe_config)
- rc = sync->vfefn.vfe_config(cfgcmd, &axi_data);
-
- return rc;
-}
-
-static int msm_put_stats_buffer(struct msm_sync *sync, void __user *arg)
-{
- int rc = -EIO;
-
- struct msm_stats_buf buf;
- unsigned long pphy;
- struct msm_vfe_cfg_cmd cfgcmd;
-
- if (copy_from_user(&buf, arg,
- sizeof(struct msm_stats_buf))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- CDBG("msm_put_stats_buffer\n");
- pphy = msm_pmem_stats_vtop_lookup(sync, buf.buffer, buf.fd);
-
- if (pphy != 0) {
- if (buf.type == STAT_AEAW)
- cfgcmd.cmd_type = CMD_STATS_BUF_RELEASE;
- else if (buf.type == STAT_AF)
- cfgcmd.cmd_type = CMD_STATS_AF_BUF_RELEASE;
- else {
- pr_err("%s: invalid buf type %d\n",
- __func__,
- buf.type);
- rc = -EINVAL;
- goto put_done;
- }
-
- cfgcmd.value = (void *)&buf;
-
- if (sync->vfefn.vfe_config) {
- rc = sync->vfefn.vfe_config(&cfgcmd, &pphy);
- if (rc < 0)
- pr_err("msm_put_stats_buffer: "\
- "vfe_config err %d\n", rc);
- } else
- pr_err("msm_put_stats_buffer: vfe_config is NULL\n");
- } else {
- pr_err("msm_put_stats_buffer: NULL physical address\n");
- rc = -EINVAL;
- }
-
-put_done:
- return rc;
-}
-
-static int msm_axi_config(struct msm_sync *sync, void __user *arg)
-{
- struct msm_vfe_cfg_cmd cfgcmd;
-
- if (copy_from_user(&cfgcmd, arg, sizeof(cfgcmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- switch (cfgcmd.cmd_type) {
- case CMD_AXI_CFG_OUT1:
- case CMD_AXI_CFG_OUT2:
- case CMD_AXI_CFG_SNAP_O1_AND_O2:
- case CMD_RAW_PICT_AXI_CFG:
- return msm_frame_axi_cfg(sync, &cfgcmd);
-
- case CMD_STATS_AXI_CFG:
- case CMD_STATS_AF_AXI_CFG:
- return msm_stats_axi_cfg(sync, &cfgcmd);
-
- default:
- pr_err("%s: unknown command type %d\n",
- __func__,
- cfgcmd.cmd_type);
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int __msm_get_pic(struct msm_sync *sync, struct msm_ctrl_cmd *ctrl)
-{
- unsigned long flags;
- int rc = 0;
- int tm;
-
- struct msm_queue_cmd *qcmd = NULL;
-
- tm = (int)ctrl->timeout_ms;
-
- rc = wait_event_interruptible_timeout(
- sync->pict_frame_wait,
- !list_empty_careful(&sync->pict_frame_q),
- msecs_to_jiffies(tm));
- if (list_empty_careful(&sync->pict_frame_q)) {
- if (rc == 0)
- return -ETIMEDOUT;
- if (rc < 0) {
- pr_err("msm_camera_get_picture, rc = %d\n", rc);
- return rc;
- }
- }
-
- spin_lock_irqsave(&sync->pict_frame_q_lock, flags);
- BUG_ON(list_empty(&sync->pict_frame_q));
- qcmd = list_first_entry(&sync->pict_frame_q,
- struct msm_queue_cmd, list);
- list_del_init(&qcmd->list);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
-
- if (qcmd->command != NULL) {
- struct msm_ctrl_cmd *q =
- (struct msm_ctrl_cmd *)qcmd->command;
- ctrl->type = q->type;
- ctrl->status = q->status;
- } else {
- ctrl->type = -1;
- ctrl->status = -1;
- }
-
- kfree(qcmd);
- return rc;
-}
-
-static int msm_get_pic(struct msm_sync *sync, void __user *arg)
-{
- struct msm_ctrl_cmd ctrlcmd_t;
- int rc;
-
- if (copy_from_user(&ctrlcmd_t,
- arg,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- rc = __msm_get_pic(sync, &ctrlcmd_t);
- if (rc < 0)
- return rc;
-
- if (sync->croplen) {
- if (ctrlcmd_t.length < sync->croplen) {
- pr_err("msm_get_pic: invalid len %d\n",
- ctrlcmd_t.length);
- return -EINVAL;
- }
- if (copy_to_user(ctrlcmd_t.value,
- sync->cropinfo,
- sync->croplen)) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- }
-
- if (copy_to_user((void *)arg,
- &ctrlcmd_t,
- sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_TO_USER();
- return -EFAULT;
- }
- return 0;
-}
-
-static int msm_set_crop(struct msm_sync *sync, void __user *arg)
-{
- struct crop_info crop;
-
- if (copy_from_user(&crop,
- arg,
- sizeof(struct crop_info))) {
- ERR_COPY_FROM_USER();
- return -EFAULT;
- }
-
- if (!sync->croplen) {
- sync->cropinfo = kmalloc(crop.len, GFP_KERNEL);
- if (!sync->cropinfo)
- return -ENOMEM;
- } else if (sync->croplen < crop.len)
- return -EINVAL;
-
- if (copy_from_user(sync->cropinfo,
- crop.info,
- crop.len)) {
- ERR_COPY_FROM_USER();
- kfree(sync->cropinfo);
- return -EFAULT;
- }
-
- sync->croplen = crop.len;
-
- return 0;
-}
-
-static int msm_pict_pp_done(struct msm_sync *sync, void __user *arg)
-{
- struct msm_ctrl_cmd udata;
- struct msm_ctrl_cmd *ctrlcmd = NULL;
- struct msm_queue_cmd *qcmd = NULL;
- unsigned long flags;
- int rc = 0;
-
- if (!sync->pict_pp)
- return -EINVAL;
-
- if (copy_from_user(&udata, arg, sizeof(struct msm_ctrl_cmd))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- goto pp_fail;
- }
-
- qcmd = kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_ctrl_cmd),
- GFP_KERNEL);
- if (!qcmd) {
- rc = -ENOMEM;
- goto pp_fail;
- }
-
- qcmd->type = MSM_CAM_Q_VFE_MSG;
- qcmd->command = ctrlcmd = (struct msm_ctrl_cmd *)(qcmd + 1);
- memset(ctrlcmd, 0, sizeof(struct msm_ctrl_cmd));
- ctrlcmd->type = udata.type;
- ctrlcmd->status = udata.status;
-
- spin_lock_irqsave(&sync->pict_frame_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->pict_frame_q);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
- wake_up(&sync->pict_frame_wait);
-
-pp_fail:
- return rc;
-}
-
-static long msm_ioctl_common(struct msm_device *pmsm,
- unsigned int cmd,
- void __user *argp)
-{
- CDBG("msm_ioctl_common\n");
- switch (cmd) {
- case MSM_CAM_IOCTL_REGISTER_PMEM:
- return msm_register_pmem(pmsm->sync, argp);
- case MSM_CAM_IOCTL_UNREGISTER_PMEM:
- return msm_pmem_table_del(pmsm->sync, argp);
- default:
- return -EINVAL;
- }
-}
-
-static long msm_ioctl_config(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_device *pmsm = filep->private_data;
-
- CDBG("msm_ioctl_config cmd = %d\n", _IOC_NR(cmd));
-
- switch (cmd) {
- case MSM_CAM_IOCTL_GET_SENSOR_INFO:
- rc = msm_get_sensor_info(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_CONFIG_VFE:
- /* Coming from config thread for update */
- rc = msm_config_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_GET_STATS:
- /* Coming from config thread wait
- * for vfe statistics and control requests */
- rc = msm_get_stats(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_ENABLE_VFE:
- /* This request comes from control thread:
- * enable either QCAMTASK or VFETASK */
- rc = msm_enable_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_DISABLE_VFE:
- /* This request comes from control thread:
- * disable either QCAMTASK or VFETASK */
- rc = msm_disable_vfe(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_VFE_APPS_RESET:
- msm_camio_vfe_blk_reset();
- rc = 0;
- break;
-
- case MSM_CAM_IOCTL_RELEASE_STATS_BUFFER:
- rc = msm_put_stats_buffer(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_AXI_CONFIG:
- rc = msm_axi_config(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_SET_CROP:
- rc = msm_set_crop(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_PICT_PP: {
- uint8_t enable;
- if (copy_from_user(&enable, argp, sizeof(enable))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else {
- pmsm->sync->pict_pp = enable;
- rc = 0;
- }
- break;
- }
-
- case MSM_CAM_IOCTL_PICT_PP_DONE:
- rc = msm_pict_pp_done(pmsm->sync, argp);
- break;
-
- case MSM_CAM_IOCTL_SENSOR_IO_CFG:
- rc = pmsm->sync->sctrl.s_config(argp);
- break;
-
- case MSM_CAM_IOCTL_FLASH_LED_CFG: {
- uint32_t led_state;
- if (copy_from_user(&led_state, argp, sizeof(led_state))) {
- ERR_COPY_FROM_USER();
- rc = -EFAULT;
- } else
- rc = msm_camera_flash_set_led_state(led_state);
- break;
- }
-
- default:
- rc = msm_ioctl_common(pmsm, cmd, argp);
- break;
- }
-
- CDBG("msm_ioctl_config cmd = %d DONE\n", _IOC_NR(cmd));
- return rc;
-}
-
-static int msm_unblock_poll_frame(struct msm_sync *);
-
-static long msm_ioctl_frame(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_device *pmsm = filep->private_data;
-
-
- switch (cmd) {
- case MSM_CAM_IOCTL_GETFRAME:
- /* Coming from frame thread to get frame
- * after SELECT is done */
- rc = msm_get_frame(pmsm->sync, argp);
- break;
- case MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER:
- rc = msm_put_frame_buffer(pmsm->sync, argp);
- break;
- case MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME:
- rc = msm_unblock_poll_frame(pmsm->sync);
- break;
- default:
- break;
- }
-
- return rc;
-}
-
-
-static long msm_ioctl_control(struct file *filep, unsigned int cmd,
- unsigned long arg)
-{
- int rc = -EINVAL;
- void __user *argp = (void __user *)arg;
- struct msm_control_device *ctrl_pmsm = filep->private_data;
- struct msm_device *pmsm = ctrl_pmsm->pmsm;
-
- switch (cmd) {
- case MSM_CAM_IOCTL_CTRL_COMMAND:
- /* Coming from control thread, may need to wait for
- * command status */
- rc = msm_control(ctrl_pmsm, 1, argp);
- break;
- case MSM_CAM_IOCTL_CTRL_COMMAND_2:
- /* Sends a message, returns immediately */
- rc = msm_control(ctrl_pmsm, 0, argp);
- break;
- case MSM_CAM_IOCTL_CTRL_CMD_DONE:
- /* Config thread calls the control thread to notify it
- * of the result of a MSM_CAM_IOCTL_CTRL_COMMAND.
- */
- rc = msm_ctrl_cmd_done(ctrl_pmsm, argp);
- break;
- case MSM_CAM_IOCTL_GET_PICTURE:
- rc = msm_get_pic(pmsm->sync, argp);
- break;
- default:
- rc = msm_ioctl_common(pmsm, cmd, argp);
- break;
- }
-
- return rc;
-}
-
-static int __msm_release(struct msm_sync *sync)
-{
- struct msm_pmem_region *region;
- struct hlist_node *hnode;
- struct hlist_node *n;
-
- mutex_lock(&sync->lock);
- if (sync->opencnt)
- sync->opencnt--;
-
- if (!sync->opencnt) {
- /* need to clean up system resource */
- if (sync->vfefn.vfe_release)
- sync->vfefn.vfe_release(sync->pdev);
-
- if (sync->cropinfo) {
- kfree(sync->cropinfo);
- sync->cropinfo = NULL;
- sync->croplen = 0;
- }
-
- hlist_for_each_entry_safe(region, hnode, n,
- &sync->frame, list) {
- hlist_del(hnode);
- put_pmem_file(region->file);
- kfree(region);
- }
-
- hlist_for_each_entry_safe(region, hnode, n,
- &sync->stats, list) {
- hlist_del(hnode);
- put_pmem_file(region->file);
- kfree(region);
- }
-
- MSM_DRAIN_QUEUE(sync, msg_event_q);
- MSM_DRAIN_QUEUE(sync, prev_frame_q);
- MSM_DRAIN_QUEUE(sync, pict_frame_q);
-
- sync->sctrl.s_release();
-
- sync->apps_id = NULL;
- CDBG("msm_release completed!\n");
- }
- mutex_unlock(&sync->lock);
-
- return 0;
-}
-
-static int msm_release_config(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_device *pmsm = filep->private_data;
- printk("msm_camera: RELEASE %s\n", filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- atomic_set(&pmsm->opened, 0);
- return rc;
-}
-
-static int msm_release_control(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_control_device *ctrl_pmsm = filep->private_data;
- struct msm_device *pmsm = ctrl_pmsm->pmsm;
- printk(KERN_INFO "msm_camera: RELEASE %s\n",
- filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- if (!rc) {
- MSM_DRAIN_QUEUE(&ctrl_pmsm->ctrl_q, ctrl_status_q);
- MSM_DRAIN_QUEUE(pmsm->sync, pict_frame_q);
- }
- kfree(ctrl_pmsm);
- return rc;
-}
-
-static int msm_release_frame(struct inode *node, struct file *filep)
-{
- int rc;
- struct msm_device *pmsm = filep->private_data;
- printk(KERN_INFO "msm_camera: RELEASE %s\n",
- filep->f_path.dentry->d_name.name);
- rc = __msm_release(pmsm->sync);
- if (!rc) {
- MSM_DRAIN_QUEUE(pmsm->sync, prev_frame_q);
- atomic_set(&pmsm->opened, 0);
- }
- return rc;
-}
-
-static int msm_unblock_poll_frame(struct msm_sync *sync)
-{
- unsigned long flags;
- CDBG("msm_unblock_poll_frame\n");
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- sync->unblock_poll_frame = 1;
- wake_up(&sync->prev_frame_wait);
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
- return 0;
-}
-
-static unsigned int __msm_poll_frame(struct msm_sync *sync,
- struct file *filep,
- struct poll_table_struct *pll_table)
-{
- int rc = 0;
- unsigned long flags;
-
- poll_wait(filep, &sync->prev_frame_wait, pll_table);
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- if (!list_empty_careful(&sync->prev_frame_q))
- /* frame ready */
- rc = POLLIN | POLLRDNORM;
- if (sync->unblock_poll_frame) {
- CDBG("%s: sync->unblock_poll_frame is true\n", __func__);
- rc |= POLLPRI;
- sync->unblock_poll_frame = 0;
- }
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
-
- return rc;
-}
-
-static unsigned int msm_poll_frame(struct file *filep,
- struct poll_table_struct *pll_table)
-{
- struct msm_device *pmsm = filep->private_data;
- return __msm_poll_frame(pmsm->sync, filep, pll_table);
-}
-
-/*
- * This function executes in interrupt context.
- */
-
-static void *msm_vfe_sync_alloc(int size,
- void *syncdata __attribute__((unused)))
-{
- struct msm_queue_cmd *qcmd =
- kmalloc(sizeof(struct msm_queue_cmd) + size, GFP_ATOMIC);
- return qcmd ? qcmd + 1 : NULL;
-}
-
-/*
- * This function executes in interrupt context.
- */
-
-static void msm_vfe_sync(struct msm_vfe_resp *vdata,
- enum msm_queue qtype, void *syncdata)
-{
- struct msm_queue_cmd *qcmd = NULL;
- struct msm_queue_cmd *qcmd_frame = NULL;
- struct msm_vfe_phy_info *fphy;
-
- unsigned long flags;
- struct msm_sync *sync = (struct msm_sync *)syncdata;
- if (!sync) {
- pr_err("msm_camera: no context in dsp callback.\n");
- return;
- }
-
- qcmd = ((struct msm_queue_cmd *)vdata) - 1;
- qcmd->type = qtype;
-
- if (qtype == MSM_CAM_Q_VFE_MSG) {
- switch (vdata->type) {
- case VFE_MSG_OUTPUT1:
- case VFE_MSG_OUTPUT2:
- qcmd_frame =
- kmalloc(sizeof(struct msm_queue_cmd) +
- sizeof(struct msm_vfe_phy_info),
- GFP_ATOMIC);
- if (!qcmd_frame)
- goto mem_fail;
- fphy = (struct msm_vfe_phy_info *)(qcmd_frame + 1);
- *fphy = vdata->phy;
-
- qcmd_frame->type = MSM_CAM_Q_VFE_MSG;
- qcmd_frame->command = fphy;
-
- CDBG("qcmd_frame= 0x%x phy_y= 0x%x, phy_cbcr= 0x%x\n",
- (int) qcmd_frame, fphy->y_phy, fphy->cbcr_phy);
-
- spin_lock_irqsave(&sync->prev_frame_q_lock, flags);
- list_add_tail(&qcmd_frame->list, &sync->prev_frame_q);
- wake_up(&sync->prev_frame_wait);
- spin_unlock_irqrestore(&sync->prev_frame_q_lock, flags);
- CDBG("woke up frame thread\n");
- break;
- case VFE_MSG_SNAPSHOT:
- if (sync->pict_pp)
- break;
-
- CDBG("snapshot pp = %d\n", sync->pict_pp);
- qcmd_frame =
- kmalloc(sizeof(struct msm_queue_cmd),
- GFP_ATOMIC);
- if (!qcmd_frame)
- goto mem_fail;
- qcmd_frame->type = MSM_CAM_Q_VFE_MSG;
- qcmd_frame->command = NULL;
- spin_lock_irqsave(&sync->pict_frame_q_lock,
- flags);
- list_add_tail(&qcmd_frame->list, &sync->pict_frame_q);
- wake_up(&sync->pict_frame_wait);
- spin_unlock_irqrestore(&sync->pict_frame_q_lock, flags);
- CDBG("woke up picture thread\n");
- break;
- default:
- CDBG("%s: qtype = %d not handled\n",
- __func__, vdata->type);
- break;
- }
- }
-
- qcmd->command = (void *)vdata;
- CDBG("vdata->type = %d\n", vdata->type);
-
- spin_lock_irqsave(&sync->msg_event_q_lock, flags);
- list_add_tail(&qcmd->list, &sync->msg_event_q);
- wake_up(&sync->msg_event_wait);
- spin_unlock_irqrestore(&sync->msg_event_q_lock, flags);
- CDBG("woke up config thread\n");
- return;
-
-mem_fail:
- kfree(qcmd);
-}
-
-static struct msm_vfe_callback msm_vfe_s = {
- .vfe_resp = msm_vfe_sync,
- .vfe_alloc = msm_vfe_sync_alloc,
-};
-
-static int __msm_open(struct msm_sync *sync, const char *const apps_id)
-{
- int rc = 0;
-
- mutex_lock(&sync->lock);
- if (sync->apps_id && strcmp(sync->apps_id, apps_id)) {
- pr_err("msm_camera(%s): sensor %s is already opened for %s\n",
- apps_id,
- sync->sdata->sensor_name,
- sync->apps_id);
- rc = -EBUSY;
- goto msm_open_done;
- }
-
- sync->apps_id = apps_id;
-
- if (!sync->opencnt) {
-
- msm_camvfe_fn_init(&sync->vfefn, sync);
- if (sync->vfefn.vfe_init) {
- rc = sync->vfefn.vfe_init(&msm_vfe_s,
- sync->pdev);
- if (rc < 0) {
- pr_err("vfe_init failed at %d\n", rc);
- goto msm_open_done;
- }
- rc = sync->sctrl.s_init(sync->sdata);
- if (rc < 0) {
- pr_err("sensor init failed: %d\n", rc);
- goto msm_open_done;
- }
- } else {
- pr_err("no sensor init func\n");
- rc = -ENODEV;
- goto msm_open_done;
- }
-
- if (rc >= 0) {
- INIT_HLIST_HEAD(&sync->frame);
- INIT_HLIST_HEAD(&sync->stats);
- sync->unblock_poll_frame = 0;
- }
- }
- sync->opencnt++;
-
-msm_open_done:
- mutex_unlock(&sync->lock);
- return rc;
-}
-
-static int msm_open_common(struct inode *inode, struct file *filep,
- int once)
-{
- int rc;
- struct msm_device *pmsm =
- container_of(inode->i_cdev, struct msm_device, cdev);
-
- CDBG("msm_camera: open %s\n", filep->f_path.dentry->d_name.name);
-
- if (atomic_cmpxchg(&pmsm->opened, 0, 1) && once) {
- pr_err("msm_camera: %s is already opened.\n",
- filep->f_path.dentry->d_name.name);
- return -EBUSY;
- }
-
- rc = nonseekable_open(inode, filep);
- if (rc < 0) {
- pr_err("msm_open: nonseekable_open error %d\n", rc);
- return rc;
- }
-
- rc = __msm_open(pmsm->sync, MSM_APPS_ID_PROP);
- if (rc < 0)
- return rc;
-
- filep->private_data = pmsm;
-
- CDBG("msm_open() open: rc = %d\n", rc);
- return rc;
-}
-
-static int msm_open(struct inode *inode, struct file *filep)
-{
- return msm_open_common(inode, filep, 1);
-}
-
-static int msm_open_control(struct inode *inode, struct file *filep)
-{
- int rc;
-
- struct msm_control_device *ctrl_pmsm =
- kmalloc(sizeof(struct msm_control_device), GFP_KERNEL);
- if (!ctrl_pmsm)
- return -ENOMEM;
-
- rc = msm_open_common(inode, filep, 0);
- if (rc < 0) {
- kfree(ctrl_pmsm);
- return rc;
- }
-
- ctrl_pmsm->pmsm = filep->private_data;
- filep->private_data = ctrl_pmsm;
- spin_lock_init(&ctrl_pmsm->ctrl_q.ctrl_status_q_lock);
- INIT_LIST_HEAD(&ctrl_pmsm->ctrl_q.ctrl_status_q);
- init_waitqueue_head(&ctrl_pmsm->ctrl_q.ctrl_status_wait);
-
- CDBG("msm_open() open: rc = %d\n", rc);
- return rc;
-}
-
-static int __msm_v4l2_control(struct msm_sync *sync,
- struct msm_ctrl_cmd *out)
-{
- int rc = 0;
-
- struct msm_queue_cmd *qcmd = NULL, *rcmd = NULL;
- struct msm_ctrl_cmd *ctrl;
- struct msm_control_device_queue FIXME;
-
- /* wake up config thread, 4 is for V4L2 application */
- qcmd = kmalloc(sizeof(struct msm_queue_cmd), GFP_KERNEL);
- if (!qcmd) {
- pr_err("msm_control: cannot allocate buffer\n");
- rc = -ENOMEM;
- goto end;
- }
- qcmd->type = MSM_CAM_Q_V4L2_REQ;
- qcmd->command = out;
-
- rcmd = __msm_control(sync, &FIXME, qcmd, out->timeout_ms);
- if (IS_ERR(rcmd)) {
- rc = PTR_ERR(rcmd);
- goto end;
- }
-
- ctrl = (struct msm_ctrl_cmd *)(rcmd->command);
- /* FIXME: we should just set out->length = ctrl->length; */
- BUG_ON(out->length < ctrl->length);
- memcpy(out->value, ctrl->value, ctrl->length);
-
-end:
- kfree(rcmd);
- CDBG("__msm_v4l2_control: end rc = %d\n", rc);
- return rc;
-}
-
-static const struct file_operations msm_fops_config = {
- .owner = THIS_MODULE,
- .open = msm_open,
- .unlocked_ioctl = msm_ioctl_config,
- .release = msm_release_config,
- .llseek = no_llseek,
-};
-
-static const struct file_operations msm_fops_control = {
- .owner = THIS_MODULE,
- .open = msm_open_control,
- .unlocked_ioctl = msm_ioctl_control,
- .release = msm_release_control,
- .llseek = no_llseek,
-};
-
-static const struct file_operations msm_fops_frame = {
- .owner = THIS_MODULE,
- .open = msm_open,
- .unlocked_ioctl = msm_ioctl_frame,
- .release = msm_release_frame,
- .poll = msm_poll_frame,
- .llseek = no_llseek,
-};
-
-static int msm_setup_cdev(struct msm_device *msm,
- int node,
- dev_t devno,
- const char *suffix,
- const struct file_operations *fops)
-{
- int rc = -ENODEV;
-
- struct device *device =
- device_create(msm_class, NULL,
- devno, NULL,
- "%s%d", suffix, node);
-
- if (IS_ERR(device)) {
- rc = PTR_ERR(device);
- pr_err("msm_camera: error creating device: %d\n", rc);
- return rc;
- }
-
- cdev_init(&msm->cdev, fops);
- msm->cdev.owner = THIS_MODULE;
-
- rc = cdev_add(&msm->cdev, devno, 1);
- if (rc < 0) {
- pr_err("msm_camera: error adding cdev: %d\n", rc);
- device_destroy(msm_class, devno);
- return rc;
- }
-
- return rc;
-}
-
-static int msm_tear_down_cdev(struct msm_device *msm, dev_t devno)
-{
- cdev_del(&msm->cdev);
- device_destroy(msm_class, devno);
- return 0;
-}
-
-int msm_v4l2_register(struct msm_v4l2_driver *drv)
-{
- /* FIXME: support multiple sensors */
- if (list_empty(&msm_sensors))
- return -ENODEV;
-
- drv->sync = list_first_entry(&msm_sensors, struct msm_sync, list);
- drv->open = __msm_open;
- drv->release = __msm_release;
- drv->ctrl = __msm_v4l2_control;
- drv->reg_pmem = __msm_register_pmem;
- drv->get_frame = __msm_get_frame;
- drv->put_frame = __msm_put_frame_buf;
- drv->get_pict = __msm_get_pic;
- drv->drv_poll = __msm_poll_frame;
-
- return 0;
-}
-EXPORT_SYMBOL(msm_v4l2_register);
-
-int msm_v4l2_unregister(struct msm_v4l2_driver *drv)
-{
- drv->sync = NULL;
- return 0;
-}
-EXPORT_SYMBOL(msm_v4l2_unregister);
-
-static int msm_sync_init(struct msm_sync *sync,
- struct platform_device *pdev,
- int (*sensor_probe)(const struct msm_camera_sensor_info *,
- struct msm_sensor_ctrl *))
-{
- int rc = 0;
- struct msm_sensor_ctrl sctrl;
- sync->sdata = pdev->dev.platform_data;
-
- spin_lock_init(&sync->msg_event_q_lock);
- INIT_LIST_HEAD(&sync->msg_event_q);
- init_waitqueue_head(&sync->msg_event_wait);
-
- spin_lock_init(&sync->prev_frame_q_lock);
- INIT_LIST_HEAD(&sync->prev_frame_q);
- init_waitqueue_head(&sync->prev_frame_wait);
-
- spin_lock_init(&sync->pict_frame_q_lock);
- INIT_LIST_HEAD(&sync->pict_frame_q);
- init_waitqueue_head(&sync->pict_frame_wait);
-
- rc = msm_camio_probe_on(pdev);
- if (rc < 0)
- return rc;
- rc = sensor_probe(sync->sdata, &sctrl);
- if (rc >= 0) {
- sync->pdev = pdev;
- sync->sctrl = sctrl;
- }
- msm_camio_probe_off(pdev);
- if (rc < 0) {
- pr_err("msm_camera: failed to initialize %s\n",
- sync->sdata->sensor_name);
- return rc;
- }
-
- sync->opencnt = 0;
- mutex_init(&sync->lock);
- CDBG("initialized %s\n", sync->sdata->sensor_name);
- return rc;
-}
-
-static int msm_sync_destroy(struct msm_sync *sync)
-{
- return 0;
-}
-
-static int msm_device_init(struct msm_device *pmsm,
- struct msm_sync *sync,
- int node)
-{
- int dev_num = 3 * node;
- int rc = msm_setup_cdev(pmsm, node,
- MKDEV(MAJOR(msm_devno), dev_num),
- "control", &msm_fops_control);
- if (rc < 0) {
- pr_err("error creating control node: %d\n", rc);
- return rc;
- }
-
- rc = msm_setup_cdev(pmsm + 1, node,
- MKDEV(MAJOR(msm_devno), dev_num + 1),
- "config", &msm_fops_config);
- if (rc < 0) {
- pr_err("error creating config node: %d\n", rc);
- msm_tear_down_cdev(pmsm, MKDEV(MAJOR(msm_devno),
- dev_num));
- return rc;
- }
-
- rc = msm_setup_cdev(pmsm + 2, node,
- MKDEV(MAJOR(msm_devno), dev_num + 2),
- "frame", &msm_fops_frame);
- if (rc < 0) {
- pr_err("error creating frame node: %d\n", rc);
- msm_tear_down_cdev(pmsm,
- MKDEV(MAJOR(msm_devno), dev_num));
- msm_tear_down_cdev(pmsm + 1,
- MKDEV(MAJOR(msm_devno), dev_num + 1));
- return rc;
- }
-
- atomic_set(&pmsm[0].opened, 0);
- atomic_set(&pmsm[1].opened, 0);
- atomic_set(&pmsm[2].opened, 0);
-
- pmsm[0].sync = sync;
- pmsm[1].sync = sync;
- pmsm[2].sync = sync;
-
- return rc;
-}
-
-int msm_camera_drv_start(struct platform_device *dev,
- int (*sensor_probe)(const struct msm_camera_sensor_info *,
- struct msm_sensor_ctrl *))
-{
- struct msm_device *pmsm = NULL;
- struct msm_sync *sync;
- int rc = -ENODEV;
- static int camera_node;
-
- if (camera_node >= MSM_MAX_CAMERA_SENSORS) {
- pr_err("msm_camera: too many camera sensors\n");
- return rc;
- }
-
- if (!msm_class) {
- /* There are three device nodes per sensor */
- rc = alloc_chrdev_region(&msm_devno, 0,
- 3 * MSM_MAX_CAMERA_SENSORS,
- "msm_camera");
- if (rc < 0) {
- pr_err("msm_camera: failed to allocate chrdev: %d\n",
- rc);
- return rc;
- }
-
- msm_class = class_create(THIS_MODULE, "msm_camera");
- if (IS_ERR(msm_class)) {
- rc = PTR_ERR(msm_class);
- pr_err("msm_camera: create device class failed: %d\n",
- rc);
- return rc;
- }
- }
-
- pmsm = kzalloc(sizeof(struct msm_device) * 3 +
- sizeof(struct msm_sync), GFP_ATOMIC);
- if (!pmsm)
- return -ENOMEM;
- sync = (struct msm_sync *)(pmsm + 3);
-
- rc = msm_sync_init(sync, dev, sensor_probe);
- if (rc < 0) {
- kfree(pmsm);
- return rc;
- }
-
- CDBG("setting camera node %d\n", camera_node);
- rc = msm_device_init(pmsm, sync, camera_node);
- if (rc < 0) {
- msm_sync_destroy(sync);
- kfree(pmsm);
- return rc;
- }
-
- camera_node++;
- list_add(&sync->list, &msm_sensors);
- return rc;
-}
-EXPORT_SYMBOL(msm_camera_drv_start);
+++ /dev/null
-/*
- * Copyright (c) 2008-2009 QUALCOMM Incorporated
- */
-
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-#include <mach/camera.h>
-
-#define CAMIF_CFG_RMSK 0x1fffff
-#define CAM_SEL_BMSK 0x2
-#define CAM_PCLK_SRC_SEL_BMSK 0x60000
-#define CAM_PCLK_INVERT_BMSK 0x80000
-#define CAM_PAD_REG_SW_RESET_BMSK 0x100000
-
-#define EXT_CAM_HSYNC_POL_SEL_BMSK 0x10000
-#define EXT_CAM_VSYNC_POL_SEL_BMSK 0x8000
-#define MDDI_CLK_CHICKEN_BIT_BMSK 0x80
-
-#define CAM_SEL_SHFT 0x1
-#define CAM_PCLK_SRC_SEL_SHFT 0x11
-#define CAM_PCLK_INVERT_SHFT 0x13
-#define CAM_PAD_REG_SW_RESET_SHFT 0x14
-
-#define EXT_CAM_HSYNC_POL_SEL_SHFT 0x10
-#define EXT_CAM_VSYNC_POL_SEL_SHFT 0xF
-#define MDDI_CLK_CHICKEN_BIT_SHFT 0x7
-#define APPS_RESET_OFFSET 0x00000210
-
-static struct clk *camio_vfe_mdc_clk;
-static struct clk *camio_mdc_clk;
-static struct clk *camio_vfe_clk;
-
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-extern int clk_set_flags(struct clk *clk, unsigned long flags);
-
-int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
-{
- int rc = -1;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk = clk_get(NULL, "vfe_mdc_clk");
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk = clk_get(NULL, "mdc_clk");
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk = clk_get(NULL, "vfe_clk");
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_enable(clk);
- rc = 0;
- }
-
- return rc;
-}
-
-int msm_camio_clk_disable(enum msm_camio_clk_type clktype)
-{
- int rc = -1;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk;
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk;
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk;
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_disable(clk);
- clk_put(clk);
- rc = 0;
- }
-
- return rc;
-}
-
-void msm_camio_clk_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_clk;
-
- if (clk != ERR_PTR(-ENOENT))
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_enable(struct platform_device *pdev)
-{
- int rc = 0;
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camio_ext = camdev->ioext;
-
- appio = request_mem_region(camio_ext.appphy,
- camio_ext.appsz, pdev->name);
- if (!appio) {
- rc = -EBUSY;
- goto enable_fail;
- }
-
- appbase = ioremap(camio_ext.appphy,
- camio_ext.appsz);
- if (!appbase) {
- rc = -ENOMEM;
- goto apps_no_mem;
- }
-
- mdcio = request_mem_region(camio_ext.mdcphy,
- camio_ext.mdcsz, pdev->name);
- if (!mdcio) {
- rc = -EBUSY;
- goto mdc_busy;
- }
-
- mdcbase = ioremap(camio_ext.mdcphy,
- camio_ext.mdcsz);
- if (!mdcbase) {
- rc = -ENOMEM;
- goto mdc_no_mem;
- }
-
- camdev->camera_gpio_on();
-
- msm_camio_clk_enable(CAMIO_VFE_CLK);
- msm_camio_clk_enable(CAMIO_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
- return 0;
-
-mdc_no_mem:
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
-mdc_busy:
- iounmap(appbase);
-apps_no_mem:
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-enable_fail:
- return rc;
-}
-
-void msm_camio_disable(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- iounmap(mdcbase);
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
- iounmap(appbase);
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-
- camdev->camera_gpio_off();
-
- msm_camio_clk_disable(CAMIO_VFE_CLK);
- msm_camio_clk_disable(CAMIO_MDC_CLK);
- msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
-}
-
-void msm_camio_camif_pad_reg_reset(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- /* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
-
- mask = CAM_SEL_BMSK |
- CAM_PCLK_SRC_SEL_BMSK |
- CAM_PCLK_INVERT_BMSK;
-
- value = 1 << CAM_SEL_SHFT |
- 3 << CAM_PCLK_SRC_SEL_SHFT |
- 0 << CAM_PCLK_INVERT_SHFT;
-
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
- mdelay(10);
-}
-
-void msm_camio_vfe_blk_reset(void)
-{
- uint32_t val;
-
- val = readl(appbase + 0x00000210);
- val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-
- val = readl(appbase + 0x00000210);
- val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-}
-
-void msm_camio_camif_pad_reg_reset_2(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-}
-
-void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
-{
- struct clk *clk = NULL;
-
- clk = camio_vfe_clk;
-
- if (clk != NULL && clk != ERR_PTR(-ENOENT)) {
- switch (srctype) {
- case MSM_CAMIO_CLK_SRC_INTERNAL:
- clk_set_flags(clk, 0x00000100 << 1);
- break;
-
- case MSM_CAMIO_CLK_SRC_EXTERNAL:
- clk_set_flags(clk, 0x00000100);
- break;
-
- default:
- break;
- }
- }
-}
-
-int msm_camio_probe_on(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- camdev->camera_gpio_on();
- return msm_camio_clk_enable(CAMIO_VFE_CLK);
-}
-
-int msm_camio_probe_off(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
- camdev->camera_gpio_off();
- return msm_camio_clk_disable(CAMIO_VFE_CLK);
-}
+++ /dev/null
-/*
- * Copyright (c) 2008-2009 QUALCOMM Incorporated
- */
-
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-#include <mach/camera.h>
-
-#define CAMIF_CFG_RMSK 0x1fffff
-#define CAM_SEL_BMSK 0x2
-#define CAM_PCLK_SRC_SEL_BMSK 0x60000
-#define CAM_PCLK_INVERT_BMSK 0x80000
-#define CAM_PAD_REG_SW_RESET_BMSK 0x100000
-
-#define EXT_CAM_HSYNC_POL_SEL_BMSK 0x10000
-#define EXT_CAM_VSYNC_POL_SEL_BMSK 0x8000
-#define MDDI_CLK_CHICKEN_BIT_BMSK 0x80
-
-#define CAM_SEL_SHFT 0x1
-#define CAM_PCLK_SRC_SEL_SHFT 0x11
-#define CAM_PCLK_INVERT_SHFT 0x13
-#define CAM_PAD_REG_SW_RESET_SHFT 0x14
-
-#define EXT_CAM_HSYNC_POL_SEL_SHFT 0x10
-#define EXT_CAM_VSYNC_POL_SEL_SHFT 0xF
-#define MDDI_CLK_CHICKEN_BIT_SHFT 0x7
-#define APPS_RESET_OFFSET 0x00000210
-
-static struct clk *camio_vfe_mdc_clk;
-static struct clk *camio_mdc_clk;
-static struct clk *camio_vfe_clk;
-static struct clk *camio_vfe_axi_clk;
-static struct msm_camera_io_ext camio_ext;
-static struct resource *appio, *mdcio;
-void __iomem *appbase, *mdcbase;
-
-extern int clk_set_flags(struct clk *clk, unsigned long flags);
-
-int msm_camio_clk_enable(enum msm_camio_clk_type clktype)
-{
- int rc = 0;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- camio_vfe_mdc_clk =
- clk = clk_get(NULL, "vfe_mdc_clk");
- break;
-
- case CAMIO_MDC_CLK:
- camio_mdc_clk =
- clk = clk_get(NULL, "mdc_clk");
- break;
-
- case CAMIO_VFE_CLK:
- camio_vfe_clk =
- clk = clk_get(NULL, "vfe_clk");
- break;
-
- case CAMIO_VFE_AXI_CLK:
- camio_vfe_axi_clk =
- clk = clk_get(NULL, "vfe_axi_clk");
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk))
- clk_enable(clk);
- else
- rc = -1;
-
- return rc;
-}
-
-int msm_camio_clk_disable(enum msm_camio_clk_type clktype)
-{
- int rc = 0;
- struct clk *clk = NULL;
-
- switch (clktype) {
- case CAMIO_VFE_MDC_CLK:
- clk = camio_vfe_mdc_clk;
- break;
-
- case CAMIO_MDC_CLK:
- clk = camio_mdc_clk;
- break;
-
- case CAMIO_VFE_CLK:
- clk = camio_vfe_clk;
- break;
-
- case CAMIO_VFE_AXI_CLK:
- clk = camio_vfe_axi_clk;
- break;
-
- default:
- break;
- }
-
- if (!IS_ERR(clk)) {
- clk_disable(clk);
- clk_put(clk);
- } else
- rc = -1;
-
- return rc;
-}
-
-void msm_camio_clk_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_mdc_clk;
-
- /* TODO: check return */
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_enable(struct platform_device *pdev)
-{
- int rc = 0;
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camio_ext = camdev->ioext;
-
- appio = request_mem_region(camio_ext.appphy,
- camio_ext.appsz, pdev->name);
- if (!appio) {
- rc = -EBUSY;
- goto enable_fail;
- }
-
- appbase = ioremap(camio_ext.appphy,
- camio_ext.appsz);
- if (!appbase) {
- rc = -ENOMEM;
- goto apps_no_mem;
- }
-
- mdcio = request_mem_region(camio_ext.mdcphy,
- camio_ext.mdcsz, pdev->name);
- if (!mdcio) {
- rc = -EBUSY;
- goto mdc_busy;
- }
-
- mdcbase = ioremap(camio_ext.mdcphy,
- camio_ext.mdcsz);
- if (!mdcbase) {
- rc = -ENOMEM;
- goto mdc_no_mem;
- }
-
- camdev->camera_gpio_on();
-
- msm_camio_clk_enable(CAMIO_VFE_CLK);
- msm_camio_clk_enable(CAMIO_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
- msm_camio_clk_enable(CAMIO_VFE_AXI_CLK);
- return 0;
-
-mdc_no_mem:
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
-mdc_busy:
- iounmap(appbase);
-apps_no_mem:
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-enable_fail:
- return rc;
-}
-
-void msm_camio_disable(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- iounmap(mdcbase);
- release_mem_region(camio_ext.mdcphy, camio_ext.mdcsz);
- iounmap(appbase);
- release_mem_region(camio_ext.appphy, camio_ext.appsz);
-
- camdev->camera_gpio_off();
-
- msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
- msm_camio_clk_disable(CAMIO_MDC_CLK);
- msm_camio_clk_disable(CAMIO_VFE_CLK);
- msm_camio_clk_disable(CAMIO_VFE_AXI_CLK);
-}
-
-void msm_camio_camif_pad_reg_reset(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- /* select CLKRGM_VFE_SRC_CAM_VFE_SRC: internal source */
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
-
- mask = CAM_SEL_BMSK |
- CAM_PCLK_SRC_SEL_BMSK |
- CAM_PCLK_INVERT_BMSK |
- EXT_CAM_HSYNC_POL_SEL_BMSK |
- EXT_CAM_VSYNC_POL_SEL_BMSK |
- MDDI_CLK_CHICKEN_BIT_BMSK;
-
- value = 1 << CAM_SEL_SHFT |
- 3 << CAM_PCLK_SRC_SEL_SHFT |
- 0 << CAM_PCLK_INVERT_SHFT |
- 0 << EXT_CAM_HSYNC_POL_SEL_SHFT |
- 0 << EXT_CAM_VSYNC_POL_SEL_SHFT |
- 0 << MDDI_CLK_CHICKEN_BIT_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_EXTERNAL);
-
- mdelay(10);
-
- /* todo: check return */
- if (camio_vfe_clk)
- clk_set_rate(camio_vfe_clk, 96000000);
-}
-
-void msm_camio_vfe_blk_reset(void)
-{
- uint32_t val;
-
- val = readl(appbase + 0x00000210);
- val |= 0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-
- val = readl(appbase + 0x00000210);
- val &= ~0x1;
- writel(val, appbase + 0x00000210);
- mdelay(10);
-}
-
-void msm_camio_camif_pad_reg_reset_2(void)
-{
- uint32_t reg;
- uint32_t mask, value;
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-
- reg = (readl(mdcbase)) & CAMIF_CFG_RMSK;
- mask = CAM_PAD_REG_SW_RESET_BMSK;
- value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
- writel((reg & (~mask)) | (value & mask), mdcbase);
- mdelay(10);
-}
-
-void msm_camio_clk_sel(enum msm_camio_clk_src_type srctype)
-{
- struct clk *clk = NULL;
-
- clk = camio_vfe_clk;
-
- if (clk != NULL) {
- switch (srctype) {
- case MSM_CAMIO_CLK_SRC_INTERNAL:
- clk_set_flags(clk, 0x00000100 << 1);
- break;
-
- case MSM_CAMIO_CLK_SRC_EXTERNAL:
- clk_set_flags(clk, 0x00000100);
- break;
-
- default:
- break;
- }
- }
-}
-
-void msm_camio_clk_axi_rate_set(int rate)
-{
- struct clk *clk = camio_vfe_axi_clk;
- /* todo: check return */
- clk_set_rate(clk, rate);
-}
-
-int msm_camio_probe_on(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camdev->camera_gpio_on();
- return msm_camio_clk_enable(CAMIO_VFE_MDC_CLK);
-}
-
-int msm_camio_probe_off(struct platform_device *pdev)
-{
- struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
- struct msm_camera_device_platform_data *camdev = sinfo->pdata;
-
- camdev->camera_gpio_off();
- return msm_camio_clk_disable(CAMIO_VFE_MDC_CLK);
-}
+++ /dev/null
-/*
- *
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- *
- */
-
-#include <linux/workqueue.h>
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/ioctl.h>
-#include <linux/spinlock.h>
-#include <linux/videodev2.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <media/v4l2-dev.h>
-#include <media/msm_camera.h>
-#include <mach/camera.h>
-#include <media/v4l2-ioctl.h>
-/*#include <linux/platform_device.h>*/
-
-#define MSM_V4L2_START_SNAPSHOT _IOWR('V', BASE_VIDIOC_PRIVATE+1, \
- struct v4l2_buffer)
-
-#define MSM_V4L2_GET_PICTURE _IOWR('V', BASE_VIDIOC_PRIVATE+2, \
- struct v4l2_buffer)
-
-#define MSM_V4L2_DEVICE_NAME "msm_v4l2"
-
-#define MSM_V4L2_PROC_NAME "msm_v4l2"
-
-#define MSM_V4L2_DEVNUM_MPEG2 0
-#define MSM_V4L2_DEVNUM_YUV 20
-
-/* HVGA-P (portrait) and HVGA-L (landscape) */
-#define MSM_V4L2_WIDTH 480
-#define MSM_V4L2_HEIGHT 320
-
-#if 1
-#define D(fmt, args...) printk(KERN_INFO "msm_v4l2: " fmt, ##args)
-#else
-#define D(fmt, args...) do {} while (0)
-#endif
-
-#define PREVIEW_FRAMES_NUM 4
-
-struct msm_v4l2_device {
- struct list_head read_queue;
- struct v4l2_format current_cap_format;
- struct v4l2_format current_pix_format;
- struct video_device *pvdev;
- struct msm_v4l2_driver *drv;
- uint8_t opencnt;
-
- spinlock_t read_queue_lock;
-};
-
-static struct msm_v4l2_device *g_pmsm_v4l2_dev;
-
-
-static DEFINE_MUTEX(msm_v4l2_opencnt_lock);
-
-static int msm_v4l2_open(struct file *f)
-{
- int rc = 0;
- D("%s\n", __func__);
- mutex_lock(&msm_v4l2_opencnt_lock);
- if (!g_pmsm_v4l2_dev->opencnt) {
- rc = g_pmsm_v4l2_dev->drv->open(
- g_pmsm_v4l2_dev->drv->sync,
- MSM_APPS_ID_V4L2);
- }
- g_pmsm_v4l2_dev->opencnt++;
- mutex_unlock(&msm_v4l2_opencnt_lock);
- return rc;
-}
-
-static int msm_v4l2_release(struct file *f)
-{
- int rc = 0;
- D("%s\n", __func__);
- mutex_lock(&msm_v4l2_opencnt_lock);
- if (!g_pmsm_v4l2_dev->opencnt) {
- g_pmsm_v4l2_dev->opencnt--;
- if (!g_pmsm_v4l2_dev->opencnt) {
- rc = g_pmsm_v4l2_dev->drv->release(
- g_pmsm_v4l2_dev->drv->sync);
- }
- }
- mutex_unlock(&msm_v4l2_opencnt_lock);
- return rc;
-}
-
-static unsigned int msm_v4l2_poll(struct file *f, struct poll_table_struct *w)
-{
- return g_pmsm_v4l2_dev->drv->drv_poll(g_pmsm_v4l2_dev->drv->sync, f, w);
-}
-
-static long msm_v4l2_ioctl(struct file *filep,
- unsigned int cmd, unsigned long arg)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("msm_v4l2_ioctl, cmd = %d, %d\n", cmd, __LINE__);
-
- switch (cmd) {
- case MSM_V4L2_START_SNAPSHOT:
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_ioctl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
- ctrlcmd->timeout_ms = 10000;
-
- D("msm_v4l2_ioctl, MSM_V4L2_START_SNAPSHOT v4l2 ioctl %d\n",
- cmd);
- ctrlcmd->type = MSM_V4L2_SNAPSHOT;
- return g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- case MSM_V4L2_GET_PICTURE:
- D("msm_v4l2_ioctl, MSM_V4L2_GET_PICTURE v4l2 ioctl %d\n", cmd);
- ctrlcmd = (struct msm_ctrl_cmd *)arg;
- return g_pmsm_v4l2_dev->drv->get_pict(
- g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
-
- default:
- D("msm_v4l2_ioctl, standard v4l2 ioctl %d\n", cmd);
- return video_ioctl2(filep, cmd, arg);
- }
-}
-
-static void msm_v4l2_release_dev(struct video_device *d)
-{
- D("%s\n", __func__);
-}
-
-static int msm_v4l2_querycap(struct file *f,
- void *pctx, struct v4l2_capability *pcaps)
-{
- D("%s\n", __func__);
- strncpy(pcaps->driver, MSM_APPS_ID_V4L2, sizeof(pcaps->driver));
- strncpy(pcaps->card,
- MSM_V4L2_DEVICE_NAME, sizeof(pcaps->card));
- pcaps->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
- return 0;
-}
-
-static int msm_v4l2_s_std(struct file *f, void *pctx, v4l2_std_id *pnorm)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_queryctrl(struct file *f,
- void *pctx, struct v4l2_queryctrl *pqctrl)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_queryctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_QUERY_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_queryctrl);
- ctrlcmd->value = pqctrl;
- ctrlcmd->timeout_ms = 10000;
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_g_ctrl(struct file *f, void *pctx, struct v4l2_control *c)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_g_ctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_GET_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_control);
- ctrlcmd->value = c;
- ctrlcmd->timeout_ms = 10000;
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_s_ctrl(struct file *f, void *pctx, struct v4l2_control *c)
-{
- int rc = 0;
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_ctrl: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_SET_CTRL;
- ctrlcmd->length = sizeof(struct v4l2_control);
- ctrlcmd->value = c;
- ctrlcmd->timeout_ms = 10000;
-
- D("%s\n", __func__);
-
- rc = g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
- if (rc < 0)
- return -1;
-
- return ctrlcmd->status;
-}
-
-static int msm_v4l2_reqbufs(struct file *f,
- void *pctx, struct v4l2_requestbuffers *b)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_querybuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- struct msm_pmem_info pmem_buf;
-#if 0
- __u32 width = 0;
- __u32 height = 0;
- __u32 y_size = 0;
- __u32 y_pad = 0;
-
- /* FIXME: g_pmsm_v4l2_dev->current_pix_format.fmt.pix.width; */
- width = 640;
- /* FIXME: g_pmsm_v4l2_dev->current_pix_format.fmt.pix.height; */
- height = 480;
-
- D("%s: width = %d, height = %d\n", __func__, width, height);
-
- y_size = width * height;
- y_pad = y_size % 4;
-#endif
-
- __u32 y_pad = pb->bytesused % 4;
-
- /* V4L2 videodev will do the copy_from_user. */
-
- memset(&pmem_buf, 0, sizeof(struct msm_pmem_info));
- pmem_buf.type = MSM_PMEM_OUTPUT2;
- pmem_buf.vaddr = (void *)pb->m.userptr;
- pmem_buf.y_off = 0;
- pmem_buf.fd = (int)pb->reserved;
- /* pmem_buf.cbcr_off = (y_size + y_pad); */
- pmem_buf.cbcr_off = (pb->bytesused + y_pad);
-
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync, &pmem_buf);
-
- return 0;
-}
-
-static int msm_v4l2_qbuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- /*
- __u32 y_size = 0;
- __u32 y_pad = 0;
- __u32 width = 0;
- __u32 height = 0;
- */
-
- __u32 y_pad = 0;
-
- struct msm_pmem_info meminfo;
- struct msm_frame frame;
- static int cnt;
-
- if ((pb->flags >> 16) & 0x0001) {
- /* this is for previwe */
-#if 0
- width = 640;
- height = 480;
-
- /* V4L2 videodev will do the copy_from_user. */
- D("%s: width = %d, height = %d\n", __func__, width, height);
- y_size = width * height;
- y_pad = y_size % 4;
-#endif
-
- y_pad = pb->bytesused % 4;
-
- if (pb->type == V4L2_BUF_TYPE_PRIVATE) {
- /* this qbuf is actually for releasing */
-
- frame.buffer = pb->m.userptr;
- frame.y_off = 0;
- /* frame.cbcr_off = (y_size + y_pad); */
- frame.cbcr_off = (pb->bytesused + y_pad);
- frame.fd = pb->reserved;
-
- D("V4L2_BUF_TYPE_PRIVATE: pb->bytesused = %d \n",
- pb->bytesused);
-
- g_pmsm_v4l2_dev->drv->put_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
-
- return 0;
- }
-
- D("V4L2_BUF_TYPE_VIDEO_CAPTURE: pb->bytesused = %d \n",
- pb->bytesused);
-
- meminfo.type = MSM_PMEM_OUTPUT2;
- meminfo.fd = (int)pb->reserved;
- meminfo.vaddr = (void *)pb->m.userptr;
- meminfo.y_off = 0;
- /* meminfo.cbcr_off = (y_size + y_pad); */
- meminfo.cbcr_off = (pb->bytesused + y_pad);
- if (cnt == PREVIEW_FRAMES_NUM - 1)
- meminfo.active = 0;
- else
- meminfo.active = 1;
- cnt++;
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync,
- &meminfo);
- } else if ((pb->flags) & 0x0001) {
- /* this is for snapshot */
-
- __u32 y_size = 0;
-
- if ((pb->flags >> 8) & 0x01) {
-
- y_size = pb->bytesused;
-
- meminfo.type = MSM_PMEM_THUMBAIL;
- } else if ((pb->flags >> 9) & 0x01) {
-
- y_size = pb->bytesused;
-
- meminfo.type = MSM_PMEM_MAINIMG;
- }
-
- y_pad = y_size % 4;
-
- meminfo.fd = (int)pb->reserved;
- meminfo.vaddr = (void *)pb->m.userptr;
- meminfo.y_off = 0;
- /* meminfo.cbcr_off = (y_size + y_pad); */
- meminfo.cbcr_off = (y_size + y_pad);
- meminfo.active = 1;
- g_pmsm_v4l2_dev->drv->reg_pmem(g_pmsm_v4l2_dev->drv->sync,
- &meminfo);
- }
-
- return 0;
-}
-
-static int msm_v4l2_dqbuf(struct file *f, void *pctx, struct v4l2_buffer *pb)
-{
- struct msm_frame frame;
- D("%s\n", __func__);
-
- /* V4L2 videodev will do the copy_to_user. */
- if (pb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
-
- D("%s, %d\n", __func__, __LINE__);
-
- g_pmsm_v4l2_dev->drv->get_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
-
- pb->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pb->m.userptr = (unsigned long)frame.buffer; /* FIXME */
- pb->reserved = (int)frame.fd;
- /* pb->length = (int)frame.cbcr_off; */
-
- pb->bytesused = frame.cbcr_off;
-
- } else if (pb->type == V4L2_BUF_TYPE_PRIVATE) {
- __u32 y_pad = pb->bytesused % 4;
-
- frame.buffer = pb->m.userptr;
- frame.y_off = 0;
- /* frame.cbcr_off = (y_size + y_pad); */
- frame.cbcr_off = (pb->bytesused + y_pad);
- frame.fd = pb->reserved;
-
- g_pmsm_v4l2_dev->drv->put_frame(
- g_pmsm_v4l2_dev->drv->sync,
- &frame);
- }
-
- return 0;
-}
-
-static int msm_v4l2_streamon(struct file *f, void *pctx, enum v4l2_buf_type i)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_STREAM_ON;
- ctrlcmd->timeout_ms = 10000;
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
-
- D("%s\n", __func__);
-
- g_pmsm_v4l2_dev->drv->ctrl(
- g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- D("%s after drv->ctrl \n", __func__);
-
- return 0;
-}
-
-static int msm_v4l2_streamoff(struct file *f, void *pctx, enum v4l2_buf_type i)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_STREAM_OFF;
- ctrlcmd->timeout_ms = 10000;
- ctrlcmd->length = 0;
- ctrlcmd->value = NULL;
-
-
- D("%s\n", __func__);
-
- g_pmsm_v4l2_dev->drv->ctrl(
- g_pmsm_v4l2_dev->drv->sync,
- ctrlcmd);
-
- return 0;
-}
-
-static int msm_v4l2_enum_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_fmtdesc *pfmtdesc)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_enum_fmt_cap(struct file *f,
- void *pctx, struct v4l2_fmtdesc *pfmtdesc)
-{
- D("%s\n", __func__);
-
- switch (pfmtdesc->index) {
- case 0:
- pfmtdesc->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pfmtdesc->flags = 0;
- strncpy(pfmtdesc->description, "YUV 4:2:0",
- sizeof(pfmtdesc->description));
- pfmtdesc->pixelformat = V4L2_PIX_FMT_YVU420;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int msm_v4l2_g_fmt_cap(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- pfmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
- pfmt->fmt.pix.width = MSM_V4L2_WIDTH;
- pfmt->fmt.pix.height = MSM_V4L2_HEIGHT;
- pfmt->fmt.pix.pixelformat = V4L2_PIX_FMT_YVU420;
- pfmt->fmt.pix.field = V4L2_FIELD_ANY;
- pfmt->fmt.pix.bytesperline = 0;
- pfmt->fmt.pix.sizeimage = 0;
- pfmt->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
- pfmt->fmt.pix.priv = 0;
- return 0;
-}
-
-static int msm_v4l2_s_fmt_cap(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- struct msm_ctrl_cmd *ctrlcmd;
-
- D("%s\n", __func__);
-
- ctrlcmd = kmalloc(sizeof(struct msm_ctrl_cmd), GFP_ATOMIC);
- if (!ctrlcmd) {
- CDBG("msm_v4l2_s_fmt_cap: cannot allocate buffer\n");
- return -ENOMEM;
- }
-
- ctrlcmd->type = MSM_V4L2_VID_CAP_TYPE;
- ctrlcmd->length = sizeof(struct v4l2_format);
- ctrlcmd->value = pfmt;
- ctrlcmd->timeout_ms = 10000;
-
- if (pfmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
- kfree(ctrlcmd);
- return -1;
- }
-
-#if 0
- /* FIXEME */
- if (pfmt->fmt.pix.pixelformat != V4L2_PIX_FMT_YVU420) {
- kfree(ctrlcmd);
- return -EINVAL;
- }
-#endif
-
- /* Ok, but check other params, too. */
-
-#if 0
- memcpy(&g_pmsm_v4l2_dev->current_pix_format.fmt.pix, pfmt,
- sizeof(struct v4l2_format));
-#endif
-
- g_pmsm_v4l2_dev->drv->ctrl(g_pmsm_v4l2_dev->drv->sync, ctrlcmd);
-
- return 0;
-}
-
-static int msm_v4l2_g_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- pfmt->type = V4L2_BUF_TYPE_VIDEO_OVERLAY;
- pfmt->fmt.pix.width = MSM_V4L2_WIDTH;
- pfmt->fmt.pix.height = MSM_V4L2_HEIGHT;
- pfmt->fmt.pix.pixelformat = V4L2_PIX_FMT_YVU420;
- pfmt->fmt.pix.field = V4L2_FIELD_ANY;
- pfmt->fmt.pix.bytesperline = 0;
- pfmt->fmt.pix.sizeimage = 0;
- pfmt->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG;
- pfmt->fmt.pix.priv = 0;
- return 0;
-}
-
-static int msm_v4l2_s_fmt_overlay(struct file *f,
- void *pctx, struct v4l2_format *pfmt)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_overlay(struct file *f, void *pctx, unsigned int i)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_g_jpegcomp(struct file *f,
- void *pctx, struct v4l2_jpegcompression *pcomp)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-static int msm_v4l2_s_jpegcomp(struct file *f,
- void *pctx, struct v4l2_jpegcompression *pcomp)
-{
- D("%s\n", __func__);
- return 0;
-}
-
-#ifdef CONFIG_PROC_FS
-int msm_v4l2_read_proc(char *pbuf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- int len = 0;
- len += snprintf(pbuf, strlen("stats\n") + 1, "stats\n");
-
- if (g_pmsm_v4l2_dev) {
- len += snprintf(pbuf, strlen("mode: ") + 1, "mode: ");
-
- if (g_pmsm_v4l2_dev->current_cap_format.type
- == V4L2_BUF_TYPE_VIDEO_CAPTURE)
- len += snprintf(pbuf, strlen("capture\n") + 1,
- "capture\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
-
- len += snprintf(pbuf, 21, "resolution: %dx%d\n",
- g_pmsm_v4l2_dev->current_cap_format.fmt.pix.
- width,
- g_pmsm_v4l2_dev->current_cap_format.fmt.pix.
- height);
-
- len += snprintf(pbuf,
- strlen("pixel format: ") + 1, "pixel format: ");
- if (g_pmsm_v4l2_dev->current_cap_format.fmt.pix.pixelformat
- == V4L2_PIX_FMT_YVU420)
- len += snprintf(pbuf, strlen("yvu420\n") + 1,
- "yvu420\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
-
- len += snprintf(pbuf, strlen("colorspace: ") + 1,
- "colorspace: ");
- if (g_pmsm_v4l2_dev->current_cap_format.fmt.pix.colorspace
- == V4L2_COLORSPACE_JPEG)
- len += snprintf(pbuf, strlen("jpeg\n") + 1, "jpeg\n");
- else
- len += snprintf(pbuf, strlen("unknown\n") + 1,
- "unknown\n");
- }
-
- *eof = 1;
- return len;
-}
-#endif
-
-static const struct v4l2_file_operations msm_v4l2_fops = {
- .owner = THIS_MODULE,
- .open = msm_v4l2_open,
- .poll = msm_v4l2_poll,
- .release = msm_v4l2_release,
- .ioctl = msm_v4l2_ioctl,
-};
-
-static void msm_v4l2_dev_init(struct msm_v4l2_device *pmsm_v4l2_dev)
-{
- pmsm_v4l2_dev->read_queue_lock =
- __SPIN_LOCK_UNLOCKED(pmsm_v4l2_dev->read_queue_lock);
- INIT_LIST_HEAD(&pmsm_v4l2_dev->read_queue);
-}
-
-static int msm_v4l2_try_fmt_cap(struct file *file,
- void *fh, struct v4l2_format *f)
-{
- /* FIXME */
- return 0;
-}
-
-static int mm_v4l2_try_fmt_type_private(struct file *file,
- void *fh, struct v4l2_format *f)
-{
- /* FIXME */
- return 0;
-}
-
-/*
- * should the following structure be used instead of the code in the function?
- * static const struct v4l2_ioctl_ops msm_v4l2_ioctl_ops = {
- * .vidioc_querycap = ....
- * }
- */
-static const struct v4l2_ioctl_ops msm_ioctl_ops = {
- .vidioc_querycap = msm_v4l2_querycap,
- .vidioc_s_std = msm_v4l2_s_std,
-
- .vidioc_queryctrl = msm_v4l2_queryctrl,
- .vidioc_g_ctrl = msm_v4l2_g_ctrl,
- .vidioc_s_ctrl = msm_v4l2_s_ctrl,
-
- .vidioc_reqbufs = msm_v4l2_reqbufs,
- .vidioc_querybuf = msm_v4l2_querybuf,
- .vidioc_qbuf = msm_v4l2_qbuf,
- .vidioc_dqbuf = msm_v4l2_dqbuf,
-
- .vidioc_streamon = msm_v4l2_streamon,
- .vidioc_streamoff = msm_v4l2_streamoff,
-
- .vidioc_enum_fmt_vid_overlay = msm_v4l2_enum_fmt_overlay,
- .vidioc_enum_fmt_vid_cap = msm_v4l2_enum_fmt_cap,
-
- .vidioc_try_fmt_vid_cap = msm_v4l2_try_fmt_cap,
- .vidioc_try_fmt_type_private = mm_v4l2_try_fmt_type_private,
-
- .vidioc_g_fmt_vid_cap = msm_v4l2_g_fmt_cap,
- .vidioc_s_fmt_vid_cap = msm_v4l2_s_fmt_cap,
- .vidioc_g_fmt_vid_overlay = msm_v4l2_g_fmt_overlay,
- .vidioc_s_fmt_vid_overlay = msm_v4l2_s_fmt_overlay,
- .vidioc_overlay = msm_v4l2_overlay,
-
- .vidioc_g_jpegcomp = msm_v4l2_g_jpegcomp,
- .vidioc_s_jpegcomp = msm_v4l2_s_jpegcomp,
-};
-
-static int msm_v4l2_video_dev_init(struct video_device *pvd)
-{
- strncpy(pvd->name, MSM_APPS_ID_V4L2, sizeof(pvd->name));
- pvd->vfl_type = 1;
- pvd->fops = &msm_v4l2_fops;
- pvd->release = msm_v4l2_release_dev;
- pvd->minor = -1;
- pvd->ioctl_ops = &msm_ioctl_ops;
- return msm_v4l2_register(g_pmsm_v4l2_dev->drv);
-}
-
-static int __init msm_v4l2_init(void)
-{
- int rc = -ENOMEM;
- struct video_device *pvdev = NULL;
- struct msm_v4l2_device *pmsm_v4l2_dev = NULL;
- D("%s\n", __func__);
-
- pvdev = video_device_alloc();
- if (pvdev == NULL)
- return rc;
-
- pmsm_v4l2_dev =
- kzalloc(sizeof(struct msm_v4l2_device), GFP_KERNEL);
- if (pmsm_v4l2_dev == NULL) {
- video_device_release(pvdev);
- return rc;
- }
-
- msm_v4l2_dev_init(pmsm_v4l2_dev);
-
- g_pmsm_v4l2_dev = pmsm_v4l2_dev;
- g_pmsm_v4l2_dev->pvdev = pvdev;
-
- g_pmsm_v4l2_dev->drv =
- kzalloc(sizeof(struct msm_v4l2_driver), GFP_KERNEL);
- if (!g_pmsm_v4l2_dev->drv) {
- video_device_release(pvdev);
- kfree(pmsm_v4l2_dev);
- return rc;
- }
-
- rc = msm_v4l2_video_dev_init(pvdev);
- if (rc < 0) {
- video_device_release(pvdev);
- kfree(g_pmsm_v4l2_dev->drv);
- kfree(pmsm_v4l2_dev);
- return rc;
- }
-
- if (video_register_device(pvdev, VFL_TYPE_GRABBER,
- MSM_V4L2_DEVNUM_YUV)) {
- D("failed to register device\n");
- video_device_release(pvdev);
- kfree(g_pmsm_v4l2_dev);
- g_pmsm_v4l2_dev = NULL;
- return -ENOENT;
- }
-#ifdef CONFIG_PROC_FS
- create_proc_read_entry(MSM_V4L2_PROC_NAME,
- 0, NULL, msm_v4l2_read_proc, NULL);
-#endif
-
- return 0;
-}
-
-static void __exit msm_v4l2_exit(void)
-{
- struct video_device *pvdev = g_pmsm_v4l2_dev->pvdev;
- D("%s\n", __func__);
-#ifdef CONFIG_PROC_FS
- remove_proc_entry(MSM_V4L2_PROC_NAME, NULL);
-#endif
- video_unregister_device(pvdev);
- video_device_release(pvdev);
-
- msm_v4l2_unregister(g_pmsm_v4l2_dev->drv);
-
- kfree(g_pmsm_v4l2_dev->drv);
- g_pmsm_v4l2_dev->drv = NULL;
-
- kfree(g_pmsm_v4l2_dev);
- g_pmsm_v4l2_dev = NULL;
-}
-
-module_init(msm_v4l2_init);
-module_exit(msm_v4l2_exit);
-
-MODULE_DESCRIPTION("MSM V4L2 driver");
-MODULE_LICENSE("GPL v2");
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include <linux/msm_adsp.h>
-#include <linux/uaccess.h>
-#include <linux/fs.h>
-#include <linux/sched.h>
-#include <linux/android_pmem.h>
-#include <linux/slab.h>
-#include <mach/msm_adsp.h>
-#include <linux/delay.h>
-#include <linux/wait.h>
-#include "msm_vfe7x.h"
-
-#define QDSP_CMDQUEUE QDSP_vfeCommandQueue
-
-#define VFE_RESET_CMD 0
-#define VFE_START_CMD 1
-#define VFE_STOP_CMD 2
-#define VFE_FRAME_ACK 20
-#define STATS_AF_ACK 21
-#define STATS_WE_ACK 22
-
-#define MSG_STOP_ACK 1
-#define MSG_SNAPSHOT 2
-#define MSG_OUTPUT1 6
-#define MSG_OUTPUT2 7
-#define MSG_STATS_AF 8
-#define MSG_STATS_WE 9
-
-static struct msm_adsp_module *qcam_mod;
-static struct msm_adsp_module *vfe_mod;
-static struct msm_vfe_callback *resp;
-static void *extdata;
-static uint32_t extlen;
-
-struct mutex vfe_lock;
-static void *vfe_syncdata;
-static uint8_t vfestopped;
-
-static struct stop_event stopevent;
-
-static void vfe_7x_convert(struct msm_vfe_phy_info *pinfo,
- enum vfe_resp_msg type,
- void *data, void **ext, int32_t *elen)
-{
- switch (type) {
- case VFE_MSG_OUTPUT1:
- case VFE_MSG_OUTPUT2: {
- pinfo->y_phy = ((struct vfe_endframe *)data)->y_address;
- pinfo->cbcr_phy =
- ((struct vfe_endframe *)data)->cbcr_address;
-
- CDBG("vfe_7x_convert, y_phy = 0x%x, cbcr_phy = 0x%x\n",
- pinfo->y_phy, pinfo->cbcr_phy);
-
- ((struct vfe_frame_extra *)extdata)->bl_evencol =
- ((struct vfe_endframe *)data)->blacklevelevencolumn;
-
- ((struct vfe_frame_extra *)extdata)->bl_oddcol =
- ((struct vfe_endframe *)data)->blackleveloddcolumn;
-
- ((struct vfe_frame_extra *)extdata)->g_def_p_cnt =
- ((struct vfe_endframe *)data)->greendefectpixelcount;
-
- ((struct vfe_frame_extra *)extdata)->r_b_def_p_cnt =
- ((struct vfe_endframe *)data)->redbluedefectpixelcount;
-
- *ext = extdata;
- *elen = extlen;
- }
- break;
-
- case VFE_MSG_STATS_AF:
- case VFE_MSG_STATS_WE:
- pinfo->sbuf_phy = *(uint32_t *)data;
- break;
-
- default:
- break;
- } /* switch */
-}
-
-static void vfe_7x_ops(void *driver_data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- uint32_t evt_buf[3];
- struct msm_vfe_resp *rp;
- void *data;
-
- len = (id == (uint16_t)-1) ? 0 : len;
- data = resp->vfe_alloc(sizeof(struct msm_vfe_resp) + len, vfe_syncdata);
-
- if (!data) {
- pr_err("rp: cannot allocate buffer\n");
- return;
- }
- rp = (struct msm_vfe_resp *)data;
- rp->evt_msg.len = len;
-
- if (id == ((uint16_t)-1)) {
- /* event */
- rp->type = VFE_EVENT;
- rp->evt_msg.type = MSM_CAMERA_EVT;
- getevent(evt_buf, sizeof(evt_buf));
- rp->evt_msg.msg_id = evt_buf[0];
- resp->vfe_resp(rp, MSM_CAM_Q_VFE_EVT, vfe_syncdata);
- } else {
- /* messages */
- rp->evt_msg.type = MSM_CAMERA_MSG;
- rp->evt_msg.msg_id = id;
- rp->evt_msg.data = rp + 1;
- getevent(rp->evt_msg.data, len);
-
- switch (rp->evt_msg.msg_id) {
- case MSG_SNAPSHOT:
- rp->type = VFE_MSG_SNAPSHOT;
- break;
-
- case MSG_OUTPUT1:
- rp->type = VFE_MSG_OUTPUT1;
- vfe_7x_convert(&(rp->phy), VFE_MSG_OUTPUT1,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case MSG_OUTPUT2:
- rp->type = VFE_MSG_OUTPUT2;
- vfe_7x_convert(&(rp->phy), VFE_MSG_OUTPUT2,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case MSG_STATS_AF:
- rp->type = VFE_MSG_STATS_AF;
- vfe_7x_convert(&(rp->phy), VFE_MSG_STATS_AF,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- case MSG_STATS_WE:
- rp->type = VFE_MSG_STATS_WE;
- vfe_7x_convert(&(rp->phy), VFE_MSG_STATS_WE,
- rp->evt_msg.data, NULL, NULL);
-
- CDBG("MSG_STATS_WE: phy = 0x%x\n", rp->phy.sbuf_phy);
- break;
-
- case MSG_STOP_ACK:
- rp->type = VFE_MSG_GENERAL;
- stopevent.state = 1;
- wake_up(&stopevent.wait);
- break;
-
-
- default:
- rp->type = VFE_MSG_GENERAL;
- break;
- }
- resp->vfe_resp(rp, MSM_CAM_Q_VFE_MSG, vfe_syncdata);
- }
-}
-
-static struct msm_adsp_ops vfe_7x_sync = {
- .event = vfe_7x_ops,
-};
-
-static int vfe_7x_enable(struct camera_enable_cmd *enable)
-{
- int rc = -EFAULT;
-
- if (!strcmp(enable->name, "QCAMTASK"))
- rc = msm_adsp_enable(qcam_mod);
- else if (!strcmp(enable->name, "VFETASK"))
- rc = msm_adsp_enable(vfe_mod);
-
- return rc;
-}
-
-static int vfe_7x_disable(struct camera_enable_cmd *enable,
- struct platform_device *dev __attribute__((unused)))
-{
- int rc = -EFAULT;
-
- if (!strcmp(enable->name, "QCAMTASK"))
- rc = msm_adsp_disable(qcam_mod);
- else if (!strcmp(enable->name, "VFETASK"))
- rc = msm_adsp_disable(vfe_mod);
-
- return rc;
-}
-
-static int vfe_7x_stop(void)
-{
- int rc = 0;
- uint32_t stopcmd = VFE_STOP_CMD;
- rc = msm_adsp_write(vfe_mod, QDSP_CMDQUEUE,
- &stopcmd, sizeof(uint32_t));
- if (rc < 0) {
- CDBG("%s:%d: failed rc = %d \n", __func__, __LINE__, rc);
- return rc;
- }
-
- stopevent.state = 0;
- rc = wait_event_timeout(stopevent.wait,
- stopevent.state != 0,
- msecs_to_jiffies(stopevent.timeout));
-
- return rc;
-}
-
-static void vfe_7x_release(struct platform_device *pdev)
-{
- mutex_lock(&vfe_lock);
- vfe_syncdata = NULL;
- mutex_unlock(&vfe_lock);
-
- if (!vfestopped) {
- CDBG("%s:%d:Calling vfe_7x_stop()\n", __func__, __LINE__);
- vfe_7x_stop();
- } else
- vfestopped = 0;
-
- msm_adsp_disable(qcam_mod);
- msm_adsp_disable(vfe_mod);
-
- msm_adsp_put(qcam_mod);
- msm_adsp_put(vfe_mod);
-
- msm_camio_disable(pdev);
-
- kfree(extdata);
- extlen = 0;
-}
-
-static int vfe_7x_init(struct msm_vfe_callback *presp,
- struct platform_device *dev)
-{
- int rc = 0;
-
- init_waitqueue_head(&stopevent.wait);
- stopevent.timeout = 200;
- stopevent.state = 0;
-
- if (presp && presp->vfe_resp)
- resp = presp;
- else
- return -EFAULT;
-
- /* Bring up all the required GPIOs and Clocks */
- rc = msm_camio_enable(dev);
- if (rc < 0)
- return rc;
-
- msm_camio_camif_pad_reg_reset();
-
- extlen = sizeof(struct vfe_frame_extra);
-
- extdata = kmalloc(extlen, GFP_ATOMIC);
- if (!extdata) {
- rc = -ENOMEM;
- goto init_fail;
- }
-
- rc = msm_adsp_get("QCAMTASK", &qcam_mod, &vfe_7x_sync, NULL);
- if (rc) {
- rc = -EBUSY;
- goto get_qcam_fail;
- }
-
- rc = msm_adsp_get("VFETASK", &vfe_mod, &vfe_7x_sync, NULL);
- if (rc) {
- rc = -EBUSY;
- goto get_vfe_fail;
- }
-
- return 0;
-
-get_vfe_fail:
- msm_adsp_put(qcam_mod);
-get_qcam_fail:
- kfree(extdata);
-init_fail:
- extlen = 0;
- return rc;
-}
-
-static int vfe_7x_config_axi(int mode,
- struct axidata *ad, struct axiout *ao)
-{
- struct msm_pmem_region *regptr;
- unsigned long *bptr;
- int cnt;
-
- int rc = 0;
-
- if (mode == OUTPUT_1 || mode == OUTPUT_1_AND_2) {
- regptr = ad->region;
-
- CDBG("bufnum1 = %d\n", ad->bufnum1);
- CDBG("config_axi1: O1, phy = 0x%lx, y_off = %d, cbcr_off =%d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- bptr = &ao->output1buffer1_y_phy;
- for (cnt = 0; cnt < ad->bufnum1; cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
-
- bptr++;
- regptr++;
- }
-
- regptr--;
- for (cnt = 0; cnt < (8 - ad->bufnum1); cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
- bptr++;
- }
- } /* if OUTPUT1 or Both */
-
- if (mode == OUTPUT_2 || mode == OUTPUT_1_AND_2) {
- regptr = &(ad->region[ad->bufnum1]);
-
- CDBG("bufnum2 = %d\n", ad->bufnum2);
- CDBG("config_axi2: O2, phy = 0x%lx, y_off = %d, cbcr_off =%d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- bptr = &ao->output2buffer1_y_phy;
- for (cnt = 0; cnt < ad->bufnum2; cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
-
- bptr++;
- regptr++;
- }
-
- regptr--;
- for (cnt = 0; cnt < (8 - ad->bufnum2); cnt++) {
- *bptr = regptr->paddr + regptr->y_off;
- bptr++;
- *bptr = regptr->paddr + regptr->cbcr_off;
- bptr++;
- }
- }
-
- return rc;
-}
-
-static int vfe_7x_config(struct msm_vfe_cfg_cmd *cmd, void *data)
-{
- struct msm_pmem_region *regptr;
- unsigned char buf[256];
-
- struct vfe_stats_ack sack;
- struct axidata *axid;
- uint32_t i;
-
- struct vfe_stats_we_cfg *scfg = NULL;
- struct vfe_stats_af_cfg *sfcfg = NULL;
-
- struct axiout *axio = NULL;
- void *cmd_data = NULL;
- void *cmd_data_alloc = NULL;
- long rc = 0;
- struct msm_vfe_command_7k *vfecmd;
-
- vfecmd =
- kmalloc(sizeof(struct msm_vfe_command_7k),
- GFP_ATOMIC);
- if (!vfecmd) {
- pr_err("vfecmd alloc failed!\n");
- return -ENOMEM;
- }
-
- if (cmd->cmd_type != CMD_FRAME_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_AF_BUF_RELEASE) {
- if (copy_from_user(vfecmd,
- (void __user *)(cmd->value),
- sizeof(struct msm_vfe_command_7k))) {
- rc = -EFAULT;
- goto config_failure;
- }
- }
-
- switch (cmd->cmd_type) {
- case CMD_STATS_ENABLE:
- case CMD_STATS_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- scfg =
- kmalloc(sizeof(struct vfe_stats_we_cfg),
- GFP_ATOMIC);
- if (!scfg) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(scfg,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- CDBG("STATS_ENABLE: bufnum = %d, enabling = %d\n",
- axid->bufnum1, scfg->wb_expstatsenable);
-
- if (axid->bufnum1 > 0) {
- regptr = axid->region;
-
- for (i = 0; i < axid->bufnum1; i++) {
-
- CDBG("STATS_ENABLE, phy = 0x%lx\n",
- regptr->paddr);
-
- scfg->wb_expstatoutputbuffer[i] =
- (void *)regptr->paddr;
- regptr++;
- }
-
- cmd_data = scfg;
-
- } else {
- rc = -EINVAL;
- goto config_done;
- }
- }
- break;
-
- case CMD_STATS_AF_ENABLE:
- case CMD_STATS_AF_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sfcfg =
- kmalloc(sizeof(struct vfe_stats_af_cfg),
- GFP_ATOMIC);
-
- if (!sfcfg) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(sfcfg,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- CDBG("AF_ENABLE: bufnum = %d, enabling = %d\n",
- axid->bufnum1, sfcfg->af_enable);
-
- if (axid->bufnum1 > 0) {
- regptr = axid->region;
-
- for (i = 0; i < axid->bufnum1; i++) {
-
- CDBG("STATS_ENABLE, phy = 0x%lx\n",
- regptr->paddr);
-
- sfcfg->af_outbuf[i] =
- (void *)regptr->paddr;
-
- regptr++;
- }
-
- cmd_data = sfcfg;
-
- } else {
- rc = -EINVAL;
- goto config_done;
- }
- }
- break;
-
- case CMD_FRAME_BUF_RELEASE: {
- struct msm_frame *b;
- unsigned long p;
- struct vfe_outputack fack;
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- b = (struct msm_frame *)(cmd->value);
- p = *(unsigned long *)data;
-
- fack.header = VFE_FRAME_ACK;
-
- fack.output2newybufferaddress =
- (void *)(p + b->y_off);
-
- fack.output2newcbcrbufferaddress =
- (void *)(p + b->cbcr_off);
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_outputack);
- cmd_data = &fack;
- }
- break;
-
- case CMD_SNAP_BUF_RELEASE:
- break;
-
- case CMD_STATS_BUF_RELEASE: {
- CDBG("vfe_7x_config: CMD_STATS_BUF_RELEASE\n");
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sack.header = STATS_WE_ACK;
- sack.bufaddr = (void *)*(uint32_t *)data;
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_stats_ack);
- cmd_data = &sack;
- }
- break;
-
- case CMD_STATS_AF_BUF_RELEASE: {
- CDBG("vfe_7x_config: CMD_STATS_AF_BUF_RELEASE\n");
- if (!data) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- sack.header = STATS_AF_ACK;
- sack.bufaddr = (void *)*(uint32_t *)data;
-
- vfecmd->queue = QDSP_CMDQUEUE;
- vfecmd->length = sizeof(struct vfe_stats_ack);
- cmd_data = &sack;
- }
- break;
-
- case CMD_GENERAL:
- case CMD_STATS_DISABLE: {
- if (vfecmd->length > 256) {
- cmd_data_alloc =
- cmd_data = kmalloc(vfecmd->length, GFP_ATOMIC);
- if (!cmd_data) {
- rc = -ENOMEM;
- goto config_failure;
- }
- } else
- cmd_data = buf;
-
- if (copy_from_user(cmd_data,
- (void __user *)(vfecmd->value),
- vfecmd->length)) {
-
- rc = -EFAULT;
- goto config_done;
- }
-
- if (vfecmd->queue == QDSP_CMDQUEUE) {
- switch (*(uint32_t *)cmd_data) {
- case VFE_RESET_CMD:
- msm_camio_vfe_blk_reset();
- msm_camio_camif_pad_reg_reset_2();
- vfestopped = 0;
- break;
-
- case VFE_START_CMD:
- msm_camio_camif_pad_reg_reset_2();
- vfestopped = 0;
- break;
-
- case VFE_STOP_CMD:
- vfestopped = 1;
- goto config_send;
-
- default:
- break;
- }
- } /* QDSP_CMDQUEUE */
- }
- break;
-
- case CMD_AXI_CFG_OUT1: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_1, axid, axio);
-
- cmd_data = axio;
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- case CMD_RAW_PICT_AXI_CFG: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void __user *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_2, axid, axio);
- cmd_data = axio;
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2: {
- axid = data;
- if (!axid) {
- rc = -EFAULT;
- goto config_failure;
- }
-
- axio = kmalloc(sizeof(struct axiout), GFP_ATOMIC);
- if (!axio) {
- rc = -ENOMEM;
- goto config_failure;
- }
-
- if (copy_from_user(axio, (void __user *)(vfecmd->value),
- sizeof(struct axiout))) {
- rc = -EFAULT;
- goto config_done;
- }
-
- vfe_7x_config_axi(OUTPUT_1_AND_2, axid, axio);
-
- cmd_data = axio;
- }
- break;
-
- default:
- break;
- } /* switch */
-
- if (vfestopped)
- goto config_done;
-
-config_send:
- CDBG("send adsp command = %d\n", *(uint32_t *)cmd_data);
- rc = msm_adsp_write(vfe_mod, vfecmd->queue,
- cmd_data, vfecmd->length);
-
-config_done:
- if (cmd_data_alloc != NULL)
- kfree(cmd_data_alloc);
-
-config_failure:
- kfree(scfg);
- kfree(axio);
- kfree(vfecmd);
- return rc;
-}
-
-void msm_camvfe_fn_init(struct msm_camvfe_fn *fptr, void *data)
-{
- mutex_init(&vfe_lock);
- fptr->vfe_init = vfe_7x_init;
- fptr->vfe_enable = vfe_7x_enable;
- fptr->vfe_config = vfe_7x_config;
- fptr->vfe_disable = vfe_7x_disable;
- fptr->vfe_release = vfe_7x_release;
- vfe_syncdata = data;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#ifndef __MSM_VFE7X_H__
-#define __MSM_VFE7X_H__
-#include <media/msm_camera.h>
-#include <mach/camera.h>
-
-struct vfe_frame_extra {
- uint32_t bl_evencol;
- uint32_t bl_oddcol;
- uint16_t g_def_p_cnt;
- uint16_t r_b_def_p_cnt;
-};
-
-struct vfe_endframe {
- uint32_t y_address;
- uint32_t cbcr_address;
-
- unsigned int blacklevelevencolumn:23;
- uint16_t reserved1:9;
- unsigned int blackleveloddcolumn:23;
- uint16_t reserved2:9;
-
- uint16_t greendefectpixelcount:8;
- uint16_t reserved3:8;
- uint16_t redbluedefectpixelcount:8;
- uint16_t reserved4:8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_outputack {
- uint32_t header;
- void *output2newybufferaddress;
- void *output2newcbcrbufferaddress;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_ack {
- uint32_t header;
- /* MUST BE 64 bit ALIGNED */
- void *bufaddr;
-} __attribute__((packed, aligned(4)));
-
-/* AXI Output Config Command sent to DSP */
-struct axiout {
- uint32_t cmdheader:32;
- int outputmode:3;
- uint8_t format:2;
- uint32_t /* reserved */ : 27;
-
- /* AXI Output 1 Y Configuration, Part 1 */
- uint32_t out1yimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1yimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 Y Configuration, Part 2 */
- uint8_t out1yburstlen:2;
- uint32_t out1ynumrows:12;
- uint32_t out1yrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 CbCr Configuration, Part 1 */
- uint32_t out1cbcrimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1cbcrimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 1 CbCr Configuration, Part 2 */
- uint8_t out1cbcrburstlen:2;
- uint32_t out1cbcrnumrows:12;
- uint32_t out1cbcrrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 Y Configuration, Part 1 */
- uint32_t out2yimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2yimagewidthin64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 Y Configuration, Part 2 */
- uint8_t out2yburstlen:2;
- uint32_t out2ynumrows:12;
- uint32_t out2yrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 CbCr Configuration, Part 1 */
- uint32_t out2cbcrimageheight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2cbcrimagewidtein64bitwords:10;
- uint32_t /* reserved */ : 6;
-
- /* AXI Output 2 CbCr Configuration, Part 2 */
- uint8_t out2cbcrburstlen:2;
- uint32_t out2cbcrnumrows:12;
- uint32_t out2cbcrrowincin64bitincs:12;
- uint32_t /* reserved */ : 6;
-
- /* Address configuration:
- * output1 phisycal address */
- unsigned long output1buffer1_y_phy;
- unsigned long output1buffer1_cbcr_phy;
- unsigned long output1buffer2_y_phy;
- unsigned long output1buffer2_cbcr_phy;
- unsigned long output1buffer3_y_phy;
- unsigned long output1buffer3_cbcr_phy;
- unsigned long output1buffer4_y_phy;
- unsigned long output1buffer4_cbcr_phy;
- unsigned long output1buffer5_y_phy;
- unsigned long output1buffer5_cbcr_phy;
- unsigned long output1buffer6_y_phy;
- unsigned long output1buffer6_cbcr_phy;
- unsigned long output1buffer7_y_phy;
- unsigned long output1buffer7_cbcr_phy;
- unsigned long output1buffer8_y_phy;
- unsigned long output1buffer8_cbcr_phy;
-
- /* output2 phisycal address */
- unsigned long output2buffer1_y_phy;
- unsigned long output2buffer1_cbcr_phy;
- unsigned long output2buffer2_y_phy;
- unsigned long output2buffer2_cbcr_phy;
- unsigned long output2buffer3_y_phy;
- unsigned long output2buffer3_cbcr_phy;
- unsigned long output2buffer4_y_phy;
- unsigned long output2buffer4_cbcr_phy;
- unsigned long output2buffer5_y_phy;
- unsigned long output2buffer5_cbcr_phy;
- unsigned long output2buffer6_y_phy;
- unsigned long output2buffer6_cbcr_phy;
- unsigned long output2buffer7_y_phy;
- unsigned long output2buffer7_cbcr_phy;
- unsigned long output2buffer8_y_phy;
- unsigned long output2buffer8_cbcr_phy;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_we_cfg {
- uint32_t header;
-
- /* White Balance/Exposure Statistic Selection */
- uint8_t wb_expstatsenable:1;
- uint8_t wb_expstatbuspriorityselection:1;
- unsigned int wb_expstatbuspriorityvalue:4;
- unsigned int /* reserved */ : 26;
-
- /* White Balance/Exposure Statistic Configuration, Part 1 */
- uint8_t exposurestatregions:1;
- uint8_t exposurestatsubregions:1;
- unsigned int /* reserved */ : 14;
-
- unsigned int whitebalanceminimumy:8;
- unsigned int whitebalancemaximumy:8;
-
- /* White Balance/Exposure Statistic Configuration, Part 2 */
- uint8_t wb_expstatslopeofneutralregionline[
- NUM_WB_EXP_NEUTRAL_REGION_LINES];
-
- /* White Balance/Exposure Statistic Configuration, Part 3 */
- unsigned int wb_expstatcrinterceptofneutralregionline2:12;
- unsigned int /* reserved */ : 4;
- unsigned int wb_expstatcbinterceptofneutralreginnline1:12;
- unsigned int /* reserved */ : 4;
-
- /* White Balance/Exposure Statistic Configuration, Part 4 */
- unsigned int wb_expstatcrinterceptofneutralregionline4:12;
- unsigned int /* reserved */ : 4;
- unsigned int wb_expstatcbinterceptofneutralregionline3:12;
- unsigned int /* reserved */ : 4;
-
- /* White Balance/Exposure Statistic Output Buffer Header */
- unsigned int wb_expmetricheaderpattern:8;
- unsigned int /* reserved */ : 24;
-
- /* White Balance/Exposure Statistic Output Buffers-MUST
- * BE 64 bit ALIGNED */
- void *wb_expstatoutputbuffer[NUM_WB_EXP_STAT_OUTPUT_BUFFERS];
-} __attribute__((packed, aligned(4)));
-
-struct vfe_stats_af_cfg {
- uint32_t header;
-
- /* Autofocus Statistic Selection */
- uint8_t af_enable:1;
- uint8_t af_busprioritysel:1;
- unsigned int af_buspriorityval:4;
- unsigned int /* reserved */ : 26;
-
- /* Autofocus Statistic Configuration, Part 1 */
- unsigned int af_singlewinvoffset:12;
- unsigned int /* reserved */ : 4;
- unsigned int af_singlewinhoffset:12;
- unsigned int /* reserved */ : 3;
- uint8_t af_winmode:1;
-
- /* Autofocus Statistic Configuration, Part 2 */
- unsigned int af_singglewinvh:11;
- unsigned int /* reserved */ : 5;
- unsigned int af_singlewinhw:11;
- unsigned int /* reserved */ : 5;
-
- /* Autofocus Statistic Configuration, Parts 3-6 */
- uint8_t af_multiwingrid[NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS];
-
- /* Autofocus Statistic Configuration, Part 7 */
- signed int af_metrichpfcoefa00:5;
- signed int af_metrichpfcoefa04:5;
- unsigned int af_metricmaxval:11;
- uint8_t af_metricsel:1;
- unsigned int /* reserved */ : 10;
-
- /* Autofocus Statistic Configuration, Part 8 */
- signed int af_metrichpfcoefa20:5;
- signed int af_metrichpfcoefa21:5;
- signed int af_metrichpfcoefa22:5;
- signed int af_metrichpfcoefa23:5;
- signed int af_metrichpfcoefa24:5;
- unsigned int /* reserved */ : 7;
-
- /* Autofocus Statistic Output Buffer Header */
- unsigned int af_metrichp:8;
- unsigned int /* reserved */ : 24;
-
- /* Autofocus Statistic Output Buffers - MUST BE 64 bit ALIGNED!!! */
- void *af_outbuf[NUM_AF_STAT_OUTPUT_BUFFERS];
-} __attribute__((packed, aligned(4))); /* VFE_StatsAutofocusConfigCmdType */
-
-struct msm_camera_frame_msg {
- unsigned long output_y_address;
- unsigned long output_cbcr_address;
-
- unsigned int blacklevelevenColumn:23;
- uint16_t reserved1:9;
- unsigned int blackleveloddColumn:23;
- uint16_t reserved2:9;
-
- uint16_t greendefectpixelcount:8;
- uint16_t reserved3:8;
- uint16_t redbluedefectpixelcount:8;
- uint16_t reserved4:8;
-} __attribute__((packed, aligned(4)));
-
-/* New one for 7k */
-struct msm_vfe_command_7k {
- uint16_t queue;
- uint16_t length;
- void *value;
-};
-
-struct stop_event {
- wait_queue_head_t wait;
- int state;
- int timeout;
-};
-
-
-#endif /* __MSM_VFE7X_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/interrupt.h>
-#include <mach/irqs.h>
-#include "msm_vfe8x_proc.h"
-
-#define ON 1
-#define OFF 0
-
-struct mutex vfe_lock;
-static void *vfe_syncdata;
-
-static int vfe_enable(struct camera_enable_cmd *enable)
-{
- int rc = 0;
- return rc;
-}
-
-static int vfe_disable(struct camera_enable_cmd *enable,
- struct platform_device *dev)
-{
- int rc = 0;
-
- vfe_stop();
-
- msm_camio_disable(dev);
- return rc;
-}
-
-static void vfe_release(struct platform_device *dev)
-{
- msm_camio_disable(dev);
- vfe_cmd_release(dev);
-
- mutex_lock(&vfe_lock);
- vfe_syncdata = NULL;
- mutex_unlock(&vfe_lock);
-}
-
-static void vfe_config_axi(int mode,
- struct axidata *ad, struct vfe_cmd_axi_output_config *ao)
-{
- struct msm_pmem_region *regptr;
- int i, j;
- uint32_t *p1, *p2;
-
- if (mode == OUTPUT_1 || mode == OUTPUT_1_AND_2) {
- regptr = ad->region;
- for (i = 0;
- i < ad->bufnum1; i++) {
-
- p1 = &(ao->output1.outputY.outFragments[i][0]);
- p2 = &(ao->output1.outputCbcr.outFragments[i][0]);
-
- for (j = 0;
- j < ao->output1.fragmentCount; j++) {
-
- *p1 = regptr->paddr + regptr->y_off;
- p1++;
-
- *p2 = regptr->paddr + regptr->cbcr_off;
- p2++;
- }
- regptr++;
- }
- } /* if OUTPUT1 or Both */
-
- if (mode == OUTPUT_2 || mode == OUTPUT_1_AND_2) {
-
- regptr = &(ad->region[ad->bufnum1]);
- CDBG("bufnum2 = %d\n", ad->bufnum2);
-
- for (i = 0;
- i < ad->bufnum2; i++) {
-
- p1 = &(ao->output2.outputY.outFragments[i][0]);
- p2 = &(ao->output2.outputCbcr.outFragments[i][0]);
-
- CDBG("config_axi: O2, phy = 0x%lx, y_off = %d, cbcr_off = %d\n",
- regptr->paddr, regptr->y_off, regptr->cbcr_off);
-
- for (j = 0;
- j < ao->output2.fragmentCount; j++) {
-
- *p1 = regptr->paddr + regptr->y_off;
- CDBG("vfe_config_axi: p1 = 0x%x\n", *p1);
- p1++;
-
- *p2 = regptr->paddr + regptr->cbcr_off;
- CDBG("vfe_config_axi: p2 = 0x%x\n", *p2);
- p2++;
- }
- regptr++;
- }
- }
-}
-
-static int vfe_proc_general(struct msm_vfe_command_8k *cmd)
-{
- int rc = 0;
-
- CDBG("vfe_proc_general: cmdID = %d\n", cmd->id);
-
- switch (cmd->id) {
- case VFE_CMD_ID_RESET:
- msm_camio_vfe_blk_reset();
- msm_camio_camif_pad_reg_reset_2();
- vfe_reset();
- break;
-
- case VFE_CMD_ID_START: {
- struct vfe_cmd_start start;
- if (copy_from_user(&start,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- /* msm_camio_camif_pad_reg_reset_2(); */
- msm_camio_camif_pad_reg_reset();
- vfe_start(&start);
- }
- break;
-
- case VFE_CMD_ID_CAMIF_CONFIG: {
- struct vfe_cmd_camif_config camif;
- if (copy_from_user(&camif,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_camif_config(&camif);
- }
- break;
-
- case VFE_CMD_ID_BLACK_LEVEL_CONFIG: {
- struct vfe_cmd_black_level_config bl;
- if (copy_from_user(&bl,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_black_level_config(&bl);
- }
- break;
-
- case VFE_CMD_ID_ROLL_OFF_CONFIG: {
- struct vfe_cmd_roll_off_config rolloff;
- if (copy_from_user(&rolloff,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_roll_off_config(&rolloff);
- }
- break;
-
- case VFE_CMD_ID_DEMUX_CHANNEL_GAIN_CONFIG: {
- struct vfe_cmd_demux_channel_gain_config demuxc;
- if (copy_from_user(&demuxc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- /* demux is always enabled. */
- vfe_demux_channel_gain_config(&demuxc);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_CONFIG: {
- struct vfe_cmd_demosaic_config demosaic;
- if (copy_from_user(&demosaic,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_config(&demosaic);
- }
- break;
-
- case VFE_CMD_ID_FOV_CROP_CONFIG:
- case VFE_CMD_ID_FOV_CROP_UPDATE: {
- struct vfe_cmd_fov_crop_config fov;
- if (copy_from_user(&fov,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_fov_crop_config(&fov);
- }
- break;
-
- case VFE_CMD_ID_MAIN_SCALER_CONFIG:
- case VFE_CMD_ID_MAIN_SCALER_UPDATE: {
- struct vfe_cmd_main_scaler_config mainds;
- if (copy_from_user(&mainds,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_main_scaler_config(&mainds);
- }
- break;
-
- case VFE_CMD_ID_WHITE_BALANCE_CONFIG:
- case VFE_CMD_ID_WHITE_BALANCE_UPDATE: {
- struct vfe_cmd_white_balance_config wb;
- if (copy_from_user(&wb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_white_balance_config(&wb);
- }
- break;
-
- case VFE_CMD_ID_COLOR_CORRECTION_CONFIG:
- case VFE_CMD_ID_COLOR_CORRECTION_UPDATE: {
- struct vfe_cmd_color_correction_config cc;
- if (copy_from_user(&cc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_color_correction_config(&cc);
- }
- break;
-
- case VFE_CMD_ID_LA_CONFIG: {
- struct vfe_cmd_la_config la;
- if (copy_from_user(&la,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_la_config(&la);
- }
- break;
-
- case VFE_CMD_ID_RGB_GAMMA_CONFIG: {
- struct vfe_cmd_rgb_gamma_config rgb;
- if (copy_from_user(&rgb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- rc = vfe_rgb_gamma_config(&rgb);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_ENHAN_CONFIG:
- case VFE_CMD_ID_CHROMA_ENHAN_UPDATE: {
- struct vfe_cmd_chroma_enhan_config chrom;
- if (copy_from_user(&chrom,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_enhan_config(&chrom);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_SUPPRESSION_CONFIG:
- case VFE_CMD_ID_CHROMA_SUPPRESSION_UPDATE: {
- struct vfe_cmd_chroma_suppression_config chromsup;
- if (copy_from_user(&chromsup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_sup_config(&chromsup);
- }
- break;
-
- case VFE_CMD_ID_ASF_CONFIG: {
- struct vfe_cmd_asf_config asf;
- if (copy_from_user(&asf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_asf_config(&asf);
- }
- break;
-
- case VFE_CMD_ID_SCALER2Y_CONFIG:
- case VFE_CMD_ID_SCALER2Y_UPDATE: {
- struct vfe_cmd_scaler2_config ds2y;
- if (copy_from_user(&ds2y,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_scaler2y_config(&ds2y);
- }
- break;
-
- case VFE_CMD_ID_SCALER2CbCr_CONFIG:
- case VFE_CMD_ID_SCALER2CbCr_UPDATE: {
- struct vfe_cmd_scaler2_config ds2cbcr;
- if (copy_from_user(&ds2cbcr,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_scaler2cbcr_config(&ds2cbcr);
- }
- break;
-
- case VFE_CMD_ID_CHROMA_SUBSAMPLE_CONFIG: {
- struct vfe_cmd_chroma_subsample_config sub;
- if (copy_from_user(&sub,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_chroma_subsample_config(&sub);
- }
- break;
-
- case VFE_CMD_ID_FRAME_SKIP_CONFIG: {
- struct vfe_cmd_frame_skip_config fskip;
- if (copy_from_user(&fskip,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_frame_skip_config(&fskip);
- }
- break;
-
- case VFE_CMD_ID_OUTPUT_CLAMP_CONFIG: {
- struct vfe_cmd_output_clamp_config clamp;
- if (copy_from_user(&clamp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_output_clamp_config(&clamp);
- }
- break;
-
- /* module update commands */
- case VFE_CMD_ID_BLACK_LEVEL_UPDATE: {
- struct vfe_cmd_black_level_config blk;
- if (copy_from_user(&blk,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_black_level_update(&blk);
- }
- break;
-
- case VFE_CMD_ID_DEMUX_CHANNEL_GAIN_UPDATE: {
- struct vfe_cmd_demux_channel_gain_config dmu;
- if (copy_from_user(&dmu,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demux_channel_gain_update(&dmu);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_BPC_UPDATE: {
- struct vfe_cmd_demosaic_bpc_update demo_bpc;
- if (copy_from_user(&demo_bpc,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_bpc_update(&demo_bpc);
- }
- break;
-
- case VFE_CMD_ID_DEMOSAIC_ABF_UPDATE: {
- struct vfe_cmd_demosaic_abf_update demo_abf;
- if (copy_from_user(&demo_abf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_demosaic_abf_update(&demo_abf);
- }
- break;
-
- case VFE_CMD_ID_LA_UPDATE: {
- struct vfe_cmd_la_config la;
- if (copy_from_user(&la,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_la_update(&la);
- }
- break;
-
- case VFE_CMD_ID_RGB_GAMMA_UPDATE: {
- struct vfe_cmd_rgb_gamma_config rgb;
- if (copy_from_user(&rgb,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- rc = vfe_rgb_gamma_update(&rgb);
- }
- break;
-
- case VFE_CMD_ID_ASF_UPDATE: {
- struct vfe_cmd_asf_update asf;
- if (copy_from_user(&asf,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_asf_update(&asf);
- }
- break;
-
- case VFE_CMD_ID_FRAME_SKIP_UPDATE: {
- struct vfe_cmd_frame_skip_update fskip;
- if (copy_from_user(&fskip,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_frame_skip_update(&fskip);
- }
- break;
-
- case VFE_CMD_ID_CAMIF_FRAME_UPDATE: {
- struct vfe_cmds_camif_frame fup;
- if (copy_from_user(&fup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_camif_frame_update(&fup);
- }
- break;
-
- /* stats update commands */
- case VFE_CMD_ID_STATS_AUTOFOCUS_UPDATE: {
- struct vfe_cmd_stats_af_update afup;
- if (copy_from_user(&afup,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_update_af(&afup);
- }
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_UPDATE: {
- struct vfe_cmd_stats_wb_exp_update wbexp;
- if (copy_from_user(&wbexp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_update_wb_exp(&wbexp);
- }
- break;
-
- /* control of start, stop, update, etc... */
- case VFE_CMD_ID_STOP:
- vfe_stop();
- break;
-
- case VFE_CMD_ID_GET_HW_VERSION:
- break;
-
- /* stats */
- case VFE_CMD_ID_STATS_SETTING: {
- struct vfe_cmd_stats_setting stats;
- if (copy_from_user(&stats,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_setting(&stats);
- }
- break;
-
- case VFE_CMD_ID_STATS_AUTOFOCUS_START: {
- struct vfe_cmd_stats_af_start af;
- if (copy_from_user(&af,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_start_af(&af);
- }
- break;
-
- case VFE_CMD_ID_STATS_AUTOFOCUS_STOP:
- vfe_stats_af_stop();
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_START: {
- struct vfe_cmd_stats_wb_exp_start awexp;
- if (copy_from_user(&awexp,
- (void __user *) cmd->value, cmd->length))
- rc = -EFAULT;
-
- vfe_stats_start_wb_exp(&awexp);
- }
- break;
-
- case VFE_CMD_ID_STATS_WB_EXP_STOP:
- vfe_stats_wb_exp_stop();
- break;
-
- case VFE_CMD_ID_ASYNC_TIMER_SETTING:
- break;
-
- case VFE_CMD_ID_UPDATE:
- vfe_update();
- break;
-
- /* test gen */
- case VFE_CMD_ID_TEST_GEN_START:
- break;
-
-/*
- acknowledge from upper layer
- these are not in general command.
-
- case VFE_CMD_ID_OUTPUT1_ACK:
- break;
- case VFE_CMD_ID_OUTPUT2_ACK:
- break;
- case VFE_CMD_ID_EPOCH1_ACK:
- break;
- case VFE_CMD_ID_EPOCH2_ACK:
- break;
- case VFE_CMD_ID_STATS_AUTOFOCUS_ACK:
- break;
- case VFE_CMD_ID_STATS_WB_EXP_ACK:
- break;
-*/
-
- default:
- break;
- } /* switch */
-
- return rc;
-}
-
-static int vfe_config(struct msm_vfe_cfg_cmd *cmd, void *data)
-{
- struct msm_pmem_region *regptr;
- struct msm_vfe_command_8k vfecmd;
-
- uint32_t i;
-
- void *cmd_data = NULL;
- long rc = 0;
-
- struct vfe_cmd_axi_output_config *axio = NULL;
- struct vfe_cmd_stats_setting *scfg = NULL;
-
- if (cmd->cmd_type != CMD_FRAME_BUF_RELEASE &&
- cmd->cmd_type != CMD_STATS_BUF_RELEASE) {
-
- if (copy_from_user(&vfecmd,
- (void __user *)(cmd->value),
- sizeof(struct msm_vfe_command_8k)))
- return -EFAULT;
- }
-
- CDBG("vfe_config: cmdType = %d\n", cmd->cmd_type);
-
- switch (cmd->cmd_type) {
- case CMD_GENERAL:
- rc = vfe_proc_general(&vfecmd);
- break;
-
- case CMD_STATS_ENABLE:
- case CMD_STATS_AXI_CFG: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- scfg =
- kmalloc(sizeof(struct vfe_cmd_stats_setting),
- GFP_ATOMIC);
- if (!scfg)
- return -ENOMEM;
-
- if (copy_from_user(scfg,
- (void __user *)(vfecmd.value),
- vfecmd.length)) {
-
- kfree(scfg);
- return -EFAULT;
- }
-
- regptr = axid->region;
- if (axid->bufnum1 > 0) {
- for (i = 0; i < axid->bufnum1; i++) {
- scfg->awbBuffer[i] =
- (uint32_t)(regptr->paddr);
- regptr++;
- }
- }
-
- if (axid->bufnum2 > 0) {
- for (i = 0; i < axid->bufnum2; i++) {
- scfg->afBuffer[i] =
- (uint32_t)(regptr->paddr);
- regptr++;
- }
- }
-
- vfe_stats_config(scfg);
- }
- break;
-
- case CMD_STATS_AF_AXI_CFG: {
- }
- break;
-
- case CMD_FRAME_BUF_RELEASE: {
- /* preview buffer release */
- struct msm_frame *b;
- unsigned long p;
- struct vfe_cmd_output_ack fack;
-
- if (!data)
- return -EFAULT;
-
- b = (struct msm_frame *)(cmd->value);
- p = *(unsigned long *)data;
-
- b->path = MSM_FRAME_ENC;
-
- fack.ybufaddr[0] =
- (uint32_t)(p + b->y_off);
-
- fack.chromabufaddr[0] =
- (uint32_t)(p + b->cbcr_off);
-
- if (b->path == MSM_FRAME_PREV_1)
- vfe_output1_ack(&fack);
-
- if (b->path == MSM_FRAME_ENC ||
- b->path == MSM_FRAME_PREV_2)
- vfe_output2_ack(&fack);
- }
- break;
-
- case CMD_SNAP_BUF_RELEASE: {
- }
- break;
-
- case CMD_STATS_BUF_RELEASE: {
- struct vfe_cmd_stats_wb_exp_ack sack;
-
- if (!data)
- return -EFAULT;
-
- sack.nextWbExpOutputBufferAddr = *(uint32_t *)data;
- vfe_stats_wb_exp_ack(&sack);
- }
- break;
-
- case CMD_AXI_CFG_OUT1: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_1, axid, axio);
- vfe_axi_output_config(axio);
- }
- break;
-
- case CMD_AXI_CFG_OUT2:
- case CMD_RAW_PICT_AXI_CFG: {
- struct axidata *axid;
-
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_2, axid, axio);
-
- axio->outputDataSize = 0;
- vfe_axi_output_config(axio);
- }
- break;
-
- case CMD_AXI_CFG_SNAP_O1_AND_O2: {
- struct axidata *axid;
- axid = data;
- if (!axid)
- return -EFAULT;
-
- axio = memdup_user((void __user *)(vfecmd.value),
- sizeof(struct vfe_cmd_axi_output_config));
- if (IS_ERR(axio))
- return PTR_ERR(axio);
-
- vfe_config_axi(OUTPUT_1_AND_2,
- axid, axio);
- vfe_axi_output_config(axio);
- cmd_data = axio;
- }
- break;
-
- default:
- break;
- } /* switch */
-
- kfree(scfg);
-
- kfree(axio);
-
-/*
- if (cmd->length > 256 &&
- cmd_data &&
- (cmd->cmd_type == CMD_GENERAL ||
- cmd->cmd_type == CMD_STATS_DISABLE)) {
- kfree(cmd_data);
- }
-*/
- return rc;
-}
-
-static int vfe_init(struct msm_vfe_callback *presp,
- struct platform_device *dev)
-{
- int rc = 0;
-
- rc = vfe_cmd_init(presp, dev, vfe_syncdata);
- if (rc < 0)
- return rc;
-
- /* Bring up all the required GPIOs and Clocks */
- return msm_camio_enable(dev);
-}
-
-void msm_camvfe_fn_init(struct msm_camvfe_fn *fptr, void *data)
-{
- mutex_init(&vfe_lock);
- fptr->vfe_init = vfe_init;
- fptr->vfe_enable = vfe_enable;
- fptr->vfe_config = vfe_config;
- fptr->vfe_disable = vfe_disable;
- fptr->vfe_release = vfe_release;
- vfe_syncdata = data;
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#ifndef __MSM_VFE8X_H__
-#define __MSM_VFE8X_H__
-
-#define TRUE 1
-#define FALSE 0
-#define boolean uint8_t
-
-enum VFE_STATE {
- VFE_STATE_IDLE,
- VFE_STATE_ACTIVE
-};
-
-enum vfe_cmd_id {
- /*
- *Important! Command_ID are arranged in order.
- *Don't change!*/
- VFE_CMD_ID_START,
- VFE_CMD_ID_RESET,
-
- /* bus and camif config */
- VFE_CMD_ID_AXI_INPUT_CONFIG,
- VFE_CMD_ID_CAMIF_CONFIG,
- VFE_CMD_ID_AXI_OUTPUT_CONFIG,
-
- /* module config */
- VFE_CMD_ID_BLACK_LEVEL_CONFIG,
- VFE_CMD_ID_ROLL_OFF_CONFIG,
- VFE_CMD_ID_DEMUX_CHANNEL_GAIN_CONFIG,
- VFE_CMD_ID_DEMOSAIC_CONFIG,
- VFE_CMD_ID_FOV_CROP_CONFIG,
- VFE_CMD_ID_MAIN_SCALER_CONFIG,
- VFE_CMD_ID_WHITE_BALANCE_CONFIG,
- VFE_CMD_ID_COLOR_CORRECTION_CONFIG,
- VFE_CMD_ID_LA_CONFIG,
- VFE_CMD_ID_RGB_GAMMA_CONFIG,
- VFE_CMD_ID_CHROMA_ENHAN_CONFIG,
- VFE_CMD_ID_CHROMA_SUPPRESSION_CONFIG,
- VFE_CMD_ID_ASF_CONFIG,
- VFE_CMD_ID_SCALER2Y_CONFIG,
- VFE_CMD_ID_SCALER2CbCr_CONFIG,
- VFE_CMD_ID_CHROMA_SUBSAMPLE_CONFIG,
- VFE_CMD_ID_FRAME_SKIP_CONFIG,
- VFE_CMD_ID_OUTPUT_CLAMP_CONFIG,
-
- /* test gen */
- VFE_CMD_ID_TEST_GEN_START,
-
- VFE_CMD_ID_UPDATE,
-
- /* ackownledge from upper layer */
- VFE_CMD_ID_OUTPUT1_ACK,
- VFE_CMD_ID_OUTPUT2_ACK,
- VFE_CMD_ID_EPOCH1_ACK,
- VFE_CMD_ID_EPOCH2_ACK,
- VFE_CMD_ID_STATS_AUTOFOCUS_ACK,
- VFE_CMD_ID_STATS_WB_EXP_ACK,
-
- /* module update commands */
- VFE_CMD_ID_BLACK_LEVEL_UPDATE,
- VFE_CMD_ID_DEMUX_CHANNEL_GAIN_UPDATE,
- VFE_CMD_ID_DEMOSAIC_BPC_UPDATE,
- VFE_CMD_ID_DEMOSAIC_ABF_UPDATE,
- VFE_CMD_ID_FOV_CROP_UPDATE,
- VFE_CMD_ID_WHITE_BALANCE_UPDATE,
- VFE_CMD_ID_COLOR_CORRECTION_UPDATE,
- VFE_CMD_ID_LA_UPDATE,
- VFE_CMD_ID_RGB_GAMMA_UPDATE,
- VFE_CMD_ID_CHROMA_ENHAN_UPDATE,
- VFE_CMD_ID_CHROMA_SUPPRESSION_UPDATE,
- VFE_CMD_ID_MAIN_SCALER_UPDATE,
- VFE_CMD_ID_SCALER2CbCr_UPDATE,
- VFE_CMD_ID_SCALER2Y_UPDATE,
- VFE_CMD_ID_ASF_UPDATE,
- VFE_CMD_ID_FRAME_SKIP_UPDATE,
- VFE_CMD_ID_CAMIF_FRAME_UPDATE,
-
- /* stats update commands */
- VFE_CMD_ID_STATS_AUTOFOCUS_UPDATE,
- VFE_CMD_ID_STATS_WB_EXP_UPDATE,
-
- /* control of start, stop, update, etc... */
- VFE_CMD_ID_STOP,
- VFE_CMD_ID_GET_HW_VERSION,
-
- /* stats */
- VFE_CMD_ID_STATS_SETTING,
- VFE_CMD_ID_STATS_AUTOFOCUS_START,
- VFE_CMD_ID_STATS_AUTOFOCUS_STOP,
- VFE_CMD_ID_STATS_WB_EXP_START,
- VFE_CMD_ID_STATS_WB_EXP_STOP,
-
- VFE_CMD_ID_ASYNC_TIMER_SETTING,
-
- /* max id */
- VFE_CMD_ID_MAX
-};
-
-struct vfe_cmd_hw_version {
- uint32_t minorVersion;
- uint32_t majorVersion;
- uint32_t coreVersion;
-};
-
-enum VFE_CAMIF_SYNC_EDGE {
- VFE_CAMIF_SYNC_EDGE_ActiveHigh,
- VFE_CAMIF_SYNC_EDGE_ActiveLow
-};
-
-enum VFE_CAMIF_SYNC_MODE {
- VFE_CAMIF_SYNC_MODE_APS,
- VFE_CAMIF_SYNC_MODE_EFS,
- VFE_CAMIF_SYNC_MODE_ELS,
- VFE_CAMIF_SYNC_MODE_ILLEGAL
-};
-
-struct vfe_cmds_camif_efs {
- uint8_t efsendofline;
- uint8_t efsstartofline;
- uint8_t efsendofframe;
- uint8_t efsstartofframe;
-};
-
-struct vfe_cmds_camif_frame {
- uint16_t pixelsPerLine;
- uint16_t linesPerFrame;
-};
-
-struct vfe_cmds_camif_window {
- uint16_t firstpixel;
- uint16_t lastpixel;
- uint16_t firstline;
- uint16_t lastline;
-};
-
-enum CAMIF_SUBSAMPLE_FRAME_SKIP {
- CAMIF_SUBSAMPLE_FRAME_SKIP_0,
- CAMIF_SUBSAMPLE_FRAME_SKIP_AllFrames,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_2Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_3Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_4Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_5Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_6Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_7Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_8Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_9Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_10Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_11Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_12Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_13Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_14Frame,
- CAMIF_SUBSAMPLE_FRAME_SKIP_ONE_OUT_OF_EVERY_15Frame
-};
-
-struct vfe_cmds_camif_subsample {
- uint16_t pixelskipmask;
- uint16_t lineskipmask;
- enum CAMIF_SUBSAMPLE_FRAME_SKIP frameskip;
- uint8_t frameskipmode;
- uint8_t pixelskipwrap;
-};
-
-struct vfe_cmds_camif_epoch {
- uint8_t enable;
- uint16_t lineindex;
-};
-
-struct vfe_cmds_camif_cfg {
- enum VFE_CAMIF_SYNC_EDGE vSyncEdge;
- enum VFE_CAMIF_SYNC_EDGE hSyncEdge;
- enum VFE_CAMIF_SYNC_MODE syncMode;
- uint8_t vfeSubSampleEnable;
- uint8_t busSubSampleEnable;
- uint8_t irqSubSampleEnable;
- uint8_t binningEnable;
- uint8_t misrEnable;
-};
-
-struct vfe_cmd_camif_config {
- struct vfe_cmds_camif_cfg camifConfig;
- struct vfe_cmds_camif_efs EFS;
- struct vfe_cmds_camif_frame frame;
- struct vfe_cmds_camif_window window;
- struct vfe_cmds_camif_subsample subsample;
- struct vfe_cmds_camif_epoch epoch1;
- struct vfe_cmds_camif_epoch epoch2;
-};
-
-enum VFE_AXI_OUTPUT_MODE {
- VFE_AXI_OUTPUT_MODE_Output1,
- VFE_AXI_OUTPUT_MODE_Output2,
- VFE_AXI_OUTPUT_MODE_Output1AndOutput2,
- VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2,
- VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1,
- VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2,
- VFE_AXI_LAST_OUTPUT_MODE_ENUM
-};
-
-enum VFE_RAW_WR_PATH_SEL {
- VFE_RAW_OUTPUT_DISABLED,
- VFE_RAW_OUTPUT_ENC_CBCR_PATH,
- VFE_RAW_OUTPUT_VIEW_CBCR_PATH,
- VFE_RAW_OUTPUT_PATH_INVALID
-};
-
-enum VFE_RAW_PIXEL_DATA_SIZE {
- VFE_RAW_PIXEL_DATA_SIZE_8BIT,
- VFE_RAW_PIXEL_DATA_SIZE_10BIT,
- VFE_RAW_PIXEL_DATA_SIZE_12BIT,
-};
-
-#define VFE_AXI_OUTPUT_BURST_LENGTH 4
-#define VFE_MAX_NUM_FRAGMENTS_PER_FRAME 4
-#define VFE_AXI_OUTPUT_CFG_FRAME_COUNT 3
-
-struct vfe_cmds_axi_out_per_component {
- uint16_t imageWidth;
- uint16_t imageHeight;
- uint16_t outRowCount;
- uint16_t outRowIncrement;
- uint32_t outFragments[VFE_AXI_OUTPUT_CFG_FRAME_COUNT]
- [VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
-};
-
-struct vfe_cmds_axi_per_output_path {
- uint8_t fragmentCount;
- struct vfe_cmds_axi_out_per_component outputY;
- struct vfe_cmds_axi_out_per_component outputCbcr;
-};
-
-enum VFE_AXI_BURST_LENGTH {
- VFE_AXI_BURST_LENGTH_IS_2 = 2,
- VFE_AXI_BURST_LENGTH_IS_4 = 4,
- VFE_AXI_BURST_LENGTH_IS_8 = 8,
- VFE_AXI_BURST_LENGTH_IS_16 = 16
-};
-
-struct vfe_cmd_axi_output_config {
- enum VFE_AXI_BURST_LENGTH burstLength;
- enum VFE_AXI_OUTPUT_MODE outputMode;
- enum VFE_RAW_PIXEL_DATA_SIZE outputDataSize;
- struct vfe_cmds_axi_per_output_path output1;
- struct vfe_cmds_axi_per_output_path output2;
-};
-
-struct vfe_cmd_fov_crop_config {
- uint8_t enable;
- uint16_t firstPixel;
- uint16_t lastPixel;
- uint16_t firstLine;
- uint16_t lastLine;
-};
-
-struct vfe_cmds_main_scaler_stripe_init {
- uint16_t MNCounterInit;
- uint16_t phaseInit;
-};
-
-struct vfe_cmds_scaler_one_dimension {
- uint8_t enable;
- uint16_t inputSize;
- uint16_t outputSize;
- uint32_t phaseMultiplicationFactor;
- uint8_t interpolationResolution;
-};
-
-struct vfe_cmd_main_scaler_config {
- uint8_t enable;
- struct vfe_cmds_scaler_one_dimension hconfig;
- struct vfe_cmds_scaler_one_dimension vconfig;
- struct vfe_cmds_main_scaler_stripe_init MNInitH;
- struct vfe_cmds_main_scaler_stripe_init MNInitV;
-};
-
-struct vfe_cmd_scaler2_config {
- uint8_t enable;
- struct vfe_cmds_scaler_one_dimension hconfig;
- struct vfe_cmds_scaler_one_dimension vconfig;
-};
-
-struct vfe_cmd_frame_skip_config {
- uint8_t output1Period;
- uint32_t output1Pattern;
- uint8_t output2Period;
- uint32_t output2Pattern;
-};
-
-struct vfe_cmd_frame_skip_update {
- uint32_t output1Pattern;
- uint32_t output2Pattern;
-};
-
-struct vfe_cmd_output_clamp_config {
- uint8_t minCh0;
- uint8_t minCh1;
- uint8_t minCh2;
- uint8_t maxCh0;
- uint8_t maxCh1;
- uint8_t maxCh2;
-};
-
-struct vfe_cmd_chroma_subsample_config {
- uint8_t enable;
- uint8_t cropEnable;
- uint8_t vsubSampleEnable;
- uint8_t hsubSampleEnable;
- uint8_t vCosited;
- uint8_t hCosited;
- uint8_t vCositedPhase;
- uint8_t hCositedPhase;
- uint16_t cropWidthFirstPixel;
- uint16_t cropWidthLastPixel;
- uint16_t cropHeightFirstLine;
- uint16_t cropHeightLastLine;
-};
-
-enum VFE_START_INPUT_SOURCE {
- VFE_START_INPUT_SOURCE_CAMIF,
- VFE_START_INPUT_SOURCE_TESTGEN,
- VFE_START_INPUT_SOURCE_AXI,
- VFE_START_INPUT_SOURCE_INVALID
-};
-
-enum VFE_START_OPERATION_MODE {
- VFE_START_OPERATION_MODE_CONTINUOUS,
- VFE_START_OPERATION_MODE_SNAPSHOT
-};
-
-enum VFE_START_PIXEL_PATTERN {
- VFE_BAYER_RGRGRG,
- VFE_BAYER_GRGRGR,
- VFE_BAYER_BGBGBG,
- VFE_BAYER_GBGBGB,
- VFE_YUV_YCbYCr,
- VFE_YUV_YCrYCb,
- VFE_YUV_CbYCrY,
- VFE_YUV_CrYCbY
-};
-
-enum VFE_BUS_RD_INPUT_PIXEL_PATTERN {
- VFE_BAYER_RAW,
- VFE_YUV_INTERLEAVED,
- VFE_YUV_PSEUDO_PLANAR_Y,
- VFE_YUV_PSEUDO_PLANAR_CBCR
-};
-
-enum VFE_YUV_INPUT_COSITING_MODE {
- VFE_YUV_COSITED,
- VFE_YUV_INTERPOLATED
-};
-
-struct vfe_cmd_start {
- enum VFE_START_INPUT_SOURCE inputSource;
- enum VFE_START_OPERATION_MODE operationMode;
- uint8_t snapshotCount;
- enum VFE_START_PIXEL_PATTERN pixel;
- enum VFE_YUV_INPUT_COSITING_MODE yuvInputCositingMode;
-};
-
-struct vfe_cmd_output_ack {
- uint32_t ybufaddr[VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
- uint32_t chromabufaddr[VFE_MAX_NUM_FRAGMENTS_PER_FRAME];
-};
-
-#define VFE_STATS_BUFFER_COUNT 3
-
-struct vfe_cmd_stats_setting {
- uint16_t frameHDimension;
- uint16_t frameVDimension;
- uint8_t afBusPrioritySelection;
- uint8_t afBusPriority;
- uint8_t awbBusPrioritySelection;
- uint8_t awbBusPriority;
- uint8_t histBusPrioritySelection;
- uint8_t histBusPriority;
- uint32_t afBuffer[VFE_STATS_BUFFER_COUNT];
- uint32_t awbBuffer[VFE_STATS_BUFFER_COUNT];
- uint32_t histBuffer[VFE_STATS_BUFFER_COUNT];
-};
-
-struct vfe_cmd_stats_af_start {
- uint8_t enable;
- uint8_t windowMode;
- uint16_t windowHOffset;
- uint16_t windowVOffset;
- uint16_t windowWidth;
- uint16_t windowHeight;
- uint8_t gridForMultiWindows[16];
- uint8_t metricSelection;
- int16_t metricMax;
- int8_t highPassCoef[7];
- int8_t bufferHeader;
-};
-
-struct vfe_cmd_stats_af_update {
- uint8_t windowMode;
- uint16_t windowHOffset;
- uint16_t windowVOffset;
- uint16_t windowWidth;
- uint16_t windowHeight;
-};
-
-struct vfe_cmd_stats_wb_exp_start {
- uint8_t enable;
- uint8_t wbExpRegions;
- uint8_t wbExpSubRegion;
- uint8_t awbYMin;
- uint8_t awbYMax;
- int8_t awbMCFG[4];
- int16_t awbCCFG[4];
- int8_t axwHeader;
-};
-
-struct vfe_cmd_stats_wb_exp_update {
- uint8_t wbExpRegions;
- uint8_t wbExpSubRegion;
- int8_t awbYMin;
- int8_t awbYMax;
- int8_t awbMCFG[4];
- int16_t awbCCFG[4];
-};
-
-struct vfe_cmd_stats_af_ack {
- uint32_t nextAFOutputBufferAddr;
-};
-
-struct vfe_cmd_stats_wb_exp_ack {
- uint32_t nextWbExpOutputBufferAddr;
-};
-
-struct vfe_cmd_black_level_config {
- uint8_t enable;
- uint16_t evenEvenAdjustment;
- uint16_t evenOddAdjustment;
- uint16_t oddEvenAdjustment;
- uint16_t oddOddAdjustment;
-};
-
-/* 13*1 */
-#define VFE_ROLL_OFF_INIT_TABLE_SIZE 13
-/* 13*16 */
-#define VFE_ROLL_OFF_DELTA_TABLE_SIZE 208
-
-struct vfe_cmd_roll_off_config {
- uint8_t enable;
- uint16_t gridWidth;
- uint16_t gridHeight;
- uint16_t yDelta;
- uint8_t gridXIndex;
- uint8_t gridYIndex;
- uint16_t gridPixelXIndex;
- uint16_t gridPixelYIndex;
- uint16_t yDeltaAccum;
- uint16_t initTableR[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableGr[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableB[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- uint16_t initTableGb[VFE_ROLL_OFF_INIT_TABLE_SIZE];
- int16_t deltaTableR[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableGr[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableB[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
- int16_t deltaTableGb[VFE_ROLL_OFF_DELTA_TABLE_SIZE];
-};
-
-struct vfe_cmd_demux_channel_gain_config {
- uint16_t ch0EvenGain;
- uint16_t ch0OddGain;
- uint16_t ch1Gain;
- uint16_t ch2Gain;
-};
-
-struct vfe_cmds_demosaic_abf {
- uint8_t enable;
- uint8_t forceOn;
- uint8_t shift;
- uint16_t lpThreshold;
- uint16_t max;
- uint16_t min;
- uint8_t ratio;
-};
-
-struct vfe_cmds_demosaic_bpc {
- uint8_t enable;
- uint16_t fmaxThreshold;
- uint16_t fminThreshold;
- uint16_t redDiffThreshold;
- uint16_t blueDiffThreshold;
- uint16_t greenDiffThreshold;
-};
-
-struct vfe_cmd_demosaic_config {
- uint8_t enable;
- uint8_t slopeShift;
- struct vfe_cmds_demosaic_abf abfConfig;
- struct vfe_cmds_demosaic_bpc bpcConfig;
-};
-
-struct vfe_cmd_demosaic_bpc_update {
- struct vfe_cmds_demosaic_bpc bpcUpdate;
-};
-
-struct vfe_cmd_demosaic_abf_update {
- struct vfe_cmds_demosaic_abf abfUpdate;
-};
-
-struct vfe_cmd_white_balance_config {
- uint8_t enable;
- uint16_t ch2Gain;
- uint16_t ch1Gain;
- uint16_t ch0Gain;
-};
-
-enum VFE_COLOR_CORRECTION_COEF_QFACTOR {
- COEF_IS_Q7_SIGNED,
- COEF_IS_Q8_SIGNED,
- COEF_IS_Q9_SIGNED,
- COEF_IS_Q10_SIGNED
-};
-
-struct vfe_cmd_color_correction_config {
- uint8_t enable;
- enum VFE_COLOR_CORRECTION_COEF_QFACTOR coefQFactor;
- int16_t C0;
- int16_t C1;
- int16_t C2;
- int16_t C3;
- int16_t C4;
- int16_t C5;
- int16_t C6;
- int16_t C7;
- int16_t C8;
- int16_t K0;
- int16_t K1;
- int16_t K2;
-};
-
-#define VFE_LA_TABLE_LENGTH 256
-struct vfe_cmd_la_config {
- uint8_t enable;
- int16_t table[VFE_LA_TABLE_LENGTH];
-};
-
-#define VFE_GAMMA_TABLE_LENGTH 256
-enum VFE_RGB_GAMMA_TABLE_SELECT {
- RGB_GAMMA_CH0_SELECTED,
- RGB_GAMMA_CH1_SELECTED,
- RGB_GAMMA_CH2_SELECTED,
- RGB_GAMMA_CH0_CH1_SELECTED,
- RGB_GAMMA_CH0_CH2_SELECTED,
- RGB_GAMMA_CH1_CH2_SELECTED,
- RGB_GAMMA_CH0_CH1_CH2_SELECTED
-};
-
-struct vfe_cmd_rgb_gamma_config {
- uint8_t enable;
- enum VFE_RGB_GAMMA_TABLE_SELECT channelSelect;
- int16_t table[VFE_GAMMA_TABLE_LENGTH];
-};
-
-struct vfe_cmd_chroma_enhan_config {
- uint8_t enable;
- int16_t am;
- int16_t ap;
- int16_t bm;
- int16_t bp;
- int16_t cm;
- int16_t cp;
- int16_t dm;
- int16_t dp;
- int16_t kcr;
- int16_t kcb;
- int16_t RGBtoYConversionV0;
- int16_t RGBtoYConversionV1;
- int16_t RGBtoYConversionV2;
- uint8_t RGBtoYConversionOffset;
-};
-
-struct vfe_cmd_chroma_suppression_config {
- uint8_t enable;
- uint8_t m1;
- uint8_t m3;
- uint8_t n1;
- uint8_t n3;
- uint8_t nn1;
- uint8_t mm1;
-};
-
-struct vfe_cmd_asf_config {
- uint8_t enable;
- uint8_t smoothFilterEnabled;
- uint8_t sharpMode;
- uint8_t smoothCoefCenter;
- uint8_t smoothCoefSurr;
- uint8_t normalizeFactor;
- uint8_t sharpK1;
- uint8_t sharpK2;
- uint8_t sharpThreshE1;
- int8_t sharpThreshE2;
- int8_t sharpThreshE3;
- int8_t sharpThreshE4;
- int8_t sharpThreshE5;
- int8_t filter1Coefficients[9];
- int8_t filter2Coefficients[9];
- uint8_t cropEnable;
- uint16_t cropFirstPixel;
- uint16_t cropLastPixel;
- uint16_t cropFirstLine;
- uint16_t cropLastLine;
-};
-
-struct vfe_cmd_asf_update {
- uint8_t enable;
- uint8_t smoothFilterEnabled;
- uint8_t sharpMode;
- uint8_t smoothCoefCenter;
- uint8_t smoothCoefSurr;
- uint8_t normalizeFactor;
- uint8_t sharpK1;
- uint8_t sharpK2;
- uint8_t sharpThreshE1;
- int8_t sharpThreshE2;
- int8_t sharpThreshE3;
- int8_t sharpThreshE4;
- int8_t sharpThreshE5;
- int8_t filter1Coefficients[9];
- int8_t filter2Coefficients[9];
- uint8_t cropEnable;
-};
-
-enum VFE_TEST_GEN_SYNC_EDGE {
- VFE_TEST_GEN_SYNC_EDGE_ActiveHigh,
- VFE_TEST_GEN_SYNC_EDGE_ActiveLow
-};
-
-struct vfe_cmd_test_gen_start {
- uint8_t pixelDataSelect;
- uint8_t systematicDataSelect;
- enum VFE_TEST_GEN_SYNC_EDGE hsyncEdge;
- enum VFE_TEST_GEN_SYNC_EDGE vsyncEdge;
- uint16_t numFrame;
- enum VFE_RAW_PIXEL_DATA_SIZE pixelDataSize;
- uint16_t imageWidth;
- uint16_t imageHeight;
- uint32_t startOfFrameOffset;
- uint32_t endOfFrameNOffset;
- uint16_t startOfLineOffset;
- uint16_t endOfLineNOffset;
- uint16_t hbi;
- uint8_t vblEnable;
- uint16_t vbl;
- uint8_t startOfFrameDummyLine;
- uint8_t endOfFrameDummyLine;
- uint8_t unicolorBarEnable;
- uint8_t colorBarsSplitEnable;
- uint8_t unicolorBarSelect;
- enum VFE_START_PIXEL_PATTERN colorBarsPixelPattern;
- uint8_t colorBarsRotatePeriod;
- uint16_t testGenRandomSeed;
-};
-
-struct vfe_cmd_bus_pm_start {
- uint8_t output2YWrPmEnable;
- uint8_t output2CbcrWrPmEnable;
- uint8_t output1YWrPmEnable;
- uint8_t output1CbcrWrPmEnable;
-};
-
-struct vfe_cmd_camif_frame_update {
- struct vfe_cmds_camif_frame camifFrame;
-};
-
-struct vfe_cmd_sync_timer_setting {
- uint8_t whichSyncTimer;
- uint8_t operation;
- uint8_t polarity;
- uint16_t repeatCount;
- uint16_t hsyncCount;
- uint32_t pclkCount;
- uint32_t outputDuration;
-};
-
-struct vfe_cmd_async_timer_setting {
- uint8_t whichAsyncTimer;
- uint8_t operation;
- uint8_t polarity;
- uint16_t repeatCount;
- uint16_t inactiveCount;
- uint32_t activeCount;
-};
-
-struct vfe_frame_skip_counts {
- uint32_t totalFrameCount;
- uint32_t output1Count;
- uint32_t output2Count;
-};
-
-enum VFE_AXI_RD_UNPACK_HBI_SEL {
- VFE_AXI_RD_HBI_32_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_64_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_128_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_256_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_512_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_1024_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_2048_CLOCK_CYCLES,
- VFE_AXI_RD_HBI_4096_CLOCK_CYCLES
-};
-
-struct vfe_cmd_axi_input_config {
- uint32_t fragAddr[4];
- uint8_t totalFragmentCount;
- uint16_t ySize;
- uint16_t xOffset;
- uint16_t xSize;
- uint16_t rowIncrement;
- uint16_t numOfRows;
- enum VFE_AXI_BURST_LENGTH burstLength;
- uint8_t unpackPhase;
- enum VFE_AXI_RD_UNPACK_HBI_SEL unpackHbi;
- enum VFE_RAW_PIXEL_DATA_SIZE pixelSize;
- uint8_t padRepeatCountLeft;
- uint8_t padRepeatCountRight;
- uint8_t padRepeatCountTop;
- uint8_t padRepeatCountBottom;
- uint8_t padLeftComponentSelectCycle0;
- uint8_t padLeftComponentSelectCycle1;
- uint8_t padLeftComponentSelectCycle2;
- uint8_t padLeftComponentSelectCycle3;
- uint8_t padLeftStopCycle0;
- uint8_t padLeftStopCycle1;
- uint8_t padLeftStopCycle2;
- uint8_t padLeftStopCycle3;
- uint8_t padRightComponentSelectCycle0;
- uint8_t padRightComponentSelectCycle1;
- uint8_t padRightComponentSelectCycle2;
- uint8_t padRightComponentSelectCycle3;
- uint8_t padRightStopCycle0;
- uint8_t padRightStopCycle1;
- uint8_t padRightStopCycle2;
- uint8_t padRightStopCycle3;
- uint8_t padTopLineCount;
- uint8_t padBottomLineCount;
-};
-
-struct vfe_interrupt_status {
- uint8_t camifErrorIrq;
- uint8_t camifSofIrq;
- uint8_t camifEolIrq;
- uint8_t camifEofIrq;
- uint8_t camifEpoch1Irq;
- uint8_t camifEpoch2Irq;
- uint8_t camifOverflowIrq;
- uint8_t ceIrq;
- uint8_t regUpdateIrq;
- uint8_t resetAckIrq;
- uint8_t encYPingpongIrq;
- uint8_t encCbcrPingpongIrq;
- uint8_t viewYPingpongIrq;
- uint8_t viewCbcrPingpongIrq;
- uint8_t rdPingpongIrq;
- uint8_t afPingpongIrq;
- uint8_t awbPingpongIrq;
- uint8_t histPingpongIrq;
- uint8_t encIrq;
- uint8_t viewIrq;
- uint8_t busOverflowIrq;
- uint8_t afOverflowIrq;
- uint8_t awbOverflowIrq;
- uint8_t syncTimer0Irq;
- uint8_t syncTimer1Irq;
- uint8_t syncTimer2Irq;
- uint8_t asyncTimer0Irq;
- uint8_t asyncTimer1Irq;
- uint8_t asyncTimer2Irq;
- uint8_t asyncTimer3Irq;
- uint8_t axiErrorIrq;
- uint8_t violationIrq;
- uint8_t anyErrorIrqs;
- uint8_t anyOutput1PathIrqs;
- uint8_t anyOutput2PathIrqs;
- uint8_t anyOutputPathIrqs;
- uint8_t anyAsyncTimerIrqs;
- uint8_t anySyncTimerIrqs;
- uint8_t anyIrqForActiveStatesOnly;
-};
-
-enum VFE_MESSAGE_ID {
- VFE_MSG_ID_RESET_ACK,
- VFE_MSG_ID_START_ACK,
- VFE_MSG_ID_STOP_ACK,
- VFE_MSG_ID_UPDATE_ACK,
- VFE_MSG_ID_OUTPUT1,
- VFE_MSG_ID_OUTPUT2,
- VFE_MSG_ID_SNAPSHOT_DONE,
- VFE_MSG_ID_STATS_AUTOFOCUS,
- VFE_MSG_ID_STATS_WB_EXP,
- VFE_MSG_ID_EPOCH1,
- VFE_MSG_ID_EPOCH2,
- VFE_MSG_ID_SYNC_TIMER0_DONE,
- VFE_MSG_ID_SYNC_TIMER1_DONE,
- VFE_MSG_ID_SYNC_TIMER2_DONE,
- VFE_MSG_ID_ASYNC_TIMER0_DONE,
- VFE_MSG_ID_ASYNC_TIMER1_DONE,
- VFE_MSG_ID_ASYNC_TIMER2_DONE,
- VFE_MSG_ID_ASYNC_TIMER3_DONE,
- VFE_MSG_ID_AF_OVERFLOW,
- VFE_MSG_ID_AWB_OVERFLOW,
- VFE_MSG_ID_AXI_ERROR,
- VFE_MSG_ID_CAMIF_OVERFLOW,
- VFE_MSG_ID_VIOLATION,
- VFE_MSG_ID_CAMIF_ERROR,
- VFE_MSG_ID_BUS_OVERFLOW,
-};
-
-struct vfe_msg_stats_autofocus {
- uint32_t afBuffer;
- uint32_t frameCounter;
-};
-
-struct vfe_msg_stats_wb_exp {
- uint32_t awbBuffer;
- uint32_t frameCounter;
-};
-
-struct vfe_frame_bpc_info {
- uint32_t greenDefectPixelCount;
- uint32_t redBlueDefectPixelCount;
-};
-
-struct vfe_frame_asf_info {
- uint32_t asfMaxEdge;
- uint32_t asfHbiCount;
-};
-
-struct vfe_msg_camif_status {
- uint8_t camifState;
- uint32_t pixelCount;
- uint32_t lineCount;
-};
-
-struct vfe_bus_pm_per_path {
- uint32_t yWrPmStats0;
- uint32_t yWrPmStats1;
- uint32_t cbcrWrPmStats0;
- uint32_t cbcrWrPmStats1;
-};
-
-struct vfe_bus_performance_monitor {
- struct vfe_bus_pm_per_path encPathPmInfo;
- struct vfe_bus_pm_per_path viewPathPmInfo;
-};
-
-struct vfe_irq_thread_msg {
- uint32_t vfeIrqStatus;
- uint32_t camifStatus;
- uint32_t demosaicStatus;
- uint32_t asfMaxEdge;
- struct vfe_bus_performance_monitor pmInfo;
-};
-
-struct vfe_msg_output {
- uint32_t yBuffer;
- uint32_t cbcrBuffer;
- struct vfe_frame_bpc_info bpcInfo;
- struct vfe_frame_asf_info asfInfo;
- uint32_t frameCounter;
- struct vfe_bus_pm_per_path pmData;
-};
-
-struct vfe_message {
- enum VFE_MESSAGE_ID _d;
- union {
- struct vfe_msg_output msgOutput1;
- struct vfe_msg_output msgOutput2;
- struct vfe_msg_stats_autofocus msgStatsAf;
- struct vfe_msg_stats_wb_exp msgStatsWbExp;
- struct vfe_msg_camif_status msgCamifError;
- struct vfe_bus_performance_monitor msgBusOverflow;
- } _u;
-};
-
-/* New one for 8k */
-struct msm_vfe_command_8k {
- int32_t id;
- uint16_t length;
- void *value;
-};
-
-struct vfe_frame_extra {
- struct vfe_frame_bpc_info bpcInfo;
- struct vfe_frame_asf_info asfInfo;
- uint32_t frameCounter;
- struct vfe_bus_pm_per_path pmData;
-};
-#endif /* __MSM_VFE8X_H__ */
+++ /dev/null
-/*
-* Copyright (C) 2008-2009 QUALCOMM Incorporated.
-*/
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/list.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include "msm_vfe8x_proc.h"
-#include <media/msm_camera.h>
-
-struct msm_vfe8x_ctrl {
- /* bit 1:0 ENC_IRQ_MASK = 0x11:
- * generate IRQ when both y and cbcr frame is ready. */
-
- /* bit 1:0 VIEW_IRQ_MASK= 0x11:
- * generate IRQ when both y and cbcr frame is ready. */
- struct vfe_irq_composite_mask_config vfeIrqCompositeMaskLocal;
- struct vfe_module_enable vfeModuleEnableLocal;
- struct vfe_camif_cfg_data vfeCamifConfigLocal;
- struct vfe_interrupt_mask vfeImaskLocal;
- struct vfe_stats_cmd_data vfeStatsCmdLocal;
- struct vfe_bus_cfg_data vfeBusConfigLocal;
- struct vfe_cmd_bus_pm_start vfeBusPmConfigLocal;
- struct vfe_bus_cmd_data vfeBusCmdLocal;
- enum vfe_interrupt_name vfeInterruptNameLocal;
- uint32_t vfeLaBankSel;
- struct vfe_gamma_lut_sel vfeGammaLutSel;
-
- boolean vfeStartAckPendingFlag;
- boolean vfeStopAckPending;
- boolean vfeResetAckPending;
- boolean vfeUpdateAckPending;
-
- enum VFE_AXI_OUTPUT_MODE axiOutputMode;
- enum VFE_START_OPERATION_MODE vfeOperationMode;
-
- uint32_t vfeSnapShotCount;
- uint32_t vfeRequestedSnapShotCount;
- boolean vfeStatsPingPongReloadFlag;
- uint32_t vfeFrameId;
-
- struct vfe_cmd_frame_skip_config vfeFrameSkip;
- uint32_t vfeFrameSkipPattern;
- uint8_t vfeFrameSkipCount;
- uint8_t vfeFrameSkipPeriod;
-
- boolean vfeTestGenStartFlag;
- uint32_t vfeImaskPacked;
- uint32_t vfeImaskCompositePacked;
- enum VFE_RAW_PIXEL_DATA_SIZE axiInputDataSize;
- struct vfe_irq_thread_msg vfeIrqThreadMsgLocal;
-
- struct vfe_output_path_combo viewPath;
- struct vfe_output_path_combo encPath;
- struct vfe_frame_skip_counts vfeDroppedFrameCounts;
- struct vfe_stats_control afStatsControl;
- struct vfe_stats_control awbStatsControl;
-
- enum VFE_STATE vstate;
-
- spinlock_t ack_lock;
- spinlock_t state_lock;
- spinlock_t io_lock;
-
- struct msm_vfe_callback *resp;
- uint32_t extlen;
- void *extdata;
-
- spinlock_t tasklet_lock;
- struct list_head tasklet_q;
-
- int vfeirq;
- void __iomem *vfebase;
-
- void *syncdata;
-};
-static struct msm_vfe8x_ctrl *ctrl;
-static irqreturn_t vfe_parse_irq(int irq_num, void *data);
-
-struct isr_queue_cmd {
- struct list_head list;
- struct vfe_interrupt_status vfeInterruptStatus;
- struct vfe_frame_asf_info vfeAsfFrameInfo;
- struct vfe_frame_bpc_info vfeBpcFrameInfo;
- struct vfe_msg_camif_status vfeCamifStatusLocal;
- struct vfe_bus_performance_monitor vfePmData;
-};
-
-static void vfe_prog_hw(uint8_t *hwreg,
- uint32_t *inptr, uint32_t regcnt)
-{
- /* unsigned long flags; */
- uint32_t i;
- uint32_t *p;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
-
- p = (uint32_t *)(hwreg);
- for (i = 0; i < (regcnt >> 2); i++)
- writel(*inptr++, p++);
- /* *p++ = *inptr++; */
-
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-}
-
-static void vfe_read_reg_values(uint8_t *hwreg,
- uint32_t *dest, uint32_t count)
-{
- /* unsigned long flags; */
- uint32_t *temp;
- uint32_t i;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
-
- temp = (uint32_t *)(hwreg);
- for (i = 0; i < count; i++)
- *dest++ = *temp++;
-
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-}
-
-static struct vfe_irqenable vfe_read_irq_mask(void)
-{
- /* unsigned long flags; */
- uint32_t *temp;
- struct vfe_irqenable rc;
-
- memset(&rc, 0, sizeof(rc));
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->io_lock, flags); */
- temp = (uint32_t *)(ctrl->vfebase + VFE_IRQ_MASK);
-
- rc = *((struct vfe_irqenable *)temp);
- /* spin_unlock_irqrestore(&ctrl->io_lock, flags); */
-
- return rc;
-}
-
-static void
-vfe_set_bus_pipo_addr(struct vfe_output_path_combo *vpath,
- struct vfe_output_path_combo *epath)
-{
- vpath->yPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_Y_WR_PING_ADDR);
- vpath->yPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_Y_WR_PONG_ADDR);
- vpath->cbcrPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_CBCR_WR_PING_ADDR);
- vpath->cbcrPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_VIEW_CBCR_WR_PONG_ADDR);
-
- epath->yPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_Y_WR_PING_ADDR);
- epath->yPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_Y_WR_PONG_ADDR);
- epath->cbcrPath.hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PING_ADDR);
- epath->cbcrPath.hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PONG_ADDR);
-}
-
-static void vfe_axi_output(struct vfe_cmd_axi_output_config *in,
- struct vfe_output_path_combo *out1,
- struct vfe_output_path_combo *out2, uint16_t out)
-{
- struct vfe_axi_out_cfg cmd;
-
- uint16_t temp;
- uint32_t burstLength;
-
- /* force it to burst length 4, hardware does not support it. */
- burstLength = 1;
-
- /* AXI Output 2 Y Configuration*/
- /* VFE_BUS_ENC_Y_WR_PING_ADDR */
- cmd.out2YPingAddr = out2->yPath.addressBuffer[0];
-
- /* VFE_BUS_ENC_Y_WR_PONG_ADDR */
- cmd.out2YPongAddr = out2->yPath.addressBuffer[1];
-
- /* VFE_BUS_ENC_Y_WR_IMAGE_SIZE */
- cmd.out2YImageHeight = in->output2.outputY.imageHeight;
- /* convert the image width and row increment to be in
- * unit of 64bit (8 bytes) */
- temp = (in->output2.outputY.imageWidth + (out - 1)) /
- out;
- cmd.out2YImageWidthin64bit = temp;
-
- /* VFE_BUS_ENC_Y_WR_BUFFER_CFG */
- cmd.out2YBurstLength = burstLength;
- cmd.out2YNumRows = in->output2.outputY.outRowCount;
- temp = (in->output2.outputY.outRowIncrement + (out - 1)) /
- out;
- cmd.out2YRowIncrementIn64bit = temp;
-
- /* AXI Output 2 Cbcr Configuration*/
- /* VFE_BUS_ENC_Cbcr_WR_PING_ADDR */
- cmd.out2CbcrPingAddr = out2->cbcrPath.addressBuffer[0];
-
- /* VFE_BUS_ENC_Cbcr_WR_PONG_ADDR */
- cmd.out2CbcrPongAddr = out2->cbcrPath.addressBuffer[1];
-
- /* VFE_BUS_ENC_Cbcr_WR_IMAGE_SIZE */
- cmd.out2CbcrImageHeight = in->output2.outputCbcr.imageHeight;
- temp = (in->output2.outputCbcr.imageWidth + (out - 1)) /
- out;
- cmd.out2CbcrImageWidthIn64bit = temp;
-
- /* VFE_BUS_ENC_Cbcr_WR_BUFFER_CFG */
- cmd.out2CbcrBurstLength = burstLength;
- cmd.out2CbcrNumRows = in->output2.outputCbcr.outRowCount;
- temp = (in->output2.outputCbcr.outRowIncrement + (out - 1)) /
- out;
- cmd.out2CbcrRowIncrementIn64bit = temp;
-
- /* AXI Output 1 Y Configuration */
- /* VFE_BUS_VIEW_Y_WR_PING_ADDR */
- cmd.out1YPingAddr = out1->yPath.addressBuffer[0];
-
- /* VFE_BUS_VIEW_Y_WR_PONG_ADDR */
- cmd.out1YPongAddr = out1->yPath.addressBuffer[1];
-
- /* VFE_BUS_VIEW_Y_WR_IMAGE_SIZE */
- cmd.out1YImageHeight = in->output1.outputY.imageHeight;
- temp = (in->output1.outputY.imageWidth + (out - 1)) /
- out;
- cmd.out1YImageWidthin64bit = temp;
-
- /* VFE_BUS_VIEW_Y_WR_BUFFER_CFG */
- cmd.out1YBurstLength = burstLength;
- cmd.out1YNumRows = in->output1.outputY.outRowCount;
-
- temp =
- (in->output1.outputY.outRowIncrement +
- (out - 1)) / out;
- cmd.out1YRowIncrementIn64bit = temp;
-
- /* AXI Output 1 Cbcr Configuration*/
- cmd.out1CbcrPingAddr = out1->cbcrPath.addressBuffer[0];
-
- /* VFE_BUS_VIEW_Cbcr_WR_PONG_ADDR */
- cmd.out1CbcrPongAddr =
- out1->cbcrPath.addressBuffer[1];
-
- /* VFE_BUS_VIEW_Cbcr_WR_IMAGE_SIZE */
- cmd.out1CbcrImageHeight = in->output1.outputCbcr.imageHeight;
- temp = (in->output1.outputCbcr.imageWidth +
- (out - 1)) / out;
- cmd.out1CbcrImageWidthIn64bit = temp;
-
- cmd.out1CbcrBurstLength = burstLength;
- cmd.out1CbcrNumRows = in->output1.outputCbcr.outRowCount;
- temp =
- (in->output1.outputCbcr.outRowIncrement +
- (out - 1)) / out;
-
- cmd.out1CbcrRowIncrementIn64bit = temp;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_ENC_Y_WR_PING_ADDR,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_reg_bus_cfg(struct vfe_bus_cfg_data *in)
-{
- struct vfe_axi_bus_cfg cmd;
-
- cmd.stripeRdPathEn = in->stripeRdPathEn;
- cmd.encYWrPathEn = in->encYWrPathEn;
- cmd.encCbcrWrPathEn = in->encCbcrWrPathEn;
- cmd.viewYWrPathEn = in->viewYWrPathEn;
- cmd.viewCbcrWrPathEn = in->viewCbcrWrPathEn;
- cmd.rawPixelDataSize = (uint32_t)in->rawPixelDataSize;
- cmd.rawWritePathSelect = (uint32_t)in->rawWritePathSelect;
-
- /* program vfe_bus_cfg */
- writel(*((uint32_t *)&cmd), ctrl->vfebase + VFE_BUS_CFG);
-}
-
-static void vfe_reg_camif_config(struct vfe_camif_cfg_data *in)
-{
- struct VFE_CAMIFConfigType cfg;
-
- memset(&cfg, 0, sizeof(cfg));
-
- cfg.VSyncEdge =
- in->camifCfgFromCmd.vSyncEdge;
-
- cfg.HSyncEdge =
- in->camifCfgFromCmd.hSyncEdge;
-
- cfg.syncMode =
- in->camifCfgFromCmd.syncMode;
-
- cfg.vfeSubsampleEnable =
- in->camifCfgFromCmd.vfeSubSampleEnable;
-
- cfg.busSubsampleEnable =
- in->camifCfgFromCmd.busSubSampleEnable;
-
- cfg.camif2vfeEnable =
- in->camif2OutputEnable;
-
- cfg.camif2busEnable =
- in->camif2BusEnable;
-
- cfg.irqSubsampleEnable =
- in->camifCfgFromCmd.irqSubSampleEnable;
-
- cfg.binningEnable =
- in->camifCfgFromCmd.binningEnable;
-
- cfg.misrEnable =
- in->camifCfgFromCmd.misrEnable;
-
- /* program camif_config */
- writel(*((uint32_t *)&cfg), ctrl->vfebase + CAMIF_CONFIG);
-}
-
-static void vfe_reg_bus_cmd(struct vfe_bus_cmd_data *in)
-{
- struct vfe_buscmd cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.stripeReload = in->stripeReload;
- cmd.busPingpongReload = in->busPingpongReload;
- cmd.statsPingpongReload = in->statsPingpongReload;
-
- writel(*((uint32_t *)&cmd), ctrl->vfebase + VFE_BUS_CMD);
-
- CDBG("bus command = 0x%x\n", (*((uint32_t *)&cmd)));
-
- /* this is needed, as the control bits are pulse based.
- * Don't want to reload bus pingpong again. */
- in->busPingpongReload = 0;
- in->statsPingpongReload = 0;
- in->stripeReload = 0;
-}
-
-static void vfe_reg_module_cfg(struct vfe_module_enable *in)
-{
- struct vfe_mod_enable ena;
-
- memset(&ena, 0, sizeof(ena));
-
- ena.blackLevelCorrectionEnable = in->blackLevelCorrectionEnable;
- ena.lensRollOffEnable = in->lensRollOffEnable;
- ena.demuxEnable = in->demuxEnable;
- ena.chromaUpsampleEnable = in->chromaUpsampleEnable;
- ena.demosaicEnable = in->demosaicEnable;
- ena.statsEnable = in->statsEnable;
- ena.cropEnable = in->cropEnable;
- ena.mainScalerEnable = in->mainScalerEnable;
- ena.whiteBalanceEnable = in->whiteBalanceEnable;
- ena.colorCorrectionEnable = in->colorCorrectionEnable;
- ena.yHistEnable = in->yHistEnable;
- ena.skinToneEnable = in->skinToneEnable;
- ena.lumaAdaptationEnable = in->lumaAdaptationEnable;
- ena.rgbLUTEnable = in->rgbLUTEnable;
- ena.chromaEnhanEnable = in->chromaEnhanEnable;
- ena.asfEnable = in->asfEnable;
- ena.chromaSuppressionEnable = in->chromaSuppressionEnable;
- ena.chromaSubsampleEnable = in->chromaSubsampleEnable;
- ena.scaler2YEnable = in->scaler2YEnable;
- ena.scaler2CbcrEnable = in->scaler2CbcrEnable;
-
- writel(*((uint32_t *)&ena), ctrl->vfebase + VFE_MODULE_CFG);
-}
-
-static void vfe_program_dmi_cfg(enum VFE_DMI_RAM_SEL bankSel)
-{
- /* set bit 8 for auto increment. */
- uint32_t value = (uint32_t) ctrl->vfebase + VFE_DMI_CFG_DEFAULT;
-
- value += (uint32_t)bankSel;
- /* CDBG("dmi cfg input bank is 0x%x\n", bankSel); */
-
- writel(value, ctrl->vfebase + VFE_DMI_CFG);
- writel(0, ctrl->vfebase + VFE_DMI_ADDR);
-}
-
-static void vfe_write_lens_roll_off_table(
- struct vfe_cmd_roll_off_config *in)
-{
- uint16_t i;
- uint32_t data;
-
- uint16_t *initGr = in->initTableGr;
- uint16_t *initGb = in->initTableGb;
- uint16_t *initB = in->initTableB;
- uint16_t *initR = in->initTableR;
-
- int16_t *pDeltaGr = in->deltaTableGr;
- int16_t *pDeltaGb = in->deltaTableGb;
- int16_t *pDeltaB = in->deltaTableB;
- int16_t *pDeltaR = in->deltaTableR;
-
- vfe_program_dmi_cfg(ROLLOFF_RAM);
-
- /* first pack and write init table */
- for (i = 0; i < VFE_ROLL_OFF_INIT_TABLE_SIZE; i++) {
- data = (((uint32_t)(*initR)) & 0x0000FFFF) |
- (((uint32_t)(*initGr)) << 16);
- initR++;
- initGr++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
-
- data = (((uint32_t)(*initB)) & 0x0000FFFF) |
- (((uint32_t)(*initGr))<<16);
- initB++;
- initGb++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
- }
-
- /* there are gaps between the init table and delta table,
- * set the offset for delta table. */
- writel(LENS_ROLL_OFF_DELTA_TABLE_OFFSET,
- ctrl->vfebase + VFE_DMI_ADDR);
-
- /* pack and write delta table */
- for (i = 0; i < VFE_ROLL_OFF_DELTA_TABLE_SIZE; i++) {
- data = (((int32_t)(*pDeltaR)) & 0x0000FFFF) |
- (((int32_t)(*pDeltaGr))<<16);
- pDeltaR++;
- pDeltaGr++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
-
- data = (((int32_t)(*pDeltaB)) & 0x0000FFFF) |
- (((int32_t)(*pDeltaGb))<<16);
- pDeltaB++;
- pDeltaGb++;
-
- writel(data, ctrl->vfebase + VFE_DMI_DATA_LO);
- }
-
- /* After DMI transfer, to make it safe, need to set the
- * DMI_CFG to unselect any SRAM
- */
- /* unselect the SRAM Bank. */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-}
-
-static void vfe_set_default_reg_values(void)
-{
- writel(0x800080, ctrl->vfebase + VFE_DEMUX_GAIN_0);
- writel(0x800080, ctrl->vfebase + VFE_DEMUX_GAIN_1);
- writel(0xFFFFF, ctrl->vfebase + VFE_CGC_OVERRIDE);
-
- /* default frame drop period and pattern */
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_CFG);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_ENC_CBCR_PATTERN);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_CFG);
- writel(0x1f, ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_CFG);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN);
- writel(0xFFFFFFFF, ctrl->vfebase + VFE_FRAMEDROP_VIEW_CBCR_PATTERN);
- writel(0, ctrl->vfebase + VFE_CLAMP_MIN_CFG);
- writel(0xFFFFFF, ctrl->vfebase + VFE_CLAMP_MAX_CFG);
-}
-
-static void vfe_config_demux(uint32_t period, uint32_t even, uint32_t odd)
-{
- writel(period, ctrl->vfebase + VFE_DEMUX_CFG);
- writel(even, ctrl->vfebase + VFE_DEMUX_EVEN_CFG);
- writel(odd, ctrl->vfebase + VFE_DEMUX_ODD_CFG);
-}
-
-static void vfe_pm_stop(void)
-{
- writel(VFE_PERFORMANCE_MONITOR_STOP, ctrl->vfebase + VFE_BUS_PM_CMD);
-}
-
-static void vfe_program_bus_rd_irq_en(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_BUS_PINGPONG_IRQ_EN);
-}
-
-static void vfe_camif_go(void)
-{
- writel(CAMIF_COMMAND_START, ctrl->vfebase + CAMIF_COMMAND);
-}
-
-static void vfe_camif_stop_immediately(void)
-{
- writel(CAMIF_COMMAND_STOP_IMMEDIATELY, ctrl->vfebase + CAMIF_COMMAND);
- writel(0, ctrl->vfebase + VFE_CGC_OVERRIDE);
-}
-
-static void vfe_program_reg_update_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_REG_UPDATE_CMD);
-}
-
-static void vfe_program_bus_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_BUS_CMD);
-}
-
-static void vfe_program_global_reset_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_GLOBAL_RESET_CMD);
-}
-
-static void vfe_program_axi_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_AXI_CMD);
-}
-
-static void vfe_program_irq_composite_mask(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_IRQ_COMPOSITE_MASK);
-}
-
-static inline void vfe_program_irq_mask(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_IRQ_MASK);
-}
-
-static void vfe_program_chroma_upsample_cfg(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_CHROMA_UPSAMPLE_CFG);
-}
-
-static uint32_t vfe_read_axi_status(void)
-{
- return readl(ctrl->vfebase + VFE_AXI_STATUS);
-}
-
-static uint32_t vfe_read_pm_status_in_raw_capture(void)
-{
- return readl(ctrl->vfebase + VFE_BUS_ENC_CBCR_WR_PM_STATS_1);
-}
-
-static void
-vfe_set_stats_pingpong_address(struct vfe_stats_control *afControl,
- struct vfe_stats_control *awbControl)
-{
- afControl->hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- afControl->hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-
- awbControl->hwRegPingAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- awbControl->hwRegPongAddress = (uint8_t *)
- (ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static uint32_t vfe_read_camif_status(void)
-{
- return readl(ctrl->vfebase + CAMIF_STATUS);
-}
-
-static void vfe_program_lut_bank_sel(struct vfe_gamma_lut_sel *in)
-{
- struct VFE_GammaLutSelect_ConfigCmdType cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0BankSelect = in->ch0BankSelect;
- cmd.ch1BankSelect = in->ch1BankSelect;
- cmd.ch2BankSelect = in->ch2BankSelect;
- CDBG("VFE gamma lut bank selection is 0x%x\n", *((uint32_t *)&cmd));
- vfe_prog_hw(ctrl->vfebase + VFE_LUT_BANK_SEL,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_program_stats_cmd(struct vfe_stats_cmd_data *in)
-{
- struct VFE_StatsCmdType stats;
- memset(&stats, 0, sizeof(stats));
-
- stats.autoFocusEnable = in->autoFocusEnable;
- stats.axwEnable = in->axwEnable;
- stats.histEnable = in->histEnable;
- stats.clearHistEnable = in->clearHistEnable;
- stats.histAutoClearEnable = in->histAutoClearEnable;
- stats.colorConversionEnable = in->colorConversionEnable;
-
- writel(*((uint32_t *)&stats), ctrl->vfebase + VFE_STATS_CMD);
-}
-
-static void vfe_pm_start(struct vfe_cmd_bus_pm_start *in)
-{
- struct VFE_Bus_Pm_ConfigCmdType cmd;
- memset(&cmd, 0, sizeof(struct VFE_Bus_Pm_ConfigCmdType));
-
- cmd.output2YWrPmEnable = in->output2YWrPmEnable;
- cmd.output2CbcrWrPmEnable = in->output2CbcrWrPmEnable;
- cmd.output1YWrPmEnable = in->output1YWrPmEnable;
- cmd.output1CbcrWrPmEnable = in->output1CbcrWrPmEnable;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_PM_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-static void vfe_8k_pm_start(struct vfe_cmd_bus_pm_start *in)
-{
- in->output1CbcrWrPmEnable = ctrl->vfeBusConfigLocal.viewCbcrWrPathEn;
- in->output1YWrPmEnable = ctrl->vfeBusConfigLocal.viewYWrPathEn;
- in->output2CbcrWrPmEnable = ctrl->vfeBusConfigLocal.encCbcrWrPathEn;
- in->output2YWrPmEnable = ctrl->vfeBusConfigLocal.encYWrPathEn;
-
- if (in->output1CbcrWrPmEnable || in->output1YWrPmEnable)
- ctrl->viewPath.pmEnabled = TRUE;
-
- if (in->output2CbcrWrPmEnable || in->output2YWrPmEnable)
- ctrl->encPath.pmEnabled = TRUE;
-
- vfe_pm_start(in);
-
- writel(VFE_PERFORMANCE_MONITOR_GO, ctrl->vfebase + VFE_BUS_PM_CMD);
-}
-
-static uint32_t vfe_irq_pack(struct vfe_interrupt_mask data)
-{
- struct vfe_irqenable packedData;
-
- memset(&packedData, 0, sizeof(packedData));
-
- packedData.camifErrorIrq = data.camifErrorIrq;
- packedData.camifSofIrq = data.camifSofIrq;
- packedData.camifEolIrq = data.camifEolIrq;
- packedData.camifEofIrq = data.camifEofIrq;
- packedData.camifEpoch1Irq = data.camifEpoch1Irq;
- packedData.camifEpoch2Irq = data.camifEpoch2Irq;
- packedData.camifOverflowIrq = data.camifOverflowIrq;
- packedData.ceIrq = data.ceIrq;
- packedData.regUpdateIrq = data.regUpdateIrq;
- packedData.resetAckIrq = data.resetAckIrq;
- packedData.encYPingpongIrq = data.encYPingpongIrq;
- packedData.encCbcrPingpongIrq = data.encCbcrPingpongIrq;
- packedData.viewYPingpongIrq = data.viewYPingpongIrq;
- packedData.viewCbcrPingpongIrq = data.viewCbcrPingpongIrq;
- packedData.rdPingpongIrq = data.rdPingpongIrq;
- packedData.afPingpongIrq = data.afPingpongIrq;
- packedData.awbPingpongIrq = data.awbPingpongIrq;
- packedData.histPingpongIrq = data.histPingpongIrq;
- packedData.encIrq = data.encIrq;
- packedData.viewIrq = data.viewIrq;
- packedData.busOverflowIrq = data.busOverflowIrq;
- packedData.afOverflowIrq = data.afOverflowIrq;
- packedData.awbOverflowIrq = data.awbOverflowIrq;
- packedData.syncTimer0Irq = data.syncTimer0Irq;
- packedData.syncTimer1Irq = data.syncTimer1Irq;
- packedData.syncTimer2Irq = data.syncTimer2Irq;
- packedData.asyncTimer0Irq = data.asyncTimer0Irq;
- packedData.asyncTimer1Irq = data.asyncTimer1Irq;
- packedData.asyncTimer2Irq = data.asyncTimer2Irq;
- packedData.asyncTimer3Irq = data.asyncTimer3Irq;
- packedData.axiErrorIrq = data.axiErrorIrq;
- packedData.violationIrq = data.violationIrq;
-
- return *((uint32_t *)&packedData);
-}
-
-static uint32_t
-vfe_irq_composite_pack(struct vfe_irq_composite_mask_config data)
-{
- struct VFE_Irq_Composite_MaskType packedData;
-
- memset(&packedData, 0, sizeof(packedData));
-
- packedData.encIrqComMaskBits = data.encIrqComMask;
- packedData.viewIrqComMaskBits = data.viewIrqComMask;
- packedData.ceDoneSelBits = data.ceDoneSel;
-
- return *((uint32_t *)&packedData);
-}
-
-static void vfe_addr_convert(struct msm_vfe_phy_info *pinfo,
- enum vfe_resp_msg type, void *data, void **ext, int32_t *elen)
-{
- switch (type) {
- case VFE_MSG_OUTPUT1: {
- pinfo->y_phy =
- ((struct vfe_message *)data)->_u.msgOutput1.yBuffer;
- pinfo->cbcr_phy =
- ((struct vfe_message *)data)->_u.msgOutput1.cbcrBuffer;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->bpcInfo =
- ((struct vfe_message *)data)->_u.msgOutput1.bpcInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->asfInfo =
- ((struct vfe_message *)data)->_u.msgOutput1.asfInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->frameCounter =
- ((struct vfe_message *)data)->_u.msgOutput1.frameCounter;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->pmData =
- ((struct vfe_message *)data)->_u.msgOutput1.pmData;
-
- *ext = ctrl->extdata;
- *elen = ctrl->extlen;
- }
- break;
-
- case VFE_MSG_OUTPUT2: {
- pinfo->y_phy =
- ((struct vfe_message *)data)->_u.msgOutput2.yBuffer;
- pinfo->cbcr_phy =
- ((struct vfe_message *)data)->_u.msgOutput2.cbcrBuffer;
-
- CDBG("vfe_addr_convert, pinfo->y_phy = 0x%x\n", pinfo->y_phy);
- CDBG("vfe_addr_convert, pinfo->cbcr_phy = 0x%x\n",
- pinfo->cbcr_phy);
-
- ((struct vfe_frame_extra *)ctrl->extdata)->bpcInfo =
- ((struct vfe_message *)data)->_u.msgOutput2.bpcInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->asfInfo =
- ((struct vfe_message *)data)->_u.msgOutput2.asfInfo;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->frameCounter =
- ((struct vfe_message *)data)->_u.msgOutput2.frameCounter;
-
- ((struct vfe_frame_extra *)ctrl->extdata)->pmData =
- ((struct vfe_message *)data)->_u.msgOutput2.pmData;
-
- *ext = ctrl->extdata;
- *elen = ctrl->extlen;
- }
- break;
-
- case VFE_MSG_STATS_AF:
- pinfo->sbuf_phy =
- ((struct vfe_message *)data)->_u.msgStatsAf.afBuffer;
- break;
-
- case VFE_MSG_STATS_WE:
- pinfo->sbuf_phy =
- ((struct vfe_message *)data)->_u.msgStatsWbExp.awbBuffer;
- break;
-
- default:
- break;
- } /* switch */
-}
-
-static void
-vfe_proc_ops(enum VFE_MESSAGE_ID id, void *msg, size_t len)
-{
- struct msm_vfe_resp *rp;
-
- /* In 8k, OUTPUT1 & OUTPUT2 messages arrive before
- * SNAPSHOT_DONE. We don't send such messages to user */
-
- CDBG("ctrl->vfeOperationMode = %d, msgId = %d\n",
- ctrl->vfeOperationMode, id);
-
- if ((ctrl->vfeOperationMode == VFE_START_OPERATION_MODE_SNAPSHOT) &&
- (id == VFE_MSG_ID_OUTPUT1 || id == VFE_MSG_ID_OUTPUT2)) {
- return;
- }
-
- rp = ctrl->resp->vfe_alloc(sizeof(struct msm_vfe_resp), ctrl->syncdata);
- if (!rp) {
- CDBG("rp: cannot allocate buffer\n");
- return;
- }
-
- CDBG("vfe_proc_ops, msgId = %d\n", id);
-
- rp->evt_msg.type = MSM_CAMERA_MSG;
- rp->evt_msg.msg_id = id;
- rp->evt_msg.len = len;
- rp->evt_msg.data = msg;
-
- switch (rp->evt_msg.msg_id) {
- case VFE_MSG_ID_SNAPSHOT_DONE:
- rp->type = VFE_MSG_SNAPSHOT;
- break;
-
- case VFE_MSG_ID_OUTPUT1:
- rp->type = VFE_MSG_OUTPUT1;
- vfe_addr_convert(&(rp->phy), VFE_MSG_OUTPUT1,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case VFE_MSG_ID_OUTPUT2:
- rp->type = VFE_MSG_OUTPUT2;
- vfe_addr_convert(&(rp->phy), VFE_MSG_OUTPUT2,
- rp->evt_msg.data, &(rp->extdata),
- &(rp->extlen));
- break;
-
- case VFE_MSG_ID_STATS_AUTOFOCUS:
- rp->type = VFE_MSG_STATS_AF;
- vfe_addr_convert(&(rp->phy), VFE_MSG_STATS_AF,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- case VFE_MSG_ID_STATS_WB_EXP:
- rp->type = VFE_MSG_STATS_WE;
- vfe_addr_convert(&(rp->phy), VFE_MSG_STATS_WE,
- rp->evt_msg.data, NULL, NULL);
- break;
-
- default:
- rp->type = VFE_MSG_GENERAL;
- break;
- }
-
- ctrl->resp->vfe_resp(rp, MSM_CAM_Q_VFE_MSG, ctrl->syncdata);
-}
-
-static void vfe_send_msg_no_payload(enum VFE_MESSAGE_ID id)
-{
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = id;
- vfe_proc_ops(id, msg, 0);
-}
-
-static void vfe_send_bus_overflow_msg(void)
-{
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = VFE_MSG_ID_BUS_OVERFLOW;
-#if 0
- memcpy(&(msg->_u.msgBusOverflow),
- &ctrl->vfePmData, sizeof(ctrl->vfePmData));
-#endif
-
- vfe_proc_ops(VFE_MSG_ID_BUS_OVERFLOW,
- msg, sizeof(struct vfe_message));
-}
-
-static void vfe_send_camif_error_msg(void)
-{
-#if 0
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- msg->_d = VFE_MSG_ID_CAMIF_ERROR;
- memcpy(&(msg->_u.msgCamifError),
- &ctrl->vfeCamifStatusLocal, sizeof(ctrl->vfeCamifStatusLocal));
-
- vfe_proc_ops(VFE_MSG_ID_CAMIF_ERROR,
- msg, sizeof(struct vfe_message));
-#endif
-}
-
-static void vfe_process_error_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- /* all possible error irq. Note error irqs are not enabled, it is
- * checked only when other interrupts are present. */
- if (irqstatus->afOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AF_OVERFLOW);
-
- if (irqstatus->awbOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AWB_OVERFLOW);
-
- if (irqstatus->axiErrorIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_AXI_ERROR);
-
- if (irqstatus->busOverflowIrq)
- vfe_send_bus_overflow_msg();
-
- if (irqstatus->camifErrorIrq)
- vfe_send_camif_error_msg();
-
- if (irqstatus->camifOverflowIrq)
- vfe_send_msg_no_payload(VFE_MSG_ID_CAMIF_OVERFLOW);
-
- if (irqstatus->violationIrq)
- ;
-}
-
-static void vfe_process_camif_sof_irq(void)
-{
- /* increment the frame id number. */
- ctrl->vfeFrameId++;
-
- CDBG("camif_sof_irq, frameId = %d\n",
- ctrl->vfeFrameId);
-
- /* In snapshot mode, if frame skip is programmed,
- * need to check it accordingly to stop camif at
- * correct frame boundary. For the dropped frames,
- * there won't be any output path irqs, but there is
- * still SOF irq, which can help us determine when
- * to stop the camif.
- */
- if (ctrl->vfeOperationMode) {
- if ((1 << ctrl->vfeFrameSkipCount) &
- ctrl->vfeFrameSkipPattern) {
-
- ctrl->vfeSnapShotCount--;
- if (ctrl->vfeSnapShotCount == 0)
- /* terminate vfe pipeline at frame boundary. */
- writel(CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY,
- ctrl->vfebase + CAMIF_COMMAND);
- }
-
- /* update frame skip counter for bit checking. */
- ctrl->vfeFrameSkipCount++;
- if (ctrl->vfeFrameSkipCount ==
- (ctrl->vfeFrameSkipPeriod + 1))
- ctrl->vfeFrameSkipCount = 0;
- }
-}
-
-static int vfe_get_af_pingpong_status(void)
-{
- uint32_t busPingPongStatus;
- int rc = 0;
-
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- if ((busPingPongStatus & VFE_AF_PINGPONG_STATUS_BIT) == 0)
- return -EFAULT;
-
- return rc;
-}
-
-static uint32_t vfe_read_af_buf_addr(boolean pipo)
-{
- if (pipo == FALSE)
- return readl(ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- else
- return readl(ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-}
-
-static void
-vfe_update_af_buf_addr(boolean pipo, uint32_t addr)
-{
- if (pipo == FALSE)
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- else
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
-}
-
-static void
-vfe_send_af_stats_msg(uint32_t afBufAddress)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto af_stats_done;
- }
-
- msg->_d = VFE_MSG_ID_STATS_AUTOFOCUS;
- msg->_u.msgStatsAf.afBuffer = afBufAddress;
- msg->_u.msgStatsAf.frameCounter = ctrl->vfeFrameId;
-
- vfe_proc_ops(VFE_MSG_ID_STATS_AUTOFOCUS,
- msg, sizeof(struct vfe_message));
-
- ctrl->afStatsControl.ackPending = TRUE;
-
-af_stats_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_process_stats_af_irq(void)
-{
- boolean bufferAvailable;
-
- if (!(ctrl->afStatsControl.ackPending)) {
-
- /* read hardware status. */
- ctrl->afStatsControl.pingPongStatus =
- vfe_get_af_pingpong_status();
-
- bufferAvailable =
- (ctrl->afStatsControl.pingPongStatus) ^ 1;
-
- ctrl->afStatsControl.bufToRender =
- vfe_read_af_buf_addr(bufferAvailable);
-
- /* update the same buffer address (ping or pong) */
- vfe_update_af_buf_addr(bufferAvailable,
- ctrl->afStatsControl.nextFrameAddrBuf);
-
- vfe_send_af_stats_msg(ctrl->afStatsControl.bufToRender);
- } else
- ctrl->afStatsControl.droppedStatsFrameCount++;
-}
-
-static boolean vfe_get_awb_pingpong_status(void)
-{
- uint32_t busPingPongStatus;
-
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- if ((busPingPongStatus & VFE_AWB_PINGPONG_STATUS_BIT) == 0)
- return FALSE;
-
- return TRUE;
-}
-
-static uint32_t
-vfe_read_awb_buf_addr(boolean pingpong)
-{
- if (pingpong == FALSE)
- return readl(ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- else
- return readl(ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static void vfe_update_awb_buf_addr(
- boolean pingpong, uint32_t addr)
-{
- if (pingpong == FALSE)
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- else
- writel(addr, ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
-}
-
-static void vfe_send_awb_stats_msg(uint32_t awbBufAddress)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg =
- kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto awb_stats_done;
- }
-
- msg->_d = VFE_MSG_ID_STATS_WB_EXP;
- msg->_u.msgStatsWbExp.awbBuffer = awbBufAddress;
- msg->_u.msgStatsWbExp.frameCounter = ctrl->vfeFrameId;
-
- vfe_proc_ops(VFE_MSG_ID_STATS_WB_EXP,
- msg, sizeof(struct vfe_message));
-
- ctrl->awbStatsControl.ackPending = TRUE;
-
-awb_stats_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_process_stats_awb_irq(void)
-{
- boolean bufferAvailable;
-
- if (!(ctrl->awbStatsControl.ackPending)) {
-
- ctrl->awbStatsControl.pingPongStatus =
- vfe_get_awb_pingpong_status();
-
- bufferAvailable = (ctrl->awbStatsControl.pingPongStatus) ^ 1;
-
- ctrl->awbStatsControl.bufToRender =
- vfe_read_awb_buf_addr(bufferAvailable);
-
- vfe_update_awb_buf_addr(bufferAvailable,
- ctrl->awbStatsControl.nextFrameAddrBuf);
-
- vfe_send_awb_stats_msg(ctrl->awbStatsControl.bufToRender);
-
- } else
- ctrl->awbStatsControl.droppedStatsFrameCount++;
-}
-
-static void vfe_process_sync_timer_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- if (irqstatus->syncTimer0Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER0_DONE);
-
- if (irqstatus->syncTimer1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER1_DONE);
-
- if (irqstatus->syncTimer2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_SYNC_TIMER2_DONE);
-}
-
-static void vfe_process_async_timer_irq(
- struct vfe_interrupt_status *irqstatus)
-{
-
- if (irqstatus->asyncTimer0Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER0_DONE);
-
- if (irqstatus->asyncTimer1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER1_DONE);
-
- if (irqstatus->asyncTimer2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER2_DONE);
-
- if (irqstatus->asyncTimer3Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER3_DONE);
-}
-
-static void vfe_send_violation_msg(void)
-{
- vfe_send_msg_no_payload(VFE_MSG_ID_VIOLATION);
-}
-
-static void vfe_send_async_timer_msg(void)
-{
- vfe_send_msg_no_payload(VFE_MSG_ID_ASYNC_TIMER0_DONE);
-}
-
-static void vfe_write_gamma_table(uint8_t channel,
- boolean bank, int16_t *pTable)
-{
- uint16_t i;
-
- enum VFE_DMI_RAM_SEL dmiRamSel = NO_MEM_SELECTED;
-
- switch (channel) {
- case 0:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH0_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH0_BANK1;
- break;
-
- case 1:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH1_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH1_BANK1;
- break;
-
- case 2:
- if (bank == 0)
- dmiRamSel = RGBLUT_RAM_CH2_BANK0;
- else
- dmiRamSel = RGBLUT_RAM_CH2_BANK1;
- break;
-
- default:
- break;
- }
-
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_GAMMA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, need to set the DMI_CFG to unselect any SRAM
- unselect the SRAM Bank. */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-}
-
-static void vfe_prog_hw_testgen_cmd(uint32_t value)
-{
- writel(value, ctrl->vfebase + VFE_HW_TESTGEN_CMD);
-}
-
-static inline void vfe_read_irq_status(struct vfe_irq_thread_msg *out)
-{
- uint32_t *temp;
-
- memset(out, 0, sizeof(struct vfe_irq_thread_msg));
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_IRQ_STATUS);
- out->vfeIrqStatus = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + CAMIF_STATUS);
- out->camifStatus = readl(temp);
- writel(0x7, ctrl->vfebase + CAMIF_COMMAND);
- writel(0x3, ctrl->vfebase + CAMIF_COMMAND);
- CDBG("camifStatus = 0x%x\n", out->camifStatus);
-
-/*
- temp = (uint32_t *)(ctrl->vfebase + VFE_DEMOSAIC_STATUS);
- out->demosaicStatus = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_ASF_MAX_EDGE);
- out->asfMaxEdge = readl(temp);
-
- temp = (uint32_t *)(ctrl->vfebase + VFE_BUS_ENC_Y_WR_PM_STATS_0);
-*/
-
-#if 0
- out->pmInfo.encPathPmInfo.yWrPmStats0 = readl(temp++);
- out->pmInfo.encPathPmInfo.yWrPmStats1 = readl(temp++);
- out->pmInfo.encPathPmInfo.cbcrWrPmStats0 = readl(temp++);
- out->pmInfo.encPathPmInfo.cbcrWrPmStats1 = readl(temp++);
- out->pmInfo.viewPathPmInfo.yWrPmStats0 = readl(temp++);
- out->pmInfo.viewPathPmInfo.yWrPmStats1 = readl(temp++);
- out->pmInfo.viewPathPmInfo.cbcrWrPmStats0 = readl(temp++);
- out->pmInfo.viewPathPmInfo.cbcrWrPmStats1 = readl(temp);
-#endif /* if 0 Jeff */
-}
-
-static struct vfe_interrupt_status
-vfe_parse_interrupt_status(uint32_t irqStatusIn)
-{
- struct vfe_irqenable hwstat;
- struct vfe_interrupt_status ret;
- boolean temp;
-
- memset(&hwstat, 0, sizeof(hwstat));
- memset(&ret, 0, sizeof(ret));
-
- hwstat = *((struct vfe_irqenable *)(&irqStatusIn));
-
- ret.camifErrorIrq = hwstat.camifErrorIrq;
- ret.camifSofIrq = hwstat.camifSofIrq;
- ret.camifEolIrq = hwstat.camifEolIrq;
- ret.camifEofIrq = hwstat.camifEofIrq;
- ret.camifEpoch1Irq = hwstat.camifEpoch1Irq;
- ret.camifEpoch2Irq = hwstat.camifEpoch2Irq;
- ret.camifOverflowIrq = hwstat.camifOverflowIrq;
- ret.ceIrq = hwstat.ceIrq;
- ret.regUpdateIrq = hwstat.regUpdateIrq;
- ret.resetAckIrq = hwstat.resetAckIrq;
- ret.encYPingpongIrq = hwstat.encYPingpongIrq;
- ret.encCbcrPingpongIrq = hwstat.encCbcrPingpongIrq;
- ret.viewYPingpongIrq = hwstat.viewYPingpongIrq;
- ret.viewCbcrPingpongIrq = hwstat.viewCbcrPingpongIrq;
- ret.rdPingpongIrq = hwstat.rdPingpongIrq;
- ret.afPingpongIrq = hwstat.afPingpongIrq;
- ret.awbPingpongIrq = hwstat.awbPingpongIrq;
- ret.histPingpongIrq = hwstat.histPingpongIrq;
- ret.encIrq = hwstat.encIrq;
- ret.viewIrq = hwstat.viewIrq;
- ret.busOverflowIrq = hwstat.busOverflowIrq;
- ret.afOverflowIrq = hwstat.afOverflowIrq;
- ret.awbOverflowIrq = hwstat.awbOverflowIrq;
- ret.syncTimer0Irq = hwstat.syncTimer0Irq;
- ret.syncTimer1Irq = hwstat.syncTimer1Irq;
- ret.syncTimer2Irq = hwstat.syncTimer2Irq;
- ret.asyncTimer0Irq = hwstat.asyncTimer0Irq;
- ret.asyncTimer1Irq = hwstat.asyncTimer1Irq;
- ret.asyncTimer2Irq = hwstat.asyncTimer2Irq;
- ret.asyncTimer3Irq = hwstat.asyncTimer3Irq;
- ret.axiErrorIrq = hwstat.axiErrorIrq;
- ret.violationIrq = hwstat.violationIrq;
-
- /* logic OR of any error bits
- * although each irq corresponds to a bit, the data type here is a
- * boolean already. hence use logic operation.
- */
- temp =
- ret.camifErrorIrq ||
- ret.camifOverflowIrq ||
- ret.afOverflowIrq ||
- ret.awbPingpongIrq ||
- ret.busOverflowIrq ||
- ret.axiErrorIrq ||
- ret.violationIrq;
-
- ret.anyErrorIrqs = temp;
-
- /* logic OR of any output path bits*/
- temp =
- ret.encYPingpongIrq ||
- ret.encCbcrPingpongIrq ||
- ret.encIrq;
-
- ret.anyOutput2PathIrqs = temp;
-
- temp =
- ret.viewYPingpongIrq ||
- ret.viewCbcrPingpongIrq ||
- ret.viewIrq;
-
- ret.anyOutput1PathIrqs = temp;
-
- ret.anyOutputPathIrqs =
- ret.anyOutput1PathIrqs ||
- ret.anyOutput2PathIrqs;
-
- /* logic OR of any sync timer bits*/
- temp =
- ret.syncTimer0Irq ||
- ret.syncTimer1Irq ||
- ret.syncTimer2Irq;
-
- ret.anySyncTimerIrqs = temp;
-
- /* logic OR of any async timer bits*/
- temp =
- ret.asyncTimer0Irq ||
- ret.asyncTimer1Irq ||
- ret.asyncTimer2Irq ||
- ret.asyncTimer3Irq;
-
- ret.anyAsyncTimerIrqs = temp;
-
- /* bool for all interrupts that are not allowed in idle state */
- temp =
- ret.anyErrorIrqs ||
- ret.anyOutputPathIrqs ||
- ret.anySyncTimerIrqs ||
- ret.regUpdateIrq ||
- ret.awbPingpongIrq ||
- ret.afPingpongIrq ||
- ret.camifSofIrq ||
- ret.camifEpoch2Irq ||
- ret.camifEpoch1Irq;
-
- ret.anyIrqForActiveStatesOnly =
- temp;
-
- return ret;
-}
-
-static struct vfe_frame_asf_info
-vfe_get_asf_frame_info(struct vfe_irq_thread_msg *in)
-{
- struct vfe_asf_info asfInfoTemp;
- struct vfe_frame_asf_info rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&asfInfoTemp, 0, sizeof(asfInfoTemp));
-
- asfInfoTemp =
- *((struct vfe_asf_info *)(&(in->asfMaxEdge)));
-
- rc.asfHbiCount = asfInfoTemp.HBICount;
- rc.asfMaxEdge = asfInfoTemp.maxEdge;
-
- return rc;
-}
-
-static struct vfe_frame_bpc_info
-vfe_get_demosaic_frame_info(struct vfe_irq_thread_msg *in)
-{
- struct vfe_bps_info bpcInfoTemp;
- struct vfe_frame_bpc_info rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&bpcInfoTemp, 0, sizeof(bpcInfoTemp));
-
- bpcInfoTemp =
- *((struct vfe_bps_info *)(&(in->demosaicStatus)));
-
- rc.greenDefectPixelCount =
- bpcInfoTemp.greenBadPixelCount;
-
- rc.redBlueDefectPixelCount =
- bpcInfoTemp.RedBlueBadPixelCount;
-
- return rc;
-}
-
-static struct vfe_msg_camif_status
-vfe_get_camif_status(struct vfe_irq_thread_msg *in)
-{
- struct vfe_camif_stats camifStatusTemp;
- struct vfe_msg_camif_status rc;
-
- memset(&rc, 0, sizeof(rc));
- memset(&camifStatusTemp, 0, sizeof(camifStatusTemp));
-
- camifStatusTemp =
- *((struct vfe_camif_stats *)(&(in->camifStatus)));
-
- rc.camifState = (boolean)camifStatusTemp.camifHalt;
- rc.lineCount = camifStatusTemp.lineCount;
- rc.pixelCount = camifStatusTemp.pixelCount;
-
- return rc;
-}
-
-static struct vfe_bus_performance_monitor
-vfe_get_performance_monitor_data(struct vfe_irq_thread_msg *in)
-{
- struct vfe_bus_performance_monitor rc;
- memset(&rc, 0, sizeof(rc));
-
- rc.encPathPmInfo.yWrPmStats0 =
- in->pmInfo.encPathPmInfo.yWrPmStats0;
- rc.encPathPmInfo.yWrPmStats1 =
- in->pmInfo.encPathPmInfo.yWrPmStats1;
- rc.encPathPmInfo.cbcrWrPmStats0 =
- in->pmInfo.encPathPmInfo.cbcrWrPmStats0;
- rc.encPathPmInfo.cbcrWrPmStats1 =
- in->pmInfo.encPathPmInfo.cbcrWrPmStats1;
- rc.viewPathPmInfo.yWrPmStats0 =
- in->pmInfo.viewPathPmInfo.yWrPmStats0;
- rc.viewPathPmInfo.yWrPmStats1 =
- in->pmInfo.viewPathPmInfo.yWrPmStats1;
- rc.viewPathPmInfo.cbcrWrPmStats0 =
- in->pmInfo.viewPathPmInfo.cbcrWrPmStats0;
- rc.viewPathPmInfo.cbcrWrPmStats1 =
- in->pmInfo.viewPathPmInfo.cbcrWrPmStats1;
-
- return rc;
-}
-
-static void vfe_process_reg_update_irq(void)
-{
- CDBG("vfe_process_reg_update_irq: ackPendingFlag is %d\n",
- ctrl->vfeStartAckPendingFlag);
- if (ctrl->vfeStartAckPendingFlag == TRUE) {
- vfe_send_msg_no_payload(VFE_MSG_ID_START_ACK);
- ctrl->vfeStartAckPendingFlag = FALSE;
- } else
- vfe_send_msg_no_payload(VFE_MSG_ID_UPDATE_ACK);
-}
-
-static void vfe_process_reset_irq(void)
-{
- /* unsigned long flags; */
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- ctrl->vstate = VFE_STATE_IDLE;
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
-
- if (ctrl->vfeStopAckPending == TRUE) {
- ctrl->vfeStopAckPending = FALSE;
- vfe_send_msg_no_payload(VFE_MSG_ID_STOP_ACK);
- } else {
- vfe_set_default_reg_values();
- vfe_send_msg_no_payload(VFE_MSG_ID_RESET_ACK);
- }
-}
-
-static void vfe_process_pingpong_irq(struct vfe_output_path *in,
- uint8_t fragmentCount)
-{
- uint16_t circularIndex;
- uint32_t nextFragmentAddr;
-
- /* get next fragment address from circular buffer */
- circularIndex = (in->fragIndex) % (2 * fragmentCount);
- nextFragmentAddr = in->addressBuffer[circularIndex];
-
- in->fragIndex = circularIndex + 1;
-
- /* use next fragment to program hardware ping/pong address. */
- if (in->hwCurrentFlag == ping) {
- writel(nextFragmentAddr, in->hwRegPingAddress);
- in->hwCurrentFlag = pong;
-
- } else {
- writel(nextFragmentAddr, in->hwRegPongAddress);
- in->hwCurrentFlag = ping;
- }
-}
-
-static void vfe_send_output2_msg(
- struct vfe_msg_output *pPayload)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* fill message with right content. */
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto output2_msg_done;
- }
-
- msg->_d = VFE_MSG_ID_OUTPUT2;
-
- memcpy(&(msg->_u.msgOutput2),
- (void *)pPayload, sizeof(struct vfe_msg_output));
-
- vfe_proc_ops(VFE_MSG_ID_OUTPUT2,
- msg, sizeof(struct vfe_message));
-
- ctrl->encPath.ackPending = TRUE;
-
- if (!(ctrl->vfeRequestedSnapShotCount <= 3) &&
- (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT))
- ctrl->encPath.ackPending = TRUE;
-
-output2_msg_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_send_output1_msg(
- struct vfe_msg_output *pPayload)
-{
- /* unsigned long flags; */
- struct vfe_message *msg;
-
- msg = kzalloc(sizeof(struct vfe_message), GFP_ATOMIC);
- if (!msg)
- return;
-
- /* @todo This is causing issues, need further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- kfree(msg);
- goto output1_msg_done;
- }
-
- msg->_d = VFE_MSG_ID_OUTPUT1;
- memmove(&(msg->_u),
- (void *)pPayload, sizeof(struct vfe_msg_output));
-
- vfe_proc_ops(VFE_MSG_ID_OUTPUT1,
- msg, sizeof(struct vfe_message));
-
- ctrl->viewPath.ackPending = TRUE;
-
- if (!(ctrl->vfeRequestedSnapShotCount <= 3) &&
- (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT))
- ctrl->viewPath.ackPending = TRUE;
-
-output1_msg_done:
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
- return;
-}
-
-static void vfe_send_output_msg(boolean whichOutputPath,
- uint32_t yPathAddr, uint32_t cbcrPathAddr)
-{
- struct vfe_msg_output msgPayload;
-
- msgPayload.yBuffer = yPathAddr;
- msgPayload.cbcrBuffer = cbcrPathAddr;
-
- /* asf info is common for both output1 and output2 */
-#if 0
- msgPayload.asfInfo.asfHbiCount = ctrl->vfeAsfFrameInfo.asfHbiCount;
- msgPayload.asfInfo.asfMaxEdge = ctrl->vfeAsfFrameInfo.asfMaxEdge;
-
- /* demosaic info is common for both output1 and output2 */
- msgPayload.bpcInfo.greenDefectPixelCount =
- ctrl->vfeBpcFrameInfo.greenDefectPixelCount;
- msgPayload.bpcInfo.redBlueDefectPixelCount =
- ctrl->vfeBpcFrameInfo.redBlueDefectPixelCount;
-#endif /* if 0 */
-
- /* frame ID is common for both paths. */
- msgPayload.frameCounter = ctrl->vfeFrameId;
-
- if (whichOutputPath) {
- /* msgPayload.pmData = ctrl->vfePmData.encPathPmInfo; */
- vfe_send_output2_msg(&msgPayload);
- } else {
- /* msgPayload.pmData = ctrl->vfePmData.viewPathPmInfo; */
- vfe_send_output1_msg(&msgPayload);
- }
-}
-
-static void vfe_process_frame_done_irq_multi_frag(
- struct vfe_output_path_combo *in)
-{
- uint32_t yAddress, cbcrAddress;
- uint16_t idx;
- uint32_t *ptrY;
- uint32_t *ptrCbcr;
- const uint32_t *ptrSrc;
- uint8_t i;
-
- if (!in->ackPending) {
-
- idx = (in->currentFrame) * (in->fragCount);
-
- /* Send output message. */
- yAddress = in->yPath.addressBuffer[idx];
- cbcrAddress = in->cbcrPath.addressBuffer[idx];
-
- /* copy next frame to current frame. */
- ptrSrc = in->nextFrameAddrBuf;
- ptrY = (uint32_t *)&(in->yPath.addressBuffer[idx]);
- ptrCbcr = (uint32_t *)&(in->cbcrPath.addressBuffer[idx]);
-
- /* Copy Y address */
- for (i = 0; i < in->fragCount; i++)
- *ptrY++ = *ptrSrc++;
-
- /* Copy Cbcr address */
- for (i = 0; i < in->fragCount; i++)
- *ptrCbcr++ = *ptrSrc++;
-
- vfe_send_output_msg(in->whichOutputPath, yAddress, cbcrAddress);
-
- } else {
- if (in->whichOutputPath == 0)
- ctrl->vfeDroppedFrameCounts.output1Count++;
-
- if (in->whichOutputPath == 1)
- ctrl->vfeDroppedFrameCounts.output2Count++;
- }
-
- /* toggle current frame. */
- in->currentFrame = in->currentFrame^1;
-
- if (ctrl->vfeOperationMode)
- in->snapshotPendingCount--;
-}
-
-static void vfe_process_frame_done_irq_no_frag_io(
- struct vfe_output_path_combo *in, uint32_t *pNextAddr,
- uint32_t *pdestRenderAddr)
-{
- uint32_t busPingPongStatus;
- uint32_t tempAddress;
-
- /* 1. read hw status register. */
- busPingPongStatus =
- readl(ctrl->vfebase + VFE_BUS_PINGPONG_STATUS);
-
- CDBG("hardware status is 0x%x\n", busPingPongStatus);
-
- /* 2. determine ping or pong */
- /* use cbcr status */
- busPingPongStatus = busPingPongStatus & (1<<(in->cbcrStatusBit));
-
- /* 3. read out address and update address */
- if (busPingPongStatus == 0) {
- /* hw is working on ping, render pong buffer */
- /* a. read out pong address */
- /* read out y address. */
- tempAddress = readl(in->yPath.hwRegPongAddress);
-
- CDBG("pong 1 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr++ = tempAddress;
- /* read out cbcr address. */
- tempAddress = readl(in->cbcrPath.hwRegPongAddress);
-
- CDBG("pong 2 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr = tempAddress;
-
- /* b. update pong address */
- writel(*pNextAddr++, in->yPath.hwRegPongAddress);
- writel(*pNextAddr, in->cbcrPath.hwRegPongAddress);
- } else {
- /* hw is working on pong, render ping buffer */
-
- /* a. read out ping address */
- tempAddress = readl(in->yPath.hwRegPingAddress);
- CDBG("ping 1 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr++ = tempAddress;
- tempAddress = readl(in->cbcrPath.hwRegPingAddress);
-
- CDBG("ping 2 addr = 0x%x\n", tempAddress);
- *pdestRenderAddr = tempAddress;
-
- /* b. update ping address */
- writel(*pNextAddr++, in->yPath.hwRegPingAddress);
- CDBG("NextAddress = 0x%x\n", *pNextAddr);
- writel(*pNextAddr, in->cbcrPath.hwRegPingAddress);
- }
-}
-
-static void vfe_process_frame_done_irq_no_frag(
- struct vfe_output_path_combo *in)
-{
- uint32_t addressToRender[2];
- static uint32_t fcnt;
-
- if (fcnt++ < 3)
- return;
-
- if (!in->ackPending) {
- vfe_process_frame_done_irq_no_frag_io(in,
- in->nextFrameAddrBuf, addressToRender);
-
- /* use addressToRender to send out message. */
- vfe_send_output_msg(in->whichOutputPath,
- addressToRender[0], addressToRender[1]);
-
- } else {
- /* ackPending is still there, accumulate dropped frame count.
- * These count can be read through ioctrl command. */
- CDBG("waiting frame ACK\n");
-
- if (in->whichOutputPath == 0)
- ctrl->vfeDroppedFrameCounts.output1Count++;
-
- if (in->whichOutputPath == 1)
- ctrl->vfeDroppedFrameCounts.output2Count++;
- }
-
- /* in case of multishot when upper layer did not ack, there will still
- * be a snapshot done msg sent out, even though the number of frames
- * sent out may be less than the desired number of frames. snapshot
- * done msg would be helpful to indicate that vfe pipeline has stop,
- * and in good known state.
- */
- if (ctrl->vfeOperationMode)
- in->snapshotPendingCount--;
-}
-
-static void vfe_process_output_path_irq(
- struct vfe_interrupt_status *irqstatus)
-{
- /* unsigned long flags; */
-
- /* process the view path interrupts */
- if (irqstatus->anyOutput1PathIrqs) {
- if (ctrl->viewPath.multiFrag) {
-
- if (irqstatus->viewCbcrPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->viewPath.cbcrPath),
- ctrl->viewPath.fragCount);
-
- if (irqstatus->viewYPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->viewPath.yPath),
- ctrl->viewPath.fragCount);
-
- if (irqstatus->viewIrq)
- vfe_process_frame_done_irq_multi_frag(
- &ctrl->viewPath);
-
- } else {
- /* typical case for no fragment,
- only frame done irq is enabled. */
- if (irqstatus->viewIrq)
- vfe_process_frame_done_irq_no_frag(
- &ctrl->viewPath);
- }
- }
-
- /* process the encoder path interrupts */
- if (irqstatus->anyOutput2PathIrqs) {
- if (ctrl->encPath.multiFrag) {
- if (irqstatus->encCbcrPingpongIrq)
- vfe_process_pingpong_irq(
- &(ctrl->encPath.cbcrPath),
- ctrl->encPath.fragCount);
-
- if (irqstatus->encYPingpongIrq)
- vfe_process_pingpong_irq(&(ctrl->encPath.yPath),
- ctrl->encPath.fragCount);
-
- if (irqstatus->encIrq)
- vfe_process_frame_done_irq_multi_frag(
- &ctrl->encPath);
-
- } else {
- if (irqstatus->encIrq)
- vfe_process_frame_done_irq_no_frag(
- &ctrl->encPath);
- }
- }
-
- if (ctrl->vfeOperationMode) {
- if ((ctrl->encPath.snapshotPendingCount == 0) &&
- (ctrl->viewPath.snapshotPendingCount == 0)) {
-
- /* @todo This is causing issues, further investigate */
- /* spin_lock_irqsave(&ctrl->state_lock, flags); */
- ctrl->vstate = VFE_STATE_IDLE;
- /* spin_unlock_irqrestore(&ctrl->state_lock, flags); */
-
- vfe_send_msg_no_payload(VFE_MSG_ID_SNAPSHOT_DONE);
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_STOP);
- vfe_pm_stop();
- }
- }
-}
-
-static void vfe_do_tasklet(unsigned long data)
-{
- unsigned long flags;
-
- struct isr_queue_cmd *qcmd = NULL;
-
- CDBG("=== vfe_do_tasklet start === \n");
-
- spin_lock_irqsave(&ctrl->tasklet_lock, flags);
- qcmd = list_first_entry(&ctrl->tasklet_q,
- struct isr_queue_cmd, list);
-
- if (!qcmd) {
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
- return;
- }
-
- list_del(&qcmd->list);
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
-
- if (qcmd->vfeInterruptStatus.regUpdateIrq) {
- CDBG("irq regUpdateIrq\n");
- vfe_process_reg_update_irq();
- }
-
- if (qcmd->vfeInterruptStatus.resetAckIrq) {
- CDBG("irq resetAckIrq\n");
- vfe_process_reset_irq();
- }
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- if (ctrl->vstate != VFE_STATE_ACTIVE) {
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
- return;
- }
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-
-#if 0
- if (qcmd->vfeInterruptStatus.camifEpoch1Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_EPOCH1);
-
- if (qcmd->vfeInterruptStatus.camifEpoch2Irq)
- vfe_send_msg_no_payload(VFE_MSG_ID_EPOCH2);
-#endif /* Jeff */
-
- /* next, check output path related interrupts. */
- if (qcmd->vfeInterruptStatus.anyOutputPathIrqs) {
- CDBG("irq anyOutputPathIrqs\n");
- vfe_process_output_path_irq(&qcmd->vfeInterruptStatus);
- }
-
- if (qcmd->vfeInterruptStatus.afPingpongIrq)
- vfe_process_stats_af_irq();
-
- if (qcmd->vfeInterruptStatus.awbPingpongIrq)
- vfe_process_stats_awb_irq();
-
- /* any error irqs*/
- if (qcmd->vfeInterruptStatus.anyErrorIrqs)
- vfe_process_error_irq(&qcmd->vfeInterruptStatus);
-
-#if 0
- if (qcmd->vfeInterruptStatus.anySyncTimerIrqs)
- vfe_process_sync_timer_irq();
-
- if (qcmd->vfeInterruptStatus.anyAsyncTimerIrqs)
- vfe_process_async_timer_irq();
-#endif /* Jeff */
-
- if (qcmd->vfeInterruptStatus.camifSofIrq) {
- CDBG("irq camifSofIrq\n");
- vfe_process_camif_sof_irq();
- }
-
- kfree(qcmd);
- CDBG("=== vfe_do_tasklet end === \n");
-}
-
-DECLARE_TASKLET(vfe_tasklet, vfe_do_tasklet, 0);
-
-static irqreturn_t vfe_parse_irq(int irq_num, void *data)
-{
- unsigned long flags;
- uint32_t irqStatusLocal;
- struct vfe_irq_thread_msg irq;
- struct isr_queue_cmd *qcmd;
-
- CDBG("vfe_parse_irq\n");
-
- vfe_read_irq_status(&irq);
-
- if (irq.vfeIrqStatus == 0) {
- CDBG("vfe_parse_irq: irq.vfeIrqStatus is 0\n");
- return IRQ_HANDLED;
- }
-
- qcmd = kzalloc(sizeof(struct isr_queue_cmd),
- GFP_ATOMIC);
- if (!qcmd) {
- CDBG("vfe_parse_irq: qcmd malloc failed!\n");
- return IRQ_HANDLED;
- }
-
- spin_lock_irqsave(&ctrl->ack_lock, flags);
-
- if (ctrl->vfeStopAckPending)
- irqStatusLocal =
- (VFE_IMASK_WHILE_STOPPING & irq.vfeIrqStatus);
- else
- irqStatusLocal =
- ((ctrl->vfeImaskPacked | VFE_IMASK_ERROR_ONLY) &
- irq.vfeIrqStatus);
-
- spin_unlock_irqrestore(&ctrl->ack_lock, flags);
-
- /* first parse the interrupt status to local data structures. */
- qcmd->vfeInterruptStatus = vfe_parse_interrupt_status(irqStatusLocal);
- qcmd->vfeAsfFrameInfo = vfe_get_asf_frame_info(&irq);
- qcmd->vfeBpcFrameInfo = vfe_get_demosaic_frame_info(&irq);
- qcmd->vfeCamifStatusLocal = vfe_get_camif_status(&irq);
- qcmd->vfePmData = vfe_get_performance_monitor_data(&irq);
-
- spin_lock_irqsave(&ctrl->tasklet_lock, flags);
- list_add_tail(&qcmd->list, &ctrl->tasklet_q);
- spin_unlock_irqrestore(&ctrl->tasklet_lock, flags);
- tasklet_schedule(&vfe_tasklet);
-
- /* clear the pending interrupt of the same kind.*/
- writel(irq.vfeIrqStatus, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- return IRQ_HANDLED;
-}
-
-int vfe_cmd_init(struct msm_vfe_callback *presp,
- struct platform_device *pdev, void *sdata)
-{
- struct resource *vfemem, *vfeirq, *vfeio;
- int rc;
-
- vfemem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!vfemem) {
- CDBG("no mem resource?\n");
- return -ENODEV;
- }
-
- vfeirq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!vfeirq) {
- CDBG("no irq resource?\n");
- return -ENODEV;
- }
-
- vfeio = request_mem_region(vfemem->start,
- resource_size(vfemem), pdev->name);
- if (!vfeio) {
- CDBG("VFE region already claimed\n");
- return -EBUSY;
- }
-
- ctrl =
- kzalloc(sizeof(struct msm_vfe8x_ctrl), GFP_KERNEL);
- if (!ctrl) {
- rc = -ENOMEM;
- goto cmd_init_failed1;
- }
-
- ctrl->vfeirq = vfeirq->start;
-
- ctrl->vfebase =
- ioremap(vfemem->start, (vfemem->end - vfemem->start) + 1);
- if (!ctrl->vfebase) {
- rc = -ENOMEM;
- goto cmd_init_failed2;
- }
-
- rc = request_irq(ctrl->vfeirq, vfe_parse_irq,
- IRQF_TRIGGER_RISING, "vfe", 0);
- if (rc < 0)
- goto cmd_init_failed2;
-
- if (presp && presp->vfe_resp)
- ctrl->resp = presp;
- else {
- rc = -EINVAL;
- goto cmd_init_failed3;
- }
-
- ctrl->extdata =
- kmalloc(sizeof(struct vfe_frame_extra), GFP_KERNEL);
- if (!ctrl->extdata) {
- rc = -ENOMEM;
- goto cmd_init_failed3;
- }
-
- spin_lock_init(&ctrl->ack_lock);
- spin_lock_init(&ctrl->state_lock);
- spin_lock_init(&ctrl->io_lock);
-
- ctrl->extlen = sizeof(struct vfe_frame_extra);
-
- spin_lock_init(&ctrl->tasklet_lock);
- INIT_LIST_HEAD(&ctrl->tasklet_q);
-
- ctrl->syncdata = sdata;
- return 0;
-
-cmd_init_failed3:
- disable_irq(ctrl->vfeirq);
- free_irq(ctrl->vfeirq, 0);
- iounmap(ctrl->vfebase);
-cmd_init_failed2:
- kfree(ctrl);
-cmd_init_failed1:
- release_mem_region(vfemem->start, (vfemem->end - vfemem->start) + 1);
- return rc;
-}
-
-void vfe_cmd_release(struct platform_device *dev)
-{
- struct resource *mem;
-
- disable_irq(ctrl->vfeirq);
- free_irq(ctrl->vfeirq, 0);
-
- iounmap(ctrl->vfebase);
- mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
- release_mem_region(mem->start, (mem->end - mem->start) + 1);
-
- ctrl->extlen = 0;
-
- kfree(ctrl->extdata);
- kfree(ctrl);
-}
-
-void vfe_stats_af_stop(void)
-{
- ctrl->vfeStatsCmdLocal.autoFocusEnable = FALSE;
- ctrl->vfeImaskLocal.afPingpongIrq = FALSE;
-}
-
-void vfe_stop(void)
-{
- boolean vfeAxiBusy;
- uint32_t vfeAxiStauts;
-
- /* for reset hw modules, and send msg when reset_irq comes.*/
- ctrl->vfeStopAckPending = TRUE;
-
- ctrl->vfeStatsPingPongReloadFlag = FALSE;
- vfe_pm_stop();
-
- /* disable all interrupts. */
- vfe_program_irq_mask(VFE_DISABLE_ALL_IRQS);
-
- /* in either continuous or snapshot mode, stop command can be issued
- * at any time.
- */
- vfe_camif_stop_immediately();
- vfe_program_axi_cmd(AXI_HALT);
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_STOP);
-
- vfeAxiBusy = TRUE;
-
- while (vfeAxiBusy) {
- vfeAxiStauts = vfe_read_axi_status();
- if ((vfeAxiStauts & AXI_STATUS_BUSY_MASK) != 0)
- vfeAxiBusy = FALSE;
- }
-
- vfe_program_axi_cmd(AXI_HALT_CLEAR);
-
- /* clear all pending interrupts */
- writel(VFE_CLEAR_ALL_IRQS, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* enable reset_ack and async timer interrupt only while stopping
- * the pipeline.
- */
- vfe_program_irq_mask(VFE_IMASK_WHILE_STOPPING);
-
- vfe_program_global_reset_cmd(VFE_RESET_UPON_STOP_CMD);
-}
-
-void vfe_update(void)
-{
- ctrl->vfeModuleEnableLocal.statsEnable =
- ctrl->vfeStatsCmdLocal.autoFocusEnable |
- ctrl->vfeStatsCmdLocal.axwEnable;
-
- vfe_reg_module_cfg(&ctrl->vfeModuleEnableLocal);
-
- vfe_program_stats_cmd(&ctrl->vfeStatsCmdLocal);
-
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
- vfe_program_irq_mask(ctrl->vfeImaskPacked);
-
- if ((ctrl->vfeModuleEnableLocal.statsEnable == TRUE) &&
- (ctrl->vfeStatsPingPongReloadFlag == FALSE)) {
- ctrl->vfeStatsPingPongReloadFlag = TRUE;
-
- ctrl->vfeBusCmdLocal.statsPingpongReload = TRUE;
- vfe_reg_bus_cmd(&ctrl->vfeBusCmdLocal);
- }
-
- vfe_program_reg_update_cmd(VFE_REG_UPDATE_TRIGGER);
-}
-
-int vfe_rgb_gamma_update(struct vfe_cmd_rgb_gamma_config *in)
-{
- int rc = 0;
-
- ctrl->vfeModuleEnableLocal.rgbLUTEnable = in->enable;
-
- switch (in->channelSelect) {
- case RGB_GAMMA_CH0_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- vfe_write_gamma_table(0,
- ctrl->vfeGammaLutSel.ch0BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH1_SELECTED:
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- vfe_write_gamma_table(1,
- ctrl->vfeGammaLutSel.ch1BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(2,
- ctrl->vfeGammaLutSel.ch2BankSelect, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH0_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH1_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_CH2_SELECTED:
- ctrl->vfeGammaLutSel.ch0BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch1BankSelect ^= 1;
- ctrl->vfeGammaLutSel.ch2BankSelect ^= 1;
- vfe_write_gamma_table(0, ctrl->vfeGammaLutSel.ch0BankSelect,
- in->table);
- vfe_write_gamma_table(1, ctrl->vfeGammaLutSel.ch1BankSelect,
- in->table);
- vfe_write_gamma_table(2, ctrl->vfeGammaLutSel.ch2BankSelect,
- in->table);
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- /* update the gammaLutSel register. */
- vfe_program_lut_bank_sel(&ctrl->vfeGammaLutSel);
-
- return rc;
-}
-
-int vfe_rgb_gamma_config(struct vfe_cmd_rgb_gamma_config *in)
-{
- int rc = 0;
-
- ctrl->vfeModuleEnableLocal.rgbLUTEnable = in->enable;
-
- switch (in->channelSelect) {
- case RGB_GAMMA_CH0_SELECTED:
-vfe_write_gamma_table(0, 0, in->table);
-break;
-
- case RGB_GAMMA_CH1_SELECTED:
- vfe_write_gamma_table(1, 0, in->table);
- break;
-
- case RGB_GAMMA_CH2_SELECTED:
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(1, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH2_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH1_CH2_SELECTED:
- vfe_write_gamma_table(1, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- case RGB_GAMMA_CH0_CH1_CH2_SELECTED:
- vfe_write_gamma_table(0, 0, in->table);
- vfe_write_gamma_table(1, 0, in->table);
- vfe_write_gamma_table(2, 0, in->table);
- break;
-
- default:
- rc = -EINVAL;
- break;
- } /* switch */
-
- return rc;
-}
-
-void vfe_stats_af_ack(struct vfe_cmd_stats_af_ack *in)
-{
- ctrl->afStatsControl.nextFrameAddrBuf = in->nextAFOutputBufferAddr;
- ctrl->afStatsControl.ackPending = FALSE;
-}
-
-void vfe_stats_wb_exp_ack(struct vfe_cmd_stats_wb_exp_ack *in)
-{
- ctrl->awbStatsControl.nextFrameAddrBuf = in->nextWbExpOutputBufferAddr;
- ctrl->awbStatsControl.ackPending = FALSE;
-}
-
-void vfe_output2_ack(struct vfe_cmd_output_ack *in)
-{
- const uint32_t *psrc;
- uint32_t *pdest;
- uint8_t i;
-
- pdest = ctrl->encPath.nextFrameAddrBuf;
-
- CDBG("output2_ack: ack addr = 0x%x\n", in->ybufaddr[0]);
-
- psrc = in->ybufaddr;
- for (i = 0; i < ctrl->encPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- psrc = in->chromabufaddr;
- for (i = 0; i < ctrl->encPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- ctrl->encPath.ackPending = FALSE;
-}
-
-void vfe_output1_ack(struct vfe_cmd_output_ack *in)
-{
- const uint32_t *psrc;
- uint32_t *pdest;
- uint8_t i;
-
- pdest = ctrl->viewPath.nextFrameAddrBuf;
-
- psrc = in->ybufaddr;
- for (i = 0; i < ctrl->viewPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- psrc = in->chromabufaddr;
- for (i = 0; i < ctrl->viewPath.fragCount; i++)
- *pdest++ = *psrc++;
-
- ctrl->viewPath.ackPending = FALSE;
-}
-
-void vfe_start(struct vfe_cmd_start *in)
-{
- unsigned long flags;
- uint32_t pmstatus = 0;
- boolean rawmode;
- uint32_t demperiod = 0;
- uint32_t demeven = 0;
- uint32_t demodd = 0;
-
- /* derived from other commands. (camif config, axi output config,
- * etc)
- */
- struct vfe_cfg hwcfg;
- struct vfe_upsample_cfg chromupcfg;
-
- CDBG("vfe_start operationMode = %d\n", in->operationMode);
-
- memset(&hwcfg, 0, sizeof(hwcfg));
- memset(&chromupcfg, 0, sizeof(chromupcfg));
-
- switch (in->pixel) {
- case VFE_BAYER_RGRGRG:
- demperiod = 1;
- demeven = 0xC9;
- demodd = 0xAC;
- break;
-
- case VFE_BAYER_GRGRGR:
- demperiod = 1;
- demeven = 0x9C;
- demodd = 0xCA;
- break;
-
- case VFE_BAYER_BGBGBG:
- demperiod = 1;
- demeven = 0xCA;
- demodd = 0x9C;
- break;
-
- case VFE_BAYER_GBGBGB:
- demperiod = 1;
- demeven = 0xAC;
- demodd = 0xC9;
- break;
-
- case VFE_YUV_YCbYCr:
- demperiod = 3;
- demeven = 0x9CAC;
- demodd = 0x9CAC;
- break;
-
- case VFE_YUV_YCrYCb:
- demperiod = 3;
- demeven = 0xAC9C;
- demodd = 0xAC9C;
- break;
-
- case VFE_YUV_CbYCrY:
- demperiod = 3;
- demeven = 0xC9CA;
- demodd = 0xC9CA;
- break;
-
- case VFE_YUV_CrYCbY:
- demperiod = 3;
- demeven = 0xCAC9;
- demodd = 0xCAC9;
- break;
-
- default:
- return;
- }
-
- vfe_config_demux(demperiod, demeven, demodd);
-
- vfe_program_lut_bank_sel(&ctrl->vfeGammaLutSel);
-
- /* save variables to local. */
- ctrl->vfeOperationMode = in->operationMode;
- if (ctrl->vfeOperationMode ==
- VFE_START_OPERATION_MODE_SNAPSHOT) {
- /* in snapshot mode, initialize snapshot count*/
- ctrl->vfeSnapShotCount = in->snapshotCount;
-
- /* save the requested count, this is temporarily done, to
- help with HJR / multishot. */
- ctrl->vfeRequestedSnapShotCount = ctrl->vfeSnapShotCount;
-
- CDBG("requested snapshot count = %d\n", ctrl->vfeSnapShotCount);
-
- /* Assumption is to have the same pattern and period for both
- paths, if both paths are used. */
- if (ctrl->viewPath.pathEnabled) {
- ctrl->viewPath.snapshotPendingCount =
- in->snapshotCount;
-
- ctrl->vfeFrameSkipPattern =
- ctrl->vfeFrameSkip.output1Pattern;
- ctrl->vfeFrameSkipPeriod =
- ctrl->vfeFrameSkip.output1Period;
- }
-
- if (ctrl->encPath.pathEnabled) {
- ctrl->encPath.snapshotPendingCount =
- in->snapshotCount;
-
- ctrl->vfeFrameSkipPattern =
- ctrl->vfeFrameSkip.output2Pattern;
- ctrl->vfeFrameSkipPeriod =
- ctrl->vfeFrameSkip.output2Period;
- }
- }
-
- /* enable color conversion for bayer sensor
- if stats enabled, need to do color conversion. */
- if (in->pixel <= VFE_BAYER_GBGBGB)
- ctrl->vfeStatsCmdLocal.colorConversionEnable = TRUE;
-
- vfe_program_stats_cmd(&ctrl->vfeStatsCmdLocal);
-
- if (in->pixel >= VFE_YUV_YCbYCr)
- ctrl->vfeModuleEnableLocal.chromaUpsampleEnable = TRUE;
-
- ctrl->vfeModuleEnableLocal.demuxEnable = TRUE;
-
- /* if any stats module is enabled, the main bit is enabled. */
- ctrl->vfeModuleEnableLocal.statsEnable =
- ctrl->vfeStatsCmdLocal.autoFocusEnable |
- ctrl->vfeStatsCmdLocal.axwEnable;
-
- vfe_reg_module_cfg(&ctrl->vfeModuleEnableLocal);
-
- /* in case of offline processing, do not need to config camif. Having
- * bus output enabled in camif_config register might confuse the
- * hardware?
- */
- if (in->inputSource != VFE_START_INPUT_SOURCE_AXI) {
- vfe_reg_camif_config(&ctrl->vfeCamifConfigLocal);
- } else {
- /* offline processing, enable axi read */
- ctrl->vfeBusConfigLocal.stripeRdPathEn = TRUE;
- ctrl->vfeBusCmdLocal.stripeReload = TRUE;
- ctrl->vfeBusConfigLocal.rawPixelDataSize =
- ctrl->axiInputDataSize;
- }
-
- vfe_reg_bus_cfg(&ctrl->vfeBusConfigLocal);
-
- /* directly from start command */
- hwcfg.pixelPattern = in->pixel;
- hwcfg.inputSource = in->inputSource;
- writel(*(uint32_t *)&hwcfg, ctrl->vfebase + VFE_CFG);
-
- /* regardless module enabled or not, it does not hurt
- * to program the cositing mode. */
- chromupcfg.chromaCositingForYCbCrInputs =
- in->yuvInputCositingMode;
-
- writel(*(uint32_t *)&(chromupcfg),
- ctrl->vfebase + VFE_CHROMA_UPSAMPLE_CFG);
-
- /* MISR to monitor the axi read. */
- writel(0xd8, ctrl->vfebase + VFE_BUS_MISR_MAST_CFG_0);
-
- /* clear all pending interrupts. */
- writel(VFE_CLEAR_ALL_IRQS, ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* define how composite interrupt work. */
- ctrl->vfeImaskCompositePacked =
- vfe_irq_composite_pack(ctrl->vfeIrqCompositeMaskLocal);
-
- vfe_program_irq_composite_mask(ctrl->vfeImaskCompositePacked);
-
- /* enable all necessary interrupts. */
- ctrl->vfeImaskLocal.camifSofIrq = TRUE;
- ctrl->vfeImaskLocal.regUpdateIrq = TRUE;
- ctrl->vfeImaskLocal.resetAckIrq = TRUE;
-
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
- vfe_program_irq_mask(ctrl->vfeImaskPacked);
-
- /* enable bus performance monitor */
- vfe_8k_pm_start(&ctrl->vfeBusPmConfigLocal);
-
- /* trigger vfe reg update */
- ctrl->vfeStartAckPendingFlag = TRUE;
-
- /* write bus command to trigger reload of ping pong buffer. */
- ctrl->vfeBusCmdLocal.busPingpongReload = TRUE;
-
- if (ctrl->vfeModuleEnableLocal.statsEnable == TRUE) {
- ctrl->vfeBusCmdLocal.statsPingpongReload = TRUE;
- ctrl->vfeStatsPingPongReloadFlag = TRUE;
- }
-
- writel(VFE_REG_UPDATE_TRIGGER,
- ctrl->vfebase + VFE_REG_UPDATE_CMD);
-
- /* program later than the reg update. */
- vfe_reg_bus_cmd(&ctrl->vfeBusCmdLocal);
-
- if ((in->inputSource ==
- VFE_START_INPUT_SOURCE_CAMIF) ||
- (in->inputSource ==
- VFE_START_INPUT_SOURCE_TESTGEN))
- writel(CAMIF_COMMAND_START, ctrl->vfebase + CAMIF_COMMAND);
-
- /* start test gen if it is enabled */
- if (ctrl->vfeTestGenStartFlag == TRUE) {
- ctrl->vfeTestGenStartFlag = FALSE;
- vfe_prog_hw_testgen_cmd(VFE_TEST_GEN_GO);
- }
-
- CDBG("ctrl->axiOutputMode = %d\n", ctrl->axiOutputMode);
- if (ctrl->axiOutputMode == VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2) {
- /* raw dump mode */
- rawmode = TRUE;
-
- while (rawmode) {
- pmstatus =
- readl(ctrl->vfebase +
- VFE_BUS_ENC_CBCR_WR_PM_STATS_1);
-
- if ((pmstatus & VFE_PM_BUF_MAX_CNT_MASK) != 0)
- rawmode = FALSE;
- }
-
- vfe_send_msg_no_payload(VFE_MSG_ID_START_ACK);
- ctrl->vfeStartAckPendingFlag = FALSE;
- }
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- ctrl->vstate = VFE_STATE_ACTIVE;
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-}
-
-void vfe_la_update(struct vfe_cmd_la_config *in)
-{
- int16_t *pTable;
- enum VFE_DMI_RAM_SEL dmiRamSel;
- int i;
-
- pTable = in->table;
- ctrl->vfeModuleEnableLocal.lumaAdaptationEnable = in->enable;
-
- /* toggle the bank to be used. */
- ctrl->vfeLaBankSel ^= 1;
-
- if (ctrl->vfeLaBankSel == 0)
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK0;
- else
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK1;
-
- /* configure the DMI_CFG to select right sram */
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_LA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, to make it safe, need to set
- * the DMI_CFG to unselect any SRAM */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
- writel(ctrl->vfeLaBankSel, ctrl->vfebase + VFE_LA_CFG);
-}
-
-void vfe_la_config(struct vfe_cmd_la_config *in)
-{
- uint16_t i;
- int16_t *pTable;
- enum VFE_DMI_RAM_SEL dmiRamSel;
-
- pTable = in->table;
- ctrl->vfeModuleEnableLocal.lumaAdaptationEnable = in->enable;
-
- if (ctrl->vfeLaBankSel == 0)
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK0;
- else
- dmiRamSel = LUMA_ADAPT_LUT_RAM_BANK1;
-
- /* configure the DMI_CFG to select right sram */
- vfe_program_dmi_cfg(dmiRamSel);
-
- for (i = 0; i < VFE_LA_TABLE_LENGTH; i++) {
- writel((uint32_t)(*pTable), ctrl->vfebase + VFE_DMI_DATA_LO);
- pTable++;
- }
-
- /* After DMI transfer, to make it safe, need to set the
- * DMI_CFG to unselect any SRAM */
- writel(VFE_DMI_CFG_DEFAULT, ctrl->vfebase + VFE_DMI_CFG);
-
- /* can only be bank 0 or bank 1 for now. */
- writel(ctrl->vfeLaBankSel, ctrl->vfebase + VFE_LA_CFG);
- CDBG("VFE Luma adaptation bank selection is 0x%x\n",
- *(uint32_t *)&ctrl->vfeLaBankSel);
-}
-
-void vfe_test_gen_start(struct vfe_cmd_test_gen_start *in)
-{
- struct VFE_TestGen_ConfigCmdType cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.numFrame = in->numFrame;
- cmd.pixelDataSelect = in->pixelDataSelect;
- cmd.systematicDataSelect = in->systematicDataSelect;
- cmd.pixelDataSize = (uint32_t)in->pixelDataSize;
- cmd.hsyncEdge = (uint32_t)in->hsyncEdge;
- cmd.vsyncEdge = (uint32_t)in->vsyncEdge;
- cmd.imageWidth = in->imageWidth;
- cmd.imageHeight = in->imageHeight;
- cmd.sofOffset = in->startOfFrameOffset;
- cmd.eofNOffset = in->endOfFrameNOffset;
- cmd.solOffset = in->startOfLineOffset;
- cmd.eolNOffset = in->endOfLineNOffset;
- cmd.hBlankInterval = in->hbi;
- cmd.vBlankInterval = in->vbl;
- cmd.vBlankIntervalEnable = in->vblEnable;
- cmd.sofDummy = in->startOfFrameDummyLine;
- cmd.eofDummy = in->endOfFrameDummyLine;
- cmd.unicolorBarSelect = in->unicolorBarSelect;
- cmd.unicolorBarEnable = in->unicolorBarEnable;
- cmd.splitEnable = in->colorBarsSplitEnable;
- cmd.pixelPattern = (uint32_t)in->colorBarsPixelPattern;
- cmd.rotatePeriod = in->colorBarsRotatePeriod;
- cmd.randomSeed = in->testGenRandomSeed;
-
- vfe_prog_hw(ctrl->vfebase + VFE_HW_TESTGEN_CFG,
- (uint32_t *) &cmd, sizeof(cmd));
-}
-
-void vfe_frame_skip_update(struct vfe_cmd_frame_skip_update *in)
-{
- struct VFE_FRAME_SKIP_UpdateCmdType cmd;
-
- cmd.yPattern = in->output1Pattern;
- cmd.cbcrPattern = in->output1Pattern;
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_VIEW_Y_PATTERN,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd.yPattern = in->output2Pattern;
- cmd.cbcrPattern = in->output2Pattern;
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_PATTERN,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_frame_skip_config(struct vfe_cmd_frame_skip_config *in)
-{
- struct vfe_frame_skip_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeFrameSkip = *in;
-
- cmd.output2YPeriod = in->output2Period;
- cmd.output2CbCrPeriod = in->output2Period;
- cmd.output2YPattern = in->output2Pattern;
- cmd.output2CbCrPattern = in->output2Pattern;
- cmd.output1YPeriod = in->output1Period;
- cmd.output1CbCrPeriod = in->output1Period;
- cmd.output1YPattern = in->output1Pattern;
- cmd.output1CbCrPattern = in->output1Pattern;
-
- vfe_prog_hw(ctrl->vfebase + VFE_FRAMEDROP_ENC_Y_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_output_clamp_config(struct vfe_cmd_output_clamp_config *in)
-{
- struct vfe_output_clamp_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.yChanMax = in->maxCh0;
- cmd.cbChanMax = in->maxCh1;
- cmd.crChanMax = in->maxCh2;
-
- cmd.yChanMin = in->minCh0;
- cmd.cbChanMin = in->minCh1;
- cmd.crChanMin = in->minCh2;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CLAMP_MAX_CFG, (uint32_t *)&cmd,
- sizeof(cmd));
-}
-
-void vfe_camif_frame_update(struct vfe_cmds_camif_frame *in)
-{
- struct vfe_camifframe_update cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.pixelsPerLine = in->pixelsPerLine;
- cmd.linesPerFrame = in->linesPerFrame;
-
- vfe_prog_hw(ctrl->vfebase + CAMIF_FRAME_CONFIG, (uint32_t *)&cmd,
- sizeof(cmd));
-}
-
-void vfe_color_correction_config(
- struct vfe_cmd_color_correction_config *in)
-{
- struct vfe_color_correction_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- ctrl->vfeModuleEnableLocal.colorCorrectionEnable = in->enable;
-
- cmd.c0 = in->C0;
- cmd.c1 = in->C1;
- cmd.c2 = in->C2;
- cmd.c3 = in->C3;
- cmd.c4 = in->C4;
- cmd.c5 = in->C5;
- cmd.c6 = in->C6;
- cmd.c7 = in->C7;
- cmd.c8 = in->C8;
-
- cmd.k0 = in->K0;
- cmd.k1 = in->K1;
- cmd.k2 = in->K2;
-
- cmd.coefQFactor = in->coefQFactor;
-
- vfe_prog_hw(ctrl->vfebase + VFE_COLOR_CORRECT_COEFF_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_demosaic_abf_update(struct vfe_cmd_demosaic_abf_update *in)
-{
-struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_abf_cfg cmdabf;
- uint32_t temp;
-
- memset(&cmd, 0, sizeof(cmd));
- temp = readl(ctrl->vfebase + VFE_DEMOSAIC_CFG);
-
- cmd = *((struct vfe_demosaic_cfg *)(&temp));
- cmd.abfEnable = in->abfUpdate.enable;
- cmd.forceAbfOn = in->abfUpdate.forceOn;
- cmd.abfShift = in->abfUpdate.shift;
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmdabf.lpThreshold = in->abfUpdate.lpThreshold;
- cmdabf.ratio = in->abfUpdate.ratio;
- cmdabf.minValue = in->abfUpdate.min;
- cmdabf.maxValue = in->abfUpdate.max;
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_ABF_CFG_0,
- (uint32_t *)&cmdabf, sizeof(cmdabf));
-}
-
-void vfe_demosaic_bpc_update(struct vfe_cmd_demosaic_bpc_update *in)
-{
- struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_bpc_cfg cmdbpc;
- uint32_t temp;
-
- memset(&cmd, 0, sizeof(cmd));
-
- temp = readl(ctrl->vfebase + VFE_DEMOSAIC_CFG);
-
- cmd = *((struct vfe_demosaic_cfg *)(&temp));
- cmd.badPixelCorrEnable = in->bpcUpdate.enable;
- cmd.fminThreshold = in->bpcUpdate.fminThreshold;
- cmd.fmaxThreshold = in->bpcUpdate.fmaxThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmdbpc.blueDiffThreshold = in->bpcUpdate.blueDiffThreshold;
- cmdbpc.redDiffThreshold = in->bpcUpdate.redDiffThreshold;
- cmdbpc.greenDiffThreshold = in->bpcUpdate.greenDiffThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_BPC_CFG_0,
- (uint32_t *)&cmdbpc, sizeof(cmdbpc));
-}
-
-void vfe_demosaic_config(struct vfe_cmd_demosaic_config *in)
-{
- struct vfe_demosaic_cfg cmd;
- struct vfe_demosaic_bpc_cfg cmd_bpc;
- struct vfe_demosaic_abf_cfg cmd_abf;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd_bpc, 0, sizeof(cmd_bpc));
- memset(&cmd_abf, 0, sizeof(cmd_abf));
-
- ctrl->vfeModuleEnableLocal.demosaicEnable = in->enable;
-
- cmd.abfEnable = in->abfConfig.enable;
- cmd.badPixelCorrEnable = in->bpcConfig.enable;
- cmd.forceAbfOn = in->abfConfig.forceOn;
- cmd.abfShift = in->abfConfig.shift;
- cmd.fminThreshold = in->bpcConfig.fminThreshold;
- cmd.fmaxThreshold = in->bpcConfig.fmaxThreshold;
- cmd.slopeShift = in->slopeShift;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd_abf.lpThreshold = in->abfConfig.lpThreshold;
- cmd_abf.ratio = in->abfConfig.ratio;
- cmd_abf.minValue = in->abfConfig.min;
- cmd_abf.maxValue = in->abfConfig.max;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_ABF_CFG_0,
- (uint32_t *)&cmd_abf, sizeof(cmd_abf));
-
- cmd_bpc.blueDiffThreshold = in->bpcConfig.blueDiffThreshold;
- cmd_bpc.redDiffThreshold = in->bpcConfig.redDiffThreshold;
- cmd_bpc.greenDiffThreshold = in->bpcConfig.greenDiffThreshold;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMOSAIC_BPC_CFG_0,
- (uint32_t *)&cmd_bpc, sizeof(cmd_bpc));
-}
-
-void vfe_demux_channel_gain_update(
- struct vfe_cmd_demux_channel_gain_config *in)
-{
- struct vfe_demux_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0EvenGain = in->ch0EvenGain;
- cmd.ch0OddGain = in->ch0OddGain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMUX_GAIN_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_demux_channel_gain_config(
- struct vfe_cmd_demux_channel_gain_config *in)
-{
- struct vfe_demux_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.ch0EvenGain = in->ch0EvenGain;
- cmd.ch0OddGain = in->ch0OddGain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_DEMUX_GAIN_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_black_level_update(struct vfe_cmd_black_level_config *in)
-{
- struct vfe_blacklevel_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- ctrl->vfeModuleEnableLocal.blackLevelCorrectionEnable = in->enable;
-
- cmd.evenEvenAdjustment = in->evenEvenAdjustment;
- cmd.evenOddAdjustment = in->evenOddAdjustment;
- cmd.oddEvenAdjustment = in->oddEvenAdjustment;
- cmd.oddOddAdjustment = in->oddOddAdjustment;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BLACK_EVEN_EVEN_VALUE,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_black_level_config(struct vfe_cmd_black_level_config *in)
-{
- struct vfe_blacklevel_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.blackLevelCorrectionEnable = in->enable;
-
- cmd.evenEvenAdjustment = in->evenEvenAdjustment;
- cmd.evenOddAdjustment = in->evenOddAdjustment;
- cmd.oddEvenAdjustment = in->oddEvenAdjustment;
- cmd.oddOddAdjustment = in->oddOddAdjustment;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BLACK_EVEN_EVEN_VALUE,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_asf_update(struct vfe_cmd_asf_update *in)
-{
- struct vfe_asf_update cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.asfEnable = in->enable;
-
- cmd.smoothEnable = in->smoothFilterEnabled;
- cmd.sharpMode = in->sharpMode;
- cmd.smoothCoeff1 = in->smoothCoefCenter;
- cmd.smoothCoeff0 = in->smoothCoefSurr;
- cmd.cropEnable = in->cropEnable;
- cmd.sharpThresholdE1 = in->sharpThreshE1;
- cmd.sharpDegreeK1 = in->sharpK1;
- cmd.sharpDegreeK2 = in->sharpK2;
- cmd.normalizeFactor = in->normalizeFactor;
- cmd.sharpThresholdE2 = in->sharpThreshE2;
- cmd.sharpThresholdE3 = in->sharpThreshE3;
- cmd.sharpThresholdE4 = in->sharpThreshE4;
- cmd.sharpThresholdE5 = in->sharpThreshE5;
- cmd.F1Coeff0 = in->filter1Coefficients[0];
- cmd.F1Coeff1 = in->filter1Coefficients[1];
- cmd.F1Coeff2 = in->filter1Coefficients[2];
- cmd.F1Coeff3 = in->filter1Coefficients[3];
- cmd.F1Coeff4 = in->filter1Coefficients[4];
- cmd.F1Coeff5 = in->filter1Coefficients[5];
- cmd.F1Coeff6 = in->filter1Coefficients[6];
- cmd.F1Coeff7 = in->filter1Coefficients[7];
- cmd.F1Coeff8 = in->filter1Coefficients[8];
- cmd.F2Coeff0 = in->filter2Coefficients[0];
- cmd.F2Coeff1 = in->filter2Coefficients[1];
- cmd.F2Coeff2 = in->filter2Coefficients[2];
- cmd.F2Coeff3 = in->filter2Coefficients[3];
- cmd.F2Coeff4 = in->filter2Coefficients[4];
- cmd.F2Coeff5 = in->filter2Coefficients[5];
- cmd.F2Coeff6 = in->filter2Coefficients[6];
- cmd.F2Coeff7 = in->filter2Coefficients[7];
- cmd.F2Coeff8 = in->filter2Coefficients[8];
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_asf_config(struct vfe_cmd_asf_config *in)
-{
- struct vfe_asf_update cmd;
- struct vfe_asfcrop_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->vfeModuleEnableLocal.asfEnable = in->enable;
-
- cmd.smoothEnable = in->smoothFilterEnabled;
- cmd.sharpMode = in->sharpMode;
- cmd.smoothCoeff0 = in->smoothCoefCenter;
- cmd.smoothCoeff1 = in->smoothCoefSurr;
- cmd.cropEnable = in->cropEnable;
- cmd.sharpThresholdE1 = in->sharpThreshE1;
- cmd.sharpDegreeK1 = in->sharpK1;
- cmd.sharpDegreeK2 = in->sharpK2;
- cmd.normalizeFactor = in->normalizeFactor;
- cmd.sharpThresholdE2 = in->sharpThreshE2;
- cmd.sharpThresholdE3 = in->sharpThreshE3;
- cmd.sharpThresholdE4 = in->sharpThreshE4;
- cmd.sharpThresholdE5 = in->sharpThreshE5;
- cmd.F1Coeff0 = in->filter1Coefficients[0];
- cmd.F1Coeff1 = in->filter1Coefficients[1];
- cmd.F1Coeff2 = in->filter1Coefficients[2];
- cmd.F1Coeff3 = in->filter1Coefficients[3];
- cmd.F1Coeff4 = in->filter1Coefficients[4];
- cmd.F1Coeff5 = in->filter1Coefficients[5];
- cmd.F1Coeff6 = in->filter1Coefficients[6];
- cmd.F1Coeff7 = in->filter1Coefficients[7];
- cmd.F1Coeff8 = in->filter1Coefficients[8];
- cmd.F2Coeff0 = in->filter2Coefficients[0];
- cmd.F2Coeff1 = in->filter2Coefficients[1];
- cmd.F2Coeff2 = in->filter2Coefficients[2];
- cmd.F2Coeff3 = in->filter2Coefficients[3];
- cmd.F2Coeff4 = in->filter2Coefficients[4];
- cmd.F2Coeff5 = in->filter2Coefficients[5];
- cmd.F2Coeff6 = in->filter2Coefficients[6];
- cmd.F2Coeff7 = in->filter2Coefficients[7];
- cmd.F2Coeff8 = in->filter2Coefficients[8];
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.firstLine = in->cropFirstLine;
- cmd2.lastLine = in->cropLastLine;
- cmd2.firstPixel = in->cropFirstPixel;
- cmd2.lastPixel = in->cropLastPixel;
-
- vfe_prog_hw(ctrl->vfebase + VFE_ASF_CROP_WIDTH_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_white_balance_config(struct vfe_cmd_white_balance_config *in)
-{
- struct vfe_wb_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.whiteBalanceEnable =
- in->enable;
-
- cmd.ch0Gain = in->ch0Gain;
- cmd.ch1Gain = in->ch1Gain;
- cmd.ch2Gain = in->ch2Gain;
-
- vfe_prog_hw(ctrl->vfebase + VFE_WB_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_chroma_sup_config(struct vfe_cmd_chroma_suppression_config *in)
-{
- struct vfe_chroma_suppress_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.chromaSuppressionEnable = in->enable;
-
- cmd.m1 = in->m1;
- cmd.m3 = in->m3;
- cmd.n1 = in->n1;
- cmd.n3 = in->n3;
- cmd.mm1 = in->mm1;
- cmd.nn1 = in->nn1;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_SUPPRESS_CFG_0,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_roll_off_config(struct vfe_cmd_roll_off_config *in)
-{
- struct vfe_rolloff_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.lensRollOffEnable = in->enable;
-
- cmd.gridWidth = in->gridWidth;
- cmd.gridHeight = in->gridHeight;
- cmd.yDelta = in->yDelta;
- cmd.gridX = in->gridXIndex;
- cmd.gridY = in->gridYIndex;
- cmd.pixelX = in->gridPixelXIndex;
- cmd.pixelY = in->gridPixelYIndex;
- cmd.yDeltaAccum = in->yDeltaAccum;
-
- vfe_prog_hw(ctrl->vfebase + VFE_ROLLOFF_CFG_0,
- (uint32_t *)&cmd, sizeof(cmd));
-
- vfe_write_lens_roll_off_table(in);
-}
-
-void vfe_chroma_subsample_config(
- struct vfe_cmd_chroma_subsample_config *in)
-{
- struct vfe_chromasubsample_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.chromaSubsampleEnable = in->enable;
-
- cmd.hCositedPhase = in->hCositedPhase;
- cmd.vCositedPhase = in->vCositedPhase;
- cmd.hCosited = in->hCosited;
- cmd.vCosited = in->vCosited;
- cmd.hsubSampleEnable = in->hsubSampleEnable;
- cmd.vsubSampleEnable = in->vsubSampleEnable;
- cmd.cropEnable = in->cropEnable;
- cmd.cropWidthLastPixel = in->cropWidthLastPixel;
- cmd.cropWidthFirstPixel = in->cropWidthFirstPixel;
- cmd.cropHeightLastLine = in->cropHeightLastLine;
- cmd.cropHeightFirstLine = in->cropHeightFirstLine;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_SUBSAMPLE_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_chroma_enhan_config(struct vfe_cmd_chroma_enhan_config *in)
-{
- struct vfe_chroma_enhance_cfg cmd;
- struct vfe_color_convert_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->vfeModuleEnableLocal.chromaEnhanEnable = in->enable;
-
- cmd.ap = in->ap;
- cmd.am = in->am;
- cmd.bp = in->bp;
- cmd.bm = in->bm;
- cmd.cp = in->cp;
- cmd.cm = in->cm;
- cmd.dp = in->dp;
- cmd.dm = in->dm;
- cmd.kcb = in->kcb;
- cmd.kcr = in->kcr;
-
- cmd2.v0 = in->RGBtoYConversionV0;
- cmd2.v1 = in->RGBtoYConversionV1;
- cmd2.v2 = in->RGBtoYConversionV2;
- cmd2.ConvertOffset = in->RGBtoYConversionOffset;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CHROMA_ENHAN_A,
- (uint32_t *)&cmd, sizeof(cmd));
-
- vfe_prog_hw(ctrl->vfebase + VFE_COLOR_CONVERT_COEFF_0,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_scaler2cbcr_config(struct vfe_cmd_scaler2_config *in)
-{
- struct vfe_scaler2_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.scaler2CbcrEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_CBCR_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_scaler2y_config(struct vfe_cmd_scaler2_config *in)
-{
- struct vfe_scaler2_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.scaler2YEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_Y_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_main_scaler_config(struct vfe_cmd_main_scaler_config *in)
-{
- struct vfe_main_scaler_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.mainScalerEnable = in->enable;
-
- cmd.hEnable = in->hconfig.enable;
- cmd.vEnable = in->vconfig.enable;
- cmd.inWidth = in->hconfig.inputSize;
- cmd.outWidth = in->hconfig.outputSize;
- cmd.horizPhaseMult = in->hconfig.phaseMultiplicationFactor;
- cmd.horizInterResolution = in->hconfig.interpolationResolution;
- cmd.horizMNInit = in->MNInitH.MNCounterInit;
- cmd.horizPhaseInit = in->MNInitH.phaseInit;
- cmd.inHeight = in->vconfig.inputSize;
- cmd.outHeight = in->vconfig.outputSize;
- cmd.vertPhaseMult = in->vconfig.phaseMultiplicationFactor;
- cmd.vertInterResolution = in->vconfig.interpolationResolution;
- cmd.vertMNInit = in->MNInitV.MNCounterInit;
- cmd.vertPhaseInit = in->MNInitV.phaseInit;
-
- vfe_prog_hw(ctrl->vfebase + VFE_SCALE_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_stats_wb_exp_stop(void)
-{
- ctrl->vfeStatsCmdLocal.axwEnable = FALSE;
- ctrl->vfeImaskLocal.awbPingpongIrq = FALSE;
-}
-
-void vfe_stats_update_wb_exp(struct vfe_cmd_stats_wb_exp_update *in)
-{
- struct vfe_statsawb_update cmd;
- struct vfe_statsawbae_update cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
- cmd.m1 = in->awbMCFG[0];
- cmd.m2 = in->awbMCFG[1];
- cmd.m3 = in->awbMCFG[2];
- cmd.m4 = in->awbMCFG[3];
- cmd.c1 = in->awbCCFG[0];
- cmd.c2 = in->awbCCFG[1];
- cmd.c3 = in->awbCCFG[2];
- cmd.c4 = in->awbCCFG[3];
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWB_MCFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.aeRegionCfg = in->wbExpRegions;
- cmd2.aeSubregionCfg = in->wbExpSubRegion;
- cmd2.awbYMin = in->awbYMin;
- cmd2.awbYMax = in->awbYMax;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWBAE_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_stats_update_af(struct vfe_cmd_stats_af_update *in)
-{
- struct vfe_statsaf_update cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- cmd.windowVOffset = in->windowVOffset;
- cmd.windowHOffset = in->windowHOffset;
- cmd.windowMode = in->windowMode;
- cmd.windowHeight = in->windowHeight;
- cmd.windowWidth = in->windowWidth;
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_stats_start_wb_exp(struct vfe_cmd_stats_wb_exp_start *in)
-{
- struct vfe_statsawb_update cmd;
- struct vfe_statsawbae_update cmd2;
- struct vfe_statsaxw_hdr_cfg cmd3;
-
- ctrl->vfeStatsCmdLocal.axwEnable = in->enable;
- ctrl->vfeImaskLocal.awbPingpongIrq = TRUE;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
- memset(&cmd3, 0, sizeof(cmd3));
-
- cmd.m1 = in->awbMCFG[0];
- cmd.m2 = in->awbMCFG[1];
- cmd.m3 = in->awbMCFG[2];
- cmd.m4 = in->awbMCFG[3];
- cmd.c1 = in->awbCCFG[0];
- cmd.c2 = in->awbCCFG[1];
- cmd.c3 = in->awbCCFG[2];
- cmd.c4 = in->awbCCFG[3];
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWB_MCFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.aeRegionCfg = in->wbExpRegions;
- cmd2.aeSubregionCfg = in->wbExpSubRegion;
- cmd2.awbYMin = in->awbYMin;
- cmd2.awbYMax = in->awbYMax;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AWBAE_CFG,
- (uint32_t *)&cmd2, sizeof(cmd2));
-
- cmd3.axwHeader = in->axwHeader;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AXW_HEADER,
- (uint32_t *)&cmd3, sizeof(cmd3));
-}
-
-void vfe_stats_start_af(struct vfe_cmd_stats_af_start *in)
-{
- struct vfe_statsaf_update cmd;
- struct vfe_statsaf_cfg cmd2;
-
- memset(&cmd, 0, sizeof(cmd));
- memset(&cmd2, 0, sizeof(cmd2));
-
-ctrl->vfeStatsCmdLocal.autoFocusEnable = in->enable;
-ctrl->vfeImaskLocal.afPingpongIrq = TRUE;
-
- cmd.windowVOffset = in->windowVOffset;
- cmd.windowHOffset = in->windowHOffset;
- cmd.windowMode = in->windowMode;
- cmd.windowHeight = in->windowHeight;
- cmd.windowWidth = in->windowWidth;
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-
- cmd2.a00 = in->highPassCoef[0];
- cmd2.a04 = in->highPassCoef[1];
- cmd2.a20 = in->highPassCoef[2];
- cmd2.a21 = in->highPassCoef[3];
- cmd2.a22 = in->highPassCoef[4];
- cmd2.a23 = in->highPassCoef[5];
- cmd2.a24 = in->highPassCoef[6];
- cmd2.fvMax = in->metricMax;
- cmd2.fvMetric = in->metricSelection;
- cmd2.afHeader = in->bufferHeader;
- cmd2.entry00 = in->gridForMultiWindows[0];
- cmd2.entry01 = in->gridForMultiWindows[1];
- cmd2.entry02 = in->gridForMultiWindows[2];
- cmd2.entry03 = in->gridForMultiWindows[3];
- cmd2.entry10 = in->gridForMultiWindows[4];
- cmd2.entry11 = in->gridForMultiWindows[5];
- cmd2.entry12 = in->gridForMultiWindows[6];
- cmd2.entry13 = in->gridForMultiWindows[7];
- cmd2.entry20 = in->gridForMultiWindows[8];
- cmd2.entry21 = in->gridForMultiWindows[9];
- cmd2.entry22 = in->gridForMultiWindows[10];
- cmd2.entry23 = in->gridForMultiWindows[11];
- cmd2.entry30 = in->gridForMultiWindows[12];
- cmd2.entry31 = in->gridForMultiWindows[13];
- cmd2.entry32 = in->gridForMultiWindows[14];
- cmd2.entry33 = in->gridForMultiWindows[15];
-
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_AF_GRID_0,
- (uint32_t *)&cmd2, sizeof(cmd2));
-}
-
-void vfe_stats_setting(struct vfe_cmd_stats_setting *in)
-{
- struct vfe_statsframe cmd1;
- struct vfe_busstats_wrprio cmd2;
-
- memset(&cmd1, 0, sizeof(cmd1));
- memset(&cmd2, 0, sizeof(cmd2));
-
- ctrl->afStatsControl.addressBuffer[0] = in->afBuffer[0];
- ctrl->afStatsControl.addressBuffer[1] = in->afBuffer[1];
- ctrl->afStatsControl.nextFrameAddrBuf = in->afBuffer[2];
-
- ctrl->awbStatsControl.addressBuffer[0] = in->awbBuffer[0];
- ctrl->awbStatsControl.addressBuffer[1] = in->awbBuffer[1];
- ctrl->awbStatsControl.nextFrameAddrBuf = in->awbBuffer[2];
-
- cmd1.lastPixel = in->frameHDimension;
- cmd1.lastLine = in->frameVDimension;
- vfe_prog_hw(ctrl->vfebase + VFE_STATS_FRAME_SIZE,
- (uint32_t *)&cmd1, sizeof(cmd1));
-
- cmd2.afBusPriority = in->afBusPriority;
- cmd2.awbBusPriority = in->awbBusPriority;
- cmd2.histBusPriority = in->histBusPriority;
- cmd2.afBusPriorityEn = in->afBusPrioritySelection;
- cmd2.awbBusPriorityEn = in->awbBusPrioritySelection;
- cmd2.histBusPriorityEn = in->histBusPrioritySelection;
-
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_STATS_WR_PRIORITY,
- (uint32_t *)&cmd2, sizeof(cmd2));
-
- /* Program the bus ping pong address for statistics modules. */
- writel(in->afBuffer[0], ctrl->vfebase + VFE_BUS_STATS_AF_WR_PING_ADDR);
- writel(in->afBuffer[1], ctrl->vfebase + VFE_BUS_STATS_AF_WR_PONG_ADDR);
- writel(in->awbBuffer[0],
- ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PING_ADDR);
- writel(in->awbBuffer[1],
- ctrl->vfebase + VFE_BUS_STATS_AWB_WR_PONG_ADDR);
- writel(in->histBuffer[0],
- ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PING_ADDR);
- writel(in->histBuffer[1],
- ctrl->vfebase + VFE_BUS_STATS_HIST_WR_PONG_ADDR);
-}
-
-void vfe_axi_input_config(struct vfe_cmd_axi_input_config *in)
-{
- struct VFE_AxiInputCmdType cmd;
- uint32_t xSizeWord, axiRdUnpackPattern;
- uint8_t axiInputPpw;
- uint32_t busPingpongRdIrqEnable;
-
- ctrl->vfeImaskLocal.rdPingpongIrq = TRUE;
-
- switch (in->pixelSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_10BIT;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_12BIT;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- default:
- ctrl->axiInputDataSize = VFE_RAW_PIXEL_DATA_SIZE_8BIT;
- break;
- }
-
- memset(&cmd, 0, sizeof(cmd));
-
- switch (in->pixelSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- axiInputPpw = 6;
- axiRdUnpackPattern = 0xD43210;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- axiInputPpw = 5;
- axiRdUnpackPattern = 0xC3210;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- default:
- axiInputPpw = 8;
- axiRdUnpackPattern = 0xF6543210;
- break;
- }
-
- xSizeWord =
- ((((in->xOffset % axiInputPpw) + in->xSize) +
- (axiInputPpw-1)) / axiInputPpw) - 1;
-
- cmd.stripeStartAddr0 = in->fragAddr[0];
- cmd.stripeStartAddr1 = in->fragAddr[1];
- cmd.stripeStartAddr2 = in->fragAddr[2];
- cmd.stripeStartAddr3 = in->fragAddr[3];
- cmd.ySize = in->ySize;
- cmd.yOffsetDelta = 0;
- cmd.xSizeWord = xSizeWord;
- cmd.burstLength = 1;
- cmd.NumOfRows = in->numOfRows;
- cmd.RowIncrement =
- (in->rowIncrement + (axiInputPpw-1))/axiInputPpw;
- cmd.mainUnpackHeight = in->ySize;
- cmd.mainUnpackWidth = in->xSize - 1;
- cmd.mainUnpackHbiSel = (uint32_t)in->unpackHbi;
- cmd.mainUnpackPhase = in->unpackPhase;
- cmd.unpackPattern = axiRdUnpackPattern;
- cmd.padLeft = in->padRepeatCountLeft;
- cmd.padRight = in->padRepeatCountRight;
- cmd.padTop = in->padRepeatCountTop;
- cmd.padBottom = in->padRepeatCountBottom;
- cmd.leftUnpackPattern0 = in->padLeftComponentSelectCycle0;
- cmd.leftUnpackPattern1 = in->padLeftComponentSelectCycle1;
- cmd.leftUnpackPattern2 = in->padLeftComponentSelectCycle2;
- cmd.leftUnpackPattern3 = in->padLeftComponentSelectCycle3;
- cmd.leftUnpackStop0 = in->padLeftStopCycle0;
- cmd.leftUnpackStop1 = in->padLeftStopCycle1;
- cmd.leftUnpackStop2 = in->padLeftStopCycle2;
- cmd.leftUnpackStop3 = in->padLeftStopCycle3;
- cmd.rightUnpackPattern0 = in->padRightComponentSelectCycle0;
- cmd.rightUnpackPattern1 = in->padRightComponentSelectCycle1;
- cmd.rightUnpackPattern2 = in->padRightComponentSelectCycle2;
- cmd.rightUnpackPattern3 = in->padRightComponentSelectCycle3;
- cmd.rightUnpackStop0 = in->padRightStopCycle0;
- cmd.rightUnpackStop1 = in->padRightStopCycle1;
- cmd.rightUnpackStop2 = in->padRightStopCycle2;
- cmd.rightUnpackStop3 = in->padRightStopCycle3;
- cmd.topUnapckPattern = in->padTopLineCount;
- cmd.bottomUnapckPattern = in->padBottomLineCount;
-
- /* program vfe_bus_cfg */
- vfe_prog_hw(ctrl->vfebase + VFE_BUS_STRIPE_RD_ADDR_0,
- (uint32_t *)&cmd, sizeof(cmd));
-
- /* hacking code, put it to default value */
- busPingpongRdIrqEnable = 0xf;
-
- writel(busPingpongRdIrqEnable,
- ctrl->vfebase + VFE_BUS_PINGPONG_IRQ_EN);
-}
-
-void vfe_stats_config(struct vfe_cmd_stats_setting *in)
-{
- ctrl->afStatsControl.addressBuffer[0] = in->afBuffer[0];
- ctrl->afStatsControl.addressBuffer[1] = in->afBuffer[1];
- ctrl->afStatsControl.nextFrameAddrBuf = in->afBuffer[2];
-
- ctrl->awbStatsControl.addressBuffer[0] = in->awbBuffer[0];
- ctrl->awbStatsControl.addressBuffer[1] = in->awbBuffer[1];
- ctrl->awbStatsControl.nextFrameAddrBuf = in->awbBuffer[2];
-
- vfe_stats_setting(in);
-}
-
-void vfe_axi_output_config(
- struct vfe_cmd_axi_output_config *in)
-{
- /* local variable */
- uint32_t *pcircle;
- uint32_t *pdest;
- uint32_t *psrc;
- uint8_t i;
- uint8_t fcnt;
- uint16_t axioutpw = 8;
-
- /* parameters check, condition and usage mode check */
- ctrl->encPath.fragCount = in->output2.fragmentCount;
- if (ctrl->encPath.fragCount > 1)
- ctrl->encPath.multiFrag = TRUE;
-
- ctrl->viewPath.fragCount = in->output1.fragmentCount;
- if (ctrl->viewPath.fragCount > 1)
- ctrl->viewPath.multiFrag = TRUE;
-
- /* VFE_BUS_CFG. raw data size */
- ctrl->vfeBusConfigLocal.rawPixelDataSize = in->outputDataSize;
-
- switch (in->outputDataSize) {
- case VFE_RAW_PIXEL_DATA_SIZE_8BIT:
- axioutpw = 8;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_10BIT:
- axioutpw = 6;
- break;
-
- case VFE_RAW_PIXEL_DATA_SIZE_12BIT:
- axioutpw = 5;
- break;
- }
-
- ctrl->axiOutputMode = in->outputMode;
-
- CDBG("axiOutputMode = %d\n", ctrl->axiOutputMode);
-
- switch (ctrl->axiOutputMode) {
- case VFE_AXI_OUTPUT_MODE_Output1: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.encIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = FALSE;
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.viewIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = FALSE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output1AndOutput2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = FALSE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_DISABLED;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1AndOutput2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2: {
- /* For raw snapshot, we need both ping and pong buffer
- * initialized to the same address. Otherwise, if we
- * leave the pong buffer to NULL, there will be axi_error.
- * Note that ideally we should deal with this at upper layer,
- * which is in msm_vfe8x.c */
- if (!in->output2.outputCbcr.outFragments[1][0]) {
- in->output2.outputCbcr.outFragments[1][0] =
- in->output2.outputCbcr.outFragments[0][0];
- }
-
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = FALSE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_ENC_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = FALSE;
- ctrl->vfeImaskLocal.viewIrq = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = FALSE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_CAMIFToAXIViaOutput2 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_VIEW_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output2AndCAMIFToAXIViaOutput1 */
- break;
-
- case VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2: {
- ctrl->vfeCamifConfigLocal.camif2BusEnable = TRUE;
- ctrl->vfeCamifConfigLocal.camif2OutputEnable = TRUE;
- ctrl->vfeBusConfigLocal.rawWritePathSelect =
- VFE_RAW_OUTPUT_ENC_CBCR_PATH;
-
- ctrl->encPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.encIrq = TRUE;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_CBCR_ONLY;
-
- ctrl->vfeBusConfigLocal.encYWrPathEn = FALSE;
- ctrl->vfeBusConfigLocal.encCbcrWrPathEn = TRUE;
-
- ctrl->viewPath.pathEnabled = TRUE;
- ctrl->vfeImaskLocal.viewIrq = TRUE;
-
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- ctrl->vfeBusConfigLocal.viewYWrPathEn = TRUE;
- ctrl->vfeBusConfigLocal.viewCbcrWrPathEn = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encYWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.encCbcrWrPathEn &&
- ctrl->encPath.multiFrag)
- ctrl->vfeImaskLocal.encCbcrPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewYWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewYPingpongIrq = TRUE;
-
- if (ctrl->vfeBusConfigLocal.viewCbcrWrPathEn &&
- ctrl->viewPath.multiFrag)
- ctrl->vfeImaskLocal.viewCbcrPingpongIrq = TRUE;
- } /* VFE_AXI_OUTPUT_MODE_Output1AndCAMIFToAXIViaOutput2 */
- break;
-
- case VFE_AXI_LAST_OUTPUT_MODE_ENUM:
- break;
- } /* switch */
-
- /* Save the addresses for each path. */
- /* output2 path */
- fcnt = ctrl->encPath.fragCount;
-
- pcircle = ctrl->encPath.yPath.addressBuffer;
- pdest = ctrl->encPath.nextFrameAddrBuf;
-
- psrc = &(in->output2.outputY.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputY.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputY.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- pcircle = ctrl->encPath.cbcrPath.addressBuffer;
-
- psrc = &(in->output2.outputCbcr.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputCbcr.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output2.outputCbcr.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- vfe_set_bus_pipo_addr(&ctrl->viewPath, &ctrl->encPath);
-
- ctrl->encPath.ackPending = FALSE;
- ctrl->encPath.currentFrame = ping;
- ctrl->encPath.whichOutputPath = 1;
- ctrl->encPath.yPath.fragIndex = 2;
- ctrl->encPath.cbcrPath.fragIndex = 2;
- ctrl->encPath.yPath.hwCurrentFlag = ping;
- ctrl->encPath.cbcrPath.hwCurrentFlag = ping;
-
- /* output1 path */
- pcircle = ctrl->viewPath.yPath.addressBuffer;
- pdest = ctrl->viewPath.nextFrameAddrBuf;
- fcnt = ctrl->viewPath.fragCount;
-
- psrc = &(in->output1.outputY.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputY.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputY.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- pcircle = ctrl->viewPath.cbcrPath.addressBuffer;
-
- psrc = &(in->output1.outputCbcr.outFragments[0][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputCbcr.outFragments[1][0]);
- for (i = 0; i < fcnt; i++)
- *pcircle++ = *psrc++;
-
- psrc = &(in->output1.outputCbcr.outFragments[2][0]);
- for (i = 0; i < fcnt; i++)
- *pdest++ = *psrc++;
-
- ctrl->viewPath.ackPending = FALSE;
- ctrl->viewPath.currentFrame = ping;
- ctrl->viewPath.whichOutputPath = 0;
- ctrl->viewPath.yPath.fragIndex = 2;
- ctrl->viewPath.cbcrPath.fragIndex = 2;
- ctrl->viewPath.yPath.hwCurrentFlag = ping;
- ctrl->viewPath.cbcrPath.hwCurrentFlag = ping;
-
- /* call to program the registers. */
- vfe_axi_output(in, &ctrl->viewPath, &ctrl->encPath, axioutpw);
-}
-
-void vfe_camif_config(struct vfe_cmd_camif_config *in)
-{
- struct vfe_camifcfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- CDBG("camif.frame pixelsPerLine = %d\n", in->frame.pixelsPerLine);
- CDBG("camif.frame linesPerFrame = %d\n", in->frame.linesPerFrame);
- CDBG("camif.window firstpixel = %d\n", in->window.firstpixel);
- CDBG("camif.window lastpixel = %d\n", in->window.lastpixel);
- CDBG("camif.window firstline = %d\n", in->window.firstline);
- CDBG("camif.window lastline = %d\n", in->window.lastline);
-
- /* determine if epoch interrupt needs to be enabled. */
- if ((in->epoch1.enable == TRUE) &&
- (in->epoch1.lineindex <=
- in->frame.linesPerFrame))
- ctrl->vfeImaskLocal.camifEpoch1Irq = 1;
-
- if ((in->epoch2.enable == TRUE) &&
- (in->epoch2.lineindex <=
- in->frame.linesPerFrame)) {
- ctrl->vfeImaskLocal.camifEpoch2Irq = 1;
- }
-
- /* save the content to program CAMIF_CONFIG separately. */
- ctrl->vfeCamifConfigLocal.camifCfgFromCmd = in->camifConfig;
-
- /* EFS_Config */
- cmd.efsEndOfLine = in->EFS.efsendofline;
- cmd.efsStartOfLine = in->EFS.efsstartofline;
- cmd.efsEndOfFrame = in->EFS.efsendofframe;
- cmd.efsStartOfFrame = in->EFS.efsstartofframe;
-
- /* Frame Config */
- cmd.frameConfigPixelsPerLine = in->frame.pixelsPerLine;
- cmd.frameConfigLinesPerFrame = in->frame.linesPerFrame;
-
- /* Window Width Config */
- cmd.windowWidthCfgLastPixel = in->window.lastpixel;
- cmd.windowWidthCfgFirstPixel = in->window.firstpixel;
-
- /* Window Height Config */
- cmd.windowHeightCfglastLine = in->window.lastline;
- cmd.windowHeightCfgfirstLine = in->window.firstline;
-
- /* Subsample 1 Config */
- cmd.subsample1CfgPixelSkip = in->subsample.pixelskipmask;
- cmd.subsample1CfgLineSkip = in->subsample.lineskipmask;
-
- /* Subsample 2 Config */
- cmd.subsample2CfgFrameSkip = in->subsample.frameskip;
- cmd.subsample2CfgFrameSkipMode = in->subsample.frameskipmode;
- cmd.subsample2CfgPixelSkipWrap = in->subsample.pixelskipwrap;
-
- /* Epoch Interrupt */
- cmd.epoch1Line = in->epoch1.lineindex;
- cmd.epoch2Line = in->epoch2.lineindex;
-
- vfe_prog_hw(ctrl->vfebase + CAMIF_EFS_CONFIG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_fov_crop_config(struct vfe_cmd_fov_crop_config *in)
-{
- struct vfe_fov_crop_cfg cmd;
- memset(&cmd, 0, sizeof(cmd));
-
- ctrl->vfeModuleEnableLocal.cropEnable = in->enable;
-
- /* FOV Corp, Part 1 */
- cmd.lastPixel = in->lastPixel;
- cmd.firstPixel = in->firstPixel;
-
- /* FOV Corp, Part 2 */
- cmd.lastLine = in->lastLine;
- cmd.firstLine = in->firstLine;
-
- vfe_prog_hw(ctrl->vfebase + VFE_CROP_WIDTH_CFG,
- (uint32_t *)&cmd, sizeof(cmd));
-}
-
-void vfe_get_hw_version(struct vfe_cmd_hw_version *out)
-{
- uint32_t vfeHwVersionPacked;
- struct vfe_hw_ver ver;
-
- vfeHwVersionPacked = readl(ctrl->vfebase + VFE_HW_VERSION);
-
- ver = *((struct vfe_hw_ver *)&vfeHwVersionPacked);
-
- out->coreVersion = ver.coreVersion;
- out->minorVersion = ver.minorVersion;
- out->majorVersion = ver.majorVersion;
-}
-
-static void vfe_reset_internal_variables(void)
-{
- unsigned long flags;
-
- /* local variables to program the hardware. */
- ctrl->vfeImaskPacked = 0;
- ctrl->vfeImaskCompositePacked = 0;
-
- /* FALSE = disable, 1 = enable. */
- memset(&ctrl->vfeModuleEnableLocal, 0,
- sizeof(ctrl->vfeModuleEnableLocal));
-
- /* 0 = disable, 1 = enable */
- memset(&ctrl->vfeCamifConfigLocal, 0,
- sizeof(ctrl->vfeCamifConfigLocal));
- /* 0 = disable, 1 = enable */
- memset(&ctrl->vfeImaskLocal, 0, sizeof(ctrl->vfeImaskLocal));
- memset(&ctrl->vfeStatsCmdLocal, 0, sizeof(ctrl->vfeStatsCmdLocal));
- memset(&ctrl->vfeBusConfigLocal, 0, sizeof(ctrl->vfeBusConfigLocal));
- memset(&ctrl->vfeBusPmConfigLocal, 0,
- sizeof(ctrl->vfeBusPmConfigLocal));
- memset(&ctrl->vfeBusCmdLocal, 0, sizeof(ctrl->vfeBusCmdLocal));
- memset(&ctrl->vfeInterruptNameLocal, 0,
- sizeof(ctrl->vfeInterruptNameLocal));
- memset(&ctrl->vfeDroppedFrameCounts, 0,
- sizeof(ctrl->vfeDroppedFrameCounts));
- memset(&ctrl->vfeIrqThreadMsgLocal, 0,
- sizeof(ctrl->vfeIrqThreadMsgLocal));
-
- /* state control variables */
- ctrl->vfeStartAckPendingFlag = FALSE;
- ctrl->vfeStopAckPending = FALSE;
- ctrl->vfeIrqCompositeMaskLocal.ceDoneSel = 0;
- ctrl->vfeIrqCompositeMaskLocal.encIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
- ctrl->vfeIrqCompositeMaskLocal.viewIrqComMask =
- VFE_COMP_IRQ_BOTH_Y_CBCR;
-
- spin_lock_irqsave(&ctrl->state_lock, flags);
- ctrl->vstate = VFE_STATE_IDLE;
- spin_unlock_irqrestore(&ctrl->state_lock, flags);
-
- ctrl->axiOutputMode = VFE_AXI_LAST_OUTPUT_MODE_ENUM;
- /* 0 for continuous mode, 1 for snapshot mode */
- ctrl->vfeOperationMode = VFE_START_OPERATION_MODE_CONTINUOUS;
- ctrl->vfeSnapShotCount = 0;
- ctrl->vfeStatsPingPongReloadFlag = FALSE;
- /* this is unsigned 32 bit integer. */
- ctrl->vfeFrameId = 0;
- ctrl->vfeFrameSkip.output1Pattern = 0xffffffff;
- ctrl->vfeFrameSkip.output1Period = 31;
- ctrl->vfeFrameSkip.output2Pattern = 0xffffffff;
- ctrl->vfeFrameSkip.output2Period = 31;
- ctrl->vfeFrameSkipPattern = 0xffffffff;
- ctrl->vfeFrameSkipCount = 0;
- ctrl->vfeFrameSkipPeriod = 31;
-
- memset((void *)&ctrl->encPath, 0, sizeof(ctrl->encPath));
- memset((void *)&ctrl->viewPath, 0, sizeof(ctrl->viewPath));
-
- ctrl->encPath.whichOutputPath = 1;
- ctrl->encPath.cbcrStatusBit = 5;
- ctrl->viewPath.whichOutputPath = 0;
- ctrl->viewPath.cbcrStatusBit = 7;
-
- ctrl->vfeTestGenStartFlag = FALSE;
-
- /* default to bank 0. */
- ctrl->vfeLaBankSel = 0;
-
- /* default to bank 0 for all channels. */
- memset(&ctrl->vfeGammaLutSel, 0, sizeof(ctrl->vfeGammaLutSel));
-
- /* Stats control variables. */
- memset(&ctrl->afStatsControl, 0, sizeof(ctrl->afStatsControl));
- memset(&ctrl->awbStatsControl, 0, sizeof(ctrl->awbStatsControl));
- vfe_set_stats_pingpong_address(&ctrl->afStatsControl,
- &ctrl->awbStatsControl);
-}
-
-void vfe_reset(void)
-{
- vfe_reset_internal_variables();
-
- ctrl->vfeImaskLocal.resetAckIrq = TRUE;
- ctrl->vfeImaskPacked = vfe_irq_pack(ctrl->vfeImaskLocal);
-
- /* disable all interrupts. */
- writel(VFE_DISABLE_ALL_IRQS,
- ctrl->vfebase + VFE_IRQ_COMPOSITE_MASK);
-
- /* clear all pending interrupts*/
- writel(VFE_CLEAR_ALL_IRQS,
- ctrl->vfebase + VFE_IRQ_CLEAR);
-
- /* enable reset_ack interrupt. */
- writel(ctrl->vfeImaskPacked,
- ctrl->vfebase + VFE_IRQ_MASK);
-
- writel(VFE_RESET_UPON_RESET_CMD,
- ctrl->vfebase + VFE_GLOBAL_RESET_CMD);
-}
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef __MSM_VFE8X_REG_H__
-#define __MSM_VFE8X_REG_H__
-
-#include <mach/msm_iomap.h>
-#include <mach/camera.h>
-#include "msm_vfe8x.h"
-
-/* at start of camif, bit 1:0 = 0x01:enable
- * image data capture at frame boundary. */
-#define CAMIF_COMMAND_START 0x00000005
-
-/* bit 2= 0x1:clear the CAMIF_STATUS register
- * value. */
-#define CAMIF_COMMAND_CLEAR 0x00000004
-
-/* at stop of vfe pipeline, for now it is assumed
- * that camif will stop at any time. Bit 1:0 = 0x10:
- * disable image data capture immediately. */
-#define CAMIF_COMMAND_STOP_IMMEDIATELY 0x00000002
-
-/* at stop of vfe pipeline, for now it is assumed
- * that camif will stop at any time. Bit 1:0 = 0x00:
- * disable image data capture at frame boundary */
-#define CAMIF_COMMAND_STOP_AT_FRAME_BOUNDARY 0x00000000
-
-/* to halt axi bridge */
-#define AXI_HALT 0x00000001
-
-/* clear the halt bit. */
-#define AXI_HALT_CLEAR 0x00000000
-
-/* reset the pipeline when stop command is issued.
- * (without reset the register.) bit 26-31 = 0,
- * domain reset, bit 0-9 = 1 for module reset, except
- * register module. */
-#define VFE_RESET_UPON_STOP_CMD 0x000003ef
-
-/* reset the pipeline when reset command.
- * bit 26-31 = 0, domain reset, bit 0-9 = 1 for module reset. */
-#define VFE_RESET_UPON_RESET_CMD 0x000003ff
-
-/* bit 5 is for axi status idle or busy.
- * 1 = halted, 0 = busy */
-#define AXI_STATUS_BUSY_MASK 0x00000020
-
-/* bit 0 & bit 1 = 1, both y and cbcr irqs need to be present
- * for frame done interrupt */
-#define VFE_COMP_IRQ_BOTH_Y_CBCR 3
-
-/* bit 1 = 1, only cbcr irq triggers frame done interrupt */
-#define VFE_COMP_IRQ_CBCR_ONLY 2
-
-/* bit 0 = 1, only y irq triggers frame done interrupt */
-#define VFE_COMP_IRQ_Y_ONLY 1
-
-/* bit 0 = 1, PM go; bit1 = 1, PM stop */
-#define VFE_PERFORMANCE_MONITOR_GO 0x00000001
-#define VFE_PERFORMANCE_MONITOR_STOP 0x00000002
-
-/* bit 0 = 1, test gen go; bit1 = 1, test gen stop */
-#define VFE_TEST_GEN_GO 0x00000001
-#define VFE_TEST_GEN_STOP 0x00000002
-
-/* the chroma is assumed to be interpolated between
- * the luma samples. JPEG 4:2:2 */
-#define VFE_CHROMA_UPSAMPLE_INTERPOLATED 0
-
-/* constants for irq registers */
-#define VFE_DISABLE_ALL_IRQS 0
-/* bit =1 is to clear the corresponding bit in VFE_IRQ_STATUS. */
-#define VFE_CLEAR_ALL_IRQS 0xffffffff
-/* imask for while waiting for stop ack, driver has already
- * requested stop, waiting for reset irq,
- * bit 29,28,27,26 for async timer, bit 9 for reset */
-#define VFE_IMASK_WHILE_STOPPING 0x3c000200
-
-/* when normal case, don't want to block error status.
- * bit 0,6,20,21,22,30,31 */
-#define VFE_IMASK_ERROR_ONLY 0xC0700041
-#define VFE_REG_UPDATE_TRIGGER 1
-#define VFE_PM_BUF_MAX_CNT_MASK 0xFF
-#define VFE_DMI_CFG_DEFAULT 0x00000100
-#define LENS_ROLL_OFF_DELTA_TABLE_OFFSET 32
-#define VFE_AF_PINGPONG_STATUS_BIT 0x100
-#define VFE_AWB_PINGPONG_STATUS_BIT 0x200
-
-/* VFE I/O registers */
-enum {
- VFE_HW_VERSION = 0x00000000,
- VFE_GLOBAL_RESET_CMD = 0x00000004,
- VFE_MODULE_RESET = 0x00000008,
- VFE_CGC_OVERRIDE = 0x0000000C,
- VFE_MODULE_CFG = 0x00000010,
- VFE_CFG = 0x00000014,
- VFE_IRQ_MASK = 0x00000018,
- VFE_IRQ_CLEAR = 0x0000001C,
-VFE_IRQ_STATUS = 0x00000020,
-VFE_IRQ_COMPOSITE_MASK = 0x00000024,
-VFE_BUS_CMD = 0x00000028,
-VFE_BUS_CFG = 0x0000002C,
-VFE_BUS_ENC_Y_WR_PING_ADDR = 0x00000030,
-VFE_BUS_ENC_Y_WR_PONG_ADDR = 0x00000034,
-VFE_BUS_ENC_Y_WR_IMAGE_SIZE = 0x00000038,
-VFE_BUS_ENC_Y_WR_BUFFER_CFG = 0x0000003C,
-VFE_BUS_ENC_CBCR_WR_PING_ADDR = 0x00000040,
-VFE_BUS_ENC_CBCR_WR_PONG_ADDR = 0x00000044,
-VFE_BUS_ENC_CBCR_WR_IMAGE_SIZE = 0x00000048,
-VFE_BUS_ENC_CBCR_WR_BUFFER_CFG = 0x0000004C,
-VFE_BUS_VIEW_Y_WR_PING_ADDR = 0x00000050,
-VFE_BUS_VIEW_Y_WR_PONG_ADDR = 0x00000054,
-VFE_BUS_VIEW_Y_WR_IMAGE_SIZE = 0x00000058,
-VFE_BUS_VIEW_Y_WR_BUFFER_CFG = 0x0000005C,
-VFE_BUS_VIEW_CBCR_WR_PING_ADDR = 0x00000060,
-VFE_BUS_VIEW_CBCR_WR_PONG_ADDR = 0x00000064,
-VFE_BUS_VIEW_CBCR_WR_IMAGE_SIZE = 0x00000068,
-VFE_BUS_VIEW_CBCR_WR_BUFFER_CFG = 0x0000006C,
-VFE_BUS_STATS_AF_WR_PING_ADDR = 0x00000070,
-VFE_BUS_STATS_AF_WR_PONG_ADDR = 0x00000074,
-VFE_BUS_STATS_AWB_WR_PING_ADDR = 0x00000078,
-VFE_BUS_STATS_AWB_WR_PONG_ADDR = 0x0000007C,
-VFE_BUS_STATS_HIST_WR_PING_ADDR = 0x00000080,
-VFE_BUS_STATS_HIST_WR_PONG_ADDR = 0x00000084,
-VFE_BUS_STATS_WR_PRIORITY = 0x00000088,
-VFE_BUS_STRIPE_RD_ADDR_0 = 0x0000008C,
-VFE_BUS_STRIPE_RD_ADDR_1 = 0x00000090,
-VFE_BUS_STRIPE_RD_ADDR_2 = 0x00000094,
-VFE_BUS_STRIPE_RD_ADDR_3 = 0x00000098,
-VFE_BUS_STRIPE_RD_VSIZE = 0x0000009C,
-VFE_BUS_STRIPE_RD_HSIZE = 0x000000A0,
-VFE_BUS_STRIPE_RD_BUFFER_CFG = 0x000000A4,
-VFE_BUS_STRIPE_RD_UNPACK_CFG = 0x000000A8,
-VFE_BUS_STRIPE_RD_UNPACK = 0x000000AC,
-VFE_BUS_STRIPE_RD_PAD_SIZE = 0x000000B0,
-VFE_BUS_STRIPE_RD_PAD_L_UNPACK = 0x000000B4,
-VFE_BUS_STRIPE_RD_PAD_R_UNPACK = 0x000000B8,
-VFE_BUS_STRIPE_RD_PAD_TB_UNPACK = 0x000000BC,
-VFE_BUS_PINGPONG_IRQ_EN = 0x000000C0,
-VFE_BUS_PINGPONG_STATUS = 0x000000C4,
-VFE_BUS_PM_CMD = 0x000000C8,
-VFE_BUS_PM_CFG = 0x000000CC,
-VFE_BUS_ENC_Y_WR_PM_STATS_0 = 0x000000D0,
-VFE_BUS_ENC_Y_WR_PM_STATS_1 = 0x000000D4,
-VFE_BUS_ENC_CBCR_WR_PM_STATS_0 = 0x000000D8,
-VFE_BUS_ENC_CBCR_WR_PM_STATS_1 = 0x000000DC,
-VFE_BUS_VIEW_Y_WR_PM_STATS_0 = 0x000000E0,
-VFE_BUS_VIEW_Y_WR_PM_STATS_1 = 0x000000E4,
-VFE_BUS_VIEW_CBCR_WR_PM_STATS_0 = 0x000000E8,
-VFE_BUS_VIEW_CBCR_WR_PM_STATS_1 = 0x000000EC,
-VFE_BUS_MISR_CFG = 0x000000F4,
-VFE_BUS_MISR_MAST_CFG_0 = 0x000000F8,
-VFE_BUS_MISR_MAST_CFG_1 = 0x000000FC,
-VFE_BUS_MISR_RD_VAL = 0x00000100,
-VFE_AXI_CMD = 0x00000104,
-VFE_AXI_CFG = 0x00000108,
-VFE_AXI_STATUS = 0x0000010C,
-CAMIF_COMMAND = 0x00000110,
-CAMIF_CONFIG = 0x00000114,
-CAMIF_EFS_CONFIG = 0x00000118,
-CAMIF_FRAME_CONFIG = 0x0000011C,
-CAMIF_WINDOW_WIDTH_CONFIG = 0x00000120,
-CAMIF_WINDOW_HEIGHT_CONFIG = 0x00000124,
-CAMIF_SUBSAMPLE1_CONFIG = 0x00000128,
-CAMIF_SUBSAMPLE2_CONFIG = 0x0000012C,
-CAMIF_EPOCH_IRQ = 0x00000130,
-CAMIF_STATUS = 0x00000134,
-CAMIF_MISR = 0x00000138,
-VFE_SYNC_TIMER_CMD = 0x0000013C,
-VFE_SYNC_TIMER0_LINE_START = 0x00000140,
-VFE_SYNC_TIMER0_PIXEL_START = 0x00000144,
-VFE_SYNC_TIMER0_PIXEL_DURATION = 0x00000148,
-VFE_SYNC_TIMER1_LINE_START = 0x0000014C,
-VFE_SYNC_TIMER1_PIXEL_START = 0x00000150,
-VFE_SYNC_TIMER1_PIXEL_DURATION = 0x00000154,
-VFE_SYNC_TIMER2_LINE_START = 0x00000158,
-VFE_SYNC_TIMER2_PIXEL_START = 0x0000015C,
-VFE_SYNC_TIMER2_PIXEL_DURATION = 0x00000160,
-VFE_SYNC_TIMER_POLARITY = 0x00000164,
-VFE_ASYNC_TIMER_CMD = 0x00000168,
-VFE_ASYNC_TIMER0_CFG_0 = 0x0000016C,
-VFE_ASYNC_TIMER0_CFG_1 = 0x00000170,
-VFE_ASYNC_TIMER1_CFG_0 = 0x00000174,
-VFE_ASYNC_TIMER1_CFG_1 = 0x00000178,
-VFE_ASYNC_TIMER2_CFG_0 = 0x0000017C,
-VFE_ASYNC_TIMER2_CFG_1 = 0x00000180,
-VFE_ASYNC_TIMER3_CFG_0 = 0x00000184,
-VFE_ASYNC_TIMER3_CFG_1 = 0x00000188,
-VFE_TIMER_SEL = 0x0000018C,
-VFE_REG_UPDATE_CMD = 0x00000190,
-VFE_BLACK_EVEN_EVEN_VALUE = 0x00000194,
-VFE_BLACK_EVEN_ODD_VALUE = 0x00000198,
-VFE_BLACK_ODD_EVEN_VALUE = 0x0000019C,
-VFE_BLACK_ODD_ODD_VALUE = 0x000001A0,
-VFE_ROLLOFF_CFG_0 = 0x000001A4,
-VFE_ROLLOFF_CFG_1 = 0x000001A8,
-VFE_ROLLOFF_CFG_2 = 0x000001AC,
-VFE_DEMUX_CFG = 0x000001B0,
-VFE_DEMUX_GAIN_0 = 0x000001B4,
-VFE_DEMUX_GAIN_1 = 0x000001B8,
-VFE_DEMUX_EVEN_CFG = 0x000001BC,
-VFE_DEMUX_ODD_CFG = 0x000001C0,
-VFE_DEMOSAIC_CFG = 0x000001C4,
-VFE_DEMOSAIC_ABF_CFG_0 = 0x000001C8,
-VFE_DEMOSAIC_ABF_CFG_1 = 0x000001CC,
-VFE_DEMOSAIC_BPC_CFG_0 = 0x000001D0,
-VFE_DEMOSAIC_BPC_CFG_1 = 0x000001D4,
-VFE_DEMOSAIC_STATUS = 0x000001D8,
-VFE_CHROMA_UPSAMPLE_CFG = 0x000001DC,
-VFE_CROP_WIDTH_CFG = 0x000001E0,
-VFE_CROP_HEIGHT_CFG = 0x000001E4,
-VFE_COLOR_CORRECT_COEFF_0 = 0x000001E8,
-VFE_COLOR_CORRECT_COEFF_1 = 0x000001EC,
-VFE_COLOR_CORRECT_COEFF_2 = 0x000001F0,
-VFE_COLOR_CORRECT_COEFF_3 = 0x000001F4,
-VFE_COLOR_CORRECT_COEFF_4 = 0x000001F8,
-VFE_COLOR_CORRECT_COEFF_5 = 0x000001FC,
-VFE_COLOR_CORRECT_COEFF_6 = 0x00000200,
-VFE_COLOR_CORRECT_COEFF_7 = 0x00000204,
-VFE_COLOR_CORRECT_COEFF_8 = 0x00000208,
-VFE_COLOR_CORRECT_OFFSET_0 = 0x0000020C,
-VFE_COLOR_CORRECT_OFFSET_1 = 0x00000210,
-VFE_COLOR_CORRECT_OFFSET_2 = 0x00000214,
-VFE_COLOR_CORRECT_COEFF_Q = 0x00000218,
-VFE_LA_CFG = 0x0000021C,
-VFE_LUT_BANK_SEL = 0x00000220,
-VFE_CHROMA_ENHAN_A = 0x00000224,
-VFE_CHROMA_ENHAN_B = 0x00000228,
-VFE_CHROMA_ENHAN_C = 0x0000022C,
-VFE_CHROMA_ENHAN_D = 0x00000230,
-VFE_CHROMA_ENHAN_K = 0x00000234,
-VFE_COLOR_CONVERT_COEFF_0 = 0x00000238,
-VFE_COLOR_CONVERT_COEFF_1 = 0x0000023C,
-VFE_COLOR_CONVERT_COEFF_2 = 0x00000240,
-VFE_COLOR_CONVERT_OFFSET = 0x00000244,
-VFE_ASF_CFG = 0x00000248,
-VFE_ASF_SHARP_CFG_0 = 0x0000024C,
-VFE_ASF_SHARP_CFG_1 = 0x00000250,
-VFE_ASF_SHARP_COEFF_0 = 0x00000254,
-VFE_ASF_SHARP_COEFF_1 = 0x00000258,
-VFE_ASF_SHARP_COEFF_2 = 0x0000025C,
-VFE_ASF_SHARP_COEFF_3 = 0x00000260,
-VFE_ASF_MAX_EDGE = 0x00000264,
-VFE_ASF_CROP_WIDTH_CFG = 0x00000268,
-VFE_ASF_CROP_HEIGHT_CFG = 0x0000026C,
-VFE_SCALE_CFG = 0x00000270,
-VFE_SCALE_H_IMAGE_SIZE_CFG = 0x00000274,
-VFE_SCALE_H_PHASE_CFG = 0x00000278,
-VFE_SCALE_H_STRIPE_CFG = 0x0000027C,
-VFE_SCALE_V_IMAGE_SIZE_CFG = 0x00000280,
-VFE_SCALE_V_PHASE_CFG = 0x00000284,
-VFE_SCALE_V_STRIPE_CFG = 0x00000288,
-VFE_SCALE_Y_CFG = 0x0000028C,
-VFE_SCALE_Y_H_IMAGE_SIZE_CFG = 0x00000290,
-VFE_SCALE_Y_H_PHASE_CFG = 0x00000294,
-VFE_SCALE_Y_V_IMAGE_SIZE_CFG = 0x00000298,
-VFE_SCALE_Y_V_PHASE_CFG = 0x0000029C,
-VFE_SCALE_CBCR_CFG = 0x000002A0,
-VFE_SCALE_CBCR_H_IMAGE_SIZE_CFG = 0x000002A4,
-VFE_SCALE_CBCR_H_PHASE_CFG = 0x000002A8,
-VFE_SCALE_CBCR_V_IMAGE_SIZE_CFG = 0x000002AC,
-VFE_SCALE_CBCR_V_PHASE_CFG = 0x000002B0,
-VFE_WB_CFG = 0x000002B4,
-VFE_CHROMA_SUPPRESS_CFG_0 = 0x000002B8,
-VFE_CHROMA_SUPPRESS_CFG_1 = 0x000002BC,
-VFE_CHROMA_SUBSAMPLE_CFG = 0x000002C0,
-VFE_CHROMA_SUB_CROP_WIDTH_CFG = 0x000002C4,
-VFE_CHROMA_SUB_CROP_HEIGHT_CFG = 0x000002C8,
-VFE_FRAMEDROP_ENC_Y_CFG = 0x000002CC,
-VFE_FRAMEDROP_ENC_CBCR_CFG = 0x000002D0,
-VFE_FRAMEDROP_ENC_Y_PATTERN = 0x000002D4,
-VFE_FRAMEDROP_ENC_CBCR_PATTERN = 0x000002D8,
-VFE_FRAMEDROP_VIEW_Y_CFG = 0x000002DC,
-VFE_FRAMEDROP_VIEW_CBCR_CFG = 0x000002E0,
-VFE_FRAMEDROP_VIEW_Y_PATTERN = 0x000002E4,
-VFE_FRAMEDROP_VIEW_CBCR_PATTERN = 0x000002E8,
-VFE_CLAMP_MAX_CFG = 0x000002EC,
-VFE_CLAMP_MIN_CFG = 0x000002F0,
-VFE_STATS_CMD = 0x000002F4,
-VFE_STATS_AF_CFG = 0x000002F8,
-VFE_STATS_AF_DIM = 0x000002FC,
-VFE_STATS_AF_GRID_0 = 0x00000300,
-VFE_STATS_AF_GRID_1 = 0x00000304,
-VFE_STATS_AF_GRID_2 = 0x00000308,
-VFE_STATS_AF_GRID_3 = 0x0000030C,
-VFE_STATS_AF_HEADER = 0x00000310,
-VFE_STATS_AF_COEF0 = 0x00000314,
-VFE_STATS_AF_COEF1 = 0x00000318,
-VFE_STATS_AWBAE_CFG = 0x0000031C,
-VFE_STATS_AXW_HEADER = 0x00000320,
-VFE_STATS_AWB_MCFG = 0x00000324,
-VFE_STATS_AWB_CCFG1 = 0x00000328,
-VFE_STATS_AWB_CCFG2 = 0x0000032C,
-VFE_STATS_HIST_HEADER = 0x00000330,
-VFE_STATS_HIST_INNER_OFFSET = 0x00000334,
-VFE_STATS_HIST_INNER_DIM = 0x00000338,
-VFE_STATS_FRAME_SIZE = 0x0000033C,
-VFE_DMI_CFG = 0x00000340,
-VFE_DMI_ADDR = 0x00000344,
-VFE_DMI_DATA_HI = 0x00000348,
-VFE_DMI_DATA_LO = 0x0000034C,
-VFE_DMI_RAM_AUTO_LOAD_CMD = 0x00000350,
-VFE_DMI_RAM_AUTO_LOAD_STATUS = 0x00000354,
-VFE_DMI_RAM_AUTO_LOAD_CFG = 0x00000358,
-VFE_DMI_RAM_AUTO_LOAD_SEED = 0x0000035C,
-VFE_TESTBUS_SEL = 0x00000360,
-VFE_TESTGEN_CFG = 0x00000364,
-VFE_SW_TESTGEN_CMD = 0x00000368,
-VFE_HW_TESTGEN_CMD = 0x0000036C,
-VFE_HW_TESTGEN_CFG = 0x00000370,
-VFE_HW_TESTGEN_IMAGE_CFG = 0x00000374,
-VFE_HW_TESTGEN_SOF_OFFSET_CFG = 0x00000378,
-VFE_HW_TESTGEN_EOF_NOFFSET_CFG = 0x0000037C,
-VFE_HW_TESTGEN_SOL_OFFSET_CFG = 0x00000380,
-VFE_HW_TESTGEN_EOL_NOFFSET_CFG = 0x00000384,
-VFE_HW_TESTGEN_HBI_CFG = 0x00000388,
-VFE_HW_TESTGEN_VBL_CFG = 0x0000038C,
-VFE_HW_TESTGEN_SOF_DUMMY_LINE_CFG2 = 0x00000390,
-VFE_HW_TESTGEN_EOF_DUMMY_LINE_CFG2 = 0x00000394,
-VFE_HW_TESTGEN_COLOR_BARS_CFG = 0x00000398,
-VFE_HW_TESTGEN_RANDOM_CFG = 0x0000039C,
-VFE_SPARE = 0x000003A0,
-};
-
-#define ping 0x0
-#define pong 0x1
-
-struct vfe_bus_cfg_data {
- boolean stripeRdPathEn;
- boolean encYWrPathEn;
- boolean encCbcrWrPathEn;
- boolean viewYWrPathEn;
- boolean viewCbcrWrPathEn;
- enum VFE_RAW_PIXEL_DATA_SIZE rawPixelDataSize;
- enum VFE_RAW_WR_PATH_SEL rawWritePathSelect;
-};
-
-struct vfe_camif_cfg_data {
- boolean camif2OutputEnable;
- boolean camif2BusEnable;
- struct vfe_cmds_camif_cfg camifCfgFromCmd;
-};
-
-struct vfe_irq_composite_mask_config {
- uint8_t encIrqComMask;
- uint8_t viewIrqComMask;
- uint8_t ceDoneSel;
-};
-
-/* define a structure for each output path.*/
-struct vfe_output_path {
- uint32_t addressBuffer[8];
- uint16_t fragIndex;
- boolean hwCurrentFlag;
- uint8_t *hwRegPingAddress;
- uint8_t *hwRegPongAddress;
-};
-
-struct vfe_output_path_combo {
- boolean whichOutputPath;
- boolean pathEnabled;
- boolean multiFrag;
- uint8_t fragCount;
- boolean ackPending;
- uint8_t currentFrame;
- uint32_t nextFrameAddrBuf[8];
- struct vfe_output_path yPath;
- struct vfe_output_path cbcrPath;
- uint8_t snapshotPendingCount;
- boolean pmEnabled;
- uint8_t cbcrStatusBit;
-};
-
-struct vfe_stats_control {
- boolean ackPending;
- uint32_t addressBuffer[2];
- uint32_t nextFrameAddrBuf;
- boolean pingPongStatus;
- uint8_t *hwRegPingAddress;
- uint8_t *hwRegPongAddress;
- uint32_t droppedStatsFrameCount;
- uint32_t bufToRender;
-};
-
-struct vfe_gamma_lut_sel {
- boolean ch0BankSelect;
- boolean ch1BankSelect;
- boolean ch2BankSelect;
-};
-
-struct vfe_interrupt_mask {
- boolean camifErrorIrq;
- boolean camifSofIrq;
- boolean camifEolIrq;
- boolean camifEofIrq;
- boolean camifEpoch1Irq;
- boolean camifEpoch2Irq;
- boolean camifOverflowIrq;
- boolean ceIrq;
- boolean regUpdateIrq;
- boolean resetAckIrq;
- boolean encYPingpongIrq;
- boolean encCbcrPingpongIrq;
- boolean viewYPingpongIrq;
- boolean viewCbcrPingpongIrq;
- boolean rdPingpongIrq;
- boolean afPingpongIrq;
- boolean awbPingpongIrq;
- boolean histPingpongIrq;
- boolean encIrq;
- boolean viewIrq;
- boolean busOverflowIrq;
- boolean afOverflowIrq;
- boolean awbOverflowIrq;
- boolean syncTimer0Irq;
- boolean syncTimer1Irq;
- boolean syncTimer2Irq;
- boolean asyncTimer0Irq;
- boolean asyncTimer1Irq;
- boolean asyncTimer2Irq;
- boolean asyncTimer3Irq;
- boolean axiErrorIrq;
- boolean violationIrq;
-};
-
-enum vfe_interrupt_name {
- CAMIF_ERROR_IRQ,
- CAMIF_SOF_IRQ,
- CAMIF_EOL_IRQ,
- CAMIF_EOF_IRQ,
- CAMIF_EPOCH1_IRQ,
- CAMIF_EPOCH2_IRQ,
- CAMIF_OVERFLOW_IRQ,
- CE_IRQ,
- REG_UPDATE_IRQ,
- RESET_ACK_IRQ,
- ENC_Y_PINGPONG_IRQ,
- ENC_CBCR_PINGPONG_IRQ,
- VIEW_Y_PINGPONG_IRQ,
- VIEW_CBCR_PINGPONG_IRQ,
- RD_PINGPONG_IRQ,
- AF_PINGPONG_IRQ,
- AWB_PINGPONG_IRQ,
- HIST_PINGPONG_IRQ,
- ENC_IRQ,
- VIEW_IRQ,
- BUS_OVERFLOW_IRQ,
- AF_OVERFLOW_IRQ,
- AWB_OVERFLOW_IRQ,
- SYNC_TIMER0_IRQ,
- SYNC_TIMER1_IRQ,
- SYNC_TIMER2_IRQ,
- ASYNC_TIMER0_IRQ,
- ASYNC_TIMER1_IRQ,
- ASYNC_TIMER2_IRQ,
- ASYNC_TIMER3_IRQ,
- AXI_ERROR_IRQ,
- VIOLATION_IRQ
-};
-
-enum VFE_DMI_RAM_SEL {
- NO_MEM_SELECTED = 0,
- ROLLOFF_RAM = 0x1,
- RGBLUT_RAM_CH0_BANK0 = 0x2,
- RGBLUT_RAM_CH0_BANK1 = 0x3,
- RGBLUT_RAM_CH1_BANK0 = 0x4,
- RGBLUT_RAM_CH1_BANK1 = 0x5,
- RGBLUT_RAM_CH2_BANK0 = 0x6,
- RGBLUT_RAM_CH2_BANK1 = 0x7,
- STATS_HIST_CB_EVEN_RAM = 0x8,
- STATS_HIST_CB_ODD_RAM = 0x9,
- STATS_HIST_CR_EVEN_RAM = 0xa,
- STATS_HIST_CR_ODD_RAM = 0xb,
- RGBLUT_CHX_BANK0 = 0xc,
- RGBLUT_CHX_BANK1 = 0xd,
- LUMA_ADAPT_LUT_RAM_BANK0 = 0xe,
- LUMA_ADAPT_LUT_RAM_BANK1 = 0xf
-};
-
-struct vfe_module_enable {
- boolean blackLevelCorrectionEnable;
- boolean lensRollOffEnable;
- boolean demuxEnable;
- boolean chromaUpsampleEnable;
- boolean demosaicEnable;
- boolean statsEnable;
- boolean cropEnable;
- boolean mainScalerEnable;
- boolean whiteBalanceEnable;
- boolean colorCorrectionEnable;
- boolean yHistEnable;
- boolean skinToneEnable;
- boolean lumaAdaptationEnable;
- boolean rgbLUTEnable;
- boolean chromaEnhanEnable;
- boolean asfEnable;
- boolean chromaSuppressionEnable;
- boolean chromaSubsampleEnable;
- boolean scaler2YEnable;
- boolean scaler2CbcrEnable;
-};
-
-struct vfe_bus_cmd_data {
- boolean stripeReload;
- boolean busPingpongReload;
- boolean statsPingpongReload;
-};
-
-struct vfe_stats_cmd_data {
- boolean autoFocusEnable;
- boolean axwEnable;
- boolean histEnable;
- boolean clearHistEnable;
- boolean histAutoClearEnable;
- boolean colorConversionEnable;
-};
-
-struct vfe_hw_ver {
- uint32_t minorVersion:8;
- uint32_t majorVersion:8;
- uint32_t coreVersion:4;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_cfg {
- uint32_t pixelPattern:3;
- uint32_t /* reserved */ : 13;
- uint32_t inputSource:2;
- uint32_t /* reserved */ : 14;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_buscmd {
- uint32_t stripeReload:1;
- uint32_t /* reserved */ : 3;
- uint32_t busPingpongReload:1;
- uint32_t statsPingpongReload:1;
- uint32_t /* reserved */ : 26;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_Irq_Composite_MaskType {
- uint32_t encIrqComMaskBits:2;
- uint32_t viewIrqComMaskBits:2;
- uint32_t ceDoneSelBits:5;
- uint32_t /* reserved */ : 23;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_mod_enable {
- uint32_t blackLevelCorrectionEnable:1;
- uint32_t lensRollOffEnable:1;
- uint32_t demuxEnable:1;
- uint32_t chromaUpsampleEnable:1;
- uint32_t demosaicEnable:1;
- uint32_t statsEnable:1;
- uint32_t cropEnable:1;
- uint32_t mainScalerEnable:1;
- uint32_t whiteBalanceEnable:1;
- uint32_t colorCorrectionEnable:1;
- uint32_t yHistEnable:1;
- uint32_t skinToneEnable:1;
- uint32_t lumaAdaptationEnable:1;
- uint32_t rgbLUTEnable:1;
- uint32_t chromaEnhanEnable:1;
- uint32_t asfEnable:1;
- uint32_t chromaSuppressionEnable:1;
- uint32_t chromaSubsampleEnable:1;
- uint32_t scaler2YEnable:1;
- uint32_t scaler2CbcrEnable:1;
- uint32_t /* reserved */ : 14;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_irqenable {
- uint32_t camifErrorIrq:1;
- uint32_t camifSofIrq:1;
- uint32_t camifEolIrq:1;
- uint32_t camifEofIrq:1;
- uint32_t camifEpoch1Irq:1;
- uint32_t camifEpoch2Irq:1;
- uint32_t camifOverflowIrq:1;
- uint32_t ceIrq:1;
- uint32_t regUpdateIrq:1;
- uint32_t resetAckIrq:1;
- uint32_t encYPingpongIrq:1;
- uint32_t encCbcrPingpongIrq:1;
- uint32_t viewYPingpongIrq:1;
- uint32_t viewCbcrPingpongIrq:1;
- uint32_t rdPingpongIrq:1;
- uint32_t afPingpongIrq:1;
- uint32_t awbPingpongIrq:1;
- uint32_t histPingpongIrq:1;
- uint32_t encIrq:1;
- uint32_t viewIrq:1;
- uint32_t busOverflowIrq:1;
- uint32_t afOverflowIrq:1;
- uint32_t awbOverflowIrq:1;
- uint32_t syncTimer0Irq:1;
- uint32_t syncTimer1Irq:1;
- uint32_t syncTimer2Irq:1;
- uint32_t asyncTimer0Irq:1;
- uint32_t asyncTimer1Irq:1;
- uint32_t asyncTimer2Irq:1;
- uint32_t asyncTimer3Irq:1;
- uint32_t axiErrorIrq:1;
- uint32_t violationIrq:1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_upsample_cfg {
- uint32_t chromaCositingForYCbCrInputs:1;
- uint32_t /* reserved */ : 31;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_CAMIFConfigType {
- /* CAMIF Config */
- uint32_t /* reserved */ : 1;
- uint32_t VSyncEdge:1;
- uint32_t HSyncEdge:1;
- uint32_t syncMode:2;
- uint32_t vfeSubsampleEnable:1;
- uint32_t /* reserved */ : 1;
- uint32_t busSubsampleEnable:1;
- uint32_t camif2vfeEnable:1;
- uint32_t /* reserved */ : 1;
- uint32_t camif2busEnable:1;
- uint32_t irqSubsampleEnable:1;
- uint32_t binningEnable:1;
- uint32_t /* reserved */ : 18;
- uint32_t misrEnable:1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camifcfg {
- /* EFS_Config */
- uint32_t efsEndOfLine:8;
- uint32_t efsStartOfLine:8;
- uint32_t efsEndOfFrame:8;
- uint32_t efsStartOfFrame:8;
- /* Frame Config */
- uint32_t frameConfigPixelsPerLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t frameConfigLinesPerFrame:14;
- uint32_t /* reserved */ : 2;
- /* Window Width Config */
- uint32_t windowWidthCfgLastPixel:14;
- uint32_t /* reserved */ : 2;
- uint32_t windowWidthCfgFirstPixel:14;
- uint32_t /* reserved */ : 2;
- /* Window Height Config */
- uint32_t windowHeightCfglastLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t windowHeightCfgfirstLine:14;
- uint32_t /* reserved */ : 2;
- /* Subsample 1 Config */
- uint32_t subsample1CfgPixelSkip:16;
- uint32_t subsample1CfgLineSkip:16;
- /* Subsample 2 Config */
- uint32_t subsample2CfgFrameSkip:4;
- uint32_t subsample2CfgFrameSkipMode:1;
- uint32_t subsample2CfgPixelSkipWrap:1;
- uint32_t /* reserved */ : 26;
- /* Epoch Interrupt */
- uint32_t epoch1Line:14;
- uint32_t /* reserved */ : 2;
- uint32_t epoch2Line:14;
- uint32_t /* reserved */ : 2;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camifframe_update {
- uint32_t pixelsPerLine:14;
- uint32_t /* reserved */ : 2;
- uint32_t linesPerFrame:14;
- uint32_t /* reserved */ : 2;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_axi_bus_cfg {
- uint32_t stripeRdPathEn:1;
- uint32_t /* reserved */ : 3;
- uint32_t encYWrPathEn:1;
- uint32_t encCbcrWrPathEn:1;
- uint32_t viewYWrPathEn:1;
- uint32_t viewCbcrWrPathEn:1;
- uint32_t rawPixelDataSize:2;
- uint32_t rawWritePathSelect:2;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_axi_out_cfg {
- uint32_t out2YPingAddr:32;
- uint32_t out2YPongAddr:32;
- uint32_t out2YImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2YImageWidthin64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out2YBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out2YNumRows:12;
- uint32_t out2YRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2CbcrPingAddr:32;
- uint32_t out2CbcrPongAddr:32;
- uint32_t out2CbcrImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out2CbcrImageWidthIn64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out2CbcrBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out2CbcrNumRows:12;
- uint32_t out2CbcrRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1YPingAddr:32;
- uint32_t out1YPongAddr:32;
- uint32_t out1YImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1YImageWidthin64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out1YBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out1YNumRows:12;
- uint32_t out1YRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1CbcrPingAddr:32;
- uint32_t out1CbcrPongAddr:32;
- uint32_t out1CbcrImageHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t out1CbcrImageWidthIn64bit:10;
- uint32_t /* reserved */ : 6;
- uint32_t out1CbcrBurstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t out1CbcrNumRows:12;
- uint32_t out1CbcrRowIncrementIn64bit:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_output_clamp_cfg {
- /* Output Clamp Maximums */
- uint32_t yChanMax:8;
- uint32_t cbChanMax:8;
- uint32_t crChanMax:8;
- uint32_t /* reserved */ : 8;
- /* Output Clamp Minimums */
- uint32_t yChanMin:8;
- uint32_t cbChanMin:8;
- uint32_t crChanMin:8;
- uint32_t /* reserved */ : 8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_fov_crop_cfg {
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstPixel:12;
- uint32_t /* reserved */ : 4;
-
- /* FOV Corp, Part 2 */
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_FRAME_SKIP_UpdateCmdType {
- uint32_t yPattern:32;
- uint32_t cbcrPattern:32;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_frame_skip_cfg {
- /* Frame Drop Enc (output2) */
- uint32_t output2YPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output2CbCrPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output2YPattern:32;
- uint32_t output2CbCrPattern:32;
- /* Frame Drop View (output1) */
- uint32_t output1YPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output1CbCrPeriod:5;
- uint32_t /* reserved */ : 27;
- uint32_t output1YPattern:32;
- uint32_t output1CbCrPattern:32;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_main_scaler_cfg {
- /* Scaler Enable Config */
- uint32_t hEnable:1;
- uint32_t vEnable:1;
- uint32_t /* reserved */ : 30;
- /* Scale H Image Size Config */
- uint32_t inWidth:12;
- uint32_t /* reserved */ : 4;
- uint32_t outWidth:12;
- uint32_t /* reserved */ : 4;
- /* Scale H Phase Config */
- uint32_t horizPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t horizInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scale H Stripe Config */
- uint32_t horizMNInit:12;
- uint32_t /* reserved */ : 4;
- uint32_t horizPhaseInit:15;
- uint32_t /* reserved */ : 1;
- /* Scale V Image Size Config */
- uint32_t inHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t outHeight:12;
- uint32_t /* reserved */ : 4;
- /* Scale V Phase Config */
- uint32_t vertPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t vertInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scale V Stripe Config */
- uint32_t vertMNInit:12;
- uint32_t /* reserved */ : 4;
- uint32_t vertPhaseInit:15;
- uint32_t /* reserved */ : 1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_scaler2_cfg {
- /* Scaler Enable Config */
- uint32_t hEnable:1;
- uint32_t vEnable:1;
- uint32_t /* reserved */ : 30;
- /* Scaler H Image Size Config */
- uint32_t inWidth:12;
- uint32_t /* reserved */ : 4;
- uint32_t outWidth:12;
- uint32_t /* reserved */ : 4;
- /* Scaler H Phase Config */
- uint32_t horizPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t horizInterResolution:2;
- uint32_t /* reserved */ : 10;
- /* Scaler V Image Size Config */
- uint32_t inHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t outHeight:12;
- uint32_t /* reserved */ : 4;
- /* Scaler V Phase Config */
- uint32_t vertPhaseMult:18;
- uint32_t /* reserved */ : 2;
- uint32_t vertInterResolution:2;
- uint32_t /* reserved */ : 10;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_rolloff_cfg {
- /* Rolloff 0 Config */
- uint32_t gridWidth:9;
- uint32_t gridHeight:9;
- uint32_t yDelta:9;
- uint32_t /* reserved */ : 5;
- /* Rolloff 1 Config*/
- uint32_t gridX:4;
- uint32_t gridY:4;
- uint32_t pixelX:9;
- uint32_t /* reserved */ : 3;
- uint32_t pixelY:9;
- uint32_t /* reserved */ : 3;
- /* Rolloff 2 Config */
- uint32_t yDeltaAccum:12;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asf_update {
- /* ASF Config Command */
- uint32_t smoothEnable:1;
- uint32_t sharpMode:2;
- uint32_t /* reserved */ : 1;
- uint32_t smoothCoeff1:4;
- uint32_t smoothCoeff0:8;
- uint32_t pipeFlushCount:12;
- uint32_t pipeFlushOvd:1;
- uint32_t flushHaltOvd:1;
- uint32_t cropEnable:1;
- uint32_t /* reserved */ : 1;
- /* Sharpening Config 0 */
- uint32_t sharpThresholdE1:7;
- uint32_t /* reserved */ : 1;
- uint32_t sharpDegreeK1:5;
- uint32_t /* reserved */ : 3;
- uint32_t sharpDegreeK2:5;
- uint32_t /* reserved */ : 3;
- uint32_t normalizeFactor:7;
- uint32_t /* reserved */ : 1;
- /* Sharpening Config 1 */
- uint32_t sharpThresholdE2:8;
- uint32_t sharpThresholdE3:8;
- uint32_t sharpThresholdE4:8;
- uint32_t sharpThresholdE5:8;
- /* Sharpening Coefficients 0 */
- uint32_t F1Coeff0:6;
- uint32_t F1Coeff1:6;
- uint32_t F1Coeff2:6;
- uint32_t F1Coeff3:6;
- uint32_t F1Coeff4:6;
- uint32_t /* reserved */ : 2;
- /* Sharpening Coefficients 1 */
- uint32_t F1Coeff5:6;
- uint32_t F1Coeff6:6;
- uint32_t F1Coeff7:6;
- uint32_t F1Coeff8:7;
- uint32_t /* reserved */ : 7;
- /* Sharpening Coefficients 2 */
- uint32_t F2Coeff0:6;
- uint32_t F2Coeff1:6;
- uint32_t F2Coeff2:6;
- uint32_t F2Coeff3:6;
- uint32_t F2Coeff4:6;
- uint32_t /* reserved */ : 2;
- /* Sharpening Coefficients 3 */
- uint32_t F2Coeff5:6;
- uint32_t F2Coeff6:6;
- uint32_t F2Coeff7:6;
- uint32_t F2Coeff8:7;
- uint32_t /* reserved */ : 7;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asfcrop_cfg {
- /* ASF Crop Width Config */
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstPixel:12;
- uint32_t /* reserved */ : 4;
- /* ASP Crop Height Config */
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t firstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chroma_suppress_cfg {
- /* Chroma Suppress 0 Config */
- uint32_t m1:8;
- uint32_t m3:8;
- uint32_t n1:3;
- uint32_t /* reserved */ : 1;
- uint32_t n3:3;
- uint32_t /* reserved */ : 9;
- /* Chroma Suppress 1 Config */
- uint32_t mm1:8;
- uint32_t nn1:3;
- uint32_t /* reserved */ : 21;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chromasubsample_cfg {
- /* Chroma Subsample Selection */
- uint32_t hCositedPhase:1;
- uint32_t vCositedPhase:1;
- uint32_t hCosited:1;
- uint32_t vCosited:1;
- uint32_t hsubSampleEnable:1;
- uint32_t vsubSampleEnable:1;
- uint32_t cropEnable:1;
- uint32_t /* reserved */ : 25;
- uint32_t cropWidthLastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropWidthFirstPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropHeightLastLine:12;
- uint32_t /* reserved */ : 4;
- uint32_t cropHeightFirstLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_blacklevel_cfg {
- /* Black Even-Even Value Config */
- uint32_t evenEvenAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Even-Odd Value Config */
- uint32_t evenOddAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Odd-Even Value Config */
- uint32_t oddEvenAdjustment:9;
- uint32_t /* reserved */ : 23;
- /* Black Odd-Odd Value Config */
- uint32_t oddOddAdjustment:9;
- uint32_t /* reserved */ : 23;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demux_cfg {
- /* Demux Gain 0 Config */
- uint32_t ch0EvenGain:10;
- uint32_t /* reserved */ : 6;
- uint32_t ch0OddGain:10;
- uint32_t /* reserved */ : 6;
- /* Demux Gain 1 Config */
- uint32_t ch1Gain:10;
- uint32_t /* reserved */ : 6;
- uint32_t ch2Gain:10;
- uint32_t /* reserved */ : 6;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_bps_info {
- uint32_t greenBadPixelCount:8;
- uint32_t /* reserved */ : 8;
- uint32_t RedBlueBadPixelCount:8;
- uint32_t /* reserved */ : 8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_cfg {
- /* Demosaic Config */
- uint32_t abfEnable:1;
- uint32_t badPixelCorrEnable:1;
- uint32_t forceAbfOn:1;
- uint32_t /* reserved */ : 1;
- uint32_t abfShift:4;
- uint32_t fminThreshold:7;
- uint32_t /* reserved */ : 1;
- uint32_t fmaxThreshold:7;
- uint32_t /* reserved */ : 5;
- uint32_t slopeShift:3;
- uint32_t /* reserved */ : 1;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_bpc_cfg {
- /* Demosaic BPC Config 0 */
- uint32_t blueDiffThreshold:12;
- uint32_t redDiffThreshold:12;
- uint32_t /* reserved */ : 8;
- /* Demosaic BPC Config 1 */
- uint32_t greenDiffThreshold:12;
- uint32_t /* reserved */ : 20;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_demosaic_abf_cfg {
- /* Demosaic ABF Config 0 */
- uint32_t lpThreshold:10;
- uint32_t /* reserved */ : 22;
- /* Demosaic ABF Config 1 */
- uint32_t ratio:4;
- uint32_t minValue:10;
- uint32_t /* reserved */ : 2;
- uint32_t maxValue:10;
- uint32_t /* reserved */ : 6;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_color_correction_cfg {
- /* Color Corr. Coefficient 0 Config */
- uint32_t c0:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 1 Config */
- uint32_t c1:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 2 Config */
- uint32_t c2:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 3 Config */
- uint32_t c3:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 4 Config */
- uint32_t c4:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 5 Config */
- uint32_t c5:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 6 Config */
- uint32_t c6:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 7 Config */
- uint32_t c7:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Coefficient 8 Config */
- uint32_t c8:12;
- uint32_t /* reserved */ : 20;
- /* Color Corr. Offset 0 Config */
- uint32_t k0:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Offset 1 Config */
- uint32_t k1:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Offset 2 Config */
- uint32_t k2:11;
- uint32_t /* reserved */ : 21;
- /* Color Corr. Coefficient Q Config */
- uint32_t coefQFactor:2;
- uint32_t /* reserved */ : 30;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_LumaAdaptation_ConfigCmdType {
- /* LA Config */
- uint32_t lutBankSelect:1;
- uint32_t /* reserved */ : 31;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_wb_cfg {
- /* WB Config */
- uint32_t ch0Gain:9;
- uint32_t ch1Gain:9;
- uint32_t ch2Gain:9;
- uint32_t /* reserved */ : 5;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_GammaLutSelect_ConfigCmdType {
- /* LUT Bank Select Config */
- uint32_t ch0BankSelect:1;
- uint32_t ch1BankSelect:1;
- uint32_t ch2BankSelect:1;
- uint32_t /* reserved */ : 29;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_chroma_enhance_cfg {
- /* Chroma Enhance A Config */
- uint32_t ap:11;
- uint32_t /* reserved */ : 5;
- uint32_t am:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance B Config */
- uint32_t bp:11;
- uint32_t /* reserved */ : 5;
- uint32_t bm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance C Config */
- uint32_t cp:11;
- uint32_t /* reserved */ : 5;
- uint32_t cm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance D Config */
- uint32_t dp:11;
- uint32_t /* reserved */ : 5;
- uint32_t dm:11;
- uint32_t /* reserved */ : 5;
- /* Chroma Enhance K Config */
- uint32_t kcb:11;
- uint32_t /* reserved */ : 5;
- uint32_t kcr:11;
- uint32_t /* reserved */ : 5;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_color_convert_cfg {
- /* Conversion Coefficient 0 */
- uint32_t v0:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Coefficient 1 */
- uint32_t v1:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Coefficient 2 */
- uint32_t v2:12;
- uint32_t /* reserved */ : 20;
- /* Conversion Offset */
- uint32_t ConvertOffset:8;
- uint32_t /* reserved */ : 24;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_SyncTimer_ConfigCmdType {
- /* Timer Line Start Config */
- uint32_t timerLineStart:12;
- uint32_t /* reserved */ : 20;
- /* Timer Pixel Start Config */
- uint32_t timerPixelStart:18;
- uint32_t /* reserved */ : 14;
- /* Timer Pixel Duration Config */
- uint32_t timerPixelDuration:28;
- uint32_t /* reserved */ : 4;
- /* Sync Timer Polarity Config */
- uint32_t timer0Polarity:1;
- uint32_t timer1Polarity:1;
- uint32_t timer2Polarity:1;
- uint32_t /* reserved */ : 29;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AsyncTimer_ConfigCmdType {
- /* Async Timer Config 0 */
- uint32_t inactiveLength:20;
- uint32_t numRepetition:10;
- uint32_t /* reserved */ : 1;
- uint32_t polarity:1;
- /* Async Timer Config 1 */
- uint32_t activeLength:20;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AWBAEStatistics_ConfigCmdType {
- /* AWB autoexposure Config */
- uint32_t aeRegionConfig:1;
- uint32_t aeSubregionConfig:1;
- uint32_t /* reserved */ : 14;
- uint32_t awbYMin:8;
- uint32_t awbYMax:8;
- /* AXW Header */
- uint32_t axwHeader:8;
- uint32_t /* reserved */ : 24;
- /* AWB Mconfig */
- uint32_t m4:8;
- uint32_t m3:8;
- uint32_t m2:8;
- uint32_t m1:8;
- /* AWB Cconfig */
- uint32_t c2:12;
- uint32_t /* reserved */ : 4;
- uint32_t c1:12;
- uint32_t /* reserved */ : 4;
- /* AWB Cconfig 2 */
- uint32_t c4:12;
- uint32_t /* reserved */ : 4;
- uint32_t c3:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_TestGen_ConfigCmdType {
- /* HW Test Gen Config */
- uint32_t numFrame:10;
- uint32_t /* reserved */ : 2;
- uint32_t pixelDataSelect:1;
- uint32_t systematicDataSelect:1;
- uint32_t /* reserved */ : 2;
- uint32_t pixelDataSize:2;
- uint32_t hsyncEdge:1;
- uint32_t vsyncEdge:1;
- uint32_t /* reserved */ : 12;
- /* HW Test Gen Image Config */
- uint32_t imageWidth:14;
- uint32_t /* reserved */ : 2;
- uint32_t imageHeight:14;
- uint32_t /* reserved */ : 2;
- /* SOF Offset Config */
- uint32_t sofOffset:24;
- uint32_t /* reserved */ : 8;
- /* EOF NOffset Config */
- uint32_t eofNOffset:24;
- uint32_t /* reserved */ : 8;
- /* SOL Offset Config */
- uint32_t solOffset:9;
- uint32_t /* reserved */ : 23;
- /* EOL NOffset Config */
- uint32_t eolNOffset:9;
- uint32_t /* reserved */ : 23;
- /* HBI Config */
- uint32_t hBlankInterval:14;
- uint32_t /* reserved */ : 18;
- /* VBL Config */
- uint32_t vBlankInterval:14;
- uint32_t /* reserved */ : 2;
- uint32_t vBlankIntervalEnable:1;
- uint32_t /* reserved */ : 15;
- /* SOF Dummy Line Config */
- uint32_t sofDummy:8;
- uint32_t /* reserved */ : 24;
- /* EOF Dummy Line Config */
- uint32_t eofDummy:8;
- uint32_t /* reserved */ : 24;
- /* Color Bars Config */
- uint32_t unicolorBarSelect:3;
- uint32_t /* reserved */ : 1;
- uint32_t unicolorBarEnable:1;
- uint32_t splitEnable:1;
- uint32_t pixelPattern:2;
- uint32_t rotatePeriod:6;
- uint32_t /* reserved */ : 18;
- /* Random Config */
- uint32_t randomSeed:16;
- uint32_t /* reserved */ : 16;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_Bus_Pm_ConfigCmdType {
- /* VFE Bus Performance Monitor Config */
- uint32_t output2YWrPmEnable:1;
- uint32_t output2CbcrWrPmEnable:1;
- uint32_t output1YWrPmEnable:1;
- uint32_t output1CbcrWrPmEnable:1;
- uint32_t /* reserved */ : 28;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_asf_info {
- /* asf max edge */
- uint32_t maxEdge:13;
- uint32_t /* reserved */ : 3;
- /* HBi count */
- uint32_t HBICount:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_camif_stats {
- uint32_t pixelCount:14;
- uint32_t /* reserved */ : 2;
- uint32_t lineCount:14;
- uint32_t /* reserved */ : 1;
- uint32_t camifHalt:1;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_StatsCmdType {
- uint32_t autoFocusEnable:1;
- uint32_t axwEnable:1;
- uint32_t histEnable:1;
- uint32_t clearHistEnable:1;
- uint32_t histAutoClearEnable:1;
- uint32_t colorConversionEnable:1;
- uint32_t /* reserved */ : 26;
-} __attribute__((packed, aligned(4)));
-
-
-struct vfe_statsframe {
- uint32_t lastPixel:12;
- uint32_t /* reserved */ : 4;
- uint32_t lastLine:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_busstats_wrprio {
- uint32_t afBusPriority:4;
- uint32_t awbBusPriority:4;
- uint32_t histBusPriority:4;
- uint32_t afBusPriorityEn:1;
- uint32_t awbBusPriorityEn:1;
- uint32_t histBusPriorityEn:1;
- uint32_t /* reserved */ : 17;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaf_update {
- /* VFE_STATS_AF_CFG */
- uint32_t windowVOffset:12;
- uint32_t /* reserved */ : 4;
- uint32_t windowHOffset:12;
- uint32_t /* reserved */ : 3;
- uint32_t windowMode:1;
-
- /* VFE_STATS_AF_DIM */
- uint32_t windowHeight:12;
- uint32_t /* reserved */ : 4;
- uint32_t windowWidth:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaf_cfg {
- /* VFE_STATS_AF_GRID_0 */
- uint32_t entry00:8;
- uint32_t entry01:8;
- uint32_t entry02:8;
- uint32_t entry03:8;
-
- /* VFE_STATS_AF_GRID_1 */
- uint32_t entry10:8;
- uint32_t entry11:8;
- uint32_t entry12:8;
- uint32_t entry13:8;
-
- /* VFE_STATS_AF_GRID_2 */
- uint32_t entry20:8;
- uint32_t entry21:8;
- uint32_t entry22:8;
- uint32_t entry23:8;
-
- /* VFE_STATS_AF_GRID_3 */
- uint32_t entry30:8;
- uint32_t entry31:8;
- uint32_t entry32:8;
- uint32_t entry33:8;
-
- /* VFE_STATS_AF_HEADER */
- uint32_t afHeader:8;
- uint32_t /* reserved */ : 24;
- /* VFE_STATS_AF_COEF0 */
- uint32_t a00:5;
- uint32_t a04:5;
- uint32_t fvMax:11;
- uint32_t fvMetric:1;
- uint32_t /* reserved */ : 10;
-
- /* VFE_STATS_AF_COEF1 */
- uint32_t a20:5;
- uint32_t a21:5;
- uint32_t a22:5;
- uint32_t a23:5;
- uint32_t a24:5;
- uint32_t /* reserved */ : 7;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsawbae_update {
- uint32_t aeRegionCfg:1;
- uint32_t aeSubregionCfg:1;
- uint32_t /* reserved */ : 14;
- uint32_t awbYMin:8;
- uint32_t awbYMax:8;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsaxw_hdr_cfg {
- /* Stats AXW Header Config */
- uint32_t axwHeader:8;
- uint32_t /* reserved */ : 24;
-} __attribute__((packed, aligned(4)));
-
-struct vfe_statsawb_update {
- /* AWB MConfig */
- uint32_t m4:8;
- uint32_t m3:8;
- uint32_t m2:8;
- uint32_t m1:8;
-
- /* AWB CConfig1 */
- uint32_t c2:12;
- uint32_t /* reserved */ : 4;
- uint32_t c1:12;
- uint32_t /* reserved */ : 4;
-
- /* AWB CConfig2 */
- uint32_t c4:12;
- uint32_t /* reserved */ : 4;
- uint32_t c3:12;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_SyncTimerCmdType {
- uint32_t hsyncCount:12;
- uint32_t /* reserved */ : 20;
- uint32_t pclkCount:18;
- uint32_t /* reserved */ : 14;
- uint32_t outputDuration:28;
- uint32_t /* reserved */ : 4;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AsyncTimerCmdType {
- /* config 0 */
- uint32_t inactiveCount:20;
- uint32_t repeatCount:10;
- uint32_t /* reserved */ : 1;
- uint32_t polarity:1;
- /* config 1 */
- uint32_t activeCount:20;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AxiInputCmdType {
- uint32_t stripeStartAddr0:32;
- uint32_t stripeStartAddr1:32;
- uint32_t stripeStartAddr2:32;
- uint32_t stripeStartAddr3:32;
-
- uint32_t ySize:12;
- uint32_t yOffsetDelta:12;
- uint32_t /* reserved */ : 8;
-
- /* bus_stripe_rd_hSize */
- uint32_t /* reserved */ : 16;
- uint32_t xSizeWord:10;
- uint32_t /* reserved */ : 6;
-
- /* bus_stripe_rd_buffer_cfg */
- uint32_t burstLength:2;
- uint32_t /* reserved */ : 2;
- uint32_t NumOfRows:12;
- uint32_t RowIncrement:12;
- uint32_t /* reserved */ : 4;
-
- /* bus_stripe_rd_unpack_cfg */
- uint32_t mainUnpackHeight:12;
- uint32_t mainUnpackWidth:13;
- uint32_t mainUnpackHbiSel:3;
- uint32_t mainUnpackPhase:3;
- uint32_t /* reserved */ : 1;
-
- /* bus_stripe_rd_unpack */
- uint32_t unpackPattern:32;
-
- /* bus_stripe_rd_pad_size */
- uint32_t padLeft:7;
- uint32_t /* reserved */ : 1;
- uint32_t padRight:7;
- uint32_t /* reserved */ : 1;
- uint32_t padTop:7;
- uint32_t /* reserved */ : 1;
- uint32_t padBottom:7;
- uint32_t /* reserved */ : 1;
-
- /* bus_stripe_rd_pad_L_unpack */
- uint32_t leftUnpackPattern0:4;
- uint32_t leftUnpackPattern1:4;
- uint32_t leftUnpackPattern2:4;
- uint32_t leftUnpackPattern3:4;
- uint32_t leftUnpackStop0:1;
- uint32_t leftUnpackStop1:1;
- uint32_t leftUnpackStop2:1;
- uint32_t leftUnpackStop3:1;
- uint32_t /* reserved */ : 12;
-
- /* bus_stripe_rd_pad_R_unpack */
- uint32_t rightUnpackPattern0:4;
- uint32_t rightUnpackPattern1:4;
- uint32_t rightUnpackPattern2:4;
- uint32_t rightUnpackPattern3:4;
- uint32_t rightUnpackStop0:1;
- uint32_t rightUnpackStop1:1;
- uint32_t rightUnpackStop2:1;
- uint32_t rightUnpackStop3:1;
- uint32_t /* reserved */ : 12;
-
- /* bus_stripe_rd_pad_tb_unpack */
- uint32_t topUnapckPattern:4;
- uint32_t /* reserved */ : 12;
- uint32_t bottomUnapckPattern:4;
- uint32_t /* reserved */ : 12;
-} __attribute__((packed, aligned(4)));
-
-struct VFE_AxiRdFragIrqEnable {
- uint32_t stripeRdFragirq0Enable:1;
- uint32_t stripeRdFragirq1Enable:1;
- uint32_t stripeRdFragirq2Enable:1;
- uint32_t stripeRdFragirq3Enable:1;
- uint32_t /* reserved */ : 28;
-} __attribute__((packed, aligned(4)));
-
-int vfe_cmd_init(struct msm_vfe_callback *, struct platform_device *, void *);
-void vfe_stats_af_stop(void);
-void vfe_stop(void);
-void vfe_update(void);
-int vfe_rgb_gamma_update(struct vfe_cmd_rgb_gamma_config *);
-int vfe_rgb_gamma_config(struct vfe_cmd_rgb_gamma_config *);
-void vfe_stats_wb_exp_ack(struct vfe_cmd_stats_wb_exp_ack *);
-void vfe_stats_af_ack(struct vfe_cmd_stats_af_ack *);
-void vfe_start(struct vfe_cmd_start *);
-void vfe_la_update(struct vfe_cmd_la_config *);
-void vfe_la_config(struct vfe_cmd_la_config *);
-void vfe_test_gen_start(struct vfe_cmd_test_gen_start *);
-void vfe_frame_skip_update(struct vfe_cmd_frame_skip_update *);
-void vfe_frame_skip_config(struct vfe_cmd_frame_skip_config *);
-void vfe_output_clamp_config(struct vfe_cmd_output_clamp_config *);
-void vfe_camif_frame_update(struct vfe_cmds_camif_frame *);
-void vfe_color_correction_config(struct vfe_cmd_color_correction_config *);
-void vfe_demosaic_abf_update(struct vfe_cmd_demosaic_abf_update *);
-void vfe_demosaic_bpc_update(struct vfe_cmd_demosaic_bpc_update *);
-void vfe_demosaic_config(struct vfe_cmd_demosaic_config *);
-void vfe_demux_channel_gain_update(struct vfe_cmd_demux_channel_gain_config *);
-void vfe_demux_channel_gain_config(struct vfe_cmd_demux_channel_gain_config *);
-void vfe_black_level_update(struct vfe_cmd_black_level_config *);
-void vfe_black_level_config(struct vfe_cmd_black_level_config *);
-void vfe_asf_update(struct vfe_cmd_asf_update *);
-void vfe_asf_config(struct vfe_cmd_asf_config *);
-void vfe_white_balance_config(struct vfe_cmd_white_balance_config *);
-void vfe_chroma_sup_config(struct vfe_cmd_chroma_suppression_config *);
-void vfe_roll_off_config(struct vfe_cmd_roll_off_config *);
-void vfe_chroma_subsample_config(struct vfe_cmd_chroma_subsample_config *);
-void vfe_chroma_enhan_config(struct vfe_cmd_chroma_enhan_config *);
-void vfe_scaler2cbcr_config(struct vfe_cmd_scaler2_config *);
-void vfe_scaler2y_config(struct vfe_cmd_scaler2_config *);
-void vfe_main_scaler_config(struct vfe_cmd_main_scaler_config *);
-void vfe_stats_wb_exp_stop(void);
-void vfe_stats_update_wb_exp(struct vfe_cmd_stats_wb_exp_update *);
-void vfe_stats_update_af(struct vfe_cmd_stats_af_update *);
-void vfe_stats_start_wb_exp(struct vfe_cmd_stats_wb_exp_start *);
-void vfe_stats_start_af(struct vfe_cmd_stats_af_start *);
-void vfe_stats_setting(struct vfe_cmd_stats_setting *);
-void vfe_axi_input_config(struct vfe_cmd_axi_input_config *);
-void vfe_stats_config(struct vfe_cmd_stats_setting *);
-void vfe_axi_output_config(struct vfe_cmd_axi_output_config *);
-void vfe_camif_config(struct vfe_cmd_camif_config *);
-void vfe_fov_crop_config(struct vfe_cmd_fov_crop_config *);
-void vfe_get_hw_version(struct vfe_cmd_hw_version *);
-void vfe_reset(void);
-void vfe_cmd_release(struct platform_device *);
-void vfe_output1_ack(struct vfe_cmd_output_ack *);
-void vfe_output2_ack(struct vfe_cmd_output_ack *);
-#endif /* __MSM_VFE8X_REG_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <media/msm_camera.h>
-#include <mach/gpio.h>
-#include "mt9d112.h"
-
-/* Micron MT9D112 Registers and their values */
-/* Sensor Core Registers */
-#define REG_MT9D112_MODEL_ID 0x3000
-#define MT9D112_MODEL_ID 0x1580
-
-/* SOC Registers Page 1 */
-#define REG_MT9D112_SENSOR_RESET 0x301A
-#define REG_MT9D112_STANDBY_CONTROL 0x3202
-#define REG_MT9D112_MCU_BOOT 0x3386
-
-struct mt9d112_work {
- struct work_struct work;
-};
-
-static struct mt9d112_work *mt9d112_sensorw;
-static struct i2c_client *mt9d112_client;
-
-struct mt9d112_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-};
-
-
-static struct mt9d112_ctrl *mt9d112_ctrl;
-
-static DECLARE_WAIT_QUEUE_HEAD(mt9d112_wait_queue);
-DEFINE_SEMAPHORE(mt9d112_sem);
-
-
-/*=============================================================
- EXTERNAL DECLARATIONS
-==============================================================*/
-extern struct mt9d112_reg mt9d112_regs;
-
-
-/*=============================================================*/
-
-static int mt9d112_reset(const struct msm_camera_sensor_info *dev)
-{
- int rc = 0;
-
- rc = gpio_request(dev->sensor_reset, "mt9d112");
-
- if (!rc) {
- rc = gpio_direction_output(dev->sensor_reset, 0);
- mdelay(20);
- rc = gpio_direction_output(dev->sensor_reset, 1);
- }
-
- gpio_free(dev->sensor_reset);
- return rc;
-}
-
-static int32_t mt9d112_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9d112_client->adapter, msg, 1) < 0) {
- CDBG("mt9d112_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9d112_i2c_write(unsigned short saddr,
- unsigned short waddr, unsigned short wdata, enum mt9d112_width width)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- switch (width) {
- case WORD_LEN: {
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9d112_i2c_txdata(saddr, buf, 4);
- }
- break;
-
- case BYTE_LEN: {
- buf[0] = waddr;
- buf[1] = wdata;
- rc = mt9d112_i2c_txdata(saddr, buf, 2);
- }
- break;
-
- default:
- break;
- }
-
- if (rc < 0)
- CDBG(
- "i2c_write failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9d112_i2c_write_table(
- struct mt9d112_i2c_reg_conf const *reg_conf_tbl,
- int num_of_items_in_table)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num_of_items_in_table; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata,
- reg_conf_tbl->width);
- if (rc < 0)
- break;
- if (reg_conf_tbl->mdelay_time != 0)
- mdelay(reg_conf_tbl->mdelay_time);
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int mt9d112_i2c_rxdata(unsigned short saddr,
- unsigned char *rxdata, int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9d112_client->adapter, msgs, 2) < 0) {
- CDBG("mt9d112_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9d112_i2c_read(unsigned short saddr,
- unsigned short raddr, unsigned short *rdata, enum mt9d112_width width)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- switch (width) {
- case WORD_LEN: {
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9d112_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
- }
- break;
-
- default:
- break;
- }
-
- if (rc < 0)
- CDBG("mt9d112_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9d112_set_lens_roll_off(void)
-{
- int32_t rc = 0;
- rc = mt9d112_i2c_write_table(&mt9d112_regs.rftbl[0],
- mt9d112_regs.rftbl_size);
- return rc;
-}
-
-static long mt9d112_reg_init(void)
-{
- int32_t array_length;
- int32_t i;
- long rc;
-
- /* PLL Setup Start */
- rc = mt9d112_i2c_write_table(&mt9d112_regs.plltbl[0],
- mt9d112_regs.plltbl_size);
-
- if (rc < 0)
- return rc;
- /* PLL Setup End */
-
- array_length = mt9d112_regs.prev_snap_reg_settings_size;
-
- /* Configure sensor for Preview mode and Snapshot mode */
- for (i = 0; i < array_length; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- mt9d112_regs.prev_snap_reg_settings[i].register_address,
- mt9d112_regs.prev_snap_reg_settings[i].register_value,
- WORD_LEN);
-
- if (rc < 0)
- return rc;
- }
-
- /* Configure for Noise Reduction, Saturation and Aperture Correction */
- array_length = mt9d112_regs.noise_reduction_reg_settings_size;
-
- for (i = 0; i < array_length; i++) {
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- mt9d112_regs.noise_reduction_reg_settings[i].register_address,
- mt9d112_regs.noise_reduction_reg_settings[i].register_value,
- WORD_LEN);
-
- if (rc < 0)
- return rc;
- }
-
- /* Set Color Kill Saturation point to optimum value */
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x35A4,
- 0x0593,
- WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write_table(&mt9d112_regs.stbl[0],
- mt9d112_regs.stbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_set_lens_roll_off();
- if (rc < 0)
- return rc;
-
- return 0;
-}
-
-static long mt9d112_set_sensor_mode(int mode)
-{
- uint16_t clock;
- long rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA20C, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0004, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA215, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0004, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA20B, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0000, WORD_LEN);
- if (rc < 0)
- return rc;
-
- clock = 0x0250;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x341C, clock, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0001, WORD_LEN);
- if (rc < 0)
- return rc;
-
- mdelay(5);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- /* Switch to lower fps for Snapshot */
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x341C, 0x0120, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA120, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0002, WORD_LEN);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc =
- mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0002, WORD_LEN);
- if (rc < 0)
- return rc;
- break;
-
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static long mt9d112_set_effect(int mode, int effect)
-{
- uint16_t reg_addr;
- uint16_t reg_val;
- long rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- /* Context A Special Effects */
- reg_addr = 0x2799;
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- /* Context B Special Effects */
- reg_addr = 0x279B;
- break;
-
- default:
- reg_addr = 0x2799;
- break;
- }
-
- switch (effect) {
- case CAMERA_EFFECT_OFF: {
- reg_val = 0x6440;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_MONO: {
- reg_val = 0x6441;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_NEGATIVE: {
- reg_val = 0x6443;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_SOLARIZE: {
- reg_val = 0x6445;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_SEPIA: {
- reg_val = 0x6442;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
- }
- break;
-
- case CAMERA_EFFECT_PASTEL:
- case CAMERA_EFFECT_MOSAIC:
- case CAMERA_EFFECT_RESIZE:
- return -EINVAL;
-
- default: {
- reg_val = 0x6440;
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, reg_addr, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, reg_val, WORD_LEN);
- if (rc < 0)
- return rc;
-
- return -EINVAL;
- }
- }
-
- /* Refresh Sequencer */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x338C, 0xA103, WORD_LEN);
- if (rc < 0)
- return rc;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x3390, 0x0005, WORD_LEN);
-
- return rc;
-}
-
-static int mt9d112_sensor_init_probe(const struct msm_camera_sensor_info *data)
-{
- uint16_t model_id = 0;
- int rc = 0;
-
- CDBG("init entry \n");
- rc = mt9d112_reset(data);
- if (rc < 0) {
- CDBG("reset failed!\n");
- goto init_probe_fail;
- }
-
- mdelay(5);
-
- /* Micron suggested Power up block Start:
- * Put MCU into Reset - Stop MCU */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_MCU_BOOT, 0x0501, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- /* Pull MCU from Reset - Start MCU */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_MCU_BOOT, 0x0500, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(5);
-
- /* Micron Suggested - Power up block */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_SENSOR_RESET, 0x0ACC, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- REG_MT9D112_STANDBY_CONTROL, 0x0008, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- /* FUSED_DEFECT_CORRECTION */
- rc = mt9d112_i2c_write(mt9d112_client->addr,
- 0x33F4, 0x031D, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(5);
-
- /* Micron suggested Power up block End */
- /* Read the Model ID of the sensor */
- rc = mt9d112_i2c_read(mt9d112_client->addr,
- REG_MT9D112_MODEL_ID, &model_id, WORD_LEN);
- if (rc < 0)
- goto init_probe_fail;
-
- CDBG("mt9d112 model_id = 0x%x\n", model_id);
-
- /* Check if it matches it with the value in Datasheet */
- if (model_id != MT9D112_MODEL_ID) {
- rc = -EINVAL;
- goto init_probe_fail;
- }
-
- rc = mt9d112_reg_init();
- if (rc < 0)
- goto init_probe_fail;
-
- return rc;
-
-init_probe_fail:
- return rc;
-}
-
-int mt9d112_sensor_init(const struct msm_camera_sensor_info *data)
-{
- int rc = 0;
-
- mt9d112_ctrl = kzalloc(sizeof(struct mt9d112_ctrl), GFP_KERNEL);
- if (!mt9d112_ctrl) {
- CDBG("mt9d112_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- if (data)
- mt9d112_ctrl->sensordata = data;
-
- /* Input MCLK = 24MHz */
- msm_camio_clk_rate_set(24000000);
- mdelay(5);
-
- msm_camio_camif_pad_reg_reset();
-
- rc = mt9d112_sensor_init_probe(data);
- if (rc < 0) {
- CDBG("mt9d112_sensor_init failed!\n");
- goto init_fail;
- }
-
-init_done:
- return rc;
-
-init_fail:
- kfree(mt9d112_ctrl);
- return rc;
-}
-
-static int mt9d112_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9d112_wait_queue);
- return 0;
-}
-
-int mt9d112_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cfg_data;
- long rc = 0;
-
- if (copy_from_user(&cfg_data,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- /* down(&mt9d112_sem); */
-
- CDBG("mt9d112_ioctl, cfgtype = %d, mode = %d\n",
- cfg_data.cfgtype, cfg_data.mode);
-
- switch (cfg_data.cfgtype) {
- case CFG_SET_MODE:
- rc = mt9d112_set_sensor_mode(
- cfg_data.mode);
- break;
-
- case CFG_SET_EFFECT:
- rc = mt9d112_set_effect(cfg_data.mode,
- cfg_data.cfg.effect);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- default:
- rc = -EINVAL;
- break;
- }
-
- /* up(&mt9d112_sem); */
-
- return rc;
-}
-
-int mt9d112_sensor_release(void)
-{
- int rc = 0;
-
- /* down(&mt9d112_sem); */
-
- kfree(mt9d112_ctrl);
- /* up(&mt9d112_sem); */
-
- return rc;
-}
-
-static int mt9d112_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- rc = -ENOTSUPP;
- goto probe_failure;
- }
-
- mt9d112_sensorw =
- kzalloc(sizeof(struct mt9d112_work), GFP_KERNEL);
-
- if (!mt9d112_sensorw) {
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9d112_sensorw);
- mt9d112_init_client(client);
- mt9d112_client = client;
-
- CDBG("mt9d112_probe succeeded!\n");
-
- return 0;
-
-probe_failure:
- kfree(mt9d112_sensorw);
- mt9d112_sensorw = NULL;
- CDBG("mt9d112_probe failed!\n");
- return rc;
-}
-
-static const struct i2c_device_id mt9d112_i2c_id[] = {
- { "mt9d112", 0},
- { },
-};
-
-static struct i2c_driver mt9d112_i2c_driver = {
- .id_table = mt9d112_i2c_id,
- .probe = mt9d112_i2c_probe,
- .remove = __exit_p(mt9d112_i2c_remove),
- .driver = {
- .name = "mt9d112",
- },
-};
-
-static int mt9d112_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = i2c_add_driver(&mt9d112_i2c_driver);
- if (rc < 0 || mt9d112_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- /* Input MCLK = 24MHz */
- msm_camio_clk_rate_set(24000000);
- mdelay(5);
-
- rc = mt9d112_sensor_init_probe(info);
- if (rc < 0)
- goto probe_done;
-
- s->s_init = mt9d112_sensor_init;
- s->s_release = mt9d112_sensor_release;
- s->s_config = mt9d112_sensor_config;
-
-probe_done:
- CDBG("%s %s:%d\n", __FILE__, __func__, __LINE__);
- return rc;
-}
-
-static int __mt9d112_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9d112_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9d112_probe,
- .driver = {
- .name = "msm_camera_mt9d112",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9d112_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9d112_init);
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef MT9D112_H
-#define MT9D112_H
-
-#include <linux/types.h>
-#include <mach/camera.h>
-
-enum mt9d112_width {
- WORD_LEN,
- BYTE_LEN
-};
-
-struct mt9d112_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
- enum mt9d112_width width;
- unsigned short mdelay_time;
-};
-
-struct mt9d112_reg {
- const struct register_address_value_pair *prev_snap_reg_settings;
- uint16_t prev_snap_reg_settings_size;
- const struct register_address_value_pair *noise_reduction_reg_settings;
- uint16_t noise_reduction_reg_settings_size;
- const struct mt9d112_i2c_reg_conf *plltbl;
- uint16_t plltbl_size;
- const struct mt9d112_i2c_reg_conf *stbl;
- uint16_t stbl_size;
- const struct mt9d112_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* MT9D112_H */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include "mt9d112.h"
-
-struct register_address_value_pair
-preview_snapshot_mode_reg_settings_array[] = {
- {0x338C, 0x2703},
- {0x3390, 800}, /* Output Width (P) = 640 */
- {0x338C, 0x2705},
- {0x3390, 600}, /* Output Height (P) = 480 */
- {0x338C, 0x2707},
- {0x3390, 0x0640}, /* Output Width (S) = 1600 */
- {0x338C, 0x2709},
- {0x3390, 0x04B0}, /* Output Height (S) = 1200 */
- {0x338C, 0x270D},
- {0x3390, 0x0000}, /* Row Start (P) = 0 */
- {0x338C, 0x270F},
- {0x3390, 0x0000}, /* Column Start (P) = 0 */
- {0x338C, 0x2711},
- {0x3390, 0x04BD}, /* Row End (P) = 1213 */
- {0x338C, 0x2713},
- {0x3390, 0x064D}, /* Column End (P) = 1613 */
- {0x338C, 0x2715},
- {0x3390, 0x0000}, /* Extra Delay (P) = 0 */
- {0x338C, 0x2717},
- {0x3390, 0x2111}, /* Row Speed (P) = 8465 */
- {0x338C, 0x2719},
- {0x3390, 0x046C}, /* Read Mode (P) = 1132 */
- {0x338C, 0x271B},
- {0x3390, 0x024F}, /* Sensor_Sample_Time_pck(P) = 591 */
- {0x338C, 0x271D},
- {0x3390, 0x0102}, /* Sensor_Fine_Correction(P) = 258 */
- {0x338C, 0x271F},
- {0x3390, 0x0279}, /* Sensor_Fine_IT_min(P) = 633 */
- {0x338C, 0x2721},
- {0x3390, 0x0155}, /* Sensor_Fine_IT_max_margin(P) = 341 */
- {0x338C, 0x2723},
- {0x3390, 659}, /* Frame Lines (P) = 679 */
- {0x338C, 0x2725},
- {0x3390, 0x0824}, /* Line Length (P) = 2084 */
- {0x338C, 0x2727},
- {0x3390, 0x2020},
- {0x338C, 0x2729},
- {0x3390, 0x2020},
- {0x338C, 0x272B},
- {0x3390, 0x1020},
- {0x338C, 0x272D},
- {0x3390, 0x2007},
- {0x338C, 0x272F},
- {0x3390, 0x0004}, /* Row Start(S) = 4 */
- {0x338C, 0x2731},
- {0x3390, 0x0004}, /* Column Start(S) = 4 */
- {0x338C, 0x2733},
- {0x3390, 0x04BB}, /* Row End(S) = 1211 */
- {0x338C, 0x2735},
- {0x3390, 0x064B}, /* Column End(S) = 1611 */
- {0x338C, 0x2737},
- {0x3390, 0x04CE}, /* Extra Delay(S) = 1230 */
- {0x338C, 0x2739},
- {0x3390, 0x2111}, /* Row Speed(S) = 8465 */
- {0x338C, 0x273B},
- {0x3390, 0x0024}, /* Read Mode(S) = 36 */
- {0x338C, 0x273D},
- {0x3390, 0x0120}, /* Sensor sample time pck(S) = 288 */
- {0x338C, 0x2741},
- {0x3390, 0x0169}, /* Sensor_Fine_IT_min(P) = 361 */
- {0x338C, 0x2745},
- {0x3390, 0x04FF}, /* Frame Lines(S) = 1279 */
- {0x338C, 0x2747},
- {0x3390, 0x0824}, /* Line Length(S) = 2084 */
- {0x338C, 0x2751},
- {0x3390, 0x0000}, /* Crop_X0(P) = 0 */
- {0x338C, 0x2753},
- {0x3390, 0x0320}, /* Crop_X1(P) = 800 */
- {0x338C, 0x2755},
- {0x3390, 0x0000}, /* Crop_Y0(P) = 0 */
- {0x338C, 0x2757},
- {0x3390, 0x0258}, /* Crop_Y1(P) = 600 */
- {0x338C, 0x275F},
- {0x3390, 0x0000}, /* Crop_X0(S) = 0 */
- {0x338C, 0x2761},
- {0x3390, 0x0640}, /* Crop_X1(S) = 1600 */
- {0x338C, 0x2763},
- {0x3390, 0x0000}, /* Crop_Y0(S) = 0 */
- {0x338C, 0x2765},
- {0x3390, 0x04B0}, /* Crop_Y1(S) = 1200 */
- {0x338C, 0x222E},
- {0x3390, 0x00A0}, /* R9 Step = 160 */
- {0x338C, 0xA408},
- {0x3390, 0x001F},
- {0x338C, 0xA409},
- {0x3390, 0x0021},
- {0x338C, 0xA40A},
- {0x3390, 0x0025},
- {0x338C, 0xA40B},
- {0x3390, 0x0027},
- {0x338C, 0x2411},
- {0x3390, 0x00A0},
- {0x338C, 0x2413},
- {0x3390, 0x00C0},
- {0x338C, 0x2415},
- {0x3390, 0x00A0},
- {0x338C, 0x2417},
- {0x3390, 0x00C0},
- {0x338C, 0x2799},
- {0x3390, 0x6408}, /* MODE_SPEC_EFFECTS(P) */
- {0x338C, 0x279B},
- {0x3390, 0x6408}, /* MODE_SPEC_EFFECTS(S) */
-};
-
-static struct register_address_value_pair
-noise_reduction_reg_settings_array[] = {
- {0x338C, 0xA76D},
- {0x3390, 0x0003},
- {0x338C, 0xA76E},
- {0x3390, 0x0003},
- {0x338C, 0xA76F},
- {0x3390, 0},
- {0x338C, 0xA770},
- {0x3390, 21},
- {0x338C, 0xA771},
- {0x3390, 37},
- {0x338C, 0xA772},
- {0x3390, 63},
- {0x338C, 0xA773},
- {0x3390, 100},
- {0x338C, 0xA774},
- {0x3390, 128},
- {0x338C, 0xA775},
- {0x3390, 151},
- {0x338C, 0xA776},
- {0x3390, 169},
- {0x338C, 0xA777},
- {0x3390, 186},
- {0x338C, 0xA778},
- {0x3390, 199},
- {0x338C, 0xA779},
- {0x3390, 210},
- {0x338C, 0xA77A},
- {0x3390, 220},
- {0x338C, 0xA77B},
- {0x3390, 228},
- {0x338C, 0xA77C},
- {0x3390, 234},
- {0x338C, 0xA77D},
- {0x3390, 240},
- {0x338C, 0xA77E},
- {0x3390, 244},
- {0x338C, 0xA77F},
- {0x3390, 248},
- {0x338C, 0xA780},
- {0x3390, 252},
- {0x338C, 0xA781},
- {0x3390, 255},
- {0x338C, 0xA782},
- {0x3390, 0},
- {0x338C, 0xA783},
- {0x3390, 21},
- {0x338C, 0xA784},
- {0x3390, 37},
- {0x338C, 0xA785},
- {0x3390, 63},
- {0x338C, 0xA786},
- {0x3390, 100},
- {0x338C, 0xA787},
- {0x3390, 128},
- {0x338C, 0xA788},
- {0x3390, 151},
- {0x338C, 0xA789},
- {0x3390, 169},
- {0x338C, 0xA78A},
- {0x3390, 186},
- {0x338C, 0xA78B},
- {0x3390, 199},
- {0x338C, 0xA78C},
- {0x3390, 210},
- {0x338C, 0xA78D},
- {0x3390, 220},
- {0x338C, 0xA78E},
- {0x3390, 228},
- {0x338C, 0xA78F},
- {0x3390, 234},
- {0x338C, 0xA790},
- {0x3390, 240},
- {0x338C, 0xA791},
- {0x3390, 244},
- {0x338C, 0xA793},
- {0x3390, 252},
- {0x338C, 0xA794},
- {0x3390, 255},
- {0x338C, 0xA103},
- {0x3390, 6},
-};
-
-static const struct mt9d112_i2c_reg_conf const lens_roll_off_tbl[] = {
- { 0x34CE, 0x81A0, WORD_LEN, 0 },
- { 0x34D0, 0x6331, WORD_LEN, 0 },
- { 0x34D2, 0x3394, WORD_LEN, 0 },
- { 0x34D4, 0x9966, WORD_LEN, 0 },
- { 0x34D6, 0x4B25, WORD_LEN, 0 },
- { 0x34D8, 0x2670, WORD_LEN, 0 },
- { 0x34DA, 0x724C, WORD_LEN, 0 },
- { 0x34DC, 0xFFFD, WORD_LEN, 0 },
- { 0x34DE, 0x00CA, WORD_LEN, 0 },
- { 0x34E6, 0x00AC, WORD_LEN, 0 },
- { 0x34EE, 0x0EE1, WORD_LEN, 0 },
- { 0x34F6, 0x0D87, WORD_LEN, 0 },
- { 0x3500, 0xE1F7, WORD_LEN, 0 },
- { 0x3508, 0x1CF4, WORD_LEN, 0 },
- { 0x3510, 0x1D28, WORD_LEN, 0 },
- { 0x3518, 0x1F26, WORD_LEN, 0 },
- { 0x3520, 0x2220, WORD_LEN, 0 },
- { 0x3528, 0x333D, WORD_LEN, 0 },
- { 0x3530, 0x15D9, WORD_LEN, 0 },
- { 0x3538, 0xCFB8, WORD_LEN, 0 },
- { 0x354C, 0x05FE, WORD_LEN, 0 },
- { 0x3544, 0x05F8, WORD_LEN, 0 },
- { 0x355C, 0x0596, WORD_LEN, 0 },
- { 0x3554, 0x0611, WORD_LEN, 0 },
- { 0x34E0, 0x00F2, WORD_LEN, 0 },
- { 0x34E8, 0x00A8, WORD_LEN, 0 },
- { 0x34F0, 0x0F7B, WORD_LEN, 0 },
- { 0x34F8, 0x0CD7, WORD_LEN, 0 },
- { 0x3502, 0xFEDB, WORD_LEN, 0 },
- { 0x350A, 0x13E4, WORD_LEN, 0 },
- { 0x3512, 0x1F2C, WORD_LEN, 0 },
- { 0x351A, 0x1D20, WORD_LEN, 0 },
- { 0x3522, 0x2422, WORD_LEN, 0 },
- { 0x352A, 0x2925, WORD_LEN, 0 },
- { 0x3532, 0x1D04, WORD_LEN, 0 },
- { 0x353A, 0xFBF2, WORD_LEN, 0 },
- { 0x354E, 0x0616, WORD_LEN, 0 },
- { 0x3546, 0x0597, WORD_LEN, 0 },
- { 0x355E, 0x05CD, WORD_LEN, 0 },
- { 0x3556, 0x0529, WORD_LEN, 0 },
- { 0x34E4, 0x00B2, WORD_LEN, 0 },
- { 0x34EC, 0x005E, WORD_LEN, 0 },
- { 0x34F4, 0x0F43, WORD_LEN, 0 },
- { 0x34FC, 0x0E2F, WORD_LEN, 0 },
- { 0x3506, 0xF9FC, WORD_LEN, 0 },
- { 0x350E, 0x0CE4, WORD_LEN, 0 },
- { 0x3516, 0x1E1E, WORD_LEN, 0 },
- { 0x351E, 0x1B19, WORD_LEN, 0 },
- { 0x3526, 0x151B, WORD_LEN, 0 },
- { 0x352E, 0x1416, WORD_LEN, 0 },
- { 0x3536, 0x10FC, WORD_LEN, 0 },
- { 0x353E, 0xC018, WORD_LEN, 0 },
- { 0x3552, 0x06B4, WORD_LEN, 0 },
- { 0x354A, 0x0506, WORD_LEN, 0 },
- { 0x3562, 0x06AB, WORD_LEN, 0 },
- { 0x355A, 0x063A, WORD_LEN, 0 },
- { 0x34E2, 0x00E5, WORD_LEN, 0 },
- { 0x34EA, 0x008B, WORD_LEN, 0 },
- { 0x34F2, 0x0E4C, WORD_LEN, 0 },
- { 0x34FA, 0x0CA3, WORD_LEN, 0 },
- { 0x3504, 0x0907, WORD_LEN, 0 },
- { 0x350C, 0x1DFD, WORD_LEN, 0 },
- { 0x3514, 0x1E24, WORD_LEN, 0 },
- { 0x351C, 0x2529, WORD_LEN, 0 },
- { 0x3524, 0x1D20, WORD_LEN, 0 },
- { 0x352C, 0x2332, WORD_LEN, 0 },
- { 0x3534, 0x10E9, WORD_LEN, 0 },
- { 0x353C, 0x0BCB, WORD_LEN, 0 },
- { 0x3550, 0x04EF, WORD_LEN, 0 },
- { 0x3548, 0x0609, WORD_LEN, 0 },
- { 0x3560, 0x0580, WORD_LEN, 0 },
- { 0x3558, 0x05DD, WORD_LEN, 0 },
- { 0x3540, 0x0000, WORD_LEN, 0 },
- { 0x3542, 0x0000, WORD_LEN, 0 }
-};
-
-static const struct mt9d112_i2c_reg_conf const pll_setup_tbl[] = {
- { 0x341E, 0x8F09, WORD_LEN, 0 },
- { 0x341C, 0x0250, WORD_LEN, 0 },
- { 0x341E, 0x8F09, WORD_LEN, 5 },
- { 0x341E, 0x8F08, WORD_LEN, 0 }
-};
-
-/* Refresh Sequencer */
-static const struct mt9d112_i2c_reg_conf const sequencer_tbl[] = {
- { 0x338C, 0x2799, WORD_LEN, 0},
- { 0x3390, 0x6440, WORD_LEN, 5},
- { 0x338C, 0x279B, WORD_LEN, 0},
- { 0x3390, 0x6440, WORD_LEN, 5},
- { 0x338C, 0xA103, WORD_LEN, 0},
- { 0x3390, 0x0005, WORD_LEN, 5},
- { 0x338C, 0xA103, WORD_LEN, 0},
- { 0x3390, 0x0006, WORD_LEN, 5}
-};
-
-struct mt9d112_reg mt9d112_regs = {
- .prev_snap_reg_settings = &preview_snapshot_mode_reg_settings_array[0],
- .prev_snap_reg_settings_size = ARRAY_SIZE(preview_snapshot_mode_reg_settings_array),
- .noise_reduction_reg_settings = &noise_reduction_reg_settings_array[0],
- .noise_reduction_reg_settings_size = ARRAY_SIZE(noise_reduction_reg_settings_array),
- .plltbl = pll_setup_tbl,
- .plltbl_size = ARRAY_SIZE(pll_setup_tbl),
- .stbl = sequencer_tbl,
- .stbl_size = ARRAY_SIZE(sequencer_tbl),
- .rftbl = lens_roll_off_tbl,
- .rftbl_size = ARRAY_SIZE(lens_roll_off_tbl)
-};
-
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-
-#ifndef MT9T012_H
-#define MT9T012_H
-
-#include <linux/types.h>
-
-struct reg_struct {
- uint16_t vt_pix_clk_div; /* 0x0300 */
- uint16_t vt_sys_clk_div; /* 0x0302 */
- uint16_t pre_pll_clk_div; /* 0x0304 */
- uint16_t pll_multiplier; /* 0x0306 */
- uint16_t op_pix_clk_div; /* 0x0308 */
- uint16_t op_sys_clk_div; /* 0x030A */
- uint16_t scale_m; /* 0x0404 */
- uint16_t row_speed; /* 0x3016 */
- uint16_t x_addr_start; /* 0x3004 */
- uint16_t x_addr_end; /* 0x3008 */
- uint16_t y_addr_start; /* 0x3002 */
- uint16_t y_addr_end; /* 0x3006 */
- uint16_t read_mode; /* 0x3040 */
- uint16_t x_output_size ; /* 0x034C */
- uint16_t y_output_size; /* 0x034E */
- uint16_t line_length_pck; /* 0x300C */
- uint16_t frame_length_lines; /* 0x300A */
- uint16_t coarse_int_time; /* 0x3012 */
- uint16_t fine_int_time; /* 0x3014 */
-};
-
-
-struct mt9p012_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
-};
-
-
-struct mt9p012_reg {
- struct reg_struct *reg_pat;
- uint16_t reg_pat_size;
- struct mt9p012_i2c_reg_conf *ttbl;
- uint16_t ttbl_size;
- struct mt9p012_i2c_reg_conf *lctbl;
- uint16_t lctbl_size;
- struct mt9p012_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* MT9T012_H */
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/kernel.h>
-#include <media/msm_camera.h>
-#include <mach/gpio.h>
-#include <mach/camera.h>
-#include "mt9p012.h"
-
-/*=============================================================
- SENSOR REGISTER DEFINES
-==============================================================*/
-#define MT9P012_REG_MODEL_ID 0x0000
-#define MT9P012_MODEL_ID 0x2801
-#define REG_GROUPED_PARAMETER_HOLD 0x0104
-#define GROUPED_PARAMETER_HOLD 0x0100
-#define GROUPED_PARAMETER_UPDATE 0x0000
-#define REG_COARSE_INT_TIME 0x3012
-#define REG_VT_PIX_CLK_DIV 0x0300
-#define REG_VT_SYS_CLK_DIV 0x0302
-#define REG_PRE_PLL_CLK_DIV 0x0304
-#define REG_PLL_MULTIPLIER 0x0306
-#define REG_OP_PIX_CLK_DIV 0x0308
-#define REG_OP_SYS_CLK_DIV 0x030A
-#define REG_SCALE_M 0x0404
-#define REG_FRAME_LENGTH_LINES 0x300A
-#define REG_LINE_LENGTH_PCK 0x300C
-#define REG_X_ADDR_START 0x3004
-#define REG_Y_ADDR_START 0x3002
-#define REG_X_ADDR_END 0x3008
-#define REG_Y_ADDR_END 0x3006
-#define REG_X_OUTPUT_SIZE 0x034C
-#define REG_Y_OUTPUT_SIZE 0x034E
-#define REG_FINE_INTEGRATION_TIME 0x3014
-#define REG_ROW_SPEED 0x3016
-#define MT9P012_REG_RESET_REGISTER 0x301A
-#define MT9P012_RESET_REGISTER_PWON 0x10CC
-#define MT9P012_RESET_REGISTER_PWOFF 0x10C8
-#define REG_READ_MODE 0x3040
-#define REG_GLOBAL_GAIN 0x305E
-#define REG_TEST_PATTERN_MODE 0x3070
-
-#define MT9P012_REV_7
-
-
-enum mt9p012_test_mode {
- TEST_OFF,
- TEST_1,
- TEST_2,
- TEST_3
-};
-
-enum mt9p012_resolution {
- QTR_SIZE,
- FULL_SIZE,
- INVALID_SIZE
-};
-
-enum mt9p012_reg_update {
- /* Sensor egisters that need to be updated during initialization */
- REG_INIT,
- /* Sensor egisters that needs periodic I2C writes */
- UPDATE_PERIODIC,
- /* All the sensor Registers will be updated */
- UPDATE_ALL,
- /* Not valid update */
- UPDATE_INVALID
-};
-
-enum mt9p012_setting {
- RES_PREVIEW,
- RES_CAPTURE
-};
-
-/* actuator's Slave Address */
-#define MT9P012_AF_I2C_ADDR 0x18
-
-/* AF Total steps parameters */
-#define MT9P012_STEPS_NEAR_TO_CLOSEST_INF 32
-#define MT9P012_TOTAL_STEPS_NEAR_TO_FAR 32
-
-#define MT9P012_MU5M0_PREVIEW_DUMMY_PIXELS 0
-#define MT9P012_MU5M0_PREVIEW_DUMMY_LINES 0
-
-/* Time in milisecs for waiting for the sensor to reset.*/
-#define MT9P012_RESET_DELAY_MSECS 66
-
-/* for 20 fps preview */
-#define MT9P012_DEFAULT_CLOCK_RATE 24000000
-#define MT9P012_DEFAULT_MAX_FPS 26 /* ???? */
-
-struct mt9p012_work {
- struct work_struct work;
-};
-static struct mt9p012_work *mt9p012_sensorw;
-static struct i2c_client *mt9p012_client;
-
-struct mt9p012_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum mt9p012_resolution prev_res;
- enum mt9p012_resolution pict_res;
- enum mt9p012_resolution curr_res;
- enum mt9p012_test_mode set_test;
-};
-
-
-static struct mt9p012_ctrl *mt9p012_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(mt9p012_wait_queue);
-DEFINE_SEMAPHORE(mt9p012_sem);
-
-/*=============================================================
- EXTERNAL DECLARATIONS
-==============================================================*/
-extern struct mt9p012_reg mt9p012_regs; /* from mt9p012_reg.c */
-
-
-
-/*=============================================================*/
-
-static int mt9p012_i2c_rxdata(unsigned short saddr, unsigned char *rxdata,
- int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9p012_client->adapter, msgs, 2) < 0) {
- CDBG("mt9p012_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9p012_i2c_read_w(unsigned short saddr, unsigned short raddr,
- unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9p012_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- CDBG("mt9p012_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_txdata(unsigned short saddr, unsigned char *txdata,
- int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9p012_client->adapter, msg, 1) < 0) {
- CDBG("mt9p012_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9p012_i2c_write_b(unsigned short saddr, unsigned short baddr,
- unsigned short bdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[2];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = baddr;
- buf[1] = bdata;
- rc = mt9p012_i2c_txdata(saddr, buf, 2);
-
- if (rc < 0)
- CDBG("i2c_write failed, saddr = 0x%x addr = 0x%x, val =0x%x!\n",
- saddr, baddr, bdata);
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_write_w(unsigned short saddr, unsigned short waddr,
- unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9p012_i2c_txdata(saddr, buf, 4);
-
- if (rc < 0)
- CDBG("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9p012_i2c_write_w_table(
- struct mt9p012_i2c_reg_conf *reg_conf_tbl, int num)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num; i++) {
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata);
- if (rc < 0)
- break;
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int32_t mt9p012_test(enum mt9p012_test_mode mo)
-{
- int32_t rc = 0;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- if (mo == TEST_OFF)
- return 0;
- else {
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.ttbl, mt9p012_regs.ttbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
- if (rc < 0)
- return rc;
- }
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9p012_lens_shading_enable(uint8_t is_enable)
-{
- int32_t rc = 0;
-
- CDBG("%s: entered. enable = %d\n", __func__, is_enable);
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x3780,
- ((uint16_t) is_enable) << 15);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE);
-
- CDBG("%s: exiting. rc = %d\n", __func__, rc);
- return rc;
-}
-
-static int32_t mt9p012_set_lc(void)
-{
- int32_t rc;
-
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.lctbl, mt9p012_regs.lctbl_size);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w_table(mt9p012_regs.rftbl, mt9p012_regs.rftbl_size);
-
- return rc;
-}
-
-static void mt9p012_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /*Q10 */
- uint32_t pclk_mult; /*Q10 */
-
- if (mt9p012_ctrl->prev_res == QTR_SIZE) {
- divider = (uint32_t)
- (((mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines *
- mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck) * 0x00000400) /
- (mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines *
- mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck));
-
- pclk_mult =
- (uint32_t) ((mt9p012_regs.reg_pat[RES_CAPTURE].pll_multiplier *
- 0x00000400) / (mt9p012_regs.reg_pat[RES_PREVIEW].pll_multiplier));
- } else {
- /* full size resolution used for preview. */
- divider = 0x00000400; /*1.0 */
- pclk_mult = 0x00000400; /*1.0 */
- }
-
- /* Verify PCLK settings and frame sizes. */
- *pfps = (uint16_t) (fps * divider * pclk_mult / 0x00000400 /
- 0x00000400);
-}
-
-static uint16_t mt9p012_get_prev_lines_pf(void)
-{
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- return mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines;
- else
- return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9p012_get_prev_pixels_pl(void)
-{
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- return mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck;
- else
- return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint16_t mt9p012_get_pict_lines_pf(void)
-{
- return mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9p012_get_pict_pixels_pl(void)
-{
- return mt9p012_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint32_t mt9p012_get_pict_max_exp_lc(void)
-{
- uint16_t snapshot_lines_per_frame;
-
- if (mt9p012_ctrl->pict_res == QTR_SIZE)
- snapshot_lines_per_frame =
- mt9p012_regs.reg_pat[RES_PREVIEW].frame_length_lines - 1;
- else
- snapshot_lines_per_frame =
- mt9p012_regs.reg_pat[RES_CAPTURE].frame_length_lines - 1;
-
- return snapshot_lines_per_frame * 24;
-}
-
-static int32_t mt9p012_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q10 format */
- int32_t rc = 0;
-
- mt9p012_ctrl->fps_divider = fps->fps_div;
- mt9p012_ctrl->pict_fps_divider = fps->pict_fps_div;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return -EBUSY;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_LINE_LENGTH_PCK,
- (mt9p012_regs.reg_pat[RES_PREVIEW].line_length_pck *
- fps->f_mult / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
-
- return rc;
-}
-
-static int32_t mt9p012_write_exp_gain(uint16_t gain, uint32_t line)
-{
- uint16_t max_legal_gain = 0x01FF;
- uint32_t line_length_ratio = 0x00000400;
- enum mt9p012_setting setting;
- int32_t rc = 0;
-
- CDBG("Line:%d mt9p012_write_exp_gain \n", __LINE__);
-
- if (mt9p012_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
- mt9p012_ctrl->my_reg_gain = gain;
- mt9p012_ctrl->my_reg_line_count = (uint16_t)line;
- }
-
- if (gain > max_legal_gain) {
- CDBG("Max legal gain Line:%d \n", __LINE__);
- gain = max_legal_gain;
- }
-
- /* Verify no overflow */
- if (mt9p012_ctrl->sensormode != SENSOR_SNAPSHOT_MODE) {
- line = (uint32_t)(line * mt9p012_ctrl->fps_divider /
- 0x00000400);
- setting = RES_PREVIEW;
- } else {
- line = (uint32_t)(line * mt9p012_ctrl->pict_fps_divider /
- 0x00000400);
- setting = RES_CAPTURE;
- }
-
- /* Set digital gain to 1 */
-#ifdef MT9P012_REV_7
- gain |= 0x1000;
-#else
- gain |= 0x0200;
-#endif
-
- if ((mt9p012_regs.reg_pat[setting].frame_length_lines - 1) < line) {
- line_length_ratio = (uint32_t) (line * 0x00000400) /
- (mt9p012_regs.reg_pat[setting].frame_length_lines - 1);
- } else
- line_length_ratio = 0x00000400;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(
- mt9p012_client->addr,
- REG_GLOBAL_GAIN, gain);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_COARSE_INT_TIME,
- line);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- CDBG("mt9p012_write_exp_gain: gain = %d, line = %d\n", gain, line);
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
-
- return rc;
-}
-
-static int32_t mt9p012_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- CDBG("Line:%d mt9p012_set_pict_exp_gain \n", __LINE__);
-
- rc =
- mt9p012_write_exp_gain(gain, line);
- if (rc < 0) {
- CDBG("Line:%d mt9p012_set_pict_exp_gain failed... \n",
- __LINE__);
- return rc;
- }
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- 0x10CC | 0x0002);
- if (rc < 0) {
- CDBG("mt9p012_i2c_write_w failed... Line:%d \n", __LINE__);
- return rc;
- }
-
- mdelay(5);
-
- /* camera_timed_wait(snapshot_wait*exposure_ratio); */
- return rc;
-}
-
-static int32_t mt9p012_setting(enum mt9p012_reg_update rupdate,
- enum mt9p012_setting rt)
-{
- int32_t rc = 0;
-
- switch (rupdate) {
- case UPDATE_PERIODIC:
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-
- struct mt9p012_i2c_reg_conf ppc_tbl[] = {
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD},
- {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
- {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
- {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
- {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
- {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
- {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
- {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
- {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
- {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
-
- {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
- {REG_FRAME_LENGTH_LINES,
- (mt9p012_regs.reg_pat[rt].frame_length_lines *
- mt9p012_ctrl->fps_divider / 0x00000400)},
- {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
- {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE},
- };
-
- rc = mt9p012_i2c_write_w_table(&ppc_tbl[0],
- ARRAY_SIZE(ppc_tbl));
- if (rc < 0)
- return rc;
-
- rc = mt9p012_test(mt9p012_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- MT9P012_RESET_REGISTER_PWON | 0x0002);
- if (rc < 0)
- return rc;
-
- mdelay(5); /* 15? wait for sensor to transition*/
-
- return rc;
- }
- break; /* UPDATE_PERIODIC */
-
- case REG_INIT:
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
- struct mt9p012_i2c_reg_conf ipc_tbl1[] = {
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWOFF},
- {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
- {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
- {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
-#ifdef MT9P012_REV_7
- {0x30B0, 0x0001},
- {0x308E, 0xE060},
- {0x3092, 0x0A52},
- {0x3094, 0x4656},
- {0x3096, 0x5652},
- {0x30CA, 0x8006},
- {0x312A, 0xDD02},
- {0x312C, 0x00E4},
- {0x3170, 0x299A},
-#endif
- /* optimized settings for noise */
- {0x3088, 0x6FF6},
- {0x3154, 0x0282},
- {0x3156, 0x0381},
- {0x3162, 0x04CE},
- {0x0204, 0x0010},
- {0x0206, 0x0010},
- {0x0208, 0x0010},
- {0x020A, 0x0010},
- {0x020C, 0x0010},
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON},
- };
-
- struct mt9p012_i2c_reg_conf ipc_tbl2[] = {
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWOFF},
- {REG_VT_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].vt_sys_clk_div},
- {REG_PRE_PLL_CLK_DIV, mt9p012_regs.reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER, mt9p012_regs.reg_pat[rt].pll_multiplier},
- {REG_OP_PIX_CLK_DIV, mt9p012_regs.reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, mt9p012_regs.reg_pat[rt].op_sys_clk_div},
-#ifdef MT9P012_REV_7
- {0x30B0, 0x0001},
- {0x308E, 0xE060},
- {0x3092, 0x0A52},
- {0x3094, 0x4656},
- {0x3096, 0x5652},
- {0x30CA, 0x8006},
- {0x312A, 0xDD02},
- {0x312C, 0x00E4},
- {0x3170, 0x299A},
-#endif
- /* optimized settings for noise */
- {0x3088, 0x6FF6},
- {0x3154, 0x0282},
- {0x3156, 0x0381},
- {0x3162, 0x04CE},
- {0x0204, 0x0010},
- {0x0206, 0x0010},
- {0x0208, 0x0010},
- {0x020A, 0x0010},
- {0x020C, 0x0010},
- {MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON},
- };
-
- struct mt9p012_i2c_reg_conf ipc_tbl3[] = {
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD},
- /* Set preview or snapshot mode */
- {REG_ROW_SPEED, mt9p012_regs.reg_pat[rt].row_speed},
- {REG_X_ADDR_START, mt9p012_regs.reg_pat[rt].x_addr_start},
- {REG_X_ADDR_END, mt9p012_regs.reg_pat[rt].x_addr_end},
- {REG_Y_ADDR_START, mt9p012_regs.reg_pat[rt].y_addr_start},
- {REG_Y_ADDR_END, mt9p012_regs.reg_pat[rt].y_addr_end},
- {REG_READ_MODE, mt9p012_regs.reg_pat[rt].read_mode},
- {REG_SCALE_M, mt9p012_regs.reg_pat[rt].scale_m},
- {REG_X_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].x_output_size},
- {REG_Y_OUTPUT_SIZE, mt9p012_regs.reg_pat[rt].y_output_size},
- {REG_LINE_LENGTH_PCK, mt9p012_regs.reg_pat[rt].line_length_pck},
- {REG_FRAME_LENGTH_LINES,
- mt9p012_regs.reg_pat[rt].frame_length_lines},
- {REG_COARSE_INT_TIME, mt9p012_regs.reg_pat[rt].coarse_int_time},
- {REG_FINE_INTEGRATION_TIME, mt9p012_regs.reg_pat[rt].fine_int_time},
- {REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE},
- };
-
- /* reset fps_divider */
- mt9p012_ctrl->fps_divider = 1 * 0x0400;
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl1[0],
- ARRAY_SIZE(ipc_tbl1));
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl2[0],
- ARRAY_SIZE(ipc_tbl2));
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc = mt9p012_i2c_write_w_table(&ipc_tbl3[0],
- ARRAY_SIZE(ipc_tbl3));
- if (rc < 0)
- return rc;
-
- /* load lens shading */
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc = mt9p012_set_lc();
- if (rc < 0)
- return rc;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- REG_GROUPED_PARAMETER_HOLD, GROUPED_PARAMETER_UPDATE);
-
- if (rc < 0)
- return rc;
- }
- break; /* case REG_INIT: */
-
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int32_t mt9p012_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case QTR_SIZE:
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_PREVIEW);
- if (rc < 0)
- return rc;
-
- CDBG("mt9p012 sensor configuration done!\n");
- break;
-
- case FULL_SIZE:
- rc =
- mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- break;
-
- default:
- return 0;
- } /* switch */
-
- mt9p012_ctrl->prev_res = res;
- mt9p012_ctrl->curr_res = res;
- mt9p012_ctrl->sensormode = mode;
-
- rc =
- mt9p012_write_exp_gain(mt9p012_ctrl->my_reg_gain,
- mt9p012_ctrl->my_reg_line_count);
-
- rc =
- mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- 0x10cc|0x0002);
-
- return rc;
-}
-
-static int32_t mt9p012_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9p012_ctrl->curr_res = mt9p012_ctrl->pict_res;
-
- mt9p012_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t mt9p012_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9p012_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9p012_ctrl->curr_res = mt9p012_ctrl->pict_res;
-
- mt9p012_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t mt9p012_power_down(void)
-{
- int32_t rc = 0;
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER,
- MT9P012_RESET_REGISTER_PWOFF);
-
- mdelay(5);
- return rc;
-}
-
-static int32_t mt9p012_move_focus(int direction, int32_t num_steps)
-{
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_position;
- uint8_t code_val_msb, code_val_lsb;
-
- if (num_steps > MT9P012_TOTAL_STEPS_NEAR_TO_FAR)
- num_steps = MT9P012_TOTAL_STEPS_NEAR_TO_FAR;
- else if (num_steps == 0) {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- if (direction == MOVE_NEAR)
- step_direction = 16; /* 10bit */
- else if (direction == MOVE_FAR)
- step_direction = -16; /* 10 bit */
- else {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- if (mt9p012_ctrl->curr_lens_pos < mt9p012_ctrl->init_curr_lens_pos)
- mt9p012_ctrl->curr_lens_pos =
- mt9p012_ctrl->init_curr_lens_pos;
-
- actual_step = (int16_t)(step_direction * (int16_t)num_steps);
- next_position = (int16_t)(mt9p012_ctrl->curr_lens_pos + actual_step);
-
- if (next_position > 1023)
- next_position = 1023;
- else if (next_position < 0)
- next_position = 0;
-
- code_val_msb = next_position >> 4;
- code_val_lsb = (next_position & 0x000F) << 4;
- /* code_val_lsb |= mode_mask; */
-
- /* Writing the digital code for current to the actuator */
- if (mt9p012_i2c_write_b(MT9P012_AF_I2C_ADDR >> 1,
- code_val_msb, code_val_lsb) < 0) {
- CDBG("mt9p012_move_focus failed at line %d ...\n", __LINE__);
- return -EBUSY;
- }
-
- /* Storing the current lens Position */
- mt9p012_ctrl->curr_lens_pos = next_position;
-
- return 0;
-}
-
-static int32_t mt9p012_set_default_focus(void)
-{
- int32_t rc = 0;
- uint8_t code_val_msb, code_val_lsb;
-
- code_val_msb = 0x00;
- code_val_lsb = 0x00;
-
- /* Write the digital code for current to the actuator */
- rc = mt9p012_i2c_write_b(MT9P012_AF_I2C_ADDR >> 1,
- code_val_msb, code_val_lsb);
-
- mt9p012_ctrl->curr_lens_pos = 0;
- mt9p012_ctrl->init_curr_lens_pos = 0;
-
- return rc;
-}
-
-static int mt9p012_probe_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int mt9p012_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
- uint16_t chipid;
-
- rc = gpio_request(data->sensor_reset, "mt9p012");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- /* RESET the sensor image part via I2C command */
- CDBG("mt9p012_sensor_init(): reseting sensor.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER, 0x10CC|0x0001);
- if (rc < 0) {
- CDBG("sensor reset failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- mdelay(MT9P012_RESET_DELAY_MSECS);
-
- /* 3. Read sensor Model ID: */
- rc = mt9p012_i2c_read_w(mt9p012_client->addr,
- MT9P012_REG_MODEL_ID, &chipid);
- if (rc < 0)
- goto init_probe_fail;
-
- /* 4. Compare sensor ID to MT9T012VC ID: */
- if (chipid != MT9P012_MODEL_ID) {
- CDBG("mt9p012 wrong model_id = 0x%x\n", chipid);
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x306E, 0x9000);
- if (rc < 0) {
- CDBG("REV_7 write failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- /* RESET_REGISTER, enable parallel interface and disable serialiser */
- CDBG("mt9p012_sensor_init(): enabling parallel interface.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr, 0x301A, 0x10CC);
- if (rc < 0) {
- CDBG("enable parallel interface failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- /* To disable the 2 extra lines */
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- 0x3064, 0x0805);
-
- if (rc < 0) {
- CDBG("disable the 2 extra lines failed. rc = %d\n", rc);
- goto init_probe_fail;
- }
-
- mdelay(MT9P012_RESET_DELAY_MSECS);
- goto init_probe_done;
-
-init_probe_fail:
- mt9p012_probe_init_done(data);
-init_probe_done:
- return rc;
-}
-
-static int mt9p012_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- mt9p012_ctrl = kzalloc(sizeof(struct mt9p012_ctrl), GFP_KERNEL);
- if (!mt9p012_ctrl) {
- CDBG("mt9p012_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- mt9p012_ctrl->fps_divider = 1 * 0x00000400;
- mt9p012_ctrl->pict_fps_divider = 1 * 0x00000400;
- mt9p012_ctrl->set_test = TEST_OFF;
- mt9p012_ctrl->prev_res = QTR_SIZE;
- mt9p012_ctrl->pict_res = FULL_SIZE;
-
- if (data)
- mt9p012_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9P012_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = mt9p012_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail1;
-
- if (mt9p012_ctrl->prev_res == QTR_SIZE)
- rc = mt9p012_setting(REG_INIT, RES_PREVIEW);
- else
- rc = mt9p012_setting(REG_INIT, RES_CAPTURE);
-
- if (rc < 0) {
- CDBG("mt9p012_setting failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* sensor : output enable */
- CDBG("mt9p012_sensor_open_init(): enabling output.\n");
- rc = mt9p012_i2c_write_w(mt9p012_client->addr,
- MT9P012_REG_RESET_REGISTER, MT9P012_RESET_REGISTER_PWON);
- if (rc < 0) {
- CDBG("sensor output enable failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* TODO: enable AF actuator */
-#if 0
- CDBG("enable AF actuator, gpio = %d\n",
- mt9p012_ctrl->sensordata->vcm_pwd);
- rc = gpio_request(mt9p012_ctrl->sensordata->vcm_pwd, "mt9p012");
- if (!rc)
- gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 1);
- else {
- CDBG("mt9p012_ctrl gpio request failed!\n");
- goto init_fail1;
- }
- mdelay(20);
-
- rc = mt9p012_set_default_focus();
-#endif
- if (rc >= 0)
- goto init_done;
-
- /* TODO:
- * gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 0);
- * gpio_free(mt9p012_ctrl->sensordata->vcm_pwd); */
-init_fail1:
- mt9p012_probe_init_done(data);
- kfree(mt9p012_ctrl);
-init_done:
- return rc;
-}
-
-static int mt9p012_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9p012_wait_queue);
- return 0;
-}
-
-static int32_t mt9p012_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = mt9p012_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = mt9p012_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = mt9p012_raw_snapshot_config(mode);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-int mt9p012_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- int rc = 0;
-
- if (copy_from_user(&cdata,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&mt9p012_sem);
-
- CDBG("%s: cfgtype = %d\n", __func__, cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- mt9p012_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
-
- if (copy_to_user((void *)argp, &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = mt9p012_get_prev_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = mt9p012_get_prev_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = mt9p012_get_pict_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl = mt9p012_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- mt9p012_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = mt9p012_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc = mt9p012_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- CDBG("Line:%d CFG_SET_PICT_EXP_GAIN \n", __LINE__);
- rc = mt9p012_set_pict_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc = mt9p012_set_sensor_mode(cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = mt9p012_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- CDBG("mt9p012_ioctl: CFG_MOVE_FOCUS: cdata.cfg.focus.dir=%d cdata.cfg.focus.steps=%d\n",
- cdata.cfg.focus.dir, cdata.cfg.focus.steps);
- rc = mt9p012_move_focus(cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc = mt9p012_set_default_focus();
- break;
-
- case CFG_SET_LENS_SHADING:
- CDBG("%s: CFG_SET_LENS_SHADING\n", __func__);
- rc = mt9p012_lens_shading_enable(cdata.cfg.lens_shading);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- cdata.max_steps = MT9P012_STEPS_NEAR_TO_CLOSEST_INF;
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_EFFECT:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&mt9p012_sem);
- return rc;
-}
-
-int mt9p012_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&mt9p012_sem);
-
- mt9p012_power_down();
-
- gpio_direction_output(mt9p012_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(mt9p012_ctrl->sensordata->sensor_reset);
-
- gpio_direction_output(mt9p012_ctrl->sensordata->vcm_pwd, 0);
- gpio_free(mt9p012_ctrl->sensordata->vcm_pwd);
-
- kfree(mt9p012_ctrl);
- mt9p012_ctrl = NULL;
-
- CDBG("mt9p012_release completed\n");
-
- up(&mt9p012_sem);
- return rc;
-}
-
-static int mt9p012_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("mt9p012_probe called!\n");
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- CDBG("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- mt9p012_sensorw = kzalloc(sizeof(struct mt9p012_work), GFP_KERNEL);
- if (!mt9p012_sensorw) {
- CDBG("kzalloc failed.\n");
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9p012_sensorw);
- mt9p012_init_client(client);
- mt9p012_client = client;
-
- mdelay(50);
-
- CDBG("mt9p012_probe successed! rc = %d\n", rc);
- return 0;
-
-probe_failure:
- CDBG("mt9p012_probe failed! rc = %d\n", rc);
- return rc;
-}
-
-static const struct i2c_device_id mt9p012_i2c_id[] = {
- { "mt9p012", 0},
- { }
-};
-
-static struct i2c_driver mt9p012_i2c_driver = {
- .id_table = mt9p012_i2c_id,
- .probe = mt9p012_i2c_probe,
- .remove = __exit_p(mt9p012_i2c_remove),
- .driver = {
- .name = "mt9p012",
- },
-};
-
-static int mt9p012_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = i2c_add_driver(&mt9p012_i2c_driver);
- if (rc < 0 || mt9p012_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- msm_camio_clk_rate_set(MT9P012_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- rc = mt9p012_probe_init_sensor(info);
- if (rc < 0)
- goto probe_done;
-
- s->s_init = mt9p012_sensor_open_init;
- s->s_release = mt9p012_sensor_release;
- s->s_config = mt9p012_sensor_config;
- mt9p012_probe_init_done(info);
-
-probe_done:
- CDBG("%s %s:%d\n", __FILE__, __func__, __LINE__);
- return rc;
-}
-
-static int __mt9p012_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9p012_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9p012_probe,
- .driver = {
- .name = "msm_camera_mt9p012",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9p012_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9p012_init);
+++ /dev/null
-/*
- * Copyright (C) 2009 QUALCOMM Incorporated.
- */
-
-#include "mt9p012.h"
-#include <linux/kernel.h>
-
-/*Micron settings from Applications for lower power consumption.*/
-struct reg_struct mt9p012_reg_pat[2] = {
- { /* Preview */
- /* vt_pix_clk_div REG=0x0300 */
- 6, /* 5 */
-
- /* vt_sys_clk_div REG=0x0302 */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 */
- 2,
-
- /* pll_multiplier REG=0x0306 */
- 60,
-
- /* op_pix_clk_div REG=0x0308 */
- 8, /* 10 */
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2597,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1949,
-
- /* read_mode REG=0x3040
- * Preview 2x2 skipping */
- 0x00C3,
-
- /* x_output_size REG=0x034C */
- 1296,
-
- /* y_output_size REG=0x034E */
- 972,
-
- /* line_length_pck REG=0x300C */
- 3784,
-
- /* frame_length_lines REG=0x300A */
- 1057,
-
- /* coarse_integration_time REG=0x3012 */
- 16,
-
- /* fine_integration_time REG=0x3014 */
- 1764
- },
- { /*Snapshot*/
- /* vt_pix_clk_div REG=0x0300 */
- 6,
-
- /* vt_sys_clk_div REG=0x0302 */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 */
- 2,
-
- /* pll_multiplier REG=0x0306
- * 60 for 10fps snapshot */
- 60,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2615,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1967,
-
- /* read_mode REG=0x3040 */
- 0x0041,
-
- /* x_output_size REG=0x034C */
- 2608,
-
- /* y_output_size REG=0x034E */
- 1960,
-
- /* line_length_pck REG=0x300C */
- 3911,
-
- /* frame_length_lines REG=0x300A //10 fps snapshot */
- 2045,
-
- /* coarse_integration_time REG=0x3012 */
- 16,
-
- /* fine_integration_time REG=0x3014 */
- 882
- }
-};
-
-
-struct mt9p012_i2c_reg_conf mt9p012_test_tbl[] = {
- {0x3044, 0x0544 & 0xFBFF},
- {0x30CA, 0x0004 | 0x0001},
- {0x30D4, 0x9020 & 0x7FFF},
- {0x31E0, 0x0003 & 0xFFFE},
- {0x3180, 0x91FF & 0x7FFF},
- {0x301A, (0x10CC | 0x8000) & 0xFFF7},
- {0x301E, 0x0000},
- {0x3780, 0x0000},
-};
-
-
-struct mt9p012_i2c_reg_conf mt9p012_lc_tbl[] = {
- /* [Lens shading 85 Percent TL84] */
- /* P_RD_P0Q0 */
- {0x360A, 0x7FEF},
- /* P_RD_P0Q1 */
- {0x360C, 0x232C},
- /* P_RD_P0Q2 */
- {0x360E, 0x7050},
- /* P_RD_P0Q3 */
- {0x3610, 0xF3CC},
- /* P_RD_P0Q4 */
- {0x3612, 0x89D1},
- /* P_RD_P1Q0 */
- {0x364A, 0xBE0D},
- /* P_RD_P1Q1 */
- {0x364C, 0x9ACB},
- /* P_RD_P1Q2 */
- {0x364E, 0x2150},
- /* P_RD_P1Q3 */
- {0x3650, 0xB26B},
- /* P_RD_P1Q4 */
- {0x3652, 0x9511},
- /* P_RD_P2Q0 */
- {0x368A, 0x2151},
- /* P_RD_P2Q1 */
- {0x368C, 0x00AD},
- /* P_RD_P2Q2 */
- {0x368E, 0x8334},
- /* P_RD_P2Q3 */
- {0x3690, 0x478E},
- /* P_RD_P2Q4 */
- {0x3692, 0x0515},
- /* P_RD_P3Q0 */
- {0x36CA, 0x0710},
- /* P_RD_P3Q1 */
- {0x36CC, 0x452D},
- /* P_RD_P3Q2 */
- {0x36CE, 0xF352},
- /* P_RD_P3Q3 */
- {0x36D0, 0x190F},
- /* P_RD_P3Q4 */
- {0x36D2, 0x4413},
- /* P_RD_P4Q0 */
- {0x370A, 0xD112},
- /* P_RD_P4Q1 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q2 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q3 */
- {0x3710, 0xDC11},
- /* P_RD_P4Q4 */
- {0x3712, 0xD776},
- /* P_GR_P0Q0 */
- {0x3600, 0x1750},
- /* P_GR_P0Q1 */
- {0x3602, 0xF0AC},
- /* P_GR_P0Q2 */
- {0x3604, 0x4711},
- /* P_GR_P0Q3 */
- {0x3606, 0x07CE},
- /* P_GR_P0Q4 */
- {0x3608, 0x96B2},
- /* P_GR_P1Q0 */
- {0x3640, 0xA9AE},
- /* P_GR_P1Q1 */
- {0x3642, 0xF9AC},
- /* P_GR_P1Q2 */
- {0x3644, 0x39F1},
- /* P_GR_P1Q3 */
- {0x3646, 0x016F},
- /* P_GR_P1Q4 */
- {0x3648, 0x8AB2},
- /* P_GR_P2Q0 */
- {0x3680, 0x1752},
- /* P_GR_P2Q1 */
- {0x3682, 0x70F0},
- /* P_GR_P2Q2 */
- {0x3684, 0x83F5},
- /* P_GR_P2Q3 */
- {0x3686, 0x8392},
- /* P_GR_P2Q4 */
- {0x3688, 0x1FD6},
- /* P_GR_P3Q0 */
- {0x36C0, 0x1131},
- /* P_GR_P3Q1 */
- {0x36C2, 0x3DAF},
- /* P_GR_P3Q2 */
- {0x36C4, 0x89B4},
- /* P_GR_P3Q3 */
- {0x36C6, 0xA391},
- /* P_GR_P3Q4 */
- {0x36C8, 0x1334},
- /* P_GR_P4Q0 */
- {0x3700, 0xDC13},
- /* P_GR_P4Q1 */
- {0x3702, 0xD052},
- /* P_GR_P4Q2 */
- {0x3704, 0x5156},
- /* P_GR_P4Q3 */
- {0x3706, 0x1F13},
- /* P_GR_P4Q4 */
- {0x3708, 0x8C38},
- /* P_BL_P0Q0 */
- {0x3614, 0x0050},
- /* P_BL_P0Q1 */
- {0x3616, 0xBD4C},
- /* P_BL_P0Q2 */
- {0x3618, 0x41B0},
- /* P_BL_P0Q3 */
- {0x361A, 0x660D},
- /* P_BL_P0Q4 */
- {0x361C, 0xC590},
- /* P_BL_P1Q0 */
- {0x3654, 0x87EC},
- /* P_BL_P1Q1 */
- {0x3656, 0xE44C},
- /* P_BL_P1Q2 */
- {0x3658, 0x302E},
- /* P_BL_P1Q3 */
- {0x365A, 0x106E},
- /* P_BL_P1Q4 */
- {0x365C, 0xB58E},
- /* P_BL_P2Q0 */
- {0x3694, 0x0DD1},
- /* P_BL_P2Q1 */
- {0x3696, 0x2A50},
- /* P_BL_P2Q2 */
- {0x3698, 0xC793},
- /* P_BL_P2Q3 */
- {0x369A, 0xE8F1},
- /* P_BL_P2Q4 */
- {0x369C, 0x4174},
- /* P_BL_P3Q0 */
- {0x36D4, 0x01EF},
- /* P_BL_P3Q1 */
- {0x36D6, 0x06CF},
- /* P_BL_P3Q2 */
- {0x36D8, 0x8D91},
- /* P_BL_P3Q3 */
- {0x36DA, 0x91F0},
- /* P_BL_P3Q4 */
- {0x36DC, 0x52EF},
- /* P_BL_P4Q0 */
- {0x3714, 0xA6D2},
- /* P_BL_P4Q1 */
- {0x3716, 0xA312},
- /* P_BL_P4Q2 */
- {0x3718, 0x2695},
- /* P_BL_P4Q3 */
- {0x371A, 0x3953},
- /* P_BL_P4Q4 */
- {0x371C, 0x9356},
- /* P_GB_P0Q0 */
- {0x361E, 0x7EAF},
- /* P_GB_P0Q1 */
- {0x3620, 0x2A4C},
- /* P_GB_P0Q2 */
- {0x3622, 0x49F0},
- {0x3624, 0xF1EC},
- /* P_GB_P0Q4 */
- {0x3626, 0xC670},
- /* P_GB_P1Q0 */
- {0x365E, 0x8E0C},
- /* P_GB_P1Q1 */
- {0x3660, 0xC2A9},
- /* P_GB_P1Q2 */
- {0x3662, 0x274F},
- /* P_GB_P1Q3 */
- {0x3664, 0xADAB},
- /* P_GB_P1Q4 */
- {0x3666, 0x8EF0},
- /* P_GB_P2Q0 */
- {0x369E, 0x09B1},
- /* P_GB_P2Q1 */
- {0x36A0, 0xAA2E},
- /* P_GB_P2Q2 */
- {0x36A2, 0xC3D3},
- /* P_GB_P2Q3 */
- {0x36A4, 0x7FAF},
- /* P_GB_P2Q4 */
- {0x36A6, 0x3F34},
- /* P_GB_P3Q0 */
- {0x36DE, 0x4C8F},
- /* P_GB_P3Q1 */
- {0x36E0, 0x886E},
- /* P_GB_P3Q2 */
- {0x36E2, 0xE831},
- /* P_GB_P3Q3 */
- {0x36E4, 0x1FD0},
- /* P_GB_P3Q4 */
- {0x36E6, 0x1192},
- /* P_GB_P4Q0 */
- {0x371E, 0xB952},
- /* P_GB_P4Q1 */
- {0x3720, 0x6DCF},
- /* P_GB_P4Q2 */
- {0x3722, 0x1B55},
- /* P_GB_P4Q3 */
- {0x3724, 0xA112},
- /* P_GB_P4Q4 */
- {0x3726, 0x82F6},
- /* POLY_ORIGIN_C */
- {0x3782, 0x0510},
- /* POLY_ORIGIN_R */
- {0x3784, 0x0390},
- /* POLY_SC_ENABLE */
- {0x3780, 0x8000},
-};
-
-/* rolloff table for illuminant A */
-struct mt9p012_i2c_reg_conf mt9p012_rolloff_tbl[] = {
- /* P_RD_P0Q0 */
- {0x360A, 0x7FEF},
- /* P_RD_P0Q1 */
- {0x360C, 0x232C},
- /* P_RD_P0Q2 */
- {0x360E, 0x7050},
- /* P_RD_P0Q3 */
- {0x3610, 0xF3CC},
- /* P_RD_P0Q4 */
- {0x3612, 0x89D1},
- /* P_RD_P1Q0 */
- {0x364A, 0xBE0D},
- /* P_RD_P1Q1 */
- {0x364C, 0x9ACB},
- /* P_RD_P1Q2 */
- {0x364E, 0x2150},
- /* P_RD_P1Q3 */
- {0x3650, 0xB26B},
- /* P_RD_P1Q4 */
- {0x3652, 0x9511},
- /* P_RD_P2Q0 */
- {0x368A, 0x2151},
- /* P_RD_P2Q1 */
- {0x368C, 0x00AD},
- /* P_RD_P2Q2 */
- {0x368E, 0x8334},
- /* P_RD_P2Q3 */
- {0x3690, 0x478E},
- /* P_RD_P2Q4 */
- {0x3692, 0x0515},
- /* P_RD_P3Q0 */
- {0x36CA, 0x0710},
- /* P_RD_P3Q1 */
- {0x36CC, 0x452D},
- /* P_RD_P3Q2 */
- {0x36CE, 0xF352},
- /* P_RD_P3Q3 */
- {0x36D0, 0x190F},
- /* P_RD_P3Q4 */
- {0x36D2, 0x4413},
- /* P_RD_P4Q0 */
- {0x370A, 0xD112},
- /* P_RD_P4Q1 */
- {0x370C, 0xF50F},
- /* P_RD_P4Q2 */
- {0x370E, 0x6375},
- /* P_RD_P4Q3 */
- {0x3710, 0xDC11},
- /* P_RD_P4Q4 */
- {0x3712, 0xD776},
- /* P_GR_P0Q0 */
- {0x3600, 0x1750},
- /* P_GR_P0Q1 */
- {0x3602, 0xF0AC},
- /* P_GR_P0Q2 */
- {0x3604, 0x4711},
- /* P_GR_P0Q3 */
- {0x3606, 0x07CE},
- /* P_GR_P0Q4 */
- {0x3608, 0x96B2},
- /* P_GR_P1Q0 */
- {0x3640, 0xA9AE},
- /* P_GR_P1Q1 */
- {0x3642, 0xF9AC},
- /* P_GR_P1Q2 */
- {0x3644, 0x39F1},
- /* P_GR_P1Q3 */
- {0x3646, 0x016F},
- /* P_GR_P1Q4 */
- {0x3648, 0x8AB2},
- /* P_GR_P2Q0 */
- {0x3680, 0x1752},
- /* P_GR_P2Q1 */
- {0x3682, 0x70F0},
- /* P_GR_P2Q2 */
- {0x3684, 0x83F5},
- /* P_GR_P2Q3 */
- {0x3686, 0x8392},
- /* P_GR_P2Q4 */
- {0x3688, 0x1FD6},
- /* P_GR_P3Q0 */
- {0x36C0, 0x1131},
- /* P_GR_P3Q1 */
- {0x36C2, 0x3DAF},
- /* P_GR_P3Q2 */
- {0x36C4, 0x89B4},
- /* P_GR_P3Q3 */
- {0x36C6, 0xA391},
- /* P_GR_P3Q4 */
- {0x36C8, 0x1334},
- /* P_GR_P4Q0 */
- {0x3700, 0xDC13},
- /* P_GR_P4Q1 */
- {0x3702, 0xD052},
- /* P_GR_P4Q2 */
- {0x3704, 0x5156},
- /* P_GR_P4Q3 */
- {0x3706, 0x1F13},
- /* P_GR_P4Q4 */
- {0x3708, 0x8C38},
- /* P_BL_P0Q0 */
- {0x3614, 0x0050},
- /* P_BL_P0Q1 */
- {0x3616, 0xBD4C},
- /* P_BL_P0Q2 */
- {0x3618, 0x41B0},
- /* P_BL_P0Q3 */
- {0x361A, 0x660D},
- /* P_BL_P0Q4 */
- {0x361C, 0xC590},
- /* P_BL_P1Q0 */
- {0x3654, 0x87EC},
- /* P_BL_P1Q1 */
- {0x3656, 0xE44C},
- /* P_BL_P1Q2 */
- {0x3658, 0x302E},
- /* P_BL_P1Q3 */
- {0x365A, 0x106E},
- /* P_BL_P1Q4 */
- {0x365C, 0xB58E},
- /* P_BL_P2Q0 */
- {0x3694, 0x0DD1},
- /* P_BL_P2Q1 */
- {0x3696, 0x2A50},
- /* P_BL_P2Q2 */
- {0x3698, 0xC793},
- /* P_BL_P2Q3 */
- {0x369A, 0xE8F1},
- /* P_BL_P2Q4 */
- {0x369C, 0x4174},
- /* P_BL_P3Q0 */
- {0x36D4, 0x01EF},
- /* P_BL_P3Q1 */
- {0x36D6, 0x06CF},
- /* P_BL_P3Q2 */
- {0x36D8, 0x8D91},
- /* P_BL_P3Q3 */
- {0x36DA, 0x91F0},
- /* P_BL_P3Q4 */
- {0x36DC, 0x52EF},
- /* P_BL_P4Q0 */
- {0x3714, 0xA6D2},
- /* P_BL_P4Q1 */
- {0x3716, 0xA312},
- /* P_BL_P4Q2 */
- {0x3718, 0x2695},
- /* P_BL_P4Q3 */
- {0x371A, 0x3953},
- /* P_BL_P4Q4 */
- {0x371C, 0x9356},
- /* P_GB_P0Q0 */
- {0x361E, 0x7EAF},
- /* P_GB_P0Q1 */
- {0x3620, 0x2A4C},
- /* P_GB_P0Q2 */
- {0x3622, 0x49F0},
- {0x3624, 0xF1EC},
- /* P_GB_P0Q4 */
- {0x3626, 0xC670},
- /* P_GB_P1Q0 */
- {0x365E, 0x8E0C},
- /* P_GB_P1Q1 */
- {0x3660, 0xC2A9},
- /* P_GB_P1Q2 */
- {0x3662, 0x274F},
- /* P_GB_P1Q3 */
- {0x3664, 0xADAB},
- /* P_GB_P1Q4 */
- {0x3666, 0x8EF0},
- /* P_GB_P2Q0 */
- {0x369E, 0x09B1},
- /* P_GB_P2Q1 */
- {0x36A0, 0xAA2E},
- /* P_GB_P2Q2 */
- {0x36A2, 0xC3D3},
- /* P_GB_P2Q3 */
- {0x36A4, 0x7FAF},
- /* P_GB_P2Q4 */
- {0x36A6, 0x3F34},
- /* P_GB_P3Q0 */
- {0x36DE, 0x4C8F},
- /* P_GB_P3Q1 */
- {0x36E0, 0x886E},
- /* P_GB_P3Q2 */
- {0x36E2, 0xE831},
- /* P_GB_P3Q3 */
- {0x36E4, 0x1FD0},
- /* P_GB_P3Q4 */
- {0x36E6, 0x1192},
- /* P_GB_P4Q0 */
- {0x371E, 0xB952},
- /* P_GB_P4Q1 */
- {0x3720, 0x6DCF},
- /* P_GB_P4Q2 */
- {0x3722, 0x1B55},
- /* P_GB_P4Q3 */
- {0x3724, 0xA112},
- /* P_GB_P4Q4 */
- {0x3726, 0x82F6},
- /* POLY_ORIGIN_C */
- {0x3782, 0x0510},
- /* POLY_ORIGIN_R */
- {0x3784, 0x0390},
- /* POLY_SC_ENABLE */
- {0x3780, 0x8000},
-};
-
-
-struct mt9p012_reg mt9p012_regs = {
- .reg_pat = &mt9p012_reg_pat[0],
- .reg_pat_size = ARRAY_SIZE(mt9p012_reg_pat),
- .ttbl = &mt9p012_test_tbl[0],
- .ttbl_size = ARRAY_SIZE(mt9p012_test_tbl),
- .lctbl = &mt9p012_lc_tbl[0],
- .lctbl_size = ARRAY_SIZE(mt9p012_lc_tbl),
- .rftbl = &mt9p012_rolloff_tbl[0],
- .rftbl_size = ARRAY_SIZE(mt9p012_rolloff_tbl)
-};
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/i2c.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/kernel.h>
-#include <media/msm_camera.h>
-#include <mach/gpio.h>
-#include <mach/camera.h>
-#include <asm/mach-types.h>
-#include "mt9t013.h"
-
-/*=============================================================
- SENSOR REGISTER DEFINES
-==============================================================*/
-#define MT9T013_REG_MODEL_ID 0x0000
-#define MT9T013_MODEL_ID 0x2600
-#define REG_GROUPED_PARAMETER_HOLD 0x0104
-#define GROUPED_PARAMETER_HOLD 0x0100
-#define GROUPED_PARAMETER_UPDATE 0x0000
-#define REG_COARSE_INT_TIME 0x3012
-#define REG_VT_PIX_CLK_DIV 0x0300
-#define REG_VT_SYS_CLK_DIV 0x0302
-#define REG_PRE_PLL_CLK_DIV 0x0304
-#define REG_PLL_MULTIPLIER 0x0306
-#define REG_OP_PIX_CLK_DIV 0x0308
-#define REG_OP_SYS_CLK_DIV 0x030A
-#define REG_SCALE_M 0x0404
-#define REG_FRAME_LENGTH_LINES 0x300A
-#define REG_LINE_LENGTH_PCK 0x300C
-#define REG_X_ADDR_START 0x3004
-#define REG_Y_ADDR_START 0x3002
-#define REG_X_ADDR_END 0x3008
-#define REG_Y_ADDR_END 0x3006
-#define REG_X_OUTPUT_SIZE 0x034C
-#define REG_Y_OUTPUT_SIZE 0x034E
-#define REG_FINE_INT_TIME 0x3014
-#define REG_ROW_SPEED 0x3016
-#define MT9T013_REG_RESET_REGISTER 0x301A
-#define MT9T013_RESET_REGISTER_PWON 0x10CC
-#define MT9T013_RESET_REGISTER_PWOFF 0x1008 /* 0x10C8 stop streaming*/
-#define REG_READ_MODE 0x3040
-#define REG_GLOBAL_GAIN 0x305E
-#define REG_TEST_PATTERN_MODE 0x3070
-
-
-enum mt9t013_test_mode {
- TEST_OFF,
- TEST_1,
- TEST_2,
- TEST_3
-};
-
-enum mt9t013_resolution {
- QTR_SIZE,
- FULL_SIZE,
- INVALID_SIZE
-};
-
-enum mt9t013_reg_update {
- REG_INIT, /* registers that need to be updated during initialization */
- UPDATE_PERIODIC, /* registers that needs periodic I2C writes */
- UPDATE_ALL, /* all registers will be updated */
- UPDATE_INVALID
-};
-
-enum mt9t013_setting {
- RES_PREVIEW,
- RES_CAPTURE
-};
-
-/* actuator's Slave Address */
-#define MT9T013_AF_I2C_ADDR 0x18
-
-/*
-* AF Total steps parameters
-*/
-#define MT9T013_TOTAL_STEPS_NEAR_TO_FAR 30
-
-/*
- * Time in milisecs for waiting for the sensor to reset.
- */
-#define MT9T013_RESET_DELAY_MSECS 66
-
-/* for 30 fps preview */
-#define MT9T013_DEFAULT_CLOCK_RATE 24000000
-#define MT9T013_DEFAULT_MAX_FPS 26
-
-
-/* FIXME: Changes from here */
-struct mt9t013_work {
- struct work_struct work;
-};
-
-static struct mt9t013_work *mt9t013_sensorw;
-static struct i2c_client *mt9t013_client;
-
-struct mt9t013_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum mt9t013_resolution prev_res;
- enum mt9t013_resolution pict_res;
- enum mt9t013_resolution curr_res;
- enum mt9t013_test_mode set_test;
-
- unsigned short imgaddr;
-};
-
-
-static struct mt9t013_ctrl *mt9t013_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(mt9t013_wait_queue);
-DEFINE_SEMAPHORE(mt9t013_sem);
-
-extern struct mt9t013_reg mt9t013_regs; /* from mt9t013_reg.c */
-
-static int mt9t013_i2c_rxdata(unsigned short saddr,
- unsigned char *rxdata, int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(mt9t013_client->adapter, msgs, 2) < 0) {
- pr_err("mt9t013_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9t013_i2c_read_w(unsigned short saddr,
- unsigned short raddr, unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = mt9t013_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- pr_err("mt9t013_i2c_read failed!\n");
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(mt9t013_client->adapter, msg, 1) < 0) {
- pr_err("mt9t013_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t mt9t013_i2c_write_b(unsigned short saddr,
- unsigned short waddr, unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[2];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = waddr;
- buf[1] = wdata;
- rc = mt9t013_i2c_txdata(saddr, buf, 2);
-
- if (rc < 0)
- pr_err("i2c_write failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_write_w(unsigned short saddr,
- unsigned short waddr, unsigned short wdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = (wdata & 0xFF00)>>8;
- buf[3] = (wdata & 0x00FF);
-
- rc = mt9t013_i2c_txdata(saddr, buf, 4);
-
- if (rc < 0)
- pr_err("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, wdata);
-
- return rc;
-}
-
-static int32_t mt9t013_i2c_write_w_table(
- struct mt9t013_i2c_reg_conf *reg_conf_tbl, int num_of_items_in_table)
-{
- int i;
- int32_t rc = -EIO;
-
- for (i = 0; i < num_of_items_in_table; i++) {
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- reg_conf_tbl->waddr, reg_conf_tbl->wdata);
- if (rc < 0)
- break;
- reg_conf_tbl++;
- }
-
- return rc;
-}
-
-static int32_t mt9t013_test(enum mt9t013_test_mode mo)
-{
- int32_t rc = 0;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- if (mo == TEST_OFF)
- return 0;
- else {
- rc = mt9t013_i2c_write_w_table(mt9t013_regs.ttbl,
- mt9t013_regs.ttbl_size);
- if (rc < 0)
- return rc;
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
- if (rc < 0)
- return rc;
- }
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_lc(void)
-{
- int32_t rc;
-
- rc = mt9t013_i2c_write_w_table(mt9t013_regs.lctbl, mt9t013_regs.lctbl_size);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_default_focus(uint8_t af_step)
-{
- int32_t rc = 0;
- uint8_t code_val_msb, code_val_lsb;
- code_val_msb = 0x01;
- code_val_lsb = af_step;
-
- /* Write the digital code for current to the actuator */
- rc = mt9t013_i2c_write_b(MT9T013_AF_I2C_ADDR>>1,
- code_val_msb, code_val_lsb);
-
- mt9t013_ctrl->curr_lens_pos = 0;
- mt9t013_ctrl->init_curr_lens_pos = 0;
- return rc;
-}
-
-static void mt9t013_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /*Q10 */
- uint32_t pclk_mult; /*Q10 */
-
- if (mt9t013_ctrl->prev_res == QTR_SIZE) {
- divider =
- (uint32_t)(
- ((mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines *
- mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck) *
- 0x00000400) /
- (mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines *
- mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck));
-
- pclk_mult =
- (uint32_t) ((mt9t013_regs.reg_pat[RES_CAPTURE].pll_multiplier *
- 0x00000400) /
- (mt9t013_regs.reg_pat[RES_PREVIEW].pll_multiplier));
-
- } else {
- /* full size resolution used for preview. */
- divider = 0x00000400; /*1.0 */
- pclk_mult = 0x00000400; /*1.0 */
- }
-
- /* Verify PCLK settings and frame sizes. */
- *pfps =
- (uint16_t) (fps * divider * pclk_mult /
- 0x00000400 / 0x00000400);
-}
-
-static uint16_t mt9t013_get_prev_lines_pf(void)
-{
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- return mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines;
- else
- return mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9t013_get_prev_pixels_pl(void)
-{
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- return mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck;
- else
- return mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint16_t mt9t013_get_pict_lines_pf(void)
-{
- return mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines;
-}
-
-static uint16_t mt9t013_get_pict_pixels_pl(void)
-{
- return mt9t013_regs.reg_pat[RES_CAPTURE].line_length_pck;
-}
-
-static uint32_t mt9t013_get_pict_max_exp_lc(void)
-{
- uint16_t snapshot_lines_per_frame;
-
- if (mt9t013_ctrl->pict_res == QTR_SIZE) {
- snapshot_lines_per_frame =
- mt9t013_regs.reg_pat[RES_PREVIEW].frame_length_lines - 1;
- } else {
- snapshot_lines_per_frame =
- mt9t013_regs.reg_pat[RES_CAPTURE].frame_length_lines - 1;
- }
-
- return snapshot_lines_per_frame * 24;
-}
-
-static int32_t mt9t013_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q8 format */
- int32_t rc = 0;
-
- mt9t013_ctrl->fps_divider = fps->fps_div;
- mt9t013_ctrl->pict_fps_divider = fps->pict_fps_div;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return -EBUSY;
-
- CDBG("mt9t013_set_fps: fps_div is %d, frame_rate is %d\n",
- fps->fps_div,
- (uint16_t) (mt9t013_regs.reg_pat[RES_PREVIEW].
- frame_length_lines *
- fps->fps_div/0x00000400));
-
- CDBG("mt9t013_set_fps: fps_mult is %d, frame_rate is %d\n",
- fps->f_mult,
- (uint16_t)(mt9t013_regs.reg_pat[RES_PREVIEW].
- line_length_pck *
- fps->f_mult / 0x00000400));
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- (uint16_t) (
- mt9t013_regs.reg_pat[RES_PREVIEW].line_length_pck *
- fps->f_mult / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_write_exp_gain(uint16_t gain, uint32_t line)
-{
- const uint16_t max_legal_gain = 0x01FF;
- uint32_t line_length_ratio = 0x00000400;
- enum mt9t013_setting setting;
- int32_t rc = 0;
-
- if (mt9t013_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
- mt9t013_ctrl->my_reg_gain = gain;
- mt9t013_ctrl->my_reg_line_count = (uint16_t) line;
- }
-
- if (gain > max_legal_gain)
- gain = max_legal_gain;
-
- /* Verify no overflow */
- if (mt9t013_ctrl->sensormode != SENSOR_SNAPSHOT_MODE) {
- line = (uint32_t) (line * mt9t013_ctrl->fps_divider /
- 0x00000400);
-
- setting = RES_PREVIEW;
-
- } else {
- line = (uint32_t) (line * mt9t013_ctrl->pict_fps_divider /
- 0x00000400);
-
- setting = RES_CAPTURE;
- }
-
- /*Set digital gain to 1 */
- gain |= 0x0200;
-
- if ((mt9t013_regs.reg_pat[setting].frame_length_lines - 1) < line) {
-
- line_length_ratio =
- (uint32_t) (line * 0x00000400) /
- (mt9t013_regs.reg_pat[setting].frame_length_lines - 1);
- } else
- line_length_ratio = 0x00000400;
-
- /* There used to be PARAMETER_HOLD register write before and
- * after REG_GLOBAL_GAIN & REG_COARSE_INIT_TIME. This causes
- * aec oscillation. Hence removed. */
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr, REG_GLOBAL_GAIN, gain);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- (uint16_t)((uint32_t) line * 0x00000400 /
- line_length_ratio));
- if (rc < 0)
- return rc;
-
- return rc;
-}
-
-static int32_t mt9t013_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- rc = mt9t013_write_exp_gain(gain, line);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- 0x10CC | 0x0002);
-
- mdelay(5);
-
- /* camera_timed_wait(snapshot_wait*exposure_ratio); */
- return rc;
-}
-
-static int32_t mt9t013_setting(enum mt9t013_reg_update rupdate,
- enum mt9t013_setting rt)
-{
- int32_t rc = 0;
-
- switch (rupdate) {
- case UPDATE_PERIODIC: {
-
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-#if 0
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc < 0)
- return rc;
-#endif
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_sys_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PRE_PLL_CLK_DIV,
- mt9t013_regs.reg_pat[rt].pre_pll_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PLL_MULTIPLIER,
- mt9t013_regs.reg_pat[rt].pll_multiplier);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_sys_clk_div);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_ROW_SPEED,
- mt9t013_regs.reg_pat[rt].row_speed);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_START,
- mt9t013_regs.reg_pat[rt].x_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_END,
- mt9t013_regs.reg_pat[rt].x_addr_end);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_START,
- mt9t013_regs.reg_pat[rt].y_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_END,
- mt9t013_regs.reg_pat[rt].y_addr_end);
- if (rc < 0)
- return rc;
-
- if (machine_is_sapphire()) {
- if (rt == 0)
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x046F);
- else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x0027);
- } else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- mt9t013_regs.reg_pat[rt].read_mode);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_SCALE_M,
- mt9t013_regs.reg_pat[rt].scale_m);
- if (rc < 0)
- return rc;
-
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].x_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].y_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- mt9t013_regs.reg_pat[rt].line_length_pck);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FRAME_LENGTH_LINES,
- (mt9t013_regs.reg_pat[rt].frame_length_lines *
- mt9t013_ctrl->fps_divider / 0x00000400));
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- mt9t013_regs.reg_pat[rt].coarse_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FINE_INT_TIME,
- mt9t013_regs.reg_pat[rt].fine_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_test(mt9t013_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- return rc;
- }
- }
- break;
-
- /*CAMSENSOR_REG_UPDATE_PERIODIC */
- case REG_INIT: {
- if (rt == RES_PREVIEW || rt == RES_CAPTURE) {
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc < 0)
- /* MODE_SELECT, stop streaming */
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_VT_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].vt_sys_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PRE_PLL_CLK_DIV,
- mt9t013_regs.reg_pat[rt].pre_pll_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_PLL_MULTIPLIER,
- mt9t013_regs.reg_pat[rt].pll_multiplier);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_PIX_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_pix_clk_div);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_OP_SYS_CLK_DIV,
- mt9t013_regs.reg_pat[rt].op_sys_clk_div);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- /* additional power saving mode ok around 38.2MHz */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3084, 0x2409);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3092, 0x0A49);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3094, 0x4949);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3096, 0x4949);
- if (rc < 0)
- return rc;
-
- /* Set preview or snapshot mode */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_ROW_SPEED,
- mt9t013_regs.reg_pat[rt].row_speed);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_START,
- mt9t013_regs.reg_pat[rt].x_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_ADDR_END,
- mt9t013_regs.reg_pat[rt].x_addr_end);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_START,
- mt9t013_regs.reg_pat[rt].y_addr_start);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_ADDR_END,
- mt9t013_regs.reg_pat[rt].y_addr_end);
- if (rc < 0)
- return rc;
-
- if (machine_is_sapphire()) {
- if (rt == 0)
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x046F);
- else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- 0x0027);
- } else
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_READ_MODE,
- mt9t013_regs.reg_pat[rt].read_mode);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_SCALE_M,
- mt9t013_regs.reg_pat[rt].scale_m);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_X_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].x_output_size);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_Y_OUTPUT_SIZE,
- mt9t013_regs.reg_pat[rt].y_output_size);
- if (rc < 0)
- return 0;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_LINE_LENGTH_PCK,
- mt9t013_regs.reg_pat[rt].line_length_pck);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FRAME_LENGTH_LINES,
- mt9t013_regs.reg_pat[rt].frame_length_lines);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_COARSE_INT_TIME,
- mt9t013_regs.reg_pat[rt].coarse_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_FINE_INT_TIME,
- mt9t013_regs.reg_pat[rt].fine_int_time);
- if (rc < 0)
- return rc;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- /* load lens shading */
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- /* most likely needs to be written only once. */
- rc = mt9t013_set_lc();
- if (rc < 0)
- return -EBUSY;
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- if (rc < 0)
- return rc;
-
- rc = mt9t013_test(mt9t013_ctrl->set_test);
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc =
- mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
- if (rc < 0)
- /* MODE_SELECT, stop streaming */
- return rc;
-
- CDBG("!!! mt9t013 !!! PowerOn is done!\n");
- mdelay(5);
- return rc;
- }
- } /* case CAMSENSOR_REG_INIT: */
- break;
-
- /*CAMSENSOR_REG_INIT */
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int32_t mt9t013_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case QTR_SIZE:
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_PREVIEW);
- if (rc < 0)
- return rc;
- CDBG("sensor configuration done!\n");
- break;
-
- case FULL_SIZE:
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- mt9t013_ctrl->prev_res = res;
- mt9t013_ctrl->curr_res = res;
- mt9t013_ctrl->sensormode = mode;
-
- return mt9t013_write_exp_gain(mt9t013_ctrl->my_reg_gain,
- mt9t013_ctrl->my_reg_line_count);
-}
-
-static int32_t mt9t013_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9t013_ctrl->curr_res = mt9t013_ctrl->pict_res;
- mt9t013_ctrl->sensormode = mode;
- return rc;
-}
-
-static int32_t mt9t013_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = mt9t013_setting(UPDATE_PERIODIC, RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- mt9t013_ctrl->curr_res = mt9t013_ctrl->pict_res;
- mt9t013_ctrl->sensormode = mode;
- return rc;
-}
-
-static int32_t mt9t013_power_down(void)
-{
- int32_t rc = 0;
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWOFF);
- if (rc >= 0)
- mdelay(5);
- return rc;
-}
-
-static int32_t mt9t013_move_focus(int direction, int32_t num_steps)
-{
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_position;
- int16_t break_steps[4];
- uint8_t code_val_msb, code_val_lsb;
- int16_t i;
-
- if (num_steps > MT9T013_TOTAL_STEPS_NEAR_TO_FAR)
- num_steps = MT9T013_TOTAL_STEPS_NEAR_TO_FAR;
- else if (num_steps == 0)
- return -EINVAL;
-
- if (direction == MOVE_NEAR)
- step_direction = 4;
- else if (direction == MOVE_FAR)
- step_direction = -4;
- else
- return -EINVAL;
-
- if (mt9t013_ctrl->curr_lens_pos < mt9t013_ctrl->init_curr_lens_pos)
- mt9t013_ctrl->curr_lens_pos = mt9t013_ctrl->init_curr_lens_pos;
-
- actual_step =
- (int16_t) (step_direction *
- (int16_t) num_steps);
-
- for (i = 0; i < 4; i++)
- break_steps[i] =
- actual_step / 4 * (i + 1) - actual_step / 4 * i;
-
- for (i = 0; i < 4; i++) {
- next_position =
- (int16_t)
- (mt9t013_ctrl->curr_lens_pos + break_steps[i]);
-
- if (next_position > 255)
- next_position = 255;
- else if (next_position < 0)
- next_position = 0;
-
- code_val_msb =
- ((next_position >> 4) << 2) |
- ((next_position << 4) >> 6);
-
- code_val_lsb =
- ((next_position & 0x03) << 6);
-
- /* Writing the digital code for current to the actuator */
- if (mt9t013_i2c_write_b(MT9T013_AF_I2C_ADDR>>1,
- code_val_msb, code_val_lsb) < 0)
- return -EBUSY;
-
- /* Storing the current lens Position */
- mt9t013_ctrl->curr_lens_pos = next_position;
-
- if (i < 3)
- mdelay(1);
- } /* for */
-
- return 0;
-}
-
-static int mt9t013_sensor_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int mt9t013_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int rc;
- uint16_t chipid;
-
- rc = gpio_request(data->sensor_reset, "mt9t013");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- /* RESET the sensor image part via I2C command */
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER, 0x1009);
- if (rc < 0)
- goto init_probe_fail;
-
- /* 3. Read sensor Model ID: */
- rc = mt9t013_i2c_read_w(mt9t013_client->addr,
- MT9T013_REG_MODEL_ID, &chipid);
-
- if (rc < 0)
- goto init_probe_fail;
-
- CDBG("mt9t013 model_id = 0x%x\n", chipid);
-
- /* 4. Compare sensor ID to MT9T012VC ID: */
- if (chipid != MT9T013_MODEL_ID) {
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- 0x3064, 0x0805);
- if (rc < 0)
- goto init_probe_fail;
-
- mdelay(MT9T013_RESET_DELAY_MSECS);
-
- goto init_probe_done;
-
- /* sensor: output enable */
-#if 0
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- MT9T013_REG_RESET_REGISTER,
- MT9T013_RESET_REGISTER_PWON);
-
- /* if this fails, the sensor is not the MT9T013 */
- rc = mt9t013_set_default_focus(0);
-#endif
-
-init_probe_fail:
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
-init_probe_done:
- return rc;
-}
-
-static int32_t mt9t013_poweron_af(void)
-{
- int32_t rc = 0;
-
- /* enable AF actuator */
- CDBG("enable AF actuator, gpio = %d\n",
- mt9t013_ctrl->sensordata->vcm_pwd);
- rc = gpio_request(mt9t013_ctrl->sensordata->vcm_pwd, "mt9t013");
- if (!rc) {
- gpio_direction_output(mt9t013_ctrl->sensordata->vcm_pwd, 0);
- mdelay(20);
- rc = mt9t013_set_default_focus(0);
- } else
- pr_err("%s, gpio_request failed (%d)!\n", __func__, rc);
- return rc;
-}
-
-static void mt9t013_poweroff_af(void)
-{
- gpio_direction_output(mt9t013_ctrl->sensordata->vcm_pwd, 1);
- gpio_free(mt9t013_ctrl->sensordata->vcm_pwd);
-}
-
-int mt9t013_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- mt9t013_ctrl = kzalloc(sizeof(struct mt9t013_ctrl), GFP_KERNEL);
- if (!mt9t013_ctrl) {
- pr_err("mt9t013_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- mt9t013_ctrl->fps_divider = 1 * 0x00000400;
- mt9t013_ctrl->pict_fps_divider = 1 * 0x00000400;
- mt9t013_ctrl->set_test = TEST_OFF;
- mt9t013_ctrl->prev_res = QTR_SIZE;
- mt9t013_ctrl->pict_res = FULL_SIZE;
-
- if (data)
- mt9t013_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9T013_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = mt9t013_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail;
-
- if (mt9t013_ctrl->prev_res == QTR_SIZE)
- rc = mt9t013_setting(REG_INIT, RES_PREVIEW);
- else
- rc = mt9t013_setting(REG_INIT, RES_CAPTURE);
-
- if (rc >= 0)
- rc = mt9t013_poweron_af();
-
- if (rc < 0)
- goto init_fail;
- else
- goto init_done;
-
-init_fail:
- kfree(mt9t013_ctrl);
-init_done:
- return rc;
-}
-
-static int mt9t013_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&mt9t013_wait_queue);
- return 0;
-}
-
-
-static int32_t mt9t013_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
- rc = mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_HOLD);
- if (rc < 0)
- return rc;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = mt9t013_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = mt9t013_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = mt9t013_raw_snapshot_config(mode);
- break;
-
- default:
- return -EINVAL;
- }
-
- /* FIXME: what should we do if rc < 0? */
- if (rc >= 0)
- return mt9t013_i2c_write_w(mt9t013_client->addr,
- REG_GROUPED_PARAMETER_HOLD,
- GROUPED_PARAMETER_UPDATE);
- return rc;
-}
-
-int mt9t013_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- long rc = 0;
-
- if (copy_from_user(&cdata, (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&mt9t013_sem);
-
- CDBG("mt9t013_sensor_config: cfgtype = %d\n", cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- mt9t013_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = mt9t013_get_prev_lines_pf();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = mt9t013_get_prev_pixels_pl();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = mt9t013_get_pict_lines_pf();
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl =
- mt9t013_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- mt9t013_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = mt9t013_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc = mt9t013_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- rc = mt9t013_set_pict_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc = mt9t013_set_sensor_mode(cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = mt9t013_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- rc = mt9t013_move_focus(cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc = mt9t013_set_default_focus(cdata.cfg.focus.steps);
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- cdata.max_steps = MT9T013_TOTAL_STEPS_NEAR_TO_FAR;
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_EFFECT:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&mt9t013_sem);
- return rc;
-}
-
-int mt9t013_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&mt9t013_sem);
-
- mt9t013_poweroff_af();
- mt9t013_power_down();
-
- gpio_direction_output(mt9t013_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(mt9t013_ctrl->sensordata->sensor_reset);
-
- kfree(mt9t013_ctrl);
-
- up(&mt9t013_sem);
- CDBG("mt9t013_release completed!\n");
- return rc;
-}
-
-static int mt9t013_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- rc = -ENOTSUPP;
- goto probe_failure;
- }
-
- mt9t013_sensorw =
- kzalloc(sizeof(struct mt9t013_work), GFP_KERNEL);
-
- if (!mt9t013_sensorw) {
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, mt9t013_sensorw);
- mt9t013_init_client(client);
- mt9t013_client = client;
- mt9t013_client->addr = mt9t013_client->addr >> 1;
- mdelay(50);
-
- CDBG("i2c probe ok\n");
- return 0;
-
-probe_failure:
- kfree(mt9t013_sensorw);
- mt9t013_sensorw = NULL;
- pr_err("i2c probe failure %d\n", rc);
- return rc;
-}
-
-static const struct i2c_device_id mt9t013_i2c_id[] = {
- { "mt9t013", 0},
- { }
-};
-
-static struct i2c_driver mt9t013_i2c_driver = {
- .id_table = mt9t013_i2c_id,
- .probe = mt9t013_i2c_probe,
- .remove = __exit_p(mt9t013_i2c_remove),
- .driver = {
- .name = "mt9t013",
- },
-};
-
-static int mt9t013_sensor_probe(
- const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- /* We expect this driver to match with the i2c device registered
- * in the board file immediately. */
- int rc = i2c_add_driver(&mt9t013_i2c_driver);
- if (rc < 0 || mt9t013_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_done;
- }
-
- /* enable mclk first */
- msm_camio_clk_rate_set(MT9T013_DEFAULT_CLOCK_RATE);
- mdelay(20);
-
- rc = mt9t013_probe_init_sensor(info);
- if (rc < 0) {
- i2c_del_driver(&mt9t013_i2c_driver);
- goto probe_done;
- }
-
- s->s_init = mt9t013_sensor_open_init;
- s->s_release = mt9t013_sensor_release;
- s->s_config = mt9t013_sensor_config;
- mt9t013_sensor_init_done(info);
-
-probe_done:
- return rc;
-}
-
-static int __mt9t013_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, mt9t013_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __mt9t013_probe,
- .driver = {
- .name = "msm_camera_mt9t013",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init mt9t013_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(mt9t013_init);
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef MT9T013_H
-#define MT9T013_H
-
-#include <linux/types.h>
-
-struct reg_struct {
- uint16_t vt_pix_clk_div; /* 0x0300 */
- uint16_t vt_sys_clk_div; /* 0x0302 */
- uint16_t pre_pll_clk_div; /* 0x0304 */
- uint16_t pll_multiplier; /* 0x0306 */
- uint16_t op_pix_clk_div; /* 0x0308 */
- uint16_t op_sys_clk_div; /* 0x030A */
- uint16_t scale_m; /* 0x0404 */
- uint16_t row_speed; /* 0x3016 */
- uint16_t x_addr_start; /* 0x3004 */
- uint16_t x_addr_end; /* 0x3008 */
- uint16_t y_addr_start; /* 0x3002 */
- uint16_t y_addr_end; /* 0x3006 */
- uint16_t read_mode; /* 0x3040 */
- uint16_t x_output_size; /* 0x034C */
- uint16_t y_output_size; /* 0x034E */
- uint16_t line_length_pck; /* 0x300C */
- uint16_t frame_length_lines; /* 0x300A */
- uint16_t coarse_int_time; /* 0x3012 */
- uint16_t fine_int_time; /* 0x3014 */
-};
-
-struct mt9t013_i2c_reg_conf {
- unsigned short waddr;
- unsigned short wdata;
-};
-
-struct mt9t013_reg {
- struct reg_struct *reg_pat;
- uint16_t reg_pat_size;
- struct mt9t013_i2c_reg_conf *ttbl;
- uint16_t ttbl_size;
- struct mt9t013_i2c_reg_conf *lctbl;
- uint16_t lctbl_size;
- struct mt9t013_i2c_reg_conf *rftbl;
- uint16_t rftbl_size;
-};
-
-#endif /* #define MT9T013_H */
+++ /dev/null
-/*
- * Copyright (C) 2009 QUALCOMM Incorporated.
- */
-
-#include "mt9t013.h"
-#include <linux/kernel.h>
-
-struct reg_struct const mt9t013_reg_pat[2] = {
- { /* Preview 2x2 binning 20fps, pclk MHz, MCLK 24MHz */
- /* vt_pix_clk_div:REG=0x0300 update get_snapshot_fps
- * if this change */
- 8,
-
- /* vt_sys_clk_div: REG=0x0302 update get_snapshot_fps
- * if this change */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps
- * if this change */
- 2,
-
- /* pll_multiplier REG=0x0306 60 for 30fps preview, 40
- * for 20fps preview
- * 46 for 30fps preview, try 47/48 to increase further */
- 46,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2053,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1541,
-
- /* read_mode REG=0x3040 */
- 0x046C,
-
- /* x_output_size REG=0x034C */
- 1024,
-
- /* y_output_size REG=0x034E */
- 768,
-
- /* line_length_pck REG=0x300C */
- 2616,
-
- /* frame_length_lines REG=0x300A */
- 916,
-
- /* coarse_int_time REG=0x3012 */
- 16,
-
- /* fine_int_time REG=0x3014 */
- 1461
- },
- { /*Snapshot */
- /* vt_pix_clk_div REG=0x0300 update get_snapshot_fps
- * if this change */
- 8,
-
- /* vt_sys_clk_div REG=0x0302 update get_snapshot_fps
- * if this change */
- 1,
-
- /* pre_pll_clk_div REG=0x0304 update get_snapshot_fps
- * if this change */
- 2,
-
- /* pll_multiplier REG=0x0306 50 for 15fps snapshot,
- * 40 for 10fps snapshot
- * 46 for 30fps snapshot, try 47/48 to increase further */
- 46,
-
- /* op_pix_clk_div REG=0x0308 */
- 8,
-
- /* op_sys_clk_div REG=0x030A */
- 1,
-
- /* scale_m REG=0x0404 */
- 16,
-
- /* row_speed REG=0x3016 */
- 0x0111,
-
- /* x_addr_start REG=0x3004 */
- 8,
-
- /* x_addr_end REG=0x3008 */
- 2071,
-
- /* y_addr_start REG=0x3002 */
- 8,
-
- /* y_addr_end REG=0x3006 */
- 1551,
-
- /* read_mode REG=0x3040 */
- 0x0024,
-
- /* x_output_size REG=0x034C */
- 2064,
-
- /* y_output_size REG=0x034E */
- 1544,
-
- /* line_length_pck REG=0x300C */
- 2952,
-
- /* frame_length_lines REG=0x300A */
- 1629,
-
- /* coarse_int_time REG=0x3012 */
- 16,
-
- /* fine_int_time REG=0x3014 */
- 733
- }
-};
-
-struct mt9t013_i2c_reg_conf mt9t013_test_tbl[] = {
- { 0x3044, 0x0544 & 0xFBFF },
- { 0x30CA, 0x0004 | 0x0001 },
- { 0x30D4, 0x9020 & 0x7FFF },
- { 0x31E0, 0x0003 & 0xFFFE },
- { 0x3180, 0x91FF & 0x7FFF },
- { 0x301A, (0x10CC | 0x8000) & 0xFFF7 },
- { 0x301E, 0x0000 },
- { 0x3780, 0x0000 },
-};
-
-/* [Lens shading 85 Percent TL84] */
-struct mt9t013_i2c_reg_conf mt9t013_lc_tbl[] = {
- { 0x360A, 0x0290 }, /* P_RD_P0Q0 */
- { 0x360C, 0xC92D }, /* P_RD_P0Q1 */
- { 0x360E, 0x0771 }, /* P_RD_P0Q2 */
- { 0x3610, 0xE38C }, /* P_RD_P0Q3 */
- { 0x3612, 0xD74F }, /* P_RD_P0Q4 */
- { 0x364A, 0x168C }, /* P_RD_P1Q0 */
- { 0x364C, 0xCACB }, /* P_RD_P1Q1 */
- { 0x364E, 0x8C4C }, /* P_RD_P1Q2 */
- { 0x3650, 0x0BEA }, /* P_RD_P1Q3 */
- { 0x3652, 0xDC0F }, /* P_RD_P1Q4 */
- { 0x368A, 0x70B0 }, /* P_RD_P2Q0 */
- { 0x368C, 0x200B }, /* P_RD_P2Q1 */
- { 0x368E, 0x30B2 }, /* P_RD_P2Q2 */
- { 0x3690, 0xD04F }, /* P_RD_P2Q3 */
- { 0x3692, 0xACF5 }, /* P_RD_P2Q4 */
- { 0x36CA, 0xF7C9 }, /* P_RD_P3Q0 */
- { 0x36CC, 0x2AED }, /* P_RD_P3Q1 */
- { 0x36CE, 0xA652 }, /* P_RD_P3Q2 */
- { 0x36D0, 0x8192 }, /* P_RD_P3Q3 */
- { 0x36D2, 0x3A15 }, /* P_RD_P3Q4 */
- { 0x370A, 0xDA30 }, /* P_RD_P4Q0 */
- { 0x370C, 0x2E2F }, /* P_RD_P4Q1 */
- { 0x370E, 0xBB56 }, /* P_RD_P4Q2 */
- { 0x3710, 0x8195 }, /* P_RD_P4Q3 */
- { 0x3712, 0x02F9 }, /* P_RD_P4Q4 */
- { 0x3600, 0x0230 }, /* P_GR_P0Q0 */
- { 0x3602, 0x58AD }, /* P_GR_P0Q1 */
- { 0x3604, 0x18D1 }, /* P_GR_P0Q2 */
- { 0x3606, 0x260D }, /* P_GR_P0Q3 */
- { 0x3608, 0xF530 }, /* P_GR_P0Q4 */
- { 0x3640, 0x17EB }, /* P_GR_P1Q0 */
- { 0x3642, 0x3CAB }, /* P_GR_P1Q1 */
- { 0x3644, 0x87CE }, /* P_GR_P1Q2 */
- { 0x3646, 0xC02E }, /* P_GR_P1Q3 */
- { 0x3648, 0xF48F }, /* P_GR_P1Q4 */
- { 0x3680, 0x5350 }, /* P_GR_P2Q0 */
- { 0x3682, 0x7EAF }, /* P_GR_P2Q1 */
- { 0x3684, 0x4312 }, /* P_GR_P2Q2 */
- { 0x3686, 0xC652 }, /* P_GR_P2Q3 */
- { 0x3688, 0xBC15 }, /* P_GR_P2Q4 */
- { 0x36C0, 0xB8AD }, /* P_GR_P3Q0 */
- { 0x36C2, 0xBDCD }, /* P_GR_P3Q1 */
- { 0x36C4, 0xE4B2 }, /* P_GR_P3Q2 */
- { 0x36C6, 0xB50F }, /* P_GR_P3Q3 */
- { 0x36C8, 0x5B95 }, /* P_GR_P3Q4 */
- { 0x3700, 0xFC90 }, /* P_GR_P4Q0 */
- { 0x3702, 0x8C51 }, /* P_GR_P4Q1 */
- { 0x3704, 0xCED6 }, /* P_GR_P4Q2 */
- { 0x3706, 0xB594 }, /* P_GR_P4Q3 */
- { 0x3708, 0x0A39 }, /* P_GR_P4Q4 */
- { 0x3614, 0x0230 }, /* P_BL_P0Q0 */
- { 0x3616, 0x160D }, /* P_BL_P0Q1 */
- { 0x3618, 0x08D1 }, /* P_BL_P0Q2 */
- { 0x361A, 0x98AB }, /* P_BL_P0Q3 */
- { 0x361C, 0xEA50 }, /* P_BL_P0Q4 */
- { 0x3654, 0xB4EA }, /* P_BL_P1Q0 */
- { 0x3656, 0xEA6C }, /* P_BL_P1Q1 */
- { 0x3658, 0xFE08 }, /* P_BL_P1Q2 */
- { 0x365A, 0x2C6E }, /* P_BL_P1Q3 */
- { 0x365C, 0xEB0E }, /* P_BL_P1Q4 */
- { 0x3694, 0x6DF0 }, /* P_BL_P2Q0 */
- { 0x3696, 0x3ACF }, /* P_BL_P2Q1 */
- { 0x3698, 0x3E0F }, /* P_BL_P2Q2 */
- { 0x369A, 0xB2B1 }, /* P_BL_P2Q3 */
- { 0x369C, 0xC374 }, /* P_BL_P2Q4 */
- { 0x36D4, 0xF2AA }, /* P_BL_P3Q0 */
- { 0x36D6, 0x8CCC }, /* P_BL_P3Q1 */
- { 0x36D8, 0xDEF2 }, /* P_BL_P3Q2 */
- { 0x36DA, 0xFA11 }, /* P_BL_P3Q3 */
- { 0x36DC, 0x42F5 }, /* P_BL_P3Q4 */
- { 0x3714, 0xF4F1 }, /* P_BL_P4Q0 */
- { 0x3716, 0xF6F0 }, /* P_BL_P4Q1 */
- { 0x3718, 0x8FD6 }, /* P_BL_P4Q2 */
- { 0x371A, 0xEA14 }, /* P_BL_P4Q3 */
- { 0x371C, 0x6338 }, /* P_BL_P4Q4 */
- { 0x361E, 0x0350 }, /* P_GB_P0Q0 */
- { 0x3620, 0x91AE }, /* P_GB_P0Q1 */
- { 0x3622, 0x0571 }, /* P_GB_P0Q2 */
- { 0x3624, 0x100D }, /* P_GB_P0Q3 */
- { 0x3626, 0xCA70 }, /* P_GB_P0Q4 */
- { 0x365E, 0xE6CB }, /* P_GB_P1Q0 */
- { 0x3660, 0x50ED }, /* P_GB_P1Q1 */
- { 0x3662, 0x3DAE }, /* P_GB_P1Q2 */
- { 0x3664, 0xAA4F }, /* P_GB_P1Q3 */
- { 0x3666, 0xDC50 }, /* P_GB_P1Q4 */
- { 0x369E, 0x5470 }, /* P_GB_P2Q0 */
- { 0x36A0, 0x1F6E }, /* P_GB_P2Q1 */
- { 0x36A2, 0x6671 }, /* P_GB_P2Q2 */
- { 0x36A4, 0xC010 }, /* P_GB_P2Q3 */
- { 0x36A6, 0x8DF5 }, /* P_GB_P2Q4 */
- { 0x36DE, 0x0B0C }, /* P_GB_P3Q0 */
- { 0x36E0, 0x84CE }, /* P_GB_P3Q1 */
- { 0x36E2, 0x8493 }, /* P_GB_P3Q2 */
- { 0x36E4, 0xA610 }, /* P_GB_P3Q3 */
- { 0x36E6, 0x50B5 }, /* P_GB_P3Q4 */
- { 0x371E, 0x9651 }, /* P_GB_P4Q0 */
- { 0x3720, 0x1EAB }, /* P_GB_P4Q1 */
- { 0x3722, 0xAF76 }, /* P_GB_P4Q2 */
- { 0x3724, 0xE4F4 }, /* P_GB_P4Q3 */
- { 0x3726, 0x79F8 }, /* P_GB_P4Q4 */
- { 0x3782, 0x0410 }, /* POLY_ORIGIN_C */
- { 0x3784, 0x0320 }, /* POLY_ORIGIN_R */
- { 0x3780, 0x8000 } /* POLY_SC_ENABLE */
-};
-
-struct mt9t013_reg mt9t013_regs = {
- .reg_pat = &mt9t013_reg_pat[0],
- .reg_pat_size = ARRAY_SIZE(mt9t013_reg_pat),
- .ttbl = &mt9t013_test_tbl[0],
- .ttbl_size = ARRAY_SIZE(mt9t013_test_tbl),
- .lctbl = &mt9t013_lc_tbl[0],
- .lctbl_size = ARRAY_SIZE(mt9t013_lc_tbl),
- .rftbl = &mt9t013_lc_tbl[0], /* &mt9t013_rolloff_tbl[0], */
- .rftbl_size = ARRAY_SIZE(mt9t013_lc_tbl)
-};
-
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <media/msm_camera.h>
-#include <mach/gpio.h>
-#include <mach/camera.h>
-#include "s5k3e2fx.h"
-
-#define S5K3E2FX_REG_MODEL_ID 0x0000
-#define S5K3E2FX_MODEL_ID 0x3E2F
-
-/* PLL Registers */
-#define REG_PRE_PLL_CLK_DIV 0x0305
-#define REG_PLL_MULTIPLIER_MSB 0x0306
-#define REG_PLL_MULTIPLIER_LSB 0x0307
-#define REG_VT_PIX_CLK_DIV 0x0301
-#define REG_VT_SYS_CLK_DIV 0x0303
-#define REG_OP_PIX_CLK_DIV 0x0309
-#define REG_OP_SYS_CLK_DIV 0x030B
-
-/* Data Format Registers */
-#define REG_CCP_DATA_FORMAT_MSB 0x0112
-#define REG_CCP_DATA_FORMAT_LSB 0x0113
-
-/* Output Size */
-#define REG_X_OUTPUT_SIZE_MSB 0x034C
-#define REG_X_OUTPUT_SIZE_LSB 0x034D
-#define REG_Y_OUTPUT_SIZE_MSB 0x034E
-#define REG_Y_OUTPUT_SIZE_LSB 0x034F
-
-/* Binning */
-#define REG_X_EVEN_INC 0x0381
-#define REG_X_ODD_INC 0x0383
-#define REG_Y_EVEN_INC 0x0385
-#define REG_Y_ODD_INC 0x0387
-/*Reserved register */
-#define REG_BINNING_ENABLE 0x3014
-
-/* Frame Fotmat */
-#define REG_FRAME_LENGTH_LINES_MSB 0x0340
-#define REG_FRAME_LENGTH_LINES_LSB 0x0341
-#define REG_LINE_LENGTH_PCK_MSB 0x0342
-#define REG_LINE_LENGTH_PCK_LSB 0x0343
-
-/* MSR setting */
-/* Reserved registers */
-#define REG_SHADE_CLK_ENABLE 0x30AC
-#define REG_SEL_CCP 0x30C4
-#define REG_VPIX 0x3024
-#define REG_CLAMP_ON 0x3015
-#define REG_OFFSET 0x307E
-
-/* CDS timing settings */
-/* Reserved registers */
-#define REG_LD_START 0x3000
-#define REG_LD_END 0x3001
-#define REG_SL_START 0x3002
-#define REG_SL_END 0x3003
-#define REG_RX_START 0x3004
-#define REG_S1_START 0x3005
-#define REG_S1_END 0x3006
-#define REG_S1S_START 0x3007
-#define REG_S1S_END 0x3008
-#define REG_S3_START 0x3009
-#define REG_S3_END 0x300A
-#define REG_CMP_EN_START 0x300B
-#define REG_CLP_SL_START 0x300C
-#define REG_CLP_SL_END 0x300D
-#define REG_OFF_START 0x300E
-#define REG_RMP_EN_START 0x300F
-#define REG_TX_START 0x3010
-#define REG_TX_END 0x3011
-#define REG_STX_WIDTH 0x3012
-#define REG_TYPE1_AF_ENABLE 0x3130
-#define DRIVER_ENABLED 0x0001
-#define AUTO_START_ENABLED 0x0010
-#define REG_NEW_POSITION 0x3131
-#define REG_3152_RESERVED 0x3152
-#define REG_315A_RESERVED 0x315A
-#define REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB 0x0204
-#define REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB 0x0205
-#define REG_FINE_INTEGRATION_TIME 0x0200
-#define REG_COARSE_INTEGRATION_TIME 0x0202
-#define REG_COARSE_INTEGRATION_TIME_LSB 0x0203
-
-/* Mode select register */
-#define S5K3E2FX_REG_MODE_SELECT 0x0100
-#define S5K3E2FX_MODE_SELECT_STREAM 0x01 /* start streaming */
-#define S5K3E2FX_MODE_SELECT_SW_STANDBY 0x00 /* software standby */
-#define S5K3E2FX_REG_SOFTWARE_RESET 0x0103
-#define S5K3E2FX_SOFTWARE_RESET 0x01
-#define REG_TEST_PATTERN_MODE 0x0601
-
-struct reg_struct {
- uint8_t pre_pll_clk_div; /* 0x0305 */
- uint8_t pll_multiplier_msb; /* 0x0306 */
- uint8_t pll_multiplier_lsb; /* 0x0307 */
- uint8_t vt_pix_clk_div; /* 0x0301 */
- uint8_t vt_sys_clk_div; /* 0x0303 */
- uint8_t op_pix_clk_div; /* 0x0309 */
- uint8_t op_sys_clk_div; /* 0x030B */
- uint8_t ccp_data_format_msb; /* 0x0112 */
- uint8_t ccp_data_format_lsb; /* 0x0113 */
- uint8_t x_output_size_msb; /* 0x034C */
- uint8_t x_output_size_lsb; /* 0x034D */
- uint8_t y_output_size_msb; /* 0x034E */
- uint8_t y_output_size_lsb; /* 0x034F */
- uint8_t x_even_inc; /* 0x0381 */
- uint8_t x_odd_inc; /* 0x0383 */
- uint8_t y_even_inc; /* 0x0385 */
- uint8_t y_odd_inc; /* 0x0387 */
- uint8_t binning_enable; /* 0x3014 */
- uint8_t frame_length_lines_msb; /* 0x0340 */
- uint8_t frame_length_lines_lsb; /* 0x0341 */
- uint8_t line_length_pck_msb; /* 0x0342 */
- uint8_t line_length_pck_lsb; /* 0x0343 */
- uint8_t shade_clk_enable ; /* 0x30AC */
- uint8_t sel_ccp; /* 0x30C4 */
- uint8_t vpix; /* 0x3024 */
- uint8_t clamp_on; /* 0x3015 */
- uint8_t offset; /* 0x307E */
- uint8_t ld_start; /* 0x3000 */
- uint8_t ld_end; /* 0x3001 */
- uint8_t sl_start; /* 0x3002 */
- uint8_t sl_end; /* 0x3003 */
- uint8_t rx_start; /* 0x3004 */
- uint8_t s1_start; /* 0x3005 */
- uint8_t s1_end; /* 0x3006 */
- uint8_t s1s_start; /* 0x3007 */
- uint8_t s1s_end; /* 0x3008 */
- uint8_t s3_start; /* 0x3009 */
- uint8_t s3_end; /* 0x300A */
- uint8_t cmp_en_start; /* 0x300B */
- uint8_t clp_sl_start; /* 0x300C */
- uint8_t clp_sl_end; /* 0x300D */
- uint8_t off_start; /* 0x300E */
- uint8_t rmp_en_start; /* 0x300F */
- uint8_t tx_start; /* 0x3010 */
- uint8_t tx_end; /* 0x3011 */
- uint8_t stx_width; /* 0x3012 */
- uint8_t reg_3152_reserved; /* 0x3152 */
- uint8_t reg_315A_reserved; /* 0x315A */
- uint8_t analogue_gain_code_global_msb; /* 0x0204 */
- uint8_t analogue_gain_code_global_lsb; /* 0x0205 */
- uint8_t fine_integration_time; /* 0x0200 */
- uint8_t coarse_integration_time; /* 0x0202 */
- uint32_t size_h;
- uint32_t blk_l;
- uint32_t size_w;
- uint32_t blk_p;
-};
-
-struct reg_struct s5k3e2fx_reg_pat[2] = {
- { /* Preview */
- 0x06, /* pre_pll_clk_div REG=0x0305 */
- 0x00, /* pll_multiplier_msb REG=0x0306 */
- 0x88, /* pll_multiplier_lsb REG=0x0307 */
- 0x0a, /* vt_pix_clk_div REG=0x0301 */
- 0x01, /* vt_sys_clk_div REG=0x0303 */
- 0x0a, /* op_pix_clk_div REG=0x0309 */
- 0x01, /* op_sys_clk_div REG=0x030B */
- 0x0a, /* ccp_data_format_msb REG=0x0112 */
- 0x0a, /* ccp_data_format_lsb REG=0x0113 */
- 0x05, /* x_output_size_msb REG=0x034C */
- 0x10, /* x_output_size_lsb REG=0x034D */
- 0x03, /* y_output_size_msb REG=0x034E */
- 0xcc, /* y_output_size_lsb REG=0x034F */
-
- /* enable binning for preview */
- 0x01, /* x_even_inc REG=0x0381 */
- 0x01, /* x_odd_inc REG=0x0383 */
- 0x01, /* y_even_inc REG=0x0385 */
- 0x03, /* y_odd_inc REG=0x0387 */
- 0x06, /* binning_enable REG=0x3014 */
-
- 0x03, /* frame_length_lines_msb REG=0x0340 */
- 0xde, /* frame_length_lines_lsb REG=0x0341 */
- 0x0a, /* line_length_pck_msb REG=0x0342 */
- 0xac, /* line_length_pck_lsb REG=0x0343 */
- 0x81, /* shade_clk_enable REG=0x30AC */
- 0x01, /* sel_ccp REG=0x30C4 */
- 0x04, /* vpix REG=0x3024 */
- 0x00, /* clamp_on REG=0x3015 */
- 0x02, /* offset REG=0x307E */
- 0x03, /* ld_start REG=0x3000 */
- 0x9c, /* ld_end REG=0x3001 */
- 0x02, /* sl_start REG=0x3002 */
- 0x9e, /* sl_end REG=0x3003 */
- 0x05, /* rx_start REG=0x3004 */
- 0x0f, /* s1_start REG=0x3005 */
- 0x24, /* s1_end REG=0x3006 */
- 0x7c, /* s1s_start REG=0x3007 */
- 0x9a, /* s1s_end REG=0x3008 */
- 0x10, /* s3_start REG=0x3009 */
- 0x14, /* s3_end REG=0x300A */
- 0x10, /* cmp_en_start REG=0x300B */
- 0x04, /* clp_sl_start REG=0x300C */
- 0x26, /* clp_sl_end REG=0x300D */
- 0x02, /* off_start REG=0x300E */
- 0x0e, /* rmp_en_start REG=0x300F */
- 0x30, /* tx_start REG=0x3010 */
- 0x4e, /* tx_end REG=0x3011 */
- 0x1E, /* stx_width REG=0x3012 */
- 0x08, /* reg_3152_reserved REG=0x3152 */
- 0x10, /* reg_315A_reserved REG=0x315A */
- 0x00, /* analogue_gain_code_global_msb REG=0x0204 */
- 0x80, /* analogue_gain_code_global_lsb REG=0x0205 */
- 0x02, /* fine_integration_time REG=0x0200 */
- 0x03, /* coarse_integration_time REG=0x0202 */
- 972,
- 18,
- 1296,
- 1436
- },
- { /* Snapshot */
- 0x06, /* pre_pll_clk_div REG=0x0305 */
- 0x00, /* pll_multiplier_msb REG=0x0306 */
- 0x88, /* pll_multiplier_lsb REG=0x0307 */
- 0x0a, /* vt_pix_clk_div REG=0x0301 */
- 0x01, /* vt_sys_clk_div REG=0x0303 */
- 0x0a, /* op_pix_clk_div REG=0x0309 */
- 0x01, /* op_sys_clk_div REG=0x030B */
- 0x0a, /* ccp_data_format_msb REG=0x0112 */
- 0x0a, /* ccp_data_format_lsb REG=0x0113 */
- 0x0a, /* x_output_size_msb REG=0x034C */
- 0x30, /* x_output_size_lsb REG=0x034D */
- 0x07, /* y_output_size_msb REG=0x034E */
- 0xa8, /* y_output_size_lsb REG=0x034F */
-
- /* disable binning for snapshot */
- 0x01, /* x_even_inc REG=0x0381 */
- 0x01, /* x_odd_inc REG=0x0383 */
- 0x01, /* y_even_inc REG=0x0385 */
- 0x01, /* y_odd_inc REG=0x0387 */
- 0x00, /* binning_enable REG=0x3014 */
-
- 0x07, /* frame_length_lines_msb REG=0x0340 */
- 0xb6, /* frame_length_lines_lsb REG=0x0341 */
- 0x0a, /* line_length_pck_msb REG=0x0342 */
- 0xac, /* line_length_pck_lsb REG=0x0343 */
- 0x81, /* shade_clk_enable REG=0x30AC */
- 0x01, /* sel_ccp REG=0x30C4 */
- 0x04, /* vpix REG=0x3024 */
- 0x00, /* clamp_on REG=0x3015 */
- 0x02, /* offset REG=0x307E */
- 0x03, /* ld_start REG=0x3000 */
- 0x9c, /* ld_end REG=0x3001 */
- 0x02, /* sl_start REG=0x3002 */
- 0x9e, /* sl_end REG=0x3003 */
- 0x05, /* rx_start REG=0x3004 */
- 0x0f, /* s1_start REG=0x3005 */
- 0x24, /* s1_end REG=0x3006 */
- 0x7c, /* s1s_start REG=0x3007 */
- 0x9a, /* s1s_end REG=0x3008 */
- 0x10, /* s3_start REG=0x3009 */
- 0x14, /* s3_end REG=0x300A */
- 0x10, /* cmp_en_start REG=0x300B */
- 0x04, /* clp_sl_start REG=0x300C */
- 0x26, /* clp_sl_end REG=0x300D */
- 0x02, /* off_start REG=0x300E */
- 0x0e, /* rmp_en_start REG=0x300F */
- 0x30, /* tx_start REG=0x3010 */
- 0x4e, /* tx_end REG=0x3011 */
- 0x1E, /* stx_width REG=0x3012 */
- 0x08, /* reg_3152_reserved REG=0x3152 */
- 0x10, /* reg_315A_reserved REG=0x315A */
- 0x00, /* analogue_gain_code_global_msb REG=0x0204 */
- 0x80, /* analogue_gain_code_global_lsb REG=0x0205 */
- 0x02, /* fine_integration_time REG=0x0200 */
- 0x03, /* coarse_integration_time REG=0x0202 */
- 1960,
- 14,
- 2608,
- 124
- }
-};
-
-struct s5k3e2fx_work {
- struct work_struct work;
-};
-static struct s5k3e2fx_work *s5k3e2fx_sensorw;
-static struct i2c_client *s5k3e2fx_client;
-
-struct s5k3e2fx_ctrl {
- const struct msm_camera_sensor_info *sensordata;
-
- int sensormode;
- uint32_t fps_divider; /* init to 1 * 0x00000400 */
- uint32_t pict_fps_divider; /* init to 1 * 0x00000400 */
-
- uint16_t curr_lens_pos;
- uint16_t init_curr_lens_pos;
- uint16_t my_reg_gain;
- uint32_t my_reg_line_count;
-
- enum msm_s_resolution prev_res;
- enum msm_s_resolution pict_res;
- enum msm_s_resolution curr_res;
- enum msm_s_test_mode set_test;
-};
-
-struct s5k3e2fx_i2c_reg_conf {
- unsigned short waddr;
- unsigned char bdata;
-};
-
-static struct s5k3e2fx_ctrl *s5k3e2fx_ctrl;
-static DECLARE_WAIT_QUEUE_HEAD(s5k3e2fx_wait_queue);
-DEFINE_SEMAPHORE(s5k3e2fx_sem);
-
-static int s5k3e2fx_i2c_rxdata(unsigned short saddr, unsigned char *rxdata,
- int length)
-{
- struct i2c_msg msgs[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = 2,
- .buf = rxdata,
- },
- {
- .addr = saddr,
- .flags = I2C_M_RD,
- .len = length,
- .buf = rxdata,
- },
- };
-
- if (i2c_transfer(s5k3e2fx_client->adapter, msgs, 2) < 0) {
- CDBG("s5k3e2fx_i2c_rxdata failed!\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t s5k3e2fx_i2c_txdata(unsigned short saddr,
- unsigned char *txdata, int length)
-{
- struct i2c_msg msg[] = {
- {
- .addr = saddr,
- .flags = 0,
- .len = length,
- .buf = txdata,
- },
- };
-
- if (i2c_transfer(s5k3e2fx_client->adapter, msg, 1) < 0) {
- CDBG("s5k3e2fx_i2c_txdata failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static int32_t s5k3e2fx_i2c_write_b(unsigned short saddr, unsigned short waddr,
- unsigned char bdata)
-{
- int32_t rc = -EIO;
- unsigned char buf[4];
-
- memset(buf, 0, sizeof(buf));
- buf[0] = (waddr & 0xFF00)>>8;
- buf[1] = (waddr & 0x00FF);
- buf[2] = bdata;
-
- rc = s5k3e2fx_i2c_txdata(saddr, buf, 3);
-
- if (rc < 0)
- CDBG("i2c_write_w failed, addr = 0x%x, val = 0x%x!\n",
- waddr, bdata);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_i2c_write_table(
- struct s5k3e2fx_i2c_reg_conf *reg_cfg_tbl, int num)
-{
- int i;
- int32_t rc = -EIO;
- for (i = 0; i < num; i++) {
- if (rc < 0)
- break;
- reg_cfg_tbl++;
- }
-
- return rc;
-}
-
-static int32_t s5k3e2fx_i2c_read_w(unsigned short saddr, unsigned short raddr,
- unsigned short *rdata)
-{
- int32_t rc = 0;
- unsigned char buf[4];
-
- if (!rdata)
- return -EIO;
-
- memset(buf, 0, sizeof(buf));
-
- buf[0] = (raddr & 0xFF00)>>8;
- buf[1] = (raddr & 0x00FF);
-
- rc = s5k3e2fx_i2c_rxdata(saddr, buf, 2);
- if (rc < 0)
- return rc;
-
- *rdata = buf[0] << 8 | buf[1];
-
- if (rc < 0)
- CDBG("s5k3e2fx_i2c_read failed!\n");
-
- return rc;
-}
-
-static int s5k3e2fx_probe_init_done(const struct msm_camera_sensor_info *data)
-{
- gpio_direction_output(data->sensor_reset, 0);
- gpio_free(data->sensor_reset);
- return 0;
-}
-
-static int s5k3e2fx_probe_init_sensor(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
- uint16_t chipid = 0;
-
- rc = gpio_request(data->sensor_reset, "s5k3e2fx");
- if (!rc)
- gpio_direction_output(data->sensor_reset, 1);
- else
- goto init_probe_done;
-
- mdelay(20);
-
- CDBG("s5k3e2fx_sensor_init(): reseting sensor.\n");
-
- rc = s5k3e2fx_i2c_read_w(s5k3e2fx_client->addr,
- S5K3E2FX_REG_MODEL_ID, &chipid);
- if (rc < 0)
- goto init_probe_fail;
-
- if (chipid != S5K3E2FX_MODEL_ID) {
- CDBG("S5K3E2FX wrong model_id = 0x%x\n", chipid);
- rc = -ENODEV;
- goto init_probe_fail;
- }
-
- goto init_probe_done;
-
-init_probe_fail:
- s5k3e2fx_probe_init_done(data);
-init_probe_done:
- return rc;
-}
-
-static int s5k3e2fx_init_client(struct i2c_client *client)
-{
- /* Initialize the MSM_CAMI2C Chip */
- init_waitqueue_head(&s5k3e2fx_wait_queue);
- return 0;
-}
-
-static const struct i2c_device_id s5k3e2fx_i2c_id[] = {
- { "s5k3e2fx", 0},
- { }
-};
-
-static int s5k3e2fx_i2c_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-{
- int rc = 0;
- CDBG("s5k3e2fx_probe called!\n");
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- CDBG("i2c_check_functionality failed\n");
- goto probe_failure;
- }
-
- s5k3e2fx_sensorw = kzalloc(sizeof(struct s5k3e2fx_work), GFP_KERNEL);
- if (!s5k3e2fx_sensorw) {
- CDBG("kzalloc failed.\n");
- rc = -ENOMEM;
- goto probe_failure;
- }
-
- i2c_set_clientdata(client, s5k3e2fx_sensorw);
- s5k3e2fx_init_client(client);
- s5k3e2fx_client = client;
-
- mdelay(50);
-
- CDBG("s5k3e2fx_probe successed! rc = %d\n", rc);
- return 0;
-
-probe_failure:
- CDBG("s5k3e2fx_probe failed! rc = %d\n", rc);
- return rc;
-}
-
-static struct i2c_driver s5k3e2fx_i2c_driver = {
- .id_table = s5k3e2fx_i2c_id,
- .probe = s5k3e2fx_i2c_probe,
- .remove = __exit_p(s5k3e2fx_i2c_remove),
- .driver = {
- .name = "s5k3e2fx",
- },
-};
-
-static int32_t s5k3e2fx_test(enum msm_s_test_mode mo)
-{
- int32_t rc = 0;
-
- if (mo == S_TEST_OFF)
- rc = 0;
- else
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_TEST_PATTERN_MODE, (uint16_t)mo);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_setting(enum msm_s_reg_update rupdate,
- enum msm_s_setting rt)
-{
- int32_t rc = 0;
- uint16_t num_lperf;
-
- switch (rupdate) {
- case S_UPDATE_PERIODIC:
- if (rt == S_RES_PREVIEW || rt == S_RES_CAPTURE) {
-
- struct s5k3e2fx_i2c_reg_conf tbl_1[] = {
- {REG_CCP_DATA_FORMAT_MSB, s5k3e2fx_reg_pat[rt].ccp_data_format_msb},
- {REG_CCP_DATA_FORMAT_LSB, s5k3e2fx_reg_pat[rt].ccp_data_format_lsb},
- {REG_X_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].x_output_size_msb},
- {REG_X_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].x_output_size_lsb},
- {REG_Y_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].y_output_size_msb},
- {REG_Y_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].y_output_size_lsb},
- {REG_X_EVEN_INC, s5k3e2fx_reg_pat[rt].x_even_inc},
- {REG_X_ODD_INC, s5k3e2fx_reg_pat[rt].x_odd_inc},
- {REG_Y_EVEN_INC, s5k3e2fx_reg_pat[rt].y_even_inc},
- {REG_Y_ODD_INC, s5k3e2fx_reg_pat[rt].y_odd_inc},
- {REG_BINNING_ENABLE, s5k3e2fx_reg_pat[rt].binning_enable},
- };
-
- struct s5k3e2fx_i2c_reg_conf tbl_2[] = {
- {REG_FRAME_LENGTH_LINES_MSB, 0},
- {REG_FRAME_LENGTH_LINES_LSB, 0},
- {REG_LINE_LENGTH_PCK_MSB, s5k3e2fx_reg_pat[rt].line_length_pck_msb},
- {REG_LINE_LENGTH_PCK_LSB, s5k3e2fx_reg_pat[rt].line_length_pck_lsb},
- {REG_SHADE_CLK_ENABLE, s5k3e2fx_reg_pat[rt].shade_clk_enable},
- {REG_SEL_CCP, s5k3e2fx_reg_pat[rt].sel_ccp},
- {REG_VPIX, s5k3e2fx_reg_pat[rt].vpix},
- {REG_CLAMP_ON, s5k3e2fx_reg_pat[rt].clamp_on},
- {REG_OFFSET, s5k3e2fx_reg_pat[rt].offset},
- {REG_LD_START, s5k3e2fx_reg_pat[rt].ld_start},
- {REG_LD_END, s5k3e2fx_reg_pat[rt].ld_end},
- {REG_SL_START, s5k3e2fx_reg_pat[rt].sl_start},
- {REG_SL_END, s5k3e2fx_reg_pat[rt].sl_end},
- {REG_RX_START, s5k3e2fx_reg_pat[rt].rx_start},
- {REG_S1_START, s5k3e2fx_reg_pat[rt].s1_start},
- {REG_S1_END, s5k3e2fx_reg_pat[rt].s1_end},
- {REG_S1S_START, s5k3e2fx_reg_pat[rt].s1s_start},
- {REG_S1S_END, s5k3e2fx_reg_pat[rt].s1s_end},
- {REG_S3_START, s5k3e2fx_reg_pat[rt].s3_start},
- {REG_S3_END, s5k3e2fx_reg_pat[rt].s3_end},
- {REG_CMP_EN_START, s5k3e2fx_reg_pat[rt].cmp_en_start},
- {REG_CLP_SL_START, s5k3e2fx_reg_pat[rt].clp_sl_start},
- {REG_CLP_SL_END, s5k3e2fx_reg_pat[rt].clp_sl_end},
- {REG_OFF_START, s5k3e2fx_reg_pat[rt].off_start},
- {REG_RMP_EN_START, s5k3e2fx_reg_pat[rt].rmp_en_start},
- {REG_TX_START, s5k3e2fx_reg_pat[rt].tx_start},
- {REG_TX_END, s5k3e2fx_reg_pat[rt].tx_end},
- {REG_STX_WIDTH, s5k3e2fx_reg_pat[rt].stx_width},
- {REG_3152_RESERVED, s5k3e2fx_reg_pat[rt].reg_3152_reserved},
- {REG_315A_RESERVED, s5k3e2fx_reg_pat[rt].reg_315A_reserved},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_msb},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_lsb},
- {REG_FINE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].fine_integration_time},
- {REG_COARSE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].coarse_integration_time},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_STREAM},
- };
-
- rc = s5k3e2fx_i2c_write_table(&tbl_1[0],
- ARRAY_SIZE(tbl_1));
- if (rc < 0)
- return rc;
-
- num_lperf =
- (uint16_t)((s5k3e2fx_reg_pat[rt].frame_length_lines_msb << 8) & 0xFF00) +
- s5k3e2fx_reg_pat[rt].frame_length_lines_lsb;
-
- num_lperf = num_lperf * s5k3e2fx_ctrl->fps_divider / 0x0400;
-
- tbl_2[0] = (struct s5k3e2fx_i2c_reg_conf) {REG_FRAME_LENGTH_LINES_MSB, (num_lperf & 0xFF00) >> 8};
- tbl_2[1] = (struct s5k3e2fx_i2c_reg_conf) {REG_FRAME_LENGTH_LINES_LSB, (num_lperf & 0x00FF)};
-
- rc = s5k3e2fx_i2c_write_table(&tbl_2[0],
- ARRAY_SIZE(tbl_2));
- if (rc < 0)
- return rc;
-
- mdelay(5);
-
- rc = s5k3e2fx_test(s5k3e2fx_ctrl->set_test);
- if (rc < 0)
- return rc;
- }
- break; /* UPDATE_PERIODIC */
-
- case S_REG_INIT:
- if (rt == S_RES_PREVIEW || rt == S_RES_CAPTURE) {
-
- struct s5k3e2fx_i2c_reg_conf tbl_3[] = {
- {S5K3E2FX_REG_SOFTWARE_RESET, S5K3E2FX_SOFTWARE_RESET},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_SW_STANDBY},
- /* PLL setting */
- {REG_PRE_PLL_CLK_DIV, s5k3e2fx_reg_pat[rt].pre_pll_clk_div},
- {REG_PLL_MULTIPLIER_MSB, s5k3e2fx_reg_pat[rt].pll_multiplier_msb},
- {REG_PLL_MULTIPLIER_LSB, s5k3e2fx_reg_pat[rt].pll_multiplier_lsb},
- {REG_VT_PIX_CLK_DIV, s5k3e2fx_reg_pat[rt].vt_pix_clk_div},
- {REG_VT_SYS_CLK_DIV, s5k3e2fx_reg_pat[rt].vt_sys_clk_div},
- {REG_OP_PIX_CLK_DIV, s5k3e2fx_reg_pat[rt].op_pix_clk_div},
- {REG_OP_SYS_CLK_DIV, s5k3e2fx_reg_pat[rt].op_sys_clk_div},
- /*Data Format */
- {REG_CCP_DATA_FORMAT_MSB, s5k3e2fx_reg_pat[rt].ccp_data_format_msb},
- {REG_CCP_DATA_FORMAT_LSB, s5k3e2fx_reg_pat[rt].ccp_data_format_lsb},
- /*Output Size */
- {REG_X_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].x_output_size_msb},
- {REG_X_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].x_output_size_lsb},
- {REG_Y_OUTPUT_SIZE_MSB, s5k3e2fx_reg_pat[rt].y_output_size_msb},
- {REG_Y_OUTPUT_SIZE_LSB, s5k3e2fx_reg_pat[rt].y_output_size_lsb},
- /* Binning */
- {REG_X_EVEN_INC, s5k3e2fx_reg_pat[rt].x_even_inc},
- {REG_X_ODD_INC, s5k3e2fx_reg_pat[rt].x_odd_inc },
- {REG_Y_EVEN_INC, s5k3e2fx_reg_pat[rt].y_even_inc},
- {REG_Y_ODD_INC, s5k3e2fx_reg_pat[rt].y_odd_inc},
- {REG_BINNING_ENABLE, s5k3e2fx_reg_pat[rt].binning_enable},
- /* Frame format */
- {REG_FRAME_LENGTH_LINES_MSB, s5k3e2fx_reg_pat[rt].frame_length_lines_msb},
- {REG_FRAME_LENGTH_LINES_LSB, s5k3e2fx_reg_pat[rt].frame_length_lines_lsb},
- {REG_LINE_LENGTH_PCK_MSB, s5k3e2fx_reg_pat[rt].line_length_pck_msb},
- {REG_LINE_LENGTH_PCK_LSB, s5k3e2fx_reg_pat[rt].line_length_pck_lsb},
- /* MSR setting */
- {REG_SHADE_CLK_ENABLE, s5k3e2fx_reg_pat[rt].shade_clk_enable},
- {REG_SEL_CCP, s5k3e2fx_reg_pat[rt].sel_ccp},
- {REG_VPIX, s5k3e2fx_reg_pat[rt].vpix},
- {REG_CLAMP_ON, s5k3e2fx_reg_pat[rt].clamp_on},
- {REG_OFFSET, s5k3e2fx_reg_pat[rt].offset},
- /* CDS timing setting */
- {REG_LD_START, s5k3e2fx_reg_pat[rt].ld_start},
- {REG_LD_END, s5k3e2fx_reg_pat[rt].ld_end},
- {REG_SL_START, s5k3e2fx_reg_pat[rt].sl_start},
- {REG_SL_END, s5k3e2fx_reg_pat[rt].sl_end},
- {REG_RX_START, s5k3e2fx_reg_pat[rt].rx_start},
- {REG_S1_START, s5k3e2fx_reg_pat[rt].s1_start},
- {REG_S1_END, s5k3e2fx_reg_pat[rt].s1_end},
- {REG_S1S_START, s5k3e2fx_reg_pat[rt].s1s_start},
- {REG_S1S_END, s5k3e2fx_reg_pat[rt].s1s_end},
- {REG_S3_START, s5k3e2fx_reg_pat[rt].s3_start},
- {REG_S3_END, s5k3e2fx_reg_pat[rt].s3_end},
- {REG_CMP_EN_START, s5k3e2fx_reg_pat[rt].cmp_en_start},
- {REG_CLP_SL_START, s5k3e2fx_reg_pat[rt].clp_sl_start},
- {REG_CLP_SL_END, s5k3e2fx_reg_pat[rt].clp_sl_end},
- {REG_OFF_START, s5k3e2fx_reg_pat[rt].off_start},
- {REG_RMP_EN_START, s5k3e2fx_reg_pat[rt].rmp_en_start},
- {REG_TX_START, s5k3e2fx_reg_pat[rt].tx_start},
- {REG_TX_END, s5k3e2fx_reg_pat[rt].tx_end},
- {REG_STX_WIDTH, s5k3e2fx_reg_pat[rt].stx_width},
- {REG_3152_RESERVED, s5k3e2fx_reg_pat[rt].reg_3152_reserved},
- {REG_315A_RESERVED, s5k3e2fx_reg_pat[rt].reg_315A_reserved},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_msb},
- {REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB, s5k3e2fx_reg_pat[rt].analogue_gain_code_global_lsb},
- {REG_FINE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].fine_integration_time},
- {REG_COARSE_INTEGRATION_TIME, s5k3e2fx_reg_pat[rt].coarse_integration_time},
- {S5K3E2FX_REG_MODE_SELECT, S5K3E2FX_MODE_SELECT_STREAM},
- };
-
- /* reset fps_divider */
- s5k3e2fx_ctrl->fps_divider = 1 * 0x0400;
- rc = s5k3e2fx_i2c_write_table(&tbl_3[0],
- ARRAY_SIZE(tbl_3));
- if (rc < 0)
- return rc;
- }
- break; /* case REG_INIT: */
-
- default:
- rc = -EINVAL;
- break;
- } /* switch (rupdate) */
-
- return rc;
-}
-
-static int s5k3e2fx_sensor_open_init(const struct msm_camera_sensor_info *data)
-{
- int32_t rc;
-
- s5k3e2fx_ctrl = kzalloc(sizeof(struct s5k3e2fx_ctrl), GFP_KERNEL);
- if (!s5k3e2fx_ctrl) {
- CDBG("s5k3e2fx_init failed!\n");
- rc = -ENOMEM;
- goto init_done;
- }
-
- s5k3e2fx_ctrl->fps_divider = 1 * 0x00000400;
- s5k3e2fx_ctrl->pict_fps_divider = 1 * 0x00000400;
- s5k3e2fx_ctrl->set_test = S_TEST_OFF;
- s5k3e2fx_ctrl->prev_res = S_QTR_SIZE;
- s5k3e2fx_ctrl->pict_res = S_FULL_SIZE;
-
- if (data)
- s5k3e2fx_ctrl->sensordata = data;
-
- /* enable mclk first */
- msm_camio_clk_rate_set(24000000);
- mdelay(20);
-
- msm_camio_camif_pad_reg_reset();
- mdelay(20);
-
- rc = s5k3e2fx_probe_init_sensor(data);
- if (rc < 0)
- goto init_fail1;
-
- if (s5k3e2fx_ctrl->prev_res == S_QTR_SIZE)
- rc = s5k3e2fx_setting(S_REG_INIT, S_RES_PREVIEW);
- else
- rc = s5k3e2fx_setting(S_REG_INIT, S_RES_CAPTURE);
-
- if (rc < 0) {
- CDBG("s5k3e2fx_setting failed. rc = %d\n", rc);
- goto init_fail1;
- }
-
- /* initialize AF */
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3146, 0x3A);
- if (rc < 0)
- goto init_fail1;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3130, 0x03);
- if (rc < 0)
- goto init_fail1;
-
- goto init_done;
-
-init_fail1:
- s5k3e2fx_probe_init_done(data);
- kfree(s5k3e2fx_ctrl);
-init_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_power_down(void)
-{
- int32_t rc = 0;
- return rc;
-}
-
-static int s5k3e2fx_sensor_release(void)
-{
- int rc = -EBADF;
-
- down(&s5k3e2fx_sem);
-
- s5k3e2fx_power_down();
-
- gpio_direction_output(s5k3e2fx_ctrl->sensordata->sensor_reset,
- 0);
- gpio_free(s5k3e2fx_ctrl->sensordata->sensor_reset);
-
- kfree(s5k3e2fx_ctrl);
- s5k3e2fx_ctrl = NULL;
-
- CDBG("s5k3e2fx_release completed\n");
-
- up(&s5k3e2fx_sem);
- return rc;
-}
-
-static void s5k3e2fx_get_pict_fps(uint16_t fps, uint16_t *pfps)
-{
- /* input fps is preview fps in Q8 format */
- uint32_t divider; /* Q10 */
-
- divider = (uint32_t)
- ((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- (s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p)) * 0x00000400 /
- ((s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l) *
- (s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p));
-
- /* Verify PCLK settings and frame sizes. */
- *pfps = (uint16_t)(fps * divider / 0x00000400);
-}
-
-static uint16_t s5k3e2fx_get_prev_lines_pf(void)
-{
- return (s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l);
-}
-
-static uint16_t s5k3e2fx_get_prev_pixels_pl(void)
-{
- return s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_p;
-}
-
-static uint16_t s5k3e2fx_get_pict_lines_pf(void)
-{
- return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-}
-
-static uint16_t s5k3e2fx_get_pict_pixels_pl(void)
-{
- return s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
-}
-
-static uint32_t s5k3e2fx_get_pict_max_exp_lc(void)
-{
- uint32_t snapshot_lines_per_frame;
-
- if (s5k3e2fx_ctrl->pict_res == S_QTR_SIZE)
- snapshot_lines_per_frame =
- s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l;
- else
- snapshot_lines_per_frame = 3961 * 3;
-
- return snapshot_lines_per_frame;
-}
-
-static int32_t s5k3e2fx_set_fps(struct fps_cfg *fps)
-{
- /* input is new fps in Q10 format */
- int32_t rc = 0;
-
- s5k3e2fx_ctrl->fps_divider = fps->fps_div;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_FRAME_LENGTH_LINES_MSB,
- (((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- s5k3e2fx_ctrl->fps_divider / 0x400) & 0xFF00) >> 8);
- if (rc < 0)
- goto set_fps_done;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- REG_FRAME_LENGTH_LINES_LSB,
- (((s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_PREVIEW].blk_l) *
- s5k3e2fx_ctrl->fps_divider / 0x400) & 0xFF00));
-
-set_fps_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_write_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- uint16_t max_legal_gain = 0x0200;
- uint32_t ll_ratio; /* Q10 */
- uint16_t ll_pck, fl_lines;
- uint16_t offset = 4;
- uint8_t gain_msb, gain_lsb;
- uint8_t intg_t_msb, intg_t_lsb;
- uint8_t ll_pck_msb, ll_pck_lsb, tmp;
-
- struct s5k3e2fx_i2c_reg_conf tbl[2];
-
- CDBG("Line:%d s5k3e2fx_write_exp_gain \n", __LINE__);
-
- if (s5k3e2fx_ctrl->sensormode == SENSOR_PREVIEW_MODE) {
-
- s5k3e2fx_ctrl->my_reg_gain = gain;
- s5k3e2fx_ctrl->my_reg_line_count = (uint16_t)line;
-
- fl_lines = s5k3e2fx_reg_pat[S_RES_PREVIEW].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-
- ll_pck = s5k3e2fx_reg_pat[S_RES_PREVIEW].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
-
- } else {
-
- fl_lines = s5k3e2fx_reg_pat[S_RES_CAPTURE].size_h +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_l;
-
- ll_pck = s5k3e2fx_reg_pat[S_RES_CAPTURE].size_w +
- s5k3e2fx_reg_pat[S_RES_CAPTURE].blk_p;
- }
-
- if (gain > max_legal_gain)
- gain = max_legal_gain;
-
- /* in Q10 */
- line = (line * s5k3e2fx_ctrl->fps_divider);
-
- if (fl_lines < (line / 0x400))
- ll_ratio = (line / (fl_lines - offset));
- else
- ll_ratio = 0x400;
-
- /* update gain registers */
- gain_msb = (gain & 0xFF00) >> 8;
- gain_lsb = gain & 0x00FF;
- tbl[0].waddr = REG_ANALOGUE_GAIN_CODE_GLOBAL_MSB;
- tbl[0].bdata = gain_msb;
- tbl[1].waddr = REG_ANALOGUE_GAIN_CODE_GLOBAL_LSB;
- tbl[1].bdata = gain_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
- if (rc < 0)
- goto write_gain_done;
-
- ll_pck = ll_pck * ll_ratio;
- ll_pck_msb = ((ll_pck / 0x400) & 0xFF00) >> 8;
- ll_pck_lsb = (ll_pck / 0x400) & 0x00FF;
- tbl[0].waddr = REG_LINE_LENGTH_PCK_MSB;
- tbl[0].bdata = s5k3e2fx_reg_pat[S_RES_PREVIEW].line_length_pck_msb;
- tbl[1].waddr = REG_LINE_LENGTH_PCK_LSB;
- tbl[1].bdata = s5k3e2fx_reg_pat[S_RES_PREVIEW].line_length_pck_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
- if (rc < 0)
- goto write_gain_done;
-
- tmp = (ll_pck * 0x400) / ll_ratio;
- intg_t_msb = (tmp & 0xFF00) >> 8;
- intg_t_lsb = (tmp & 0x00FF);
- tbl[0].waddr = REG_COARSE_INTEGRATION_TIME;
- tbl[0].bdata = intg_t_msb;
- tbl[1].waddr = REG_COARSE_INTEGRATION_TIME_LSB;
- tbl[1].bdata = intg_t_lsb;
- rc = s5k3e2fx_i2c_write_table(&tbl[0], ARRAY_SIZE(tbl));
-
-write_gain_done:
- return rc;
-}
-
-static int32_t s5k3e2fx_set_pict_exp_gain(uint16_t gain, uint32_t line)
-{
- int32_t rc = 0;
-
- CDBG("Line:%d s5k3e2fx_set_pict_exp_gain \n", __LINE__);
-
- rc =
- s5k3e2fx_write_exp_gain(gain, line);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_video_config(int mode, int res)
-{
- int32_t rc;
-
- switch (res) {
- case S_QTR_SIZE:
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_PREVIEW);
- if (rc < 0)
- return rc;
-
- CDBG("s5k3e2fx sensor configuration done!\n");
- break;
-
- case S_FULL_SIZE:
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- break;
-
- default:
- return 0;
- } /* switch */
-
- s5k3e2fx_ctrl->prev_res = res;
- s5k3e2fx_ctrl->curr_res = res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- rc =
- s5k3e2fx_write_exp_gain(s5k3e2fx_ctrl->my_reg_gain,
- s5k3e2fx_ctrl->my_reg_line_count);
-
- return rc;
-}
-
-static int32_t s5k3e2fx_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_res = s5k3e2fx_ctrl->pict_res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_raw_snapshot_config(int mode)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_setting(S_UPDATE_PERIODIC, S_RES_CAPTURE);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_res = s5k3e2fx_ctrl->pict_res;
- s5k3e2fx_ctrl->sensormode = mode;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_set_sensor_mode(int mode, int res)
-{
- int32_t rc = 0;
-
- switch (mode) {
- case SENSOR_PREVIEW_MODE:
- rc = s5k3e2fx_video_config(mode, res);
- break;
-
- case SENSOR_SNAPSHOT_MODE:
- rc = s5k3e2fx_snapshot_config(mode);
- break;
-
- case SENSOR_RAW_SNAPSHOT_MODE:
- rc = s5k3e2fx_raw_snapshot_config(mode);
- break;
-
- default:
- rc = -EINVAL;
- break;
- }
-
- return rc;
-}
-
-static int32_t s5k3e2fx_set_default_focus(void)
-{
- int32_t rc = 0;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- 0x3131, 0);
- if (rc < 0)
- return rc;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr,
- 0x3132, 0);
- if (rc < 0)
- return rc;
-
- s5k3e2fx_ctrl->curr_lens_pos = 0;
-
- return rc;
-}
-
-static int32_t s5k3e2fx_move_focus(int direction, int32_t num_steps)
-{
- int32_t rc = 0;
- int32_t i;
- int16_t step_direction;
- int16_t actual_step;
- int16_t next_pos, pos_offset;
- int16_t init_code = 50;
- uint8_t next_pos_msb, next_pos_lsb;
- int16_t s_move[5];
- uint32_t gain; /* Q10 format */
-
- if (direction == MOVE_NEAR)
- step_direction = 20;
- else if (direction == MOVE_FAR)
- step_direction = -20;
- else {
- CDBG("s5k3e2fx_move_focus failed at line %d ...\n", __LINE__);
- return -EINVAL;
- }
-
- actual_step = step_direction * (int16_t)num_steps;
- pos_offset = init_code + s5k3e2fx_ctrl->curr_lens_pos;
- gain = ((actual_step << 10) / 5) >> 10;
-
- for (i = 0; i <= 4; i++)
- s_move[i] = gain;
-
- /* Ring Damping Code */
- for (i = 0; i <= 4; i++) {
- next_pos = (int16_t)(pos_offset + s_move[i]);
-
- if (next_pos > (738 + init_code))
- next_pos = 738 + init_code;
- else if (next_pos < 0)
- next_pos = 0;
-
- CDBG("next_position in damping mode = %d\n", next_pos);
- /* Writing the Values to the actuator */
- if (next_pos == init_code)
- next_pos = 0x00;
-
- next_pos_msb = next_pos >> 8;
- next_pos_lsb = next_pos & 0x00FF;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3131, next_pos_msb);
- if (rc < 0)
- break;
-
- rc = s5k3e2fx_i2c_write_b(s5k3e2fx_client->addr, 0x3132, next_pos_lsb);
- if (rc < 0)
- break;
-
- pos_offset = next_pos;
- s5k3e2fx_ctrl->curr_lens_pos = pos_offset - init_code;
- if (i < 4)
- mdelay(3);
- }
-
- return rc;
-}
-
-static int s5k3e2fx_sensor_config(void __user *argp)
-{
- struct sensor_cfg_data cdata;
- long rc = 0;
-
- if (copy_from_user(&cdata,
- (void *)argp,
- sizeof(struct sensor_cfg_data)))
- return -EFAULT;
-
- down(&s5k3e2fx_sem);
-
- CDBG("%s: cfgtype = %d\n", __func__, cdata.cfgtype);
- switch (cdata.cfgtype) {
- case CFG_GET_PICT_FPS:
- s5k3e2fx_get_pict_fps(cdata.cfg.gfps.prevfps,
- &(cdata.cfg.gfps.pictfps));
-
- if (copy_to_user((void *)argp, &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_L_PF:
- cdata.cfg.prevl_pf = s5k3e2fx_get_prev_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PREV_P_PL:
- cdata.cfg.prevp_pl = s5k3e2fx_get_prev_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_L_PF:
- cdata.cfg.pictl_pf = s5k3e2fx_get_pict_lines_pf();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_P_PL:
- cdata.cfg.pictp_pl = s5k3e2fx_get_pict_pixels_pl();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_GET_PICT_MAX_EXP_LC:
- cdata.cfg.pict_max_exp_lc =
- s5k3e2fx_get_pict_max_exp_lc();
-
- if (copy_to_user((void *)argp,
- &cdata,
- sizeof(struct sensor_cfg_data)))
- rc = -EFAULT;
- break;
-
- case CFG_SET_FPS:
- case CFG_SET_PICT_FPS:
- rc = s5k3e2fx_set_fps(&(cdata.cfg.fps));
- break;
-
- case CFG_SET_EXP_GAIN:
- rc =
- s5k3e2fx_write_exp_gain(cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_PICT_EXP_GAIN:
- CDBG("Line:%d CFG_SET_PICT_EXP_GAIN \n", __LINE__);
- rc =
- s5k3e2fx_set_pict_exp_gain(
- cdata.cfg.exp_gain.gain,
- cdata.cfg.exp_gain.line);
- break;
-
- case CFG_SET_MODE:
- rc =
- s5k3e2fx_set_sensor_mode(
- cdata.mode, cdata.rs);
- break;
-
- case CFG_PWR_DOWN:
- rc = s5k3e2fx_power_down();
- break;
-
- case CFG_MOVE_FOCUS:
- rc =
- s5k3e2fx_move_focus(
- cdata.cfg.focus.dir,
- cdata.cfg.focus.steps);
- break;
-
- case CFG_SET_DEFAULT_FOCUS:
- rc =
- s5k3e2fx_set_default_focus();
- break;
-
- case CFG_GET_AF_MAX_STEPS:
- case CFG_SET_EFFECT:
- case CFG_SET_LENS_SHADING:
- default:
- rc = -EINVAL;
- break;
- }
-
- up(&s5k3e2fx_sem);
- return rc;
-}
-
-static int s5k3e2fx_sensor_probe(const struct msm_camera_sensor_info *info,
- struct msm_sensor_ctrl *s)
-{
- int rc = 0;
-
- rc = i2c_add_driver(&s5k3e2fx_i2c_driver);
- if (rc < 0 || s5k3e2fx_client == NULL) {
- rc = -ENOTSUPP;
- goto probe_fail;
- }
-
- msm_camio_clk_rate_set(24000000);
- mdelay(20);
-
- rc = s5k3e2fx_probe_init_sensor(info);
- if (rc < 0)
- goto probe_fail;
-
- s->s_init = s5k3e2fx_sensor_open_init;
- s->s_release = s5k3e2fx_sensor_release;
- s->s_config = s5k3e2fx_sensor_config;
- s5k3e2fx_probe_init_done(info);
-
- return rc;
-
-probe_fail:
- CDBG("SENSOR PROBE FAILS!\n");
- return rc;
-}
-
-static int __s5k3e2fx_probe(struct platform_device *pdev)
-{
- return msm_camera_drv_start(pdev, s5k3e2fx_sensor_probe);
-}
-
-static struct platform_driver msm_camera_driver = {
- .probe = __s5k3e2fx_probe,
- .driver = {
- .name = "msm_camera_s5k3e2fx",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init s5k3e2fx_init(void)
-{
- return platform_driver_register(&msm_camera_driver);
-}
-
-module_init(s5k3e2fx_init);
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef CAMSENSOR_S5K3E2FX
-#define CAMSENSOR_S5K3E2FX
-
-#include <mach/board.h>
-#endif /* CAMSENSOR_S5K3E2FX */
+++ /dev/null
-/* arch/arm/mach-msm/generic_gpio.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <asm/gpio.h>
-#include "gpio_chip.h"
-
-#define GPIO_NUM_TO_CHIP_INDEX(gpio) ((gpio)>>5)
-
-struct gpio_state {
- unsigned long flags;
- int refcount;
-};
-
-static DEFINE_SPINLOCK(gpio_chips_lock);
-static LIST_HEAD(gpio_chip_list);
-static struct gpio_chip **gpio_chip_array;
-static unsigned long gpio_chip_array_size;
-
-int register_gpio_chip(struct gpio_chip *new_gpio_chip)
-{
- int err = 0;
- struct gpio_chip *gpio_chip;
- int i;
- unsigned long irq_flags;
- unsigned int chip_array_start_index, chip_array_end_index;
-
- new_gpio_chip->state = kzalloc((new_gpio_chip->end + 1 - new_gpio_chip->start) * sizeof(new_gpio_chip->state[0]), GFP_KERNEL);
- if (new_gpio_chip->state == NULL) {
- printk(KERN_ERR "register_gpio_chip: failed to allocate state\n");
- return -ENOMEM;
- }
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip_array_start_index = GPIO_NUM_TO_CHIP_INDEX(new_gpio_chip->start);
- chip_array_end_index = GPIO_NUM_TO_CHIP_INDEX(new_gpio_chip->end);
- if (chip_array_end_index >= gpio_chip_array_size) {
- struct gpio_chip **new_gpio_chip_array;
- unsigned long new_gpio_chip_array_size = chip_array_end_index + 1;
-
- new_gpio_chip_array = kmalloc(new_gpio_chip_array_size * sizeof(new_gpio_chip_array[0]), GFP_ATOMIC);
- if (new_gpio_chip_array == NULL) {
- printk(KERN_ERR "register_gpio_chip: failed to allocate array\n");
- err = -ENOMEM;
- goto failed;
- }
- for (i = 0; i < gpio_chip_array_size; i++)
- new_gpio_chip_array[i] = gpio_chip_array[i];
- for (i = gpio_chip_array_size; i < new_gpio_chip_array_size; i++)
- new_gpio_chip_array[i] = NULL;
- gpio_chip_array = new_gpio_chip_array;
- gpio_chip_array_size = new_gpio_chip_array_size;
- }
- list_for_each_entry(gpio_chip, &gpio_chip_list, list) {
- if (gpio_chip->start > new_gpio_chip->end) {
- list_add_tail(&new_gpio_chip->list, &gpio_chip->list);
- goto added;
- }
- if (gpio_chip->end >= new_gpio_chip->start) {
- printk(KERN_ERR "register_gpio_source %u-%u overlaps with %u-%u\n",
- new_gpio_chip->start, new_gpio_chip->end,
- gpio_chip->start, gpio_chip->end);
- err = -EBUSY;
- goto failed;
- }
- }
- list_add_tail(&new_gpio_chip->list, &gpio_chip_list);
-added:
- for (i = chip_array_start_index; i <= chip_array_end_index; i++) {
- if (gpio_chip_array[i] == NULL || gpio_chip_array[i]->start > new_gpio_chip->start)
- gpio_chip_array[i] = new_gpio_chip;
- }
-failed:
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- if (err)
- kfree(new_gpio_chip->state);
- return err;
-}
-
-static struct gpio_chip *get_gpio_chip_locked(unsigned int gpio)
-{
- unsigned long i;
- struct gpio_chip *chip;
-
- i = GPIO_NUM_TO_CHIP_INDEX(gpio);
- if (i >= gpio_chip_array_size)
- return NULL;
- chip = gpio_chip_array[i];
- if (chip == NULL)
- return NULL;
- list_for_each_entry_from(chip, &gpio_chip_list, list) {
- if (gpio < chip->start)
- return NULL;
- if (gpio <= chip->end)
- return chip;
- }
- return NULL;
-}
-
-static int request_gpio(unsigned int gpio, unsigned long flags)
-{
- int err = 0;
- struct gpio_chip *chip;
- unsigned long irq_flags;
- unsigned long chip_index;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip == NULL) {
- err = -EINVAL;
- goto err;
- }
- chip_index = gpio - chip->start;
- if (chip->state[chip_index].refcount == 0) {
- chip->configure(chip, gpio, flags);
- chip->state[chip_index].flags = flags;
- chip->state[chip_index].refcount++;
- } else if ((flags & IRQF_SHARED) && (chip->state[chip_index].flags & IRQF_SHARED))
- chip->state[chip_index].refcount++;
- else
- err = -EBUSY;
-err:
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return err;
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
- return request_gpio(gpio, 0);
-}
-EXPORT_SYMBOL(gpio_request);
-
-void gpio_free(unsigned gpio)
-{
- struct gpio_chip *chip;
- unsigned long irq_flags;
- unsigned long chip_index;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip) {
- chip_index = gpio - chip->start;
- chip->state[chip_index].refcount--;
- }
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
-}
-EXPORT_SYMBOL(gpio_free);
-
-static int gpio_get_irq_num(unsigned int gpio, unsigned int *irqp, unsigned long *irqnumflagsp)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->get_irq_num)
- ret = chip->get_irq_num(chip, gpio, irqp, irqnumflagsp);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-
-int gpio_to_irq(unsigned gpio)
-{
- int ret, irq;
- ret = gpio_get_irq_num(gpio, &irq, NULL);
- if (ret)
- return ret;
- return irq;
-}
-EXPORT_SYMBOL(gpio_to_irq);
-
-int gpio_configure(unsigned int gpio, unsigned long flags)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip)
- ret = chip->configure(chip, gpio, flags);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_configure);
-
-int gpio_direction_input(unsigned gpio)
-{
- return gpio_configure(gpio, GPIOF_INPUT);
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- gpio_set_value(gpio, value);
- return gpio_configure(gpio, GPIOF_DRIVE_OUTPUT);
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->read)
- ret = chip->read(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int on)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->write)
- ret = chip->write(chip, gpio, on);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
-}
-EXPORT_SYMBOL(gpio_set_value);
-
-int gpio_read_detect_status(unsigned int gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->read_detect_status)
- ret = chip->read_detect_status(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_read_detect_status);
-
-int gpio_clear_detect_status(unsigned int gpio)
-{
- int ret = -ENOTSUPP;
- struct gpio_chip *chip;
- unsigned long irq_flags;
-
- spin_lock_irqsave(&gpio_chips_lock, irq_flags);
- chip = get_gpio_chip_locked(gpio);
- if (chip && chip->clear_detect_status)
- ret = chip->clear_detect_status(chip, gpio);
- spin_unlock_irqrestore(&gpio_chips_lock, irq_flags);
- return ret;
-}
-EXPORT_SYMBOL(gpio_clear_detect_status);
+++ /dev/null
-/* drivers/input/misc/gpio_axis.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/gpio_event.h>
-#include <linux/interrupt.h>
-
-struct gpio_axis_state {
- struct input_dev *input_dev;
- struct gpio_event_axis_info *info;
- uint32_t pos;
-};
-
-uint16_t gpio_axis_4bit_gray_map_table[] = {
- [0x0] = 0x0, [0x1] = 0x1, /* 0000 0001 */
- [0x3] = 0x2, [0x2] = 0x3, /* 0011 0010 */
- [0x6] = 0x4, [0x7] = 0x5, /* 0110 0111 */
- [0x5] = 0x6, [0x4] = 0x7, /* 0101 0100 */
- [0xc] = 0x8, [0xd] = 0x9, /* 1100 1101 */
- [0xf] = 0xa, [0xe] = 0xb, /* 1111 1110 */
- [0xa] = 0xc, [0xb] = 0xd, /* 1010 1011 */
- [0x9] = 0xe, [0x8] = 0xf, /* 1001 1000 */
-};
-uint16_t gpio_axis_4bit_gray_map(struct gpio_event_axis_info *info, uint16_t in)
-{
- return gpio_axis_4bit_gray_map_table[in];
-}
-
-uint16_t gpio_axis_5bit_singletrack_map_table[] = {
- [0x10] = 0x00, [0x14] = 0x01, [0x1c] = 0x02, /* 10000 10100 11100 */
- [0x1e] = 0x03, [0x1a] = 0x04, [0x18] = 0x05, /* 11110 11010 11000 */
- [0x08] = 0x06, [0x0a] = 0x07, [0x0e] = 0x08, /* 01000 01010 01110 */
- [0x0f] = 0x09, [0x0d] = 0x0a, [0x0c] = 0x0b, /* 01111 01101 01100 */
- [0x04] = 0x0c, [0x05] = 0x0d, [0x07] = 0x0e, /* 00100 00101 00111 */
- [0x17] = 0x0f, [0x16] = 0x10, [0x06] = 0x11, /* 10111 10110 00110 */
- [0x02] = 0x12, [0x12] = 0x13, [0x13] = 0x14, /* 00010 10010 10011 */
- [0x1b] = 0x15, [0x0b] = 0x16, [0x03] = 0x17, /* 11011 01011 00011 */
- [0x01] = 0x18, [0x09] = 0x19, [0x19] = 0x1a, /* 00001 01001 11001 */
- [0x1d] = 0x1b, [0x15] = 0x1c, [0x11] = 0x1d, /* 11101 10101 10001 */
-};
-uint16_t gpio_axis_5bit_singletrack_map(
- struct gpio_event_axis_info *info, uint16_t in)
-{
- return gpio_axis_5bit_singletrack_map_table[in];
-}
-
-static void gpio_event_update_axis(struct gpio_axis_state *as, int report)
-{
- struct gpio_event_axis_info *ai = as->info;
- int i;
- int change;
- uint16_t state = 0;
- uint16_t pos;
- uint16_t old_pos = as->pos;
- for (i = ai->count - 1; i >= 0; i--)
- state = (state << 1) | gpio_get_value(ai->gpio[i]);
- pos = ai->map(ai, state);
- if (ai->flags & GPIOEAF_PRINT_RAW)
- pr_info("axis %d-%d raw %x, pos %d -> %d\n",
- ai->type, ai->code, state, old_pos, pos);
- if (report && pos != old_pos) {
- if (ai->type == EV_REL) {
- change = (ai->decoded_size + pos - old_pos) %
- ai->decoded_size;
- if (change > ai->decoded_size / 2)
- change -= ai->decoded_size;
- if (change == ai->decoded_size / 2) {
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d unknown direction, "
- "pos %d -> %d\n", ai->type,
- ai->code, old_pos, pos);
- change = 0; /* no closest direction */
- }
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d change %d\n",
- ai->type, ai->code, change);
- input_report_rel(as->input_dev, ai->code, change);
- } else {
- if (ai->flags & GPIOEAF_PRINT_EVENT)
- pr_info("axis %d-%d now %d\n",
- ai->type, ai->code, pos);
- input_event(as->input_dev, ai->type, ai->code, pos);
- }
- input_sync(as->input_dev);
- }
- as->pos = pos;
-}
-
-static irqreturn_t gpio_axis_irq_handler(int irq, void *dev_id)
-{
- struct gpio_axis_state *as = dev_id;
- gpio_event_update_axis(as, 1);
- return IRQ_HANDLED;
-}
-
-int gpio_event_axis_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func)
-{
- int ret;
- int i;
- int irq;
- struct gpio_event_axis_info *ai;
- struct gpio_axis_state *as;
-
- ai = container_of(info, struct gpio_event_axis_info, info);
- if (func == GPIO_EVENT_FUNC_SUSPEND) {
- for (i = 0; i < ai->count; i++)
- disable_irq(gpio_to_irq(ai->gpio[i]));
- return 0;
- }
- if (func == GPIO_EVENT_FUNC_RESUME) {
- for (i = 0; i < ai->count; i++)
- enable_irq(gpio_to_irq(ai->gpio[i]));
- return 0;
- }
-
- if (func == GPIO_EVENT_FUNC_INIT) {
- *data = as = kmalloc(sizeof(*as), GFP_KERNEL);
- if (as == NULL) {
- ret = -ENOMEM;
- goto err_alloc_axis_state_failed;
- }
- as->input_dev = input_dev;
- as->info = ai;
-
- input_set_capability(input_dev, ai->type, ai->code);
- if (ai->type == EV_ABS) {
- input_set_abs_params(input_dev, ai->code, 0,
- ai->decoded_size - 1, 0, 0);
- }
- for (i = 0; i < ai->count; i++) {
- ret = gpio_request(ai->gpio[i], "gpio_event_axis");
- if (ret < 0)
- goto err_request_gpio_failed;
- ret = gpio_direction_input(ai->gpio[i]);
- if (ret < 0)
- goto err_gpio_direction_input_failed;
- ret = irq = gpio_to_irq(ai->gpio[i]);
- if (ret < 0)
- goto err_get_irq_num_failed;
- ret = request_irq(irq, gpio_axis_irq_handler,
- IRQF_TRIGGER_RISING |
- IRQF_TRIGGER_FALLING,
- "gpio_event_axis", as);
- if (ret < 0)
- goto err_request_irq_failed;
- }
- gpio_event_update_axis(as, 0);
- return 0;
- }
-
- ret = 0;
- as = *data;
- for (i = ai->count - 1; i >= 0; i--) {
- free_irq(gpio_to_irq(ai->gpio[i]), as);
-err_request_irq_failed:
-err_get_irq_num_failed:
-err_gpio_direction_input_failed:
- gpio_free(ai->gpio[i]);
-err_request_gpio_failed:
- ;
- }
- kfree(as);
- *data = NULL;
-err_alloc_axis_state_failed:
- return ret;
-}
+++ /dev/null
-/* drivers/input/misc/gpio_event.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/input.h>
-#include <linux/gpio_event.h>
-#include <linux/hrtimer.h>
-#include <linux/platform_device.h>
-
-struct gpio_event {
- struct input_dev *input_dev;
- const struct gpio_event_platform_data *info;
- void *state[0];
-};
-
-static int gpio_input_event(
- struct input_dev *dev, unsigned int type, unsigned int code, int value)
-{
- int i;
- int ret = 0;
- int tmp_ret;
- struct gpio_event_info **ii;
- struct gpio_event *ip = input_get_drvdata(dev);
-
- for (i = 0, ii = ip->info->info; i < ip->info->info_count; i++, ii++) {
- if ((*ii)->event) {
- tmp_ret = (*ii)->event(ip->input_dev, *ii,
- &ip->state[i], type, code, value);
- if (tmp_ret)
- ret = tmp_ret;
- }
- }
- return ret;
-}
-
-static int gpio_event_call_all_func(struct gpio_event *ip, int func)
-{
- int i;
- int ret;
- struct gpio_event_info **ii;
-
- if (func == GPIO_EVENT_FUNC_INIT || func == GPIO_EVENT_FUNC_RESUME) {
- ii = ip->info->info;
- for (i = 0; i < ip->info->info_count; i++, ii++) {
- if ((*ii)->func == NULL) {
- ret = -ENODEV;
- pr_err("gpio_event_probe: Incomplete pdata, "
- "no function\n");
- goto err_no_func;
- }
- ret = (*ii)->func(ip->input_dev, *ii, &ip->state[i],
- func);
- if (ret) {
- pr_err("gpio_event_probe: function failed\n");
- goto err_func_failed;
- }
- }
- return 0;
- }
-
- ret = 0;
- i = ip->info->info_count;
- ii = ip->info->info + i;
- while (i > 0) {
- i--;
- ii--;
- (*ii)->func(ip->input_dev, *ii, &ip->state[i], func & ~1);
-err_func_failed:
-err_no_func:
- ;
- }
- return ret;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-void gpio_event_suspend(struct early_suspend *h)
-{
- struct gpio_event *ip;
- ip = container_of(h, struct gpio_event, early_suspend);
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_SUSPEND);
- ip->info->power(ip->info, 0);
-}
-
-void gpio_event_resume(struct early_suspend *h)
-{
- struct gpio_event *ip;
- ip = container_of(h, struct gpio_event, early_suspend);
- ip->info->power(ip->info, 1);
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_RESUME);
-}
-#endif
-
-static int __init gpio_event_probe(struct platform_device *pdev)
-{
- int err;
- struct gpio_event *ip;
- struct input_dev *input_dev;
- struct gpio_event_platform_data *event_info;
-
- event_info = pdev->dev.platform_data;
- if (event_info == NULL) {
- pr_err("gpio_event_probe: No pdata\n");
- return -ENODEV;
- }
- if (event_info->name == NULL ||
- event_info->info == NULL ||
- event_info->info_count == 0) {
- pr_err("gpio_event_probe: Incomplete pdata\n");
- return -ENODEV;
- }
- ip = kzalloc(sizeof(*ip) +
- sizeof(ip->state[0]) * event_info->info_count, GFP_KERNEL);
- if (ip == NULL) {
- err = -ENOMEM;
- pr_err("gpio_event_probe: Failed to allocate private data\n");
- goto err_kp_alloc_failed;
- }
- platform_set_drvdata(pdev, ip);
-
- input_dev = input_allocate_device();
- if (input_dev == NULL) {
- err = -ENOMEM;
- pr_err("gpio_event_probe: Failed to allocate input device\n");
- goto err_input_dev_alloc_failed;
- }
- input_set_drvdata(input_dev, ip);
- ip->input_dev = input_dev;
- ip->info = event_info;
- if (event_info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ip->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
- ip->early_suspend.suspend = gpio_event_suspend;
- ip->early_suspend.resume = gpio_event_resume;
- register_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 1);
- }
-
- input_dev->name = ip->info->name;
- input_dev->event = gpio_input_event;
-
- err = gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_INIT);
- if (err)
- goto err_call_all_func_failed;
-
- err = input_register_device(input_dev);
- if (err) {
- pr_err("gpio_event_probe: Unable to register %s input device\n",
- input_dev->name);
- goto err_input_register_device_failed;
- }
-
- return 0;
-
-err_input_register_device_failed:
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
-err_call_all_func_failed:
- if (event_info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 0);
- }
- input_free_device(input_dev);
-err_input_dev_alloc_failed:
- kfree(ip);
-err_kp_alloc_failed:
- return err;
-}
-
-static int gpio_event_remove(struct platform_device *pdev)
-{
- struct gpio_event *ip = platform_get_drvdata(pdev);
-
- gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
- if (ip->info->power) {
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ip->early_suspend);
-#endif
- ip->info->power(ip->info, 0);
- }
- input_unregister_device(ip->input_dev);
- kfree(ip);
- return 0;
-}
-
-static struct platform_driver gpio_event_driver = {
- .probe = gpio_event_probe,
- .remove = gpio_event_remove,
- .driver = {
- .name = GPIO_EVENT_DEV_NAME,
- },
-};
-
-static int __devinit gpio_event_init(void)
-{
- return platform_driver_register(&gpio_event_driver);
-}
-
-static void __exit gpio_event_exit(void)
-{
- platform_driver_unregister(&gpio_event_driver);
-}
-
-module_init(gpio_event_init);
-module_exit(gpio_event_exit);
-
-MODULE_DESCRIPTION("GPIO Event Driver");
-MODULE_LICENSE("GPL");
-
+++ /dev/null
-/* drivers/input/misc/gpio_input.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/gpio_event.h>
-#include <linux/hrtimer.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-
-enum {
- DEBOUNCE_UNSTABLE = BIT(0), /* Got irq, while debouncing */
- DEBOUNCE_PRESSED = BIT(1),
- DEBOUNCE_NOTPRESSED = BIT(2),
- DEBOUNCE_WAIT_IRQ = BIT(3), /* Stable irq state */
- DEBOUNCE_POLL = BIT(4), /* Stable polling state */
-
- DEBOUNCE_UNKNOWN =
- DEBOUNCE_PRESSED | DEBOUNCE_NOTPRESSED,
-};
-
-struct gpio_key_state {
- struct gpio_input_state *ds;
- uint8_t debounce;
-};
-
-struct gpio_input_state {
- struct input_dev *input_dev;
- const struct gpio_event_input_info *info;
- struct hrtimer timer;
- int use_irq;
- int debounce_count;
- spinlock_t irq_lock;
- struct gpio_key_state key_state[0];
-};
-
-static enum hrtimer_restart gpio_event_input_timer_func(struct hrtimer *timer)
-{
- int i;
- int pressed;
- struct gpio_input_state *ds =
- container_of(timer, struct gpio_input_state, timer);
- unsigned gpio_flags = ds->info->flags;
- unsigned npolarity;
- int nkeys = ds->info->keymap_size;
- const struct gpio_event_direct_entry *key_entry;
- struct gpio_key_state *key_state;
- unsigned long irqflags;
- uint8_t debounce;
-
-#if 0
- key_entry = kp->keys_info->keymap;
- key_state = kp->key_state;
- for (i = 0; i < nkeys; i++, key_entry++, key_state++)
- pr_info("gpio_read_detect_status %d %d\n", key_entry->gpio,
- gpio_read_detect_status(key_entry->gpio));
-#endif
- key_entry = ds->info->keymap;
- key_state = ds->key_state;
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- for (i = 0; i < nkeys; i++, key_entry++, key_state++) {
- debounce = key_state->debounce;
- if (debounce & DEBOUNCE_WAIT_IRQ)
- continue;
- if (key_state->debounce & DEBOUNCE_UNSTABLE) {
- debounce = key_state->debounce = DEBOUNCE_UNKNOWN;
- enable_irq(gpio_to_irq(key_entry->gpio));
- pr_info("gpio_keys_scan_keys: key %x-%x, %d "
- "(%d) continue debounce\n",
- ds->info->type, key_entry->code,
- i, key_entry->gpio);
- }
- npolarity = !(gpio_flags & GPIOEDF_ACTIVE_HIGH);
- pressed = gpio_get_value(key_entry->gpio) ^ npolarity;
- if (debounce & DEBOUNCE_POLL) {
- if (pressed == !(debounce & DEBOUNCE_PRESSED)) {
- ds->debounce_count++;
- key_state->debounce = DEBOUNCE_UNKNOWN;
- if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
- pr_info("gpio_keys_scan_keys: key %x-"
- "%x, %d (%d) start debounce\n",
- ds->info->type, key_entry->code,
- i, key_entry->gpio);
- }
- continue;
- }
- if (pressed && (debounce & DEBOUNCE_NOTPRESSED)) {
- if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
- pr_info("gpio_keys_scan_keys: key %x-%x, %d "
- "(%d) debounce pressed 1\n",
- ds->info->type, key_entry->code,
- i, key_entry->gpio);
- key_state->debounce = DEBOUNCE_PRESSED;
- continue;
- }
- if (!pressed && (debounce & DEBOUNCE_PRESSED)) {
- if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
- pr_info("gpio_keys_scan_keys: key %x-%x, %d "
- "(%d) debounce pressed 0\n",
- ds->info->type, key_entry->code,
- i, key_entry->gpio);
- key_state->debounce = DEBOUNCE_NOTPRESSED;
- continue;
- }
- /* key is stable */
- ds->debounce_count--;
- if (ds->use_irq)
- key_state->debounce |= DEBOUNCE_WAIT_IRQ;
- else
- key_state->debounce |= DEBOUNCE_POLL;
- if (gpio_flags & GPIOEDF_PRINT_KEYS)
- pr_info("gpio_keys_scan_keys: key %x-%x, %d (%d) "
- "changed to %d\n", ds->info->type,
- key_entry->code, i, key_entry->gpio, pressed);
- input_event(ds->input_dev, ds->info->type,
- key_entry->code, pressed);
- }
-
-#if 0
- key_entry = kp->keys_info->keymap;
- key_state = kp->key_state;
- for (i = 0; i < nkeys; i++, key_entry++, key_state++) {
- pr_info("gpio_read_detect_status %d %d\n", key_entry->gpio,
- gpio_read_detect_status(key_entry->gpio));
- }
-#endif
-
- if (ds->debounce_count)
- hrtimer_start(timer, ds->info->debounce_time, HRTIMER_MODE_REL);
- else if (!ds->use_irq)
- hrtimer_start(timer, ds->info->poll_time, HRTIMER_MODE_REL);
-
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
-
- return HRTIMER_NORESTART;
-}
-
-static irqreturn_t gpio_event_input_irq_handler(int irq, void *dev_id)
-{
- struct gpio_key_state *ks = dev_id;
- struct gpio_input_state *ds = ks->ds;
- int keymap_index = ks - ds->key_state;
- const struct gpio_event_direct_entry *key_entry;
- unsigned long irqflags;
- int pressed;
-
- if (!ds->use_irq)
- return IRQ_HANDLED;
-
- key_entry = &ds->info->keymap[keymap_index];
-
- if (ds->info->debounce_time.tv64) {
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- if (ks->debounce & DEBOUNCE_WAIT_IRQ) {
- ks->debounce = DEBOUNCE_UNKNOWN;
- if (ds->debounce_count++ == 0) {
- hrtimer_start(
- &ds->timer, ds->info->debounce_time,
- HRTIMER_MODE_REL);
- }
- if (ds->info->flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
- pr_info("gpio_event_input_irq_handler: "
- "key %x-%x, %d (%d) start debounce\n",
- ds->info->type, key_entry->code,
- keymap_index, key_entry->gpio);
- } else {
- disable_irq(irq);
- ks->debounce = DEBOUNCE_UNSTABLE;
- }
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
- } else {
- pressed = gpio_get_value(key_entry->gpio) ^
- !(ds->info->flags & GPIOEDF_ACTIVE_HIGH);
- if (ds->info->flags & GPIOEDF_PRINT_KEYS)
- pr_info("gpio_event_input_irq_handler: key %x-%x, %d "
- "(%d) changed to %d\n",
- ds->info->type, key_entry->code, keymap_index,
- key_entry->gpio, pressed);
- input_event(ds->input_dev, ds->info->type,
- key_entry->code, pressed);
- }
- return IRQ_HANDLED;
-}
-
-static int gpio_event_input_request_irqs(struct gpio_input_state *ds)
-{
- int i;
- int err;
- unsigned int irq;
- unsigned long req_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
-
- for (i = 0; i < ds->info->keymap_size; i++) {
- err = irq = gpio_to_irq(ds->info->keymap[i].gpio);
- if (err < 0)
- goto err_gpio_get_irq_num_failed;
- err = request_irq(irq, gpio_event_input_irq_handler,
- req_flags, "gpio_keys", &ds->key_state[i]);
- if (err) {
- pr_err("gpio_event_input_request_irqs: request_irq "
- "failed for input %d, irq %d\n",
- ds->info->keymap[i].gpio, irq);
- goto err_request_irq_failed;
- }
- enable_irq_wake(irq);
- }
- return 0;
-
- for (i = ds->info->keymap_size - 1; i >= 0; i--) {
- free_irq(gpio_to_irq(ds->info->keymap[i].gpio),
- &ds->key_state[i]);
-err_request_irq_failed:
-err_gpio_get_irq_num_failed:
- ;
- }
- return err;
-}
-
-int gpio_event_input_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func)
-{
- int ret;
- int i;
- unsigned long irqflags;
- struct gpio_event_input_info *di;
- struct gpio_input_state *ds = *data;
-
- di = container_of(info, struct gpio_event_input_info, info);
-
- if (func == GPIO_EVENT_FUNC_SUSPEND) {
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- if (ds->use_irq)
- for (i = 0; i < di->keymap_size; i++)
- disable_irq(gpio_to_irq(di->keymap[i].gpio));
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
- hrtimer_cancel(&ds->timer);
- return 0;
- }
- if (func == GPIO_EVENT_FUNC_RESUME) {
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- if (ds->use_irq)
- for (i = 0; i < di->keymap_size; i++)
- enable_irq(gpio_to_irq(di->keymap[i].gpio));
- hrtimer_start(&ds->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
- return 0;
- }
-
- if (func == GPIO_EVENT_FUNC_INIT) {
- if (ktime_to_ns(di->poll_time) <= 0)
- di->poll_time = ktime_set(0, 20 * NSEC_PER_MSEC);
-
- *data = ds = kzalloc(sizeof(*ds) + sizeof(ds->key_state[0]) *
- di->keymap_size, GFP_KERNEL);
- if (ds == NULL) {
- ret = -ENOMEM;
- pr_err("gpio_event_input_func: "
- "Failed to allocate private data\n");
- goto err_ds_alloc_failed;
- }
- ds->debounce_count = di->keymap_size;
- ds->input_dev = input_dev;
- ds->info = di;
- spin_lock_init(&ds->irq_lock);
-
- for (i = 0; i < di->keymap_size; i++) {
- input_set_capability(input_dev, di->type,
- di->keymap[i].code);
- ds->key_state[i].ds = ds;
- ds->key_state[i].debounce = DEBOUNCE_UNKNOWN;
- }
-
- for (i = 0; i < di->keymap_size; i++) {
- ret = gpio_request(di->keymap[i].gpio, "gpio_kp_in");
- if (ret) {
- pr_err("gpio_event_input_func: gpio_request "
- "failed for %d\n", di->keymap[i].gpio);
- goto err_gpio_request_failed;
- }
- ret = gpio_direction_input(di->keymap[i].gpio);
- if (ret) {
- pr_err("gpio_event_input_func: "
- "gpio_direction_input failed for %d\n",
- di->keymap[i].gpio);
- goto err_gpio_configure_failed;
- }
- }
-
- ret = gpio_event_input_request_irqs(ds);
-
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- ds->use_irq = ret == 0;
-
- pr_info("GPIO Input Driver: Start gpio inputs for %s in %s "
- "mode\n",
- input_dev->name, ret == 0 ? "interrupt" : "polling");
-
- hrtimer_init(&ds->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- ds->timer.function = gpio_event_input_timer_func;
- hrtimer_start(&ds->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
- return 0;
- }
-
- ret = 0;
- spin_lock_irqsave(&ds->irq_lock, irqflags);
- hrtimer_cancel(&ds->timer);
- if (ds->use_irq) {
- for (i = di->keymap_size - 1; i >= 0; i--) {
- free_irq(gpio_to_irq(di->keymap[i].gpio),
- &ds->key_state[i]);
- }
- }
- spin_unlock_irqrestore(&ds->irq_lock, irqflags);
-
- for (i = di->keymap_size - 1; i >= 0; i--) {
-err_gpio_configure_failed:
- gpio_free(di->keymap[i].gpio);
-err_gpio_request_failed:
- ;
- }
- kfree(ds);
-err_ds_alloc_failed:
- return ret;
-}
+++ /dev/null
-/* drivers/input/misc/gpio_matrix.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/gpio_event.h>
-#include <linux/hrtimer.h>
-#include <linux/interrupt.h>
-
-struct gpio_kp {
- struct input_dev *input_dev;
- struct gpio_event_matrix_info *keypad_info;
- struct hrtimer timer;
- int current_output;
- unsigned int use_irq:1;
- unsigned int key_state_changed:1;
- unsigned int last_key_state_changed:1;
- unsigned int some_keys_pressed:2;
- unsigned long keys_pressed[0];
-};
-
-static void clear_phantom_key(struct gpio_kp *kp, int out, int in)
-{
- struct gpio_event_matrix_info *mi = kp->keypad_info;
- int key_index = out * mi->ninputs + in;
- unsigned short keycode = mi->keymap[key_index];;
-
- if (!test_bit(keycode, kp->input_dev->key)) {
- if (mi->flags & GPIOKPF_PRINT_PHANTOM_KEYS)
- pr_info("gpiomatrix: phantom key %x, %d-%d (%d-%d) "
- "cleared\n", keycode, out, in,
- mi->output_gpios[out], mi->input_gpios[in]);
- __clear_bit(key_index, kp->keys_pressed);
- } else {
- if (mi->flags & GPIOKPF_PRINT_PHANTOM_KEYS)
- pr_info("gpiomatrix: phantom key %x, %d-%d (%d-%d) "
- "not cleared\n", keycode, out, in,
- mi->output_gpios[out], mi->input_gpios[in]);
- }
-}
-
-static int restore_keys_for_input(struct gpio_kp *kp, int out, int in)
-{
- int rv = 0;
- int key_index;
-
- key_index = out * kp->keypad_info->ninputs + in;
- while (out < kp->keypad_info->noutputs) {
- if (test_bit(key_index, kp->keys_pressed)) {
- rv = 1;
- clear_phantom_key(kp, out, in);
- }
- key_index += kp->keypad_info->ninputs;
- out++;
- }
- return rv;
-}
-
-static void remove_phantom_keys(struct gpio_kp *kp)
-{
- int out, in, inp;
- int key_index;
-
- if (kp->some_keys_pressed < 3)
- return;
-
- for (out = 0; out < kp->keypad_info->noutputs; out++) {
- inp = -1;
- key_index = out * kp->keypad_info->ninputs;
- for (in = 0; in < kp->keypad_info->ninputs; in++, key_index++) {
- if (test_bit(key_index, kp->keys_pressed)) {
- if (inp == -1) {
- inp = in;
- continue;
- }
- if (inp >= 0) {
- if (!restore_keys_for_input(kp, out + 1,
- inp))
- break;
- clear_phantom_key(kp, out, inp);
- inp = -2;
- }
- restore_keys_for_input(kp, out, in);
- }
- }
- }
-}
-
-static void report_key(struct gpio_kp *kp, int key_index, int out, int in)
-{
- struct gpio_event_matrix_info *mi = kp->keypad_info;
- int pressed = test_bit(key_index, kp->keys_pressed);
- unsigned short keycode = mi->keymap[key_index];
- if (pressed != test_bit(keycode, kp->input_dev->key)) {
- if (keycode == KEY_RESERVED) {
- if (mi->flags & GPIOKPF_PRINT_UNMAPPED_KEYS)
- pr_info("gpiomatrix: unmapped key, %d-%d "
- "(%d-%d) changed to %d\n",
- out, in, mi->output_gpios[out],
- mi->input_gpios[in], pressed);
- } else {
- if (mi->flags & GPIOKPF_PRINT_MAPPED_KEYS)
- pr_info("gpiomatrix: key %x, %d-%d (%d-%d) "
- "changed to %d\n", keycode,
- out, in, mi->output_gpios[out],
- mi->input_gpios[in], pressed);
- input_report_key(kp->input_dev, keycode, pressed);
- }
- }
-}
-
-static enum hrtimer_restart gpio_keypad_timer_func(struct hrtimer *timer)
-{
- int out, in;
- int key_index;
- int gpio;
- struct gpio_kp *kp = container_of(timer, struct gpio_kp, timer);
- struct gpio_event_matrix_info *mi = kp->keypad_info;
- unsigned gpio_keypad_flags = mi->flags;
- unsigned polarity = !!(gpio_keypad_flags & GPIOKPF_ACTIVE_HIGH);
-
- out = kp->current_output;
- if (out == mi->noutputs) {
- out = 0;
- kp->last_key_state_changed = kp->key_state_changed;
- kp->key_state_changed = 0;
- kp->some_keys_pressed = 0;
- } else {
- key_index = out * mi->ninputs;
- for (in = 0; in < mi->ninputs; in++, key_index++) {
- gpio = mi->input_gpios[in];
- if (gpio_get_value(gpio) ^ !polarity) {
- if (kp->some_keys_pressed < 3)
- kp->some_keys_pressed++;
- kp->key_state_changed |= !__test_and_set_bit(
- key_index, kp->keys_pressed);
- } else
- kp->key_state_changed |= __test_and_clear_bit(
- key_index, kp->keys_pressed);
- }
- gpio = mi->output_gpios[out];
- if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
- gpio_set_value(gpio, !polarity);
- else
- gpio_direction_input(gpio);
- out++;
- }
- kp->current_output = out;
- if (out < mi->noutputs) {
- gpio = mi->output_gpios[out];
- if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
- gpio_set_value(gpio, polarity);
- else
- gpio_direction_output(gpio, polarity);
- hrtimer_start(timer, mi->settle_time, HRTIMER_MODE_REL);
- return HRTIMER_NORESTART;
- }
- if (gpio_keypad_flags & GPIOKPF_DEBOUNCE) {
- if (kp->key_state_changed) {
- hrtimer_start(&kp->timer, mi->debounce_delay,
- HRTIMER_MODE_REL);
- return HRTIMER_NORESTART;
- }
- kp->key_state_changed = kp->last_key_state_changed;
- }
- if (kp->key_state_changed) {
- if (gpio_keypad_flags & GPIOKPF_REMOVE_SOME_PHANTOM_KEYS)
- remove_phantom_keys(kp);
- key_index = 0;
- for (out = 0; out < mi->noutputs; out++)
- for (in = 0; in < mi->ninputs; in++, key_index++)
- report_key(kp, key_index, out, in);
- }
- if (!kp->use_irq || kp->some_keys_pressed) {
- hrtimer_start(timer, mi->poll_time, HRTIMER_MODE_REL);
- return HRTIMER_NORESTART;
- }
-
- /* No keys are pressed, reenable interrupt */
- for (out = 0; out < mi->noutputs; out++) {
- if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
- gpio_set_value(mi->output_gpios[out], polarity);
- else
- gpio_direction_output(mi->output_gpios[out], polarity);
- }
- for (in = 0; in < mi->ninputs; in++)
- enable_irq(gpio_to_irq(mi->input_gpios[in]));
- return HRTIMER_NORESTART;
-}
-
-static irqreturn_t gpio_keypad_irq_handler(int irq_in, void *dev_id)
-{
- int i;
- struct gpio_kp *kp = dev_id;
- struct gpio_event_matrix_info *mi = kp->keypad_info;
- unsigned gpio_keypad_flags = mi->flags;
-
- if (!kp->use_irq) /* ignore interrupt while registering the handler */
- return IRQ_HANDLED;
-
- for (i = 0; i < mi->ninputs; i++)
- disable_irq(gpio_to_irq(mi->input_gpios[i]));
- for (i = 0; i < mi->noutputs; i++) {
- if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
- gpio_set_value(mi->output_gpios[i],
- !(gpio_keypad_flags & GPIOKPF_ACTIVE_HIGH));
- else
- gpio_direction_input(mi->output_gpios[i]);
- }
- hrtimer_start(&kp->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
- return IRQ_HANDLED;
-}
-
-static int gpio_keypad_request_irqs(struct gpio_kp *kp)
-{
- int i;
- int err;
- unsigned int irq;
- unsigned long request_flags;
- struct gpio_event_matrix_info *mi = kp->keypad_info;
-
- switch (mi->flags & (GPIOKPF_ACTIVE_HIGH|GPIOKPF_LEVEL_TRIGGERED_IRQ)) {
- default:
- request_flags = IRQF_TRIGGER_FALLING;
- break;
- case GPIOKPF_ACTIVE_HIGH:
- request_flags = IRQF_TRIGGER_RISING;
- break;
- case GPIOKPF_LEVEL_TRIGGERED_IRQ:
- request_flags = IRQF_TRIGGER_LOW;
- break;
- case GPIOKPF_LEVEL_TRIGGERED_IRQ | GPIOKPF_ACTIVE_HIGH:
- request_flags = IRQF_TRIGGER_HIGH;
- break;
- }
-
- for (i = 0; i < mi->ninputs; i++) {
- err = irq = gpio_to_irq(mi->input_gpios[i]);
- if (err < 0)
- goto err_gpio_get_irq_num_failed;
- err = request_irq(irq, gpio_keypad_irq_handler, request_flags,
- "gpio_kp", kp);
- if (err) {
- pr_err("gpiomatrix: request_irq failed for input %d, "
- "irq %d\n", mi->input_gpios[i], irq);
- goto err_request_irq_failed;
- }
- err = set_irq_wake(irq, 1);
- if (err) {
- pr_err("gpiomatrix: set_irq_wake failed for input %d, "
- "irq %d\n", mi->input_gpios[i], irq);
- }
- disable_irq(irq);
- }
- return 0;
-
- for (i = mi->noutputs - 1; i >= 0; i--) {
- free_irq(gpio_to_irq(mi->input_gpios[i]), kp);
-err_request_irq_failed:
-err_gpio_get_irq_num_failed:
- ;
- }
- return err;
-}
-
-int gpio_event_matrix_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func)
-{
- int i;
- int err;
- int key_count;
- struct gpio_kp *kp;
- struct gpio_event_matrix_info *mi;
-
- mi = container_of(info, struct gpio_event_matrix_info, info);
- if (func == GPIO_EVENT_FUNC_SUSPEND || func == GPIO_EVENT_FUNC_RESUME) {
- /* TODO: disable scanning */
- return 0;
- }
-
- if (func == GPIO_EVENT_FUNC_INIT) {
- if (mi->keymap == NULL ||
- mi->input_gpios == NULL ||
- mi->output_gpios == NULL) {
- err = -ENODEV;
- pr_err("gpiomatrix: Incomplete pdata\n");
- goto err_invalid_platform_data;
- }
- key_count = mi->ninputs * mi->noutputs;
-
- *data = kp = kzalloc(sizeof(*kp) + sizeof(kp->keys_pressed[0]) *
- BITS_TO_LONGS(key_count), GFP_KERNEL);
- if (kp == NULL) {
- err = -ENOMEM;
- pr_err("gpiomatrix: Failed to allocate private data\n");
- goto err_kp_alloc_failed;
- }
- kp->input_dev = input_dev;
- kp->keypad_info = mi;
- set_bit(EV_KEY, input_dev->evbit);
- for (i = 0; i < key_count; i++) {
- if (mi->keymap[i])
- set_bit(mi->keymap[i] & KEY_MAX,
- input_dev->keybit);
- }
-
- for (i = 0; i < mi->noutputs; i++) {
- if (gpio_cansleep(mi->output_gpios[i])) {
- pr_err("gpiomatrix: unsupported output gpio %d,"
- " can sleep\n", mi->output_gpios[i]);
- err = -EINVAL;
- goto err_request_output_gpio_failed;
- }
- err = gpio_request(mi->output_gpios[i], "gpio_kp_out");
- if (err) {
- pr_err("gpiomatrix: gpio_request failed for "
- "output %d\n", mi->output_gpios[i]);
- goto err_request_output_gpio_failed;
- }
- if (mi->flags & GPIOKPF_DRIVE_INACTIVE)
- err = gpio_direction_output(mi->output_gpios[i],
- !(mi->flags & GPIOKPF_ACTIVE_HIGH));
- else
- err = gpio_direction_input(mi->output_gpios[i]);
- if (err) {
- pr_err("gpiomatrix: gpio_configure failed for "
- "output %d\n", mi->output_gpios[i]);
- goto err_output_gpio_configure_failed;
- }
- }
- for (i = 0; i < mi->ninputs; i++) {
- err = gpio_request(mi->input_gpios[i], "gpio_kp_in");
- if (err) {
- pr_err("gpiomatrix: gpio_request failed for "
- "input %d\n", mi->input_gpios[i]);
- goto err_request_input_gpio_failed;
- }
- err = gpio_direction_input(mi->input_gpios[i]);
- if (err) {
- pr_err("gpiomatrix: gpio_direction_input failed"
- " for input %d\n", mi->input_gpios[i]);
- goto err_gpio_direction_input_failed;
- }
- }
- kp->current_output = mi->noutputs;
- kp->key_state_changed = 1;
-
- hrtimer_init(&kp->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- kp->timer.function = gpio_keypad_timer_func;
- err = gpio_keypad_request_irqs(kp);
- kp->use_irq = err == 0;
-
- pr_info("GPIO Matrix Keypad Driver: Start keypad matrix for %s "
- "in %s mode\n", input_dev->name,
- kp->use_irq ? "interrupt" : "polling");
-
- hrtimer_start(&kp->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
-
- return 0;
- }
-
- err = 0;
- kp = *data;
-
- if (kp->use_irq)
- for (i = mi->noutputs - 1; i >= 0; i--)
- free_irq(gpio_to_irq(mi->input_gpios[i]), kp);
-
- hrtimer_cancel(&kp->timer);
- for (i = mi->noutputs - 1; i >= 0; i--) {
-err_gpio_direction_input_failed:
- gpio_free(mi->input_gpios[i]);
-err_request_input_gpio_failed:
- ;
- }
- for (i = mi->noutputs - 1; i >= 0; i--) {
-err_output_gpio_configure_failed:
- gpio_free(mi->output_gpios[i]);
-err_request_output_gpio_failed:
- ;
- }
- kfree(kp);
-err_kp_alloc_failed:
-err_invalid_platform_data:
- return err;
-}
+++ /dev/null
-/* drivers/input/misc/gpio_output.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/gpio_event.h>
-
-int gpio_event_output_event(
- struct input_dev *input_dev, struct gpio_event_info *info, void **data,
- unsigned int type, unsigned int code, int value)
-{
- int i;
- struct gpio_event_output_info *oi;
- oi = container_of(info, struct gpio_event_output_info, info);
- if (type != oi->type)
- return 0;
- if (!(oi->flags & GPIOEDF_ACTIVE_HIGH))
- value = !value;
- for (i = 0; i < oi->keymap_size; i++)
- if (code == oi->keymap[i].code)
- gpio_set_value(oi->keymap[i].gpio, value);
- return 0;
-}
-
-int gpio_event_output_func(
- struct input_dev *input_dev, struct gpio_event_info *info, void **data,
- int func)
-{
- int ret;
- int i;
- struct gpio_event_output_info *oi;
- oi = container_of(info, struct gpio_event_output_info, info);
-
- if (func == GPIO_EVENT_FUNC_SUSPEND || func == GPIO_EVENT_FUNC_RESUME)
- return 0;
-
- if (func == GPIO_EVENT_FUNC_INIT) {
- int output_level = !(oi->flags & GPIOEDF_ACTIVE_HIGH);
- for (i = 0; i < oi->keymap_size; i++)
- input_set_capability(input_dev, oi->type,
- oi->keymap[i].code);
-
- for (i = 0; i < oi->keymap_size; i++) {
- ret = gpio_request(oi->keymap[i].gpio,
- "gpio_event_output");
- if (ret) {
- pr_err("gpio_event_output_func: gpio_request "
- "failed for %d\n", oi->keymap[i].gpio);
- goto err_gpio_request_failed;
- }
- ret = gpio_direction_output(oi->keymap[i].gpio,
- output_level);
- if (ret) {
- pr_err("gpio_event_output_func: "
- "gpio_direction_output failed for %d\n",
- oi->keymap[i].gpio);
- goto err_gpio_direction_output_failed;
- }
- }
- return 0;
- }
-
- ret = 0;
- for (i = oi->keymap_size - 1; i >= 0; i--) {
-err_gpio_direction_output_failed:
- gpio_free(oi->keymap[i].gpio);
-err_gpio_request_failed:
- ;
- }
- return ret;
-}
-
+++ /dev/null
-/* drivers/staging/dream/include/linux/android_pmem.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ANDROID_PMEM_H_
-#define _ANDROID_PMEM_H_
-
-#define PMEM_IOCTL_MAGIC 'p'
-#define PMEM_GET_PHYS _IOW(PMEM_IOCTL_MAGIC, 1, unsigned int)
-#define PMEM_MAP _IOW(PMEM_IOCTL_MAGIC, 2, unsigned int)
-#define PMEM_GET_SIZE _IOW(PMEM_IOCTL_MAGIC, 3, unsigned int)
-#define PMEM_UNMAP _IOW(PMEM_IOCTL_MAGIC, 4, unsigned int)
-/* This ioctl will allocate pmem space, backing the file, it will fail
- * if the file already has an allocation, pass it the len as the argument
- * to the ioctl */
-#define PMEM_ALLOCATE _IOW(PMEM_IOCTL_MAGIC, 5, unsigned int)
-/* This will connect a one pmem file to another, pass the file that is already
- * backed in memory as the argument to the ioctl
- */
-#define PMEM_CONNECT _IOW(PMEM_IOCTL_MAGIC, 6, unsigned int)
-/* Returns the total size of the pmem region it is sent to as a pmem_region
- * struct (with offset set to 0).
- */
-#define PMEM_GET_TOTAL_SIZE _IOW(PMEM_IOCTL_MAGIC, 7, unsigned int)
-/* Revokes gpu registers and resets the gpu. Pass a pointer to the
- * start of the mapped gpu regs (the vaddr returned by mmap) as the argument.
- */
-#define HW3D_REVOKE_GPU _IOW(PMEM_IOCTL_MAGIC, 8, unsigned int)
-#define HW3D_GRANT_GPU _IOW(PMEM_IOCTL_MAGIC, 9, unsigned int)
-#define HW3D_WAIT_FOR_INTERRUPT _IOW(PMEM_IOCTL_MAGIC, 10, unsigned int)
-
-int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart,
- unsigned long *end, struct file **filp);
-int get_pmem_user_addr(struct file *file, unsigned long *start,
- unsigned long *end);
-void put_pmem_file(struct file* file);
-void flush_pmem_file(struct file *file, unsigned long start, unsigned long len);
-
-struct android_pmem_platform_data
-{
- const char* name;
- /* starting physical address of memory region */
- unsigned long start;
- /* size of memory region */
- unsigned long size;
- /* set to indicate the region should not be managed with an allocator */
- unsigned no_allocator;
- /* set to indicate maps of this region should be cached, if a mix of
- * cached and uncached is desired, set this and open the device with
- * O_SYNC to get an uncached region */
- unsigned cached;
- /* The MSM7k has bits to enable a write buffer in the bus controller*/
- unsigned buffered;
-};
-
-struct pmem_region {
- unsigned long offset;
- unsigned long len;
-};
-
-int pmem_setup(struct android_pmem_platform_data *pdata,
- long (*ioctl)(struct file *, unsigned int, unsigned long),
- int (*release)(struct inode *, struct file *));
-
-int pmem_remap(struct pmem_region *region, struct file *file,
- unsigned operation);
-
-#endif //_ANDROID_PPP_H_
-
+++ /dev/null
-/* drivers/staging/dream/include/linux/gpio_event.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _LINUX_GPIO_EVENT_H
-#define _LINUX_GPIO_EVENT_H
-
-#include <linux/input.h>
-
-enum {
- GPIO_EVENT_FUNC_UNINIT = 0x0,
- GPIO_EVENT_FUNC_INIT = 0x1,
- GPIO_EVENT_FUNC_SUSPEND = 0x2,
- GPIO_EVENT_FUNC_RESUME = 0x3,
-};
-struct gpio_event_info {
- int (*func)(struct input_dev *input_dev,
- struct gpio_event_info *info,
- void **data, int func);
- int (*event)(struct input_dev *input_dev,
- struct gpio_event_info *info,
- void **data, unsigned int type,
- unsigned int code, int value); /* out events */
-};
-
-struct gpio_event_platform_data {
- const char *name;
- struct gpio_event_info **info;
- size_t info_count;
- int (*power)(const struct gpio_event_platform_data *pdata, bool on);
-};
-
-#define GPIO_EVENT_DEV_NAME "gpio-event"
-
-/* Key matrix */
-
-enum gpio_event_matrix_flags {
- /* unset: drive active output low, set: drive active output high */
- GPIOKPF_ACTIVE_HIGH = 1U << 0,
- GPIOKPF_DEBOUNCE = 1U << 1,
- GPIOKPF_REMOVE_SOME_PHANTOM_KEYS = 1U << 2,
- GPIOKPF_REMOVE_PHANTOM_KEYS = GPIOKPF_REMOVE_SOME_PHANTOM_KEYS |
- GPIOKPF_DEBOUNCE,
- GPIOKPF_DRIVE_INACTIVE = 1U << 3,
- GPIOKPF_LEVEL_TRIGGERED_IRQ = 1U << 4,
- GPIOKPF_PRINT_UNMAPPED_KEYS = 1U << 16,
- GPIOKPF_PRINT_MAPPED_KEYS = 1U << 17,
- GPIOKPF_PRINT_PHANTOM_KEYS = 1U << 18,
-};
-
-extern int gpio_event_matrix_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func);
-struct gpio_event_matrix_info {
- /* initialize to gpio_event_matrix_func */
- struct gpio_event_info info;
- /* size must be ninputs * noutputs */
- const unsigned short *keymap;
- unsigned int *input_gpios;
- unsigned int *output_gpios;
- unsigned int ninputs;
- unsigned int noutputs;
- /* time to wait before reading inputs after driving each output */
- ktime_t settle_time;
- /* time to wait before scanning the keypad a second time */
- ktime_t debounce_delay;
- ktime_t poll_time;
- unsigned flags;
-};
-
-/* Directly connected inputs and outputs */
-
-enum gpio_event_direct_flags {
- GPIOEDF_ACTIVE_HIGH = 1U << 0,
-/* GPIOEDF_USE_DOWN_IRQ = 1U << 1, */
-/* GPIOEDF_USE_IRQ = (1U << 2) | GPIOIDF_USE_DOWN_IRQ, */
- GPIOEDF_PRINT_KEYS = 1U << 8,
- GPIOEDF_PRINT_KEY_DEBOUNCE = 1U << 9,
-};
-
-struct gpio_event_direct_entry {
- uint32_t gpio:23;
- uint32_t code:9;
-};
-
-/* inputs */
-extern int gpio_event_input_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func);
-struct gpio_event_input_info {
- /* initialize to gpio_event_input_func */
- struct gpio_event_info info;
- ktime_t debounce_time;
- ktime_t poll_time;
- uint16_t flags;
- uint16_t type;
- const struct gpio_event_direct_entry *keymap;
- size_t keymap_size;
-};
-
-/* outputs */
-extern int gpio_event_output_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func);
-extern int gpio_event_output_event(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data,
- unsigned int type, unsigned int code, int value);
-struct gpio_event_output_info {
- /* initialize to gpio_event_output_func and gpio_event_output_event */
- struct gpio_event_info info;
- uint16_t flags;
- uint16_t type;
- const struct gpio_event_direct_entry *keymap;
- size_t keymap_size;
-};
-
-
-/* axes */
-
-enum gpio_event_axis_flags {
- GPIOEAF_PRINT_UNKNOWN_DIRECTION = 1U << 16,
- GPIOEAF_PRINT_RAW = 1U << 17,
- GPIOEAF_PRINT_EVENT = 1U << 18,
-};
-
-extern int gpio_event_axis_func(struct input_dev *input_dev,
- struct gpio_event_info *info, void **data, int func);
-struct gpio_event_axis_info {
- /* initialize to gpio_event_axis_func */
- struct gpio_event_info info;
- uint8_t count;
- uint8_t type; /* EV_REL or EV_ABS */
- uint16_t code;
- uint16_t decoded_size;
- uint16_t (*map)(struct gpio_event_axis_info *info, uint16_t in);
- uint32_t *gpio;
- uint32_t flags;
-};
-#define gpio_axis_2bit_gray_map gpio_axis_4bit_gray_map
-#define gpio_axis_3bit_gray_map gpio_axis_4bit_gray_map
-uint16_t gpio_axis_4bit_gray_map(
- struct gpio_event_axis_info *info, uint16_t in);
-uint16_t gpio_axis_5bit_singletrack_map(
- struct gpio_event_axis_info *info, uint16_t in);
-
-#endif
+++ /dev/null
-/* drivers/staging/dream/include/linux/msm_adsp.h
- *
- * Copyright (c) QUALCOMM Incorporated
- * Copyright (C) 2007 Google, Inc.
- * Author: Iliyan Malchev <ibm@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __LINUX_MSM_ADSP_H
-#define __LINUX_MSM_ADSP_H
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-#define ADSP_IOCTL_MAGIC 'q'
-
-/* ADSP_IOCTL_WRITE_COMMAND */
-struct adsp_command_t {
- uint16_t queue;
- uint32_t len; /* bytes */
- uint8_t *data;
-};
-
-/* ADSP_IOCTL_GET_EVENT */
-struct adsp_event_t {
- uint16_t type; /* 1 == event (RPC), 0 == message (adsp) */
- uint32_t timeout_ms; /* -1 for infinite, 0 for immediate return */
- uint16_t msg_id;
- uint16_t flags; /* 1 == 16--bit event, 0 == 32-bit event */
- uint32_t len; /* size in, number of bytes out */
- uint8_t *data;
-};
-
-#define ADSP_IOCTL_ENABLE \
- _IOR(ADSP_IOCTL_MAGIC, 1, unsigned)
-
-#define ADSP_IOCTL_DISABLE \
- _IOR(ADSP_IOCTL_MAGIC, 2, unsigned)
-
-#define ADSP_IOCTL_DISABLE_ACK \
- _IOR(ADSP_IOCTL_MAGIC, 3, unsigned)
-
-#define ADSP_IOCTL_WRITE_COMMAND \
- _IOR(ADSP_IOCTL_MAGIC, 4, struct adsp_command_t *)
-
-#define ADSP_IOCTL_GET_EVENT \
- _IOWR(ADSP_IOCTL_MAGIC, 5, struct adsp_event_data_t *)
-
-#define ADSP_IOCTL_SET_CLKRATE \
- _IOR(ADSP_IOCTL_MAGIC, 6, unsigned)
-
-#define ADSP_IOCTL_DISABLE_EVENT_RSP \
- _IOR(ADSP_IOCTL_MAGIC, 10, unsigned)
-
-struct adsp_pmem_info {
- int fd;
- void *vaddr;
-};
-
-#define ADSP_IOCTL_REGISTER_PMEM \
- _IOW(ADSP_IOCTL_MAGIC, 13, unsigned)
-
-#define ADSP_IOCTL_UNREGISTER_PMEM \
- _IOW(ADSP_IOCTL_MAGIC, 14, unsigned)
-
-/* Cause any further GET_EVENT ioctls to fail (-ENODEV)
- * until the device is closed and reopened. Useful for
- * terminating event dispatch threads
- */
-#define ADSP_IOCTL_ABORT_EVENT_READ \
- _IOW(ADSP_IOCTL_MAGIC, 15, unsigned)
-
-#define ADSP_IOCTL_LINK_TASK \
- _IOW(ADSP_IOCTL_MAGIC, 16, unsigned)
-
-#endif
+++ /dev/null
-/* drivers/staging/dream/include/linux/msm_audio.h
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __LINUX_MSM_AUDIO_H
-#define __LINUX_MSM_AUDIO_H
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#include <asm/sizes.h>
-
-/* PCM Audio */
-
-#define AUDIO_IOCTL_MAGIC 'a'
-
-#define AUDIO_START _IOW(AUDIO_IOCTL_MAGIC, 0, unsigned)
-#define AUDIO_STOP _IOW(AUDIO_IOCTL_MAGIC, 1, unsigned)
-#define AUDIO_FLUSH _IOW(AUDIO_IOCTL_MAGIC, 2, unsigned)
-#define AUDIO_GET_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 3, unsigned)
-#define AUDIO_SET_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 4, unsigned)
-#define AUDIO_GET_STATS _IOR(AUDIO_IOCTL_MAGIC, 5, unsigned)
-#define AUDIO_ENABLE_AUDPP _IOW(AUDIO_IOCTL_MAGIC, 6, unsigned)
-#define AUDIO_SET_ADRC _IOW(AUDIO_IOCTL_MAGIC, 7, unsigned)
-#define AUDIO_SET_EQ _IOW(AUDIO_IOCTL_MAGIC, 8, unsigned)
-#define AUDIO_SET_RX_IIR _IOW(AUDIO_IOCTL_MAGIC, 9, unsigned)
-#define AUDIO_SET_VOLUME _IOW(AUDIO_IOCTL_MAGIC, 10, unsigned)
-#define AUDIO_ENABLE_AUDPRE _IOW(AUDIO_IOCTL_MAGIC, 11, unsigned)
-#define AUDIO_SET_AGC _IOW(AUDIO_IOCTL_MAGIC, 12, unsigned)
-#define AUDIO_SET_NS _IOW(AUDIO_IOCTL_MAGIC, 13, unsigned)
-#define AUDIO_SET_TX_IIR _IOW(AUDIO_IOCTL_MAGIC, 14, unsigned)
-#define AUDIO_PAUSE _IOW(AUDIO_IOCTL_MAGIC, 15, unsigned)
-#define AUDIO_GET_PCM_CONFIG _IOR(AUDIO_IOCTL_MAGIC, 30, unsigned)
-#define AUDIO_SET_PCM_CONFIG _IOW(AUDIO_IOCTL_MAGIC, 31, unsigned)
-#define AUDIO_SWITCH_DEVICE _IOW(AUDIO_IOCTL_MAGIC, 32, unsigned)
-
-#define AUDIO_MAX_COMMON_IOCTL_NUM 100
-
-#define AUDIO_MAX_COMMON_IOCTL_NUM 100
-
-struct msm_audio_config {
- uint32_t buffer_size;
- uint32_t buffer_count;
- uint32_t channel_count;
- uint32_t sample_rate;
- uint32_t type;
- uint32_t unused[3];
-};
-
-struct msm_audio_stats {
- uint32_t byte_count;
- uint32_t sample_count;
- uint32_t unused[2];
-};
-
-/* Audio routing */
-
-#define SND_IOCTL_MAGIC 's'
-
-#define SND_MUTE_UNMUTED 0
-#define SND_MUTE_MUTED 1
-
-struct msm_snd_device_config {
- uint32_t device;
- uint32_t ear_mute;
- uint32_t mic_mute;
-};
-
-#define SND_SET_DEVICE _IOW(SND_IOCTL_MAGIC, 2, struct msm_device_config *)
-
-#define SND_METHOD_VOICE 0
-
-struct msm_snd_volume_config {
- uint32_t device;
- uint32_t method;
- uint32_t volume;
-};
-
-#define SND_SET_VOLUME _IOW(SND_IOCTL_MAGIC, 3, struct msm_snd_volume_config *)
-
-/* Returns the number of SND endpoints supported. */
-
-#define SND_GET_NUM_ENDPOINTS _IOR(SND_IOCTL_MAGIC, 4, unsigned *)
-
-struct msm_snd_endpoint {
- int id; /* input and output */
- char name[64]; /* output only */
-};
-
-/* Takes an index between 0 and one less than the number returned by
- * SND_GET_NUM_ENDPOINTS, and returns the SND index and name of a
- * SND endpoint. On input, the .id field contains the number of the
- * endpoint, and on exit it contains the SND index, while .name contains
- * the description of the endpoint.
- */
-
-#define SND_GET_ENDPOINT _IOWR(SND_IOCTL_MAGIC, 5, struct msm_snd_endpoint *)
-
-struct msm_audio_pcm_config {
- uint32_t pcm_feedback; /* 0 - disable > 0 - enable */
- uint32_t buffer_count; /* Number of buffers to allocate */
- uint32_t buffer_size; /* Size of buffer for capturing of
- PCM samples */
-};
-#endif
+++ /dev/null
-/* drivers/staging/dream/include/linux/msm_rpcrouter.h
- *
- * Copyright (c) QUALCOMM Incorporated
- * Copyright (C) 2007 Google, Inc.
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __LINUX_MSM_RPCROUTER_H
-#define __LINUX_MSM_RPCROUTER_H
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-#define RPC_ROUTER_VERSION_V1 0x00010000
-
-struct rpcrouter_ioctl_server_args {
- uint32_t prog;
- uint32_t vers;
-};
-
-#define RPC_ROUTER_IOCTL_MAGIC (0xC1)
-
-#define RPC_ROUTER_IOCTL_GET_VERSION \
- _IOR(RPC_ROUTER_IOCTL_MAGIC, 0, unsigned int)
-
-#define RPC_ROUTER_IOCTL_GET_MTU \
- _IOR(RPC_ROUTER_IOCTL_MAGIC, 1, unsigned int)
-
-#define RPC_ROUTER_IOCTL_REGISTER_SERVER \
- _IOWR(RPC_ROUTER_IOCTL_MAGIC, 2, unsigned int)
-
-#define RPC_ROUTER_IOCTL_UNREGISTER_SERVER \
- _IOWR(RPC_ROUTER_IOCTL_MAGIC, 3, unsigned int)
-
-#define RPC_ROUTER_IOCTL_GET_MINOR_VERSION \
- _IOW(RPC_ROUTER_IOCTL_MAGIC, 4, unsigned int)
-
-#endif
+++ /dev/null
-/* drivers/staging/dream/include/linux/wakelock.h
- *
- * Copyright (C) 2007-2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _LINUX_WAKELOCK_H
-#define _LINUX_WAKELOCK_H
-
-#include <linux/list.h>
-#include <linux/ktime.h>
-
-/* A wake_lock prevents the system from entering suspend or other low power
- * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock
- * prevents a full system suspend. If the type is WAKE_LOCK_IDLE, low power
- * states that cause large interrupt latencies or that disable a set of
- * interrupts will not entered from idle until the wake_locks are released.
- */
-
-enum {
- WAKE_LOCK_SUSPEND, /* Prevent suspend */
- WAKE_LOCK_IDLE, /* Prevent low power idle */
- WAKE_LOCK_TYPE_COUNT
-};
-
-struct wake_lock {
-#ifdef CONFIG_HAS_WAKELOCK
- struct list_head link;
- int flags;
- const char *name;
- unsigned long expires;
-#ifdef CONFIG_WAKELOCK_STAT
- struct {
- int count;
- int expire_count;
- int wakeup_count;
- ktime_t total_time;
- ktime_t prevent_suspend_time;
- ktime_t max_time;
- ktime_t last_time;
- } stat;
-#endif
-#endif
-};
-
-#ifdef CONFIG_HAS_WAKELOCK
-
-void wake_lock_init(struct wake_lock *lock, int type, const char *name);
-void wake_lock_destroy(struct wake_lock *lock);
-void wake_lock(struct wake_lock *lock);
-void wake_lock_timeout(struct wake_lock *lock, long timeout);
-void wake_unlock(struct wake_lock *lock);
-
-/* wake_lock_active returns a non-zero value if the wake_lock is currently
- * locked. If the wake_lock has a timeout, it does not check the timeout
- * but if the timeout had aready been checked it will return 0.
- */
-int wake_lock_active(struct wake_lock *lock);
-
-/* has_wake_lock returns 0 if no wake locks of the specified type are active,
- * and non-zero if one or more wake locks are held. Specifically it returns
- * -1 if one or more wake locks with no timeout are active or the
- * number of jiffies until all active wake locks time out.
- */
-long has_wake_lock(int type);
-
-#else
-
-static inline void wake_lock_init(struct wake_lock *lock, int type,
- const char *name) {}
-static inline void wake_lock_destroy(struct wake_lock *lock) {}
-static inline void wake_lock(struct wake_lock *lock) {}
-static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) {}
-static inline void wake_unlock(struct wake_lock *lock) {}
-
-static inline int wake_lock_active(struct wake_lock *lock) { return 0; }
-static inline long has_wake_lock(int type) { return 0; }
-
-#endif
-
-#endif
-
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-
-#ifndef __ASM__ARCH_CAMERA_H
-#define __ASM__ARCH_CAMERA_H
-
-#include <linux/list.h>
-#include <linux/poll.h>
-#include <linux/cdev.h>
-#include <linux/platform_device.h>
-#include "linux/types.h"
-
-#include <mach/board.h>
-#include <media/msm_camera.h>
-
-#ifdef CONFIG_MSM_CAMERA_DEBUG
-#define CDBG(fmt, args...) printk(KERN_INFO "msm_camera: " fmt, ##args)
-#else
-#define CDBG(fmt, args...) do { } while (0)
-#endif
-
-#define MSM_CAMERA_MSG 0
-#define MSM_CAMERA_EVT 1
-#define NUM_WB_EXP_NEUTRAL_REGION_LINES 4
-#define NUM_WB_EXP_STAT_OUTPUT_BUFFERS 3
-#define NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS 16
-#define NUM_AF_STAT_OUTPUT_BUFFERS 3
-
-enum msm_queue {
- MSM_CAM_Q_CTRL, /* control command or control command status */
- MSM_CAM_Q_VFE_EVT, /* adsp event */
- MSM_CAM_Q_VFE_MSG, /* adsp message */
- MSM_CAM_Q_V4L2_REQ, /* v4l2 request */
-};
-
-enum vfe_resp_msg {
- VFE_EVENT,
- VFE_MSG_GENERAL,
- VFE_MSG_SNAPSHOT,
- VFE_MSG_OUTPUT1,
- VFE_MSG_OUTPUT2,
- VFE_MSG_STATS_AF,
- VFE_MSG_STATS_WE,
-};
-
-struct msm_vfe_phy_info {
- uint32_t sbuf_phy;
- uint32_t y_phy;
- uint32_t cbcr_phy;
-};
-
-struct msm_vfe_resp {
- enum vfe_resp_msg type;
- struct msm_vfe_evt_msg evt_msg;
- struct msm_vfe_phy_info phy;
- void *extdata;
- int32_t extlen;
-};
-
-struct msm_vfe_callback {
- void (*vfe_resp)(struct msm_vfe_resp *,
- enum msm_queue, void *syncdata);
- void* (*vfe_alloc)(int, void *syncdata);
-};
-
-struct msm_camvfe_fn {
- int (*vfe_init)(struct msm_vfe_callback *, struct platform_device *);
- int (*vfe_enable)(struct camera_enable_cmd *);
- int (*vfe_config)(struct msm_vfe_cfg_cmd *, void *);
- int (*vfe_disable)(struct camera_enable_cmd *,
- struct platform_device *dev);
- void (*vfe_release)(struct platform_device *);
-};
-
-struct msm_sensor_ctrl {
- int (*s_init)(const struct msm_camera_sensor_info *);
- int (*s_release)(void);
- int (*s_config)(void __user *);
-};
-
-struct msm_sync {
- /* These two queues are accessed from a process context only. */
- struct hlist_head frame; /* most-frequently accessed */
- struct hlist_head stats;
-
- /* The message queue is used by the control thread to send commands
- * to the config thread, and also by the DSP to send messages to the
- * config thread. Thus it is the only queue that is accessed from
- * both interrupt and process context.
- */
- spinlock_t msg_event_q_lock;
- struct list_head msg_event_q;
- wait_queue_head_t msg_event_wait;
-
- /* This queue contains preview frames. It is accessed by the DSP (in
- * in interrupt context, and by the frame thread.
- */
- spinlock_t prev_frame_q_lock;
- struct list_head prev_frame_q;
- wait_queue_head_t prev_frame_wait;
- int unblock_poll_frame;
-
- /* This queue contains snapshot frames. It is accessed by the DSP (in
- * interrupt context, and by the control thread.
- */
- spinlock_t pict_frame_q_lock;
- struct list_head pict_frame_q;
- wait_queue_head_t pict_frame_wait;
-
- struct msm_camera_sensor_info *sdata;
- struct msm_camvfe_fn vfefn;
- struct msm_sensor_ctrl sctrl;
- struct platform_device *pdev;
- uint8_t opencnt;
- void *cropinfo;
- int croplen;
- unsigned pict_pp;
-
- const char *apps_id;
-
- struct mutex lock;
- struct list_head list;
-};
-
-#define MSM_APPS_ID_V4L2 "msm_v4l2"
-#define MSM_APPS_ID_PROP "msm_qct"
-
-struct msm_device {
- struct msm_sync *sync; /* most-frequently accessed */
- struct device *device;
- struct cdev cdev;
- /* opened is meaningful only for the config and frame nodes,
- * which may be opened only once.
- */
- atomic_t opened;
-};
-
-struct msm_control_device_queue {
- spinlock_t ctrl_status_q_lock;
- struct list_head ctrl_status_q;
- wait_queue_head_t ctrl_status_wait;
-};
-
-struct msm_control_device {
- struct msm_device *pmsm;
-
- /* This queue used by the config thread to send responses back to the
- * control thread. It is accessed only from a process context.
- */
- struct msm_control_device_queue ctrl_q;
-};
-
-/* this structure is used in kernel */
-struct msm_queue_cmd {
- struct list_head list;
- enum msm_queue type;
- void *command;
-};
-
-struct register_address_value_pair {
- uint16_t register_address;
- uint16_t register_value;
-};
-
-struct msm_pmem_region {
- struct hlist_node list;
- int type;
- void *vaddr;
- unsigned long paddr;
- unsigned long len;
- struct file *file;
- uint32_t y_off;
- uint32_t cbcr_off;
- int fd;
- uint8_t active;
-};
-
-struct axidata {
- uint32_t bufnum1;
- uint32_t bufnum2;
- struct msm_pmem_region *region;
-};
-
-#ifdef CONFIG_MSM_CAMERA_FLASH
-int msm_camera_flash_set_led_state(unsigned led_state);
-#else
-static inline int msm_camera_flash_set_led_state(unsigned led_state)
-{
- return -ENOTSUPP;
-}
-#endif
-
-/* Below functions are added for V4L2 kernel APIs */
-struct msm_v4l2_driver {
- struct msm_sync *sync;
- int (*open)(struct msm_sync *, const char *apps_id);
- int (*release)(struct msm_sync *);
- int (*ctrl)(struct msm_sync *, struct msm_ctrl_cmd *);
- int (*reg_pmem)(struct msm_sync *, struct msm_pmem_info *);
- int (*get_frame) (struct msm_sync *, struct msm_frame *);
- int (*put_frame) (struct msm_sync *, struct msm_frame *);
- int (*get_pict) (struct msm_sync *, struct msm_ctrl_cmd *);
- unsigned int (*drv_poll) (struct msm_sync *, struct file *,
- struct poll_table_struct *);
-};
-
-int msm_v4l2_register(struct msm_v4l2_driver *);
-int msm_v4l2_unregister(struct msm_v4l2_driver *);
-
-void msm_camvfe_init(void);
-int msm_camvfe_check(void *);
-void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *);
-int msm_camera_drv_start(struct platform_device *dev,
- int (*sensor_probe)(const struct msm_camera_sensor_info *,
- struct msm_sensor_ctrl *));
-
-enum msm_camio_clk_type {
- CAMIO_VFE_MDC_CLK,
- CAMIO_MDC_CLK,
- CAMIO_VFE_CLK,
- CAMIO_VFE_AXI_CLK,
-
- CAMIO_MAX_CLK
-};
-
-enum msm_camio_clk_src_type {
- MSM_CAMIO_CLK_SRC_INTERNAL,
- MSM_CAMIO_CLK_SRC_EXTERNAL,
- MSM_CAMIO_CLK_SRC_MAX
-};
-
-enum msm_s_test_mode {
- S_TEST_OFF,
- S_TEST_1,
- S_TEST_2,
- S_TEST_3
-};
-
-enum msm_s_resolution {
- S_QTR_SIZE,
- S_FULL_SIZE,
- S_INVALID_SIZE
-};
-
-enum msm_s_reg_update {
- /* Sensor egisters that need to be updated during initialization */
- S_REG_INIT,
- /* Sensor egisters that needs periodic I2C writes */
- S_UPDATE_PERIODIC,
- /* All the sensor Registers will be updated */
- S_UPDATE_ALL,
- /* Not valid update */
- S_UPDATE_INVALID
-};
-
-enum msm_s_setting {
- S_RES_PREVIEW,
- S_RES_CAPTURE
-};
-
-int msm_camio_enable(struct platform_device *dev);
-
-int msm_camio_clk_enable(enum msm_camio_clk_type clk);
-int msm_camio_clk_disable(enum msm_camio_clk_type clk);
-int msm_camio_clk_config(uint32_t freq);
-void msm_camio_clk_rate_set(int rate);
-void msm_camio_clk_axi_rate_set(int rate);
-
-void msm_camio_camif_pad_reg_reset(void);
-void msm_camio_camif_pad_reg_reset_2(void);
-
-void msm_camio_vfe_blk_reset(void);
-
-void msm_camio_clk_sel(enum msm_camio_clk_src_type);
-void msm_camio_disable(struct platform_device *);
-int msm_camio_probe_on(struct platform_device *);
-int msm_camio_probe_off(struct platform_device *);
-#endif
+++ /dev/null
-/* include/asm-arm/arch-msm/msm_adsp.h
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM__ARCH_MSM_ADSP_H
-#define __ASM__ARCH_MSM_ADSP_H
-
-struct msm_adsp_module;
-
-struct msm_adsp_ops {
- /* event is called from interrupt context when a message
- * arrives from the DSP. Use the provided function pointer
- * to copy the message into a local buffer. Do NOT call
- * it multiple times.
- */
- void (*event)(void *driver_data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len));
-};
-
-/* Get, Put, Enable, and Disable are synchronous and must only
- * be called from thread context. Enable and Disable will block
- * up to one second in the event of a fatal DSP error but are
- * much faster otherwise.
- */
-int msm_adsp_get(const char *name, struct msm_adsp_module **module,
- struct msm_adsp_ops *ops, void *driver_data);
-void msm_adsp_put(struct msm_adsp_module *module);
-int msm_adsp_enable(struct msm_adsp_module *module);
-int msm_adsp_disable(struct msm_adsp_module *module);
-int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate);
-
-/* Write is safe to call from interrupt context.
- */
-int msm_adsp_write(struct msm_adsp_module *module,
- unsigned queue_id,
- void *data, size_t len);
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-/* Command Queue Indexes */
-#define QDSP_lpmCommandQueue 0
-#define QDSP_mpuAfeQueue 1
-#define QDSP_mpuGraphicsCmdQueue 2
-#define QDSP_mpuModmathCmdQueue 3
-#define QDSP_mpuVDecCmdQueue 4
-#define QDSP_mpuVDecPktQueue 5
-#define QDSP_mpuVEncCmdQueue 6
-#define QDSP_rxMpuDecCmdQueue 7
-#define QDSP_rxMpuDecPktQueue 8
-#define QDSP_txMpuEncQueue 9
-#define QDSP_uPAudPPCmd1Queue 10
-#define QDSP_uPAudPPCmd2Queue 11
-#define QDSP_uPAudPPCmd3Queue 12
-#define QDSP_uPAudPlay0BitStreamCtrlQueue 13
-#define QDSP_uPAudPlay1BitStreamCtrlQueue 14
-#define QDSP_uPAudPlay2BitStreamCtrlQueue 15
-#define QDSP_uPAudPlay3BitStreamCtrlQueue 16
-#define QDSP_uPAudPlay4BitStreamCtrlQueue 17
-#define QDSP_uPAudPreProcCmdQueue 18
-#define QDSP_uPAudRecBitStreamQueue 19
-#define QDSP_uPAudRecCmdQueue 20
-#define QDSP_uPDiagQueue 21
-#define QDSP_uPJpegActionCmdQueue 22
-#define QDSP_uPJpegCfgCmdQueue 23
-#define QDSP_uPVocProcQueue 24
-#define QDSP_vfeCommandQueue 25
-#define QDSP_vfeCommandScaleQueue 26
-#define QDSP_vfeCommandTableQueue 27
-#define QDSP_MAX_NUM_QUEUES 28
-#else
-/* Command Queue Indexes */
-#define QDSP_lpmCommandQueue 0
-#define QDSP_mpuAfeQueue 1
-#define QDSP_mpuGraphicsCmdQueue 2
-#define QDSP_mpuModmathCmdQueue 3
-#define QDSP_mpuVDecCmdQueue 4
-#define QDSP_mpuVDecPktQueue 5
-#define QDSP_mpuVEncCmdQueue 6
-#define QDSP_rxMpuDecCmdQueue 7
-#define QDSP_rxMpuDecPktQueue 8
-#define QDSP_txMpuEncQueue 9
-#define QDSP_uPAudPPCmd1Queue 10
-#define QDSP_uPAudPPCmd2Queue 11
-#define QDSP_uPAudPPCmd3Queue 12
-#define QDSP_uPAudPlay0BitStreamCtrlQueue 13
-#define QDSP_uPAudPlay1BitStreamCtrlQueue 14
-#define QDSP_uPAudPlay2BitStreamCtrlQueue 15
-#define QDSP_uPAudPlay3BitStreamCtrlQueue 16
-#define QDSP_uPAudPlay4BitStreamCtrlQueue 17
-#define QDSP_uPAudPreProcCmdQueue 18
-#define QDSP_uPAudRecBitStreamQueue 19
-#define QDSP_uPAudRecCmdQueue 20
-#define QDSP_uPJpegActionCmdQueue 21
-#define QDSP_uPJpegCfgCmdQueue 22
-#define QDSP_uPVocProcQueue 23
-#define QDSP_vfeCommandQueue 24
-#define QDSP_vfeCommandScaleQueue 25
-#define QDSP_vfeCommandTableQueue 26
-#define QDSP_QUEUE_MAX 26
-#endif
-
-#endif
+++ /dev/null
-/** include/asm-arm/arch-msm/msm_rpcrouter.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2009 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM__ARCH_MSM_RPCROUTER_H
-#define __ASM__ARCH_MSM_RPCROUTER_H
-
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/platform_device.h>
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-/* RPC API version structure
- * Version bit 31 : 1->hashkey versioning,
- * 0->major-minor (backward compatible) versioning
- * hashkey versioning:
- * Version bits 31-0 hashkey
- * major-minor (backward compatible) versioning
- * Version bits 30-28 reserved (no match)
- * Version bits 27-16 major (must match)
- * Version bits 15-0 minor (greater or equal)
- */
-#define RPC_VERSION_MODE_MASK 0x80000000
-#define RPC_VERSION_MAJOR_MASK 0x0fff0000
-#define RPC_VERSION_MAJOR_OFFSET 16
-#define RPC_VERSION_MINOR_MASK 0x0000ffff
-
-#define MSM_RPC_VERS(major, minor) \
- ((uint32_t)((((major) << RPC_VERSION_MAJOR_OFFSET) & \
- RPC_VERSION_MAJOR_MASK) | \
- ((minor) & RPC_VERSION_MINOR_MASK)))
-#define MSM_RPC_GET_MAJOR(vers) (((vers) & RPC_VERSION_MAJOR_MASK) >> \
- RPC_VERSION_MAJOR_OFFSET)
-#define MSM_RPC_GET_MINOR(vers) ((vers) & RPC_VERSION_MINOR_MASK)
-#else
-#define MSM_RPC_VERS(major, minor) (major)
-#define MSM_RPC_GET_MAJOR(vers) (vers)
-#define MSM_RPC_GET_MINOR(vers) 0
-#endif
-
-struct msm_rpc_endpoint;
-
-struct rpcsvr_platform_device
-{
- struct platform_device base;
- uint32_t prog;
- uint32_t vers;
-};
-
-#define RPC_DATA_IN 0
-/*
- * Structures for sending / receiving direct RPC requests
- * XXX: Any cred/verif lengths > 0 not supported
- */
-
-struct rpc_request_hdr
-{
- uint32_t xid;
- uint32_t type; /* 0 */
- uint32_t rpc_vers; /* 2 */
- uint32_t prog;
- uint32_t vers;
- uint32_t procedure;
- uint32_t cred_flavor;
- uint32_t cred_length;
- uint32_t verf_flavor;
- uint32_t verf_length;
-};
-
-typedef struct
-{
- uint32_t low;
- uint32_t high;
-} rpc_reply_progmismatch_data;
-
-typedef struct
-{
-} rpc_denied_reply_hdr;
-
-typedef struct
-{
- uint32_t verf_flavor;
- uint32_t verf_length;
- uint32_t accept_stat;
-#define RPC_ACCEPTSTAT_SUCCESS 0
-#define RPC_ACCEPTSTAT_PROG_UNAVAIL 1
-#define RPC_ACCEPTSTAT_PROG_MISMATCH 2
-#define RPC_ACCEPTSTAT_PROC_UNAVAIL 3
-#define RPC_ACCEPTSTAT_GARBAGE_ARGS 4
-#define RPC_ACCEPTSTAT_SYSTEM_ERR 5
-#define RPC_ACCEPTSTAT_PROG_LOCKED 6
- /*
- * Following data is dependant on accept_stat
- * If ACCEPTSTAT == PROG_MISMATCH then there is a
- * 'rpc_reply_progmismatch_data' structure following the header.
- * Otherwise the data is procedure specific
- */
-} rpc_accepted_reply_hdr;
-
-struct rpc_reply_hdr
-{
- uint32_t xid;
- uint32_t type;
- uint32_t reply_stat;
-#define RPCMSG_REPLYSTAT_ACCEPTED 0
-#define RPCMSG_REPLYSTAT_DENIED 1
- union {
- rpc_accepted_reply_hdr acc_hdr;
- rpc_denied_reply_hdr dny_hdr;
- } data;
-};
-
-/* flags for msm_rpc_connect() */
-#define MSM_RPC_UNINTERRUPTIBLE 0x0001
-
-/* use IS_ERR() to check for failure */
-struct msm_rpc_endpoint *msm_rpc_open(void);
-/* Connect with the specified server version */
-struct msm_rpc_endpoint *msm_rpc_connect(uint32_t prog, uint32_t vers, unsigned flags);
-uint32_t msm_rpc_get_vers(struct msm_rpc_endpoint *ept);
-/* check if server version can handle client requested version */
-int msm_rpc_is_compatible_version(uint32_t server_version,
- uint32_t client_version);
-
-int msm_rpc_close(struct msm_rpc_endpoint *ept);
-int msm_rpc_write(struct msm_rpc_endpoint *ept,
- void *data, int len);
-int msm_rpc_read(struct msm_rpc_endpoint *ept,
- void **data, unsigned len, long timeout);
-void msm_rpc_setup_req(struct rpc_request_hdr *hdr,
- uint32_t prog, uint32_t vers, uint32_t proc);
-int msm_rpc_register_server(struct msm_rpc_endpoint *ept,
- uint32_t prog, uint32_t vers);
-int msm_rpc_unregister_server(struct msm_rpc_endpoint *ept,
- uint32_t prog, uint32_t vers);
-
-/* simple blocking rpc call
- *
- * request is mandatory and must have a rpc_request_hdr
- * at the start. The header will be filled out for you.
- *
- * reply provides a buffer for replies of reply_max_size
- */
-int msm_rpc_call_reply(struct msm_rpc_endpoint *ept, uint32_t proc,
- void *request, int request_size,
- void *reply, int reply_max_size,
- long timeout);
-int msm_rpc_call(struct msm_rpc_endpoint *ept, uint32_t proc,
- void *request, int request_size,
- long timeout);
-
-struct msm_rpc_server
-{
- struct list_head list;
- uint32_t flags;
-
- uint32_t prog;
- uint32_t vers;
-
- int (*rpc_call)(struct msm_rpc_server *server,
- struct rpc_request_hdr *req, unsigned len);
-};
-
-int msm_rpc_create_server(struct msm_rpc_server *server);
-
-#endif
+++ /dev/null
-/* linux/include/asm-arm/arch-msm/msm_smd.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_MSM_SMD_H
-#define __ASM_ARCH_MSM_SMD_H
-
-typedef struct smd_channel smd_channel_t;
-
-/* warning: notify() may be called before open returns */
-int smd_open(const char *name, smd_channel_t **ch, void *priv,
- void (*notify)(void *priv, unsigned event));
-
-#define SMD_EVENT_DATA 1
-#define SMD_EVENT_OPEN 2
-#define SMD_EVENT_CLOSE 3
-
-int smd_close(smd_channel_t *ch);
-
-/* passing a null pointer for data reads and discards */
-int smd_read(smd_channel_t *ch, void *data, int len);
-
-/* Write to stream channels may do a partial write and return
-** the length actually written.
-** Write to packet channels will never do a partial write --
-** it will return the requested length written or an error.
-*/
-int smd_write(smd_channel_t *ch, const void *data, int len);
-
-int smd_write_avail(smd_channel_t *ch);
-int smd_read_avail(smd_channel_t *ch);
-
-/* Returns the total size of the current packet being read.
-** Returns 0 if no packets available or a stream channel.
-*/
-int smd_cur_packet_size(smd_channel_t *ch);
-
-/* used for tty unthrottling and the like -- causes the notify()
-** callback to be called from the same lock context as is used
-** when it is called from channel updates
-*/
-void smd_kick(smd_channel_t *ch);
-
-
-#if 0
-/* these are interruptable waits which will block you until the specified
-** number of bytes are readable or writable.
-*/
-int smd_wait_until_readable(smd_channel_t *ch, int bytes);
-int smd_wait_until_writable(smd_channel_t *ch, int bytes);
-#endif
-
-typedef enum
-{
- SMD_PORT_DS = 0,
- SMD_PORT_DIAG,
- SMD_PORT_RPC_CALL,
- SMD_PORT_RPC_REPLY,
- SMD_PORT_BT,
- SMD_PORT_CONTROL,
- SMD_PORT_MEMCPY_SPARE1,
- SMD_PORT_DATA1,
- SMD_PORT_DATA2,
- SMD_PORT_DATA3,
- SMD_PORT_DATA4,
- SMD_PORT_DATA5,
- SMD_PORT_DATA6,
- SMD_PORT_DATA7,
- SMD_PORT_DATA8,
- SMD_PORT_DATA9,
- SMD_PORT_DATA10,
- SMD_PORT_DATA11,
- SMD_PORT_DATA12,
- SMD_PORT_DATA13,
- SMD_PORT_DATA14,
- SMD_PORT_DATA15,
- SMD_PORT_DATA16,
- SMD_PORT_DATA17,
- SMD_PORT_DATA18,
- SMD_PORT_DATA19,
- SMD_PORT_DATA20,
- SMD_PORT_GPS_NMEA,
- SMD_PORT_BRIDGE_1,
- SMD_PORT_BRIDGE_2,
- SMD_PORT_BRIDGE_3,
- SMD_PORT_BRIDGE_4,
- SMD_PORT_BRIDGE_5,
- SMD_PORT_LOOPBACK,
- SMD_PORT_CS_APPS_MODEM,
- SMD_PORT_CS_APPS_DSP,
- SMD_PORT_CS_MODEM_DSP,
- SMD_NUM_PORTS,
-} smd_port_id_type;
-
-#endif
+++ /dev/null
-#ifndef QDSP5AUDPLAYCMDI_H
-#define QDSP5AUDPLAYCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- Q D S P 5 A U D I O P L A Y T A S K C O M M A N D S
-
-GENERAL DESCRIPTION
- Command Interface for AUDPLAYTASK on QDSP5
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
-
- audplay_cmd_dec_data_avail
- Send buffer to AUDPLAY task
-
-
-Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audplaycmdi.h#2 $
-
-===========================================================================*/
-
-#define AUDPLAY_CMD_BITSTREAM_DATA_AVAIL 0x0000
-#define AUDPLAY_CMD_BITSTREAM_DATA_AVAIL_LEN \
- sizeof(audplay_cmd_bitstream_data_avail)
-
-/* Type specification of dec_data_avail message sent to AUDPLAYTASK
-*/
-typedef struct {
- /*command ID*/
- unsigned int cmd_id;
-
- /* Decoder ID for which message is being sent */
- unsigned int decoder_id;
-
- /* Start address of data in ARM global memory */
- unsigned int buf_ptr;
-
- /* Number of 16-bit words of bit-stream data contiguously available at the
- * above-mentioned address. */
- unsigned int buf_size;
-
- /* Partition number used by audPlayTask to communicate with DSP's RTOS
- * kernel */
- unsigned int partition_number;
-} __attribute__((packed)) audplay_cmd_bitstream_data_avail;
-
-#define AUDPLAY_CMD_HPCM_BUF_CFG 0x0003
-#define AUDPLAY_CMD_HPCM_BUF_CFG_LEN \
- sizeof(struct audplay_cmd_hpcm_buf_cfg)
-
-struct audplay_cmd_hpcm_buf_cfg {
- unsigned int cmd_id;
- unsigned int hostpcm_config;
- unsigned int feedback_frequency;
- unsigned int byte_swap;
- unsigned int max_buffers;
- unsigned int partition_number;
-} __attribute__((packed));
-
-#define AUDPLAY_CMD_BUFFER_REFRESH 0x0004
-#define AUDPLAY_CMD_BUFFER_REFRESH_LEN \
- sizeof(struct audplay_cmd_buffer_update)
-
-struct audplay_cmd_buffer_refresh {
- unsigned int cmd_id;
- unsigned int num_buffers;
- unsigned int buf_read_count;
- unsigned int buf0_address;
- unsigned int buf0_length;
- unsigned int buf1_address;
- unsigned int buf1_length;
-} __attribute__((packed));
-#endif /* QDSP5AUDPLAYCMD_H */
+++ /dev/null
-#ifndef QDSP5AUDPLAYMSG_H
-#define QDSP5AUDPLAYMSG_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- Q D S P 5 A U D I O P L A Y T A S K M S G
-
-GENERAL DESCRIPTION
- Message sent by AUDPLAY task
-
-REFERENCES
- None
-
-
-Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audplaymsg.h#3 $
-
-===========================================================================*/
-#define AUDPLAY_MSG_DEC_NEEDS_DATA 0x0001
-#define AUDPLAY_MSG_DEC_NEEDS_DATA_MSG_LEN \
- sizeof(audplay_msg_dec_needs_data)
-
-typedef struct{
- /* reserved*/
- unsigned int dec_id;
-
- /* The read pointer offset of external memory until which the
- * bitstream has been DMAed in. */
- unsigned int adecDataReadPtrOffset;
-
- /* The buffer size of external memory. */
- unsigned int adecDataBufSize;
-
- unsigned int bitstream_free_len;
- unsigned int bitstream_write_ptr;
- unsigned int bitstarem_buf_start;
- unsigned int bitstream_buf_len;
-} __attribute__((packed)) audplay_msg_dec_needs_data;
-
-#define AUDPLAY_MSG_BUFFER_UPDATE 0x0004
-#define AUDPLAY_MSG_BUFFER_UPDATE_LEN \
- sizeof(struct audplay_msg_buffer_update)
-
-struct audplay_msg_buffer_update {
- unsigned int buffer_write_count;
- unsigned int num_of_buffer;
- unsigned int buf0_address;
- unsigned int buf0_length;
- unsigned int buf1_address;
- unsigned int buf1_length;
-} __attribute__((packed));
-#endif /* QDSP5AUDPLAYMSG_H */
+++ /dev/null
-#ifndef QDSP5AUDPPCMDI_H
-#define QDSP5AUDPPCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- A U D I O P O S T P R O C E S S I N G I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by AUDPP Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audppcmdi.h#2 $
-
-===========================================================================*/
-
-/*
- * ARM to AUDPPTASK Commands
- *
- * ARM uses three command queues to communicate with AUDPPTASK
- * 1)uPAudPPCmd1Queue : Used for more frequent and shorter length commands
- * Location : MEMA
- * Buffer Size : 6 words
- * No of buffers in a queue : 20 for gaming audio and 5 for other images
- * 2)uPAudPPCmd2Queue : Used for commands which are not much lengthier
- * Location : MEMA
- * Buffer Size : 23
- * No of buffers in a queue : 2
- * 3)uPAudOOCmd3Queue : Used for lengthier and more frequent commands
- * Location : MEMA
- * Buffer Size : 145
- * No of buffers in a queue : 3
- */
-
-/*
- * Commands Related to uPAudPPCmd1Queue
- */
-
-/*
- * Command Structure to enable or disable the active decoders
- */
-
-#define AUDPP_CMD_CFG_DEC_TYPE 0x0001
-#define AUDPP_CMD_CFG_DEC_TYPE_LEN sizeof(audpp_cmd_cfg_dec_type)
-
-/* Enable the decoder */
-#define AUDPP_CMD_DEC_TYPE_M 0x000F
-
-#define AUDPP_CMD_ENA_DEC_V 0x4000
-#define AUDPP_CMD_DIS_DEC_V 0x0000
-#define AUDPP_CMD_DEC_STATE_M 0x4000
-
-#define AUDPP_CMD_UPDATDE_CFG_DEC 0x8000
-#define AUDPP_CMD_DONT_UPDATE_CFG_DEC 0x0000
-
-
-/* Type specification of cmd_cfg_dec */
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short dec0_cfg;
- unsigned short dec1_cfg;
- unsigned short dec2_cfg;
- unsigned short dec3_cfg;
- unsigned short dec4_cfg;
-} __attribute__((packed)) audpp_cmd_cfg_dec_type;
-
-/*
- * Command Structure to Pause , Resume and flushes the selected audio decoders
- */
-
-#define AUDPP_CMD_DEC_CTRL 0x0002
-#define AUDPP_CMD_DEC_CTRL_LEN sizeof(audpp_cmd_dec_ctrl)
-
-/* Decoder control commands for pause, resume and flush */
-#define AUDPP_CMD_FLUSH_V 0x2000
-
-#define AUDPP_CMD_PAUSE_V 0x4000
-#define AUDPP_CMD_RESUME_V 0x0000
-
-#define AUDPP_CMD_UPDATE_V 0x8000
-#define AUDPP_CMD_IGNORE_V 0x0000
-
-
-/* Type Spec for decoder control command*/
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short dec0_ctrl;
- unsigned short dec1_ctrl;
- unsigned short dec2_ctrl;
- unsigned short dec3_ctrl;
- unsigned short dec4_ctrl;
-} __attribute__((packed)) audpp_cmd_dec_ctrl;
-
-/*
- * Command Structure to Configure the AVSync FeedBack Mechanism
- */
-
-#define AUDPP_CMD_AVSYNC 0x0003
-#define AUDPP_CMD_AVSYNC_LEN sizeof(audpp_cmd_avsync)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short object_number;
- unsigned short interrupt_interval_lsw;
- unsigned short interrupt_interval_msw;
-} __attribute__((packed)) audpp_cmd_avsync;
-
-/*
- * Command Structure to enable or disable(sleep) the AUDPPTASK
- */
-
-#define AUDPP_CMD_CFG 0x0004
-#define AUDPP_CMD_CFG_LEN sizeof(audpp_cmd_cfg)
-
-#define AUDPP_CMD_CFG_SLEEP 0x0000
-#define AUDPP_CMD_CFG_ENABLE 0xFFFF
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short cfg;
-} __attribute__((packed)) audpp_cmd_cfg;
-
-/*
- * Command Structure to Inject or drop the specified no of samples
- */
-
-#define AUDPP_CMD_ADJUST_SAMP 0x0005
-#define AUDPP_CMD_ADJUST_SAMP_LEN sizeof(audpp_cmd_adjust_samp)
-
-#define AUDPP_CMD_SAMP_DROP -1
-#define AUDPP_CMD_SAMP_INSERT 0x0001
-
-#define AUDPP_CMD_NUM_SAMPLES 0x0001
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short object_no;
- signed short sample_insert_or_drop;
- unsigned short num_samples;
-} __attribute__((packed)) audpp_cmd_adjust_samp;
-
-/*
- * Command Structure to Configure AVSync Feedback Mechanism
- */
-
-#define AUDPP_CMD_AVSYNC_CMD_2 0x0006
-#define AUDPP_CMD_AVSYNC_CMD_2_LEN sizeof(audpp_cmd_avsync_cmd_2)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short object_number;
- unsigned short interrupt_interval_lsw;
- unsigned short interrupt_interval_msw;
- unsigned short sample_counter_dlsw;
- unsigned short sample_counter_dmsw;
- unsigned short sample_counter_msw;
- unsigned short byte_counter_dlsw;
- unsigned short byte_counter_dmsw;
- unsigned short byte_counter_msw;
-} __attribute__((packed)) audpp_cmd_avsync_cmd_2;
-
-/*
- * Command Structure to Configure AVSync Feedback Mechanism
- */
-
-#define AUDPP_CMD_AVSYNC_CMD_3 0x0007
-#define AUDPP_CMD_AVSYNC_CMD_3_LEN sizeof(audpp_cmd_avsync_cmd_3)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short object_number;
- unsigned short interrupt_interval_lsw;
- unsigned short interrupt_interval_msw;
- unsigned short sample_counter_dlsw;
- unsigned short sample_counter_dmsw;
- unsigned short sample_counter_msw;
- unsigned short byte_counter_dlsw;
- unsigned short byte_counter_dmsw;
- unsigned short byte_counter_msw;
-} __attribute__((packed)) audpp_cmd_avsync_cmd_3;
-
-#define AUDPP_CMD_ROUTING_MODE 0x0008
-#define AUDPP_CMD_ROUTING_MODE_LEN \
-sizeof(struct audpp_cmd_routing_mode)
-
-struct audpp_cmd_routing_mode {
- unsigned short cmd_id;
- unsigned short object_number;
- unsigned short routing_mode;
-} __attribute__((packed));
-
-/*
- * Commands Related to uPAudPPCmd2Queue
- */
-
-/*
- * Command Structure to configure Per decoder Parameters (Common)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS 0x0000
-#define AUDPP_CMD_CFG_ADEC_PARAMS_COMMON_LEN \
- sizeof(audpp_cmd_cfg_adec_params_common)
-
-#define AUDPP_CMD_STATUS_MSG_FLAG_ENA_FCM 0x4000
-#define AUDPP_CMD_STATUS_MSG_FLAG_DIS_FCM 0x0000
-
-#define AUDPP_CMD_STATUS_MSG_FLAG_ENA_DCM 0x8000
-#define AUDPP_CMD_STATUS_MSG_FLAG_DIS_DCM 0x0000
-
-/* Sampling frequency*/
-#define AUDPP_CMD_SAMP_RATE_96000 0x0000
-#define AUDPP_CMD_SAMP_RATE_88200 0x0001
-#define AUDPP_CMD_SAMP_RATE_64000 0x0002
-#define AUDPP_CMD_SAMP_RATE_48000 0x0003
-#define AUDPP_CMD_SAMP_RATE_44100 0x0004
-#define AUDPP_CMD_SAMP_RATE_32000 0x0005
-#define AUDPP_CMD_SAMP_RATE_24000 0x0006
-#define AUDPP_CMD_SAMP_RATE_22050 0x0007
-#define AUDPP_CMD_SAMP_RATE_16000 0x0008
-#define AUDPP_CMD_SAMP_RATE_12000 0x0009
-#define AUDPP_CMD_SAMP_RATE_11025 0x000A
-#define AUDPP_CMD_SAMP_RATE_8000 0x000B
-
-
-/*
- * Type specification of cmd_adec_cfg sent to all decoder
- */
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short length;
- unsigned short dec_id;
- unsigned short status_msg_flag;
- unsigned short decoder_frame_counter_msg_period;
- unsigned short input_sampling_frequency;
-} __attribute__((packed)) audpp_cmd_cfg_adec_params_common;
-
-/*
- * Command Structure to configure Per decoder Parameters (Wav)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_WAV_LEN \
- sizeof(audpp_cmd_cfg_adec_params_wav)
-
-
-#define AUDPP_CMD_WAV_STEREO_CFG_MONO 0x0001
-#define AUDPP_CMD_WAV_STEREO_CFG_STEREO 0x0002
-
-#define AUDPP_CMD_WAV_PCM_WIDTH_8 0x0000
-#define AUDPP_CMD_WAV_PCM_WIDTH_16 0x0001
-#define AUDPP_CMD_WAV_PCM_WIDTH_32 0x0002
-
-typedef struct {
- audpp_cmd_cfg_adec_params_common common;
- unsigned short stereo_cfg;
- unsigned short pcm_width;
- unsigned short sign;
-} __attribute__((packed)) audpp_cmd_cfg_adec_params_wav;
-
-/*
- * Command Structure to configure Per decoder Parameters (ADPCM)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_ADPCM_LEN \
- sizeof(audpp_cmd_cfg_adec_params_adpcm)
-
-
-#define AUDPP_CMD_ADPCM_STEREO_CFG_MONO 0x0001
-#define AUDPP_CMD_ADPCM_STEREO_CFG_STEREO 0x0002
-
-typedef struct {
- audpp_cmd_cfg_adec_params_common common;
- unsigned short stereo_cfg;
- unsigned short block_size;
-} __attribute__((packed)) audpp_cmd_cfg_adec_params_adpcm;
-
-/*
- * Command Structure to configure Per decoder Parameters (MP3)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_MP3_LEN \
- sizeof(audpp_cmd_cfg_adec_params_mp3)
-
-typedef struct {
- audpp_cmd_cfg_adec_params_common common;
-} __attribute__((packed)) audpp_cmd_cfg_adec_params_mp3;
-
-
-/*
- * Command Structure to configure Per decoder Parameters (AAC)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_AAC_LEN \
- sizeof(audpp_cmd_cfg_adec_params_aac)
-
-
-#define AUDPP_CMD_AAC_FORMAT_ADTS -1
-#define AUDPP_CMD_AAC_FORMAT_RAW 0x0000
-#define AUDPP_CMD_AAC_FORMAT_PSUEDO_RAW 0x0001
-#define AUDPP_CMD_AAC_FORMAT_LOAS 0x0002
-
-#define AUDPP_CMD_AAC_AUDIO_OBJECT_LC 0x0002
-#define AUDPP_CMD_AAC_AUDIO_OBJECT_LTP 0x0004
-#define AUDPP_CMD_AAC_AUDIO_OBJECT_ERLC 0x0011
-
-#define AUDPP_CMD_AAC_SBR_ON_FLAG_ON 0x0001
-#define AUDPP_CMD_AAC_SBR_ON_FLAG_OFF 0x0000
-
-#define AUDPP_CMD_AAC_SBR_PS_ON_FLAG_ON 0x0001
-#define AUDPP_CMD_AAC_SBR_PS_ON_FLAG_OFF 0x0000
-
-typedef struct {
- audpp_cmd_cfg_adec_params_common common;
- signed short format;
- unsigned short audio_object;
- unsigned short ep_config;
- unsigned short aac_section_data_resilience_flag;
- unsigned short aac_scalefactor_data_resilience_flag;
- unsigned short aac_spectral_data_resilience_flag;
- unsigned short sbr_on_flag;
- unsigned short sbr_ps_on_flag;
- unsigned short dual_mono_mode;
- unsigned short channel_configuration;
-} __attribute__((packed)) audpp_cmd_cfg_adec_params_aac;
-
-/*
- * Command Structure to configure Per decoder Parameters (V13K)
- */
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_V13K_LEN \
- sizeof(struct audpp_cmd_cfg_adec_params_v13k)
-
-
-#define AUDPP_CMD_STEREO_CFG_MONO 0x0001
-#define AUDPP_CMD_STEREO_CFG_STEREO 0x0002
-
-struct audpp_cmd_cfg_adec_params_v13k {
- audpp_cmd_cfg_adec_params_common common;
- unsigned short stereo_cfg;
-} __attribute__((packed));
-
-#define AUDPP_CMD_CFG_ADEC_PARAMS_EVRC_LEN \
- sizeof(struct audpp_cmd_cfg_adec_params_evrc)
-
-struct audpp_cmd_cfg_adec_params_evrc {
- audpp_cmd_cfg_adec_params_common common;
- unsigned short stereo_cfg;
-} __attribute__ ((packed));
-
-/*
- * Command Structure to configure the HOST PCM interface
- */
-
-#define AUDPP_CMD_PCM_INTF 0x0001
-#define AUDPP_CMD_PCM_INTF_2 0x0002
-#define AUDPP_CMD_PCM_INTF_LEN sizeof(audpp_cmd_pcm_intf)
-
-#define AUDPP_CMD_PCM_INTF_MONO_V 0x0001
-#define AUDPP_CMD_PCM_INTF_STEREO_V 0x0002
-
-/* These two values differentiate the two types of commands that could be issued
- * Interface configuration command and Buffer update command */
-
-#define AUDPP_CMD_PCM_INTF_CONFIG_CMD_V 0x0000
-#define AUDPP_CMD_PCM_INTF_BUFFER_CMD_V -1
-
-#define AUDPP_CMD_PCM_INTF_RX_ENA_M 0x000F
-#define AUDPP_CMD_PCM_INTF_RX_ENA_ARMTODSP_V 0x0008
-#define AUDPP_CMD_PCM_INTF_RX_ENA_DSPTOARM_V 0x0004
-
-/* These flags control the enabling and disabling of the interface together
- * with host interface bit mask. */
-
-#define AUDPP_CMD_PCM_INTF_ENA_V -1
-#define AUDPP_CMD_PCM_INTF_DIS_V 0x0000
-
-
-#define AUDPP_CMD_PCM_INTF_FULL_DUPLEX 0x0
-#define AUDPP_CMD_PCM_INTF_HALF_DUPLEX_TODSP 0x1
-
-
-#define AUDPP_CMD_PCM_INTF_OBJECT_NUM 0x5
-#define AUDPP_CMD_PCM_INTF_COMMON_OBJECT_NUM 0x6
-
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short object_num;
- signed short config;
- unsigned short intf_type;
-
- /* DSP -> ARM Configuration */
- unsigned short read_buf1LSW;
- unsigned short read_buf1MSW;
- unsigned short read_buf1_len;
-
- unsigned short read_buf2LSW;
- unsigned short read_buf2MSW;
- unsigned short read_buf2_len;
- /* 0:HOST_PCM_INTF disable
- ** 0xFFFF: HOST_PCM_INTF enable
- */
- signed short dsp_to_arm_flag;
- unsigned short partition_number;
-
- /* ARM -> DSP Configuration */
- unsigned short write_buf1LSW;
- unsigned short write_buf1MSW;
- unsigned short write_buf1_len;
-
- unsigned short write_buf2LSW;
- unsigned short write_buf2MSW;
- unsigned short write_buf2_len;
-
- /* 0:HOST_PCM_INTF disable
- ** 0xFFFF: HOST_PCM_INTF enable
- */
- signed short arm_to_rx_flag;
- unsigned short weight_decoder_to_rx;
- unsigned short weight_arm_to_rx;
-
- unsigned short partition_number_arm_to_dsp;
- unsigned short sample_rate;
- unsigned short channel_mode;
-} __attribute__((packed)) audpp_cmd_pcm_intf;
-
-/*
- ** BUFFER UPDATE COMMAND
- */
-#define AUDPP_CMD_PCM_INTF_SEND_BUF_PARAMS_LEN \
- sizeof(audpp_cmd_pcm_intf_send_buffer)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short host_pcm_object;
- /* set config = 0xFFFF for configuration*/
- signed short config;
- unsigned short intf_type;
- unsigned short dsp_to_arm_buf_id;
- unsigned short arm_to_dsp_buf_id;
- unsigned short arm_to_dsp_buf_len;
-} __attribute__((packed)) audpp_cmd_pcm_intf_send_buffer;
-
-
-/*
- * Commands Related to uPAudPPCmd3Queue
- */
-
-/*
- * Command Structure to configure post processing params (Commmon)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS 0x0000
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_COMMON_LEN \
- sizeof(audpp_cmd_cfg_object_params_common)
-
-#define AUDPP_CMD_OBJ0_UPDATE 0x8000
-#define AUDPP_CMD_OBJ0_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_OBJ1_UPDATE 0x8000
-#define AUDPP_CMD_OBJ1_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_OBJ2_UPDATE 0x8000
-#define AUDPP_CMD_OBJ2_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_OBJ3_UPDATE 0x8000
-#define AUDPP_CMD_OBJ3_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_OBJ4_UPDATE 0x8000
-#define AUDPP_CMD_OBJ4_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_HPCM_UPDATE 0x8000
-#define AUDPP_CMD_HPCM_DONT_UPDATE 0x0000
-
-#define AUDPP_CMD_COMMON_CFG_UPDATE 0x8000
-#define AUDPP_CMD_COMMON_CFG_DONT_UPDATE 0x0000
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short obj0_cfg;
- unsigned short obj1_cfg;
- unsigned short obj2_cfg;
- unsigned short obj3_cfg;
- unsigned short obj4_cfg;
- unsigned short host_pcm_obj_cfg;
- unsigned short comman_cfg;
- unsigned short command_type;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_common;
-
-/*
- * Command Structure to configure post processing params (Volume)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_VOLUME_LEN \
- sizeof(audpp_cmd_cfg_object_params_volume)
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- unsigned short volume;
- unsigned short pan;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_volume;
-
-/*
- * Command Structure to configure post processing params (PCM Filter) --DOUBT
- */
-
-typedef struct {
- unsigned short numerator_b0_filter_lsw;
- unsigned short numerator_b0_filter_msw;
- unsigned short numerator_b1_filter_lsw;
- unsigned short numerator_b1_filter_msw;
- unsigned short numerator_b2_filter_lsw;
- unsigned short numerator_b2_filter_msw;
-} __attribute__((packed)) numerator;
-
-typedef struct {
- unsigned short denominator_a0_filter_lsw;
- unsigned short denominator_a0_filter_msw;
- unsigned short denominator_a1_filter_lsw;
- unsigned short denominator_a1_filter_msw;
-} __attribute__((packed)) denominator;
-
-typedef struct {
- unsigned short shift_factor_0;
-} __attribute__((packed)) shift_factor;
-
-typedef struct {
- unsigned short pan_filter_0;
-} __attribute__((packed)) pan;
-
-typedef struct {
- numerator numerator_filter;
- denominator denominator_filter;
- shift_factor shift_factor_filter;
- pan pan_filter;
-} __attribute__((packed)) filter_1;
-
-typedef struct {
- numerator numerator_filter[2];
- denominator denominator_filter[2];
- shift_factor shift_factor_filter[2];
- pan pan_filter[2];
-} __attribute__((packed)) filter_2;
-
-typedef struct {
- numerator numerator_filter[3];
- denominator denominator_filter[3];
- shift_factor shift_factor_filter[3];
- pan pan_filter[3];
-} __attribute__((packed)) filter_3;
-
-typedef struct {
- numerator numerator_filter[4];
- denominator denominator_filter[4];
- shift_factor shift_factor_filter[4];
- pan pan_filter[4];
-} __attribute__((packed)) filter_4;
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_PCM_LEN \
- sizeof(audpp_cmd_cfg_object_params_pcm)
-
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- unsigned short active_flag;
- unsigned short num_bands;
- union {
- filter_1 filter_1_params;
- filter_2 filter_2_params;
- filter_3 filter_3_params;
- filter_4 filter_4_params;
- } __attribute__((packed)) params_filter;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_pcm;
-
-
-/*
- * Command Structure to configure post processing parameters (equalizer)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_EQALIZER_LEN \
- sizeof(audpp_cmd_cfg_object_params_eqalizer)
-
-typedef struct {
- unsigned short numerator_coeff_0_lsw;
- unsigned short numerator_coeff_0_msw;
- unsigned short numerator_coeff_1_lsw;
- unsigned short numerator_coeff_1_msw;
- unsigned short numerator_coeff_2_lsw;
- unsigned short numerator_coeff_2_msw;
-} __attribute__((packed)) eq_numerator;
-
-typedef struct {
- unsigned short denominator_coeff_0_lsw;
- unsigned short denominator_coeff_0_msw;
- unsigned short denominator_coeff_1_lsw;
- unsigned short denominator_coeff_1_msw;
-} __attribute__((packed)) eq_denominator;
-
-typedef struct {
- unsigned short shift_factor;
-} __attribute__((packed)) eq_shiftfactor;
-
-typedef struct {
- eq_numerator numerator;
- eq_denominator denominator;
- eq_shiftfactor shiftfactor;
-} __attribute__((packed)) eq_coeff_1;
-
-typedef struct {
- eq_numerator numerator[2];
- eq_denominator denominator[2];
- eq_shiftfactor shiftfactor[2];
-} __attribute__((packed)) eq_coeff_2;
-
-typedef struct {
- eq_numerator numerator[3];
- eq_denominator denominator[3];
- eq_shiftfactor shiftfactor[3];
-} __attribute__((packed)) eq_coeff_3;
-
-typedef struct {
- eq_numerator numerator[4];
- eq_denominator denominator[4];
- eq_shiftfactor shiftfactor[4];
-} __attribute__((packed)) eq_coeff_4;
-
-typedef struct {
- eq_numerator numerator[5];
- eq_denominator denominator[5];
- eq_shiftfactor shiftfactor[5];
-} __attribute__((packed)) eq_coeff_5;
-
-typedef struct {
- eq_numerator numerator[6];
- eq_denominator denominator[6];
- eq_shiftfactor shiftfactor[6];
-} __attribute__((packed)) eq_coeff_6;
-
-typedef struct {
- eq_numerator numerator[7];
- eq_denominator denominator[7];
- eq_shiftfactor shiftfactor[7];
-} __attribute__((packed)) eq_coeff_7;
-
-typedef struct {
- eq_numerator numerator[8];
- eq_denominator denominator[8];
- eq_shiftfactor shiftfactor[8];
-} __attribute__((packed)) eq_coeff_8;
-
-typedef struct {
- eq_numerator numerator[9];
- eq_denominator denominator[9];
- eq_shiftfactor shiftfactor[9];
-} __attribute__((packed)) eq_coeff_9;
-
-typedef struct {
- eq_numerator numerator[10];
- eq_denominator denominator[10];
- eq_shiftfactor shiftfactor[10];
-} __attribute__((packed)) eq_coeff_10;
-
-typedef struct {
- eq_numerator numerator[11];
- eq_denominator denominator[11];
- eq_shiftfactor shiftfactor[11];
-} __attribute__((packed)) eq_coeff_11;
-
-typedef struct {
- eq_numerator numerator[12];
- eq_denominator denominator[12];
- eq_shiftfactor shiftfactor[12];
-} __attribute__((packed)) eq_coeff_12;
-
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- unsigned short eq_flag;
- unsigned short num_bands;
- union {
- eq_coeff_1 eq_coeffs_1;
- eq_coeff_2 eq_coeffs_2;
- eq_coeff_3 eq_coeffs_3;
- eq_coeff_4 eq_coeffs_4;
- eq_coeff_5 eq_coeffs_5;
- eq_coeff_6 eq_coeffs_6;
- eq_coeff_7 eq_coeffs_7;
- eq_coeff_8 eq_coeffs_8;
- eq_coeff_9 eq_coeffs_9;
- eq_coeff_10 eq_coeffs_10;
- eq_coeff_11 eq_coeffs_11;
- eq_coeff_12 eq_coeffs_12;
- } __attribute__((packed)) eq_coeff;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_eqalizer;
-
-
-/*
- * Command Structure to configure post processing parameters (ADRC)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_ADRC_LEN \
- sizeof(audpp_cmd_cfg_object_params_adrc)
-
-
-#define AUDPP_CMD_ADRC_FLAG_DIS 0x0000
-#define AUDPP_CMD_ADRC_FLAG_ENA -1
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- signed short adrc_flag;
- unsigned short compression_th;
- unsigned short compression_slope;
- unsigned short rms_time;
- unsigned short attack_const_lsw;
- unsigned short attack_const_msw;
- unsigned short release_const_lsw;
- unsigned short release_const_msw;
- unsigned short adrc_system_delay;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_adrc;
-
-/*
- * Command Structure to configure post processing parameters(Spectrum Analizer)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_SPECTRAM_LEN \
- sizeof(audpp_cmd_cfg_object_params_spectram)
-
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- unsigned short sample_interval;
- unsigned short num_coeff;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_spectram;
-
-/*
- * Command Structure to configure post processing parameters (QConcert)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_QCONCERT_LEN \
- sizeof(audpp_cmd_cfg_object_params_qconcert)
-
-
-#define AUDPP_CMD_QCON_ENA_FLAG_ENA -1
-#define AUDPP_CMD_QCON_ENA_FLAG_DIS 0x0000
-
-#define AUDPP_CMD_QCON_OP_MODE_HEADPHONE -1
-#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_FRONT 0x0000
-#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_SIDE 0x0001
-#define AUDPP_CMD_QCON_OP_MODE_SPEAKER_DESKTOP 0x0002
-
-#define AUDPP_CMD_QCON_GAIN_UNIT 0x7FFF
-#define AUDPP_CMD_QCON_GAIN_SIX_DB 0x4027
-
-
-#define AUDPP_CMD_QCON_EXPANSION_MAX 0x7FFF
-
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- signed short enable_flag;
- signed short output_mode;
- signed short gain;
- signed short expansion;
- signed short delay;
- unsigned short stages_per_mode;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_qconcert;
-
-/*
- * Command Structure to configure post processing parameters (Side Chain)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_SIDECHAIN_LEN \
- sizeof(audpp_cmd_cfg_object_params_sidechain)
-
-
-#define AUDPP_CMD_SIDECHAIN_ACTIVE_FLAG_DIS 0x0000
-#define AUDPP_CMD_SIDECHAIN_ACTIVE_FLAG_ENA -1
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- signed short active_flag;
- unsigned short num_bands;
- union {
- filter_1 filter_1_params;
- filter_2 filter_2_params;
- filter_3 filter_3_params;
- filter_4 filter_4_params;
- } __attribute__((packed)) params_filter;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_sidechain;
-
-
-/*
- * Command Structure to configure post processing parameters (QAFX)
- */
-
-#define AUDPP_CMD_CFG_OBJECT_PARAMS_QAFX_LEN \
- sizeof(audpp_cmd_cfg_object_params_qafx)
-
-#define AUDPP_CMD_QAFX_ENA_DISA 0x0000
-#define AUDPP_CMD_QAFX_ENA_ENA_CFG -1
-#define AUDPP_CMD_QAFX_ENA_DIS_CFG 0x0001
-
-#define AUDPP_CMD_QAFX_CMD_TYPE_ENV 0x0100
-#define AUDPP_CMD_QAFX_CMD_TYPE_OBJ 0x0010
-#define AUDPP_CMD_QAFX_CMD_TYPE_QUERY 0x1000
-
-#define AUDPP_CMD_QAFX_CMDS_ENV_OP_MODE 0x0100
-#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_POS 0x0101
-#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_ORI 0x0102
-#define AUDPP_CMD_QAFX_CMDS_ENV_LIS_VEL 0X0103
-#define AUDPP_CMD_QAFX_CMDS_ENV_ENV_RES 0x0107
-
-#define AUDPP_CMD_QAFX_CMDS_OBJ_SAMP_FREQ 0x0010
-#define AUDPP_CMD_QAFX_CMDS_OBJ_VOL 0x0011
-#define AUDPP_CMD_QAFX_CMDS_OBJ_DIST 0x0012
-#define AUDPP_CMD_QAFX_CMDS_OBJ_POS 0x0013
-#define AUDPP_CMD_QAFX_CMDS_OBJ_VEL 0x0014
-
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- signed short enable;
- unsigned short command_type;
- unsigned short num_commands;
- unsigned short commands;
-} __attribute__((packed)) audpp_cmd_cfg_object_params_qafx;
-
-/*
- * Command Structure to enable , disable or configure the reverberation effect
- * (Common)
- */
-
-#define AUDPP_CMD_REVERB_CONFIG 0x0001
-#define AUDPP_CMD_REVERB_CONFIG_COMMON_LEN \
- sizeof(audpp_cmd_reverb_config_common)
-
-#define AUDPP_CMD_ENA_ENA 0xFFFF
-#define AUDPP_CMD_ENA_DIS 0x0000
-#define AUDPP_CMD_ENA_CFG 0x0001
-
-#define AUDPP_CMD_CMD_TYPE_ENV 0x0104
-#define AUDPP_CMD_CMD_TYPE_OBJ 0x0015
-#define AUDPP_CMD_CMD_TYPE_QUERY 0x1000
-
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short enable;
- unsigned short cmd_type;
-} __attribute__((packed)) audpp_cmd_reverb_config_common;
-
-/*
- * Command Structure to enable , disable or configure the reverberation effect
- * (ENV-0x0104)
- */
-
-#define AUDPP_CMD_REVERB_CONFIG_ENV_104_LEN \
- sizeof(audpp_cmd_reverb_config_env_104)
-
-typedef struct {
- audpp_cmd_reverb_config_common common;
- unsigned short env_gain;
- unsigned short decay_msw;
- unsigned short decay_lsw;
- unsigned short decay_timeratio_msw;
- unsigned short decay_timeratio_lsw;
- unsigned short delay_time;
- unsigned short reverb_gain;
- unsigned short reverb_delay;
-} __attribute__((packed)) audpp_cmd_reverb_config_env_104;
-
-/*
- * Command Structure to enable , disable or configure the reverberation effect
- * (ENV-0x0015)
- */
-
-#define AUDPP_CMD_REVERB_CONFIG_ENV_15_LEN \
- sizeof(audpp_cmd_reverb_config_env_15)
-
-typedef struct {
- audpp_cmd_reverb_config_common common;
- unsigned short object_num;
- unsigned short absolute_gain;
-} __attribute__((packed)) audpp_cmd_reverb_config_env_15;
-
-
-#endif /* QDSP5AUDPPCMDI_H */
-
+++ /dev/null
-#ifndef QDSP5AUDPPMSG_H
-#define QDSP5AUDPPMSG_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- Q D S P 5 A U D I O P O S T P R O C E S S I N G M S G
-
-GENERAL DESCRIPTION
- Messages sent by AUDPPTASK to ARM
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
- $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audppmsg.h#4 $
-
-===========================================================================*/
-
-/*
- * AUDPPTASK uses audPPuPRlist to send messages to the ARM
- * Location : MEMA
- * Buffer Size : 45
- * No of Buffers in a queue : 5 for gaming audio and 1 for other images
- */
-
-/*
- * MSG to Informs the ARM os Success/Failure of bringing up the decoder
- */
-
-#define AUDPP_MSG_STATUS_MSG 0x0001
-#define AUDPP_MSG_STATUS_MSG_LEN \
- sizeof(audpp_msg_status_msg)
-
-#define AUDPP_MSG_STATUS_SLEEP 0x0000
-#define AUDPP_MSG__STATUS_INIT 0x0001
-#define AUDPP_MSG_MSG_STATUS_CFG 0x0002
-#define AUDPP_MSG_STATUS_PLAY 0x0003
-
-#define AUDPP_MSG_REASON_MIPS 0x0000
-#define AUDPP_MSG_REASON_MEM 0x0001
-
-typedef struct{
- unsigned short dec_id;
- unsigned short status;
- unsigned short reason;
-} __attribute__((packed)) audpp_msg_status_msg;
-
-/*
- * MSG to communicate the spectrum analyzer output bands to the ARM
- */
-#define AUDPP_MSG_SPA_BANDS 0x0002
-#define AUDPP_MSG_SPA_BANDS_LEN \
- sizeof(audpp_msg_spa_bands)
-
-typedef struct {
- unsigned short current_object;
- unsigned short spa_band_1;
- unsigned short spa_band_2;
- unsigned short spa_band_3;
- unsigned short spa_band_4;
- unsigned short spa_band_5;
- unsigned short spa_band_6;
- unsigned short spa_band_7;
- unsigned short spa_band_8;
- unsigned short spa_band_9;
- unsigned short spa_band_10;
- unsigned short spa_band_11;
- unsigned short spa_band_12;
- unsigned short spa_band_13;
- unsigned short spa_band_14;
- unsigned short spa_band_15;
- unsigned short spa_band_16;
- unsigned short spa_band_17;
- unsigned short spa_band_18;
- unsigned short spa_band_19;
- unsigned short spa_band_20;
- unsigned short spa_band_21;
- unsigned short spa_band_22;
- unsigned short spa_band_23;
- unsigned short spa_band_24;
- unsigned short spa_band_25;
- unsigned short spa_band_26;
- unsigned short spa_band_27;
- unsigned short spa_band_28;
- unsigned short spa_band_29;
- unsigned short spa_band_30;
- unsigned short spa_band_31;
- unsigned short spa_band_32;
-} __attribute__((packed)) audpp_msg_spa_bands;
-
-/*
- * MSG to communicate the PCM I/O buffer status to ARM
- */
-#define AUDPP_MSG_HOST_PCM_INTF_MSG 0x0003
-#define AUDPP_MSG_HOST_PCM_INTF_MSG_LEN \
- sizeof(audpp_msg_host_pcm_intf_msg)
-
-#define AUDPP_MSG_HOSTPCM_ID_TX_ARM 0x0000
-#define AUDPP_MSG_HOSTPCM_ID_ARM_TX 0x0001
-#define AUDPP_MSG_HOSTPCM_ID_RX_ARM 0x0002
-#define AUDPP_MSG_HOSTPCM_ID_ARM_RX 0x0003
-
-#define AUDPP_MSG_SAMP_FREQ_INDX_96000 0x0000
-#define AUDPP_MSG_SAMP_FREQ_INDX_88200 0x0001
-#define AUDPP_MSG_SAMP_FREQ_INDX_64000 0x0002
-#define AUDPP_MSG_SAMP_FREQ_INDX_48000 0x0003
-#define AUDPP_MSG_SAMP_FREQ_INDX_44100 0x0004
-#define AUDPP_MSG_SAMP_FREQ_INDX_32000 0x0005
-#define AUDPP_MSG_SAMP_FREQ_INDX_24000 0x0006
-#define AUDPP_MSG_SAMP_FREQ_INDX_22050 0x0007
-#define AUDPP_MSG_SAMP_FREQ_INDX_16000 0x0008
-#define AUDPP_MSG_SAMP_FREQ_INDX_12000 0x0009
-#define AUDPP_MSG_SAMP_FREQ_INDX_11025 0x000A
-#define AUDPP_MSG_SAMP_FREQ_INDX_8000 0x000B
-
-#define AUDPP_MSG_CHANNEL_MODE_MONO 0x0001
-#define AUDPP_MSG_CHANNEL_MODE_STEREO 0x0002
-
-typedef struct{
- unsigned short obj_num;
- unsigned short numbers_of_samples;
- unsigned short host_pcm_id;
- unsigned short buf_indx;
- unsigned short samp_freq_indx;
- unsigned short channel_mode;
-} __attribute__((packed)) audpp_msg_host_pcm_intf_msg;
-
-
-/*
- * MSG to communicate 3D position of the source and listener , source volume
- * source rolloff, source orientation
- */
-
-#define AUDPP_MSG_QAFX_POS 0x0004
-#define AUDPP_MSG_QAFX_POS_LEN \
- sizeof(audpp_msg_qafx_pos)
-
-typedef struct {
- unsigned short current_object;
- unsigned short x_pos_lis_msw;
- unsigned short x_pos_lis_lsw;
- unsigned short y_pos_lis_msw;
- unsigned short y_pos_lis_lsw;
- unsigned short z_pos_lis_msw;
- unsigned short z_pos_lis_lsw;
- unsigned short x_fwd_msw;
- unsigned short x_fwd_lsw;
- unsigned short y_fwd_msw;
- unsigned short y_fwd_lsw;
- unsigned short z_fwd_msw;
- unsigned short z_fwd_lsw;
- unsigned short x_up_msw;
- unsigned short x_up_lsw;
- unsigned short y_up_msw;
- unsigned short y_up_lsw;
- unsigned short z_up_msw;
- unsigned short z_up_lsw;
- unsigned short x_vel_lis_msw;
- unsigned short x_vel_lis_lsw;
- unsigned short y_vel_lis_msw;
- unsigned short y_vel_lis_lsw;
- unsigned short z_vel_lis_msw;
- unsigned short z_vel_lis_lsw;
- unsigned short threed_enable_flag;
- unsigned short volume;
- unsigned short x_pos_source_msw;
- unsigned short x_pos_source_lsw;
- unsigned short y_pos_source_msw;
- unsigned short y_pos_source_lsw;
- unsigned short z_pos_source_msw;
- unsigned short z_pos_source_lsw;
- unsigned short max_dist_0_msw;
- unsigned short max_dist_0_lsw;
- unsigned short min_dist_0_msw;
- unsigned short min_dist_0_lsw;
- unsigned short roll_off_factor;
- unsigned short mute_after_max_flag;
- unsigned short x_vel_source_msw;
- unsigned short x_vel_source_lsw;
- unsigned short y_vel_source_msw;
- unsigned short y_vel_source_lsw;
- unsigned short z_vel_source_msw;
- unsigned short z_vel_source_lsw;
-} __attribute__((packed)) audpp_msg_qafx_pos;
-
-/*
- * MSG to provide AVSYNC feedback from DSP to ARM
- */
-
-#define AUDPP_MSG_AVSYNC_MSG 0x0005
-#define AUDPP_MSG_AVSYNC_MSG_LEN \
- sizeof(audpp_msg_avsync_msg)
-
-typedef struct {
- unsigned short active_flag;
- unsigned short num_samples_counter0_HSW;
- unsigned short num_samples_counter0_MSW;
- unsigned short num_samples_counter0_LSW;
- unsigned short num_bytes_counter0_HSW;
- unsigned short num_bytes_counter0_MSW;
- unsigned short num_bytes_counter0_LSW;
- unsigned short samp_freq_obj_0;
- unsigned short samp_freq_obj_1;
- unsigned short samp_freq_obj_2;
- unsigned short samp_freq_obj_3;
- unsigned short samp_freq_obj_4;
- unsigned short samp_freq_obj_5;
- unsigned short samp_freq_obj_6;
- unsigned short samp_freq_obj_7;
- unsigned short samp_freq_obj_8;
- unsigned short samp_freq_obj_9;
- unsigned short samp_freq_obj_10;
- unsigned short samp_freq_obj_11;
- unsigned short samp_freq_obj_12;
- unsigned short samp_freq_obj_13;
- unsigned short samp_freq_obj_14;
- unsigned short samp_freq_obj_15;
- unsigned short num_samples_counter4_HSW;
- unsigned short num_samples_counter4_MSW;
- unsigned short num_samples_counter4_LSW;
- unsigned short num_bytes_counter4_HSW;
- unsigned short num_bytes_counter4_MSW;
- unsigned short num_bytes_counter4_LSW;
-} __attribute__((packed)) audpp_msg_avsync_msg;
-
-/*
- * MSG to provide PCM DMA Missed feedback from the DSP to ARM
- */
-
-#define AUDPP_MSG_PCMDMAMISSED 0x0006
-#define AUDPP_MSG_PCMDMAMISSED_LEN \
- sizeof(audpp_msg_pcmdmamissed);
-
-typedef struct{
- /*
- ** Bit 0 0 = PCM DMA not missed for object 0
- ** 1 = PCM DMA missed for object0
- ** Bit 1 0 = PCM DMA not missed for object 1
- ** 1 = PCM DMA missed for object1
- ** Bit 2 0 = PCM DMA not missed for object 2
- ** 1 = PCM DMA missed for object2
- ** Bit 3 0 = PCM DMA not missed for object 3
- ** 1 = PCM DMA missed for object3
- ** Bit 4 0 = PCM DMA not missed for object 4
- ** 1 = PCM DMA missed for object4
- */
- unsigned short pcmdmamissed;
-} __attribute__((packed)) audpp_msg_pcmdmamissed;
-
-/*
- * MSG to AUDPP enable or disable feedback form DSP to ARM
- */
-
-#define AUDPP_MSG_CFG_MSG 0x0007
-#define AUDPP_MSG_CFG_MSG_LEN \
- sizeof(audpp_msg_cfg_msg)
-
-#define AUDPP_MSG_ENA_ENA 0xFFFF
-#define AUDPP_MSG_ENA_DIS 0x0000
-
-typedef struct{
- /* Enabled - 0xffff
- ** Disabled - 0
- */
- unsigned short enabled;
-} __attribute__((packed)) audpp_msg_cfg_msg;
-
-/*
- * MSG to communicate the reverb per object volume
- */
-
-#define AUDPP_MSG_QREVERB_VOLUME 0x0008
-#define AUDPP_MSG_QREVERB_VOLUME_LEN \
- sizeof(audpp_msg_qreverb_volume)
-
-
-typedef struct {
- unsigned short obj_0_gain;
- unsigned short obj_1_gain;
- unsigned short obj_2_gain;
- unsigned short obj_3_gain;
- unsigned short obj_4_gain;
- unsigned short hpcm_obj_volume;
-} __attribute__((packed)) audpp_msg_qreverb_volume;
-
-#define AUDPP_MSG_ROUTING_ACK 0x0009
-#define AUDPP_MSG_ROUTING_ACK_LEN \
- sizeof(struct audpp_msg_routing_ack)
-
-struct audpp_msg_routing_ack {
- unsigned short dec_id;
- unsigned short routing_mode;
-} __attribute__((packed));
-
-#define AUDPP_MSG_FLUSH_ACK 0x000A
-
-#endif /* QDSP5AUDPPMSG_H */
+++ /dev/null
-#ifndef QDSP5AUDPREPROCCMDI_H
-#define QDSP5AUDPREPROCCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- A U D I O P R E P R O C E S S I N G I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by AUDPREPROC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audpreproccmdi.h#2 $
-
-===========================================================================*/
-
-/*
- * AUDIOPREPROC COMMANDS:
- * ARM uses uPAudPreProcCmdQueue to communicate with AUDPREPROCTASK
- * Location : MEMB
- * Buffer size : 51
- * Number of buffers in a queue : 3
- */
-
-/*
- * Command to configure the parameters of AGC
- */
-
-#define AUDPREPROC_CMD_CFG_AGC_PARAMS 0x0000
-#define AUDPREPROC_CMD_CFG_AGC_PARAMS_LEN \
- sizeof(audpreproc_cmd_cfg_agc_params)
-
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_SLOPE 0x0009
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_TH 0x000A
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_SLOPE 0x000B
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_TH 0x000C
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_AIG_FLAG 0x000D
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_STATIC_GAIN 0x000E
-#define AUDPREPROC_CMD_TX_AGC_PARAM_MASK_TX_AGC_ENA_FLAG 0x000F
-
-#define AUDPREPROC_CMD_TX_AGC_ENA_FLAG_ENA -1
-#define AUDPREPROC_CMD_TX_AGC_ENA_FLAG_DIS 0x0000
-
-#define AUDPREPROC_CMD_ADP_GAIN_FLAG_ENA_ADP_GAIN -1
-#define AUDPREPROC_CMD_ADP_GAIN_FLAG_ENA_STATIC_GAIN 0x0000
-
-#define AUDPREPROC_CMD_PARAM_MASK_RMS_TAY 0x0004
-#define AUDPREPROC_CMD_PARAM_MASK_RELEASEK 0x0005
-#define AUDPREPROC_CMD_PARAM_MASK_DELAY 0x0006
-#define AUDPREPROC_CMD_PARAM_MASK_ATTACKK 0x0007
-#define AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_SLOW 0x0008
-#define AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_FAST 0x0009
-#define AUDPREPROC_CMD_PARAM_MASK_AIG_RELEASEK 0x000A
-#define AUDPREPROC_CMD_PARAM_MASK_AIG_MIN 0x000B
-#define AUDPREPROC_CMD_PARAM_MASK_AIG_MAX 0x000C
-#define AUDPREPROC_CMD_PARAM_MASK_LEAK_UP 0x000D
-#define AUDPREPROC_CMD_PARAM_MASK_LEAK_DOWN 0x000E
-#define AUDPREPROC_CMD_PARAM_MASK_AIG_ATTACKK 0x000F
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short tx_agc_param_mask;
- unsigned short tx_agc_enable_flag;
- unsigned short static_gain;
- signed short adaptive_gain_flag;
- unsigned short expander_th;
- unsigned short expander_slope;
- unsigned short compressor_th;
- unsigned short compressor_slope;
- unsigned short param_mask;
- unsigned short aig_attackk;
- unsigned short aig_leak_down;
- unsigned short aig_leak_up;
- unsigned short aig_max;
- unsigned short aig_min;
- unsigned short aig_releasek;
- unsigned short aig_leakrate_fast;
- unsigned short aig_leakrate_slow;
- unsigned short attackk_msw;
- unsigned short attackk_lsw;
- unsigned short delay;
- unsigned short releasek_msw;
- unsigned short releasek_lsw;
- unsigned short rms_tav;
-} __attribute__((packed)) audpreproc_cmd_cfg_agc_params;
-
-
-/*
- * Command to configure the params of Advanved AGC
- */
-
-#define AUDPREPROC_CMD_CFG_AGC_PARAMS_2 0x0001
-#define AUDPREPROC_CMD_CFG_AGC_PARAMS_2_LEN \
- sizeof(audpreproc_cmd_cfg_agc_params_2)
-
-#define AUDPREPROC_CMD_2_TX_AGC_ENA_FLAG_ENA -1;
-#define AUDPREPROC_CMD_2_TX_AGC_ENA_FLAG_DIS 0x0000;
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short agc_param_mask;
- signed short tx_agc_enable_flag;
- unsigned short comp_static_gain;
- unsigned short exp_th;
- unsigned short exp_slope;
- unsigned short comp_th;
- unsigned short comp_slope;
- unsigned short comp_rms_tav;
- unsigned short comp_samp_mask;
- unsigned short comp_attackk_msw;
- unsigned short comp_attackk_lsw;
- unsigned short comp_releasek_msw;
- unsigned short comp_releasek_lsw;
- unsigned short comp_delay;
- unsigned short comp_makeup_gain;
-} __attribute__((packed)) audpreproc_cmd_cfg_agc_params_2;
-
-/*
- * Command to configure params for ns
- */
-
-#define AUDPREPROC_CMD_CFG_NS_PARAMS 0x0002
-#define AUDPREPROC_CMD_CFG_NS_PARAMS_LEN \
- sizeof(audpreproc_cmd_cfg_ns_params)
-
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLMS_ENA 0x0001
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLMS_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_DES_ENA 0x0002
-#define AUDPREPROC_CMD_EC_MODE_NEW_DES_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_NS_ENA 0x0004
-#define AUDPREPROC_CMD_EC_MODE_NEW_NS_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_CNI_ENA 0x0008
-#define AUDPREPROC_CMD_EC_MODE_NEW_CNI_DIS 0x0000
-
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLES_ENA 0x0010
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLES_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_HB_ENA 0x0020
-#define AUDPREPROC_CMD_EC_MODE_NEW_HB_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_VA_ENA 0x0040
-#define AUDPREPROC_CMD_EC_MODE_NEW_VA_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_PCD_ENA 0x0080
-#define AUDPREPROC_CMD_EC_MODE_NEW_PCD_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_FEHI_ENA 0x0100
-#define AUDPREPROC_CMD_EC_MODE_NEW_FEHI_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_NEHI_ENA 0x0200
-#define AUDPREPROC_CMD_EC_MODE_NEW_NEHI_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLPP_ENA 0x0400
-#define AUDPREPROC_CMD_EC_MODE_NEW_NLPP_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_FNE_ENA 0x0800
-#define AUDPREPROC_CMD_EC_MODE_NEW_FNE_DIS 0x0000
-#define AUDPREPROC_CMD_EC_MODE_NEW_PRENLMS_ENA 0x1000
-#define AUDPREPROC_CMD_EC_MODE_NEW_PRENLMS_DIS 0x0000
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short ec_mode_new;
- unsigned short dens_gamma_n;
- unsigned short dens_nfe_block_size;
- unsigned short dens_limit_ns;
- unsigned short dens_limit_ns_d;
- unsigned short wb_gamma_e;
- unsigned short wb_gamma_n;
-} __attribute__((packed)) audpreproc_cmd_cfg_ns_params;
-
-/*
- * Command to configure parameters for IIR tuning filter
- */
-
-#define AUDPREPROC_CMD_CFG_IIR_TUNING_FILTER_PARAMS 0x0003
-#define AUDPREPROC_CMD_CFG_IIR_TUNING_FILTER_PARAMS_LEN \
- sizeof(audpreproc_cmd_cfg_iir_tuning_filter_params)
-
-#define AUDPREPROC_CMD_IIR_ACTIVE_FLAG_DIS 0x0000
-#define AUDPREPROC_CMD_IIR_ACTIVE_FLAG_ENA 0x0001
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short active_flag;
- unsigned short num_bands;
- unsigned short numerator_coeff_b0_filter0_lsw;
- unsigned short numerator_coeff_b0_filter0_msw;
- unsigned short numerator_coeff_b1_filter0_lsw;
- unsigned short numerator_coeff_b1_filter0_msw;
- unsigned short numerator_coeff_b2_filter0_lsw;
- unsigned short numerator_coeff_b2_filter0_msw;
- unsigned short numerator_coeff_b0_filter1_lsw;
- unsigned short numerator_coeff_b0_filter1_msw;
- unsigned short numerator_coeff_b1_filter1_lsw;
- unsigned short numerator_coeff_b1_filter1_msw;
- unsigned short numerator_coeff_b2_filter1_lsw;
- unsigned short numerator_coeff_b2_filter1_msw;
- unsigned short numerator_coeff_b0_filter2_lsw;
- unsigned short numerator_coeff_b0_filter2_msw;
- unsigned short numerator_coeff_b1_filter2_lsw;
- unsigned short numerator_coeff_b1_filter2_msw;
- unsigned short numerator_coeff_b2_filter2_lsw;
- unsigned short numerator_coeff_b2_filter2_msw;
- unsigned short numerator_coeff_b0_filter3_lsw;
- unsigned short numerator_coeff_b0_filter3_msw;
- unsigned short numerator_coeff_b1_filter3_lsw;
- unsigned short numerator_coeff_b1_filter3_msw;
- unsigned short numerator_coeff_b2_filter3_lsw;
- unsigned short numerator_coeff_b2_filter3_msw;
- unsigned short denominator_coeff_a0_filter0_lsw;
- unsigned short denominator_coeff_a0_filter0_msw;
- unsigned short denominator_coeff_a1_filter0_lsw;
- unsigned short denominator_coeff_a1_filter0_msw;
- unsigned short denominator_coeff_a0_filter1_lsw;
- unsigned short denominator_coeff_a0_filter1_msw;
- unsigned short denominator_coeff_a1_filter1_lsw;
- unsigned short denominator_coeff_a1_filter1_msw;
- unsigned short denominator_coeff_a0_filter2_lsw;
- unsigned short denominator_coeff_a0_filter2_msw;
- unsigned short denominator_coeff_a1_filter2_lsw;
- unsigned short denominator_coeff_a1_filter2_msw;
- unsigned short denominator_coeff_a0_filter3_lsw;
- unsigned short denominator_coeff_a0_filter3_msw;
- unsigned short denominator_coeff_a1_filter3_lsw;
- unsigned short denominator_coeff_a1_filter3_msw;
-
- unsigned short shift_factor_filter0;
- unsigned short shift_factor_filter1;
- unsigned short shift_factor_filter2;
- unsigned short shift_factor_filter3;
-
- unsigned short channel_selected0;
- unsigned short channel_selected1;
- unsigned short channel_selected2;
- unsigned short channel_selected3;
-} __attribute__((packed))audpreproc_cmd_cfg_iir_tuning_filter_params;
-
-#endif
+++ /dev/null
-#ifndef QDSP5AUDPREPROCMSG_H
-#define QDSP5AUDPREPROCMSG_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- A U D I O P R E P R O C E S S I N G M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of messages
- that are rcvd by AUDPREPROC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
- $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audpreprocmsg.h#3 $
-
-===========================================================================*/
-
-/*
- * ADSPREPROCTASK Messages
- * AUDPREPROCTASK uses audPreProcUpRlist to communicate with ARM
- * Location : MEMA
- * Message Length : 2
- */
-
-/*
- * Message to indicate particular feature has been enabled or disabled
- */
-
-
-#define AUDPREPROC_MSG_CMD_CFG_DONE_MSG 0x0000
-#define AUDPREPROC_MSG_CMD_CFG_DONE_MSG_LEN \
- sizeof(audpreproc_msg_cmd_cfg_done_msg)
-
-#define AUDPREPROC_MSG_TYPE_AGC 0x0000
-#define AUDPREPROC_MSG_TYPE_NOISE_REDUCTION 0x0001
-#define AUDPREPROC_MSG_TYPE_IIR_FILTER 0x0002
-
-
-#define AUDPREPROC_MSG_STATUS_FLAG_ENA -1
-#define AUDPREPROC_MSG_STATUS_FLAG_DIS 0x0000
-
-typedef struct {
- unsigned short type;
- signed short status_flag;
-} __attribute__((packed)) audpreproc_msg_cmd_cfg_done_msg;
-
-
-/*
- * Message to indicate particular feature has selected for wrong samp freq
- */
-
-#define AUDPREPROC_MSG_ERROR_MSG_ID 0x0001
-#define AUDPREPROC_MSG_ERROR_MSG_ID_LEN \
- sizeof(audpreproc_msg_error_msg_id)
-
-#define AUDPREPROC_MSG_ERR_INDEX_NS 0x0000
-
-typedef struct {
- unsigned short err_index;
-} __attribute__((packed)) audpreproc_msg_error_msg_id;
-
-#endif
+++ /dev/null
-#ifndef QDSP5AUDRECCMDI_H
-#define QDSP5AUDRECCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- A U D I O R E C O R D I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by AUDREC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
- $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audreccmdi.h#3 $
-
-============================================================================*/
-
-/*
- * AUDRECTASK COMMANDS
- * ARM uses 2 queues to communicate with the AUDRECTASK
- * 1.uPAudRecCmdQueue
- * Location :MEMC
- * Buffer Size : 8
- * No of Buffers in a queue : 3
- * 2.audRecUpBitStreamQueue
- * Location : MEMC
- * Buffer Size : 4
- * No of buffers in a queue : 2
- */
-
-/*
- * Commands on uPAudRecCmdQueue
- */
-
-/*
- * Command to initiate and terminate the audio recording section
- */
-
-#define AUDREC_CMD_CFG 0x0000
-#define AUDREC_CMD_CFG_LEN sizeof(audrec_cmd_cfg)
-
-#define AUDREC_CMD_TYPE_0_INDEX_WAV 0x0000
-#define AUDREC_CMD_TYPE_0_INDEX_AAC 0x0001
-
-#define AUDREC_CMD_TYPE_0_ENA 0x4000
-#define AUDREC_CMD_TYPE_0_DIS 0x0000
-
-#define AUDREC_CMD_TYPE_0_NOUPDATE 0x0000
-#define AUDREC_CMD_TYPE_0_UPDATE 0x8000
-
-#define AUDREC_CMD_TYPE_1_INDEX_SBC 0x0002
-
-#define AUDREC_CMD_TYPE_1_ENA 0x4000
-#define AUDREC_CMD_TYPE_1_DIS 0x0000
-
-#define AUDREC_CMD_TYPE_1_NOUPDATE 0x0000
-#define AUDREC_CMD_TYPE_1_UPDATE 0x8000
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short type_0;
- unsigned short type_1;
-} __attribute__((packed)) audrec_cmd_cfg;
-
-
-/*
- * Command to configure the recording parameters for RecType0(AAC/WAV) encoder
- */
-
-#define AUDREC_CMD_AREC0PARAM_CFG 0x0001
-#define AUDREC_CMD_AREC0PARAM_CFG_LEN \
- sizeof(audrec_cmd_arec0param_cfg)
-
-#define AUDREC_CMD_SAMP_RATE_INDX_8000 0x000B
-#define AUDREC_CMD_SAMP_RATE_INDX_11025 0x000A
-#define AUDREC_CMD_SAMP_RATE_INDX_12000 0x0009
-#define AUDREC_CMD_SAMP_RATE_INDX_16000 0x0008
-#define AUDREC_CMD_SAMP_RATE_INDX_22050 0x0007
-#define AUDREC_CMD_SAMP_RATE_INDX_24000 0x0006
-#define AUDREC_CMD_SAMP_RATE_INDX_32000 0x0005
-#define AUDREC_CMD_SAMP_RATE_INDX_44100 0x0004
-#define AUDREC_CMD_SAMP_RATE_INDX_48000 0x0003
-
-#define AUDREC_CMD_STEREO_MODE_MONO 0x0000
-#define AUDREC_CMD_STEREO_MODE_STEREO 0x0001
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short ptr_to_extpkt_buffer_msw;
- unsigned short ptr_to_extpkt_buffer_lsw;
- unsigned short buf_len;
- unsigned short samp_rate_index;
- unsigned short stereo_mode;
- unsigned short rec_quality;
-} __attribute__((packed)) audrec_cmd_arec0param_cfg;
-
-/*
- * Command to configure the recording parameters for RecType1(SBC) encoder
- */
-
-#define AUDREC_CMD_AREC1PARAM_CFG 0x0002
-#define AUDREC_CMD_AREC1PARAM_CFG_LEN \
- sizeof(audrec_cmd_arec1param_cfg)
-
-#define AUDREC_CMD_PARAM_BUF_BLOCKS_4 0x0000
-#define AUDREC_CMD_PARAM_BUF_BLOCKS_8 0x0001
-#define AUDREC_CMD_PARAM_BUF_BLOCKS_12 0x0002
-#define AUDREC_CMD_PARAM_BUF_BLOCKS_16 0x0003
-
-#define AUDREC_CMD_PARAM_BUF_SUB_BANDS_8 0x0010
-#define AUDREC_CMD_PARAM_BUF_MODE_MONO 0x0000
-#define AUDREC_CMD_PARAM_BUF_MODE_DUAL 0x0040
-#define AUDREC_CMD_PARAM_BUF_MODE_STEREO 0x0050
-#define AUDREC_CMD_PARAM_BUF_MODE_JSTEREO 0x0060
-#define AUDREC_CMD_PARAM_BUF_LOUDNESS 0x0000
-#define AUDREC_CMD_PARAM_BUF_SNR 0x0100
-#define AUDREC_CMD_PARAM_BUF_BASIC_VER 0x0000
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short ptr_to_extpkt_buffer_msw;
- unsigned short ptr_to_extpkt_buffer_lsw;
- unsigned short buf_len;
- unsigned short param_buf;
- unsigned short bit_rate_0;
- unsigned short bit_rate_1;
-} __attribute__((packed)) audrec_cmd_arec1param_cfg;
-
-
-/*
- * Commands on audRecUpBitStreamQueue
- */
-
-/*
- * Command to indicate the current packet read count
- */
-
-#define AUDREC_CMD_PACKET_EXT_PTR 0x0000
-#define AUDREC_CMD_PACKET_EXT_PTR_LEN \
- sizeof(audrec_cmd_packet_ext_ptr)
-
-#define AUDREC_CMD_TYPE_0 0x0000
-#define AUDREC_CMD_TYPE_1 0x0001
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short type;
- unsigned short curr_rec_count_msw;
- unsigned short curr_rec_count_lsw;
-} __attribute__((packed)) audrec_cmd_packet_ext_ptr;
-
-#endif
+++ /dev/null
-#ifndef QDSP5AUDRECMSGI_H
-#define QDSP5AUDRECMSGI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- A U D I O R E C O R D M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of messages
- that are sent by AUDREC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
- $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audrecmsg.h#3 $
-
-============================================================================*/
-
-/*
- * AUDRECTASK MESSAGES
- * AUDRECTASK uses audRecUpRlist to communicate with ARM
- * Location : MEMC
- * Buffer size : 4
- * No of buffers in a queue : 2
- */
-
-/*
- * Message to notify that config command is done
- */
-
-#define AUDREC_MSG_CMD_CFG_DONE_MSG 0x0002
-#define AUDREC_MSG_CMD_CFG_DONE_MSG_LEN \
- sizeof(audrec_msg_cmd_cfg_done_msg)
-
-
-#define AUDREC_MSG_CFG_DONE_TYPE_0_ENA 0x4000
-#define AUDREC_MSG_CFG_DONE_TYPE_0_DIS 0x0000
-
-#define AUDREC_MSG_CFG_DONE_TYPE_0_NO_UPDATE 0x0000
-#define AUDREC_MSG_CFG_DONE_TYPE_0_UPDATE 0x8000
-
-#define AUDREC_MSG_CFG_DONE_TYPE_1_ENA 0x4000
-#define AUDREC_MSG_CFG_DONE_TYPE_1_DIS 0x0000
-
-#define AUDREC_MSG_CFG_DONE_TYPE_1_NO_UPDATE 0x0000
-#define AUDREC_MSG_CFG_DONE_TYPE_1_UPDATE 0x8000
-
-typedef struct {
- unsigned short type_0;
- unsigned short type_1;
-} __attribute__((packed))audrec_msg_cmd_cfg_done_msg;
-
-
-/*
- * Message to notify arec0/1 cfg done and recording params revd by task
- */
-
-#define AUDREC_MSG_CMD_AREC_PARAM_CFG_DONE_MSG 0x0003
-#define AUDREC_MSG_CMD_AREC_PARAM_CFG_DONE_MSG_LEN \
- sizeof(audrec_msg_cmd_arec_param_cfg_done_msg)
-
-#define AUDREC_MSG_AREC_PARAM_TYPE_0 0x0000
-#define AUDREC_MSG_AREC_PARAM_TYPE_1 0x0001
-
-typedef struct {
- unsigned short type;
-} __attribute__((packed))audrec_msg_cmd_arec_param_cfg_done_msg;
-
-
-/*
- * Message to notify no more buffers are available in ext mem to DME
- */
-
-#define AUDREC_MSG_FATAL_ERR_MSG 0x0004
-#define AUDREC_MSG_FATAL_ERR_MSG_LEN \
- sizeof(audrec_msg_fatal_err_msg)
-
-#define AUDREC_MSG_FATAL_ERR_TYPE_0 0x0000
-#define AUDREC_MSG_FATAL_ERR_TYPE_1 0x0001
-
-typedef struct {
- unsigned short type;
-} __attribute__((packed))audrec_msg_fatal_err_msg;
-
-/*
- * Message to notify DME deliverd the encoded pkt to ext pkt buffer
- */
-
-#define AUDREC_MSG_PACKET_READY_MSG 0x0005
-#define AUDREC_MSG_PACKET_READY_MSG_LEN \
- sizeof(audrec_msg_packet_ready_msg)
-
-#define AUDREC_MSG_PACKET_READY_TYPE_0 0x0000
-#define AUDREC_MSG_PACKET_READY_TYPE_1 0x0001
-
-typedef struct {
- unsigned short type;
- unsigned short pkt_counter_msw;
- unsigned short pkt_counter_lsw;
- unsigned short pkt_read_cnt_msw;
- unsigned short pkt_read_cnt_lsw;
-} __attribute__((packed))audrec_msg_packet_ready_msg;
-
-#endif
+++ /dev/null
-#ifndef QDSP5VIDJPEGCMDI_H
-#define QDSP5VIDJPEGCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- J P E G I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by JPEG Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5jpegcmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-when who what, where, why
--------- --- ----------------------------------------------------------
-06/09/08 sv initial version
-===========================================================================*/
-
-/*
- * ARM to JPEG configuration commands are passed through the
- * uPJpegCfgCmdQueue
- */
-
-/*
- * Command to configure JPEG Encoder
- */
-
-#define JPEG_CMD_ENC_CFG 0x0000
-#define JPEG_CMD_ENC_CFG_LEN sizeof(jpeg_cmd_enc_cfg)
-
-#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_0 0x0000
-#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_90 0x0100
-#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_180 0x0200
-#define JPEG_CMD_ENC_PROCESS_CFG_OP_ROTATION_270 0x0300
-#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_M 0x0003
-#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H2V2 0x0000
-#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H2V1 0x0001
-#define JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H1V2 0x0002
-
-#define JPEG_CMD_IP_SIZE_CFG_LUMA_HEIGHT_M 0x0000FFFF
-#define JPEG_CMD_IP_SIZE_CFG_LUMA_WIDTH_M 0xFFFF0000
-#define JPEG_CMD_ENC_UPSAMP_IP_SIZE_CFG_ENA 0x0001
-#define JPEG_CMD_ENC_UPSAMP_IP_SIZE_CFG_DIS 0x0000
-
-#define JPEG_CMD_FRAG_SIZE_LUMA_HEIGHT_M 0xFFFF
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int process_cfg;
- unsigned int ip_size_cfg;
- unsigned int op_size_cfg;
- unsigned int frag_cfg;
- unsigned int frag_cfg_part[16];
-
- unsigned int part_num;
-
- unsigned int op_buf_0_cfg_part1;
- unsigned int op_buf_0_cfg_part2;
- unsigned int op_buf_1_cfg_part1;
- unsigned int op_buf_1_cfg_part2;
-
- unsigned int luma_qunt_table[32];
- unsigned int chroma_qunt_table[32];
-
- unsigned int upsamp_ip_size_cfg;
- unsigned int upsamp_ip_frame_off;
- unsigned int upsamp_pp_filter_coeff[64];
-} __attribute__((packed)) jpeg_cmd_enc_cfg;
-
-/*
- * Command to configure JPEG Decoder
- */
-
-#define JPEG_CMD_DEC_CFG 0x0001
-#define JPEG_CMD_DEC_CFG_LEN sizeof(jpeg_cmd_dec_cfg)
-
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_M 0x0001
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_H2V2 0x0000
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_H2V1 0x0001
-
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_8 0x000000
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_4 0x010000
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_2 0x020000
-#define JPEG_CMD_DEC_OP_DATA_FORMAT_SCALE_FACTOR_1 0x030000
-
-#define JPEG_CMD_DEC_IP_STREAM_BUF_CFG_PART3_NOT_FINAL 0x0000
-#define JPEG_CMD_DEC_IP_STREAM_BUF_CFG_PART3_FINAL 0x0001
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int img_dimension_cfg;
- unsigned int op_data_format;
- unsigned int restart_interval;
- unsigned int ip_buf_partition_num;
- unsigned int ip_stream_buf_cfg_part1;
- unsigned int ip_stream_buf_cfg_part2;
- unsigned int ip_stream_buf_cfg_part3;
- unsigned int op_stream_buf_0_cfg_part1;
- unsigned int op_stream_buf_0_cfg_part2;
- unsigned int op_stream_buf_0_cfg_part3;
- unsigned int op_stream_buf_1_cfg_part1;
- unsigned int op_stream_buf_1_cfg_part2;
- unsigned int op_stream_buf_1_cfg_part3;
- unsigned int luma_qunt_table_0_3;
- unsigned int luma_qunt_table_4_7;
- unsigned int luma_qunt_table_8_11;
- unsigned int luma_qunt_table_12_15;
- unsigned int luma_qunt_table_16_19;
- unsigned int luma_qunt_table_20_23;
- unsigned int luma_qunt_table_24_27;
- unsigned int luma_qunt_table_28_31;
- unsigned int luma_qunt_table_32_35;
- unsigned int luma_qunt_table_36_39;
- unsigned int luma_qunt_table_40_43;
- unsigned int luma_qunt_table_44_47;
- unsigned int luma_qunt_table_48_51;
- unsigned int luma_qunt_table_52_55;
- unsigned int luma_qunt_table_56_59;
- unsigned int luma_qunt_table_60_63;
- unsigned int chroma_qunt_table_0_3;
- unsigned int chroma_qunt_table_4_7;
- unsigned int chroma_qunt_table_8_11;
- unsigned int chroma_qunt_table_12_15;
- unsigned int chroma_qunt_table_16_19;
- unsigned int chroma_qunt_table_20_23;
- unsigned int chroma_qunt_table_24_27;
- unsigned int chroma_qunt_table_28_31;
- unsigned int chroma_qunt_table_32_35;
- unsigned int chroma_qunt_table_36_39;
- unsigned int chroma_qunt_table_40_43;
- unsigned int chroma_qunt_table_44_47;
- unsigned int chroma_qunt_table_48_51;
- unsigned int chroma_qunt_table_52_55;
- unsigned int chroma_qunt_table_56_59;
- unsigned int chroma_qunt_table_60_63;
- unsigned int luma_dc_hm_code_cnt_table_0_3;
- unsigned int luma_dc_hm_code_cnt_table_4_7;
- unsigned int luma_dc_hm_code_cnt_table_8_11;
- unsigned int luma_dc_hm_code_cnt_table_12_15;
- unsigned int luma_dc_hm_code_val_table_0_3;
- unsigned int luma_dc_hm_code_val_table_4_7;
- unsigned int luma_dc_hm_code_val_table_8_11;
- unsigned int chroma_dc_hm_code_cnt_table_0_3;
- unsigned int chroma_dc_hm_code_cnt_table_4_7;
- unsigned int chroma_dc_hm_code_cnt_table_8_11;
- unsigned int chroma_dc_hm_code_cnt_table_12_15;
- unsigned int chroma_dc_hm_code_val_table_0_3;
- unsigned int chroma_dc_hm_code_val_table_4_7;
- unsigned int chroma_dc_hm_code_val_table_8_11;
- unsigned int luma_ac_hm_code_cnt_table_0_3;
- unsigned int luma_ac_hm_code_cnt_table_4_7;
- unsigned int luma_ac_hm_code_cnt_table_8_11;
- unsigned int luma_ac_hm_code_cnt_table_12_15;
- unsigned int luma_ac_hm_code_val_table_0_3;
- unsigned int luma_ac_hm_code_val_table_4_7;
- unsigned int luma_ac_hm_code_val_table_8_11;
- unsigned int luma_ac_hm_code_val_table_12_15;
- unsigned int luma_ac_hm_code_val_table_16_19;
- unsigned int luma_ac_hm_code_val_table_20_23;
- unsigned int luma_ac_hm_code_val_table_24_27;
- unsigned int luma_ac_hm_code_val_table_28_31;
- unsigned int luma_ac_hm_code_val_table_32_35;
- unsigned int luma_ac_hm_code_val_table_36_39;
- unsigned int luma_ac_hm_code_val_table_40_43;
- unsigned int luma_ac_hm_code_val_table_44_47;
- unsigned int luma_ac_hm_code_val_table_48_51;
- unsigned int luma_ac_hm_code_val_table_52_55;
- unsigned int luma_ac_hm_code_val_table_56_59;
- unsigned int luma_ac_hm_code_val_table_60_63;
- unsigned int luma_ac_hm_code_val_table_64_67;
- unsigned int luma_ac_hm_code_val_table_68_71;
- unsigned int luma_ac_hm_code_val_table_72_75;
- unsigned int luma_ac_hm_code_val_table_76_79;
- unsigned int luma_ac_hm_code_val_table_80_83;
- unsigned int luma_ac_hm_code_val_table_84_87;
- unsigned int luma_ac_hm_code_val_table_88_91;
- unsigned int luma_ac_hm_code_val_table_92_95;
- unsigned int luma_ac_hm_code_val_table_96_99;
- unsigned int luma_ac_hm_code_val_table_100_103;
- unsigned int luma_ac_hm_code_val_table_104_107;
- unsigned int luma_ac_hm_code_val_table_108_111;
- unsigned int luma_ac_hm_code_val_table_112_115;
- unsigned int luma_ac_hm_code_val_table_116_119;
- unsigned int luma_ac_hm_code_val_table_120_123;
- unsigned int luma_ac_hm_code_val_table_124_127;
- unsigned int luma_ac_hm_code_val_table_128_131;
- unsigned int luma_ac_hm_code_val_table_132_135;
- unsigned int luma_ac_hm_code_val_table_136_139;
- unsigned int luma_ac_hm_code_val_table_140_143;
- unsigned int luma_ac_hm_code_val_table_144_147;
- unsigned int luma_ac_hm_code_val_table_148_151;
- unsigned int luma_ac_hm_code_val_table_152_155;
- unsigned int luma_ac_hm_code_val_table_156_159;
- unsigned int luma_ac_hm_code_val_table_160_161;
- unsigned int chroma_ac_hm_code_cnt_table_0_3;
- unsigned int chroma_ac_hm_code_cnt_table_4_7;
- unsigned int chroma_ac_hm_code_cnt_table_8_11;
- unsigned int chroma_ac_hm_code_cnt_table_12_15;
- unsigned int chroma_ac_hm_code_val_table_0_3;
- unsigned int chroma_ac_hm_code_val_table_4_7;
- unsigned int chroma_ac_hm_code_val_table_8_11;
- unsigned int chroma_ac_hm_code_val_table_12_15;
- unsigned int chroma_ac_hm_code_val_table_16_19;
- unsigned int chroma_ac_hm_code_val_table_20_23;
- unsigned int chroma_ac_hm_code_val_table_24_27;
- unsigned int chroma_ac_hm_code_val_table_28_31;
- unsigned int chroma_ac_hm_code_val_table_32_35;
- unsigned int chroma_ac_hm_code_val_table_36_39;
- unsigned int chroma_ac_hm_code_val_table_40_43;
- unsigned int chroma_ac_hm_code_val_table_44_47;
- unsigned int chroma_ac_hm_code_val_table_48_51;
- unsigned int chroma_ac_hm_code_val_table_52_55;
- unsigned int chroma_ac_hm_code_val_table_56_59;
- unsigned int chroma_ac_hm_code_val_table_60_63;
- unsigned int chroma_ac_hm_code_val_table_64_67;
- unsigned int chroma_ac_hm_code_val_table_68_71;
- unsigned int chroma_ac_hm_code_val_table_72_75;
- unsigned int chroma_ac_hm_code_val_table_76_79;
- unsigned int chroma_ac_hm_code_val_table_80_83;
- unsigned int chroma_ac_hm_code_val_table_84_87;
- unsigned int chroma_ac_hm_code_val_table_88_91;
- unsigned int chroma_ac_hm_code_val_table_92_95;
- unsigned int chroma_ac_hm_code_val_table_96_99;
- unsigned int chroma_ac_hm_code_val_table_100_103;
- unsigned int chroma_ac_hm_code_val_table_104_107;
- unsigned int chroma_ac_hm_code_val_table_108_111;
- unsigned int chroma_ac_hm_code_val_table_112_115;
- unsigned int chroma_ac_hm_code_val_table_116_119;
- unsigned int chroma_ac_hm_code_val_table_120_123;
- unsigned int chroma_ac_hm_code_val_table_124_127;
- unsigned int chroma_ac_hm_code_val_table_128_131;
- unsigned int chroma_ac_hm_code_val_table_132_135;
- unsigned int chroma_ac_hm_code_val_table_136_139;
- unsigned int chroma_ac_hm_code_val_table_140_143;
- unsigned int chroma_ac_hm_code_val_table_144_147;
- unsigned int chroma_ac_hm_code_val_table_148_151;
- unsigned int chroma_ac_hm_code_val_table_152_155;
- unsigned int chroma_ac_hm_code_val_table_156_159;
- unsigned int chroma_ac_hm_code_val_table_160_161;
-} __attribute__((packed)) jpeg_cmd_dec_cfg;
-
-
-/*
- * ARM to JPEG configuration commands are passed through the
- * uPJpegActionCmdQueue
- */
-
-/*
- * Command to start the encode process
- */
-
-#define JPEG_CMD_ENC_ENCODE 0x0000
-#define JPEG_CMD_ENC_ENCODE_LEN sizeof(jpeg_cmd_enc_encode)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) jpeg_cmd_enc_encode;
-
-
-/*
- * Command to transition from current state of encoder to IDLE state
- */
-
-#define JPEG_CMD_ENC_IDLE 0x0001
-#define JPEG_CMD_ENC_IDLE_LEN sizeof(jpeg_cmd_enc_idle)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) jpeg_cmd_enc_idle;
-
-
-/*
- * Command to inform the encoder that another buffer is ready
- */
-
-#define JPEG_CMD_ENC_OP_CONSUMED 0x0002
-#define JPEG_CMD_ENC_OP_CONSUMED_LEN sizeof(jpeg_cmd_enc_op_consumed)
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int op_buf_addr;
- unsigned int op_buf_size;
-} __attribute__((packed)) jpeg_cmd_enc_op_consumed;
-
-
-/*
- * Command to start the decoding process
- */
-
-#define JPEG_CMD_DEC_DECODE 0x0003
-#define JPEG_CMD_DEC_DECODE_LEN sizeof(jpeg_cmd_dec_decode)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) jpeg_cmd_dec_decode;
-
-
-/*
- * Command to transition from the current state of decoder to IDLE
- */
-
-#define JPEG_CMD_DEC_IDLE 0x0004
-#define JPEG_CMD_DEC_IDLE_LEN sizeof(jpeg_cmd_dec_idle)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) jpeg_cmd_dec_idle;
-
-
-/*
- * Command to inform that an op buffer is ready for use
- */
-
-#define JPEG_CMD_DEC_OP_CONSUMED 0x0005
-#define JPEG_CMD_DEC_OP_CONSUMED_LEN sizeof(jpeg_cmd_dec_op_consumed)
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int luma_op_buf_addr;
- unsigned int luma_op_buf_size;
- unsigned int chroma_op_buf_addr;
-} __attribute__((packed)) jpeg_cmd_dec_op_consumed;
-
-
-/*
- * Command to pass a new ip buffer to the jpeg decoder
- */
-
-#define JPEG_CMD_DEC_IP 0x0006
-#define JPEG_CMD_DEC_IP_LEN sizeof(jpeg_cmd_dec_ip_len)
-
-#define JPEG_CMD_EOI_INDICATOR_NOT_END 0x0000
-#define JPEG_CMD_EOI_INDICATOR_END 0x0001
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int ip_buf_addr;
- unsigned int ip_buf_size;
- unsigned int eoi_indicator;
-} __attribute__((packed)) jpeg_cmd_dec_ip;
-
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VIDJPEGMSGI_H
-#define QDSP5VIDJPEGMSGI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- J P E G I N T E R N A L M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of messages
- that are sent by JPEG Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5jpegmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-05/10/08 sv initial version
-===========================================================================*/
-
-/*
- * Messages from JPEG task to ARM through jpeguPMsgQueue
- */
-
-/*
- * Message is ACK for CMD_JPEGE_ENCODE cmd
- */
-
-#define JPEG_MSG_ENC_ENCODE_ACK 0x0000
-#define JPEG_MSG_ENC_ENCODE_ACK_LEN \
- sizeof(jpeg_msg_enc_encode_ack)
-
-typedef struct {
-} __attribute__((packed)) jpeg_msg_enc_encode_ack;
-
-
-/*
- * Message informs the up when op buffer is ready for consumption and
- * when encoding is complete or errors
- */
-
-#define JPEG_MSG_ENC_OP_PRODUCED 0x0001
-#define JPEG_MSG_ENC_OP_PRODUCED_LEN \
- sizeof(jpeg_msg_enc_op_produced)
-
-#define JPEG_MSGOP_OP_BUF_STATUS_ENC_DONE_PROGRESS 0x0000
-#define JPEG_MSGOP_OP_BUF_STATUS_ENC_DONE_COMPLETE 0x0001
-#define JPEG_MSGOP_OP_BUF_STATUS_ENC_ERR 0x10000
-
-typedef struct {
- unsigned int op_buf_addr;
- unsigned int op_buf_size;
- unsigned int op_buf_status;
-} __attribute__((packed)) jpeg_msg_enc_op_produced;
-
-
-/*
- * Message to ack CMD_JPEGE_IDLE
- */
-
-#define JPEG_MSG_ENC_IDLE_ACK 0x0002
-#define JPEG_MSG_ENC_IDLE_ACK_LEN sizeof(jpeg_msg_enc_idle_ack)
-
-
-typedef struct {
-} __attribute__ ((packed)) jpeg_msg_enc_idle_ack;
-
-
-/*
- * Message to indicate the illegal command
- */
-
-#define JPEG_MSG_ENC_ILLEGAL_COMMAND 0x0003
-#define JPEG_MSG_ENC_ILLEGAL_COMMAND_LEN \
- sizeof(jpeg_msg_enc_illegal_command)
-
-typedef struct {
- unsigned int status;
-} __attribute__((packed)) jpeg_msg_enc_illegal_command;
-
-
-/*
- * Message to ACK CMD_JPEGD_DECODE
- */
-
-#define JPEG_MSG_DEC_DECODE_ACK 0x0004
-#define JPEG_MSG_DEC_DECODE_ACK_LEN \
- sizeof(jpeg_msg_dec_decode_ack)
-
-
-typedef struct {
-} __attribute__((packed)) jpeg_msg_dec_decode_ack;
-
-
-/*
- * Message to inform up that an op buffer is ready for consumption and when
- * decoding is complete or an error occurs
- */
-
-#define JPEG_MSG_DEC_OP_PRODUCED 0x0005
-#define JPEG_MSG_DEC_OP_PRODUCED_LEN \
- sizeof(jpeg_msg_dec_op_produced)
-
-#define JPEG_MSG_DEC_OP_BUF_STATUS_PROGRESS 0x0000
-#define JPEG_MSG_DEC_OP_BUF_STATUS_DONE 0x0001
-
-typedef struct {
- unsigned int luma_op_buf_addr;
- unsigned int chroma_op_buf_addr;
- unsigned int num_mcus;
- unsigned int op_buf_status;
-} __attribute__((packed)) jpeg_msg_dec_op_produced;
-
-/*
- * Message to ack CMD_JPEGD_IDLE cmd
- */
-
-#define JPEG_MSG_DEC_IDLE_ACK 0x0006
-#define JPEG_MSG_DEC_IDLE_ACK_LEN sizeof(jpeg_msg_dec_idle_ack)
-
-
-typedef struct {
-} __attribute__((packed)) jpeg_msg_dec_idle_ack;
-
-
-/*
- * Message to indicate illegal cmd was received
- */
-
-#define JPEG_MSG_DEC_ILLEGAL_COMMAND 0x0007
-#define JPEG_MSG_DEC_ILLEGAL_COMMAND_LEN \
- sizeof(jpeg_msg_dec_illegal_command)
-
-
-typedef struct {
- unsigned int status;
-} __attribute__((packed)) jpeg_msg_dec_illegal_command;
-
-/*
- * Message to request up for the next segment of ip bit stream
- */
-
-#define JPEG_MSG_DEC_IP_REQUEST 0x0008
-#define JPEG_MSG_DEC_IP_REQUEST_LEN \
- sizeof(jpeg_msg_dec_ip_request)
-
-
-typedef struct {
-} __attribute__((packed)) jpeg_msg_dec_ip_request;
-
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5LPMCMDI_H
-#define QDSP5LPMCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- L P M I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by LPM Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5lpmcmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-06/12/08 sv initial version
-===========================================================================*/
-
-
-/*
- * Command to start LPM processing based on the config params
- */
-
-#define LPM_CMD_START 0x0000
-#define LPM_CMD_START_LEN sizeof(lpm_cmd_start)
-
-#define LPM_CMD_SPATIAL_FILTER_PART_OPMODE_0 0x00000000
-#define LPM_CMD_SPATIAL_FILTER_PART_OPMODE_1 0x00010000
-typedef struct {
- unsigned int cmd_id;
- unsigned int ip_data_cfg_part1;
- unsigned int ip_data_cfg_part2;
- unsigned int ip_data_cfg_part3;
- unsigned int ip_data_cfg_part4;
- unsigned int op_data_cfg_part1;
- unsigned int op_data_cfg_part2;
- unsigned int op_data_cfg_part3;
- unsigned int spatial_filter_part[32];
-} __attribute__((packed)) lpm_cmd_start;
-
-
-
-/*
- * Command to stop LPM processing
- */
-
-#define LPM_CMD_IDLE 0x0001
-#define LPM_CMD_IDLE_LEN sizeof(lpm_cmd_idle)
-
-typedef struct {
- unsigned int cmd_id;
-} __attribute__((packed)) lpm_cmd_idle;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5LPMMSGI_H
-#define QDSP5LPMMSGI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- L P M I N T E R N A L M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by LPM Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5lpmmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-06/12/08 sv initial version
-===========================================================================*/
-
-/*
- * Message to acknowledge CMD_LPM_IDLE command
- */
-
-#define LPM_MSG_IDLE_ACK 0x0000
-#define LPM_MSG_IDLE_ACK_LEN sizeof(lpm_msg_idle_ack)
-
-typedef struct {
-} __attribute__((packed)) lpm_msg_idle_ack;
-
-
-/*
- * Message to acknowledge CMD_LPM_START command
- */
-
-
-#define LPM_MSG_START_ACK 0x0001
-#define LPM_MSG_START_ACK_LEN sizeof(lpm_msg_start_ack)
-
-
-typedef struct {
-} __attribute__((packed)) lpm_msg_start_ack;
-
-
-/*
- * Message to notify the ARM that LPM processing is complete
- */
-
-#define LPM_MSG_DONE 0x0002
-#define LPM_MSG_DONE_LEN sizeof(lpm_msg_done)
-
-typedef struct {
-} __attribute__((packed)) lpm_msg_done;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VIDDECCMDI_H
-#define QDSP5VIDDECCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- V I D E O D E C O D E R I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by VIDDEC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vdeccmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-05/10/08 ac initial version
-===========================================================================*/
-
-
-/*
- * Command to inform VIDDEC that new subframe packet is ready
- */
-
-#define VIDDEC_CMD_SUBFRAME_PKT 0x0000
-#define VIDDEC_CMD_SUBFRAME_PKT_LEN \
- sizeof(viddec_cmd_subframe_pkt)
-
-#define VIDDEC_CMD_SF_INFO_1_DM_DMA_STATS_EXCHANGE_FLAG_DM 0x0000
-#define VIDDEC_CMD_SF_INFO_1_DM_DMA_STATS_EXCHANGE_FLAG_DMA 0x0001
-
-#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_CONTI 0x0000
-#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_FIRST 0x0001
-#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_LAST 0x0002
-#define VIDDEC_CMD_SF_INFO_0_SUBFRAME_FIRST_AND_LAST 0x0003
-
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_MPEG_4 0x0000
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_263_P0 0x0001
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_264 0x0002
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_H_263_p3 0x0003
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_RV9 0x0004
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_WMV9 0x0005
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_SMCDB 0x0006
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_QFRE 0x0007
-#define VIDDEC_CMD_CODEC_SELECTION_WORD_VLD 0x0008
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short packet_seq_number;
- unsigned short codec_instance_id;
- unsigned short subframe_packet_size_high;
- unsigned short subframe_packet_size_low;
- unsigned short subframe_packet_high;
- unsigned short subframe_packet_low;
- unsigned short subframe_packet_partition;
- unsigned short statistics_packet_size_high;
- unsigned short statistics_packet_size_low;
- unsigned short statistics_packet_high;
- unsigned short statistics_packet_low;
- unsigned short statistics_partition;
- unsigned short subframe_info_1;
- unsigned short subframe_info_0;
- unsigned short codec_selection_word;
- unsigned short num_mbs;
-} __attribute__((packed)) viddec_cmd_subframe_pkt;
-
-
-/*
- * Command to inform VIDDEC task that post processing is required for the frame
- */
-
-#define VIDDEC_CMD_PP_ENABLE 0x0001
-#define VIDDEC_CMD_PP_ENABLE_LEN \
- sizeof(viddec_cmd_pp_enable)
-
-#define VIDDEC_CMD_PP_INFO_0_DM_DMA_LS_EXCHANGE_FLAG_DM 0x0000
-#define VIDDEC_CMD_PP_INFO_0_DM_DMA_LS_EXCHANGE_FLAG_DMA 0x0001
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short packet_seq_num;
- unsigned short codec_instance_id;
- unsigned short postproc_info_0;
- unsigned short codec_selection_word;
- unsigned short pp_output_addr_high;
- unsigned short pp_output_addr_low;
- unsigned short postproc_info_1;
- unsigned short load_sharing_packet_size_high;
- unsigned short load_sharing_packet_size_low;
- unsigned short load_sharing_packet_high;
- unsigned short load_sharing_packet_low;
- unsigned short load_sharing_partition;
- unsigned short pp_param_0;
- unsigned short pp_param_1;
- unsigned short pp_param_2;
- unsigned short pp_param_3;
-} __attribute__((packed)) viddec_cmd_pp_enable;
-
-
-/*
- * FRAME Header Packet : It is at the start of new frame
- */
-
-#define VIDDEC_CMD_FRAME_HEADER_PACKET 0x0002
-#define VIDDEC_CMD_FRAME_HEADER_PACKET_LEN \
- sizeof(viddec_cmd_frame_header_packet)
-
-#define VIDDEC_CMD_FRAME_INFO_0_ERROR_SKIP 0x0000
-#define VIDDEC_CMD_FRAME_INFO_0_ERROR_BLACK 0x0800
-
-typedef struct {
- unsigned short packet_id;
- unsigned short x_dimension;
- unsigned short y_dimension;
- unsigned short line_width;
- unsigned short frame_info_0;
- unsigned short frame_buffer_0_high;
- unsigned short frame_buffer_0_low;
- unsigned short frame_buffer_1_high;
- unsigned short frame_buffer_1_low;
- unsigned short frame_buffer_2_high;
- unsigned short frame_buffer_2_low;
- unsigned short frame_buffer_3_high;
- unsigned short frame_buffer_3_low;
- unsigned short frame_buffer_4_high;
- unsigned short frame_buffer_4_low;
- unsigned short frame_buffer_5_high;
- unsigned short frame_buffer_5_low;
- unsigned short frame_buffer_6_high;
- unsigned short frame_buffer_6_low;
- unsigned short frame_buffer_7_high;
- unsigned short frame_buffer_7_low;
- unsigned short frame_buffer_8_high;
- unsigned short frame_buffer_8_low;
- unsigned short frame_buffer_9_high;
- unsigned short frame_buffer_9_low;
- unsigned short frame_buffer_10_high;
- unsigned short frame_buffer_10_low;
- unsigned short frame_buffer_11_high;
- unsigned short frame_buffer_11_low;
- unsigned short frame_buffer_12_high;
- unsigned short frame_buffer_12_low;
- unsigned short frame_buffer_13_high;
- unsigned short frame_buffer_13_low;
- unsigned short frame_buffer_14_high;
- unsigned short frame_buffer_14_low;
- unsigned short frame_buffer_15_high;
- unsigned short frame_buffer_15_low;
- unsigned short output_frame_buffer_high;
- unsigned short output_frame_buffer_low;
- unsigned short end_of_packet_marker;
-} __attribute__((packed)) viddec_cmd_frame_header_packet;
-
-
-/*
- * SLICE HEADER PACKET
- * I-Slice and P-Slice
- */
-
-#define VIDDEC_CMD_SLICE_HEADER_PKT_ISLICE 0x0003
-#define VIDDEC_CMD_SLICE_HEADER_PKT_ISLICE_LEN \
- sizeof(viddec_cmd_slice_header_pkt_islice)
-
-#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_PSLICE 0x0000
-#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_BSLICE 0x0100
-#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_ISLICE 0x0200
-#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_SPSLICE 0x0300
-#define VIDDEC_CMD_ISLICE_INFO_1_MOD_SLICE_TYPE_SISLICE 0x0400
-#define VIDDEC_CMD_ISLICE_INFO_1_NOPADDING 0x0000
-#define VIDDEC_CMD_ISLICE_INFO_1_PADDING 0x0800
-
-#define VIDDEC_CMD_ISLICE_EOP_MARKER 0x7FFF
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short packet_id;
- unsigned short slice_info_0;
- unsigned short slice_info_1;
- unsigned short slice_info_2;
- unsigned short num_bytes_in_rbsp_high;
- unsigned short num_bytes_in_rbsp_low;
- unsigned short num_bytes_in_rbsp_consumed;
- unsigned short end_of_packet_marker;
-} __attribute__((packed)) viddec_cmd_slice_header_pkt_islice;
-
-
-#define VIDDEC_CMD_SLICE_HEADER_PKT_PSLICE 0x0003
-#define VIDDEC_CMD_SLICE_HEADER_PKT_PSLICE_LEN \
- sizeof(viddec_cmd_slice_header_pkt_pslice)
-
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short packet_id;
- unsigned short slice_info_0;
- unsigned short slice_info_1;
- unsigned short slice_info_2;
- unsigned short slice_info_3;
- unsigned short refidx_l0_map_tab_info_0;
- unsigned short refidx_l0_map_tab_info_1;
- unsigned short refidx_l0_map_tab_info_2;
- unsigned short refidx_l0_map_tab_info_3;
- unsigned short num_bytes_in_rbsp_high;
- unsigned short num_bytes_in_rbsp_low;
- unsigned short num_bytes_in_rbsp_consumed;
- unsigned short end_of_packet_marker;
-} __attribute__((packed)) viddec_cmd_slice_header_pkt_pslice;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VIDDECMSGI_H
-#define QDSP5VIDDECMSGI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- V I D E O D E C O D E R I N T E R N A L M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of messages
- that are sent by VIDDEC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vdecmsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-05/10/08 ac initial version
-===========================================================================*/
-
-/*
- * Message to inform ARM which VDEC_SUBFRAME_PKT_CMD processed by VIDDEC TASK
- */
-
-#define VIDDEC_MSG_SUBF_DONE 0x0000
-#define VIDDEC_MSG_SUBF_DONE_LEN \
- sizeof(viddec_msg_subf_done)
-
-typedef struct {
- unsigned short packet_seq_number;
- unsigned short codec_instance_id;
-} __attribute__((packed)) viddec_msg_subf_done;
-
-
-/*
- * Message to inform ARM one frame has been decoded
- */
-
-#define VIDDEC_MSG_FRAME_DONE 0x0001
-#define VIDDEC_MSG_FRAME_DONE_LEN \
- sizeof(viddec_msg_frame_done)
-
-typedef struct {
- unsigned short packet_seq_number;
- unsigned short codec_instance_id;
-} __attribute__((packed)) viddec_msg_frame_done;
-
-
-/*
- * Message to inform ARM that post processing frame has been decoded
- */
-
-#define VIDDEC_MSG_PP_ENABLE_CMD_DONE 0x0002
-#define VIDDEC_MSG_PP_ENABLE_CMD_DONE_LEN \
- sizeof(viddec_msg_pp_enable_cmd_done)
-
-typedef struct {
- unsigned short packet_seq_number;
- unsigned short codec_instance_id;
-} __attribute__((packed)) viddec_msg_pp_enable_cmd_done;
-
-
-/*
- * Message to inform ARM that one post processing frame has been decoded
- */
-
-
-#define VIDDEC_MSG_PP_FRAME_DONE 0x0003
-#define VIDDEC_MSG_PP_FRAME_DONE_LEN \
- sizeof(viddec_msg_pp_frame_done)
-
-#define VIDDEC_MSG_DISP_WORTHY_DISP 0x0000
-#define VIDDEC_MSG_DISP_WORTHY_DISP_NONE 0xFFFF
-
-
-typedef struct {
- unsigned short packet_seq_number;
- unsigned short codec_instance_id;
- unsigned short display_worthy;
-} __attribute__((packed)) viddec_msg_pp_frame_done;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VIDENCCMDI_H
-#define QDSP5VIDENCCMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- V I D E O E N C O D E R I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by VIDENC Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 2008 by QUALCOMM, Incorporated.
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-09/25/08 umeshp initial version
-===========================================================================*/
-
- #define VIDENC_CMD_CFG 0x0000
- #define VIDENC_CMD_ACTIVE 0x0001
- #define VIDENC_CMD_IDLE 0x0002
- #define VIDENC_CMD_FRAME_START 0x0003
- #define VIDENC_CMD_STATUS_QUERY 0x0004
- #define VIDENC_CMD_RC_CFG 0x0005
- #define VIDENC_CMD_DIS_CFG 0x0006
- #define VIDENC_CMD_DIS 0x0007
- #define VIDENC_CMD_INTRA_REFRESH 0x0008
- #define VIDENC_CMD_DIGITAL_ZOOM 0x0009
-
-
-/*
- * Command to pass the frame message information to VIDENC
- */
-
-
-#define VIDENC_CMD_FRAME_START_LEN \
- sizeof(videnc_cmd_frame_start)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short frame_info;
- unsigned short frame_rho_budget_word_high;
- unsigned short frame_rho_budget_word_low;
- unsigned short input_luma_addr_high;
- unsigned short input_luma_addr_low;
- unsigned short input_chroma_addr_high;
- unsigned short input_chroma_addr_low;
- unsigned short ref_vop_buf_ptr_high;
- unsigned short ref_vop_buf_ptr_low;
- unsigned short enc_pkt_buf_ptr_high;
- unsigned short enc_pkt_buf_ptr_low;
- unsigned short enc_pkt_buf_size_high;
- unsigned short enc_pkt_buf_size_low;
- unsigned short unfilt_recon_vop_buf_ptr_high;
- unsigned short unfilt_recon_vop_buf_ptr_low;
- unsigned short filt_recon_vop_buf_ptr_high;
- unsigned short filt_recon_vop_buf_ptr_low;
-} __attribute__((packed)) videnc_cmd_frame_start;
-
-/*
- * Command to pass the frame-level digital stabilization parameters to VIDENC
- */
-
-
-#define VIDENC_CMD_DIS_LEN \
- sizeof(videnc_cmd_dis)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short vfe_out_prev_luma_addr_high;
- unsigned short vfe_out_prev_luma_addr_low;
- unsigned short stabilization_info;
-} __attribute__((packed)) videnc_cmd_dis;
-
-/*
- * Command to pass the codec related parameters to VIDENC
- */
-
-
-#define VIDENC_CMD_CFG_LEN \
- sizeof(videnc_cmd_cfg)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short cfg_info_0;
- unsigned short cfg_info_1;
- unsigned short four_mv_threshold;
- unsigned short ise_fse_mv_cost_fac;
- unsigned short venc_frame_dim;
- unsigned short venc_DM_partition;
-} __attribute__((packed)) videnc_cmd_cfg;
-
-/*
- * Command to start the video encoding
- */
-
-
-#define VIDENC_CMD_ACTIVE_LEN \
- sizeof(videnc_cmd_active)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) videnc_cmd_active;
-
-/*
- * Command to stop the video encoding
- */
-
-
-#define VIDENC_CMD_IDLE_LEN \
- sizeof(videnc_cmd_idle)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) videnc_cmd_idle;
-
-/*
- * Command to query staus of VIDENC
- */
-
-
-#define VIDENC_CMD_STATUS_QUERY_LEN \
- sizeof(videnc_cmd_status_query)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) videnc_cmd_status_query;
-
-/*
- * Command to set rate control for a frame
- */
-
-
-#define VIDENC_CMD_RC_CFG_LEN \
- sizeof(videnc_cmd_rc_cfg)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short max_frame_qp_delta;
- unsigned short max_min_frame_qp;
-} __attribute__((packed)) videnc_cmd_rc_cfg;
-
-/*
- * Command to set intra-refreshing
- */
-
-
-#define VIDENC_CMD_INTRA_REFRESH_LEN \
- sizeof(videnc_cmd_intra_refresh)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short num_mb_refresh;
- unsigned short mb_index[15];
-} __attribute__((packed)) videnc_cmd_intra_refresh;
-
-/*
- * Command to pass digital zoom information to the VIDENC
- */
-#define VIDENC_CMD_DIGITAL_ZOOM_LEN \
- sizeof(videnc_cmd_digital_zoom)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short digital_zoom_en;
- unsigned short luma_frame_shift_X;
- unsigned short luma_frame_shift_Y;
- unsigned short up_ip_luma_rows;
- unsigned short up_ip_luma_cols;
- unsigned short up_ip_chroma_rows;
- unsigned short up_ip_chroma_cols;
- unsigned short luma_ph_incr_V_low;
- unsigned short luma_ph_incr_V_high;
- unsigned short luma_ph_incr_H_low;
- unsigned short luma_ph_incr_H_high;
- unsigned short chroma_ph_incr_V_low;
- unsigned short chroma_ph_incr_V_high;
- unsigned short chroma_ph_incr_H_low;
- unsigned short chroma_ph_incr_H_high;
-} __attribute__((packed)) videnc_cmd_digital_zoom;
-
-/*
- * Command to configure digital stabilization parameters
- */
-
-#define VIDENC_CMD_DIS_CFG_LEN \
- sizeof(videnc_cmd_dis_cfg)
-
-typedef struct {
- unsigned short cmd_id;
- unsigned short image_stab_subf_start_row_col;
- unsigned short image_stab_subf_dim;
- unsigned short image_stab_info_0;
-} __attribute__((packed)) videnc_cmd_dis_cfg;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VFECMDI_H
-#define QDSP5VFECMDI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- V F E I N T E R N A L C O M M A N D S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are accepted by VFE Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vfecmdi.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-06/12/08 sv initial version
-===========================================================================*/
-
-/******************************************************************************
- * Commands through vfeCommandScaleQueue
- *****************************************************************************/
-
-/*
- * Command to program scaler for op1 . max op of scaler is VGA
- */
-
-
-#define VFE_CMD_SCALE_OP1_CFG 0x0000
-#define VFE_CMD_SCALE_OP1_CFG_LEN \
- sizeof(vfe_cmd_scale_op1_cfg)
-
-#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_Y_STANDARD 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_Y_CASCADED 0x0001
-#define VFE_CMD_SCALE_OP1_SEL_H_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_H_Y_SCALER_ENA 0x0002
-#define VFE_CMD_SCALE_OP1_SEL_H_PP_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_H_PP_Y_SCALER_ENA 0x0004
-#define VFE_CMD_SCALE_OP1_SEL_V_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_V_Y_SCALER_ENA 0x0008
-#define VFE_CMD_SCALE_OP1_SEL_V_PP_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_V_PP_Y_SCALER_ENA 0x0010
-#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_CBCR_STANDARD 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_IP_SEL_CBCR_CASCADED 0x0020
-#define VFE_CMD_SCALE_OP1_SEL_H_CBCR_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_H_CBCR_SCALER_ENA 0x0040
-#define VFE_CMD_SCALE_OP1_SEL_V_CBCR_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP1_SEL_V_CBCR_SCALER_ENA 0x0080
-
-#define VFE_CMD_OP1_PP_Y_SCALER_CFG_PART1_DONT_LOAD_COEFFS 0x80000000
-#define VFE_CMD_OP1_PP_Y_SCALER_CFG_PART1_LOAD_COEFFS 0x80000000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int scale_op1_sel;
- unsigned int y_scaler_cfg_part1;
- unsigned int y_scaler_cfg_part2;
- unsigned int cbcr_scaler_cfg_part1;
- unsigned int cbcr_scaler_cfg_part2;
- unsigned int cbcr_scaler_cfg_part3;
- unsigned int pp_y_scaler_cfg_part1;
- unsigned int pp_y_scaler_cfg_part2;
- unsigned int y_scaler_v_coeff_bank_part1[16];
- unsigned int y_scaler_v_coeff_bank_part2[16];
- unsigned int y_scaler_h_coeff_bank_part1[16];
- unsigned int y_scaler_h_coeff_bank_part2[16];
-} __attribute__((packed)) vfe_cmd_scale_op1_cfg;
-
-
-/*
- * Command to program scaler for op2
- */
-
-#define VFE_CMD_SCALE_OP2_CFG 0x0001
-#define VFE_CMD_SCALE_OP2_CFG_LEN \
- sizeof(vfe_cmd_scale_op2_cfg)
-
-#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_Y_STANDARD 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_Y_CASCADED 0x0001
-#define VFE_CMD_SCALE_OP2_SEL_H_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_H_Y_SCALER_ENA 0x0002
-#define VFE_CMD_SCALE_OP2_SEL_H_PP_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_H_PP_Y_SCALER_ENA 0x0004
-#define VFE_CMD_SCALE_OP2_SEL_V_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_V_Y_SCALER_ENA 0x0008
-#define VFE_CMD_SCALE_OP2_SEL_V_PP_Y_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_V_PP_Y_SCALER_ENA 0x0010
-#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_CBCR_STANDARD 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_IP_SEL_CBCR_CASCADED 0x0020
-#define VFE_CMD_SCALE_OP2_SEL_H_CBCR_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_H_CBCR_SCALER_ENA 0x0040
-#define VFE_CMD_SCALE_OP2_SEL_V_CBCR_SCALER_DIS 0x0000
-#define VFE_CMD_SCALE_OP2_SEL_V_CBCR_SCALER_ENA 0x0080
-
-#define VFE_CMD_OP2_PP_Y_SCALER_CFG_PART1_DONT_LOAD_COEFFS 0x80000000
-#define VFE_CMD_OP2_PP_Y_SCALER_CFG_PART1_LOAD_COEFFS 0x80000000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int scale_op2_sel;
- unsigned int y_scaler_cfg_part1;
- unsigned int y_scaler_cfg_part2;
- unsigned int cbcr_scaler_cfg_part1;
- unsigned int cbcr_scaler_cfg_part2;
- unsigned int cbcr_scaler_cfg_part3;
- unsigned int pp_y_scaler_cfg_part1;
- unsigned int pp_y_scaler_cfg_part2;
- unsigned int y_scaler_v_coeff_bank_part1[16];
- unsigned int y_scaler_v_coeff_bank_part2[16];
- unsigned int y_scaler_h_coeff_bank_part1[16];
- unsigned int y_scaler_h_coeff_bank_part2[16];
-} __attribute__((packed)) vfe_cmd_scale_op2_cfg;
-
-
-/******************************************************************************
- * Commands through vfeCommandTableQueue
- *****************************************************************************/
-
-/*
- * Command to program the AXI ip paths
- */
-
-#define VFE_CMD_AXI_IP_CFG 0x0000
-#define VFE_CMD_AXI_IP_CFG_LEN sizeof(vfe_cmd_axi_ip_cfg)
-
-#define VFE_CMD_IP_SEL_IP_FORMAT_8 0x0000
-#define VFE_CMD_IP_SEL_IP_FORMAT_10 0x0001
-#define VFE_CMD_IP_SEL_IP_FORMAT_12 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int ip_sel;
- unsigned int ip_cfg_part1;
- unsigned int ip_cfg_part2;
- unsigned int ip_unpack_cfg_part[6];
- unsigned int ip_buf_addr[8];
-} __attribute__ ((packed)) vfe_cmd_axi_ip_cfg;
-
-
-/*
- * Command to program axi op paths
- */
-
-#define VFE_CMD_AXI_OP_CFG 0x0001
-#define VFE_CMD_AXI_OP_CFG_LEN sizeof(vfe_cmd_axi_op_cfg)
-
-#define VFE_CMD_OP_SEL_OP1 0x0000
-#define VFE_CMD_OP_SEL_OP2 0x0001
-#define VFE_CMD_OP_SEL_OP1_OP2 0x0002
-#define VFE_CMD_OP_SEL_CTOA 0x0003
-#define VFE_CMD_OP_SEL_CTOA_OP1 0x0004
-#define VFE_CMD_OP_SEL_CTOA_OP2 0x0005
-#define VFE_CMD_OP_SEL_OP_FORMAT_8 0x0000
-#define VFE_CMD_OP_SEL_OP_FORMAT_10 0x0008
-#define VFE_CMD_OP_SEL_OP_FORMAT_12 0x0010
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int op_sel;
- unsigned int op1_y_cfg_part1;
- unsigned int op1_y_cfg_part2;
- unsigned int op1_cbcr_cfg_part1;
- unsigned int op1_cbcr_cfg_part2;
- unsigned int op2_y_cfg_part1;
- unsigned int op2_y_cfg_part2;
- unsigned int op2_cbcr_cfg_part1;
- unsigned int op2_cbcr_cfg_part2;
- unsigned int op1_buf1_addr[16];
- unsigned int op2_buf1_addr[16];
-} __attribute__((packed)) vfe_cmd_axi_op_cfg;
-
-
-
-
-/*
- * Command to program the roll off correction module
- */
-
-#define VFE_CMD_ROLLOFF_CFG 0x0002
-#define VFE_CMD_ROLLOFF_CFG_LEN \
- sizeof(vfe_cmd_rolloff_cfg)
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int correction_opt_center_pos;
- unsigned int radius_square_entry[32];
- unsigned int red_table_entry[32];
- unsigned int green_table_entry[32];
- unsigned int blue_table_entry[32];
-} __attribute__((packed)) vfe_cmd_rolloff_cfg;
-
-/*
- * Command to program RGB gamma table
- */
-
-#define VFE_CMD_RGB_GAMMA_CFG 0x0003
-#define VFE_CMD_RGB_GAMMA_CFG_LEN \
- sizeof(vfe_cmd_rgb_gamma_cfg)
-
-#define VFE_CMD_RGB_GAMMA_SEL_LINEAR 0x0000
-#define VFE_CMD_RGB_GAMMA_SEL_PW_LINEAR 0x0001
-typedef struct {
- unsigned int cmd_id;
- unsigned int rgb_gamma_sel;
- unsigned int rgb_gamma_entry[256];
-} __attribute__((packed)) vfe_cmd_rgb_gamma_cfg;
-
-
-/*
- * Command to program luma gamma table for the noise reduction path
- */
-
-#define VFE_CMD_Y_GAMMA_CFG 0x0004
-#define VFE_CMD_Y_GAMMA_CFG_LEN \
- sizeof(vfe_cmd_y_gamma_cfg)
-
-#define VFE_CMD_Y_GAMMA_SEL_LINEAR 0x0000
-#define VFE_CMD_Y_GAMMA_SEL_PW_LINEAR 0x0001
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int y_gamma_sel;
- unsigned int y_gamma_entry[256];
-} __attribute__((packed)) vfe_cmd_y_gamma_cfg;
-
-
-
-/******************************************************************************
- * Commands through vfeCommandQueue
- *****************************************************************************/
-
-/*
- * Command to reset the VFE to a known good state.All previously programmed
- * Params will be lost
- */
-
-
-#define VFE_CMD_RESET 0x0000
-#define VFE_CMD_RESET_LEN sizeof(vfe_cmd_reset)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) vfe_cmd_reset;
-
-
-/*
- * Command to start VFE processing based on the config params
- */
-
-
-#define VFE_CMD_START 0x0001
-#define VFE_CMD_START_LEN sizeof(vfe_cmd_start)
-
-#define VFE_CMD_STARTUP_PARAMS_SRC_CAMIF 0x0000
-#define VFE_CMD_STARTUP_PARAMS_SRC_AXI 0x0001
-#define VFE_CMD_STARTUP_PARAMS_MODE_CONTINUOUS 0x0000
-#define VFE_CMD_STARTUP_PARAMS_MODE_SNAPSHOT 0x0002
-
-#define VFE_CMD_IMAGE_PL_BLACK_LVL_CORR_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_BLACK_LVL_CORR_ENA 0x0001
-#define VFE_CMD_IMAGE_PL_ROLLOFF_CORR_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_ROLLOFF_CORR_ENA 0x0002
-#define VFE_CMD_IMAGE_PL_WHITE_BAL_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_WHITE_BAL_ENA 0x0004
-#define VFE_CMD_IMAGE_PL_RGB_GAMMA_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_RGB_GAMMA_ENA 0x0008
-#define VFE_CMD_IMAGE_PL_LUMA_NOISE_RED_PATH_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_LUMA_NOISE_RED_PATH_ENA 0x0010
-#define VFE_CMD_IMAGE_PL_ADP_FILTER_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_ADP_FILTER_ENA 0x0020
-#define VFE_CMD_IMAGE_PL_CHROMA_SAMP_DIS 0x0000
-#define VFE_CMD_IMAGE_PL_CHROMA_SAMP_ENA 0x0040
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int startup_params;
- unsigned int image_pipeline;
- unsigned int frame_dimension;
-} __attribute__((packed)) vfe_cmd_start;
-
-
-/*
- * Command to halt all processing
- */
-
-#define VFE_CMD_STOP 0x0002
-#define VFE_CMD_STOP_LEN sizeof(vfe_cmd_stop)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) vfe_cmd_stop;
-
-
-/*
- * Command to commit the params that have been programmed to take
- * effect on the next frame
- */
-
-#define VFE_CMD_UPDATE 0x0003
-#define VFE_CMD_UPDATE_LEN sizeof(vfe_cmd_update)
-
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) vfe_cmd_update;
-
-
-/*
- * Command to program CAMIF module
- */
-
-#define VFE_CMD_CAMIF_CFG 0x0004
-#define VFE_CMD_CAMIF_CFG_LEN sizeof(vfe_cmd_camif_cfg)
-
-#define VFE_CMD_CFG_VSYNC_SYNC_EDGE_HIGH 0x0000
-#define VFE_CMD_CFG_VSYNC_SYNC_EDGE_LOW 0x0002
-#define VFE_CMD_CFG_HSYNC_SYNC_EDGE_HIGH 0x0000
-#define VFE_CMD_CFG_HSYNC_SYNC_EDGE_LOW 0x0004
-#define VFE_CMD_CFG_SYNC_MODE_APS 0x0000
-#define VFE_CMD_CFG_SYNC_MODE_EFS 0X0008
-#define VFE_CMD_CFG_SYNC_MODE_ELS 0x0010
-#define VFE_CMD_CFG_SYNC_MODE_RVD 0x0018
-#define VFE_CMD_CFG_VFE_SUBSAMP_EN_DIS 0x0000
-#define VFE_CMD_CFG_VFE_SUBSAMP_EN_ENA 0x0020
-#define VFE_CMD_CFG_BUS_SUBSAMP_EN_DIS 0x0000
-#define VFE_CMD_CFG_BUS_SUBSAMP_EN_ENA 0x0080
-#define VFE_CMD_CFG_IRQ_SUBSAMP_EN_DIS 0x0000
-#define VFE_CMD_CFG_IRQ_SUBSAMP_EN_ENA 0x0800
-
-#define VFE_CMD_SUBSAMP2_CFG_PIXEL_SKIP_16 0x0000
-#define VFE_CMD_SUBSAMP2_CFG_PIXEL_SKIP_12 0x0010
-
-#define VFE_CMD_EPOCH_IRQ_1_DIS 0x0000
-#define VFE_CMD_EPOCH_IRQ_1_ENA 0x4000
-#define VFE_CMD_EPOCH_IRQ_2_DIS 0x0000
-#define VFE_CMD_EPOCH_IRQ_2_ENA 0x8000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int cfg;
- unsigned int efs_cfg;
- unsigned int frame_cfg;
- unsigned int window_width_cfg;
- unsigned int window_height_cfg;
- unsigned int subsamp1_cfg;
- unsigned int subsamp2_cfg;
- unsigned int epoch_irq;
-} __attribute__((packed)) vfe_cmd_camif_cfg;
-
-
-
-/*
- * Command to program the black level module
- */
-
-#define VFE_CMD_BLACK_LVL_CFG 0x0005
-#define VFE_CMD_BLACK_LVL_CFG_LEN sizeof(vfe_cmd_black_lvl_cfg)
-
-#define VFE_CMD_BL_SEL_MANUAL 0x0000
-#define VFE_CMD_BL_SEL_AUTO 0x0001
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int black_lvl_sel;
- unsigned int cfg_part[3];
-} __attribute__((packed)) vfe_cmd_black_lvl_cfg;
-
-
-/*
- * Command to program the active region by cropping the region of interest
- */
-
-#define VFE_CMD_ACTIVE_REGION_CFG 0x0006
-#define VFE_CMD_ACTIVE_REGION_CFG_LEN \
- sizeof(vfe_cmd_active_region_cfg)
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int cfg_part1;
- unsigned int cfg_part2;
-} __attribute__((packed)) vfe_cmd_active_region_cfg;
-
-
-
-/*
- * Command to program the defective pixel correction(DPC) ,
- * adaptive bayer filter (ABF) and demosaic modules
- */
-
-#define VFE_CMD_DEMOSAIC_CFG 0x0007
-#define VFE_CMD_DEMOSAIC_CFG_LEN sizeof(vfe_cmd_demosaic_cfg)
-
-#define VFE_CMD_DEMOSAIC_PART1_ABF_EN_DIS 0x0000
-#define VFE_CMD_DEMOSAIC_PART1_ABF_EN_ENA 0x0001
-#define VFE_CMD_DEMOSAIC_PART1_DPC_EN_DIS 0x0000
-#define VFE_CMD_DEMOSAIC_PART1_DPC_EN_ENA 0x0002
-#define VFE_CMD_DEMOSAIC_PART1_FORCE_ABF_OFF 0x0000
-#define VFE_CMD_DEMOSAIC_PART1_FORCE_ABF_ON 0x0004
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1 0x00000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_2 0x10000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_4 0x20000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_8 0x30000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_2 0x50000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_4 0x60000000
-#define VFE_CMD_DEMOSAIC_PART1_SLOPE_SHIFT_1_8 0x70000000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int demosaic_part1;
- unsigned int demosaic_part2;
- unsigned int demosaic_part3;
- unsigned int demosaic_part4;
- unsigned int demosaic_part5;
-} __attribute__((packed)) vfe_cmd_demosaic_cfg;
-
-
-/*
- * Command to program the ip format
- */
-
-#define VFE_CMD_IP_FORMAT_CFG 0x0008
-#define VFE_CMD_IP_FORMAT_CFG_LEN \
- sizeof(vfe_cmd_ip_format_cfg)
-
-#define VFE_CMD_IP_FORMAT_SEL_RGRG 0x0000
-#define VFE_CMD_IP_FORMAT_SEL_GRGR 0x0001
-#define VFE_CMD_IP_FORMAT_SEL_BGBG 0x0002
-#define VFE_CMD_IP_FORMAT_SEL_GBGB 0x0003
-#define VFE_CMD_IP_FORMAT_SEL_YCBYCR 0x0004
-#define VFE_CMD_IP_FORMAT_SEL_YCRYCB 0x0005
-#define VFE_CMD_IP_FORMAT_SEL_CBYCRY 0x0006
-#define VFE_CMD_IP_FORMAT_SEL_CRYCBY 0x0007
-#define VFE_CMD_IP_FORMAT_SEL_NO_CHROMA 0x0000
-#define VFE_CMD_IP_FORMAT_SEL_CHROMA 0x0008
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int ip_format_sel;
- unsigned int balance_gains_part1;
- unsigned int balance_gains_part2;
-} __attribute__((packed)) vfe_cmd_ip_format_cfg;
-
-
-
-/*
- * Command to program max and min allowed op values
- */
-
-#define VFE_CMD_OP_CLAMP_CFG 0x0009
-#define VFE_CMD_OP_CLAMP_CFG_LEN \
- sizeof(vfe_cmd_op_clamp_cfg)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int op_clamp_max;
- unsigned int op_clamp_min;
-} __attribute__((packed)) vfe_cmd_op_clamp_cfg;
-
-
-/*
- * Command to program chroma sub sample module
- */
-
-#define VFE_CMD_CHROMA_SUBSAMPLE_CFG 0x000A
-#define VFE_CMD_CHROMA_SUBSAMPLE_CFG_LEN \
- sizeof(vfe_cmd_chroma_subsample_cfg)
-
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_INTERESTIAL_SAMPS 0x0000
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_COSITED_SAMPS 0x0001
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_INTERESTIAL_SAMPS 0x0000
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_COSITED_SAMPS 0x0002
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_SUBSAMP_DIS 0x0000
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_H_SUBSAMP_ENA 0x0004
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_SUBSAMP_DIS 0x0000
-#define VFE_CMD_CHROMA_SUBSAMP_SEL_V_SUBSAMP_ENA 0x0008
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int chroma_subsamp_sel;
-} __attribute__((packed)) vfe_cmd_chroma_subsample_cfg;
-
-
-/*
- * Command to program the white balance module
- */
-
-#define VFE_CMD_WHITE_BALANCE_CFG 0x000B
-#define VFE_CMD_WHITE_BALANCE_CFG_LEN \
- sizeof(vfe_cmd_white_balance_cfg)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int white_balance_gains;
-} __attribute__((packed)) vfe_cmd_white_balance_cfg;
-
-
-/*
- * Command to program the color processing module
- */
-
-#define VFE_CMD_COLOR_PROCESS_CFG 0x000C
-#define VFE_CMD_COLOR_PROCESS_CFG_LEN \
- sizeof(vfe_cmd_color_process_cfg)
-
-#define VFE_CMD_COLOR_CORRE_PART7_Q7_FACTORS 0x0000
-#define VFE_CMD_COLOR_CORRE_PART7_Q8_FACTORS 0x0001
-#define VFE_CMD_COLOR_CORRE_PART7_Q9_FACTORS 0x0002
-#define VFE_CMD_COLOR_CORRE_PART7_Q10_FACTORS 0x0003
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int color_correction_part1;
- unsigned int color_correction_part2;
- unsigned int color_correction_part3;
- unsigned int color_correction_part4;
- unsigned int color_correction_part5;
- unsigned int color_correction_part6;
- unsigned int color_correction_part7;
- unsigned int chroma_enhance_part1;
- unsigned int chroma_enhance_part2;
- unsigned int chroma_enhance_part3;
- unsigned int chroma_enhance_part4;
- unsigned int chroma_enhance_part5;
- unsigned int luma_calc_part1;
- unsigned int luma_calc_part2;
-} __attribute__((packed)) vfe_cmd_color_process_cfg;
-
-
-/*
- * Command to program adaptive filter module
- */
-
-#define VFE_CMD_ADP_FILTER_CFG 0x000D
-#define VFE_CMD_ADP_FILTER_CFG_LEN \
- sizeof(vfe_cmd_adp_filter_cfg)
-
-#define VFE_CMD_ASF_CFG_PART_SMOOTH_FILTER_DIS 0x0000
-#define VFE_CMD_ASF_CFG_PART_SMOOTH_FILTER_ENA 0x0001
-#define VFE_CMD_ASF_CFG_PART_NO_SHARP_MODE 0x0000
-#define VFE_CMD_ASF_CFG_PART_SINGLE_FILTER 0x0002
-#define VFE_CMD_ASF_CFG_PART_DUAL_FILTER 0x0004
-#define VFE_CMD_ASF_CFG_PART_SHARP_MODE 0x0007
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int asf_cfg_part[7];
-} __attribute__((packed)) vfe_cmd_adp_filter_cfg;
-
-
-/*
- * Command to program for frame skip pattern for op1 and op2
- */
-
-#define VFE_CMD_FRAME_SKIP_CFG 0x000E
-#define VFE_CMD_FRAME_SKIP_CFG_LEN \
- sizeof(vfe_cmd_frame_skip_cfg)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int frame_skip_pattern_op1;
- unsigned int frame_skip_pattern_op2;
-} __attribute__((packed)) vfe_cmd_frame_skip_cfg;
-
-
-/*
- * Command to program field-of-view crop for digital zoom
- */
-
-#define VFE_CMD_FOV_CROP 0x000F
-#define VFE_CMD_FOV_CROP_LEN sizeof(vfe_cmd_fov_crop)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int fov_crop_part1;
- unsigned int fov_crop_part2;
-} __attribute__((packed)) vfe_cmd_fov_crop;
-
-
-
-/*
- * Command to program auto focus(AF) statistics module
- */
-
-#define VFE_CMD_STATS_AUTOFOCUS_CFG 0x0010
-#define VFE_CMD_STATS_AUTOFOCUS_CFG_LEN \
- sizeof(vfe_cmd_stats_autofocus_cfg)
-
-#define VFE_CMD_AF_STATS_SEL_STATS_DIS 0x0000
-#define VFE_CMD_AF_STATS_SEL_STATS_ENA 0x0001
-#define VFE_CMD_AF_STATS_SEL_PRI_FIXED 0x0000
-#define VFE_CMD_AF_STATS_SEL_PRI_VAR 0x0002
-#define VFE_CMD_AF_STATS_CFG_PART_METRIC_SUM 0x00000000
-#define VFE_CMD_AF_STATS_CFG_PART_METRIC_MAX 0x00200000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int af_stats_sel;
- unsigned int af_stats_cfg_part[8];
- unsigned int af_stats_op_buf_hdr;
- unsigned int af_stats_op_buf[3];
-} __attribute__((packed)) vfe_cmd_stats_autofocus_cfg;
-
-
-/*
- * Command to program White balance(wb) and exposure (exp)
- * statistics module
- */
-
-#define VFE_CMD_STATS_WB_EXP_CFG 0x0011
-#define VFE_CMD_STATS_WB_EXP_CFG_LEN \
- sizeof(vfe_cmd_stats_wb_exp_cfg)
-
-#define VFE_CMD_WB_EXP_STATS_SEL_STATS_DIS 0x0000
-#define VFE_CMD_WB_EXP_STATS_SEL_STATS_ENA 0x0001
-#define VFE_CMD_WB_EXP_STATS_SEL_PRI_FIXED 0x0000
-#define VFE_CMD_WB_EXP_STATS_SEL_PRI_VAR 0x0002
-
-#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_REG_8_8 0x0000
-#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_REG_16_16 0x0001
-#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_SREG_8_8 0x0000
-#define VFE_CMD_WB_EXP_STATS_CFG_PART1_EXP_SREG_4_4 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int wb_exp_stats_sel;
- unsigned int wb_exp_stats_cfg_part1;
- unsigned int wb_exp_stats_cfg_part2;
- unsigned int wb_exp_stats_cfg_part3;
- unsigned int wb_exp_stats_cfg_part4;
- unsigned int wb_exp_stats_op_buf_hdr;
- unsigned int wb_exp_stats_op_buf[3];
-} __attribute__((packed)) vfe_cmd_stats_wb_exp_cfg;
-
-
-/*
- * Command to program histogram(hg) stats module
- */
-
-#define VFE_CMD_STATS_HG_CFG 0x0012
-#define VFE_CMD_STATS_HG_CFG_LEN \
- sizeof(vfe_cmd_stats_hg_cfg)
-
-#define VFE_CMD_HG_STATS_SEL_PRI_FIXED 0x0000
-#define VFE_CMD_HG_STATS_SEL_PRI_VAR 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int hg_stats_sel;
- unsigned int hg_stats_cfg_part1;
- unsigned int hg_stats_cfg_part2;
- unsigned int hg_stats_op_buf_hdr;
- unsigned int hg_stats_op_buf;
-} __attribute__((packed)) vfe_cmd_stats_hg_cfg;
-
-
-/*
- * Command to acknowledge last MSG_VFE_OP1 message
- */
-
-#define VFE_CMD_OP1_ACK 0x0013
-#define VFE_CMD_OP1_ACK_LEN sizeof(vfe_cmd_op1_ack)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int op1_buf_y_addr;
- unsigned int op1_buf_cbcr_addr;
-} __attribute__((packed)) vfe_cmd_op1_ack;
-
-
-
-/*
- * Command to acknowledge last MSG_VFE_OP2 message
- */
-
-#define VFE_CMD_OP2_ACK 0x0014
-#define VFE_CMD_OP2_ACK_LEN sizeof(vfe_cmd_op2_ack)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int op2_buf_y_addr;
- unsigned int op2_buf_cbcr_addr;
-} __attribute__((packed)) vfe_cmd_op2_ack;
-
-
-
-/*
- * Command to acknowledge MSG_VFE_STATS_AUTOFOCUS msg
- */
-
-#define VFE_CMD_STATS_AF_ACK 0x0015
-#define VFE_CMD_STATS_AF_ACK_LEN sizeof(vfe_cmd_stats_af_ack)
-
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int af_stats_op_buf;
-} __attribute__((packed)) vfe_cmd_stats_af_ack;
-
-
-/*
- * Command to acknowledge MSG_VFE_STATS_WB_EXP msg
- */
-
-#define VFE_CMD_STATS_WB_EXP_ACK 0x0016
-#define VFE_CMD_STATS_WB_EXP_ACK_LEN sizeof(vfe_cmd_stats_wb_exp_ack)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int wb_exp_stats_op_buf;
-} __attribute__((packed)) vfe_cmd_stats_wb_exp_ack;
-
-
-/*
- * Command to acknowledge MSG_VFE_EPOCH1 message
- */
-
-#define VFE_CMD_EPOCH1_ACK 0x0017
-#define VFE_CMD_EPOCH1_ACK_LEN sizeof(vfe_cmd_epoch1_ack)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) vfe_cmd_epoch1_ack;
-
-
-/*
- * Command to acknowledge MSG_VFE_EPOCH2 message
- */
-
-#define VFE_CMD_EPOCH2_ACK 0x0018
-#define VFE_CMD_EPOCH2_ACK_LEN sizeof(vfe_cmd_epoch2_ack)
-
-typedef struct {
- unsigned short cmd_id;
-} __attribute__((packed)) vfe_cmd_epoch2_ack;
-
-
-
-/*
- * Command to configure, enable or disable synchronous timer1
- */
-
-#define VFE_CMD_SYNC_TIMER1_CFG 0x0019
-#define VFE_CMD_SYNC_TIMER1_CFG_LEN \
- sizeof(vfe_cmd_sync_timer1_cfg)
-
-#define VFE_CMD_SYNC_T1_CFG_PART1_TIMER_DIS 0x0000
-#define VFE_CMD_SYNC_T1_CFG_PART1_TIMER_ENA 0x0001
-#define VFE_CMD_SYNC_T1_CFG_PART1_POL_HIGH 0x0000
-#define VFE_CMD_SYNC_T1_CFG_PART1_POL_LOW 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int sync_t1_cfg_part1;
- unsigned int sync_t1_h_sync_countdown;
- unsigned int sync_t1_pclk_countdown;
- unsigned int sync_t1_duration;
-} __attribute__((packed)) vfe_cmd_sync_timer1_cfg;
-
-
-/*
- * Command to configure, enable or disable synchronous timer1
- */
-
-#define VFE_CMD_SYNC_TIMER2_CFG 0x001A
-#define VFE_CMD_SYNC_TIMER2_CFG_LEN \
- sizeof(vfe_cmd_sync_timer2_cfg)
-
-#define VFE_CMD_SYNC_T2_CFG_PART1_TIMER_DIS 0x0000
-#define VFE_CMD_SYNC_T2_CFG_PART1_TIMER_ENA 0x0001
-#define VFE_CMD_SYNC_T2_CFG_PART1_POL_HIGH 0x0000
-#define VFE_CMD_SYNC_T2_CFG_PART1_POL_LOW 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int sync_t2_cfg_part1;
- unsigned int sync_t2_h_sync_countdown;
- unsigned int sync_t2_pclk_countdown;
- unsigned int sync_t2_duration;
-} __attribute__((packed)) vfe_cmd_sync_timer2_cfg;
-
-
-/*
- * Command to configure and start asynchronous timer1
- */
-
-#define VFE_CMD_ASYNC_TIMER1_START 0x001B
-#define VFE_CMD_ASYNC_TIMER1_START_LEN \
- sizeof(vfe_cmd_async_timer1_start)
-
-#define VFE_CMD_ASYNC_T1_POLARITY_A_HIGH 0x0000
-#define VFE_CMD_ASYNC_T1_POLARITY_A_LOW 0x0001
-#define VFE_CMD_ASYNC_T1_POLARITY_B_HIGH 0x0000
-#define VFE_CMD_ASYNC_T1_POLARITY_B_LOW 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int async_t1a_cfg;
- unsigned int async_t1b_cfg;
- unsigned int async_t1_polarity;
-} __attribute__((packed)) vfe_cmd_async_timer1_start;
-
-
-/*
- * Command to configure and start asynchronous timer2
- */
-
-#define VFE_CMD_ASYNC_TIMER2_START 0x001C
-#define VFE_CMD_ASYNC_TIMER2_START_LEN \
- sizeof(vfe_cmd_async_timer2_start)
-
-#define VFE_CMD_ASYNC_T2_POLARITY_A_HIGH 0x0000
-#define VFE_CMD_ASYNC_T2_POLARITY_A_LOW 0x0001
-#define VFE_CMD_ASYNC_T2_POLARITY_B_HIGH 0x0000
-#define VFE_CMD_ASYNC_T2_POLARITY_B_LOW 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int async_t2a_cfg;
- unsigned int async_t2b_cfg;
- unsigned int async_t2_polarity;
-} __attribute__((packed)) vfe_cmd_async_timer2_start;
-
-
-/*
- * Command to program partial configurations of auto focus(af)
- */
-
-#define VFE_CMD_STATS_AF_UPDATE 0x001D
-#define VFE_CMD_STATS_AF_UPDATE_LEN \
- sizeof(vfe_cmd_stats_af_update)
-
-#define VFE_CMD_AF_UPDATE_PART1_WINDOW_ONE 0x00000000
-#define VFE_CMD_AF_UPDATE_PART1_WINDOW_MULTI 0x80000000
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int af_update_part1;
- unsigned int af_update_part2;
-} __attribute__((packed)) vfe_cmd_stats_af_update;
-
-
-/*
- * Command to program partial cfg of wb and exp
- */
-
-#define VFE_CMD_STATS_WB_EXP_UPDATE 0x001E
-#define VFE_CMD_STATS_WB_EXP_UPDATE_LEN \
- sizeof(vfe_cmd_stats_wb_exp_update)
-
-#define VFE_CMD_WB_EXP_UPDATE_PART1_REGIONS_8_8 0x0000
-#define VFE_CMD_WB_EXP_UPDATE_PART1_REGIONS_16_16 0x0001
-#define VFE_CMD_WB_EXP_UPDATE_PART1_SREGIONS_8_8 0x0000
-#define VFE_CMD_WB_EXP_UPDATE_PART1_SREGIONS_4_4 0x0002
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int wb_exp_update_part1;
- unsigned int wb_exp_update_part2;
- unsigned int wb_exp_update_part3;
- unsigned int wb_exp_update_part4;
-} __attribute__((packed)) vfe_cmd_stats_wb_exp_update;
-
-
-
-/*
- * Command to re program the CAMIF FRAME CONFIG settings
- */
-
-#define VFE_CMD_UPDATE_CAMIF_FRAME_CFG 0x001F
-#define VFE_CMD_UPDATE_CAMIF_FRAME_CFG_LEN \
- sizeof(vfe_cmd_update_camif_frame_cfg)
-
-typedef struct {
- unsigned int cmd_id;
- unsigned int camif_frame_cfg;
-} __attribute__((packed)) vfe_cmd_update_camif_frame_cfg;
-
-
-#endif
+++ /dev/null
-#ifndef QDSP5VFEMSGI_H
-#define QDSP5VFEMSGI_H
-
-/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
-
- V F E I N T E R N A L M E S S A G E S
-
-GENERAL DESCRIPTION
- This file contains defintions of format blocks of commands
- that are sent by VFE Task
-
-REFERENCES
- None
-
-EXTERNALIZED FUNCTIONS
- None
-
-Copyright(c) 1992 - 2008 by QUALCOMM, Incorporated.
-
-This software is licensed under the terms of the GNU General Public
-License version 2, as published by the Free Software Foundation, and
-may be copied, distributed, and modified under those terms.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
-/*===========================================================================
-
- EDIT HISTORY FOR FILE
-
-This section contains comments describing changes made to this file.
-Notice that changes are listed in reverse chronological order.
-
-$Header: //source/qcom/qct/multimedia2/AdspSvc/7XXX/qdsp5cmd/video/qdsp5vfemsg.h#2 $ $DateTime: 2008/07/30 10:50:23 $ $Author: pavanr $
-Revision History:
-
-when who what, where, why
--------- --- ----------------------------------------------------------
-06/12/08 sv initial version
-===========================================================================*/
-
-
-/*
- * Message to acknowledge CMD_VFE_REST command
- */
-
-#define VFE_MSG_RESET_ACK 0x0000
-#define VFE_MSG_RESET_ACK_LEN sizeof(vfe_msg_reset_ack)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_reset_ack;
-
-
-/*
- * Message to acknowledge CMD_VFE_START command
- */
-
-#define VFE_MSG_START_ACK 0x0001
-#define VFE_MSG_START_ACK_LEN sizeof(vfe_msg_start_ack)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_start_ack;
-
-/*
- * Message to acknowledge CMD_VFE_STOP command
- */
-
-#define VFE_MSG_STOP_ACK 0x0002
-#define VFE_MSG_STOP_ACK_LEN sizeof(vfe_msg_stop_ack)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_stop_ack;
-
-
-/*
- * Message to acknowledge CMD_VFE_UPDATE command
- */
-
-#define VFE_MSG_UPDATE_ACK 0x0003
-#define VFE_MSG_UPDATE_ACK_LEN sizeof(vfe_msg_update_ack)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_update_ack;
-
-
-/*
- * Message to notify the ARM that snapshot processing is complete
- * and that the VFE is now STATE_VFE_IDLE
- */
-
-#define VFE_MSG_SNAPSHOT_DONE 0x0004
-#define VFE_MSG_SNAPSHOT_DONE_LEN \
- sizeof(vfe_msg_snapshot_done)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_snapshot_done;
-
-
-
-/*
- * Message to notify ARM that illegal cmd was received and
- * system is in the IDLE state
- */
-
-#define VFE_MSG_ILLEGAL_CMD 0x0005
-#define VFE_MSG_ILLEGAL_CMD_LEN \
- sizeof(vfe_msg_illegal_cmd)
-
-typedef struct {
- unsigned int status;
-} __attribute__((packed)) vfe_msg_illegal_cmd;
-
-
-/*
- * Message to notify ARM that op1 buf is full and ready
- */
-
-#define VFE_MSG_OP1 0x0006
-#define VFE_MSG_OP1_LEN sizeof(vfe_msg_op1)
-
-typedef struct {
- unsigned int op1_buf_y_addr;
- unsigned int op1_buf_cbcr_addr;
- unsigned int black_level_even_col;
- unsigned int black_level_odd_col;
- unsigned int defect_pixels_detected;
- unsigned int asf_max_edge;
-} __attribute__((packed)) vfe_msg_op1;
-
-
-/*
- * Message to notify ARM that op2 buf is full and ready
- */
-
-#define VFE_MSG_OP2 0x0007
-#define VFE_MSG_OP2_LEN sizeof(vfe_msg_op2)
-
-typedef struct {
- unsigned int op2_buf_y_addr;
- unsigned int op2_buf_cbcr_addr;
- unsigned int black_level_even_col;
- unsigned int black_level_odd_col;
- unsigned int defect_pixels_detected;
- unsigned int asf_max_edge;
-} __attribute__((packed)) vfe_msg_op2;
-
-
-/*
- * Message to notify ARM that autofocus(af) stats are ready
- */
-
-#define VFE_MSG_STATS_AF 0x0008
-#define VFE_MSG_STATS_AF_LEN sizeof(vfe_msg_stats_af)
-
-typedef struct {
- unsigned int af_stats_op_buffer;
-} __attribute__((packed)) vfe_msg_stats_af;
-
-
-/*
- * Message to notify ARM that white balance(wb) and exposure (exp)
- * stats are ready
- */
-
-#define VFE_MSG_STATS_WB_EXP 0x0009
-#define VFE_MSG_STATS_WB_EXP_LEN \
- sizeof(vfe_msg_stats_wb_exp)
-
-typedef struct {
- unsigned int wb_exp_stats_op_buf;
-} __attribute__((packed)) vfe_msg_stats_wb_exp;
-
-
-/*
- * Message to notify the ARM that histogram(hg) stats are ready
- */
-
-#define VFE_MSG_STATS_HG 0x000A
-#define VFE_MSG_STATS_HG_LEN sizeof(vfe_msg_stats_hg)
-
-typedef struct {
- unsigned int hg_stats_op_buf;
-} __attribute__((packed)) vfe_msg_stats_hg;
-
-
-/*
- * Message to notify the ARM that epoch1 event occurred in the CAMIF
- */
-
-#define VFE_MSG_EPOCH1 0x000B
-#define VFE_MSG_EPOCH1_LEN sizeof(vfe_msg_epoch1)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_epoch1;
-
-
-/*
- * Message to notify the ARM that epoch2 event occurred in the CAMIF
- */
-
-#define VFE_MSG_EPOCH2 0x000C
-#define VFE_MSG_EPOCH2_LEN sizeof(vfe_msg_epoch2)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_epoch2;
-
-
-/*
- * Message to notify the ARM that sync timer1 op is completed
- */
-
-#define VFE_MSG_SYNC_T1_DONE 0x000D
-#define VFE_MSG_SYNC_T1_DONE_LEN sizeof(vfe_msg_sync_t1_done)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_sync_t1_done;
-
-
-/*
- * Message to notify the ARM that sync timer2 op is completed
- */
-
-#define VFE_MSG_SYNC_T2_DONE 0x000E
-#define VFE_MSG_SYNC_T2_DONE_LEN sizeof(vfe_msg_sync_t2_done)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_sync_t2_done;
-
-
-/*
- * Message to notify the ARM that async t1 operation completed
- */
-
-#define VFE_MSG_ASYNC_T1_DONE 0x000F
-#define VFE_MSG_ASYNC_T1_DONE_LEN sizeof(vfe_msg_async_t1_done)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_async_t1_done;
-
-
-
-/*
- * Message to notify the ARM that async t2 operation completed
- */
-
-#define VFE_MSG_ASYNC_T2_DONE 0x0010
-#define VFE_MSG_ASYNC_T2_DONE_LEN sizeof(vfe_msg_async_t2_done)
-
-typedef struct {
-} __attribute__((packed)) vfe_msg_async_t2_done;
-
-
-
-/*
- * Message to notify the ARM that an error has occurred
- */
-
-#define VFE_MSG_ERROR 0x0011
-#define VFE_MSG_ERROR_LEN sizeof(vfe_msg_error)
-
-#define VFE_MSG_ERR_COND_NO_CAMIF_ERR 0x0000
-#define VFE_MSG_ERR_COND_CAMIF_ERR 0x0001
-#define VFE_MSG_ERR_COND_OP1_Y_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_OP1_Y_BUS_OF 0x0002
-#define VFE_MSG_ERR_COND_OP1_CBCR_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_OP1_CBCR_BUS_OF 0x0004
-#define VFE_MSG_ERR_COND_OP2_Y_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_OP2_Y_BUS_OF 0x0008
-#define VFE_MSG_ERR_COND_OP2_CBCR_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_OP2_CBCR_BUS_OF 0x0010
-#define VFE_MSG_ERR_COND_AF_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_AF_BUS_OF 0x0020
-#define VFE_MSG_ERR_COND_WB_EXP_NO_BUS_OF 0x0000
-#define VFE_MSG_ERR_COND_WB_EXP_BUS_OF 0x0040
-#define VFE_MSG_ERR_COND_NO_AXI_ERR 0x0000
-#define VFE_MSG_ERR_COND_AXI_ERR 0x0080
-
-#define VFE_MSG_CAMIF_STS_IDLE 0x0000
-#define VFE_MSG_CAMIF_STS_CAPTURE_DATA 0x0001
-
-typedef struct {
- unsigned int err_cond;
- unsigned int camif_sts;
-} __attribute__((packed)) vfe_msg_error;
-
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2008-2009 QUALCOMM Incorporated.
- */
-#ifndef __LINUX_MSM_CAMERA_H
-#define __LINUX_MSM_CAMERA_H
-
-#include <linux/types.h>
-#include <asm/sizes.h>
-#include <linux/ioctl.h>
-
-#define MSM_CAM_IOCTL_MAGIC 'm'
-
-#define MSM_CAM_IOCTL_GET_SENSOR_INFO \
- _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *)
-
-#define MSM_CAM_IOCTL_REGISTER_PMEM \
- _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *)
-
-#define MSM_CAM_IOCTL_UNREGISTER_PMEM \
- _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned)
-
-#define MSM_CAM_IOCTL_CTRL_COMMAND \
- _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *)
-
-#define MSM_CAM_IOCTL_CONFIG_VFE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *)
-
-#define MSM_CAM_IOCTL_GET_STATS \
- _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *)
-
-#define MSM_CAM_IOCTL_GETFRAME \
- _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *)
-
-#define MSM_CAM_IOCTL_ENABLE_VFE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *)
-
-#define MSM_CAM_IOCTL_CTRL_CMD_DONE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *)
-
-#define MSM_CAM_IOCTL_CONFIG_CMD \
- _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *)
-
-#define MSM_CAM_IOCTL_DISABLE_VFE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *)
-
-#define MSM_CAM_IOCTL_PAD_REG_RESET2 \
- _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *)
-
-#define MSM_CAM_IOCTL_VFE_APPS_RESET \
- _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *)
-
-#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \
- _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *)
-
-#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \
- _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *)
-
-#define MSM_CAM_IOCTL_AXI_CONFIG \
- _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *)
-
-#define MSM_CAM_IOCTL_GET_PICTURE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_camera_ctrl_cmd *)
-
-#define MSM_CAM_IOCTL_SET_CROP \
- _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *)
-
-#define MSM_CAM_IOCTL_PICT_PP \
- _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *)
-
-#define MSM_CAM_IOCTL_PICT_PP_DONE \
- _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *)
-
-#define MSM_CAM_IOCTL_SENSOR_IO_CFG \
- _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *)
-
-#define MSM_CAMERA_LED_OFF 0
-#define MSM_CAMERA_LED_LOW 1
-#define MSM_CAMERA_LED_HIGH 2
-
-#define MSM_CAM_IOCTL_FLASH_LED_CFG \
- _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *)
-
-#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \
- _IO(MSM_CAM_IOCTL_MAGIC, 23)
-
-#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \
- _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *)
-
-#define MAX_SENSOR_NUM 3
-#define MAX_SENSOR_NAME 32
-
-#define MSM_CAM_CTRL_CMD_DONE 0
-#define MSM_CAM_SENSOR_VFE_CMD 1
-
-/*****************************************************
- * structure
- *****************************************************/
-
-/* define five type of structures for userspace <==> kernel
- * space communication:
- * command 1 - 2 are from userspace ==> kernel
- * command 3 - 4 are from kernel ==> userspace
- *
- * 1. control command: control command(from control thread),
- * control status (from config thread);
- */
-struct msm_ctrl_cmd {
- uint16_t type;
- uint16_t length;
- void *value;
- uint16_t status;
- uint32_t timeout_ms;
- int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */
-};
-
-struct msm_vfe_evt_msg {
- unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */
- unsigned short msg_id;
- unsigned int len; /* size in, number of bytes out */
- void *data;
-};
-
-#define MSM_CAM_RESP_CTRL 0
-#define MSM_CAM_RESP_STAT_EVT_MSG 1
-#define MSM_CAM_RESP_V4L2 2
-#define MSM_CAM_RESP_MAX 3
-
-/* this one is used to send ctrl/status up to config thread */
-struct msm_stats_event_ctrl {
- /* 0 - ctrl_cmd from control thread,
- * 1 - stats/event kernel,
- * 2 - V4L control or read request */
- int resptype;
- int timeout_ms;
- struct msm_ctrl_cmd ctrl_cmd;
- /* struct vfe_event_t stats_event; */
- struct msm_vfe_evt_msg stats_event;
-};
-
-/* 2. config command: config command(from config thread); */
-struct msm_camera_cfg_cmd {
- /* what to config:
- * 1 - sensor config, 2 - vfe config */
- uint16_t cfg_type;
-
- /* sensor config type */
- uint16_t cmd_type;
- uint16_t queue;
- uint16_t length;
- void *value;
-};
-
-#define CMD_GENERAL 0
-#define CMD_AXI_CFG_OUT1 1
-#define CMD_AXI_CFG_SNAP_O1_AND_O2 2
-#define CMD_AXI_CFG_OUT2 3
-#define CMD_PICT_T_AXI_CFG 4
-#define CMD_PICT_M_AXI_CFG 5
-#define CMD_RAW_PICT_AXI_CFG 6
-#define CMD_STATS_AXI_CFG 7
-#define CMD_STATS_AF_AXI_CFG 8
-#define CMD_FRAME_BUF_RELEASE 9
-#define CMD_PREV_BUF_CFG 10
-#define CMD_SNAP_BUF_RELEASE 11
-#define CMD_SNAP_BUF_CFG 12
-#define CMD_STATS_DISABLE 13
-#define CMD_STATS_ENABLE 14
-#define CMD_STATS_AF_ENABLE 15
-#define CMD_STATS_BUF_RELEASE 16
-#define CMD_STATS_AF_BUF_RELEASE 17
-#define UPDATE_STATS_INVALID 18
-
-/* vfe config command: config command(from config thread)*/
-struct msm_vfe_cfg_cmd {
- int cmd_type;
- uint16_t length;
- void *value;
-};
-
-#define MAX_CAMERA_ENABLE_NAME_LEN 32
-struct camera_enable_cmd {
- char name[MAX_CAMERA_ENABLE_NAME_LEN];
-};
-
-#define MSM_PMEM_OUTPUT1 0
-#define MSM_PMEM_OUTPUT2 1
-#define MSM_PMEM_OUTPUT1_OUTPUT2 2
-#define MSM_PMEM_THUMBAIL 3
-#define MSM_PMEM_MAINIMG 4
-#define MSM_PMEM_RAW_MAINIMG 5
-#define MSM_PMEM_AEC_AWB 6
-#define MSM_PMEM_AF 7
-#define MSM_PMEM_MAX 8
-
-#define FRAME_PREVIEW_OUTPUT1 0
-#define FRAME_PREVIEW_OUTPUT2 1
-#define FRAME_SNAPSHOT 2
-#define FRAME_THUMBAIL 3
-#define FRAME_RAW_SNAPSHOT 4
-#define FRAME_MAX 5
-
-struct msm_pmem_info {
- int type;
- int fd;
- void *vaddr;
- uint32_t y_off;
- uint32_t cbcr_off;
- uint8_t active;
-};
-
-struct outputCfg {
- uint32_t height;
- uint32_t width;
-
- uint32_t window_height_firstline;
- uint32_t window_height_lastline;
-};
-
-#define OUTPUT_1 0
-#define OUTPUT_2 1
-#define OUTPUT_1_AND_2 2
-#define CAMIF_TO_AXI_VIA_OUTPUT_2 3
-#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 4
-#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 5
-#define LAST_AXI_OUTPUT_MODE_ENUM = OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6
-
-#define MSM_FRAME_PREV_1 0
-#define MSM_FRAME_PREV_2 1
-#define MSM_FRAME_ENC 2
-
-struct msm_frame {
- int path;
- unsigned long buffer;
- uint32_t y_off;
- uint32_t cbcr_off;
- int fd;
-
- void *cropinfo;
- int croplen;
-};
-
-#define STAT_AEAW 0
-#define STAT_AF 1
-#define STAT_MAX 2
-
-struct msm_stats_buf {
- int type;
- unsigned long buffer;
- int fd;
-};
-
-#define MSM_V4L2_VID_CAP_TYPE 0
-#define MSM_V4L2_STREAM_ON 1
-#define MSM_V4L2_STREAM_OFF 2
-#define MSM_V4L2_SNAPSHOT 3
-#define MSM_V4L2_QUERY_CTRL 4
-#define MSM_V4L2_GET_CTRL 5
-#define MSM_V4L2_SET_CTRL 6
-#define MSM_V4L2_QUERY 7
-#define MSM_V4L2_MAX 8
-
-struct crop_info {
- void *info;
- int len;
-};
-
-struct msm_postproc {
- int ftnum;
- struct msm_frame fthumnail;
- int fmnum;
- struct msm_frame fmain;
-};
-
-struct msm_snapshot_pp_status {
- void *status;
-};
-
-#define CFG_SET_MODE 0
-#define CFG_SET_EFFECT 1
-#define CFG_START 2
-#define CFG_PWR_UP 3
-#define CFG_PWR_DOWN 4
-#define CFG_WRITE_EXPOSURE_GAIN 5
-#define CFG_SET_DEFAULT_FOCUS 6
-#define CFG_MOVE_FOCUS 7
-#define CFG_REGISTER_TO_REAL_GAIN 8
-#define CFG_REAL_TO_REGISTER_GAIN 9
-#define CFG_SET_FPS 10
-#define CFG_SET_PICT_FPS 11
-#define CFG_SET_BRIGHTNESS 12
-#define CFG_SET_CONTRAST 13
-#define CFG_SET_ZOOM 14
-#define CFG_SET_EXPOSURE_MODE 15
-#define CFG_SET_WB 16
-#define CFG_SET_ANTIBANDING 17
-#define CFG_SET_EXP_GAIN 18
-#define CFG_SET_PICT_EXP_GAIN 19
-#define CFG_SET_LENS_SHADING 20
-#define CFG_GET_PICT_FPS 21
-#define CFG_GET_PREV_L_PF 22
-#define CFG_GET_PREV_P_PL 23
-#define CFG_GET_PICT_L_PF 24
-#define CFG_GET_PICT_P_PL 25
-#define CFG_GET_AF_MAX_STEPS 26
-#define CFG_GET_PICT_MAX_EXP_LC 27
-#define CFG_MAX 28
-
-#define MOVE_NEAR 0
-#define MOVE_FAR 1
-
-#define SENSOR_PREVIEW_MODE 0
-#define SENSOR_SNAPSHOT_MODE 1
-#define SENSOR_RAW_SNAPSHOT_MODE 2
-
-#define SENSOR_QTR_SIZE 0
-#define SENSOR_FULL_SIZE 1
-#define SENSOR_INVALID_SIZE 2
-
-#define CAMERA_EFFECT_OFF 0
-#define CAMERA_EFFECT_MONO 1
-#define CAMERA_EFFECT_NEGATIVE 2
-#define CAMERA_EFFECT_SOLARIZE 3
-#define CAMERA_EFFECT_PASTEL 4
-#define CAMERA_EFFECT_MOSAIC 5
-#define CAMERA_EFFECT_RESIZE 6
-#define CAMERA_EFFECT_SEPIA 7
-#define CAMERA_EFFECT_POSTERIZE 8
-#define CAMERA_EFFECT_WHITEBOARD 9
-#define CAMERA_EFFECT_BLACKBOARD 10
-#define CAMERA_EFFECT_AQUA 11
-#define CAMERA_EFFECT_MAX 12
-
-struct sensor_pict_fps {
- uint16_t prevfps;
- uint16_t pictfps;
-};
-
-struct exp_gain_cfg {
- uint16_t gain;
- uint32_t line;
-};
-
-struct focus_cfg {
- int32_t steps;
- int dir;
-};
-
-struct fps_cfg {
- uint16_t f_mult;
- uint16_t fps_div;
- uint32_t pict_fps_div;
-};
-
-struct sensor_cfg_data {
- int cfgtype;
- int mode;
- int rs;
- uint8_t max_steps;
-
- union {
- int8_t effect;
- uint8_t lens_shading;
- uint16_t prevl_pf;
- uint16_t prevp_pl;
- uint16_t pictl_pf;
- uint16_t pictp_pl;
- uint32_t pict_max_exp_lc;
- uint16_t p_fps;
- struct sensor_pict_fps gfps;
- struct exp_gain_cfg exp_gain;
- struct focus_cfg focus;
- struct fps_cfg fps;
- } cfg;
-};
-
-#define GET_NAME 0
-#define GET_PREVIEW_LINE_PER_FRAME 1
-#define GET_PREVIEW_PIXELS_PER_LINE 2
-#define GET_SNAPSHOT_LINE_PER_FRAME 3
-#define GET_SNAPSHOT_PIXELS_PER_LINE 4
-#define GET_SNAPSHOT_FPS 5
-#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6
-
-struct msm_camsensor_info {
- char name[MAX_SENSOR_NAME];
- uint8_t flash_enabled;
-};
-#endif /* __LINUX_MSM_CAMERA_H */
+++ /dev/null
-/* drivers/android/pmem.c
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/miscdevice.h>
-#include <linux/platform_device.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/mm.h>
-#include <linux/list.h>
-#include <linux/debugfs.h>
-#include <linux/android_pmem.h>
-#include <linux/mempolicy.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-#include <asm/cacheflush.h>
-
-#define PMEM_MAX_DEVICES 10
-#define PMEM_MAX_ORDER 128
-#define PMEM_MIN_ALLOC PAGE_SIZE
-
-#define PMEM_DEBUG 1
-
-/* indicates that a refernce to this file has been taken via get_pmem_file,
- * the file should not be released until put_pmem_file is called */
-#define PMEM_FLAGS_BUSY 0x1
-/* indicates that this is a suballocation of a larger master range */
-#define PMEM_FLAGS_CONNECTED (0x1 << 1)
-/* indicates this is a master and not a sub allocation and that it is mmaped */
-#define PMEM_FLAGS_MASTERMAP (0x1 << 2)
-/* submap and unsubmap flags indicate:
- * 00: subregion has never been mmaped
- * 10: subregion has been mmaped, reference to the mm was taken
- * 11: subretion has ben released, refernece to the mm still held
- * 01: subretion has been released, reference to the mm has been released
- */
-#define PMEM_FLAGS_SUBMAP (0x1 << 3)
-#define PMEM_FLAGS_UNSUBMAP (0x1 << 4)
-
-
-struct pmem_data {
- /* in alloc mode: an index into the bitmap
- * in no_alloc mode: the size of the allocation */
- int index;
- /* see flags above for descriptions */
- unsigned int flags;
- /* protects this data field, if the mm_mmap sem will be held at the
- * same time as this sem, the mm sem must be taken first (as this is
- * the order for vma_open and vma_close ops */
- struct rw_semaphore sem;
- /* info about the mmaping process */
- struct vm_area_struct *vma;
- /* task struct of the mapping process */
- struct task_struct *task;
- /* process id of teh mapping process */
- pid_t pid;
- /* file descriptor of the master */
- int master_fd;
- /* file struct of the master */
- struct file *master_file;
- /* a list of currently available regions if this is a suballocation */
- struct list_head region_list;
- /* a linked list of data so we can access them for debugging */
- struct list_head list;
-#if PMEM_DEBUG
- int ref;
-#endif
-};
-
-struct pmem_bits {
- unsigned allocated:1; /* 1 if allocated, 0 if free */
- unsigned order:7; /* size of the region in pmem space */
-};
-
-struct pmem_region_node {
- struct pmem_region region;
- struct list_head list;
-};
-
-#define PMEM_DEBUG_MSGS 0
-#if PMEM_DEBUG_MSGS
-#define DLOG(fmt, args...) \
- do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \
- ##args); } \
- while (0)
-#else
-#define DLOG(x...) do {} while (0)
-#endif
-
-struct pmem_info {
- struct miscdevice dev;
- /* physical start address of the remaped pmem space */
- unsigned long base;
- /* vitual start address of the remaped pmem space */
- unsigned char __iomem *vbase;
- /* total size of the pmem space */
- unsigned long size;
- /* number of entries in the pmem space */
- unsigned long num_entries;
- /* pfn of the garbage page in memory */
- unsigned long garbage_pfn;
- /* index of the garbage page in the pmem space */
- int garbage_index;
- /* the bitmap for the region indicating which entries are allocated
- * and which are free */
- struct pmem_bits *bitmap;
- /* indicates the region should not be managed with an allocator */
- unsigned no_allocator;
- /* indicates maps of this region should be cached, if a mix of
- * cached and uncached is desired, set this and open the device with
- * O_SYNC to get an uncached region */
- unsigned cached;
- unsigned buffered;
- /* in no_allocator mode the first mapper gets the whole space and sets
- * this flag */
- unsigned allocated;
- /* for debugging, creates a list of pmem file structs, the
- * data_list_sem should be taken before pmem_data->sem if both are
- * needed */
- struct semaphore data_list_sem;
- struct list_head data_list;
- /* pmem_sem protects the bitmap array
- * a write lock should be held when modifying entries in bitmap
- * a read lock should be held when reading data from bits or
- * dereferencing a pointer into bitmap
- *
- * pmem_data->sem protects the pmem data of a particular file
- * Many of the function that require the pmem_data->sem have a non-
- * locking version for when the caller is already holding that sem.
- *
- * IF YOU TAKE BOTH LOCKS TAKE THEM IN THIS ORDER:
- * down(pmem_data->sem) => down(bitmap_sem)
- */
- struct rw_semaphore bitmap_sem;
-
- long (*ioctl)(struct file *, unsigned int, unsigned long);
- int (*release)(struct inode *, struct file *);
-};
-
-static struct pmem_info pmem[PMEM_MAX_DEVICES];
-static int id_count;
-
-#define PMEM_IS_FREE(id, index) (!(pmem[id].bitmap[index].allocated))
-#define PMEM_ORDER(id, index) pmem[id].bitmap[index].order
-#define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index)))
-#define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index)))
-#define PMEM_OFFSET(index) (index * PMEM_MIN_ALLOC)
-#define PMEM_START_ADDR(id, index) (PMEM_OFFSET(index) + pmem[id].base)
-#define PMEM_LEN(id, index) ((1 << PMEM_ORDER(id, index)) * PMEM_MIN_ALLOC)
-#define PMEM_END_ADDR(id, index) (PMEM_START_ADDR(id, index) + \
- PMEM_LEN(id, index))
-#define PMEM_START_VADDR(id, index) (PMEM_OFFSET(id, index) + pmem[id].vbase)
-#define PMEM_END_VADDR(id, index) (PMEM_START_VADDR(id, index) + \
- PMEM_LEN(id, index))
-#define PMEM_REVOKED(data) (data->flags & PMEM_FLAGS_REVOKED)
-#define PMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK)))
-#define PMEM_IS_SUBMAP(data) ((data->flags & PMEM_FLAGS_SUBMAP) && \
- (!(data->flags & PMEM_FLAGS_UNSUBMAP)))
-
-static int pmem_release(struct inode *, struct file *);
-static int pmem_mmap(struct file *, struct vm_area_struct *);
-static int pmem_open(struct inode *, struct file *);
-static long pmem_ioctl(struct file *, unsigned int, unsigned long);
-
-const struct file_operations pmem_fops = {
- .release = pmem_release,
- .mmap = pmem_mmap,
- .open = pmem_open,
- .unlocked_ioctl = pmem_ioctl,
- .llseek = noop_llseek,
-};
-
-static int get_id(struct file *file)
-{
- return MINOR(file->f_dentry->d_inode->i_rdev);
-}
-
-static int is_pmem_file(struct file *file)
-{
- int id;
-
- if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode))
- return 0;
- id = get_id(file);
- if (unlikely(id >= PMEM_MAX_DEVICES))
- return 0;
- if (unlikely(file->f_dentry->d_inode->i_rdev !=
- MKDEV(MISC_MAJOR, pmem[id].dev.minor)))
- return 0;
- return 1;
-}
-
-static int has_allocation(struct file *file)
-{
- struct pmem_data *data;
- /* check is_pmem_file first if not accessed via pmem_file_ops */
-
- if (unlikely(!file->private_data))
- return 0;
- data = file->private_data;
- if (unlikely(data->index < 0))
- return 0;
- return 1;
-}
-
-static int is_master_owner(struct file *file)
-{
- struct file *master_file;
- struct pmem_data *data;
- int put_needed, ret = 0;
-
- if (!is_pmem_file(file) || !has_allocation(file))
- return 0;
- data = file->private_data;
- if (PMEM_FLAGS_MASTERMAP & data->flags)
- return 1;
- master_file = fget_light(data->master_fd, &put_needed);
- if (master_file && data->master_file == master_file)
- ret = 1;
- fput_light(master_file, put_needed);
- return ret;
-}
-
-static int pmem_free(int id, int index)
-{
- /* caller should hold the write lock on pmem_sem! */
- int buddy, curr = index;
- DLOG("index %d\n", index);
-
- if (pmem[id].no_allocator) {
- pmem[id].allocated = 0;
- return 0;
- }
- /* clean up the bitmap, merging any buddies */
- pmem[id].bitmap[curr].allocated = 0;
- /* find a slots buddy Buddy# = Slot# ^ (1 << order)
- * if the buddy is also free merge them
- * repeat until the buddy is not free or end of the bitmap is reached
- */
- do {
- buddy = PMEM_BUDDY_INDEX(id, curr);
- if (PMEM_IS_FREE(id, buddy) &&
- PMEM_ORDER(id, buddy) == PMEM_ORDER(id, curr)) {
- PMEM_ORDER(id, buddy)++;
- PMEM_ORDER(id, curr)++;
- curr = min(buddy, curr);
- } else {
- break;
- }
- } while (curr < pmem[id].num_entries);
-
- return 0;
-}
-
-static void pmem_revoke(struct file *file, struct pmem_data *data);
-
-static int pmem_release(struct inode *inode, struct file *file)
-{
- struct pmem_data *data = file->private_data;
- struct pmem_region_node *region_node;
- struct list_head *elt, *elt2;
- int id = get_id(file), ret = 0;
-
-
- down(&pmem[id].data_list_sem);
- /* if this file is a master, revoke all the memory in the connected
- * files */
- if (PMEM_FLAGS_MASTERMAP & data->flags) {
- struct pmem_data *sub_data;
- list_for_each(elt, &pmem[id].data_list) {
- sub_data = list_entry(elt, struct pmem_data, list);
- down_read(&sub_data->sem);
- if (PMEM_IS_SUBMAP(sub_data) &&
- file == sub_data->master_file) {
- up_read(&sub_data->sem);
- pmem_revoke(file, sub_data);
- } else
- up_read(&sub_data->sem);
- }
- }
- list_del(&data->list);
- up(&pmem[id].data_list_sem);
-
-
- down_write(&data->sem);
-
- /* if its not a conencted file and it has an allocation, free it */
- if (!(PMEM_FLAGS_CONNECTED & data->flags) && has_allocation(file)) {
- down_write(&pmem[id].bitmap_sem);
- ret = pmem_free(id, data->index);
- up_write(&pmem[id].bitmap_sem);
- }
-
- /* if this file is a submap (mapped, connected file), downref the
- * task struct */
- if (PMEM_FLAGS_SUBMAP & data->flags)
- if (data->task) {
- put_task_struct(data->task);
- data->task = NULL;
- }
-
- file->private_data = NULL;
-
- list_for_each_safe(elt, elt2, &data->region_list) {
- region_node = list_entry(elt, struct pmem_region_node, list);
- list_del(elt);
- kfree(region_node);
- }
- BUG_ON(!list_empty(&data->region_list));
-
- up_write(&data->sem);
- kfree(data);
- if (pmem[id].release)
- ret = pmem[id].release(inode, file);
-
- return ret;
-}
-
-static int pmem_open(struct inode *inode, struct file *file)
-{
- struct pmem_data *data;
- int id = get_id(file);
- int ret = 0;
-
- DLOG("current %u file %p(%d)\n", current->pid, file, file_count(file));
- /* setup file->private_data to indicate its unmapped */
- /* you can only open a pmem device one time */
- if (file->private_data != NULL)
- return -1;
- data = kmalloc(sizeof(struct pmem_data), GFP_KERNEL);
- if (!data) {
- printk("pmem: unable to allocate memory for pmem metadata.");
- return -1;
- }
- data->flags = 0;
- data->index = -1;
- data->task = NULL;
- data->vma = NULL;
- data->pid = 0;
- data->master_file = NULL;
-#if PMEM_DEBUG
- data->ref = 0;
-#endif
- INIT_LIST_HEAD(&data->region_list);
- init_rwsem(&data->sem);
-
- file->private_data = data;
- INIT_LIST_HEAD(&data->list);
-
- down(&pmem[id].data_list_sem);
- list_add(&data->list, &pmem[id].data_list);
- up(&pmem[id].data_list_sem);
- return ret;
-}
-
-static unsigned long pmem_order(unsigned long len)
-{
- int i;
-
- len = (len + PMEM_MIN_ALLOC - 1)/PMEM_MIN_ALLOC;
- len--;
- for (i = 0; i < sizeof(len)*8; i++)
- if (len >> i == 0)
- break;
- return i;
-}
-
-static int pmem_allocate(int id, unsigned long len)
-{
- /* caller should hold the write lock on pmem_sem! */
- /* return the corresponding pdata[] entry */
- int curr = 0;
- int end = pmem[id].num_entries;
- int best_fit = -1;
- unsigned long order = pmem_order(len);
-
- if (pmem[id].no_allocator) {
- DLOG("no allocator");
- if ((len > pmem[id].size) || pmem[id].allocated)
- return -1;
- pmem[id].allocated = 1;
- return len;
- }
-
- if (order > PMEM_MAX_ORDER)
- return -1;
- DLOG("order %lx\n", order);
-
- /* look through the bitmap:
- * if you find a free slot of the correct order use it
- * otherwise, use the best fit (smallest with size > order) slot
- */
- while (curr < end) {
- if (PMEM_IS_FREE(id, curr)) {
- if (PMEM_ORDER(id, curr) == (unsigned char)order) {
- /* set the not free bit and clear others */
- best_fit = curr;
- break;
- }
- if (PMEM_ORDER(id, curr) > (unsigned char)order &&
- (best_fit < 0 ||
- PMEM_ORDER(id, curr) < PMEM_ORDER(id, best_fit)))
- best_fit = curr;
- }
- curr = PMEM_NEXT_INDEX(id, curr);
- }
-
- /* if best_fit < 0, there are no suitable slots,
- * return an error
- */
- if (best_fit < 0) {
- printk("pmem: no space left to allocate!\n");
- return -1;
- }
-
- /* now partition the best fit:
- * split the slot into 2 buddies of order - 1
- * repeat until the slot is of the correct order
- */
- while (PMEM_ORDER(id, best_fit) > (unsigned char)order) {
- int buddy;
- PMEM_ORDER(id, best_fit) -= 1;
- buddy = PMEM_BUDDY_INDEX(id, best_fit);
- PMEM_ORDER(id, buddy) = PMEM_ORDER(id, best_fit);
- }
- pmem[id].bitmap[best_fit].allocated = 1;
- return best_fit;
-}
-
-static pgprot_t phys_mem_access_prot(struct file *file, pgprot_t vma_prot)
-{
- int id = get_id(file);
-#ifdef pgprot_noncached
- if (pmem[id].cached == 0 || file->f_flags & O_SYNC)
- return pgprot_noncached(vma_prot);
-#endif
-#ifdef pgprot_ext_buffered
- else if (pmem[id].buffered)
- return pgprot_ext_buffered(vma_prot);
-#endif
- return vma_prot;
-}
-
-static unsigned long pmem_start_addr(int id, struct pmem_data *data)
-{
- if (pmem[id].no_allocator)
- return PMEM_START_ADDR(id, 0);
- else
- return PMEM_START_ADDR(id, data->index);
-
-}
-
-static void *pmem_start_vaddr(int id, struct pmem_data *data)
-{
- return pmem_start_addr(id, data) - pmem[id].base + pmem[id].vbase;
-}
-
-static unsigned long pmem_len(int id, struct pmem_data *data)
-{
- if (pmem[id].no_allocator)
- return data->index;
- else
- return PMEM_LEN(id, data->index);
-}
-
-static int pmem_map_garbage(int id, struct vm_area_struct *vma,
- struct pmem_data *data, unsigned long offset,
- unsigned long len)
-{
- int i, garbage_pages = len >> PAGE_SHIFT;
-
- vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP | VM_SHARED | VM_WRITE;
- for (i = 0; i < garbage_pages; i++) {
- if (vm_insert_pfn(vma, vma->vm_start + offset + (i * PAGE_SIZE),
- pmem[id].garbage_pfn))
- return -EAGAIN;
- }
- return 0;
-}
-
-static int pmem_unmap_pfn_range(int id, struct vm_area_struct *vma,
- struct pmem_data *data, unsigned long offset,
- unsigned long len)
-{
- int garbage_pages;
- DLOG("unmap offset %lx len %lx\n", offset, len);
-
- BUG_ON(!PMEM_IS_PAGE_ALIGNED(len));
-
- garbage_pages = len >> PAGE_SHIFT;
- zap_page_range(vma, vma->vm_start + offset, len, NULL);
- pmem_map_garbage(id, vma, data, offset, len);
- return 0;
-}
-
-static int pmem_map_pfn_range(int id, struct vm_area_struct *vma,
- struct pmem_data *data, unsigned long offset,
- unsigned long len)
-{
- DLOG("map offset %lx len %lx\n", offset, len);
- BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_start));
- BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_end));
- BUG_ON(!PMEM_IS_PAGE_ALIGNED(len));
- BUG_ON(!PMEM_IS_PAGE_ALIGNED(offset));
-
- if (io_remap_pfn_range(vma, vma->vm_start + offset,
- (pmem_start_addr(id, data) + offset) >> PAGE_SHIFT,
- len, vma->vm_page_prot)) {
- return -EAGAIN;
- }
- return 0;
-}
-
-static int pmem_remap_pfn_range(int id, struct vm_area_struct *vma,
- struct pmem_data *data, unsigned long offset,
- unsigned long len)
-{
- /* hold the mm semp for the vma you are modifying when you call this */
- BUG_ON(!vma);
- zap_page_range(vma, vma->vm_start + offset, len, NULL);
- return pmem_map_pfn_range(id, vma, data, offset, len);
-}
-
-static void pmem_vma_open(struct vm_area_struct *vma)
-{
- struct file *file = vma->vm_file;
- struct pmem_data *data = file->private_data;
- int id = get_id(file);
- /* this should never be called as we don't support copying pmem
- * ranges via fork */
- BUG_ON(!has_allocation(file));
- down_write(&data->sem);
- /* remap the garbage pages, forkers don't get access to the data */
- pmem_unmap_pfn_range(id, vma, data, 0, vma->vm_start - vma->vm_end);
- up_write(&data->sem);
-}
-
-static void pmem_vma_close(struct vm_area_struct *vma)
-{
- struct file *file = vma->vm_file;
- struct pmem_data *data = file->private_data;
-
- DLOG("current %u ppid %u file %p count %d\n", current->pid,
- current->parent->pid, file, file_count(file));
- if (unlikely(!is_pmem_file(file) || !has_allocation(file))) {
- printk(KERN_WARNING "pmem: something is very wrong, you are "
- "closing a vm backing an allocation that doesn't "
- "exist!\n");
- return;
- }
- down_write(&data->sem);
- if (data->vma == vma) {
- data->vma = NULL;
- if ((data->flags & PMEM_FLAGS_CONNECTED) &&
- (data->flags & PMEM_FLAGS_SUBMAP))
- data->flags |= PMEM_FLAGS_UNSUBMAP;
- }
- /* the kernel is going to free this vma now anyway */
- up_write(&data->sem);
-}
-
-static struct vm_operations_struct vm_ops = {
- .open = pmem_vma_open,
- .close = pmem_vma_close,
-};
-
-static int pmem_mmap(struct file *file, struct vm_area_struct *vma)
-{
- struct pmem_data *data;
- int index;
- unsigned long vma_size = vma->vm_end - vma->vm_start;
- int ret = 0, id = get_id(file);
-
- if (vma->vm_pgoff || !PMEM_IS_PAGE_ALIGNED(vma_size)) {
-#if PMEM_DEBUG
- printk(KERN_ERR "pmem: mmaps must be at offset zero, aligned"
- " and a multiple of pages_size.\n");
-#endif
- return -EINVAL;
- }
-
- data = file->private_data;
- down_write(&data->sem);
- /* check this file isn't already mmaped, for submaps check this file
- * has never been mmaped */
- if ((data->flags & PMEM_FLAGS_MASTERMAP) ||
- (data->flags & PMEM_FLAGS_SUBMAP) ||
- (data->flags & PMEM_FLAGS_UNSUBMAP)) {
-#if PMEM_DEBUG
- printk(KERN_ERR "pmem: you can only mmap a pmem file once, "
- "this file is already mmaped. %x\n", data->flags);
-#endif
- ret = -EINVAL;
- goto error;
- }
- /* if file->private_data == unalloced, alloc*/
- if (data && data->index == -1) {
- down_write(&pmem[id].bitmap_sem);
- index = pmem_allocate(id, vma->vm_end - vma->vm_start);
- up_write(&pmem[id].bitmap_sem);
- data->index = index;
- }
- /* either no space was available or an error occured */
- if (!has_allocation(file)) {
- ret = -EINVAL;
- printk("pmem: could not find allocation for map.\n");
- goto error;
- }
-
- if (pmem_len(id, data) < vma_size) {
-#if PMEM_DEBUG
- printk(KERN_WARNING "pmem: mmap size [%lu] does not match"
- "size of backing region [%lu].\n", vma_size,
- pmem_len(id, data));
-#endif
- ret = -EINVAL;
- goto error;
- }
-
- vma->vm_pgoff = pmem_start_addr(id, data) >> PAGE_SHIFT;
- vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_page_prot);
-
- if (data->flags & PMEM_FLAGS_CONNECTED) {
- struct pmem_region_node *region_node;
- struct list_head *elt;
- if (pmem_map_garbage(id, vma, data, 0, vma_size)) {
- printk("pmem: mmap failed in kernel!\n");
- ret = -EAGAIN;
- goto error;
- }
- list_for_each(elt, &data->region_list) {
- region_node = list_entry(elt, struct pmem_region_node,
- list);
- DLOG("remapping file: %p %lx %lx\n", file,
- region_node->region.offset,
- region_node->region.len);
- if (pmem_remap_pfn_range(id, vma, data,
- region_node->region.offset,
- region_node->region.len)) {
- ret = -EAGAIN;
- goto error;
- }
- }
- data->flags |= PMEM_FLAGS_SUBMAP;
- get_task_struct(current->group_leader);
- data->task = current->group_leader;
- data->vma = vma;
-#if PMEM_DEBUG
- data->pid = current->pid;
-#endif
- DLOG("submmapped file %p vma %p pid %u\n", file, vma,
- current->pid);
- } else {
- if (pmem_map_pfn_range(id, vma, data, 0, vma_size)) {
- printk(KERN_INFO "pmem: mmap failed in kernel!\n");
- ret = -EAGAIN;
- goto error;
- }
- data->flags |= PMEM_FLAGS_MASTERMAP;
- data->pid = current->pid;
- }
- vma->vm_ops = &vm_ops;
-error:
- up_write(&data->sem);
- return ret;
-}
-
-/* the following are the api for accessing pmem regions by other drivers
- * from inside the kernel */
-int get_pmem_user_addr(struct file *file, unsigned long *start,
- unsigned long *len)
-{
- struct pmem_data *data;
- if (!is_pmem_file(file) || !has_allocation(file)) {
-#if PMEM_DEBUG
- printk(KERN_INFO "pmem: requested pmem data from invalid"
- "file.\n");
-#endif
- return -1;
- }
- data = file->private_data;
- down_read(&data->sem);
- if (data->vma) {
- *start = data->vma->vm_start;
- *len = data->vma->vm_end - data->vma->vm_start;
- } else {
- *start = 0;
- *len = 0;
- }
- up_read(&data->sem);
- return 0;
-}
-
-int get_pmem_addr(struct file *file, unsigned long *start,
- unsigned long *vstart, unsigned long *len)
-{
- struct pmem_data *data;
- int id;
-
- if (!is_pmem_file(file) || !has_allocation(file))
- return -1;
-
- data = file->private_data;
- if (data->index == -1) {
-#if PMEM_DEBUG
- printk(KERN_INFO "pmem: requested pmem data from file with no "
- "allocation.\n");
- return -1;
-#endif
- }
- id = get_id(file);
-
- down_read(&data->sem);
- *start = pmem_start_addr(id, data);
- *len = pmem_len(id, data);
- *vstart = (unsigned long)pmem_start_vaddr(id, data);
- up_read(&data->sem);
-#if PMEM_DEBUG
- down_write(&data->sem);
- data->ref++;
- up_write(&data->sem);
-#endif
- return 0;
-}
-
-int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart,
- unsigned long *len, struct file **filp)
-{
- struct file *file;
-
- file = fget(fd);
- if (unlikely(file == NULL)) {
- printk(KERN_INFO "pmem: requested data from file descriptor "
- "that doesn't exist.");
- return -1;
- }
-
- if (get_pmem_addr(file, start, vstart, len))
- goto end;
-
- if (filp)
- *filp = file;
- return 0;
-end:
- fput(file);
- return -1;
-}
-
-void put_pmem_file(struct file *file)
-{
- struct pmem_data *data;
- int id;
-
- if (!is_pmem_file(file))
- return;
- id = get_id(file);
- data = file->private_data;
-#if PMEM_DEBUG
- down_write(&data->sem);
- if (data->ref == 0) {
- printk("pmem: pmem_put > pmem_get %s (pid %d)\n",
- pmem[id].dev.name, data->pid);
- BUG();
- }
- data->ref--;
- up_write(&data->sem);
-#endif
- fput(file);
-}
-
-void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len)
-{
- struct pmem_data *data;
- int id;
- void *vaddr;
- struct pmem_region_node *region_node;
- struct list_head *elt;
- void *flush_start, *flush_end;
-
- if (!is_pmem_file(file) || !has_allocation(file))
- return;
-
- id = get_id(file);
- data = file->private_data;
- if (!pmem[id].cached)
- return;
-
- down_read(&data->sem);
- vaddr = pmem_start_vaddr(id, data);
- /* if this isn't a submmapped file, flush the whole thing */
- if (unlikely(!(data->flags & PMEM_FLAGS_CONNECTED))) {
- dmac_flush_range(vaddr, vaddr + pmem_len(id, data));
- goto end;
- }
- /* otherwise, flush the region of the file we are drawing */
- list_for_each(elt, &data->region_list) {
- region_node = list_entry(elt, struct pmem_region_node, list);
- if ((offset >= region_node->region.offset) &&
- ((offset + len) <= (region_node->region.offset +
- region_node->region.len))) {
- flush_start = vaddr + region_node->region.offset;
- flush_end = flush_start + region_node->region.len;
- dmac_flush_range(flush_start, flush_end);
- break;
- }
- }
-end:
- up_read(&data->sem);
-}
-
-static int pmem_connect(unsigned long connect, struct file *file)
-{
- struct pmem_data *data = file->private_data;
- struct pmem_data *src_data;
- struct file *src_file;
- int ret = 0, put_needed;
-
- down_write(&data->sem);
- /* retrieve the src file and check it is a pmem file with an alloc */
- src_file = fget_light(connect, &put_needed);
- DLOG("connect %p to %p\n", file, src_file);
- if (!src_file) {
- printk(KERN_INFO "pmem: src file not found!\n");
- ret = -EINVAL;
- goto err_no_file;
- }
- if (unlikely(!is_pmem_file(src_file) || !has_allocation(src_file))) {
- printk(KERN_INFO "pmem: src file is not a pmem file or has no "
- "alloc!\n");
- ret = -EINVAL;
- goto err_bad_file;
- }
- src_data = src_file->private_data;
-
- if (has_allocation(file) && (data->index != src_data->index)) {
- printk(KERN_INFO "pmem: file is already mapped but doesn't "
- "match this src_file!\n");
- ret = -EINVAL;
- goto err_bad_file;
- }
- data->index = src_data->index;
- data->flags |= PMEM_FLAGS_CONNECTED;
- data->master_fd = connect;
- data->master_file = src_file;
-
-err_bad_file:
- fput_light(src_file, put_needed);
-err_no_file:
- up_write(&data->sem);
- return ret;
-}
-
-static void pmem_unlock_data_and_mm(struct pmem_data *data,
- struct mm_struct *mm)
-{
- up_write(&data->sem);
- if (mm != NULL) {
- up_write(&mm->mmap_sem);
- mmput(mm);
- }
-}
-
-static int pmem_lock_data_and_mm(struct file *file, struct pmem_data *data,
- struct mm_struct **locked_mm)
-{
- int ret = 0;
- struct mm_struct *mm = NULL;
- *locked_mm = NULL;
-lock_mm:
- down_read(&data->sem);
- if (PMEM_IS_SUBMAP(data)) {
- mm = get_task_mm(data->task);
- if (!mm) {
-#if PMEM_DEBUG
- printk(KERN_DEBUG "pmem: can't remap task is gone!\n");
-#endif
- up_read(&data->sem);
- return -1;
- }
- }
- up_read(&data->sem);
-
- if (mm)
- down_write(&mm->mmap_sem);
-
- down_write(&data->sem);
- /* check that the file didn't get mmaped before we could take the
- * data sem, this should be safe b/c you can only submap each file
- * once */
- if (PMEM_IS_SUBMAP(data) && !mm) {
- pmem_unlock_data_and_mm(data, mm);
- up_write(&data->sem);
- goto lock_mm;
- }
- /* now check that vma.mm is still there, it could have been
- * deleted by vma_close before we could get the data->sem */
- if ((data->flags & PMEM_FLAGS_UNSUBMAP) && (mm != NULL)) {
- /* might as well release this */
- if (data->flags & PMEM_FLAGS_SUBMAP) {
- put_task_struct(data->task);
- data->task = NULL;
- /* lower the submap flag to show the mm is gone */
- data->flags &= ~(PMEM_FLAGS_SUBMAP);
- }
- pmem_unlock_data_and_mm(data, mm);
- return -1;
- }
- *locked_mm = mm;
- return ret;
-}
-
-int pmem_remap(struct pmem_region *region, struct file *file,
- unsigned operation)
-{
- int ret;
- struct pmem_region_node *region_node;
- struct mm_struct *mm = NULL;
- struct list_head *elt, *elt2;
- int id = get_id(file);
- struct pmem_data *data = file->private_data;
-
- /* pmem region must be aligned on a page boundry */
- if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) ||
- !PMEM_IS_PAGE_ALIGNED(region->len))) {
-#if PMEM_DEBUG
- printk(KERN_DEBUG "pmem: request for unaligned pmem "
- "suballocation %lx %lx\n", region->offset, region->len);
-#endif
- return -EINVAL;
- }
-
- /* if userspace requests a region of len 0, there's nothing to do */
- if (region->len == 0)
- return 0;
-
- /* lock the mm and data */
- ret = pmem_lock_data_and_mm(file, data, &mm);
- if (ret)
- return 0;
-
- /* only the owner of the master file can remap the client fds
- * that back in it */
- if (!is_master_owner(file)) {
-#if PMEM_DEBUG
- printk("pmem: remap requested from non-master process\n");
-#endif
- ret = -EINVAL;
- goto err;
- }
-
- /* check that the requested range is within the src allocation */
- if (unlikely((region->offset > pmem_len(id, data)) ||
- (region->len > pmem_len(id, data)) ||
- (region->offset + region->len > pmem_len(id, data)))) {
-#if PMEM_DEBUG
- printk(KERN_INFO "pmem: suballoc doesn't fit in src_file!\n");
-#endif
- ret = -EINVAL;
- goto err;
- }
-
- if (operation == PMEM_MAP) {
- region_node = kmalloc(sizeof(struct pmem_region_node),
- GFP_KERNEL);
- if (!region_node) {
- ret = -ENOMEM;
-#if PMEM_DEBUG
- printk(KERN_INFO "No space to allocate metadata!");
-#endif
- goto err;
- }
- region_node->region = *region;
- list_add(®ion_node->list, &data->region_list);
- } else if (operation == PMEM_UNMAP) {
- int found = 0;
- list_for_each_safe(elt, elt2, &data->region_list) {
- region_node = list_entry(elt, struct pmem_region_node,
- list);
- if (region->len == 0 ||
- (region_node->region.offset == region->offset &&
- region_node->region.len == region->len)) {
- list_del(elt);
- kfree(region_node);
- found = 1;
- }
- }
- if (!found) {
-#if PMEM_DEBUG
- printk("pmem: Unmap region does not map any mapped "
- "region!");
-#endif
- ret = -EINVAL;
- goto err;
- }
- }
-
- if (data->vma && PMEM_IS_SUBMAP(data)) {
- if (operation == PMEM_MAP)
- ret = pmem_remap_pfn_range(id, data->vma, data,
- region->offset, region->len);
- else if (operation == PMEM_UNMAP)
- ret = pmem_unmap_pfn_range(id, data->vma, data,
- region->offset, region->len);
- }
-
-err:
- pmem_unlock_data_and_mm(data, mm);
- return ret;
-}
-
-static void pmem_revoke(struct file *file, struct pmem_data *data)
-{
- struct pmem_region_node *region_node;
- struct list_head *elt, *elt2;
- struct mm_struct *mm = NULL;
- int id = get_id(file);
- int ret = 0;
-
- data->master_file = NULL;
- ret = pmem_lock_data_and_mm(file, data, &mm);
- /* if lock_data_and_mm fails either the task that mapped the fd, or
- * the vma that mapped it have already gone away, nothing more
- * needs to be done */
- if (ret)
- return;
- /* unmap everything */
- /* delete the regions and region list nothing is mapped any more */
- if (data->vma)
- list_for_each_safe(elt, elt2, &data->region_list) {
- region_node = list_entry(elt, struct pmem_region_node,
- list);
- pmem_unmap_pfn_range(id, data->vma, data,
- region_node->region.offset,
- region_node->region.len);
- list_del(elt);
- kfree(region_node);
- }
- /* delete the master file */
- pmem_unlock_data_and_mm(data, mm);
-}
-
-static void pmem_get_size(struct pmem_region *region, struct file *file)
-{
- struct pmem_data *data = file->private_data;
- int id = get_id(file);
-
- if (!has_allocation(file)) {
- region->offset = 0;
- region->len = 0;
- return;
- } else {
- region->offset = pmem_start_addr(id, data);
- region->len = pmem_len(id, data);
- }
- DLOG("offset %lx len %lx\n", region->offset, region->len);
-}
-
-
-static long pmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct pmem_data *data;
- int id = get_id(file);
-
- switch (cmd) {
- case PMEM_GET_PHYS:
- {
- struct pmem_region region;
- DLOG("get_phys\n");
- if (!has_allocation(file)) {
- region.offset = 0;
- region.len = 0;
- } else {
- data = file->private_data;
- region.offset = pmem_start_addr(id, data);
- region.len = pmem_len(id, data);
- }
- printk(KERN_INFO "pmem: request for physical address "
- "of pmem region from process %d.\n", current->pid);
- if (copy_to_user((void __user *)arg, ®ion,
- sizeof(struct pmem_region)))
- return -EFAULT;
- break;
- }
- case PMEM_MAP:
- {
- struct pmem_region region;
- if (copy_from_user(®ion, (void __user *)arg,
- sizeof(struct pmem_region)))
- return -EFAULT;
- data = file->private_data;
- return pmem_remap(®ion, file, PMEM_MAP);
- }
- break;
- case PMEM_UNMAP:
- {
- struct pmem_region region;
- if (copy_from_user(®ion, (void __user *)arg,
- sizeof(struct pmem_region)))
- return -EFAULT;
- data = file->private_data;
- return pmem_remap(®ion, file, PMEM_UNMAP);
- break;
- }
- case PMEM_GET_SIZE:
- {
- struct pmem_region region;
- DLOG("get_size\n");
- pmem_get_size(®ion, file);
- if (copy_to_user((void __user *)arg, ®ion,
- sizeof(struct pmem_region)))
- return -EFAULT;
- break;
- }
- case PMEM_GET_TOTAL_SIZE:
- {
- struct pmem_region region;
- DLOG("get total size\n");
- region.offset = 0;
- get_id(file);
- region.len = pmem[id].size;
- if (copy_to_user((void __user *)arg, ®ion,
- sizeof(struct pmem_region)))
- return -EFAULT;
- break;
- }
- case PMEM_ALLOCATE:
- {
- if (has_allocation(file))
- return -EINVAL;
- data = file->private_data;
- data->index = pmem_allocate(id, arg);
- break;
- }
- case PMEM_CONNECT:
- DLOG("connect\n");
- return pmem_connect(arg, file);
- break;
- default:
- if (pmem[id].ioctl)
- return pmem[id].ioctl(file, cmd, arg);
- return -EINVAL;
- }
- return 0;
-}
-
-#if PMEM_DEBUG
-static ssize_t debug_open(struct inode *inode, struct file *file)
-{
- file->private_data = inode->i_private;
- return 0;
-}
-
-static ssize_t debug_read(struct file *file, char __user *buf, size_t count,
- loff_t *ppos)
-{
- struct list_head *elt, *elt2;
- struct pmem_data *data;
- struct pmem_region_node *region_node;
- int id = (int)file->private_data;
- const int debug_bufmax = 4096;
- static char buffer[4096];
- int n = 0;
-
- DLOG("debug open\n");
- n = scnprintf(buffer, debug_bufmax,
- "pid #: mapped regions (offset, len) (offset,len)...\n");
-
- down(&pmem[id].data_list_sem);
- list_for_each(elt, &pmem[id].data_list) {
- data = list_entry(elt, struct pmem_data, list);
- down_read(&data->sem);
- n += scnprintf(buffer + n, debug_bufmax - n, "pid %u:",
- data->pid);
- list_for_each(elt2, &data->region_list) {
- region_node = list_entry(elt2, struct pmem_region_node,
- list);
- n += scnprintf(buffer + n, debug_bufmax - n,
- "(%lx,%lx) ",
- region_node->region.offset,
- region_node->region.len);
- }
- n += scnprintf(buffer + n, debug_bufmax - n, "\n");
- up_read(&data->sem);
- }
- up(&pmem[id].data_list_sem);
-
- n++;
- buffer[n] = 0;
- return simple_read_from_buffer(buf, count, ppos, buffer, n);
-}
-
-static struct file_operations debug_fops = {
- .read = debug_read,
- .open = debug_open,
- .llseek = default_llseek,
-};
-#endif
-
-#if 0
-static struct miscdevice pmem_dev = {
- .name = "pmem",
- .fops = &pmem_fops,
-};
-#endif
-
-int pmem_setup(struct android_pmem_platform_data *pdata,
- long (*ioctl)(struct file *, unsigned int, unsigned long),
- int (*release)(struct inode *, struct file *))
-{
- int err = 0;
- int i, index = 0;
- int id = id_count;
- id_count++;
-
- pmem[id].no_allocator = pdata->no_allocator;
- pmem[id].cached = pdata->cached;
- pmem[id].buffered = pdata->buffered;
- pmem[id].base = pdata->start;
- pmem[id].size = pdata->size;
- pmem[id].ioctl = ioctl;
- pmem[id].release = release;
- init_rwsem(&pmem[id].bitmap_sem);
- sema_init(&pmem[id].data_list_sem, 1);
- INIT_LIST_HEAD(&pmem[id].data_list);
- pmem[id].dev.name = pdata->name;
- pmem[id].dev.minor = id;
- pmem[id].dev.fops = &pmem_fops;
- printk(KERN_INFO "%s: %d init\n", pdata->name, pdata->cached);
-
- err = misc_register(&pmem[id].dev);
- if (err) {
- printk(KERN_ALERT "Unable to register pmem driver!\n");
- goto err_cant_register_device;
- }
- pmem[id].num_entries = pmem[id].size / PMEM_MIN_ALLOC;
-
- pmem[id].bitmap = kcalloc(pmem[id].num_entries,
- sizeof(struct pmem_bits), GFP_KERNEL);
- if (!pmem[id].bitmap)
- goto err_no_mem_for_metadata;
-
- for (i = sizeof(pmem[id].num_entries) * 8 - 1; i >= 0; i--) {
- if ((pmem[id].num_entries) & 1<<i) {
- PMEM_ORDER(id, index) = i;
- index = PMEM_NEXT_INDEX(id, index);
- }
- }
-
- if (pmem[id].cached)
- pmem[id].vbase = ioremap_cached(pmem[id].base,
- pmem[id].size);
-#ifdef ioremap_ext_buffered
- else if (pmem[id].buffered)
- pmem[id].vbase = ioremap_ext_buffered(pmem[id].base,
- pmem[id].size);
-#endif
- else
- pmem[id].vbase = ioremap(pmem[id].base, pmem[id].size);
-
- if (pmem[id].vbase == 0)
- goto error_cant_remap;
-
- pmem[id].garbage_pfn = page_to_pfn(alloc_page(GFP_KERNEL));
- if (pmem[id].no_allocator)
- pmem[id].allocated = 0;
-
-#if PMEM_DEBUG
- debugfs_create_file(pdata->name, S_IFREG | S_IRUGO, NULL, (void *)id,
- &debug_fops);
-#endif
- return 0;
-error_cant_remap:
- kfree(pmem[id].bitmap);
-err_no_mem_for_metadata:
- misc_deregister(&pmem[id].dev);
-err_cant_register_device:
- return -1;
-}
-
-static int pmem_probe(struct platform_device *pdev)
-{
- struct android_pmem_platform_data *pdata;
-
- if (!pdev || !pdev->dev.platform_data) {
- printk(KERN_ALERT "Unable to probe pmem!\n");
- return -1;
- }
- pdata = pdev->dev.platform_data;
- return pmem_setup(pdata, NULL, NULL);
-}
-
-
-static int pmem_remove(struct platform_device *pdev)
-{
- int id = pdev->id;
- __free_page(pfn_to_page(pmem[id].garbage_pfn));
- misc_deregister(&pmem[id].dev);
- return 0;
-}
-
-static struct platform_driver pmem_driver = {
- .probe = pmem_probe,
- .remove = pmem_remove,
- .driver = { .name = "android_pmem" }
-};
-
-
-static int __init pmem_init(void)
-{
- return platform_driver_register(&pmem_driver);
-}
-
-static void __exit pmem_exit(void)
-{
- platform_driver_unregister(&pmem_driver);
-}
-
-module_init(pmem_init);
-module_exit(pmem_exit);
-
+++ /dev/null
-ccflags-y:=-Idrivers/staging/dream/include
-obj-y += adsp.o
-ifeq ($(CONFIG_MSM_AMSS_VERSION_6350),y)
-obj-y += adsp_info.o
-obj-y += audio_evrc.o audio_qcelp.o audio_amrnb.o audio_aac.o
-else
-obj-y += adsp_6225.o
-endif
-
-obj-y += adsp_driver.o
-obj-y += adsp_video_verify_cmd.o
-obj-y += adsp_videoenc_verify_cmd.o
-obj-y += adsp_jpeg_verify_cmd.o adsp_jpeg_patch_event.o
-obj-y += adsp_vfe_verify_cmd.o adsp_vfe_patch_event.o
-obj-y += adsp_lpm_verify_cmd.o
-obj-y += audio_out.o audio_in.o audio_mp3.o audmgr.o audpp.o
-obj-y += snd.o
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp.c
- *
- * Register/Interrupt access for userspace aDSP library.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- * Author: Iliyan Malchev <ibm@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/* TODO:
- * - move shareable rpc code outside of adsp.c
- * - general solution for virt->phys patchup
- * - queue IDs should be relative to modules
- * - disallow access to non-associated queues
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/kthread.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <linux/wait.h>
-
-static inline void prevent_suspend(void)
-{
-}
-static inline void allow_suspend(void)
-{
-}
-
-#include <linux/io.h>
-#include <mach/msm_iomap.h>
-#include "adsp.h"
-
-#define INT_ADSP INT_ADSP_A9_A11
-
-static struct adsp_info adsp_info;
-static struct msm_rpc_endpoint *rpc_cb_server_client;
-static struct msm_adsp_module *adsp_modules;
-static int adsp_open_count;
-static DEFINE_MUTEX(adsp_open_lock);
-
-/* protect interactions with the ADSP command/message queue */
-static spinlock_t adsp_cmd_lock;
-
-static uint32_t current_image = -1;
-
-void adsp_set_image(struct adsp_info *info, uint32_t image)
-{
- current_image = image;
-}
-
-/*
- * Checks whether the module_id is available in the
- * module_entries table.If module_id is available returns `0`.
- * If module_id is not available returns `-ENXIO`.
- */
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-static int32_t adsp_validate_module(uint32_t module_id)
-{
- uint32_t *ptr;
- uint32_t module_index;
- uint32_t num_mod_entries;
-
- ptr = adsp_info.init_info_ptr->module_entries;
- num_mod_entries = adsp_info.init_info_ptr->module_table_size;
-
- for (module_index = 0; module_index < num_mod_entries; module_index++)
- if (module_id == ptr[module_index])
- return 0;
-
- return -ENXIO;
-}
-#else
-static inline int32_t adsp_validate_module(uint32_t module_id) { return 0; }
-#endif
-
-uint32_t adsp_get_module(struct adsp_info *info, uint32_t task)
-{
- BUG_ON(current_image == -1UL);
- return info->task_to_module[current_image][task];
-}
-
-uint32_t adsp_get_queue_offset(struct adsp_info *info, uint32_t queue_id)
-{
- BUG_ON(current_image == -1UL);
- return info->queue_offset[current_image][queue_id];
-}
-
-static int rpc_adsp_rtos_app_to_modem(uint32_t cmd, uint32_t module,
- struct msm_adsp_module *adsp_module)
-{
- int rc;
- struct rpc_adsp_rtos_app_to_modem_args_t rpc_req;
- struct rpc_reply_hdr *rpc_rsp;
-
- msm_rpc_setup_req(&rpc_req.hdr,
- RPC_ADSP_RTOS_ATOM_PROG,
- msm_rpc_get_vers(adsp_module->rpc_client),
- RPC_ADSP_RTOS_APP_TO_MODEM_PROC);
-
- rpc_req.gotit = cpu_to_be32(1);
- rpc_req.cmd = cpu_to_be32(cmd);
- rpc_req.proc_id = cpu_to_be32(RPC_ADSP_RTOS_PROC_APPS);
- rpc_req.module = cpu_to_be32(module);
- rc = msm_rpc_write(adsp_module->rpc_client, &rpc_req, sizeof(rpc_req));
- if (rc < 0) {
- pr_err("adsp: could not send RPC request: %d\n", rc);
- return rc;
- }
-
- rc = msm_rpc_read(adsp_module->rpc_client,
- (void **)&rpc_rsp, -1, (5*HZ));
- if (rc < 0) {
- pr_err("adsp: error receiving RPC reply: %d (%d)\n",
- rc, -ERESTARTSYS);
- return rc;
- }
-
- if (be32_to_cpu(rpc_rsp->reply_stat) != RPCMSG_REPLYSTAT_ACCEPTED) {
- pr_err("adsp: RPC call was denied!\n");
- kfree(rpc_rsp);
- return -EPERM;
- }
-
- if (be32_to_cpu(rpc_rsp->data.acc_hdr.accept_stat) !=
- RPC_ACCEPTSTAT_SUCCESS) {
- pr_err("adsp error: RPC call was not successful (%d)\n",
- be32_to_cpu(rpc_rsp->data.acc_hdr.accept_stat));
- kfree(rpc_rsp);
- return -EINVAL;
- }
-
- kfree(rpc_rsp);
- return 0;
-}
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-static int get_module_index(uint32_t id)
-{
- int mod_idx;
- for (mod_idx = 0; mod_idx < adsp_info.module_count; mod_idx++)
- if (adsp_info.module[mod_idx].id == id)
- return mod_idx;
-
- return -ENXIO;
-}
-#endif
-
-static struct msm_adsp_module *find_adsp_module_by_id(
- struct adsp_info *info, uint32_t id)
-{
- if (id > info->max_module_id) {
- return NULL;
- } else {
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- id = get_module_index(id);
- if (id < 0)
- return NULL;
-#endif
- return info->id_to_module[id];
- }
-}
-
-static struct msm_adsp_module *find_adsp_module_by_name(
- struct adsp_info *info, const char *name)
-{
- unsigned n;
- for (n = 0; n < info->module_count; n++)
- if (!strcmp(name, adsp_modules[n].name))
- return adsp_modules + n;
- return NULL;
-}
-
-static int adsp_rpc_init(struct msm_adsp_module *adsp_module)
-{
- /* remove the original connect once compatible support is complete */
- adsp_module->rpc_client = msm_rpc_connect(
- RPC_ADSP_RTOS_ATOM_PROG,
- RPC_ADSP_RTOS_ATOM_VERS,
- MSM_RPC_UNINTERRUPTIBLE);
-
- if (IS_ERR(adsp_module->rpc_client)) {
- int rc = PTR_ERR(adsp_module->rpc_client);
- adsp_module->rpc_client = 0;
- pr_err("adsp: could not open rpc client: %d\n", rc);
- return rc;
- }
-
- return 0;
-}
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-/*
- * Send RPC_ADSP_RTOS_CMD_GET_INIT_INFO cmd to ARM9 and get
- * queue offsets and module entries (init info) as part of the event.
- */
-static void msm_get_init_info(void)
-{
- int rc;
- struct rpc_adsp_rtos_app_to_modem_args_t rpc_req;
-
- adsp_info.init_info_rpc_client = msm_rpc_connect(
- RPC_ADSP_RTOS_ATOM_PROG,
- RPC_ADSP_RTOS_ATOM_VERS,
- MSM_RPC_UNINTERRUPTIBLE);
- if (IS_ERR(adsp_info.init_info_rpc_client)) {
- rc = PTR_ERR(adsp_info.init_info_rpc_client);
- adsp_info.init_info_rpc_client = 0;
- pr_err("adsp: could not open rpc client: %d\n", rc);
- return;
- }
-
- msm_rpc_setup_req(&rpc_req.hdr,
- RPC_ADSP_RTOS_ATOM_PROG,
- msm_rpc_get_vers(adsp_info.init_info_rpc_client),
- RPC_ADSP_RTOS_APP_TO_MODEM_PROC);
-
- rpc_req.gotit = cpu_to_be32(1);
- rpc_req.cmd = cpu_to_be32(RPC_ADSP_RTOS_CMD_GET_INIT_INFO);
- rpc_req.proc_id = cpu_to_be32(RPC_ADSP_RTOS_PROC_APPS);
- rpc_req.module = 0;
-
- rc = msm_rpc_write(adsp_info.init_info_rpc_client,
- &rpc_req, sizeof(rpc_req));
- if (rc < 0)
- pr_err("adsp: could not send RPC request: %d\n", rc);
-}
-#endif
-
-int msm_adsp_get(const char *name, struct msm_adsp_module **out,
- struct msm_adsp_ops *ops, void *driver_data)
-{
- struct msm_adsp_module *module;
- int rc = 0;
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- static uint32_t init_info_cmd_sent;
- if (!init_info_cmd_sent) {
- msm_get_init_info();
- init_waitqueue_head(&adsp_info.init_info_wait);
- rc = wait_event_timeout(adsp_info.init_info_wait,
- adsp_info.init_info_state == ADSP_STATE_INIT_INFO,
- 5 * HZ);
- if (!rc) {
- pr_info("adsp: INIT_INFO failed\n");
- return -ETIMEDOUT;
- }
- init_info_cmd_sent++;
- }
-#endif
-
- module = find_adsp_module_by_name(&adsp_info, name);
- if (!module)
- return -ENODEV;
-
- mutex_lock(&module->lock);
- pr_info("adsp: opening module %s\n", module->name);
- if (module->open_count++ == 0 && module->clk)
- clk_enable(module->clk);
-
- mutex_lock(&adsp_open_lock);
- if (adsp_open_count++ == 0) {
- enable_irq(INT_ADSP);
- prevent_suspend();
- }
- mutex_unlock(&adsp_open_lock);
-
- if (module->ops) {
- rc = -EBUSY;
- goto done;
- }
-
- rc = adsp_rpc_init(module);
- if (rc)
- goto done;
-
- module->ops = ops;
- module->driver_data = driver_data;
- *out = module;
- rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_REGISTER_APP,
- module->id, module);
- if (rc) {
- module->ops = NULL;
- module->driver_data = NULL;
- *out = NULL;
- pr_err("adsp: REGISTER_APP failed\n");
- goto done;
- }
-
- pr_info("adsp: module %s has been registered\n", module->name);
-
-done:
- mutex_lock(&adsp_open_lock);
- if (rc && --adsp_open_count == 0) {
- disable_irq(INT_ADSP);
- allow_suspend();
- }
- if (rc && --module->open_count == 0 && module->clk)
- clk_disable(module->clk);
- mutex_unlock(&adsp_open_lock);
- mutex_unlock(&module->lock);
- return rc;
-}
-EXPORT_SYMBOL(msm_adsp_get);
-
-static int msm_adsp_disable_locked(struct msm_adsp_module *module);
-
-void msm_adsp_put(struct msm_adsp_module *module)
-{
- unsigned long flags;
-
- mutex_lock(&module->lock);
- if (--module->open_count == 0 && module->clk)
- clk_disable(module->clk);
- if (module->ops) {
- pr_info("adsp: closing module %s\n", module->name);
-
- /* lock to ensure a dsp event cannot be delivered
- * during or after removal of the ops and driver_data
- */
- spin_lock_irqsave(&adsp_cmd_lock, flags);
- module->ops = NULL;
- module->driver_data = NULL;
- spin_unlock_irqrestore(&adsp_cmd_lock, flags);
-
- if (module->state != ADSP_STATE_DISABLED) {
- pr_info("adsp: disabling module %s\n", module->name);
- msm_adsp_disable_locked(module);
- }
-
- msm_rpc_close(module->rpc_client);
- module->rpc_client = 0;
- if (--adsp_open_count == 0) {
- disable_irq(INT_ADSP);
- allow_suspend();
- pr_info("adsp: disable interrupt\n");
- }
- } else {
- pr_info("adsp: module %s is already closed\n", module->name);
- }
- mutex_unlock(&module->lock);
-}
-EXPORT_SYMBOL(msm_adsp_put);
-
-/* this should be common code with rpc_servers.c */
-static int rpc_send_accepted_void_reply(struct msm_rpc_endpoint *client,
- uint32_t xid, uint32_t accept_status)
-{
- int rc = 0;
- uint8_t reply_buf[sizeof(struct rpc_reply_hdr)];
- struct rpc_reply_hdr *reply = (struct rpc_reply_hdr *)reply_buf;
-
- reply->xid = cpu_to_be32(xid);
- reply->type = cpu_to_be32(1); /* reply */
- reply->reply_stat = cpu_to_be32(RPCMSG_REPLYSTAT_ACCEPTED);
-
- reply->data.acc_hdr.accept_stat = cpu_to_be32(accept_status);
- reply->data.acc_hdr.verf_flavor = 0;
- reply->data.acc_hdr.verf_length = 0;
-
- rc = msm_rpc_write(rpc_cb_server_client, reply_buf, sizeof(reply_buf));
- if (rc < 0)
- pr_err("adsp: could not write RPC response: %d\n", rc);
- return rc;
-}
-
-int __msm_adsp_write(struct msm_adsp_module *module, unsigned dsp_queue_addr,
- void *cmd_buf, size_t cmd_size)
-{
- uint32_t ctrl_word;
- uint32_t dsp_q_addr;
- uint32_t dsp_addr;
- uint32_t cmd_id = 0;
- int cnt = 0;
- int ret_status = 0;
- unsigned long flags;
- struct adsp_info *info = module->info;
-
- spin_lock_irqsave(&adsp_cmd_lock, flags);
-
- if (module->state != ADSP_STATE_ENABLED) {
- spin_unlock_irqrestore(&adsp_cmd_lock, flags);
- pr_err("adsp: module %s not enabled before write\n",
- module->name);
- return -ENODEV;
- }
- if (adsp_validate_module(module->id)) {
- spin_unlock_irqrestore(&adsp_cmd_lock, flags);
- pr_info("adsp: module id validation failed %s %d\n",
- module->name, module->id);
- return -ENXIO;
- }
- dsp_q_addr = adsp_get_queue_offset(info, dsp_queue_addr);
- dsp_q_addr &= ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M;
-
- /* Poll until the ADSP is ready to accept a command.
- * Wait for 100us, return error if it's not responding.
- * If this returns an error, we need to disable ALL modules and
- * then retry.
- */
- while (((ctrl_word = readl(info->write_ctrl)) &
- ADSP_RTOS_WRITE_CTRL_WORD_READY_M) !=
- ADSP_RTOS_WRITE_CTRL_WORD_READY_V) {
- if (cnt > 100) {
- pr_err("adsp: timeout waiting for DSP write ready\n");
- ret_status = -EIO;
- goto fail;
- }
- pr_warning("adsp: waiting for DSP write ready\n");
- udelay(1);
- cnt++;
- }
-
- /* Set the mutex bits */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M);
- ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V;
-
- /* Clear the command bits */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_CMD_M);
-
- /* Set the queue address bits */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M);
- ctrl_word |= dsp_q_addr;
-
- writel(ctrl_word, info->write_ctrl);
-
- /* Generate an interrupt to the DSP. This notifies the DSP that
- * we are about to send a command on this particular queue. The
- * DSP will in response change its state.
- */
- writel(1, info->send_irq);
-
- /* Poll until the adsp responds to the interrupt; this does not
- * generate an interrupt from the adsp. This should happen within
- * 5ms.
- */
- cnt = 0;
- while ((readl(info->write_ctrl) &
- ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M) ==
- ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V) {
- if (cnt > 5000) {
- pr_err("adsp: timeout waiting for adsp ack\n");
- ret_status = -EIO;
- goto fail;
- }
- udelay(1);
- cnt++;
- }
-
- /* Read the ctrl word */
- ctrl_word = readl(info->write_ctrl);
-
- if ((ctrl_word & ADSP_RTOS_WRITE_CTRL_WORD_STATUS_M) !=
- ADSP_RTOS_WRITE_CTRL_WORD_NO_ERR_V) {
- ret_status = -EAGAIN;
- goto fail;
- }
-
- /* Ctrl word status bits were 00, no error in the ctrl word */
-
- /* Get the DSP buffer address */
- dsp_addr = (ctrl_word & ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M) +
- (uint32_t)MSM_AD5_BASE;
-
- if (dsp_addr < (uint32_t)(MSM_AD5_BASE + QDSP_RAMC_OFFSET)) {
- uint16_t *buf_ptr = (uint16_t *) cmd_buf;
- uint16_t *dsp_addr16 = (uint16_t *)dsp_addr;
- cmd_size /= sizeof(uint16_t);
-
- /* Save the command ID */
- cmd_id = (uint32_t) buf_ptr[0];
-
- /* Copy the command to DSP memory */
- cmd_size++;
- while (--cmd_size)
- *dsp_addr16++ = *buf_ptr++;
- } else {
- uint32_t *buf_ptr = (uint32_t *) cmd_buf;
- uint32_t *dsp_addr32 = (uint32_t *)dsp_addr;
- cmd_size /= sizeof(uint32_t);
-
- /* Save the command ID */
- cmd_id = buf_ptr[0];
-
- cmd_size++;
- while (--cmd_size)
- *dsp_addr32++ = *buf_ptr++;
- }
-
- /* Set the mutex bits */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M);
- ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V;
-
- /* Set the command bits to write done */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_CMD_M);
- ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_DONE_V;
-
- /* Set the queue address bits */
- ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M);
- ctrl_word |= dsp_q_addr;
-
- writel(ctrl_word, info->write_ctrl);
-
- /* Generate an interrupt to the DSP. It does not respond with
- * an interrupt, and we do not need to wait for it to
- * acknowledge, because it will hold the mutex lock until it's
- * ready to receive more commands again.
- */
- writel(1, info->send_irq);
-
- module->num_commands++;
-
-fail:
- spin_unlock_irqrestore(&adsp_cmd_lock, flags);
- return ret_status;
-}
-EXPORT_SYMBOL(msm_adsp_write);
-
-int msm_adsp_write(struct msm_adsp_module *module, unsigned dsp_queue_addr,
- void *cmd_buf, size_t cmd_size)
-{
- int rc, retries = 0;
- do {
- rc = __msm_adsp_write(module, dsp_queue_addr, cmd_buf, cmd_size);
- if (rc == -EAGAIN)
- udelay(10);
- } while(rc == -EAGAIN && retries++ < 100);
- if (retries > 50)
- pr_warning("adsp: %s command took %d attempts: rc %d\n",
- module->name, retries, rc);
- return rc;
-}
-
-#ifdef CONFIG_MSM_ADSP_REPORT_EVENTS
-static void *modem_event_addr;
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-static void read_modem_event(void *buf, size_t len)
-{
- uint32_t *dptr = buf;
- struct rpc_adsp_rtos_modem_to_app_args_t *sptr;
- struct adsp_rtos_mp_mtoa_type *pkt_ptr;
-
- sptr = modem_event_addr;
- pkt_ptr = &sptr->mtoa_pkt.adsp_rtos_mp_mtoa_data.mp_mtoa_packet;
-
- dptr[0] = be32_to_cpu(sptr->mtoa_pkt.mp_mtoa_header.event);
- dptr[1] = be32_to_cpu(pkt_ptr->module);
- dptr[2] = be32_to_cpu(pkt_ptr->image);
-}
-#else
-static void read_modem_event(void *buf, size_t len)
-{
- uint32_t *dptr = buf;
- struct rpc_adsp_rtos_modem_to_app_args_t *sptr =
- modem_event_addr;
- dptr[0] = be32_to_cpu(sptr->event);
- dptr[1] = be32_to_cpu(sptr->module);
- dptr[2] = be32_to_cpu(sptr->image);
-}
-#endif /* CONFIG_MSM_AMSS_VERSION >= 6350 */
-#endif /* CONFIG_MSM_ADSP_REPORT_EVENTS */
-
-static void handle_adsp_rtos_mtoa_app(struct rpc_request_hdr *req)
-{
- struct rpc_adsp_rtos_modem_to_app_args_t *args =
- (struct rpc_adsp_rtos_modem_to_app_args_t *)req;
- uint32_t event;
- uint32_t proc_id;
- uint32_t module_id;
- uint32_t image;
- struct msm_adsp_module *module;
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- struct adsp_rtos_mp_mtoa_type *pkt_ptr =
- &args->mtoa_pkt.adsp_rtos_mp_mtoa_data.mp_mtoa_packet;
-
- event = be32_to_cpu(args->mtoa_pkt.mp_mtoa_header.event);
- proc_id = be32_to_cpu(args->mtoa_pkt.mp_mtoa_header.proc_id);
- module_id = be32_to_cpu(pkt_ptr->module);
- image = be32_to_cpu(pkt_ptr->image);
-
- if (be32_to_cpu(args->mtoa_pkt.desc_field) == RPC_ADSP_RTOS_INIT_INFO) {
- struct queue_to_offset_type *qptr;
- struct queue_to_offset_type *qtbl;
- uint32_t *mptr;
- uint32_t *mtbl;
- uint32_t q_idx;
- uint32_t num_entries;
- uint32_t entries_per_image;
- struct adsp_rtos_mp_mtoa_init_info_type *iptr;
- struct adsp_rtos_mp_mtoa_init_info_type *sptr;
- int32_t i_no, e_idx;
-
- pr_info("adsp:INIT_INFO Event\n");
- sptr = &args->mtoa_pkt.adsp_rtos_mp_mtoa_data.
- mp_mtoa_init_packet;
-
- iptr = adsp_info.init_info_ptr;
- iptr->image_count = be32_to_cpu(sptr->image_count);
- iptr->num_queue_offsets = be32_to_cpu(sptr->num_queue_offsets);
- num_entries = iptr->num_queue_offsets;
- qptr = &sptr->queue_offsets_tbl[0][0];
- for (i_no = 0; i_no < iptr->image_count; i_no++) {
- qtbl = &iptr->queue_offsets_tbl[i_no][0];
- for (e_idx = 0; e_idx < num_entries; e_idx++) {
- qtbl[e_idx].offset = be32_to_cpu(qptr->offset);
- qtbl[e_idx].queue = be32_to_cpu(qptr->queue);
- q_idx = be32_to_cpu(qptr->queue);
- iptr->queue_offsets[i_no][q_idx] =
- qtbl[e_idx].offset;
- qptr++;
- }
- }
-
- num_entries = be32_to_cpu(sptr->num_task_module_entries);
- iptr->num_task_module_entries = num_entries;
- entries_per_image = num_entries / iptr->image_count;
- mptr = &sptr->task_to_module_tbl[0][0];
- for (i_no = 0; i_no < iptr->image_count; i_no++) {
- mtbl = &iptr->task_to_module_tbl[i_no][0];
- for (e_idx = 0; e_idx < entries_per_image; e_idx++) {
- mtbl[e_idx] = be32_to_cpu(*mptr);
- mptr++;
- }
- }
-
- iptr->module_table_size = be32_to_cpu(sptr->module_table_size);
- mptr = &sptr->module_entries[0];
- for (i_no = 0; i_no < iptr->module_table_size; i_no++)
- iptr->module_entries[i_no] = be32_to_cpu(mptr[i_no]);
- adsp_info.init_info_state = ADSP_STATE_INIT_INFO;
- rpc_send_accepted_void_reply(rpc_cb_server_client, req->xid,
- RPC_ACCEPTSTAT_SUCCESS);
- wake_up(&adsp_info.init_info_wait);
-
- return;
- }
-#else
- event = be32_to_cpu(args->event);
- proc_id = be32_to_cpu(args->proc_id);
- module_id = be32_to_cpu(args->module);
- image = be32_to_cpu(args->image);
-#endif
-
- pr_info("adsp: rpc event=%d, proc_id=%d, module=%d, image=%d\n",
- event, proc_id, module_id, image);
-
- module = find_adsp_module_by_id(&adsp_info, module_id);
- if (!module) {
- pr_err("adsp: module %d is not supported!\n", module_id);
- rpc_send_accepted_void_reply(rpc_cb_server_client, req->xid,
- RPC_ACCEPTSTAT_GARBAGE_ARGS);
- return;
- }
-
- mutex_lock(&module->lock);
- switch (event) {
- case RPC_ADSP_RTOS_MOD_READY:
- pr_info("adsp: module %s: READY\n", module->name);
- module->state = ADSP_STATE_ENABLED;
- wake_up(&module->state_wait);
- adsp_set_image(module->info, image);
- break;
- case RPC_ADSP_RTOS_MOD_DISABLE:
- pr_info("adsp: module %s: DISABLED\n", module->name);
- module->state = ADSP_STATE_DISABLED;
- wake_up(&module->state_wait);
- break;
- case RPC_ADSP_RTOS_SERVICE_RESET:
- pr_info("adsp: module %s: SERVICE_RESET\n", module->name);
- module->state = ADSP_STATE_DISABLED;
- wake_up(&module->state_wait);
- break;
- case RPC_ADSP_RTOS_CMD_SUCCESS:
- pr_info("adsp: module %s: CMD_SUCCESS\n", module->name);
- break;
- case RPC_ADSP_RTOS_CMD_FAIL:
- pr_info("adsp: module %s: CMD_FAIL\n", module->name);
- break;
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- case RPC_ADSP_RTOS_DISABLE_FAIL:
- pr_info("adsp: module %s: DISABLE_FAIL\n", module->name);
- break;
-#endif
- default:
- pr_info("adsp: unknown event %d\n", event);
- rpc_send_accepted_void_reply(rpc_cb_server_client, req->xid,
- RPC_ACCEPTSTAT_GARBAGE_ARGS);
- mutex_unlock(&module->lock);
- return;
- }
- rpc_send_accepted_void_reply(rpc_cb_server_client, req->xid,
- RPC_ACCEPTSTAT_SUCCESS);
- mutex_unlock(&module->lock);
-#ifdef CONFIG_MSM_ADSP_REPORT_EVENTS
- modem_event_addr = (uint32_t *)req;
- module->ops->event(module->driver_data, EVENT_MSG_ID,
- EVENT_LEN, read_modem_event);
-#endif
-}
-
-static int handle_adsp_rtos_mtoa(struct rpc_request_hdr *req)
-{
- switch (req->procedure) {
- case RPC_ADSP_RTOS_MTOA_NULL_PROC:
- rpc_send_accepted_void_reply(rpc_cb_server_client,
- req->xid,
- RPC_ACCEPTSTAT_SUCCESS);
- break;
- case RPC_ADSP_RTOS_MODEM_TO_APP_PROC:
- handle_adsp_rtos_mtoa_app(req);
- break;
- default:
- pr_err("adsp: unknowned proc %d\n", req->procedure);
- rpc_send_accepted_void_reply(
- rpc_cb_server_client, req->xid,
- RPC_ACCEPTSTAT_PROC_UNAVAIL);
- break;
- }
- return 0;
-}
-
-/* this should be common code with rpc_servers.c */
-static int adsp_rpc_thread(void *data)
-{
- void *buffer;
- struct rpc_request_hdr *req;
- int rc;
-
- do {
- rc = msm_rpc_read(rpc_cb_server_client, &buffer, -1, -1);
- if (rc < 0) {
- pr_err("adsp: could not read rpc: %d\n", rc);
- break;
- }
- req = (struct rpc_request_hdr *)buffer;
-
- req->type = be32_to_cpu(req->type);
- req->xid = be32_to_cpu(req->xid);
- req->rpc_vers = be32_to_cpu(req->rpc_vers);
- req->prog = be32_to_cpu(req->prog);
- req->vers = be32_to_cpu(req->vers);
- req->procedure = be32_to_cpu(req->procedure);
-
- if (req->type != 0)
- goto bad_rpc;
- if (req->rpc_vers != 2)
- goto bad_rpc;
- if (req->prog != RPC_ADSP_RTOS_MTOA_PROG)
- goto bad_rpc;
- if (req->vers != RPC_ADSP_RTOS_MTOA_VERS)
- goto bad_rpc;
-
- handle_adsp_rtos_mtoa(req);
- kfree(buffer);
- continue;
-
-bad_rpc:
- pr_err("adsp: bogus rpc from modem\n");
- kfree(buffer);
- } while (1);
-
- do_exit(0);
-}
-
-static size_t read_event_size;
-static void *read_event_addr;
-
-static void read_event_16(void *buf, size_t len)
-{
- uint16_t *dst = buf;
- uint16_t *src = read_event_addr;
- len /= 2;
- if (len > read_event_size)
- len = read_event_size;
- while (len--)
- *dst++ = *src++;
-}
-
-static void read_event_32(void *buf, size_t len)
-{
- uint32_t *dst = buf;
- uint32_t *src = read_event_addr;
- len /= 2;
- if (len > read_event_size)
- len = read_event_size;
- while (len--)
- *dst++ = *src++;
-}
-
-static int adsp_rtos_read_ctrl_word_cmd_tast_to_h_v(
- struct adsp_info *info, void *dsp_addr)
-{
- struct msm_adsp_module *module;
- unsigned rtos_task_id;
- unsigned msg_id;
- unsigned msg_length;
- void (*func)(void *, size_t);
-
- if (dsp_addr >= (void *)(MSM_AD5_BASE + QDSP_RAMC_OFFSET)) {
- uint32_t *dsp_addr32 = dsp_addr;
- uint32_t tmp = *dsp_addr32++;
- rtos_task_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M) >> 8;
- msg_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M);
- read_event_size = tmp >> 16;
- read_event_addr = dsp_addr32;
- msg_length = read_event_size * sizeof(uint32_t);
- func = read_event_32;
- } else {
- uint16_t *dsp_addr16 = dsp_addr;
- uint16_t tmp = *dsp_addr16++;
- rtos_task_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M) >> 8;
- msg_id = tmp & ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M;
- read_event_size = *dsp_addr16++;
- read_event_addr = dsp_addr16;
- msg_length = read_event_size * sizeof(uint16_t);
- func = read_event_16;
- }
-
- if (rtos_task_id > info->max_task_id) {
- pr_err("adsp: bogus task id %d\n", rtos_task_id);
- return 0;
- }
- module = find_adsp_module_by_id(info,
- adsp_get_module(info, rtos_task_id));
-
- if (!module) {
- pr_err("adsp: no module for task id %d\n", rtos_task_id);
- return 0;
- }
-
- module->num_events++;
-
- if (!module->ops) {
- pr_err("adsp: module %s is not open\n", module->name);
- return 0;
- }
-
- module->ops->event(module->driver_data, msg_id, msg_length, func);
- return 0;
-}
-
-static int adsp_get_event(struct adsp_info *info)
-{
- uint32_t ctrl_word;
- uint32_t ready;
- void *dsp_addr;
- uint32_t cmd_type;
- int cnt;
- unsigned long flags;
- int rc = 0;
-
- spin_lock_irqsave(&adsp_cmd_lock, flags);
-
- /* Whenever the DSP has a message, it updates this control word
- * and generates an interrupt. When we receive the interrupt, we
- * read this register to find out what ADSP task the command is
- * comming from.
- *
- * The ADSP should *always* be ready on the first call, but the
- * irq handler calls us in a loop (to handle back-to-back command
- * processing), so we give the DSP some time to return to the
- * ready state. The DSP will not issue another IRQ for events
- * pending between the first IRQ and the event queue being drained,
- * unfortunately.
- */
-
- for (cnt = 0; cnt < 10; cnt++) {
- ctrl_word = readl(info->read_ctrl);
-
- if ((ctrl_word & ADSP_RTOS_READ_CTRL_WORD_FLAG_M) ==
- ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_CONT_V)
- goto ready;
-
- udelay(10);
- }
- pr_warning("adsp: not ready after 100uS\n");
- rc = -EBUSY;
- goto done;
-
-ready:
- /* Here we check to see if there are pending messages. If there are
- * none, we siply return -EAGAIN to indicate that there are no more
- * messages pending.
- */
- ready = ctrl_word & ADSP_RTOS_READ_CTRL_WORD_READY_M;
- if ((ready != ADSP_RTOS_READ_CTRL_WORD_READY_V) &&
- (ready != ADSP_RTOS_READ_CTRL_WORD_CONT_V)) {
- rc = -EAGAIN;
- goto done;
- }
-
- /* DSP says that there are messages waiting for the host to read */
-
- /* Get the Command Type */
- cmd_type = ctrl_word & ADSP_RTOS_READ_CTRL_WORD_CMD_TYPE_M;
-
- /* Get the DSP buffer address */
- dsp_addr = (void *)((ctrl_word &
- ADSP_RTOS_READ_CTRL_WORD_DSP_ADDR_M) +
- (uint32_t)MSM_AD5_BASE);
-
- /* We can only handle Task-to-Host messages */
- if (cmd_type != ADSP_RTOS_READ_CTRL_WORD_CMD_TASK_TO_H_V) {
- pr_err("adsp: unknown dsp cmd_type %d\n", cmd_type);
- rc = -EIO;
- goto done;
- }
-
- adsp_rtos_read_ctrl_word_cmd_tast_to_h_v(info, dsp_addr);
-
- ctrl_word = readl(info->read_ctrl);
- ctrl_word &= ~ADSP_RTOS_READ_CTRL_WORD_READY_M;
-
- /* Write ctrl word to the DSP */
- writel(ctrl_word, info->read_ctrl);
-
- /* Generate an interrupt to the DSP */
- writel(1, info->send_irq);
-
-done:
- spin_unlock_irqrestore(&adsp_cmd_lock, flags);
- return rc;
-}
-
-static irqreturn_t adsp_irq_handler(int irq, void *data)
-{
- struct adsp_info *info = &adsp_info;
- int cnt = 0;
- for (cnt = 0; cnt < 10; cnt++)
- if (adsp_get_event(info) < 0)
- break;
- if (cnt > info->event_backlog_max)
- info->event_backlog_max = cnt;
- info->events_received += cnt;
- if (cnt == 10)
- pr_err("adsp: too many (%d) events for single irq!\n", cnt);
- return IRQ_HANDLED;
-}
-
-int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate)
-{
- if (module->clk && clk_rate)
- return clk_set_rate(module->clk, clk_rate);
-
- return -EINVAL;
-}
-
-int msm_adsp_enable(struct msm_adsp_module *module)
-{
- int rc = 0;
-
- pr_info("msm_adsp_enable() '%s'state[%d] id[%d]\n",
- module->name, module->state, module->id);
-
- mutex_lock(&module->lock);
- switch (module->state) {
- case ADSP_STATE_DISABLED:
- rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_ENABLE,
- module->id, module);
- if (rc)
- break;
- module->state = ADSP_STATE_ENABLING;
- mutex_unlock(&module->lock);
- rc = wait_event_timeout(module->state_wait,
- module->state != ADSP_STATE_ENABLING,
- 1 * HZ);
- mutex_lock(&module->lock);
- if (module->state == ADSP_STATE_ENABLED) {
- rc = 0;
- } else {
- pr_err("adsp: module '%s' enable timed out\n",
- module->name);
- rc = -ETIMEDOUT;
- }
- break;
- case ADSP_STATE_ENABLING:
- pr_warning("adsp: module '%s' enable in progress\n",
- module->name);
- break;
- case ADSP_STATE_ENABLED:
- pr_warning("adsp: module '%s' already enabled\n",
- module->name);
- break;
- case ADSP_STATE_DISABLING:
- pr_err("adsp: module '%s' disable in progress\n",
- module->name);
- rc = -EBUSY;
- break;
- }
- mutex_unlock(&module->lock);
- return rc;
-}
-EXPORT_SYMBOL(msm_adsp_enable);
-
-static int msm_adsp_disable_locked(struct msm_adsp_module *module)
-{
- int rc = 0;
-
- switch (module->state) {
- case ADSP_STATE_DISABLED:
- pr_warning("adsp: module '%s' already disabled\n",
- module->name);
- break;
- case ADSP_STATE_ENABLING:
- case ADSP_STATE_ENABLED:
- rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_DISABLE,
- module->id, module);
- module->state = ADSP_STATE_DISABLED;
- }
- return rc;
-}
-
-int msm_adsp_disable(struct msm_adsp_module *module)
-{
- int rc;
- pr_info("msm_adsp_disable() '%s'\n", module->name);
- mutex_lock(&module->lock);
- rc = msm_adsp_disable_locked(module);
- mutex_unlock(&module->lock);
- return rc;
-}
-EXPORT_SYMBOL(msm_adsp_disable);
-
-static int msm_adsp_probe(struct platform_device *pdev)
-{
- unsigned count;
- int rc, i;
- int max_module_id;
-
- pr_info("adsp: probe\n");
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- adsp_info.init_info_ptr = kzalloc(
- (sizeof(struct adsp_rtos_mp_mtoa_init_info_type)), GFP_KERNEL);
- if (!adsp_info.init_info_ptr)
- return -ENOMEM;
-#endif
-
- rc = adsp_init_info(&adsp_info);
- if (rc)
- return rc;
- adsp_info.send_irq += (uint32_t) MSM_AD5_BASE;
- adsp_info.read_ctrl += (uint32_t) MSM_AD5_BASE;
- adsp_info.write_ctrl += (uint32_t) MSM_AD5_BASE;
- count = adsp_info.module_count;
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- max_module_id = count;
-#else
- max_module_id = adsp_info.max_module_id + 1;
-#endif
-
- adsp_modules = kzalloc(
- sizeof(struct msm_adsp_module) * count +
- sizeof(void *) * max_module_id, GFP_KERNEL);
- if (!adsp_modules)
- return -ENOMEM;
-
- adsp_info.id_to_module = (void *) (adsp_modules + count);
-
- spin_lock_init(&adsp_cmd_lock);
-
- rc = request_irq(INT_ADSP, adsp_irq_handler, IRQF_TRIGGER_RISING,
- "adsp", 0);
- if (rc < 0)
- goto fail_request_irq;
- disable_irq(INT_ADSP);
-
- rpc_cb_server_client = msm_rpc_open();
- if (IS_ERR(rpc_cb_server_client)) {
- rpc_cb_server_client = NULL;
- rc = PTR_ERR(rpc_cb_server_client);
- pr_err("adsp: could not create rpc server (%d)\n", rc);
- goto fail_rpc_open;
- }
-
- rc = msm_rpc_register_server(rpc_cb_server_client,
- RPC_ADSP_RTOS_MTOA_PROG,
- RPC_ADSP_RTOS_MTOA_VERS);
- if (rc) {
- pr_err("adsp: could not register callback server (%d)\n", rc);
- goto fail_rpc_register;
- }
-
- /* start the kernel thread to process the callbacks */
- kthread_run(adsp_rpc_thread, NULL, "kadspd");
-
- for (i = 0; i < count; i++) {
- struct msm_adsp_module *mod = adsp_modules + i;
- mutex_init(&mod->lock);
- init_waitqueue_head(&mod->state_wait);
- mod->info = &adsp_info;
- mod->name = adsp_info.module[i].name;
- mod->id = adsp_info.module[i].id;
- if (adsp_info.module[i].clk_name)
- mod->clk = clk_get(NULL, adsp_info.module[i].clk_name);
- else
- mod->clk = NULL;
- if (mod->clk && adsp_info.module[i].clk_rate)
- clk_set_rate(mod->clk, adsp_info.module[i].clk_rate);
- mod->verify_cmd = adsp_info.module[i].verify_cmd;
- mod->patch_event = adsp_info.module[i].patch_event;
- INIT_HLIST_HEAD(&mod->pmem_regions);
- mod->pdev.name = adsp_info.module[i].pdev_name;
- mod->pdev.id = -1;
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- adsp_info.id_to_module[i] = mod;
-#else
- adsp_info.id_to_module[mod->id] = mod;
-#endif
- platform_device_register(&mod->pdev);
- }
-
- msm_adsp_publish_cdevs(adsp_modules, count);
-
- return 0;
-
-fail_rpc_register:
- msm_rpc_close(rpc_cb_server_client);
- rpc_cb_server_client = NULL;
-fail_rpc_open:
- enable_irq(INT_ADSP);
- free_irq(INT_ADSP, 0);
-fail_request_irq:
- kfree(adsp_modules);
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- kfree(adsp_info.init_info_ptr);
-#endif
- return rc;
-}
-
-static struct platform_driver msm_adsp_driver = {
- .probe = msm_adsp_probe,
- .driver = {
- .name = MSM_ADSP_DRIVER_NAME,
- .owner = THIS_MODULE,
- },
-};
-
-static int __init adsp_init(void)
-{
- return platform_driver_register(&msm_adsp_driver);
-}
-
-device_initcall(adsp_init);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp.h
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- * Author: Iliyan Malchev <ibm@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_MSM_ADSP_H
-#define _ARCH_ARM_MACH_MSM_ADSP_H
-
-#include <linux/types.h>
-#include <linux/msm_adsp.h>
-#include <mach/msm_rpcrouter.h>
-#include <mach/msm_adsp.h>
-
-int adsp_pmem_fixup(struct msm_adsp_module *module, void **addr,
- unsigned long len);
-int adsp_pmem_fixup_kvaddr(struct msm_adsp_module *module, void **addr,
- unsigned long *kvaddr, unsigned long len);
-int adsp_pmem_paddr_fixup(struct msm_adsp_module *module, void **addr);
-
-int adsp_vfe_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size);
-int adsp_jpeg_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size);
-int adsp_lpm_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size);
-int adsp_video_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size);
-int adsp_videoenc_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size);
-
-
-struct adsp_event;
-
-int adsp_vfe_patch_event(struct msm_adsp_module *module,
- struct adsp_event *event);
-
-int adsp_jpeg_patch_event(struct msm_adsp_module *module,
- struct adsp_event *event);
-
-
-struct adsp_module_info {
- const char *name;
- const char *pdev_name;
- uint32_t id;
- const char *clk_name;
- unsigned long clk_rate;
- int (*verify_cmd) (struct msm_adsp_module*, unsigned int, void *,
- size_t);
- int (*patch_event) (struct msm_adsp_module*, struct adsp_event *);
-};
-
-#define ADSP_EVENT_MAX_SIZE 496
-#define EVENT_LEN 12
-#define EVENT_MSG_ID ((uint16_t)~0)
-
-struct adsp_event {
- struct list_head list;
- uint32_t size; /* always in bytes */
- uint16_t msg_id;
- uint16_t type; /* 0 for msgs (from aDSP), -1 for events (from ARM9) */
- int is16; /* always 0 (msg is 32-bit) when the event type is 1(ARM9) */
- union {
- uint16_t msg16[ADSP_EVENT_MAX_SIZE / 2];
- uint32_t msg32[ADSP_EVENT_MAX_SIZE / 4];
- } data;
-};
-
-struct adsp_info {
- uint32_t send_irq;
- uint32_t read_ctrl;
- uint32_t write_ctrl;
-
- uint32_t max_msg16_size;
- uint32_t max_msg32_size;
-
- uint32_t max_task_id;
- uint32_t max_module_id;
- uint32_t max_queue_id;
- uint32_t max_image_id;
-
- /* for each image id, a map of queue id to offset */
- uint32_t **queue_offset;
-
- /* for each image id, a map of task id to module id */
- uint32_t **task_to_module;
-
- /* for each module id, map of module id to module */
- struct msm_adsp_module **id_to_module;
-
- uint32_t module_count;
- struct adsp_module_info *module;
-
- /* stats */
- uint32_t events_received;
- uint32_t event_backlog_max;
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- /* rpc_client for init_info */
- struct msm_rpc_endpoint *init_info_rpc_client;
- struct adsp_rtos_mp_mtoa_init_info_type *init_info_ptr;
- wait_queue_head_t init_info_wait;
- unsigned init_info_state;
-#endif
-};
-
-#define RPC_ADSP_RTOS_ATOM_PROG 0x3000000a
-#define RPC_ADSP_RTOS_MTOA_PROG 0x3000000b
-#define RPC_ADSP_RTOS_ATOM_NULL_PROC 0
-#define RPC_ADSP_RTOS_MTOA_NULL_PROC 0
-#define RPC_ADSP_RTOS_APP_TO_MODEM_PROC 2
-#define RPC_ADSP_RTOS_MODEM_TO_APP_PROC 2
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(1,0)
-#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(2,1) /* must be actual vers */
-#define MSM_ADSP_DRIVER_NAME "rs3000000a:00010000"
-#elif (CONFIG_MSM_AMSS_VERSION == 6220) || (CONFIG_MSM_AMSS_VERSION == 6225)
-#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(0x71d1094b, 0)
-#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(0xee3a9966, 0)
-#define MSM_ADSP_DRIVER_NAME "rs3000000a:71d1094b"
-#elif CONFIG_MSM_AMSS_VERSION == 6210
-#define RPC_ADSP_RTOS_ATOM_VERS MSM_RPC_VERS(0x20f17fd3, 0)
-#define RPC_ADSP_RTOS_MTOA_VERS MSM_RPC_VERS(0x75babbd6, 0)
-#define MSM_ADSP_DRIVER_NAME "rs3000000a:20f17fd3"
-#else
-#error "Unknown AMSS version"
-#endif
-
-enum rpc_adsp_rtos_proc_type {
- RPC_ADSP_RTOS_PROC_NONE = 0,
- RPC_ADSP_RTOS_PROC_MODEM = 1,
- RPC_ADSP_RTOS_PROC_APPS = 2,
-};
-
-enum {
- RPC_ADSP_RTOS_CMD_REGISTER_APP,
- RPC_ADSP_RTOS_CMD_ENABLE,
- RPC_ADSP_RTOS_CMD_DISABLE,
- RPC_ADSP_RTOS_CMD_KERNEL_COMMAND,
- RPC_ADSP_RTOS_CMD_16_COMMAND,
- RPC_ADSP_RTOS_CMD_32_COMMAND,
- RPC_ADSP_RTOS_CMD_DISABLE_EVENT_RSP,
- RPC_ADSP_RTOS_CMD_REMOTE_EVENT,
- RPC_ADSP_RTOS_CMD_SET_STATE,
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- RPC_ADSP_RTOS_CMD_REMOTE_INIT_INFO_EVENT,
- RPC_ADSP_RTOS_CMD_GET_INIT_INFO,
-#endif
-};
-
-enum rpc_adsp_rtos_mod_status_type {
- RPC_ADSP_RTOS_MOD_READY,
- RPC_ADSP_RTOS_MOD_DISABLE,
- RPC_ADSP_RTOS_SERVICE_RESET,
- RPC_ADSP_RTOS_CMD_FAIL,
- RPC_ADSP_RTOS_CMD_SUCCESS,
-#if CONFIG_MSM_AMSS_VERSION >= 6350
- RPC_ADSP_RTOS_INIT_INFO,
- RPC_ADSP_RTOS_DISABLE_FAIL,
-#endif
-};
-
-struct rpc_adsp_rtos_app_to_modem_args_t {
- struct rpc_request_hdr hdr;
- uint32_t gotit; /* if 1, the next elements are present */
- uint32_t cmd; /* e.g., RPC_ADSP_RTOS_CMD_REGISTER_APP */
- uint32_t proc_id; /* e.g., RPC_ADSP_RTOS_PROC_APPS */
- uint32_t module; /* e.g., QDSP_MODULE_AUDPPTASK */
-};
-
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-enum qdsp_image_type {
- QDSP_IMAGE_COMBO,
- QDSP_IMAGE_GAUDIO,
- QDSP_IMAGE_QTV_LP,
- QDSP_IMAGE_MAX,
- /* DO NOT USE: Force this enum to be a 32bit type to improve speed */
- QDSP_IMAGE_32BIT_DUMMY = 0x10000
-};
-
-struct adsp_rtos_mp_mtoa_header_type {
- enum rpc_adsp_rtos_mod_status_type event;
- enum rpc_adsp_rtos_proc_type proc_id;
-};
-
-/* ADSP RTOS MP Communications - Modem to APP's Event Info*/
-struct adsp_rtos_mp_mtoa_type {
- uint32_t module;
- uint32_t image;
- uint32_t apps_okts;
-};
-
-/* ADSP RTOS MP Communications - Modem to APP's Init Info */
-#define IMG_MAX 8
-#define ENTRIES_MAX 64
-
-struct queue_to_offset_type {
- uint32_t queue;
- uint32_t offset;
-};
-
-struct adsp_rtos_mp_mtoa_init_info_type {
- uint32_t image_count;
- uint32_t num_queue_offsets;
- struct queue_to_offset_type queue_offsets_tbl[IMG_MAX][ENTRIES_MAX];
- uint32_t num_task_module_entries;
- uint32_t task_to_module_tbl[IMG_MAX][ENTRIES_MAX];
-
- uint32_t module_table_size;
- uint32_t module_entries[ENTRIES_MAX];
- /*
- * queue_offsets[] is to store only queue_offsets
- */
- uint32_t queue_offsets[IMG_MAX][ENTRIES_MAX];
-};
-
-struct adsp_rtos_mp_mtoa_s_type {
- struct adsp_rtos_mp_mtoa_header_type mp_mtoa_header;
-
- uint32_t desc_field;
- union {
- struct adsp_rtos_mp_mtoa_init_info_type mp_mtoa_init_packet;
- struct adsp_rtos_mp_mtoa_type mp_mtoa_packet;
- } adsp_rtos_mp_mtoa_data;
-};
-
-struct rpc_adsp_rtos_modem_to_app_args_t {
- struct rpc_request_hdr hdr;
- uint32_t gotit; /* if 1, the next elements are present */
- struct adsp_rtos_mp_mtoa_s_type mtoa_pkt;
-};
-#else
-struct rpc_adsp_rtos_modem_to_app_args_t {
- struct rpc_request_hdr hdr;
- uint32_t gotit; /* if 1, the next elements are present */
- uint32_t event; /* e.g., RPC_ADSP_RTOS_CMD_REGISTER_APP */
- uint32_t proc_id; /* e.g., RPC_ADSP_RTOS_PROC_APPS */
- uint32_t module; /* e.g., QDSP_MODULE_AUDPPTASK */
- uint32_t image; /* RPC_QDSP_IMAGE_GAUDIO */
-};
-#endif /* CONFIG_MSM_AMSS_VERSION >= 6350 */
-
-#define ADSP_STATE_DISABLED 0
-#define ADSP_STATE_ENABLING 1
-#define ADSP_STATE_ENABLED 2
-#define ADSP_STATE_DISABLING 3
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-#define ADSP_STATE_INIT_INFO 4
-#endif
-
-struct msm_adsp_module {
- struct mutex lock;
- const char *name;
- unsigned id;
- struct adsp_info *info;
-
- struct msm_rpc_endpoint *rpc_client;
- struct msm_adsp_ops *ops;
- void *driver_data;
-
- /* statistics */
- unsigned num_commands;
- unsigned num_events;
-
- wait_queue_head_t state_wait;
- unsigned state;
-
- struct platform_device pdev;
- struct clk *clk;
- int open_count;
-
- struct mutex pmem_regions_lock;
- struct hlist_head pmem_regions;
- int (*verify_cmd) (struct msm_adsp_module*, unsigned int, void *,
- size_t);
- int (*patch_event) (struct msm_adsp_module*, struct adsp_event *);
-};
-
-extern void msm_adsp_publish_cdevs(struct msm_adsp_module *, unsigned);
-extern int adsp_init_info(struct adsp_info *info);
-
-/* Value to indicate that a queue is not defined for a particular image */
-#if CONFIG_MSM_AMSS_VERSION >= 6350
-#define QDSP_RTOS_NO_QUEUE 0xfffffffe
-#else
-#define QDSP_RTOS_NO_QUEUE 0xffffffff
-#endif
-
-/*
- * Constants used to communicate with the ADSP RTOS
- */
-#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M 0x80000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V 0x80000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_AVAIL_V 0x00000000U
-
-#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_M 0x70000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_REQ_V 0x00000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_DONE_V 0x10000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_CMD_NO_CMD_V 0x70000000U
-
-#define ADSP_RTOS_WRITE_CTRL_WORD_STATUS_M 0x0E000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_NO_ERR_V 0x00000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_NO_FREE_BUF_V 0x02000000U
-
-#define ADSP_RTOS_WRITE_CTRL_WORD_KERNEL_FLG_M 0x01000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_MSG_WRITE_V 0x00000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_CMD_V 0x01000000U
-
-#define ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M 0x00FFFFFFU
-#define ADSP_RTOS_WRITE_CTRL_WORD_HTOD_CMD_ID_M 0x00FFFFFFU
-
-/* Combination of MUTEX and CMD bits to check if the DSP is busy */
-#define ADSP_RTOS_WRITE_CTRL_WORD_READY_M 0xF0000000U
-#define ADSP_RTOS_WRITE_CTRL_WORD_READY_V 0x70000000U
-
-/* RTOS to Host processor command mask values */
-#define ADSP_RTOS_READ_CTRL_WORD_FLAG_M 0x80000000U
-#define ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_WAIT_V 0x00000000U
-#define ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_CONT_V 0x80000000U
-
-#define ADSP_RTOS_READ_CTRL_WORD_CMD_M 0x60000000U
-#define ADSP_RTOS_READ_CTRL_WORD_READ_DONE_V 0x00000000U
-#define ADSP_RTOS_READ_CTRL_WORD_READ_REQ_V 0x20000000U
-#define ADSP_RTOS_READ_CTRL_WORD_NO_CMD_V 0x60000000U
-
-/* Combination of FLAG and COMMAND bits to check if MSG ready */
-#define ADSP_RTOS_READ_CTRL_WORD_READY_M 0xE0000000U
-#define ADSP_RTOS_READ_CTRL_WORD_READY_V 0xA0000000U
-#define ADSP_RTOS_READ_CTRL_WORD_CONT_V 0xC0000000U
-#define ADSP_RTOS_READ_CTRL_WORD_DONE_V 0xE0000000U
-
-#define ADSP_RTOS_READ_CTRL_WORD_STATUS_M 0x18000000U
-#define ADSP_RTOS_READ_CTRL_WORD_NO_ERR_V 0x00000000U
-
-#define ADSP_RTOS_READ_CTRL_WORD_IN_PROG_M 0x04000000U
-#define ADSP_RTOS_READ_CTRL_WORD_NO_READ_IN_PROG_V 0x00000000U
-#define ADSP_RTOS_READ_CTRL_WORD_READ_IN_PROG_V 0x04000000U
-
-#define ADSP_RTOS_READ_CTRL_WORD_CMD_TYPE_M 0x03000000U
-#define ADSP_RTOS_READ_CTRL_WORD_CMD_TASK_TO_H_V 0x00000000U
-#define ADSP_RTOS_READ_CTRL_WORD_CMD_KRNL_TO_H_V 0x01000000U
-#define ADSP_RTOS_READ_CTRL_WORD_CMD_H_TO_KRNL_CFM_V 0x02000000U
-
-#define ADSP_RTOS_READ_CTRL_WORD_DSP_ADDR_M 0x00FFFFFFU
-
-#define ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M 0x000000FFU
-#define ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M 0x0000FF00U
-
-/* Base address of DSP and DSP hardware registers */
-#define QDSP_RAMC_OFFSET 0x400000
-
-#endif /* _ARCH_ARM_MACH_MSM_ADSP_H */
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_6210.h
- *
- * Copyright (c) 2008 QUALCOMM Incorporated.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include "adsp.h"
-
-/* Firmware modules */
-typedef enum {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEO_AAC_VOC,
- QDSP_MODULE_PCM_DEC,
- QDSP_MODULE_AUDIO_DEC_MP3,
- QDSP_MODULE_AUDIO_DEC_AAC,
- QDSP_MODULE_AUDIO_DEC_WMA,
- QDSP_MODULE_HOSTPCM,
- QDSP_MODULE_DTMF,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_SBC_ENC,
- QDSP_MODULE_VOC,
- QDSP_MODULE_VOC_PCM,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_WAV_ENC,
- QDSP_MODULE_AACLC_ENC,
- QDSP_MODULE_VIDEO_AMR,
- QDSP_MODULE_VOC_AMR,
- QDSP_MODULE_VOC_EVRC,
- QDSP_MODULE_VOC_13K,
- QDSP_MODULE_VOC_FGV,
- QDSP_MODULE_DIAGTASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_QCAMTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MIDI,
- QDSP_MODULE_GAUDIO,
- QDSP_MODULE_VDEC_LP_MODE,
- QDSP_MODULE_MAX,
-} qdsp_module_type;
-
-#define QDSP_RTOS_MAX_TASK_ID 19U
-
-/* Table of modules indexed by task ID for the GAUDIO image */
-static qdsp_module_type qdsp_gaudio_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the GAUDIO image */
-static uint32_t qdsp_gaudio_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x3be, /* QDSP_mpuAfeQueue */
- 0x3ee, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x3c2, /* QDSP_uPAudPPCmd1Queue */
- 0x3c6, /* QDSP_uPAudPPCmd2Queue */
- 0x3ca, /* QDSP_uPAudPPCmd3Queue */
- 0x3da, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- 0x3de, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- 0x3e2, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- 0x3e6, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- 0x3ea, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x3ce, /* QDSP_uPAudPreProcCmdQueue */
- 0x3d6, /* QDSP_uPAudRecBitStreamQueue */
- 0x3d2, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
-};
-
-/* Table of modules indexed by task ID for the COMBO image */
-static qdsp_module_type qdsp_combo_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the COMBO image */
-static uint32_t qdsp_combo_queue_offset_table[] = {
- 0x585, /* QDSP_lpmCommandQueue */
- 0x52d, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- 0x541, /* QDSP_mpuModmathCmdQueue */
- 0x555, /* QDSP_mpuVDecCmdQueue */
- 0x559, /* QDSP_mpuVDecPktQueue */
- 0x551, /* QDSP_mpuVEncCmdQueue */
- 0x535, /* QDSP_rxMpuDecCmdQueue */
- 0x539, /* QDSP_rxMpuDecPktQueue */
- 0x53d, /* QDSP_txMpuEncQueue */
- 0x55d, /* QDSP_uPAudPPCmd1Queue */
- 0x561, /* QDSP_uPAudPPCmd2Queue */
- 0x565, /* QDSP_uPAudPPCmd3Queue */
- 0x575, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- 0x579, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x569, /* QDSP_uPAudPreProcCmdQueue */
- 0x571, /* QDSP_uPAudRecBitStreamQueue */
- 0x56d, /* QDSP_uPAudRecCmdQueue */
- 0x581, /* QDSP_uPJpegActionCmdQueue */
- 0x57d, /* QDSP_uPJpegCfgCmdQueue */
- 0x531, /* QDSP_uPVocProcQueue */
- 0x545, /* QDSP_vfeCommandQueue */
- 0x54d, /* QDSP_vfeCommandScaleQueue */
- 0x549 /* QDSP_vfeCommandTableQueue */
-};
-
-/* Table of modules indexed by task ID for the QTV_LP image */
-static qdsp_module_type qdsp_qtv_lp_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the QTV_LP image */
-static uint32_t qdsp_qtv_lp_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x40c, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- 0x410, /* QDSP_mpuVDecCmdQueue */
- 0x414, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x41c, /* QDSP_uPAudPPCmd1Queue */
- 0x420, /* QDSP_uPAudPPCmd2Queue */
- 0x424, /* QDSP_uPAudPPCmd3Queue */
- 0x430, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x418, /* QDSP_uPAudPreProcCmdQueue */
- 0x42c, /* QDSP_uPAudRecBitStreamQueue */
- 0x428, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
-};
-
-/* Tables to convert tasks to modules */
-static uint32_t *qdsp_task_to_module[] = {
- qdsp_combo_task_to_module_table,
- qdsp_gaudio_task_to_module_table,
- qdsp_qtv_lp_task_to_module_table,
-};
-
-/* Tables to retrieve queue offsets */
-static uint32_t *qdsp_queue_offset_table[] = {
- qdsp_combo_queue_offset_table,
- qdsp_gaudio_queue_offset_table,
- qdsp_qtv_lp_queue_offset_table,
-};
-
-#define QDSP_MODULE(n) \
- { .name = #n, .pdev_name = "adsp_" #n, .id = QDSP_MODULE_##n }
-
-static struct adsp_module_info module_info[] = {
- QDSP_MODULE(AUDPPTASK),
- QDSP_MODULE(AUDRECTASK),
- QDSP_MODULE(AUDPREPROCTASK),
- QDSP_MODULE(VFETASK),
- QDSP_MODULE(QCAMTASK),
- QDSP_MODULE(LPMTASK),
- QDSP_MODULE(JPEGTASK),
- QDSP_MODULE(VIDEOTASK),
- QDSP_MODULE(VDEC_LP_MODE),
-};
-
-int adsp_init_info(struct adsp_info *info)
-{
- info->send_irq = 0x00c00200;
- info->read_ctrl = 0x00400038;
- info->write_ctrl = 0x00400034;
-
- info->max_msg16_size = 193;
- info->max_msg32_size = 8;
-
- info->max_task_id = 16;
- info->max_module_id = QDSP_MODULE_MAX - 1;
- info->max_queue_id = QDSP_QUEUE_MAX;
- info->max_image_id = 2;
- info->queue_offset = qdsp_queue_offset_table;
- info->task_to_module = qdsp_task_to_module;
-
- info->module_count = ARRAY_SIZE(module_info);
- info->module = module_info;
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_6220.h
- *
- * Copyright (c) 2008 QUALCOMM Incorporated.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include "adsp.h"
-
-/* Firmware modules */
-typedef enum {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEO_AAC_VOC,
- QDSP_MODULE_PCM_DEC,
- QDSP_MODULE_AUDIO_DEC_MP3,
- QDSP_MODULE_AUDIO_DEC_AAC,
- QDSP_MODULE_AUDIO_DEC_WMA,
- QDSP_MODULE_HOSTPCM,
- QDSP_MODULE_DTMF,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_SBC_ENC,
- QDSP_MODULE_VOC,
- QDSP_MODULE_VOC_PCM,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_WAV_ENC,
- QDSP_MODULE_AACLC_ENC,
- QDSP_MODULE_VIDEO_AMR,
- QDSP_MODULE_VOC_AMR,
- QDSP_MODULE_VOC_EVRC,
- QDSP_MODULE_VOC_13K,
- QDSP_MODULE_VOC_FGV,
- QDSP_MODULE_DIAGTASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_QCAMTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MIDI,
- QDSP_MODULE_GAUDIO,
- QDSP_MODULE_VDEC_LP_MODE,
- QDSP_MODULE_MAX,
-} qdsp_module_type;
-
-#define QDSP_RTOS_MAX_TASK_ID 19U
-
-/* Table of modules indexed by task ID for the GAUDIO image */
-static qdsp_module_type qdsp_gaudio_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the GAUDIO image */
-static uint32_t qdsp_gaudio_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x3f0, /* QDSP_mpuAfeQueue */
- 0x420, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x3f4, /* QDSP_uPAudPPCmd1Queue */
- 0x3f8, /* QDSP_uPAudPPCmd2Queue */
- 0x3fc, /* QDSP_uPAudPPCmd3Queue */
- 0x40c, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- 0x410, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- 0x414, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- 0x418, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- 0x41c, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x400, /* QDSP_uPAudPreProcCmdQueue */
- 0x408, /* QDSP_uPAudRecBitStreamQueue */
- 0x404, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
-};
-
-/* Table of modules indexed by task ID for the COMBO image */
-static qdsp_module_type qdsp_combo_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the COMBO image */
-static uint32_t qdsp_combo_queue_offset_table[] = {
- 0x6f2, /* QDSP_lpmCommandQueue */
- 0x69e, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- 0x6b2, /* QDSP_mpuModmathCmdQueue */
- 0x6c6, /* QDSP_mpuVDecCmdQueue */
- 0x6ca, /* QDSP_mpuVDecPktQueue */
- 0x6c2, /* QDSP_mpuVEncCmdQueue */
- 0x6a6, /* QDSP_rxMpuDecCmdQueue */
- 0x6aa, /* QDSP_rxMpuDecPktQueue */
- 0x6ae, /* QDSP_txMpuEncQueue */
- 0x6ce, /* QDSP_uPAudPPCmd1Queue */
- 0x6d2, /* QDSP_uPAudPPCmd2Queue */
- 0x6d6, /* QDSP_uPAudPPCmd3Queue */
- 0x6e6, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x6da, /* QDSP_uPAudPreProcCmdQueue */
- 0x6e2, /* QDSP_uPAudRecBitStreamQueue */
- 0x6de, /* QDSP_uPAudRecCmdQueue */
- 0x6ee, /* QDSP_uPJpegActionCmdQueue */
- 0x6ea, /* QDSP_uPJpegCfgCmdQueue */
- 0x6a2, /* QDSP_uPVocProcQueue */
- 0x6b6, /* QDSP_vfeCommandQueue */
- 0x6be, /* QDSP_vfeCommandScaleQueue */
- 0x6ba /* QDSP_vfeCommandTableQueue */
-};
-
-/* Table of modules indexed by task ID for the QTV_LP image */
-static qdsp_module_type qdsp_qtv_lp_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX
-};
-
-/* Queue offset table indexed by queue ID for the QTV_LP image */
-static uint32_t qdsp_qtv_lp_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x430, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- 0x434, /* QDSP_mpuVDecCmdQueue */
- 0x438, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x440, /* QDSP_uPAudPPCmd1Queue */
- 0x444, /* QDSP_uPAudPPCmd2Queue */
- 0x448, /* QDSP_uPAudPPCmd3Queue */
- 0x454, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x43c, /* QDSP_uPAudPreProcCmdQueue */
- 0x450, /* QDSP_uPAudRecBitStreamQueue */
- 0x44c, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE /* QDSP_vfeCommandTableQueue */
-};
-
-/* Tables to convert tasks to modules */
-static qdsp_module_type *qdsp_task_to_module[] = {
- qdsp_combo_task_to_module_table,
- qdsp_gaudio_task_to_module_table,
- qdsp_qtv_lp_task_to_module_table,
-};
-
-/* Tables to retrieve queue offsets */
-static uint32_t *qdsp_queue_offset_table[] = {
- qdsp_combo_queue_offset_table,
- qdsp_gaudio_queue_offset_table,
- qdsp_qtv_lp_queue_offset_table,
-};
-
-#define QDSP_MODULE(n) \
- { .name = #n, .pdev_name = "adsp_" #n, .id = QDSP_MODULE_##n }
-
-static struct adsp_module_info module_info[] = {
- QDSP_MODULE(AUDPLAY0TASK),
- QDSP_MODULE(AUDPPTASK),
- QDSP_MODULE(AUDPREPROCTASK),
- QDSP_MODULE(AUDRECTASK),
- QDSP_MODULE(VFETASK),
- QDSP_MODULE(QCAMTASK),
- QDSP_MODULE(LPMTASK),
- QDSP_MODULE(JPEGTASK),
- QDSP_MODULE(VIDEOTASK),
- QDSP_MODULE(VDEC_LP_MODE),
-};
-
-int adsp_init_info(struct adsp_info *info)
-{
- info->send_irq = 0x00c00200;
- info->read_ctrl = 0x00400038;
- info->write_ctrl = 0x00400034;
-
- info->max_msg16_size = 193;
- info->max_msg32_size = 8;
-
- info->max_task_id = 16;
- info->max_module_id = QDSP_MODULE_MAX - 1;
- info->max_queue_id = QDSP_QUEUE_MAX;
- info->max_image_id = 2;
- info->queue_offset = qdsp_queue_offset_table;
- info->task_to_module = qdsp_task_to_module;
-
- info->module_count = ARRAY_SIZE(module_info);
- info->module = module_info;
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_6225.h
- *
- * Copyright (c) 2008 QUALCOMM Incorporated.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include "adsp.h"
-
-/* Firmware modules */
-typedef enum {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEO_AAC_VOC,
- QDSP_MODULE_PCM_DEC,
- QDSP_MODULE_AUDIO_DEC_MP3,
- QDSP_MODULE_AUDIO_DEC_AAC,
- QDSP_MODULE_AUDIO_DEC_WMA,
- QDSP_MODULE_HOSTPCM,
- QDSP_MODULE_DTMF,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_SBC_ENC,
- QDSP_MODULE_VOC_UMTS,
- QDSP_MODULE_VOC_CDMA,
- QDSP_MODULE_VOC_PCM,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_WAV_ENC,
- QDSP_MODULE_AACLC_ENC,
- QDSP_MODULE_VIDEO_AMR,
- QDSP_MODULE_VOC_AMR,
- QDSP_MODULE_VOC_EVRC,
- QDSP_MODULE_VOC_13K,
- QDSP_MODULE_VOC_FGV,
- QDSP_MODULE_DIAGTASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_QCAMTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MIDI,
- QDSP_MODULE_GAUDIO,
- QDSP_MODULE_VDEC_LP_MODE,
- QDSP_MODULE_MAX,
-} qdsp_module_type;
-
-#define QDSP_RTOS_MAX_TASK_ID 30U
-
-/* Table of modules indexed by task ID for the GAUDIO image */
-static qdsp_module_type qdsp_gaudio_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_AUDPLAY2TASK,
- QDSP_MODULE_AUDPLAY3TASK,
- QDSP_MODULE_AUDPLAY4TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_GRAPHICSTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
-};
-
-/* Queue offset table indexed by queue ID for the GAUDIO image */
-static uint32_t qdsp_gaudio_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x3f0, /* QDSP_mpuAfeQueue */
- 0x420, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x3f4, /* QDSP_uPAudPPCmd1Queue */
- 0x3f8, /* QDSP_uPAudPPCmd2Queue */
- 0x3fc, /* QDSP_uPAudPPCmd3Queue */
- 0x40c, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- 0x410, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- 0x414, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- 0x418, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- 0x41c, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x400, /* QDSP_uPAudPreProcCmdQueue */
- 0x408, /* QDSP_uPAudRecBitStreamQueue */
- 0x404, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandTableQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPDiagQueue */
-};
-
-/* Table of modules indexed by task ID for the COMBO image */
-static qdsp_module_type qdsp_combo_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_VOCDECTASK,
- QDSP_MODULE_VOCENCTASK,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_VIDEOENCTASK,
- QDSP_MODULE_VOICEPROCTASK,
- QDSP_MODULE_VFETASK,
- QDSP_MODULE_JPEGTASK,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_AUDPLAY1TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_LPMTASK,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MODMATHTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_DIAGTASK,
- QDSP_MODULE_MAX,
-};
-
-/* Queue offset table indexed by queue ID for the COMBO image */
-static uint32_t qdsp_combo_queue_offset_table[] = {
- 0x714, /* QDSP_lpmCommandQueue */
- 0x6bc, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- 0x6d0, /* QDSP_mpuModmathCmdQueue */
- 0x6e8, /* QDSP_mpuVDecCmdQueue */
- 0x6ec, /* QDSP_mpuVDecPktQueue */
- 0x6e4, /* QDSP_mpuVEncCmdQueue */
- 0x6c4, /* QDSP_rxMpuDecCmdQueue */
- 0x6c8, /* QDSP_rxMpuDecPktQueue */
- 0x6cc, /* QDSP_txMpuEncQueue */
- 0x6f0, /* QDSP_uPAudPPCmd1Queue */
- 0x6f4, /* QDSP_uPAudPPCmd2Queue */
- 0x6f8, /* QDSP_uPAudPPCmd3Queue */
- 0x708, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x6fc, /* QDSP_uPAudPreProcCmdQueue */
- 0x704, /* QDSP_uPAudRecBitStreamQueue */
- 0x700, /* QDSP_uPAudRecCmdQueue */
- 0x710, /* QDSP_uPJpegActionCmdQueue */
- 0x70c, /* QDSP_uPJpegCfgCmdQueue */
- 0x6c0, /* QDSP_uPVocProcQueue */
- 0x6d8, /* QDSP_vfeCommandQueue */
- 0x6e0, /* QDSP_vfeCommandScaleQueue */
- 0x6dc, /* QDSP_vfeCommandTableQueue */
- 0x6d4, /* QDSP_uPDiagQueue */
-};
-
-/* Table of modules indexed by task ID for the QTV_LP image */
-static qdsp_module_type qdsp_qtv_lp_task_to_module_table[] = {
- QDSP_MODULE_KERNEL,
- QDSP_MODULE_AFETASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_VIDEOTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDPPTASK,
- QDSP_MODULE_AUDPLAY0TASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_AUDRECTASK,
- QDSP_MODULE_AUDPREPROCTASK,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
- QDSP_MODULE_MAX,
-};
-
-/* Queue offset table indexed by queue ID for the QTV_LP image */
-static uint32_t qdsp_qtv_lp_queue_offset_table[] = {
- QDSP_RTOS_NO_QUEUE, /* QDSP_lpmCommandQueue */
- 0x3fe, /* QDSP_mpuAfeQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuGraphicsCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuModmathCmdQueue */
- 0x402, /* QDSP_mpuVDecCmdQueue */
- 0x406, /* QDSP_mpuVDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_mpuVEncCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_rxMpuDecPktQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_txMpuEncQueue */
- 0x40e, /* QDSP_uPAudPPCmd1Queue */
- 0x412, /* QDSP_uPAudPPCmd2Queue */
- 0x416, /* QDSP_uPAudPPCmd3Queue */
- 0x422, /* QDSP_uPAudPlay0BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay1BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay2BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay3BitStreamCtrlQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPAudPlay4BitStreamCtrlQueue */
- 0x40a, /* QDSP_uPAudPreProcCmdQueue */
- 0x41e, /* QDSP_uPAudRecBitStreamQueue */
- 0x41a, /* QDSP_uPAudRecCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegActionCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPJpegCfgCmdQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPVocProcQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandScaleQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_vfeCommandTableQueue */
- QDSP_RTOS_NO_QUEUE, /* QDSP_uPDiagQueue */
-};
-
-/* Tables to convert tasks to modules */
-static qdsp_module_type *qdsp_task_to_module[] = {
- qdsp_combo_task_to_module_table,
- qdsp_gaudio_task_to_module_table,
- qdsp_qtv_lp_task_to_module_table,
-};
-
-/* Tables to retrieve queue offsets */
-static uint32_t *qdsp_queue_offset_table[] = {
- qdsp_combo_queue_offset_table,
- qdsp_gaudio_queue_offset_table,
- qdsp_qtv_lp_queue_offset_table,
-};
-
-#define QDSP_MODULE(n, clkname, clkrate, verify_cmd_func, patch_event_func) \
- { .name = #n, .pdev_name = "adsp_" #n, .id = QDSP_MODULE_##n, \
- .clk_name = clkname, .clk_rate = clkrate, \
- .verify_cmd = verify_cmd_func, .patch_event = patch_event_func }
-
-static struct adsp_module_info module_info[] = {
- QDSP_MODULE(AUDPLAY0TASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDPPTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDRECTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDPREPROCTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(VFETASK, "vfe_clk", 0, adsp_vfe_verify_cmd,
- adsp_vfe_patch_event),
- QDSP_MODULE(QCAMTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(LPMTASK, NULL, 0, adsp_lpm_verify_cmd, NULL),
- QDSP_MODULE(JPEGTASK, "vdc_clk", 0, adsp_jpeg_verify_cmd,
- adsp_jpeg_patch_event),
- QDSP_MODULE(VIDEOTASK, "vdc_clk", 96000000,
- adsp_video_verify_cmd, NULL),
- QDSP_MODULE(VDEC_LP_MODE, NULL, 0, NULL, NULL),
- QDSP_MODULE(VIDEOENCTASK, "vdc_clk", 96000000,
- adsp_videoenc_verify_cmd, NULL),
-};
-
-int adsp_init_info(struct adsp_info *info)
-{
- info->send_irq = 0x00c00200;
- info->read_ctrl = 0x00400038;
- info->write_ctrl = 0x00400034;
-
- info->max_msg16_size = 193;
- info->max_msg32_size = 8;
-
- info->max_task_id = 16;
- info->max_module_id = QDSP_MODULE_MAX - 1;
- info->max_queue_id = QDSP_QUEUE_MAX;
- info->max_image_id = 2;
- info->queue_offset = qdsp_queue_offset_table;
- info->task_to_module = qdsp_task_to_module;
-
- info->module_count = ARRAY_SIZE(module_info);
- info->module = module_info;
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_driver.c
- *
- * Copyright (C) 2008 Google, Inc.
- * Author: Iliyan Malchev <ibm@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/cdev.h>
-#include <linux/fs.h>
-#include <linux/list.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-
-#include "adsp.h"
-
-#include <linux/msm_adsp.h>
-#include <linux/android_pmem.h>
-
-struct adsp_pmem_region {
- struct hlist_node list;
- void *vaddr;
- unsigned long paddr;
- unsigned long kvaddr;
- unsigned long len;
- struct file *file;
-};
-
-struct adsp_device {
- struct msm_adsp_module *module;
-
- spinlock_t event_queue_lock;
- wait_queue_head_t event_wait;
- struct list_head event_queue;
- int abort;
-
- const char *name;
- struct device *device;
- struct cdev cdev;
-};
-
-static struct adsp_device *inode_to_device(struct inode *inode);
-
-#define __CONTAINS(r, v, l) ({ \
- typeof(r) __r = r; \
- typeof(v) __v = v; \
- typeof(v) __e = __v + l; \
- int res = __v >= __r->vaddr && \
- __e <= __r->vaddr + __r->len; \
- res; \
-})
-
-#define CONTAINS(r1, r2) ({ \
- typeof(r2) __r2 = r2; \
- __CONTAINS(r1, __r2->vaddr, __r2->len); \
-})
-
-#define IN_RANGE(r, v) ({ \
- typeof(r) __r = r; \
- typeof(v) __vv = v; \
- int res = ((__vv >= __r->vaddr) && \
- (__vv < (__r->vaddr + __r->len))); \
- res; \
-})
-
-#define OVERLAPS(r1, r2) ({ \
- typeof(r1) __r1 = r1; \
- typeof(r2) __r2 = r2; \
- typeof(__r2->vaddr) __v = __r2->vaddr; \
- typeof(__v) __e = __v + __r2->len - 1; \
- int res = (IN_RANGE(__r1, __v) || IN_RANGE(__r1, __e)); \
- res; \
-})
-
-static int adsp_pmem_check(struct msm_adsp_module *module,
- void *vaddr, unsigned long len)
-{
- struct adsp_pmem_region *region_elt;
- struct hlist_node *node;
- struct adsp_pmem_region t = { .vaddr = vaddr, .len = len };
-
- hlist_for_each_entry(region_elt, node, &module->pmem_regions, list) {
- if (CONTAINS(region_elt, &t) || CONTAINS(&t, region_elt) ||
- OVERLAPS(region_elt, &t)) {
- printk(KERN_ERR "adsp: module %s:"
- " region (vaddr %p len %ld)"
- " clashes with registered region"
- " (vaddr %p paddr %p len %ld)\n",
- module->name,
- vaddr, len,
- region_elt->vaddr,
- (void *)region_elt->paddr,
- region_elt->len);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static int adsp_pmem_add(struct msm_adsp_module *module,
- struct adsp_pmem_info *info)
-{
- unsigned long paddr, kvaddr, len;
- struct file *file;
- struct adsp_pmem_region *region;
- int rc = -EINVAL;
-
- mutex_lock(&module->pmem_regions_lock);
- region = kmalloc(sizeof(*region), GFP_KERNEL);
- if (!region) {
- rc = -ENOMEM;
- goto end;
- }
- INIT_HLIST_NODE(®ion->list);
- if (get_pmem_file(info->fd, &paddr, &kvaddr, &len, &file)) {
- kfree(region);
- goto end;
- }
-
- rc = adsp_pmem_check(module, info->vaddr, len);
- if (rc < 0) {
- put_pmem_file(file);
- kfree(region);
- goto end;
- }
-
- region->vaddr = info->vaddr;
- region->paddr = paddr;
- region->kvaddr = kvaddr;
- region->len = len;
- region->file = file;
-
- hlist_add_head(®ion->list, &module->pmem_regions);
-end:
- mutex_unlock(&module->pmem_regions_lock);
- return rc;
-}
-
-static int adsp_pmem_lookup_vaddr(struct msm_adsp_module *module, void **addr,
- unsigned long len, struct adsp_pmem_region **region)
-{
- struct hlist_node *node;
- void *vaddr = *addr;
- struct adsp_pmem_region *region_elt;
-
- int match_count = 0;
-
- *region = NULL;
-
- /* returns physical address or zero */
- hlist_for_each_entry(region_elt, node, &module->pmem_regions, list) {
- if (vaddr >= region_elt->vaddr &&
- vaddr < region_elt->vaddr + region_elt->len &&
- vaddr + len <= region_elt->vaddr + region_elt->len) {
- /* offset since we could pass vaddr inside a registerd
- * pmem buffer
- */
-
- match_count++;
- if (!*region)
- *region = region_elt;
- }
- }
-
- if (match_count > 1) {
- printk(KERN_ERR "adsp: module %s: "
- "multiple hits for vaddr %p, len %ld\n",
- module->name, vaddr, len);
- hlist_for_each_entry(region_elt, node,
- &module->pmem_regions, list) {
- if (vaddr >= region_elt->vaddr &&
- vaddr < region_elt->vaddr + region_elt->len &&
- vaddr + len <= region_elt->vaddr + region_elt->len)
- printk(KERN_ERR "\t%p, %ld --> %p\n",
- region_elt->vaddr,
- region_elt->len,
- (void *)region_elt->paddr);
- }
- }
-
- return *region ? 0 : -1;
-}
-
-int adsp_pmem_fixup_kvaddr(struct msm_adsp_module *module, void **addr,
- unsigned long *kvaddr, unsigned long len)
-{
- struct adsp_pmem_region *region;
- void *vaddr = *addr;
- unsigned long *paddr = (unsigned long *)addr;
- int ret;
-
- ret = adsp_pmem_lookup_vaddr(module, addr, len, ®ion);
- if (ret) {
- printk(KERN_ERR "adsp: not patching %s (paddr & kvaddr),"
- " lookup (%p, %ld) failed\n",
- module->name, vaddr, len);
- return ret;
- }
- *paddr = region->paddr + (vaddr - region->vaddr);
- *kvaddr = region->kvaddr + (vaddr - region->vaddr);
- return 0;
-}
-
-int adsp_pmem_fixup(struct msm_adsp_module *module, void **addr,
- unsigned long len)
-{
- struct adsp_pmem_region *region;
- void *vaddr = *addr;
- unsigned long *paddr = (unsigned long *)addr;
- int ret;
-
- ret = adsp_pmem_lookup_vaddr(module, addr, len, ®ion);
- if (ret) {
- printk(KERN_ERR "adsp: not patching %s, lookup (%p, %ld) failed\n",
- module->name, vaddr, len);
- return ret;
- }
-
- *paddr = region->paddr + (vaddr - region->vaddr);
- return 0;
-}
-
-static int adsp_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- /* call the per module verifier */
- if (module->verify_cmd)
- return module->verify_cmd(module, queue_id, cmd_data,
- cmd_size);
- else
- printk(KERN_INFO "adsp: no packet verifying function "
- "for task %s\n", module->name);
- return 0;
-}
-
-static long adsp_write_cmd(struct adsp_device *adev, void __user *arg)
-{
- struct adsp_command_t cmd;
- unsigned char buf[256];
- void *cmd_data;
- long rc;
-
- if (copy_from_user(&cmd, (void __user *)arg, sizeof(cmd)))
- return -EFAULT;
-
- if (cmd.len > 256) {
- cmd_data = kmalloc(cmd.len, GFP_USER);
- if (!cmd_data)
- return -ENOMEM;
- } else {
- cmd_data = buf;
- }
-
- if (copy_from_user(cmd_data, (void __user *)(cmd.data), cmd.len)) {
- rc = -EFAULT;
- goto end;
- }
-
- mutex_lock(&adev->module->pmem_regions_lock);
- if (adsp_verify_cmd(adev->module, cmd.queue, cmd_data, cmd.len)) {
- printk(KERN_ERR "module %s: verify failed.\n",
- adev->module->name);
- rc = -EINVAL;
- goto end;
- }
- rc = msm_adsp_write(adev->module, cmd.queue, cmd_data, cmd.len);
-end:
- mutex_unlock(&adev->module->pmem_regions_lock);
-
- if (cmd.len > 256)
- kfree(cmd_data);
-
- return rc;
-}
-
-static int adsp_events_pending(struct adsp_device *adev)
-{
- unsigned long flags;
- int yes;
- spin_lock_irqsave(&adev->event_queue_lock, flags);
- yes = !list_empty(&adev->event_queue);
- spin_unlock_irqrestore(&adev->event_queue_lock, flags);
- return yes || adev->abort;
-}
-
-static int adsp_pmem_lookup_paddr(struct msm_adsp_module *module, void **addr,
- struct adsp_pmem_region **region)
-{
- struct hlist_node *node;
- unsigned long paddr = (unsigned long)(*addr);
- struct adsp_pmem_region *region_elt;
-
- hlist_for_each_entry(region_elt, node, &module->pmem_regions, list) {
- if (paddr >= region_elt->paddr &&
- paddr < region_elt->paddr + region_elt->len) {
- *region = region_elt;
- return 0;
- }
- }
- return -1;
-}
-
-int adsp_pmem_paddr_fixup(struct msm_adsp_module *module, void **addr)
-{
- struct adsp_pmem_region *region;
- unsigned long paddr = (unsigned long)(*addr);
- unsigned long *vaddr = (unsigned long *)addr;
- int ret;
-
- ret = adsp_pmem_lookup_paddr(module, addr, ®ion);
- if (ret) {
- printk(KERN_ERR "adsp: not patching %s, paddr %p lookup failed\n",
- module->name, vaddr);
- return ret;
- }
-
- *vaddr = (unsigned long)region->vaddr + (paddr - region->paddr);
- return 0;
-}
-
-static int adsp_patch_event(struct msm_adsp_module *module,
- struct adsp_event *event)
-{
- /* call the per-module msg verifier */
- if (module->patch_event)
- return module->patch_event(module, event);
- return 0;
-}
-
-static long adsp_get_event(struct adsp_device *adev, void __user *arg)
-{
- unsigned long flags;
- struct adsp_event *data = NULL;
- struct adsp_event_t evt;
- int timeout;
- long rc = 0;
-
- if (copy_from_user(&evt, arg, sizeof(struct adsp_event_t)))
- return -EFAULT;
-
- timeout = (int)evt.timeout_ms;
-
- if (timeout > 0) {
- rc = wait_event_interruptible_timeout(
- adev->event_wait, adsp_events_pending(adev),
- msecs_to_jiffies(timeout));
- if (rc == 0)
- return -ETIMEDOUT;
- } else {
- rc = wait_event_interruptible(
- adev->event_wait, adsp_events_pending(adev));
- }
- if (rc < 0)
- return rc;
-
- if (adev->abort)
- return -ENODEV;
-
- spin_lock_irqsave(&adev->event_queue_lock, flags);
- if (!list_empty(&adev->event_queue)) {
- data = list_first_entry(&adev->event_queue,
- struct adsp_event, list);
- list_del(&data->list);
- }
- spin_unlock_irqrestore(&adev->event_queue_lock, flags);
-
- if (!data)
- return -EAGAIN;
-
- /* DSP messages are type 0; they may contain physical addresses */
- if (data->type == 0)
- adsp_patch_event(adev->module, data);
-
- /* map adsp_event --> adsp_event_t */
- if (evt.len < data->size) {
- rc = -ETOOSMALL;
- goto end;
- }
- if (data->msg_id != EVENT_MSG_ID) {
- if (copy_to_user((void *)(evt.data), data->data.msg16,
- data->size)) {
- rc = -EFAULT;
- goto end;
- }
- } else {
- if (copy_to_user((void *)(evt.data), data->data.msg32,
- data->size)) {
- rc = -EFAULT;
- goto end;
- }
- }
-
- evt.type = data->type; /* 0 --> from aDSP, 1 --> from ARM9 */
- evt.msg_id = data->msg_id;
- evt.flags = data->is16;
- evt.len = data->size;
- if (copy_to_user(arg, &evt, sizeof(evt)))
- rc = -EFAULT;
-end:
- kfree(data);
- return rc;
-}
-
-static long adsp_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- struct adsp_device *adev = filp->private_data;
-
- switch (cmd) {
- case ADSP_IOCTL_ENABLE:
- return msm_adsp_enable(adev->module);
-
- case ADSP_IOCTL_DISABLE:
- return msm_adsp_disable(adev->module);
-
- case ADSP_IOCTL_DISABLE_EVENT_RSP:
- return 0;
-
- case ADSP_IOCTL_DISABLE_ACK:
- pr_err("adsp: ADSP_IOCTL_DISABLE_ACK is not implemented.\n");
- break;
-
- case ADSP_IOCTL_WRITE_COMMAND:
- return adsp_write_cmd(adev, (void __user *) arg);
-
- case ADSP_IOCTL_GET_EVENT:
- return adsp_get_event(adev, (void __user *) arg);
-
- case ADSP_IOCTL_SET_CLKRATE: {
-#if CONFIG_MSM_AMSS_VERSION==6350
- unsigned long clk_rate;
- if (copy_from_user(&clk_rate, (void *) arg, sizeof(clk_rate)))
- return -EFAULT;
- return adsp_set_clkrate(adev->module, clk_rate);
-#endif
- }
-
- case ADSP_IOCTL_REGISTER_PMEM: {
- struct adsp_pmem_info info;
- if (copy_from_user(&info, (void *) arg, sizeof(info)))
- return -EFAULT;
- return adsp_pmem_add(adev->module, &info);
- }
-
- case ADSP_IOCTL_ABORT_EVENT_READ:
- adev->abort = 1;
- wake_up(&adev->event_wait);
- break;
-
- default:
- break;
- }
- return -EINVAL;
-}
-
-static int adsp_release(struct inode *inode, struct file *filp)
-{
- struct adsp_device *adev = filp->private_data;
- struct msm_adsp_module *module = adev->module;
- struct hlist_node *node, *tmp;
- struct adsp_pmem_region *region;
-
- pr_info("adsp_release() '%s'\n", adev->name);
-
- /* clear module before putting it to avoid race with open() */
- adev->module = NULL;
-
- mutex_lock(&module->pmem_regions_lock);
- hlist_for_each_safe(node, tmp, &module->pmem_regions) {
- region = hlist_entry(node, struct adsp_pmem_region, list);
- hlist_del(node);
- put_pmem_file(region->file);
- kfree(region);
- }
- mutex_unlock(&module->pmem_regions_lock);
- BUG_ON(!hlist_empty(&module->pmem_regions));
-
- msm_adsp_put(module);
- return 0;
-}
-
-static void adsp_event(void *driver_data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- struct adsp_device *adev = driver_data;
- struct adsp_event *event;
- unsigned long flags;
-
- if (len > ADSP_EVENT_MAX_SIZE) {
- pr_err("adsp_event: event too large (%d bytes)\n", len);
- return;
- }
-
- event = kmalloc(sizeof(*event), GFP_ATOMIC);
- if (!event) {
- pr_err("adsp_event: cannot allocate buffer\n");
- return;
- }
-
- if (id != EVENT_MSG_ID) {
- event->type = 0;
- event->is16 = 0;
- event->msg_id = id;
- event->size = len;
-
- getevent(event->data.msg16, len);
- } else {
- event->type = 1;
- event->is16 = 1;
- event->msg_id = id;
- event->size = len;
- getevent(event->data.msg32, len);
- }
-
- spin_lock_irqsave(&adev->event_queue_lock, flags);
- list_add_tail(&event->list, &adev->event_queue);
- spin_unlock_irqrestore(&adev->event_queue_lock, flags);
- wake_up(&adev->event_wait);
-}
-
-static struct msm_adsp_ops adsp_ops = {
- .event = adsp_event,
-};
-
-static int adsp_open(struct inode *inode, struct file *filp)
-{
- struct adsp_device *adev;
- int rc;
-
- rc = nonseekable_open(inode, filp);
- if (rc < 0)
- return rc;
-
- adev = inode_to_device(inode);
- if (!adev)
- return -ENODEV;
-
- pr_info("adsp_open() name = '%s'\n", adev->name);
-
- rc = msm_adsp_get(adev->name, &adev->module, &adsp_ops, adev);
- if (rc)
- return rc;
-
- pr_info("adsp_open() module '%s' adev %p\n", adev->name, adev);
- filp->private_data = adev;
- adev->abort = 0;
- INIT_HLIST_HEAD(&adev->module->pmem_regions);
- mutex_init(&adev->module->pmem_regions_lock);
-
- return 0;
-}
-
-static unsigned adsp_device_count;
-static struct adsp_device *adsp_devices;
-
-static struct adsp_device *inode_to_device(struct inode *inode)
-{
- unsigned n = MINOR(inode->i_rdev);
- if (n < adsp_device_count) {
- if (adsp_devices[n].device)
- return adsp_devices + n;
- }
- return NULL;
-}
-
-static dev_t adsp_devno;
-static struct class *adsp_class;
-
-static struct file_operations adsp_fops = {
- .owner = THIS_MODULE,
- .open = adsp_open,
- .unlocked_ioctl = adsp_ioctl,
- .release = adsp_release,
- .llseek = no_llseek,
-};
-
-static void adsp_create(struct adsp_device *adev, const char *name,
- struct device *parent, dev_t devt)
-{
- struct device *dev;
- int rc;
-
- dev = device_create(adsp_class, parent, devt, "%s", name);
- if (IS_ERR(dev))
- return;
-
- init_waitqueue_head(&adev->event_wait);
- INIT_LIST_HEAD(&adev->event_queue);
- spin_lock_init(&adev->event_queue_lock);
-
- cdev_init(&adev->cdev, &adsp_fops);
- adev->cdev.owner = THIS_MODULE;
-
- rc = cdev_add(&adev->cdev, devt, 1);
- if (rc < 0) {
- device_destroy(adsp_class, devt);
- } else {
- adev->device = dev;
- adev->name = name;
- }
-}
-
-void msm_adsp_publish_cdevs(struct msm_adsp_module *modules, unsigned n)
-{
- int rc;
-
- adsp_devices = kzalloc(sizeof(struct adsp_device) * n, GFP_KERNEL);
- if (!adsp_devices)
- return;
-
- adsp_class = class_create(THIS_MODULE, "adsp");
- if (IS_ERR(adsp_class))
- goto fail_create_class;
-
- rc = alloc_chrdev_region(&adsp_devno, 0, n, "adsp");
- if (rc < 0)
- goto fail_alloc_region;
-
- adsp_device_count = n;
- for (n = 0; n < adsp_device_count; n++) {
- adsp_create(adsp_devices + n,
- modules[n].name, &modules[n].pdev.dev,
- MKDEV(MAJOR(adsp_devno), n));
- }
-
- return;
-
-fail_alloc_region:
- class_unregister(adsp_class);
-fail_create_class:
- kfree(adsp_devices);
-}
+++ /dev/null
-/* arch/arm/mach-msm/adsp_info.c
- *
- * Copyright (c) 2008 QUALCOMM Incorporated.
- * Copyright (c) 2008 QUALCOMM USA, INC.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include "adsp.h"
-
-/* Firmware modules */
-#define QDSP_MODULE_KERNEL 0x0106dd4e
-#define QDSP_MODULE_AFETASK 0x0106dd6f
-#define QDSP_MODULE_AUDPLAY0TASK 0x0106dd70
-#define QDSP_MODULE_AUDPLAY1TASK 0x0106dd71
-#define QDSP_MODULE_AUDPPTASK 0x0106dd72
-#define QDSP_MODULE_VIDEOTASK 0x0106dd73
-#define QDSP_MODULE_VIDEO_AAC_VOC 0x0106dd74
-#define QDSP_MODULE_PCM_DEC 0x0106dd75
-#define QDSP_MODULE_AUDIO_DEC_MP3 0x0106dd76
-#define QDSP_MODULE_AUDIO_DEC_AAC 0x0106dd77
-#define QDSP_MODULE_AUDIO_DEC_WMA 0x0106dd78
-#define QDSP_MODULE_HOSTPCM 0x0106dd79
-#define QDSP_MODULE_DTMF 0x0106dd7a
-#define QDSP_MODULE_AUDRECTASK 0x0106dd7b
-#define QDSP_MODULE_AUDPREPROCTASK 0x0106dd7c
-#define QDSP_MODULE_SBC_ENC 0x0106dd7d
-#define QDSP_MODULE_VOC_UMTS 0x0106dd9a
-#define QDSP_MODULE_VOC_CDMA 0x0106dd98
-#define QDSP_MODULE_VOC_PCM 0x0106dd7f
-#define QDSP_MODULE_VOCENCTASK 0x0106dd80
-#define QDSP_MODULE_VOCDECTASK 0x0106dd81
-#define QDSP_MODULE_VOICEPROCTASK 0x0106dd82
-#define QDSP_MODULE_VIDEOENCTASK 0x0106dd83
-#define QDSP_MODULE_VFETASK 0x0106dd84
-#define QDSP_MODULE_WAV_ENC 0x0106dd85
-#define QDSP_MODULE_AACLC_ENC 0x0106dd86
-#define QDSP_MODULE_VIDEO_AMR 0x0106dd87
-#define QDSP_MODULE_VOC_AMR 0x0106dd88
-#define QDSP_MODULE_VOC_EVRC 0x0106dd89
-#define QDSP_MODULE_VOC_13K 0x0106dd8a
-#define QDSP_MODULE_VOC_FGV 0x0106dd8b
-#define QDSP_MODULE_DIAGTASK 0x0106dd8c
-#define QDSP_MODULE_JPEGTASK 0x0106dd8d
-#define QDSP_MODULE_LPMTASK 0x0106dd8e
-#define QDSP_MODULE_QCAMTASK 0x0106dd8f
-#define QDSP_MODULE_MODMATHTASK 0x0106dd90
-#define QDSP_MODULE_AUDPLAY2TASK 0x0106dd91
-#define QDSP_MODULE_AUDPLAY3TASK 0x0106dd92
-#define QDSP_MODULE_AUDPLAY4TASK 0x0106dd93
-#define QDSP_MODULE_GRAPHICSTASK 0x0106dd94
-#define QDSP_MODULE_MIDI 0x0106dd95
-#define QDSP_MODULE_GAUDIO 0x0106dd96
-#define QDSP_MODULE_VDEC_LP_MODE 0x0106dd97
-#define QDSP_MODULE_MAX 0x7fffffff
-
- /* DO NOT USE: Force this enum to be a 32bit type to improve speed */
-#define QDSP_MODULE_32BIT_DUMMY 0x10000
-
-static uint32_t *qdsp_task_to_module[IMG_MAX];
-static uint32_t *qdsp_queue_offset_table[IMG_MAX];
-
-#define QDSP_MODULE(n, clkname, clkrate, verify_cmd_func, patch_event_func) \
- { .name = #n, .pdev_name = "adsp_" #n, .id = QDSP_MODULE_##n, \
- .clk_name = clkname, .clk_rate = clkrate, \
- .verify_cmd = verify_cmd_func, .patch_event = patch_event_func }
-
-static struct adsp_module_info module_info[] = {
- QDSP_MODULE(AUDPLAY0TASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDPPTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDRECTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(AUDPREPROCTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(VFETASK, "vfe_clk", 0, adsp_vfe_verify_cmd,
- adsp_vfe_patch_event),
- QDSP_MODULE(QCAMTASK, NULL, 0, NULL, NULL),
- QDSP_MODULE(LPMTASK, NULL, 0, adsp_lpm_verify_cmd, NULL),
- QDSP_MODULE(JPEGTASK, "vdc_clk", 96000000, adsp_jpeg_verify_cmd,
- adsp_jpeg_patch_event),
- QDSP_MODULE(VIDEOTASK, "vdc_clk", 96000000,
- adsp_video_verify_cmd, NULL),
- QDSP_MODULE(VDEC_LP_MODE, NULL, 0, NULL, NULL),
- QDSP_MODULE(VIDEOENCTASK, "vdc_clk", 96000000,
- adsp_videoenc_verify_cmd, NULL),
-};
-
-int adsp_init_info(struct adsp_info *info)
-{
- uint32_t img_num;
-
- info->send_irq = 0x00c00200;
- info->read_ctrl = 0x00400038;
- info->write_ctrl = 0x00400034;
-
- info->max_msg16_size = 193;
- info->max_msg32_size = 8;
- for (img_num = 0; img_num < IMG_MAX; img_num++)
- qdsp_queue_offset_table[img_num] =
- &info->init_info_ptr->queue_offsets[img_num][0];
-
- for (img_num = 0; img_num < IMG_MAX; img_num++)
- qdsp_task_to_module[img_num] =
- &info->init_info_ptr->task_to_module_tbl[img_num][0];
- info->max_task_id = 30;
- info->max_module_id = QDSP_MODULE_MAX - 1;
- info->max_queue_id = QDSP_MAX_NUM_QUEUES;
- info->max_image_id = 2;
- info->queue_offset = qdsp_queue_offset_table;
- info->task_to_module = qdsp_task_to_module;
-
- info->module_count = ARRAY_SIZE(module_info);
- info->module = module_info;
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_jpeg_patch_event.c
- *
- * Verification code for aDSP JPEG events.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/qdsp5/qdsp5jpegmsg.h>
-#include "adsp.h"
-
-int adsp_jpeg_patch_event(struct msm_adsp_module *module,
- struct adsp_event *event)
-{
- if (event->msg_id == JPEG_MSG_ENC_OP_PRODUCED) {
- jpeg_msg_enc_op_produced *op = (jpeg_msg_enc_op_produced *)event->data.msg16;
- return adsp_pmem_paddr_fixup(module, (void **)&op->op_buf_addr);
- }
-
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_jpeg_verify_cmd.c
- *
- * Verification code for aDSP JPEG packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/qdsp5/qdsp5jpegcmdi.h>
-#include "adsp.h"
-
-static uint32_t dec_fmt;
-
-static inline void get_sizes(jpeg_cmd_enc_cfg *cmd, uint32_t *luma_size,
- uint32_t *chroma_size)
-{
- uint32_t fmt, luma_width, luma_height;
-
- fmt = cmd->process_cfg & JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_M;
- luma_width = (cmd->ip_size_cfg & JPEG_CMD_IP_SIZE_CFG_LUMA_WIDTH_M)
- >> 16;
- luma_height = cmd->frag_cfg & JPEG_CMD_FRAG_SIZE_LUMA_HEIGHT_M;
- *luma_size = luma_width * luma_height;
- if (fmt == JPEG_CMD_ENC_PROCESS_CFG_IP_DATA_FORMAT_H2V2)
- *chroma_size = *luma_size/2;
- else
- *chroma_size = *luma_size;
-}
-
-static inline int verify_jpeg_cmd_enc_cfg(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- jpeg_cmd_enc_cfg *cmd = (jpeg_cmd_enc_cfg *)cmd_data;
- uint32_t luma_size, chroma_size;
- int i, num_frags;
-
- if (cmd_size != sizeof(jpeg_cmd_enc_cfg)) {
- printk(KERN_ERR "adsp: module %s: JPEG ENC CFG invalid cmd_size %d\n",
- module->name, cmd_size);
- return -1;
- }
-
- get_sizes(cmd, &luma_size, &chroma_size);
- num_frags = (cmd->process_cfg >> 10) & 0xf;
- num_frags = ((num_frags == 1) ? num_frags : num_frags * 2);
- for (i = 0; i < num_frags; i += 2) {
- if (adsp_pmem_fixup(module, (void **)(&cmd->frag_cfg_part[i]), luma_size) ||
- adsp_pmem_fixup(module, (void **)(&cmd->frag_cfg_part[i+1]), chroma_size))
- return -1;
- }
-
- if (adsp_pmem_fixup(module, (void **)&cmd->op_buf_0_cfg_part1,
- cmd->op_buf_0_cfg_part2) ||
- adsp_pmem_fixup(module, (void **)&cmd->op_buf_1_cfg_part1,
- cmd->op_buf_1_cfg_part2))
- return -1;
- return 0;
-}
-
-static inline int verify_jpeg_cmd_dec_cfg(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- jpeg_cmd_dec_cfg *cmd = (jpeg_cmd_dec_cfg *)cmd_data;
- uint32_t div;
-
- if (cmd_size != sizeof(jpeg_cmd_dec_cfg)) {
- printk(KERN_ERR "adsp: module %s: JPEG DEC CFG invalid cmd_size %d\n",
- module->name, cmd_size);
- return -1;
- }
-
- if (adsp_pmem_fixup(module, (void **)&cmd->ip_stream_buf_cfg_part1,
- cmd->ip_stream_buf_cfg_part2) ||
- adsp_pmem_fixup(module, (void **)&cmd->op_stream_buf_0_cfg_part1,
- cmd->op_stream_buf_0_cfg_part2) ||
- adsp_pmem_fixup(module, (void **)&cmd->op_stream_buf_1_cfg_part1,
- cmd->op_stream_buf_1_cfg_part2))
- return -1;
- dec_fmt = cmd->op_data_format &
- JPEG_CMD_DEC_OP_DATA_FORMAT_M;
- div = (dec_fmt == JPEG_CMD_DEC_OP_DATA_FORMAT_H2V2) ? 2 : 1;
- if (adsp_pmem_fixup(module, (void **)&cmd->op_stream_buf_0_cfg_part3,
- cmd->op_stream_buf_0_cfg_part2 / div) ||
- adsp_pmem_fixup(module, (void **)&cmd->op_stream_buf_1_cfg_part3,
- cmd->op_stream_buf_1_cfg_part2 / div))
- return -1;
- return 0;
-}
-
-static int verify_jpeg_cfg_cmd(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- uint32_t cmd_id = ((uint32_t *)cmd_data)[0];
- switch(cmd_id) {
- case JPEG_CMD_ENC_CFG:
- return verify_jpeg_cmd_enc_cfg(module, cmd_data, cmd_size);
- case JPEG_CMD_DEC_CFG:
- return verify_jpeg_cmd_dec_cfg(module, cmd_data, cmd_size);
- default:
- if (cmd_id > 1) {
- printk(KERN_ERR "adsp: module %s: invalid JPEG CFG cmd_id %d\n", module->name, cmd_id);
- return -1;
- }
- }
- return 0;
-}
-
-static int verify_jpeg_action_cmd(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- uint32_t cmd_id = ((uint32_t *)cmd_data)[0];
- switch (cmd_id) {
- case JPEG_CMD_ENC_OP_CONSUMED:
- {
- jpeg_cmd_enc_op_consumed *cmd =
- (jpeg_cmd_enc_op_consumed *)cmd_data;
-
- if (cmd_size != sizeof(jpeg_cmd_enc_op_consumed)) {
- printk(KERN_ERR "adsp: module %s: JPEG_CMD_ENC_OP_CONSUMED invalid size %d\n",
- module->name, cmd_size);
- return -1;
- }
-
- if (adsp_pmem_fixup(module, (void **)&cmd->op_buf_addr,
- cmd->op_buf_size))
- return -1;
- }
- break;
- case JPEG_CMD_DEC_OP_CONSUMED:
- {
- uint32_t div;
- jpeg_cmd_dec_op_consumed *cmd =
- (jpeg_cmd_dec_op_consumed *)cmd_data;
-
- if (cmd_size != sizeof(jpeg_cmd_enc_op_consumed)) {
- printk(KERN_ERR "adsp: module %s: JPEG_CMD_DEC_OP_CONSUMED invalid size %d\n",
- module->name, cmd_size);
- return -1;
- }
-
- div = (dec_fmt == JPEG_CMD_DEC_OP_DATA_FORMAT_H2V2) ? 2 : 1;
- if (adsp_pmem_fixup(module, (void **)&cmd->luma_op_buf_addr,
- cmd->luma_op_buf_size) ||
- adsp_pmem_fixup(module, (void **)&cmd->chroma_op_buf_addr,
- cmd->luma_op_buf_size / div))
- return -1;
- }
- break;
- default:
- if (cmd_id > 7) {
- printk(KERN_ERR "adsp: module %s: invalid cmd_id %d\n",
- module->name, cmd_id);
- return -1;
- }
- }
- return 0;
-}
-
-int adsp_jpeg_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- switch(queue_id) {
- case QDSP_uPJpegCfgCmdQueue:
- return verify_jpeg_cfg_cmd(module, cmd_data, cmd_size);
- case QDSP_uPJpegActionCmdQueue:
- return verify_jpeg_action_cmd(module, cmd_data, cmd_size);
- default:
- return -1;
- }
-}
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_lpm_verify_cmd.c
- *
- * Verificion code for aDSP LPM packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/qdsp5/qdsp5lpmcmdi.h>
-#include "adsp.h"
-
-int adsp_lpm_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- uint32_t cmd_id, col_height, input_row_incr, output_row_incr,
- input_size, output_size;
- uint32_t size_mask = 0x0fff;
- lpm_cmd_start *cmd;
-
- if (queue_id != QDSP_lpmCommandQueue) {
- printk(KERN_ERR "adsp: module %s: wrong queue id %d\n",
- module->name, queue_id);
- return -1;
- }
-
- cmd = (lpm_cmd_start *)cmd_data;
- cmd_id = cmd->cmd_id;
-
- if (cmd_id == LPM_CMD_START) {
- if (cmd_size != sizeof(lpm_cmd_start)) {
- printk(KERN_ERR "adsp: module %s: wrong size %d, expect %d\n",
- module->name, cmd_size, sizeof(lpm_cmd_start));
- return -1;
- }
- col_height = cmd->ip_data_cfg_part1 & size_mask;
- input_row_incr = cmd->ip_data_cfg_part2 & size_mask;
- output_row_incr = cmd->op_data_cfg_part1 & size_mask;
- input_size = col_height * input_row_incr;
- output_size = col_height * output_row_incr;
- if ((cmd->ip_data_cfg_part4 && adsp_pmem_fixup(module,
- (void **)(&cmd->ip_data_cfg_part4),
- input_size)) ||
- (cmd->op_data_cfg_part3 && adsp_pmem_fixup(module,
- (void **)(&cmd->op_data_cfg_part3),
- output_size)))
- return -1;
- } else if (cmd_id > 1) {
- printk(KERN_ERR "adsp: module %s: invalid cmd_id %d\n",
- module->name, cmd_id);
- return -1;
- }
- return 0;
-}
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_vfe_patch_event.c
- *
- * Verification code for aDSP VFE packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/qdsp5/qdsp5vfemsg.h>
-#include "adsp.h"
-
-static int patch_op_event(struct msm_adsp_module *module,
- struct adsp_event *event)
-{
- vfe_msg_op1 *op = (vfe_msg_op1 *)event->data.msg16;
- if (adsp_pmem_paddr_fixup(module, (void **)&op->op1_buf_y_addr) ||
- adsp_pmem_paddr_fixup(module, (void **)&op->op1_buf_cbcr_addr))
- return -1;
- return 0;
-}
-
-static int patch_af_wb_event(struct msm_adsp_module *module,
- struct adsp_event *event)
-{
- vfe_msg_stats_wb_exp *af = (vfe_msg_stats_wb_exp *)event->data.msg16;
- return adsp_pmem_paddr_fixup(module, (void **)&af->wb_exp_stats_op_buf);
-}
-
-int adsp_vfe_patch_event(struct msm_adsp_module *module,
- struct adsp_event *event)
-{
- switch(event->msg_id) {
- case VFE_MSG_OP1:
- case VFE_MSG_OP2:
- return patch_op_event(module, event);
- case VFE_MSG_STATS_AF:
- case VFE_MSG_STATS_WB_EXP:
- return patch_af_wb_event(module, event);
- default:
- break;
- }
-
- return 0;
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_vfe_verify_cmd.c
- *
- * Verification code for aDSP VFE packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/qdsp5/qdsp5vfecmdi.h>
-#include "adsp.h"
-
-static uint32_t size1_y, size2_y, size1_cbcr, size2_cbcr;
-static uint32_t af_size = 4228;
-static uint32_t awb_size = 8196;
-
-static inline int verify_cmd_op_ack(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- vfe_cmd_op1_ack *cmd = (vfe_cmd_op1_ack *)cmd_data;
- void **addr_y = (void **)&cmd->op1_buf_y_addr;
- void **addr_cbcr = (void **)(&cmd->op1_buf_cbcr_addr);
-
- if (cmd_size != sizeof(vfe_cmd_op1_ack))
- return -1;
- if ((*addr_y && adsp_pmem_fixup(module, addr_y, size1_y)) ||
- (*addr_cbcr && adsp_pmem_fixup(module, addr_cbcr, size1_cbcr)))
- return -1;
- return 0;
-}
-
-static inline int verify_cmd_stats_autofocus_cfg(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- int i;
- vfe_cmd_stats_autofocus_cfg *cmd =
- (vfe_cmd_stats_autofocus_cfg *)cmd_data;
-
- if (cmd_size != sizeof(vfe_cmd_stats_autofocus_cfg))
- return -1;
-
- for (i = 0; i < 3; i++) {
- void **addr = (void **)(&cmd->af_stats_op_buf[i]);
- if (*addr && adsp_pmem_fixup(module, addr, af_size))
- return -1;
- }
- return 0;
-}
-
-static inline int verify_cmd_stats_wb_exp_cfg(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- vfe_cmd_stats_wb_exp_cfg *cmd =
- (vfe_cmd_stats_wb_exp_cfg *)cmd_data;
- int i;
-
- if (cmd_size != sizeof(vfe_cmd_stats_wb_exp_cfg))
- return -1;
-
- for (i = 0; i < 3; i++) {
- void **addr = (void **)(&cmd->wb_exp_stats_op_buf[i]);
- if (*addr && adsp_pmem_fixup(module, addr, awb_size))
- return -1;
- }
- return 0;
-}
-
-static inline int verify_cmd_stats_af_ack(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- vfe_cmd_stats_af_ack *cmd = (vfe_cmd_stats_af_ack *)cmd_data;
- void **addr = (void **)&cmd->af_stats_op_buf;
-
- if (cmd_size != sizeof(vfe_cmd_stats_af_ack))
- return -1;
-
- if (*addr && adsp_pmem_fixup(module, addr, af_size))
- return -1;
- return 0;
-}
-
-static inline int verify_cmd_stats_wb_exp_ack(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- vfe_cmd_stats_wb_exp_ack *cmd =
- (vfe_cmd_stats_wb_exp_ack *)cmd_data;
- void **addr = (void **)&cmd->wb_exp_stats_op_buf;
-
- if (cmd_size != sizeof(vfe_cmd_stats_wb_exp_ack))
- return -1;
-
- if (*addr && adsp_pmem_fixup(module, addr, awb_size))
- return -1;
- return 0;
-}
-
-static int verify_vfe_command(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- uint32_t cmd_id = ((uint32_t *)cmd_data)[0];
- switch (cmd_id) {
- case VFE_CMD_OP1_ACK:
- return verify_cmd_op_ack(module, cmd_data, cmd_size);
- case VFE_CMD_OP2_ACK:
- return verify_cmd_op_ack(module, cmd_data, cmd_size);
- case VFE_CMD_STATS_AUTOFOCUS_CFG:
- return verify_cmd_stats_autofocus_cfg(module, cmd_data,
- cmd_size);
- case VFE_CMD_STATS_WB_EXP_CFG:
- return verify_cmd_stats_wb_exp_cfg(module, cmd_data, cmd_size);
- case VFE_CMD_STATS_AF_ACK:
- return verify_cmd_stats_af_ack(module, cmd_data, cmd_size);
- case VFE_CMD_STATS_WB_EXP_ACK:
- return verify_cmd_stats_wb_exp_ack(module, cmd_data, cmd_size);
- default:
- if (cmd_id > 29) {
- printk(KERN_ERR "adsp: module %s: invalid VFE command id %d\n", module->name, cmd_id);
- return -1;
- }
- }
- return 0;
-}
-
-static int verify_vfe_command_scale(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- uint32_t cmd_id = ((uint32_t *)cmd_data)[0];
- // FIXME: check the size
- if (cmd_id > 1) {
- printk(KERN_ERR "adsp: module %s: invalid VFE SCALE command id %d\n", module->name, cmd_id);
- return -1;
- }
- return 0;
-}
-
-
-static uint32_t get_size(uint32_t hw)
-{
- uint32_t height, width;
- uint32_t height_mask = 0x3ffc;
- uint32_t width_mask = 0x3ffc000;
-
- height = (hw & height_mask) >> 2;
- width = (hw & width_mask) >> 14 ;
- return height * width;
-}
-
-static int verify_vfe_command_table(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- uint32_t cmd_id = ((uint32_t *)cmd_data)[0];
- int i;
-
- switch (cmd_id) {
- case VFE_CMD_AXI_IP_CFG:
- {
- vfe_cmd_axi_ip_cfg *cmd = (vfe_cmd_axi_ip_cfg *)cmd_data;
- uint32_t size;
- if (cmd_size != sizeof(vfe_cmd_axi_ip_cfg)) {
- printk(KERN_ERR "adsp: module %s: invalid VFE TABLE (VFE_CMD_AXI_IP_CFG) command size %d\n",
- module->name, cmd_size);
- return -1;
- }
- size = get_size(cmd->ip_cfg_part2);
-
- for (i = 0; i < 8; i++) {
- void **addr = (void **)
- &cmd->ip_buf_addr[i];
- if (*addr && adsp_pmem_fixup(module, addr, size))
- return -1;
- }
- }
- case VFE_CMD_AXI_OP_CFG:
- {
- vfe_cmd_axi_op_cfg *cmd = (vfe_cmd_axi_op_cfg *)cmd_data;
- void **addr1_y, **addr2_y, **addr1_cbcr, **addr2_cbcr;
-
- if (cmd_size != sizeof(vfe_cmd_axi_op_cfg)) {
- printk(KERN_ERR "adsp: module %s: invalid VFE TABLE (VFE_CMD_AXI_OP_CFG) command size %d\n",
- module->name, cmd_size);
- return -1;
- }
- size1_y = get_size(cmd->op1_y_cfg_part2);
- size1_cbcr = get_size(cmd->op1_cbcr_cfg_part2);
- size2_y = get_size(cmd->op2_y_cfg_part2);
- size2_cbcr = get_size(cmd->op2_cbcr_cfg_part2);
- for (i = 0; i < 8; i++) {
- addr1_y = (void **)(&cmd->op1_buf1_addr[2*i]);
- addr1_cbcr = (void **)(&cmd->op1_buf1_addr[2*i+1]);
- addr2_y = (void **)(&cmd->op2_buf1_addr[2*i]);
- addr2_cbcr = (void **)(&cmd->op2_buf1_addr[2*i+1]);
-/*
- printk("module %s: [%d] %p %p %p %p\n",
- module->name, i,
- *addr1_y, *addr1_cbcr, *addr2_y, *addr2_cbcr);
-*/
- if ((*addr1_y && adsp_pmem_fixup(module, addr1_y, size1_y)) ||
- (*addr1_cbcr && adsp_pmem_fixup(module, addr1_cbcr, size1_cbcr)) ||
- (*addr2_y && adsp_pmem_fixup(module, addr2_y, size2_y)) ||
- (*addr2_cbcr && adsp_pmem_fixup(module, addr2_cbcr, size2_cbcr)))
- return -1;
- }
- }
- default:
- if (cmd_id > 4) {
- printk(KERN_ERR "adsp: module %s: invalid VFE TABLE command id %d\n",
- module->name, cmd_id);
- return -1;
- }
- }
- return 0;
-}
-
-int adsp_vfe_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- switch (queue_id) {
- case QDSP_vfeCommandQueue:
- return verify_vfe_command(module, cmd_data, cmd_size);
- case QDSP_vfeCommandScaleQueue:
- return verify_vfe_command_scale(module, cmd_data, cmd_size);
- case QDSP_vfeCommandTableQueue:
- return verify_vfe_command_table(module, cmd_data, cmd_size);
- default:
- printk(KERN_ERR "adsp: module %s: unknown queue id %d\n",
- module->name, queue_id);
- return -1;
- }
-}
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_video_verify_cmd.c
- *
- * Verificion code for aDSP VDEC packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/io.h>
-
-#define ADSP_DEBUG_MSGS 0
-#if ADSP_DEBUG_MSGS
-#define DLOG(fmt,args...) \
- do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \
- ##args); } \
- while (0)
-#else
-#define DLOG(x...) do {} while (0)
-#endif
-
-
-#include <mach/qdsp5/qdsp5vdeccmdi.h>
-#include "adsp.h"
-
-static inline void *high_low_short_to_ptr(unsigned short high,
- unsigned short low)
-{
- return (void *)((((unsigned long)high) << 16) | ((unsigned long)low));
-}
-
-static inline void ptr_to_high_low_short(void *ptr, unsigned short *high,
- unsigned short *low)
-{
- *high = (unsigned short)((((unsigned long)ptr) >> 16) & 0xffff);
- *low = (unsigned short)((unsigned long)ptr & 0xffff);
-}
-
-static int pmem_fixup_high_low(unsigned short *high,
- unsigned short *low,
- unsigned short size_high,
- unsigned short size_low,
- struct msm_adsp_module *module,
- unsigned long *addr, unsigned long *size)
-{
- void *phys_addr;
- unsigned long phys_size;
- unsigned long kvaddr;
-
- phys_addr = high_low_short_to_ptr(*high, *low);
- phys_size = (unsigned long)high_low_short_to_ptr(size_high, size_low);
- DLOG("virt %x %x\n", phys_addr, phys_size);
- if (adsp_pmem_fixup_kvaddr(module, &phys_addr, &kvaddr, phys_size)) {
- DLOG("ah%x al%x sh%x sl%x addr %x size %x\n",
- *high, *low, size_high, size_low, phys_addr, phys_size);
- return -1;
- }
- ptr_to_high_low_short(phys_addr, high, low);
- DLOG("phys %x %x\n", phys_addr, phys_size);
- if (addr)
- *addr = kvaddr;
- if (size)
- *size = phys_size;
- return 0;
-}
-
-static int verify_vdec_pkt_cmd(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- unsigned short cmd_id = ((unsigned short *)cmd_data)[0];
- viddec_cmd_subframe_pkt *pkt;
- unsigned long subframe_pkt_addr;
- unsigned long subframe_pkt_size;
- viddec_cmd_frame_header_packet *frame_header_pkt;
- int i, num_addr, skip;
- unsigned short *frame_buffer_high, *frame_buffer_low;
- unsigned long frame_buffer_size;
- unsigned short frame_buffer_size_high, frame_buffer_size_low;
-
- DLOG("cmd_size %d cmd_id %d cmd_data %x\n", cmd_size, cmd_id, cmd_data);
- if (cmd_id != VIDDEC_CMD_SUBFRAME_PKT) {
- printk(KERN_INFO "adsp_video: unknown video packet %u\n",
- cmd_id);
- return 0;
- }
- if (cmd_size < sizeof(viddec_cmd_subframe_pkt))
- return -1;
-
- pkt = (viddec_cmd_subframe_pkt *)cmd_data;
-
- if (pmem_fixup_high_low(&(pkt->subframe_packet_high),
- &(pkt->subframe_packet_low),
- pkt->subframe_packet_size_high,
- pkt->subframe_packet_size_low,
- module,
- &subframe_pkt_addr,
- &subframe_pkt_size))
- return -1;
-
- /* deref those ptrs and check if they are a frame header packet */
- frame_header_pkt = (viddec_cmd_frame_header_packet *)subframe_pkt_addr;
-
- switch (frame_header_pkt->packet_id) {
- case 0xB201: /* h.264 */
- num_addr = skip = 8;
- break;
- case 0x4D01: /* mpeg-4 and h.263 */
- num_addr = 3;
- skip = 0;
- break;
- default:
- return 0;
- }
-
- frame_buffer_high = &frame_header_pkt->frame_buffer_0_high;
- frame_buffer_low = &frame_header_pkt->frame_buffer_0_low;
- frame_buffer_size = (frame_header_pkt->x_dimension *
- frame_header_pkt->y_dimension * 3) / 2;
- ptr_to_high_low_short((void *)frame_buffer_size,
- &frame_buffer_size_high,
- &frame_buffer_size_low);
- for (i = 0; i < num_addr; i++) {
- if (pmem_fixup_high_low(frame_buffer_high, frame_buffer_low,
- frame_buffer_size_high,
- frame_buffer_size_low,
- module,
- NULL, NULL))
- return -1;
- frame_buffer_high += 2;
- frame_buffer_low += 2;
- }
- /* Patch the output buffer. */
- frame_buffer_high += 2*skip;
- frame_buffer_low += 2*skip;
- if (pmem_fixup_high_low(frame_buffer_high, frame_buffer_low,
- frame_buffer_size_high,
- frame_buffer_size_low, module, NULL, NULL))
- return -1;
- return 0;
-}
-
-int adsp_video_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- switch (queue_id) {
- case QDSP_mpuVDecPktQueue:
- DLOG("\n");
- return verify_vdec_pkt_cmd(module, cmd_data, cmd_size);
- default:
- printk(KERN_INFO "unknown video queue %u\n", queue_id);
- return 0;
- }
-}
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/adsp_video_verify_cmd.c
- *
- * Verificion code for aDSP VENC packets from userspace.
- *
- * Copyright (c) 2008 QUALCOMM Incorporated
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/io.h>
-
-#define ADSP_DEBUG_MSGS 0
-#if ADSP_DEBUG_MSGS
-#define DLOG(fmt,args...) \
- do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \
- ##args); } \
- while (0)
-#else
-#define DLOG(x...) do {} while (0)
-#endif
-
-#include <mach/qdsp5/qdsp5venccmdi.h>
-#include "adsp.h"
-
-
-static unsigned short x_dimension, y_dimension;
-
-static inline void *high_low_short_to_ptr(unsigned short high,
- unsigned short low)
-{
- return (void *)((((unsigned long)high) << 16) | ((unsigned long)low));
-}
-
-static inline void ptr_to_high_low_short(void *ptr, unsigned short *high,
- unsigned short *low)
-{
- *high = (unsigned short)((((unsigned long)ptr) >> 16) & 0xffff);
- *low = (unsigned short)((unsigned long)ptr & 0xffff);
-}
-
-static int pmem_fixup_high_low(unsigned short *high,
- unsigned short *low,
- unsigned short size_high,
- unsigned short size_low,
- struct msm_adsp_module *module,
- unsigned long *addr, unsigned long *size)
-{
- void *phys_addr;
- unsigned long phys_size;
- unsigned long kvaddr;
-
- phys_addr = high_low_short_to_ptr(*high, *low);
- phys_size = (unsigned long)high_low_short_to_ptr(size_high, size_low);
- DLOG("virt %x %x\n", phys_addr, phys_size);
- if (adsp_pmem_fixup_kvaddr(module, &phys_addr, &kvaddr, phys_size)) {
- DLOG("ah%x al%x sh%x sl%x addr %x size %x\n",
- *high, *low, size_high, size_low, phys_addr, phys_size);
- return -1;
- }
- ptr_to_high_low_short(phys_addr, high, low);
- DLOG("phys %x %x\n", phys_addr, phys_size);
- if (addr)
- *addr = kvaddr;
- if (size)
- *size = phys_size;
- return 0;
-}
-
-static int verify_venc_cmd(struct msm_adsp_module *module,
- void *cmd_data, size_t cmd_size)
-{
- unsigned short cmd_id = ((unsigned short *)cmd_data)[0];
- unsigned long frame_buf_size, luma_buf_size, chroma_buf_size;
- unsigned short frame_buf_size_high, frame_buf_size_low;
- unsigned short luma_buf_size_high, luma_buf_size_low;
- unsigned short chroma_buf_size_high, chroma_buf_size_low;
- videnc_cmd_cfg *config_cmd;
- videnc_cmd_frame_start *frame_cmd;
- videnc_cmd_dis *dis_cmd;
-
- DLOG("cmd_size %d cmd_id %d cmd_data %x\n", cmd_size, cmd_id, cmd_data);
- switch (cmd_id) {
- case VIDENC_CMD_ACTIVE:
- if (cmd_size < sizeof(videnc_cmd_active))
- return -1;
- break;
- case VIDENC_CMD_IDLE:
- if (cmd_size < sizeof(videnc_cmd_idle))
- return -1;
- x_dimension = y_dimension = 0;
- break;
- case VIDENC_CMD_STATUS_QUERY:
- if (cmd_size < sizeof(videnc_cmd_status_query))
- return -1;
- break;
- case VIDENC_CMD_RC_CFG:
- if (cmd_size < sizeof(videnc_cmd_rc_cfg))
- return -1;
- break;
- case VIDENC_CMD_INTRA_REFRESH:
- if (cmd_size < sizeof(videnc_cmd_intra_refresh))
- return -1;
- break;
- case VIDENC_CMD_DIGITAL_ZOOM:
- if (cmd_size < sizeof(videnc_cmd_digital_zoom))
- return -1;
- break;
- case VIDENC_CMD_DIS_CFG:
- if (cmd_size < sizeof(videnc_cmd_dis_cfg))
- return -1;
- break;
- case VIDENC_CMD_CFG:
- if (cmd_size < sizeof(videnc_cmd_cfg))
- return -1;
- config_cmd = (videnc_cmd_cfg *)cmd_data;
- x_dimension = ((config_cmd->venc_frame_dim) & 0xFF00)>>8;
- x_dimension = x_dimension*16;
- y_dimension = (config_cmd->venc_frame_dim) & 0xFF;
- y_dimension = y_dimension * 16;
- break;
- case VIDENC_CMD_FRAME_START:
- if (cmd_size < sizeof(videnc_cmd_frame_start))
- return -1;
- frame_cmd = (videnc_cmd_frame_start *)cmd_data;
- luma_buf_size = x_dimension * y_dimension;
- chroma_buf_size = luma_buf_size>>1;
- frame_buf_size = luma_buf_size + chroma_buf_size;
- ptr_to_high_low_short((void *)luma_buf_size,
- &luma_buf_size_high,
- &luma_buf_size_low);
- ptr_to_high_low_short((void *)chroma_buf_size,
- &chroma_buf_size_high,
- &chroma_buf_size_low);
- ptr_to_high_low_short((void *)frame_buf_size,
- &frame_buf_size_high,
- &frame_buf_size_low);
- /* Address of raw Y data. */
- if (pmem_fixup_high_low(&frame_cmd->input_luma_addr_high,
- &frame_cmd->input_luma_addr_low,
- luma_buf_size_high,
- luma_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- /* Address of raw CbCr data */
- if (pmem_fixup_high_low(&frame_cmd->input_chroma_addr_high,
- &frame_cmd->input_chroma_addr_low,
- chroma_buf_size_high,
- chroma_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- /* Reference VOP */
- if (pmem_fixup_high_low(&frame_cmd->ref_vop_buf_ptr_high,
- &frame_cmd->ref_vop_buf_ptr_low,
- frame_buf_size_high,
- frame_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- /* Encoded Packet Address */
- if (pmem_fixup_high_low(&frame_cmd->enc_pkt_buf_ptr_high,
- &frame_cmd->enc_pkt_buf_ptr_low,
- frame_cmd->enc_pkt_buf_size_high,
- frame_cmd->enc_pkt_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- /* Unfiltered VOP Buffer Address */
- if (pmem_fixup_high_low(
- &frame_cmd->unfilt_recon_vop_buf_ptr_high,
- &frame_cmd->unfilt_recon_vop_buf_ptr_low,
- frame_buf_size_high,
- frame_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- /* Filtered VOP Buffer Address */
- if (pmem_fixup_high_low(&frame_cmd->filt_recon_vop_buf_ptr_high,
- &frame_cmd->filt_recon_vop_buf_ptr_low,
- frame_buf_size_high,
- frame_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- break;
- case VIDENC_CMD_DIS:
- if (cmd_size < sizeof(videnc_cmd_dis))
- return -1;
- dis_cmd = (videnc_cmd_dis *)cmd_data;
- luma_buf_size = x_dimension * y_dimension;
- ptr_to_high_low_short((void *)luma_buf_size,
- &luma_buf_size_high,
- &luma_buf_size_low);
- /* Prev VFE Luma Output Address */
- if (pmem_fixup_high_low(&dis_cmd->vfe_out_prev_luma_addr_high,
- &dis_cmd->vfe_out_prev_luma_addr_low,
- luma_buf_size_high,
- luma_buf_size_low,
- module,
- NULL, NULL))
- return -1;
- break;
- default:
- printk(KERN_INFO "adsp_video:unknown encoder video command %u\n",
- cmd_id);
- return 0;
- }
-
- return 0;
-}
-
-
-int adsp_videoenc_verify_cmd(struct msm_adsp_module *module,
- unsigned int queue_id, void *cmd_data,
- size_t cmd_size)
-{
- switch (queue_id) {
- case QDSP_mpuVEncCmdQueue:
- DLOG("\n");
- return verify_venc_cmd(module, cmd_data, cmd_size);
- default:
- printk(KERN_INFO "unknown video queue %u\n", queue_id);
- return 0;
- }
-}
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audio_aac.c
- *
- * aac audio decoder device
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- * Copyright (c) 2008-2009 QUALCOMM USA, INC.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <linux/delay.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include "audmgr.h"
-
-#include <mach/msm_adsp.h>
-#include <mach/msm_audio_aac.h>
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-#include <mach/qdsp5/qdsp5audplaycmdi.h>
-#include <mach/qdsp5/qdsp5audplaymsg.h>
-
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-#ifdef DEBUG
-#define dprintk(format, arg...) \
-printk(KERN_DEBUG format, ## arg)
-#else
-#define dprintk(format, arg...) do {} while (0)
-#endif
-
-#define BUFSZ 32768
-#define DMASZ (BUFSZ * 2)
-
-#define AUDPLAY_INVALID_READ_PTR_OFFSET 0xFFFF
-#define AUDDEC_DEC_AAC 5
-
-#define PCM_BUFSZ_MIN 9600 /* Hold one stereo AAC frame */
-#define PCM_BUF_MAX_COUNT 5 /* DSP only accepts 5 buffers at most
- but support 2 buffers currently */
-#define ROUTING_MODE_FTRT 1
-#define ROUTING_MODE_RT 2
-/* Decoder status received from AUDPPTASK */
-#define AUDPP_DEC_STATUS_SLEEP 0
-#define AUDPP_DEC_STATUS_INIT 1
-#define AUDPP_DEC_STATUS_CFG 2
-#define AUDPP_DEC_STATUS_PLAY 3
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used; /* Input usage actual DSP produced PCM size */
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[2];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
-
- atomic_t out_bytes;
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t write_wait;
-
- /* Host PCM section */
- struct buffer in[PCM_BUF_MAX_COUNT];
- struct mutex read_lock;
- wait_queue_head_t read_wait; /* Wait queue for read */
- char *read_data; /* pointer to reader buffer */
- dma_addr_t read_phys; /* physical address of reader buffer */
- uint8_t read_next; /* index to input buffers to be read next */
- uint8_t fill_next; /* index to buffer that DSP should be filling */
- uint8_t pcm_buf_count; /* number of pcm buffer allocated */
- /* ---- End of Host PCM section */
-
- struct msm_adsp_module *audplay;
-
- /* configuration to use on next enable */
- uint32_t out_sample_rate;
- uint32_t out_channel_mode;
- struct msm_audio_aac_config aac_config;
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- int rflush; /* Read flush */
- int wflush; /* Write flush */
- int opened;
- int enabled;
- int running;
- int stopped; /* set when stopped, cleared on flush */
- int pcm_feedback;
- int buf_refresh;
-
- int reserved; /* A byte is being reserved */
- char rsv_byte; /* Handle odd length user data */
-
- unsigned volume;
-
- uint16_t dec_id;
- uint32_t read_ptr_offset;
-};
-
-static int auddec_dsp_config(struct audio *audio, int enable);
-static void audpp_cmd_cfg_adec_params(struct audio *audio);
-static void audpp_cmd_cfg_routing_mode(struct audio *audio);
-static void audplay_send_data(struct audio *audio, unsigned needed);
-static void audplay_config_hostpcm(struct audio *audio);
-static void audplay_buffer_refresh(struct audio *audio);
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg);
-
-/* must be called with audio->lock held */
-static int audio_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- dprintk("audio_enable()\n");
-
- if (audio->enabled)
- return 0;
-
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_PLAYBACK;
- cfg.codec = RPC_AUD_DEF_CODEC_AAC;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audplay)) {
- pr_err("audio: msm_adsp_enable(audplay) failed\n");
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- if (audpp_enable(audio->dec_id, audio_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- msm_adsp_disable(audio->audplay);
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audio_disable(struct audio *audio)
-{
- dprintk("audio_disable()\n");
- if (audio->enabled) {
- audio->enabled = 0;
- auddec_dsp_config(audio, 0);
- wake_up(&audio->write_wait);
- wake_up(&audio->read_wait);
- msm_adsp_disable(audio->audplay);
- audpp_disable(audio->dec_id, audio);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audio_update_pcm_buf_entry(struct audio *audio, uint32_t *payload)
-{
- uint8_t index;
- unsigned long flags;
-
- if (audio->rflush)
- return;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- for (index = 0; index < payload[1]; index++) {
- if (audio->in[audio->fill_next].addr ==
- payload[2 + index * 2]) {
- dprintk("audio_update_pcm_buf_entry: in[%d] ready\n",
- audio->fill_next);
- audio->in[audio->fill_next].used =
- payload[3 + index * 2];
- if ((++audio->fill_next) == audio->pcm_buf_count)
- audio->fill_next = 0;
-
- } else {
- pr_err
- ("audio_update_pcm_buf_entry: expected=%x ret=%x\n"
- , audio->in[audio->fill_next].addr,
- payload[1 + index * 2]);
- break;
- }
- }
- if (audio->in[audio->fill_next].used == 0) {
- audplay_buffer_refresh(audio);
- } else {
- dprintk("audio_update_pcm_buf_entry: read cannot keep up\n");
- audio->buf_refresh = 1;
- }
- wake_up(&audio->read_wait);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-
-}
-
-static void audplay_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent) (void *ptr, size_t len))
-{
- struct audio *audio = data;
- uint32_t msg[28];
- getevent(msg, sizeof(msg));
-
- dprintk("audplay_dsp_event: msg_id=%x\n", id);
-
- switch (id) {
- case AUDPLAY_MSG_DEC_NEEDS_DATA:
- audplay_send_data(audio, 1);
- break;
-
- case AUDPLAY_MSG_BUFFER_UPDATE:
- audio_update_pcm_buf_entry(audio, msg);
- break;
-
- default:
- pr_err("unexpected message from decoder \n");
- }
-}
-
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned status = msg[1];
-
- switch (status) {
- case AUDPP_DEC_STATUS_SLEEP:
- dprintk("decoder status: sleep \n");
- break;
-
- case AUDPP_DEC_STATUS_INIT:
- dprintk("decoder status: init \n");
- audpp_cmd_cfg_routing_mode(audio);
- break;
-
- case AUDPP_DEC_STATUS_CFG:
- dprintk("decoder status: cfg \n");
- break;
- case AUDPP_DEC_STATUS_PLAY:
- dprintk("decoder status: play \n");
- if (audio->pcm_feedback) {
- audplay_config_hostpcm(audio);
- audplay_buffer_refresh(audio);
- }
- break;
- default:
- pr_err("unknown decoder status \n");
- }
- break;
- }
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- dprintk("audio_dsp_event: CFG_MSG ENABLE\n");
- auddec_dsp_config(audio, 1);
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(audio->dec_id, audio->volume,
- 0);
- audpp_avsync(audio->dec_id, 22050);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- dprintk("audio_dsp_event: CFG_MSG DISABLE\n");
- audpp_avsync(audio->dec_id, 0);
- audio->running = 0;
- } else {
- pr_err("audio_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- dprintk("audio_dsp_event: ROUTING_ACK mode=%d\n", msg[1]);
- audpp_cmd_cfg_adec_params(audio);
- break;
-
- case AUDPP_MSG_FLUSH_ACK:
- dprintk("%s: FLUSH_ACK\n", __func__);
- audio->wflush = 0;
- audio->rflush = 0;
- if (audio->pcm_feedback)
- audplay_buffer_refresh(audio);
- break;
-
- default:
- pr_err("audio_dsp_event: UNKNOWN (%d)\n", id);
- }
-
-}
-
-struct msm_adsp_ops audplay_adsp_ops_aac = {
- .event = audplay_dsp_event,
-};
-
-#define audplay_send_queue0(audio, cmd, len) \
- msm_adsp_write(audio->audplay, QDSP_uPAudPlay0BitStreamCtrlQueue, \
- cmd, len)
-
-static int auddec_dsp_config(struct audio *audio, int enable)
-{
- audpp_cmd_cfg_dec_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_CFG_DEC_TYPE;
- if (enable)
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_ENA_DEC_V | AUDDEC_DEC_AAC;
- else
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC | AUDPP_CMD_DIS_DEC_V;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_adec_params(struct audio *audio)
-{
- audpp_cmd_cfg_adec_params_aac cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.cmd_id = AUDPP_CMD_CFG_ADEC_PARAMS;
- cmd.common.length = AUDPP_CMD_CFG_ADEC_PARAMS_AAC_LEN;
- cmd.common.dec_id = audio->dec_id;
- cmd.common.input_sampling_frequency = audio->out_sample_rate;
- cmd.format = audio->aac_config.format;
- cmd.audio_object = audio->aac_config.audio_object;
- cmd.ep_config = audio->aac_config.ep_config;
- cmd.aac_section_data_resilience_flag =
- audio->aac_config.aac_section_data_resilience_flag;
- cmd.aac_scalefactor_data_resilience_flag =
- audio->aac_config.aac_scalefactor_data_resilience_flag;
- cmd.aac_spectral_data_resilience_flag =
- audio->aac_config.aac_spectral_data_resilience_flag;
- cmd.sbr_on_flag = audio->aac_config.sbr_on_flag;
- cmd.sbr_ps_on_flag = audio->aac_config.sbr_ps_on_flag;
- cmd.channel_configuration = audio->aac_config.channel_configuration;
-
- audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_routing_mode(struct audio *audio)
-{
- struct audpp_cmd_routing_mode cmd;
- dprintk("audpp_cmd_cfg_routing_mode()\n");
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_ROUTING_MODE;
- cmd.object_number = audio->dec_id;
- if (audio->pcm_feedback)
- cmd.routing_mode = ROUTING_MODE_FTRT;
- else
- cmd.routing_mode = ROUTING_MODE_RT;
-
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static int audplay_dsp_send_data_avail(struct audio *audio,
- unsigned idx, unsigned len)
-{
- audplay_cmd_bitstream_data_avail cmd;
-
- cmd.cmd_id = AUDPLAY_CMD_BITSTREAM_DATA_AVAIL;
- cmd.decoder_id = audio->dec_id;
- cmd.buf_ptr = audio->out[idx].addr;
- cmd.buf_size = len / 2;
- cmd.partition_number = 0;
- return audplay_send_queue0(audio, &cmd, sizeof(cmd));
-}
-
-static void audplay_buffer_refresh(struct audio *audio)
-{
- struct audplay_cmd_buffer_refresh refresh_cmd;
-
- refresh_cmd.cmd_id = AUDPLAY_CMD_BUFFER_REFRESH;
- refresh_cmd.num_buffers = 1;
- refresh_cmd.buf0_address = audio->in[audio->fill_next].addr;
- refresh_cmd.buf0_length = audio->in[audio->fill_next].size -
- (audio->in[audio->fill_next].size % 1024); /* AAC frame size */
- refresh_cmd.buf_read_count = 0;
- dprintk("audplay_buffer_fresh: buf0_addr=%x buf0_len=%d\n",
- refresh_cmd.buf0_address, refresh_cmd.buf0_length);
- (void)audplay_send_queue0(audio, &refresh_cmd, sizeof(refresh_cmd));
-}
-
-static void audplay_config_hostpcm(struct audio *audio)
-{
- struct audplay_cmd_hpcm_buf_cfg cfg_cmd;
-
- dprintk("audplay_config_hostpcm()\n");
- cfg_cmd.cmd_id = AUDPLAY_CMD_HPCM_BUF_CFG;
- cfg_cmd.max_buffers = audio->pcm_buf_count;
- cfg_cmd.byte_swap = 0;
- cfg_cmd.hostpcm_config = (0x8000) | (0x4000);
- cfg_cmd.feedback_frequency = 1;
- cfg_cmd.partition_number = 0;
- (void)audplay_send_queue0(audio, &cfg_cmd, sizeof(cfg_cmd));
-
-}
-
-static void audplay_send_data(struct audio *audio, unsigned needed)
-{
- struct buffer *frame;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (!audio->running)
- goto done;
-
- if (needed && !audio->wflush) {
- /* We were called from the callback because the DSP
- * requested more data. Note that the DSP does want
- * more data, and if a buffer was in-flight, mark it
- * as available (since the DSP must now be done with
- * it).
- */
- audio->out_needed = 1;
- frame = audio->out + audio->out_tail;
- if (frame->used == 0xffffffff) {
- dprintk("frame %d free\n", audio->out_tail);
- frame->used = 0;
- audio->out_tail ^= 1;
- wake_up(&audio->write_wait);
- }
- }
-
- if (audio->out_needed) {
- /* If the DSP currently wants data and we have a
- * buffer available, we will send it and reset
- * the needed flag. We'll mark the buffer as in-flight
- * so that it won't be recycled until the next buffer
- * is requested
- */
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- BUG_ON(frame->used == 0xffffffff);
-/* printk("frame %d busy\n", audio->out_tail); */
- audplay_dsp_send_data_avail(audio, audio->out_tail,
- frame->used);
- frame->used = 0xffffffff;
- audio->out_needed = 0;
- }
- }
- done:
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-}
-
-/* ------------------- device --------------------- */
-
-static void audio_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->reserved = 0;
- audio->out_needed = 0;
- atomic_set(&audio->out_bytes, 0);
-}
-
-static void audio_flush_pcm_buf(struct audio *audio)
-{
- uint8_t index;
-
- for (index = 0; index < PCM_BUF_MAX_COUNT; index++)
- audio->in[index].used = 0;
- audio->buf_refresh = 0;
- audio->read_next = 0;
- audio->fill_next = 0;
-}
-
-static int audaac_validate_usr_config(struct msm_audio_aac_config *config)
-{
- int ret_val = -1;
-
- if (config->format != AUDIO_AAC_FORMAT_ADTS &&
- config->format != AUDIO_AAC_FORMAT_RAW &&
- config->format != AUDIO_AAC_FORMAT_PSUEDO_RAW &&
- config->format != AUDIO_AAC_FORMAT_LOAS)
- goto done;
-
- if (config->audio_object != AUDIO_AAC_OBJECT_LC &&
- config->audio_object != AUDIO_AAC_OBJECT_LTP &&
- config->audio_object != AUDIO_AAC_OBJECT_ERLC)
- goto done;
-
- if (config->audio_object == AUDIO_AAC_OBJECT_ERLC) {
- if (config->ep_config > 3)
- goto done;
- if (config->aac_scalefactor_data_resilience_flag !=
- AUDIO_AAC_SCA_DATA_RES_OFF &&
- config->aac_scalefactor_data_resilience_flag !=
- AUDIO_AAC_SCA_DATA_RES_ON)
- goto done;
- if (config->aac_section_data_resilience_flag !=
- AUDIO_AAC_SEC_DATA_RES_OFF &&
- config->aac_section_data_resilience_flag !=
- AUDIO_AAC_SEC_DATA_RES_ON)
- goto done;
- if (config->aac_spectral_data_resilience_flag !=
- AUDIO_AAC_SPEC_DATA_RES_OFF &&
- config->aac_spectral_data_resilience_flag !=
- AUDIO_AAC_SPEC_DATA_RES_ON)
- goto done;
- } else {
- config->aac_section_data_resilience_flag =
- AUDIO_AAC_SEC_DATA_RES_OFF;
- config->aac_scalefactor_data_resilience_flag =
- AUDIO_AAC_SCA_DATA_RES_OFF;
- config->aac_spectral_data_resilience_flag =
- AUDIO_AAC_SPEC_DATA_RES_OFF;
- }
-
- if (config->sbr_on_flag != AUDIO_AAC_SBR_ON_FLAG_OFF &&
- config->sbr_on_flag != AUDIO_AAC_SBR_ON_FLAG_ON)
- goto done;
-
- if (config->sbr_ps_on_flag != AUDIO_AAC_SBR_PS_ON_FLAG_OFF &&
- config->sbr_ps_on_flag != AUDIO_AAC_SBR_PS_ON_FLAG_ON)
- goto done;
-
- if (config->dual_mono_mode > AUDIO_AAC_DUAL_MONO_PL_SR)
- goto done;
-
- if (config->channel_configuration > 2)
- goto done;
-
- ret_val = 0;
- done:
- return ret_val;
-}
-
-static void audio_ioport_reset(struct audio *audio)
-{
- /* Make sure read/write thread are free from
- * sleep and knowing that system is not able
- * to process io request at the moment
- */
- wake_up(&audio->write_wait);
- mutex_lock(&audio->write_lock);
- audio_flush(audio);
- mutex_unlock(&audio->write_lock);
- wake_up(&audio->read_wait);
- mutex_lock(&audio->read_lock);
- audio_flush_pcm_buf(audio);
- mutex_unlock(&audio->read_lock);
-}
-
-static long audio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0;
-
- dprintk("audio_ioctl() cmd = %d\n", cmd);
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = audpp_avsync_byte_count(audio->dec_id);
- stats.sample_count = audpp_avsync_sample_count(audio->dec_id);
- if (copy_to_user((void *)arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(audio->dec_id, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- return 0;
- }
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audio_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audio_disable(audio);
- audio->stopped = 1;
- audio_ioport_reset(audio);
- audio->stopped = 0;
- break;
- case AUDIO_FLUSH:
- dprintk("%s: AUDIO_FLUSH\n", __func__);
- audio->rflush = 1;
- audio->wflush = 1;
- audio_ioport_reset(audio);
- if (audio->running)
- audpp_flush(audio->dec_id);
- else {
- audio->rflush = 0;
- audio->wflush = 0;
- }
- break;
-
- case AUDIO_SET_CONFIG:{
- struct msm_audio_config config;
-
- if (copy_from_user
- (&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
-
- if (config.channel_count == 1) {
- config.channel_count =
- AUDPP_CMD_PCM_INTF_MONO_V;
- } else if (config.channel_count == 2) {
- config.channel_count =
- AUDPP_CMD_PCM_INTF_STEREO_V;
- } else {
- rc = -EINVAL;
- break;
- }
-
- audio->out_sample_rate = config.sample_rate;
- audio->out_channel_mode = config.channel_count;
- rc = 0;
- break;
- }
- case AUDIO_GET_CONFIG:{
- struct msm_audio_config config;
- config.buffer_size = BUFSZ;
- config.buffer_count = 2;
- config.sample_rate = audio->out_sample_rate;
- if (audio->out_channel_mode ==
- AUDPP_CMD_PCM_INTF_MONO_V) {
- config.channel_count = 1;
- } else {
- config.channel_count = 2;
- }
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
-
- break;
- }
- case AUDIO_GET_AAC_CONFIG:{
- if (copy_to_user((void *)arg, &audio->aac_config,
- sizeof(audio->aac_config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_AAC_CONFIG:{
- struct msm_audio_aac_config usr_config;
-
- if (copy_from_user
- (&usr_config, (void *)arg,
- sizeof(usr_config))) {
- rc = -EFAULT;
- break;
- }
-
- if (audaac_validate_usr_config(&usr_config) == 0) {
- audio->aac_config = usr_config;
- rc = 0;
- } else
- rc = -EINVAL;
-
- break;
- }
- case AUDIO_GET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- config.pcm_feedback = 0;
- config.buffer_count = PCM_BUF_MAX_COUNT;
- config.buffer_size = PCM_BUFSZ_MIN;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- if (copy_from_user
- (&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if ((config.buffer_count > PCM_BUF_MAX_COUNT) ||
- (config.buffer_count == 1))
- config.buffer_count = PCM_BUF_MAX_COUNT;
-
- if (config.buffer_size < PCM_BUFSZ_MIN)
- config.buffer_size = PCM_BUFSZ_MIN;
-
- /* Check if pcm feedback is required */
- if ((config.pcm_feedback) && (!audio->read_data)) {
- dprintk("ioctl: allocate PCM buffer %d\n",
- config.buffer_count *
- config.buffer_size);
- audio->read_data =
- dma_alloc_coherent(NULL,
- config.buffer_size *
- config.buffer_count,
- &audio->read_phys,
- GFP_KERNEL);
- if (!audio->read_data) {
- pr_err("audio_aac: buf alloc fail\n");
- rc = -1;
- } else {
- uint8_t index;
- uint32_t offset = 0;
- audio->pcm_feedback = 1;
- audio->buf_refresh = 0;
- audio->pcm_buf_count =
- config.buffer_count;
- audio->read_next = 0;
- audio->fill_next = 0;
-
- for (index = 0;
- index < config.buffer_count;
- index++) {
- audio->in[index].data =
- audio->read_data + offset;
- audio->in[index].addr =
- audio->read_phys + offset;
- audio->in[index].size =
- config.buffer_size;
- audio->in[index].used = 0;
- offset += config.buffer_size;
- }
- rc = 0;
- }
- } else {
- rc = 0;
- }
- break;
- }
- case AUDIO_PAUSE:
- dprintk("%s: AUDIO_PAUSE %ld\n", __func__, arg);
- rc = audpp_pause(audio->dec_id, (int) arg);
- break;
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audio_read(struct file *file, char __user *buf, size_t count,
- loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- int rc = 0;
-
- if (!audio->pcm_feedback)
- return 0; /* PCM feedback is not enabled. Nothing to read */
-
- mutex_lock(&audio->read_lock);
- dprintk("audio_read() %d \n", count);
- while (count > 0) {
- rc = wait_event_interruptible(audio->read_wait,
- (audio->in[audio->read_next].
- used > 0) || (audio->stopped)
- || (audio->rflush));
-
- if (rc < 0)
- break;
-
- if (audio->stopped || audio->rflush) {
- rc = -EBUSY;
- break;
- }
-
- if (count < audio->in[audio->read_next].used) {
- /* Read must happen in frame boundary. Since driver
- does not know frame size, read count must be greater
- or equal to size of PCM samples */
- dprintk("audio_read: no partial frame done reading\n");
- break;
- } else {
- dprintk("audio_read: read from in[%d]\n",
- audio->read_next);
- if (copy_to_user
- (buf, audio->in[audio->read_next].data,
- audio->in[audio->read_next].used)) {
- pr_err("audio_read: invalid addr %x \n",
- (unsigned int)buf);
- rc = -EFAULT;
- break;
- }
- count -= audio->in[audio->read_next].used;
- buf += audio->in[audio->read_next].used;
- audio->in[audio->read_next].used = 0;
- if ((++audio->read_next) == audio->pcm_buf_count)
- audio->read_next = 0;
- if (audio->in[audio->read_next].used == 0)
- break; /* No data ready at this moment
- * Exit while loop to prevent
- * output thread sleep too long
- */
- }
- }
-
- /* don't feed output buffer to HW decoder during flushing
- * buffer refresh command will be sent once flush completes
- * send buf refresh command here can confuse HW decoder
- */
- if (audio->buf_refresh && !audio->rflush) {
- audio->buf_refresh = 0;
- dprintk("audio_read: kick start pcm feedback again\n");
- audplay_buffer_refresh(audio);
- }
-
- mutex_unlock(&audio->read_lock);
-
- if (buf > start)
- rc = buf - start;
-
- dprintk("audio_read: read %d bytes\n", rc);
- return rc;
-}
-
-static ssize_t audio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- char *cpy_ptr;
- int rc = 0;
- unsigned dsize;
-
- mutex_lock(&audio->write_lock);
- while (count > 0) {
- frame = audio->out + audio->out_head;
- cpy_ptr = frame->data;
- dsize = 0;
- rc = wait_event_interruptible(audio->write_wait,
- (frame->used == 0)
- || (audio->stopped)
- || (audio->wflush));
- if (rc < 0)
- break;
- if (audio->stopped || audio->wflush) {
- rc = -EBUSY;
- break;
- }
-
- if (audio->reserved) {
- dprintk("%s: append reserved byte %x\n",
- __func__, audio->rsv_byte);
- *cpy_ptr = audio->rsv_byte;
- xfer = (count > (frame->size - 1)) ?
- frame->size - 1 : count;
- cpy_ptr++;
- dsize = 1;
- audio->reserved = 0;
- } else
- xfer = (count > frame->size) ? frame->size : count;
-
- if (copy_from_user(cpy_ptr, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
-
- dsize += xfer;
- if (dsize & 1) {
- audio->rsv_byte = ((char *) frame->data)[dsize - 1];
- dprintk("%s: odd length buf reserve last byte %x\n",
- __func__, audio->rsv_byte);
- audio->reserved = 1;
- dsize--;
- }
- count -= xfer;
- buf += xfer;
-
- if (dsize > 0) {
- audio->out_head ^= 1;
- frame->used = dsize;
- audplay_send_data(audio, 0);
- }
- }
- mutex_unlock(&audio->write_lock);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audio_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- dprintk("audio_release()\n");
-
- mutex_lock(&audio->lock);
- audio_disable(audio);
- audio_flush(audio);
- audio_flush_pcm_buf(audio);
- msm_adsp_put(audio->audplay);
- audio->audplay = NULL;
- audio->opened = 0;
- audio->reserved = 0;
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- audio->data = NULL;
- if (audio->read_data != NULL) {
- dma_free_coherent(NULL,
- audio->in[0].size * audio->pcm_buf_count,
- audio->read_data, audio->read_phys);
- audio->read_data = NULL;
- }
- audio->pcm_feedback = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio the_aac_audio;
-
-static int audio_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_aac_audio;
- int rc;
-
- mutex_lock(&audio->lock);
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- rc = -EBUSY;
- goto done;
- }
-
- if (!audio->data) {
- audio->data = dma_alloc_coherent(NULL, DMASZ,
- &audio->phys, GFP_KERNEL);
- if (!audio->data) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto done;
- }
- }
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto done;
-
- rc = msm_adsp_get("AUDPLAY0TASK", &audio->audplay,
- &audplay_adsp_ops_aac, audio);
- if (rc) {
- pr_err("audio: failed to get audplay0 dsp module\n");
- goto done;
- }
- audio->out_sample_rate = 44100;
- audio->out_channel_mode = AUDPP_CMD_PCM_INTF_STEREO_V;
- audio->aac_config.format = AUDIO_AAC_FORMAT_ADTS;
- audio->aac_config.audio_object = AUDIO_AAC_OBJECT_LC;
- audio->aac_config.ep_config = 0;
- audio->aac_config.aac_section_data_resilience_flag =
- AUDIO_AAC_SEC_DATA_RES_OFF;
- audio->aac_config.aac_scalefactor_data_resilience_flag =
- AUDIO_AAC_SCA_DATA_RES_OFF;
- audio->aac_config.aac_spectral_data_resilience_flag =
- AUDIO_AAC_SPEC_DATA_RES_OFF;
- audio->aac_config.sbr_on_flag = AUDIO_AAC_SBR_ON_FLAG_ON;
- audio->aac_config.sbr_ps_on_flag = AUDIO_AAC_SBR_PS_ON_FLAG_ON;
- audio->aac_config.dual_mono_mode = AUDIO_AAC_DUAL_MONO_PL_SR;
- audio->aac_config.channel_configuration = 2;
- audio->dec_id = 0;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = BUFSZ;
-
- audio->out[1].data = audio->data + BUFSZ;
- audio->out[1].addr = audio->phys + BUFSZ;
- audio->out[1].size = BUFSZ;
-
- audio->volume = 0x2000; /* Q13 1.0 */
-
- audio_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
-done:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static struct file_operations audio_aac_fops = {
- .owner = THIS_MODULE,
- .open = audio_open,
- .release = audio_release,
- .read = audio_read,
- .write = audio_write,
- .unlocked_ioctl = audio_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_aac_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_aac",
- .fops = &audio_aac_fops,
-};
-
-static int __init audio_init(void)
-{
- mutex_init(&the_aac_audio.lock);
- mutex_init(&the_aac_audio.write_lock);
- mutex_init(&the_aac_audio.read_lock);
- spin_lock_init(&the_aac_audio.dsp_lock);
- init_waitqueue_head(&the_aac_audio.write_wait);
- init_waitqueue_head(&the_aac_audio.read_wait);
- the_aac_audio.read_data = NULL;
- return misc_register(&audio_aac_misc);
-}
-
-device_initcall(audio_init);
+++ /dev/null
-/* linux/arch/arm/mach-msm/qdsp5/audio_amrnb.c
- *
- * amrnb audio decoder device
- *
- * Copyright (c) 2008 QUALCOMM USA, INC.
- *
- * Based on the mp3 native driver in arch/arm/mach-msm/qdsp5/audio_mp3.c
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * All source code in this file is licensed under the following license except
- * where indicated.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * See the GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can find it at http://www.fsf.org
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <linux/delay.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-#include <linux/msm_audio.h>
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-#include <mach/qdsp5/qdsp5audplaycmdi.h>
-#include <mach/qdsp5/qdsp5audplaymsg.h>
-
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-#define DEBUG
-#ifdef DEBUG
-#define dprintk(format, arg...) \
-printk(KERN_DEBUG format, ## arg)
-#else
-#define dprintk(format, arg...) do {} while (0)
-#endif
-
-#define BUFSZ 1024 /* Hold minimum 700ms voice data */
-#define DMASZ (BUFSZ * 2)
-
-#define AUDPLAY_INVALID_READ_PTR_OFFSET 0xFFFF
-#define AUDDEC_DEC_AMRNB 10
-
-#define PCM_BUFSZ_MIN 1600 /* 100ms worth of data */
-#define AMRNB_DECODED_FRSZ 320 /* AMR-NB 20ms 8KHz mono PCM size */
-#define PCM_BUF_MAX_COUNT 5 /* DSP only accepts 5 buffers at most
- but support 2 buffers currently */
-#define ROUTING_MODE_FTRT 1
-#define ROUTING_MODE_RT 2
-/* Decoder status received from AUDPPTASK */
-#define AUDPP_DEC_STATUS_SLEEP 0
-#define AUDPP_DEC_STATUS_INIT 1
-#define AUDPP_DEC_STATUS_CFG 2
-#define AUDPP_DEC_STATUS_PLAY 3
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used; /* Input usage actual DSP produced PCM size */
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[2];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
-
- atomic_t out_bytes;
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t write_wait;
-
- /* Host PCM section */
- struct buffer in[PCM_BUF_MAX_COUNT];
- struct mutex read_lock;
- wait_queue_head_t read_wait; /* Wait queue for read */
- char *read_data; /* pointer to reader buffer */
- dma_addr_t read_phys; /* physical address of reader buffer */
- uint8_t read_next; /* index to input buffers to be read next */
- uint8_t fill_next; /* index to buffer that DSP should be filling */
- uint8_t pcm_buf_count; /* number of pcm buffer allocated */
- /* ---- End of Host PCM section */
-
- struct msm_adsp_module *audplay;
-
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- uint8_t opened:1;
- uint8_t enabled:1;
- uint8_t running:1;
- uint8_t stopped:1; /* set when stopped, cleared on flush */
- uint8_t pcm_feedback:1;
- uint8_t buf_refresh:1;
-
- unsigned volume;
-
- uint16_t dec_id;
- uint32_t read_ptr_offset;
-};
-
-struct audpp_cmd_cfg_adec_params_amrnb {
- audpp_cmd_cfg_adec_params_common common;
- unsigned short stereo_cfg;
-} __attribute__((packed)) ;
-
-static int auddec_dsp_config(struct audio *audio, int enable);
-static void audpp_cmd_cfg_adec_params(struct audio *audio);
-static void audpp_cmd_cfg_routing_mode(struct audio *audio);
-static void audamrnb_send_data(struct audio *audio, unsigned needed);
-static void audamrnb_config_hostpcm(struct audio *audio);
-static void audamrnb_buffer_refresh(struct audio *audio);
-static void audamrnb_dsp_event(void *private, unsigned id, uint16_t *msg);
-
-/* must be called with audio->lock held */
-static int audamrnb_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- dprintk("audamrnb_enable()\n");
-
- if (audio->enabled)
- return 0;
-
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_PLAYBACK;
- cfg.codec = RPC_AUD_DEF_CODEC_AMR_NB;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audplay)) {
- pr_err("audio: msm_adsp_enable(audplay) failed\n");
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- if (audpp_enable(audio->dec_id, audamrnb_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- msm_adsp_disable(audio->audplay);
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audamrnb_disable(struct audio *audio)
-{
- dprintk("audamrnb_disable()\n");
- if (audio->enabled) {
- audio->enabled = 0;
- auddec_dsp_config(audio, 0);
- wake_up(&audio->write_wait);
- wake_up(&audio->read_wait);
- msm_adsp_disable(audio->audplay);
- audpp_disable(audio->dec_id, audio);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audamrnb_update_pcm_buf_entry(struct audio *audio,
- uint32_t *payload)
-{
- uint8_t index;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- for (index = 0; index < payload[1]; index++) {
- if (audio->in[audio->fill_next].addr ==
- payload[2 + index * 2]) {
- dprintk("audamrnb_update_pcm_buf_entry: in[%d] ready\n",
- audio->fill_next);
- audio->in[audio->fill_next].used =
- payload[3 + index * 2];
- if ((++audio->fill_next) == audio->pcm_buf_count)
- audio->fill_next = 0;
-
- } else {
- pr_err
- ("audamrnb_update_pcm_buf_entry: expected=%x ret=%x\n"
- , audio->in[audio->fill_next].addr,
- payload[1 + index * 2]);
- break;
- }
- }
- if (audio->in[audio->fill_next].used == 0) {
- audamrnb_buffer_refresh(audio);
- } else {
- dprintk("audamrnb_update_pcm_buf_entry: read cannot keep up\n");
- audio->buf_refresh = 1;
- }
-
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- wake_up(&audio->read_wait);
-}
-
-static void audplay_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent) (void *ptr, size_t len))
-{
- struct audio *audio = data;
- uint32_t msg[28];
- getevent(msg, sizeof(msg));
-
- dprintk("audplay_dsp_event: msg_id=%x\n", id);
-
- switch (id) {
- case AUDPLAY_MSG_DEC_NEEDS_DATA:
- audamrnb_send_data(audio, 1);
- break;
-
- case AUDPLAY_MSG_BUFFER_UPDATE:
- audamrnb_update_pcm_buf_entry(audio, msg);
- break;
-
- default:
- pr_err("unexpected message from decoder \n");
- }
-}
-
-static void audamrnb_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned status = msg[1];
-
- switch (status) {
- case AUDPP_DEC_STATUS_SLEEP:
- dprintk("decoder status: sleep \n");
- break;
-
- case AUDPP_DEC_STATUS_INIT:
- dprintk("decoder status: init \n");
- audpp_cmd_cfg_routing_mode(audio);
- break;
-
- case AUDPP_DEC_STATUS_CFG:
- dprintk("decoder status: cfg \n");
- break;
- case AUDPP_DEC_STATUS_PLAY:
- dprintk("decoder status: play \n");
- if (audio->pcm_feedback) {
- audamrnb_config_hostpcm(audio);
- audamrnb_buffer_refresh(audio);
- }
- break;
- default:
- pr_err("unknown decoder status \n");
- break;
- }
- break;
- }
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- dprintk("audamrnb_dsp_event: CFG_MSG ENABLE\n");
- auddec_dsp_config(audio, 1);
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(audio->dec_id, audio->volume,
- 0);
- audpp_avsync(audio->dec_id, 22050);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- dprintk("audamrnb_dsp_event: CFG_MSG DISABLE\n");
- audpp_avsync(audio->dec_id, 0);
- audio->running = 0;
- } else {
- pr_err("audamrnb_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- dprintk("audamrnb_dsp_event: ROUTING_ACK mode=%d\n", msg[1]);
- audpp_cmd_cfg_adec_params(audio);
- break;
-
- default:
- pr_err("audamrnb_dsp_event: UNKNOWN (%d)\n", id);
- }
-
-}
-
-struct msm_adsp_ops audplay_adsp_ops_amrnb = {
- .event = audplay_dsp_event,
-};
-
-#define audplay_send_queue0(audio, cmd, len) \
- msm_adsp_write(audio->audplay, QDSP_uPAudPlay0BitStreamCtrlQueue, \
- cmd, len)
-
-static int auddec_dsp_config(struct audio *audio, int enable)
-{
- audpp_cmd_cfg_dec_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_CFG_DEC_TYPE;
- if (enable)
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_ENA_DEC_V | AUDDEC_DEC_AMRNB;
- else
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC | AUDPP_CMD_DIS_DEC_V;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_adec_params(struct audio *audio)
-{
- struct audpp_cmd_cfg_adec_params_amrnb cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.cmd_id = AUDPP_CMD_CFG_ADEC_PARAMS;
- cmd.common.length = AUDPP_CMD_CFG_ADEC_PARAMS_V13K_LEN;
- cmd.common.dec_id = audio->dec_id;
- cmd.common.input_sampling_frequency = 8000;
- cmd.stereo_cfg = AUDPP_CMD_PCM_INTF_MONO_V;
-
- audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_routing_mode(struct audio *audio)
-{
- struct audpp_cmd_routing_mode cmd;
- dprintk("audpp_cmd_cfg_routing_mode()\n");
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_ROUTING_MODE;
- cmd.object_number = audio->dec_id;
- if (audio->pcm_feedback)
- cmd.routing_mode = ROUTING_MODE_FTRT;
- else
- cmd.routing_mode = ROUTING_MODE_RT;
-
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static int audplay_dsp_send_data_avail(struct audio *audio,
- unsigned idx, unsigned len)
-{
- audplay_cmd_bitstream_data_avail cmd;
-
- cmd.cmd_id = AUDPLAY_CMD_BITSTREAM_DATA_AVAIL;
- cmd.decoder_id = audio->dec_id;
- cmd.buf_ptr = audio->out[idx].addr;
- cmd.buf_size = len / 2;
- cmd.partition_number = 0;
- return audplay_send_queue0(audio, &cmd, sizeof(cmd));
-}
-
-static void audamrnb_buffer_refresh(struct audio *audio)
-{
- struct audplay_cmd_buffer_refresh refresh_cmd;
-
- refresh_cmd.cmd_id = AUDPLAY_CMD_BUFFER_REFRESH;
- refresh_cmd.num_buffers = 1;
- refresh_cmd.buf0_address = audio->in[audio->fill_next].addr;
- refresh_cmd.buf0_length = audio->in[audio->fill_next].size -
- (audio->in[audio->fill_next].size % AMRNB_DECODED_FRSZ);
- refresh_cmd.buf_read_count = 0;
- dprintk("audplay_buffer_fresh: buf0_addr=%x buf0_len=%d\n",
- refresh_cmd.buf0_address, refresh_cmd.buf0_length);
- (void)audplay_send_queue0(audio, &refresh_cmd, sizeof(refresh_cmd));
-}
-
-static void audamrnb_config_hostpcm(struct audio *audio)
-{
- struct audplay_cmd_hpcm_buf_cfg cfg_cmd;
-
- dprintk("audamrnb_config_hostpcm()\n");
- cfg_cmd.cmd_id = AUDPLAY_CMD_HPCM_BUF_CFG;
- cfg_cmd.max_buffers = audio->pcm_buf_count;
- cfg_cmd.byte_swap = 0;
- cfg_cmd.hostpcm_config = (0x8000) | (0x4000);
- cfg_cmd.feedback_frequency = 1;
- cfg_cmd.partition_number = 0;
- (void)audplay_send_queue0(audio, &cfg_cmd, sizeof(cfg_cmd));
-
-}
-
-static void audamrnb_send_data(struct audio *audio, unsigned needed)
-{
- struct buffer *frame;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (!audio->running)
- goto done;
-
- if (needed) {
- /* We were called from the callback because the DSP
- * requested more data. Note that the DSP does want
- * more data, and if a buffer was in-flight, mark it
- * as available (since the DSP must now be done with
- * it).
- */
- audio->out_needed = 1;
- frame = audio->out + audio->out_tail;
- if (frame->used == 0xffffffff) {
- frame->used = 0;
- audio->out_tail ^= 1;
- wake_up(&audio->write_wait);
- }
- }
-
- if (audio->out_needed) {
- /* If the DSP currently wants data and we have a
- * buffer available, we will send it and reset
- * the needed flag. We'll mark the buffer as in-flight
- * so that it won't be recycled until the next buffer
- * is requested
- */
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- BUG_ON(frame->used == 0xffffffff);
-/* printk("frame %d busy\n", audio->out_tail); */
- audplay_dsp_send_data_avail(audio, audio->out_tail,
- frame->used);
- frame->used = 0xffffffff;
- audio->out_needed = 0;
- }
- }
- done:
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-}
-
-/* ------------------- device --------------------- */
-
-static void audamrnb_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->stopped = 0;
- atomic_set(&audio->out_bytes, 0);
-}
-
-static void audamrnb_flush_pcm_buf(struct audio *audio)
-{
- uint8_t index;
-
- for (index = 0; index < PCM_BUF_MAX_COUNT; index++)
- audio->in[index].used = 0;
-
- audio->read_next = 0;
- audio->fill_next = 0;
-}
-
-static long audamrnb_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0;
-
- dprintk("audamrnb_ioctl() cmd = %d\n", cmd);
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = audpp_avsync_byte_count(audio->dec_id);
- stats.sample_count = audpp_avsync_sample_count(audio->dec_id);
- if (copy_to_user((void *)arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(audio->dec_id, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- return 0;
- }
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audamrnb_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audamrnb_disable(audio);
- audio->stopped = 1;
- break;
- case AUDIO_FLUSH:
- if (audio->stopped) {
- /* Make sure we're stopped and we wake any threads
- * that might be blocked holding the write_lock.
- * While audio->stopped write threads will always
- * exit immediately.
- */
- wake_up(&audio->write_wait);
- mutex_lock(&audio->write_lock);
- audamrnb_flush(audio);
- mutex_unlock(&audio->write_lock);
- wake_up(&audio->read_wait);
- mutex_lock(&audio->read_lock);
- audamrnb_flush_pcm_buf(audio);
- mutex_unlock(&audio->read_lock);
- break;
- }
-
- case AUDIO_SET_CONFIG:{
- dprintk("AUDIO_SET_CONFIG not applicable \n");
- break;
- }
- case AUDIO_GET_CONFIG:{
- struct msm_audio_config config;
- config.buffer_size = BUFSZ;
- config.buffer_count = 2;
- config.sample_rate = 8000;
- config.channel_count = 1;
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
-
- break;
- }
- case AUDIO_GET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- config.pcm_feedback = 0;
- config.buffer_count = PCM_BUF_MAX_COUNT;
- config.buffer_size = PCM_BUFSZ_MIN;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- if (copy_from_user
- (&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if ((config.buffer_count > PCM_BUF_MAX_COUNT) ||
- (config.buffer_count == 1))
- config.buffer_count = PCM_BUF_MAX_COUNT;
-
- if (config.buffer_size < PCM_BUFSZ_MIN)
- config.buffer_size = PCM_BUFSZ_MIN;
-
- /* Check if pcm feedback is required */
- if ((config.pcm_feedback) && (!audio->read_data)) {
- dprintk("audamrnb_ioctl: allocate PCM buf %d\n",
- config.buffer_count *
- config.buffer_size);
- audio->read_data =
- dma_alloc_coherent(NULL,
- config.buffer_size *
- config.buffer_count,
- &audio->read_phys,
- GFP_KERNEL);
- if (!audio->read_data) {
- pr_err("audamrnb_ioctl: no mem for pcm buf\n");
- rc = -1;
- } else {
- uint8_t index;
- uint32_t offset = 0;
- audio->pcm_feedback = 1;
- audio->buf_refresh = 0;
- audio->pcm_buf_count =
- config.buffer_count;
- audio->read_next = 0;
- audio->fill_next = 0;
-
- for (index = 0;
- index < config.buffer_count; index++) {
- audio->in[index].data =
- audio->read_data + offset;
- audio->in[index].addr =
- audio->read_phys + offset;
- audio->in[index].size =
- config.buffer_size;
- audio->in[index].used = 0;
- offset += config.buffer_size;
- }
- rc = 0;
- }
- } else {
- rc = 0;
- }
- break;
- }
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audamrnb_read(struct file *file, char __user *buf, size_t count,
- loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- int rc = 0;
-
- if (!audio->pcm_feedback)
- return 0; /* PCM feedback is not enabled. Nothing to read */
-
- mutex_lock(&audio->read_lock);
- dprintk("audamrnb_read() %d \n", count);
- while (count > 0) {
- rc = wait_event_interruptible(audio->read_wait,
- (audio->in[audio->read_next].
- used > 0) || (audio->stopped));
-
- if (rc < 0)
- break;
-
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
-
- if (count < audio->in[audio->read_next].used) {
- /* Read must happen in frame boundary. Since driver does
- * not know frame size, read count must be greater or
- * equal to size of PCM samples
- */
- dprintk("audamrnb_read:read stop - partial frame\n");
- break;
- } else {
- dprintk("audamrnb_read: read from in[%d]\n",
- audio->read_next);
- if (copy_to_user
- (buf, audio->in[audio->read_next].data,
- audio->in[audio->read_next].used)) {
- pr_err("audamrnb_read: invalid addr %x \n",
- (unsigned int)buf);
- rc = -EFAULT;
- break;
- }
- count -= audio->in[audio->read_next].used;
- buf += audio->in[audio->read_next].used;
- audio->in[audio->read_next].used = 0;
- if ((++audio->read_next) == audio->pcm_buf_count)
- audio->read_next = 0;
- }
- }
-
- if (audio->buf_refresh) {
- audio->buf_refresh = 0;
- dprintk("audamrnb_read: kick start pcm feedback again\n");
- audamrnb_buffer_refresh(audio);
- }
-
- mutex_unlock(&audio->read_lock);
-
- if (buf > start)
- rc = buf - start;
-
- dprintk("audamrnb_read: read %d bytes\n", rc);
- return rc;
-}
-
-static ssize_t audamrnb_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- int rc = 0;
-
- if (count & 1)
- return -EINVAL;
- dprintk("audamrnb_write() \n");
- mutex_lock(&audio->write_lock);
- while (count > 0) {
- frame = audio->out + audio->out_head;
- rc = wait_event_interruptible(audio->write_wait,
- (frame->used == 0)
- || (audio->stopped));
- dprintk("audamrnb_write() buffer available\n");
- if (rc < 0)
- break;
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
- xfer = (count > frame->size) ? frame->size : count;
- if (copy_from_user(frame->data, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
-
- frame->used = xfer;
- audio->out_head ^= 1;
- count -= xfer;
- buf += xfer;
-
- audamrnb_send_data(audio, 0);
-
- }
- mutex_unlock(&audio->write_lock);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audamrnb_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- dprintk("audamrnb_release()\n");
-
- mutex_lock(&audio->lock);
- audamrnb_disable(audio);
- audamrnb_flush(audio);
- audamrnb_flush_pcm_buf(audio);
- msm_adsp_put(audio->audplay);
- audio->audplay = NULL;
- audio->opened = 0;
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- audio->data = NULL;
- if (audio->read_data != NULL) {
- dma_free_coherent(NULL,
- audio->in[0].size * audio->pcm_buf_count,
- audio->read_data, audio->read_phys);
- audio->read_data = NULL;
- }
- audio->pcm_feedback = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio the_amrnb_audio;
-
-static int audamrnb_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_amrnb_audio;
- int rc;
-
- mutex_lock(&audio->lock);
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- rc = -EBUSY;
- goto done;
- }
-
- if (!audio->data) {
- audio->data = dma_alloc_coherent(NULL, DMASZ,
- &audio->phys, GFP_KERNEL);
- if (!audio->data) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto done;
- }
- }
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto done;
-
- rc = msm_adsp_get("AUDPLAY0TASK", &audio->audplay,
- &audplay_adsp_ops_amrnb, audio);
- if (rc) {
- pr_err("audio: failed to get audplay0 dsp module\n");
- audmgr_disable(&audio->audmgr);
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- audio->data = NULL;
- goto done;
- }
-
- audio->dec_id = 0;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = BUFSZ;
-
- audio->out[1].data = audio->data + BUFSZ;
- audio->out[1].addr = audio->phys + BUFSZ;
- audio->out[1].size = BUFSZ;
-
- audio->volume = 0x2000; /* Q13 1.0 */
-
- audamrnb_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
-done:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static struct file_operations audio_amrnb_fops = {
- .owner = THIS_MODULE,
- .open = audamrnb_open,
- .release = audamrnb_release,
- .read = audamrnb_read,
- .write = audamrnb_write,
- .unlocked_ioctl = audamrnb_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_amrnb_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_amrnb",
- .fops = &audio_amrnb_fops,
-};
-
-static int __init audamrnb_init(void)
-{
- mutex_init(&the_amrnb_audio.lock);
- mutex_init(&the_amrnb_audio.write_lock);
- mutex_init(&the_amrnb_audio.read_lock);
- spin_lock_init(&the_amrnb_audio.dsp_lock);
- init_waitqueue_head(&the_amrnb_audio.write_wait);
- init_waitqueue_head(&the_amrnb_audio.read_wait);
- the_amrnb_audio.read_data = NULL;
- return misc_register(&audio_amrnb_misc);
-}
-
-static void __exit audamrnb_exit(void)
-{
- misc_deregister(&audio_amrnb_misc);
-}
-
-module_init(audamrnb_init);
-module_exit(audamrnb_exit);
-
-MODULE_DESCRIPTION("MSM AMR-NB driver");
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("QUALCOMM Inc");
+++ /dev/null
-/* arch/arm/mach-msm/audio_evrc.c
- *
- * Copyright (c) 2008 QUALCOMM USA, INC.
- *
- * This code also borrows from audio_aac.c, which is
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * See the GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can find it at http://www.fsf.org.
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <linux/gfp.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-#include <linux/msm_audio.h>
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-#include <mach/qdsp5/qdsp5audplaycmdi.h>
-#include <mach/qdsp5/qdsp5audplaymsg.h>
-
-#include "adsp.h"
-
-#ifdef DEBUG
-#define dprintk(format, arg...) \
- printk(KERN_DEBUG format, ## arg)
-#else
-#define dprintk(format, arg...) do {} while (0)
-#endif
-
-/* Hold 30 packets of 24 bytes each*/
-#define BUFSZ 720
-#define DMASZ (BUFSZ * 2)
-
-#define AUDDEC_DEC_EVRC 12
-
-#define PCM_BUFSZ_MIN 1600 /* 100ms worth of data */
-#define PCM_BUF_MAX_COUNT 5
-/* DSP only accepts 5 buffers at most
- * but support 2 buffers currently
- */
-#define EVRC_DECODED_FRSZ 320 /* EVRC 20ms 8KHz mono PCM size */
-
-#define ROUTING_MODE_FTRT 1
-#define ROUTING_MODE_RT 2
-/* Decoder status received from AUDPPTASK */
-#define AUDPP_DEC_STATUS_SLEEP 0
-#define AUDPP_DEC_STATUS_INIT 1
-#define AUDPP_DEC_STATUS_CFG 2
-#define AUDPP_DEC_STATUS_PLAY 3
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used; /* Input usage actual DSP produced PCM size */
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[2];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
-
- atomic_t out_bytes;
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t write_wait;
-
- /* Host PCM section */
- struct buffer in[PCM_BUF_MAX_COUNT];
- struct mutex read_lock;
- wait_queue_head_t read_wait; /* Wait queue for read */
- char *read_data; /* pointer to reader buffer */
- dma_addr_t read_phys; /* physical address of reader buffer */
- uint8_t read_next; /* index to input buffers to be read next */
- uint8_t fill_next; /* index to buffer that DSP should be filling */
- uint8_t pcm_buf_count; /* number of pcm buffer allocated */
- /* ---- End of Host PCM section */
-
- struct msm_adsp_module *audplay;
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- uint8_t opened:1;
- uint8_t enabled:1;
- uint8_t running:1;
- uint8_t stopped:1; /* set when stopped, cleared on flush */
- uint8_t pcm_feedback:1;
- uint8_t buf_refresh:1;
-
- unsigned volume;
- uint16_t dec_id;
- uint32_t read_ptr_offset;
-};
-static struct audio the_evrc_audio;
-
-static int auddec_dsp_config(struct audio *audio, int enable);
-static void audpp_cmd_cfg_adec_params(struct audio *audio);
-static void audpp_cmd_cfg_routing_mode(struct audio *audio);
-static void audevrc_send_data(struct audio *audio, unsigned needed);
-static void audevrc_dsp_event(void *private, unsigned id, uint16_t *msg);
-static void audevrc_config_hostpcm(struct audio *audio);
-static void audevrc_buffer_refresh(struct audio *audio);
-
-/* must be called with audio->lock held */
-static int audevrc_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- if (audio->enabled)
- return 0;
-
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_PLAYBACK;
- cfg.codec = RPC_AUD_DEF_CODEC_EVRC;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audplay)) {
- pr_err("audio: msm_adsp_enable(audplay) failed\n");
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- if (audpp_enable(audio->dec_id, audevrc_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- msm_adsp_disable(audio->audplay);
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audevrc_disable(struct audio *audio)
-{
- if (audio->enabled) {
- audio->enabled = 0;
- auddec_dsp_config(audio, 0);
- wake_up(&audio->write_wait);
- wake_up(&audio->read_wait);
- msm_adsp_disable(audio->audplay);
- audpp_disable(audio->dec_id, audio);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-
-static void audevrc_update_pcm_buf_entry(struct audio *audio,
- uint32_t *payload)
-{
- uint8_t index;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- for (index = 0; index < payload[1]; index++) {
- if (audio->in[audio->fill_next].addr
- == payload[2 + index * 2]) {
- dprintk("audevrc_update_pcm_buf_entry: in[%d] ready\n",
- audio->fill_next);
- audio->in[audio->fill_next].used =
- payload[3 + index * 2];
- if ((++audio->fill_next) == audio->pcm_buf_count)
- audio->fill_next = 0;
-
- } else {
- pr_err
- ("audevrc_update_pcm_buf_entry: expected=%x ret=%x\n",
- audio->in[audio->fill_next].addr,
- payload[1 + index * 2]);
- break;
- }
- }
- if (audio->in[audio->fill_next].used == 0) {
- audevrc_buffer_refresh(audio);
- } else {
- dprintk("audevrc_update_pcm_buf_entry: read cannot keep up\n");
- audio->buf_refresh = 1;
- }
-
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- wake_up(&audio->read_wait);
-}
-
-static void audplay_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent) (void *ptr, size_t len))
-{
- struct audio *audio = data;
- uint32_t msg[28];
- getevent(msg, sizeof(msg));
-
- dprintk("audplay_dsp_event: msg_id=%x\n", id);
- switch (id) {
- case AUDPLAY_MSG_DEC_NEEDS_DATA:
- audevrc_send_data(audio, 1);
- break;
- case AUDPLAY_MSG_BUFFER_UPDATE:
- dprintk("audevrc_update_pcm_buf_entry:======> \n");
- audevrc_update_pcm_buf_entry(audio, msg);
- break;
- default:
- pr_err("unexpected message from decoder \n");
- }
-}
-
-static void audevrc_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned status = msg[1];
-
- switch (status) {
- case AUDPP_DEC_STATUS_SLEEP:
- dprintk("decoder status: sleep \n");
- break;
-
- case AUDPP_DEC_STATUS_INIT:
- dprintk("decoder status: init \n");
- audpp_cmd_cfg_routing_mode(audio);
- break;
-
- case AUDPP_DEC_STATUS_CFG:
- dprintk("decoder status: cfg \n");
- break;
- case AUDPP_DEC_STATUS_PLAY:
- dprintk("decoder status: play \n");
- if (audio->pcm_feedback) {
- audevrc_config_hostpcm(audio);
- audevrc_buffer_refresh(audio);
- }
- break;
- default:
- pr_err("unknown decoder status \n");
- }
- break;
- }
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- dprintk("audevrc_dsp_event: CFG_MSG ENABLE\n");
- auddec_dsp_config(audio, 1);
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(audio->dec_id, audio->volume,
- 0);
- audpp_avsync(audio->dec_id, 22050);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- dprintk("audevrc_dsp_event: CFG_MSG DISABLE\n");
- audpp_avsync(audio->dec_id, 0);
- audio->running = 0;
- } else {
- pr_err("audevrc_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- dprintk("audevrc_dsp_event: ROUTING_ACK\n");
- audpp_cmd_cfg_adec_params(audio);
- break;
-
- default:
- pr_err("audevrc_dsp_event: UNKNOWN (%d)\n", id);
- }
-
-}
-
-struct msm_adsp_ops audplay_adsp_ops_evrc = {
- .event = audplay_dsp_event,
-};
-
-#define audplay_send_queue0(audio, cmd, len) \
- msm_adsp_write(audio->audplay, QDSP_uPAudPlay0BitStreamCtrlQueue, \
- cmd, len)
-
-static int auddec_dsp_config(struct audio *audio, int enable)
-{
- audpp_cmd_cfg_dec_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_CFG_DEC_TYPE;
- if (enable)
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_ENA_DEC_V | AUDDEC_DEC_EVRC;
- else
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC | AUDPP_CMD_DIS_DEC_V;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_adec_params(struct audio *audio)
-{
- struct audpp_cmd_cfg_adec_params_evrc cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.cmd_id = AUDPP_CMD_CFG_ADEC_PARAMS;
- cmd.common.length = sizeof(cmd);
- cmd.common.dec_id = audio->dec_id;
- cmd.common.input_sampling_frequency = 8000;
- cmd.stereo_cfg = AUDPP_CMD_PCM_INTF_MONO_V;
-
- audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_routing_mode(struct audio *audio)
-{
- struct audpp_cmd_routing_mode cmd;
- dprintk("audpp_cmd_cfg_routing_mode()\n");
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_ROUTING_MODE;
- cmd.object_number = audio->dec_id;
- if (audio->pcm_feedback)
- cmd.routing_mode = ROUTING_MODE_FTRT;
- else
- cmd.routing_mode = ROUTING_MODE_RT;
-
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static int audplay_dsp_send_data_avail(struct audio *audio,
- unsigned idx, unsigned len)
-{
- audplay_cmd_bitstream_data_avail cmd;
-
- cmd.cmd_id = AUDPLAY_CMD_BITSTREAM_DATA_AVAIL;
- cmd.decoder_id = audio->dec_id;
- cmd.buf_ptr = audio->out[idx].addr;
- cmd.buf_size = len / 2;
- cmd.partition_number = 0;
- return audplay_send_queue0(audio, &cmd, sizeof(cmd));
-}
-
-static void audevrc_buffer_refresh(struct audio *audio)
-{
- struct audplay_cmd_buffer_refresh refresh_cmd;
-
- refresh_cmd.cmd_id = AUDPLAY_CMD_BUFFER_REFRESH;
- refresh_cmd.num_buffers = 1;
- refresh_cmd.buf0_address = audio->in[audio->fill_next].addr;
- refresh_cmd.buf0_length = audio->in[audio->fill_next].size;
-
- refresh_cmd.buf_read_count = 0;
- dprintk("audplay_buffer_fresh: buf0_addr=%x buf0_len=%d\n",
- refresh_cmd.buf0_address, refresh_cmd.buf0_length);
- audplay_send_queue0(audio, &refresh_cmd, sizeof(refresh_cmd));
-}
-
-static void audevrc_config_hostpcm(struct audio *audio)
-{
- struct audplay_cmd_hpcm_buf_cfg cfg_cmd;
-
- dprintk("audevrc_config_hostpcm()\n");
- cfg_cmd.cmd_id = AUDPLAY_CMD_HPCM_BUF_CFG;
- cfg_cmd.max_buffers = 1;
- cfg_cmd.byte_swap = 0;
- cfg_cmd.hostpcm_config = (0x8000) | (0x4000);
- cfg_cmd.feedback_frequency = 1;
- cfg_cmd.partition_number = 0;
- audplay_send_queue0(audio, &cfg_cmd, sizeof(cfg_cmd));
-
-}
-
-static void audevrc_send_data(struct audio *audio, unsigned needed)
-{
- struct buffer *frame;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (!audio->running)
- goto done;
-
- if (needed) {
- /* We were called from the callback because the DSP
- * requested more data. Note that the DSP does want
- * more data, and if a buffer was in-flight, mark it
- * as available (since the DSP must now be done with
- * it).
- */
- audio->out_needed = 1;
- frame = audio->out + audio->out_tail;
- if (frame->used == 0xffffffff) {
- dprintk("frame %d free\n", audio->out_tail);
- frame->used = 0;
- audio->out_tail ^= 1;
- wake_up(&audio->write_wait);
- }
- }
-
- if (audio->out_needed) {
- /* If the DSP currently wants data and we have a
- * buffer available, we will send it and reset
- * the needed flag. We'll mark the buffer as in-flight
- * so that it won't be recycled until the next buffer
- * is requested
- */
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- BUG_ON(frame->used == 0xffffffff);
- dprintk("frame %d busy\n", audio->out_tail);
- audplay_dsp_send_data_avail(audio, audio->out_tail,
- frame->used);
- frame->used = 0xffffffff;
- audio->out_needed = 0;
- }
- }
-done:
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-}
-
-/* ------------------- device --------------------- */
-
-static void audevrc_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->stopped = 0;
- atomic_set(&audio->out_bytes, 0);
-}
-
-static void audevrc_flush_pcm_buf(struct audio *audio)
-{
- uint8_t index;
-
- for (index = 0; index < PCM_BUF_MAX_COUNT; index++)
- audio->in[index].used = 0;
-
- audio->read_next = 0;
- audio->fill_next = 0;
-}
-
-static long audevrc_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0;
-
- dprintk("audevrc_ioctl() cmd = %d\n", cmd);
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = audpp_avsync_byte_count(audio->dec_id);
- stats.sample_count = audpp_avsync_sample_count(audio->dec_id);
- if (copy_to_user((void *)arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(audio->dec_id, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- return 0;
- }
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audevrc_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audevrc_disable(audio);
- audio->stopped = 1;
- break;
- case AUDIO_SET_CONFIG:{
- dprintk("AUDIO_SET_CONFIG not applicable \n");
- break;
- }
- case AUDIO_GET_CONFIG:{
- struct msm_audio_config config;
- config.buffer_size = BUFSZ;
- config.buffer_count = 2;
- config.sample_rate = 8000;
- config.channel_count = 1;
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void *)arg, &config, sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_GET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- config.pcm_feedback = 0;
- config.buffer_count = PCM_BUF_MAX_COUNT;
- config.buffer_size = PCM_BUFSZ_MIN;
- if (copy_to_user((void *)arg, &config, sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- if (copy_from_user
- (&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if ((config.buffer_count > PCM_BUF_MAX_COUNT) ||
- (config.buffer_count == 1))
- config.buffer_count = PCM_BUF_MAX_COUNT;
-
- if (config.buffer_size < PCM_BUFSZ_MIN)
- config.buffer_size = PCM_BUFSZ_MIN;
-
- /* Check if pcm feedback is required */
- if ((config.pcm_feedback) && (!audio->read_data)) {
- dprintk("audevrc_ioctl: allocate PCM buf %d\n",
- config.buffer_count *
- config.buffer_size);
- audio->read_data =
- dma_alloc_coherent(NULL,
- config.buffer_size *
- config.buffer_count,
- &audio->read_phys,
- GFP_KERNEL);
- if (!audio->read_data) {
- pr_err
- ("audevrc_ioctl: no mem for pcm buf\n");
- rc = -1;
- } else {
- uint8_t index;
- uint32_t offset = 0;
- audio->pcm_feedback = 1;
- audio->buf_refresh = 0;
- audio->pcm_buf_count =
- config.buffer_count;
- audio->read_next = 0;
- audio->fill_next = 0;
-
- for (index = 0;
- index < config.buffer_count;
- index++) {
- audio->in[index].data =
- audio->read_data + offset;
- audio->in[index].addr =
- audio->read_phys + offset;
- audio->in[index].size =
- config.buffer_size;
- audio->in[index].used = 0;
- offset += config.buffer_size;
- }
- rc = 0;
- }
- } else {
- rc = 0;
- }
- break;
- }
- case AUDIO_PAUSE:
- dprintk("%s: AUDIO_PAUSE %ld\n", __func__, arg);
- rc = audpp_pause(audio->dec_id, (int) arg);
- break;
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audevrc_read(struct file *file, char __user *buf, size_t count,
- loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- int rc = 0;
- if (!audio->pcm_feedback) {
- return 0;
- /* PCM feedback is not enabled. Nothing to read */
- }
- mutex_lock(&audio->read_lock);
- dprintk("audevrc_read() \n");
- while (count > 0) {
- rc = wait_event_interruptible(audio->read_wait,
- (audio->in[audio->read_next].
- used > 0) || (audio->stopped));
- dprintk("audevrc_read() wait terminated \n");
- if (rc < 0)
- break;
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
- if (count < audio->in[audio->read_next].used) {
- /* Read must happen in frame boundary. Since driver does
- * not know frame size, read count must be greater or
- * equal to size of PCM samples
- */
- dprintk("audevrc_read:read stop - partial frame\n");
- break;
- } else {
- dprintk("audevrc_read: read from in[%d]\n",
- audio->read_next);
- if (copy_to_user
- (buf, audio->in[audio->read_next].data,
- audio->in[audio->read_next].used)) {
- pr_err("audevrc_read: invalid addr %x \n",
- (unsigned int)buf);
- rc = -EFAULT;
- break;
- }
- count -= audio->in[audio->read_next].used;
- buf += audio->in[audio->read_next].used;
- audio->in[audio->read_next].used = 0;
- if ((++audio->read_next) == audio->pcm_buf_count)
- audio->read_next = 0;
- if (audio->in[audio->read_next].used == 0)
- break; /* No data ready at this moment
- * Exit while loop to prevent
- * output thread sleep too long
- */
-
- }
- }
- if (audio->buf_refresh) {
- audio->buf_refresh = 0;
- dprintk("audevrc_read: kick start pcm feedback again\n");
- audevrc_buffer_refresh(audio);
- }
- mutex_unlock(&audio->read_lock);
- if (buf > start)
- rc = buf - start;
- dprintk("audevrc_read: read %d bytes\n", rc);
- return rc;
-}
-
-static ssize_t audevrc_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- int rc = 0;
-
- if (count & 1)
- return -EINVAL;
- mutex_lock(&audio->write_lock);
- dprintk("audevrc_write() \n");
- while (count > 0) {
- frame = audio->out + audio->out_head;
- rc = wait_event_interruptible(audio->write_wait,
- (frame->used == 0)
- || (audio->stopped));
- if (rc < 0)
- break;
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
- xfer = (count > frame->size) ? frame->size : count;
- if (copy_from_user(frame->data, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
-
- frame->used = xfer;
- audio->out_head ^= 1;
- count -= xfer;
- buf += xfer;
-
- audevrc_send_data(audio, 0);
-
- }
- mutex_unlock(&audio->write_lock);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audevrc_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- dprintk("audevrc_release()\n");
-
- mutex_lock(&audio->lock);
- audevrc_disable(audio);
- audevrc_flush(audio);
- audevrc_flush_pcm_buf(audio);
- msm_adsp_put(audio->audplay);
- audio->audplay = NULL;
- audio->opened = 0;
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- audio->data = NULL;
- if (audio->read_data != NULL) {
- dma_free_coherent(NULL,
- audio->in[0].size * audio->pcm_buf_count,
- audio->read_data, audio->read_phys);
- audio->read_data = NULL;
- }
- audio->pcm_feedback = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio the_evrc_audio;
-
-static int audevrc_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_evrc_audio;
- int rc;
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- return -EBUSY;
- }
-
- /* Acquire Lock */
- mutex_lock(&audio->lock);
-
- if (!audio->data) {
- audio->data = dma_alloc_coherent(NULL, DMASZ,
- &audio->phys, GFP_KERNEL);
- if (!audio->data) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto dma_fail;
- }
- }
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto audmgr_fail;
-
- rc = msm_adsp_get("AUDPLAY0TASK", &audio->audplay,
- &audplay_adsp_ops_evrc, audio);
- if (rc) {
- pr_err("audio: failed to get audplay0 dsp module\n");
- goto adsp_fail;
- }
-
- audio->dec_id = 0;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = BUFSZ;
-
- audio->out[1].data = audio->data + BUFSZ;
- audio->out[1].addr = audio->phys + BUFSZ;
- audio->out[1].size = BUFSZ;
-
- audio->volume = 0x3FFF;
-
- audevrc_flush(audio);
-
- audio->opened = 1;
- file->private_data = audio;
-
- mutex_unlock(&audio->lock);
- return rc;
-
-adsp_fail:
- audmgr_close(&audio->audmgr);
-audmgr_fail:
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
-dma_fail:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static struct file_operations audio_evrc_fops = {
- .owner = THIS_MODULE,
- .open = audevrc_open,
- .release = audevrc_release,
- .read = audevrc_read,
- .write = audevrc_write,
- .unlocked_ioctl = audevrc_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_evrc_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_evrc",
- .fops = &audio_evrc_fops,
-};
-
-static int __init audevrc_init(void)
-{
- mutex_init(&the_evrc_audio.lock);
- mutex_init(&the_evrc_audio.write_lock);
- mutex_init(&the_evrc_audio.read_lock);
- spin_lock_init(&the_evrc_audio.dsp_lock);
- init_waitqueue_head(&the_evrc_audio.write_wait);
- init_waitqueue_head(&the_evrc_audio.read_wait);
- the_evrc_audio.read_data = NULL;
- return misc_register(&audio_evrc_misc);
-}
-
-static void __exit audevrc_exit(void)
-{
- misc_deregister(&audio_evrc_misc);
-}
-
-module_init(audevrc_init);
-module_exit(audevrc_exit);
-
-MODULE_DESCRIPTION("MSM EVRC driver");
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("QUALCOMM Inc");
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audio_in.c
- *
- * pcm audio input device
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <linux/delay.h>
-
-#include <linux/msm_audio.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-#include <mach/msm_rpcrouter.h>
-
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audpreproccmdi.h>
-#include <mach/qdsp5/qdsp5audpreprocmsg.h>
-#include <mach/qdsp5/qdsp5audreccmdi.h>
-#include <mach/qdsp5/qdsp5audrecmsg.h>
-
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-/* FRAME_NUM must be a power of two */
-#define FRAME_NUM (8)
-#define FRAME_SIZE (2052 * 2)
-#define MONO_DATA_SIZE (2048)
-#define STEREO_DATA_SIZE (MONO_DATA_SIZE * 2)
-#define DMASZ (FRAME_SIZE * FRAME_NUM)
-
-#define AGC_PARAM_SIZE (20)
-#define NS_PARAM_SIZE (6)
-#define IIR_PARAM_SIZE (48)
-#define DEBUG (0)
-
-#define AGC_ENABLE 0x0001
-#define NS_ENABLE 0x0002
-#define IIR_ENABLE 0x0004
-
-struct tx_agc_config {
- uint16_t agc_params[AGC_PARAM_SIZE];
-};
-
-struct ns_config {
- uint16_t ns_params[NS_PARAM_SIZE];
-};
-
-struct tx_iir_filter {
- uint16_t num_bands;
- uint16_t iir_params[IIR_PARAM_SIZE];
-};
-
-struct audpre_cmd_iir_config_type {
- uint16_t cmd_id;
- uint16_t active_flag;
- uint16_t num_bands;
- uint16_t iir_params[IIR_PARAM_SIZE];
-};
-
-struct buffer {
- void *data;
- uint32_t size;
- uint32_t read;
- uint32_t addr;
-};
-
-struct audio_in {
- struct buffer in[FRAME_NUM];
-
- spinlock_t dsp_lock;
-
- atomic_t in_bytes;
-
- struct mutex lock;
- struct mutex read_lock;
- wait_queue_head_t wait;
-
- struct msm_adsp_module *audpre;
- struct msm_adsp_module *audrec;
-
- /* configuration to use on next enable */
- uint32_t samp_rate;
- uint32_t channel_mode;
- uint32_t buffer_size; /* 2048 for mono, 4096 for stereo */
- uint32_t type; /* 0 for PCM ,1 for AAC */
- uint32_t dsp_cnt;
- uint32_t in_head; /* next buffer dsp will write */
- uint32_t in_tail; /* next buffer read() will read */
- uint32_t in_count; /* number of buffers available to read() */
-
- unsigned short samp_rate_index;
-
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- int opened;
- int enabled;
- int running;
- int stopped; /* set when stopped, cleared on flush */
-
- /* audpre settings */
- int agc_enable;
- struct tx_agc_config agc;
-
- int ns_enable;
- struct ns_config ns;
-
- int iir_enable;
- struct tx_iir_filter iir;
-};
-
-static int audio_in_dsp_enable(struct audio_in *audio, int enable);
-static int audio_in_encoder_config(struct audio_in *audio);
-static int audio_dsp_read_buffer(struct audio_in *audio, uint32_t read_cnt);
-static void audio_flush(struct audio_in *audio);
-static int audio_dsp_set_agc(struct audio_in *audio);
-static int audio_dsp_set_ns(struct audio_in *audio);
-static int audio_dsp_set_tx_iir(struct audio_in *audio);
-
-static unsigned convert_dsp_samp_index(unsigned index)
-{
- switch (index) {
- case 48000: return AUDREC_CMD_SAMP_RATE_INDX_48000;
- case 44100: return AUDREC_CMD_SAMP_RATE_INDX_44100;
- case 32000: return AUDREC_CMD_SAMP_RATE_INDX_32000;
- case 24000: return AUDREC_CMD_SAMP_RATE_INDX_24000;
- case 22050: return AUDREC_CMD_SAMP_RATE_INDX_22050;
- case 16000: return AUDREC_CMD_SAMP_RATE_INDX_16000;
- case 12000: return AUDREC_CMD_SAMP_RATE_INDX_12000;
- case 11025: return AUDREC_CMD_SAMP_RATE_INDX_11025;
- case 8000: return AUDREC_CMD_SAMP_RATE_INDX_8000;
- default: return AUDREC_CMD_SAMP_RATE_INDX_11025;
- }
-}
-
-static unsigned convert_samp_rate(unsigned hz)
-{
- switch (hz) {
- case 48000: return RPC_AUD_DEF_SAMPLE_RATE_48000;
- case 44100: return RPC_AUD_DEF_SAMPLE_RATE_44100;
- case 32000: return RPC_AUD_DEF_SAMPLE_RATE_32000;
- case 24000: return RPC_AUD_DEF_SAMPLE_RATE_24000;
- case 22050: return RPC_AUD_DEF_SAMPLE_RATE_22050;
- case 16000: return RPC_AUD_DEF_SAMPLE_RATE_16000;
- case 12000: return RPC_AUD_DEF_SAMPLE_RATE_12000;
- case 11025: return RPC_AUD_DEF_SAMPLE_RATE_11025;
- case 8000: return RPC_AUD_DEF_SAMPLE_RATE_8000;
- default: return RPC_AUD_DEF_SAMPLE_RATE_11025;
- }
-}
-
-static unsigned convert_samp_index(unsigned index)
-{
- switch (index) {
- case RPC_AUD_DEF_SAMPLE_RATE_48000: return 48000;
- case RPC_AUD_DEF_SAMPLE_RATE_44100: return 44100;
- case RPC_AUD_DEF_SAMPLE_RATE_32000: return 32000;
- case RPC_AUD_DEF_SAMPLE_RATE_24000: return 24000;
- case RPC_AUD_DEF_SAMPLE_RATE_22050: return 22050;
- case RPC_AUD_DEF_SAMPLE_RATE_16000: return 16000;
- case RPC_AUD_DEF_SAMPLE_RATE_12000: return 12000;
- case RPC_AUD_DEF_SAMPLE_RATE_11025: return 11025;
- case RPC_AUD_DEF_SAMPLE_RATE_8000: return 8000;
- default: return 11025;
- }
-}
-
-/* must be called with audio->lock held */
-static int audio_in_enable(struct audio_in *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- if (audio->enabled)
- return 0;
-
- cfg.tx_rate = audio->samp_rate;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.def_method = RPC_AUD_DEF_METHOD_RECORD;
- if (audio->type == AUDREC_CMD_TYPE_0_INDEX_WAV)
- cfg.codec = RPC_AUD_DEF_CODEC_PCM;
- else
- cfg.codec = RPC_AUD_DEF_CODEC_AAC;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audpre)) {
- pr_err("audrec: msm_adsp_enable(audpre) failed\n");
- return -ENODEV;
- }
- if (msm_adsp_enable(audio->audrec)) {
- pr_err("audrec: msm_adsp_enable(audrec) failed\n");
- return -ENODEV;
- }
-
- audio->enabled = 1;
- audio_in_dsp_enable(audio, 1);
-
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audio_in_disable(struct audio_in *audio)
-{
- if (audio->enabled) {
- audio->enabled = 0;
-
- audio_in_dsp_enable(audio, 0);
-
- wake_up(&audio->wait);
-
- msm_adsp_disable(audio->audrec);
- msm_adsp_disable(audio->audpre);
- audmgr_disable(&audio->audmgr);
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audpre_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- uint16_t msg[2];
- getevent(msg, sizeof(msg));
-
- switch (id) {
- case AUDPREPROC_MSG_CMD_CFG_DONE_MSG:
- pr_info("audpre: type %d, status_flag %d\n", msg[0], msg[1]);
- break;
- case AUDPREPROC_MSG_ERROR_MSG_ID:
- pr_info("audpre: err_index %d\n", msg[0]);
- break;
- default:
- pr_err("audpre: unknown event %d\n", id);
- }
-}
-
-struct audio_frame {
- uint16_t count_low;
- uint16_t count_high;
- uint16_t bytes;
- uint16_t unknown;
- unsigned char samples[];
-} __attribute__((packed));
-
-static void audio_in_get_dsp_frames(struct audio_in *audio)
-{
- struct audio_frame *frame;
- uint32_t index;
- unsigned long flags;
-
- index = audio->in_head;
-
- /* XXX check for bogus frame size? */
-
- frame = (void *) (((char *)audio->in[index].data) - sizeof(*frame));
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->in[index].size = frame->bytes;
-
- audio->in_head = (audio->in_head + 1) & (FRAME_NUM - 1);
-
- /* If overflow, move the tail index foward. */
- if (audio->in_head == audio->in_tail)
- audio->in_tail = (audio->in_tail + 1) & (FRAME_NUM - 1);
- else
- audio->in_count++;
-
- audio_dsp_read_buffer(audio, audio->dsp_cnt++);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-
- wake_up(&audio->wait);
-}
-
-static void audrec_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- struct audio_in *audio = data;
- uint16_t msg[3];
- getevent(msg, sizeof(msg));
-
- switch (id) {
- case AUDREC_MSG_CMD_CFG_DONE_MSG:
- if (msg[0] & AUDREC_MSG_CFG_DONE_TYPE_0_UPDATE) {
- if (msg[0] & AUDREC_MSG_CFG_DONE_TYPE_0_ENA) {
- pr_info("audpre: CFG ENABLED\n");
- audio_dsp_set_agc(audio);
- audio_dsp_set_ns(audio);
- audio_dsp_set_tx_iir(audio);
- audio_in_encoder_config(audio);
- } else {
- pr_info("audrec: CFG SLEEP\n");
- audio->running = 0;
- }
- } else {
- pr_info("audrec: CMD_CFG_DONE %x\n", msg[0]);
- }
- break;
- case AUDREC_MSG_CMD_AREC_PARAM_CFG_DONE_MSG: {
- pr_info("audrec: PARAM CFG DONE\n");
- audio->running = 1;
- break;
- }
- case AUDREC_MSG_FATAL_ERR_MSG:
- pr_err("audrec: ERROR %x\n", msg[0]);
- break;
- case AUDREC_MSG_PACKET_READY_MSG:
-/* REC_DBG("type %x, count %d", msg[0], (msg[1] | (msg[2] << 16))); */
- audio_in_get_dsp_frames(audio);
- break;
- default:
- pr_err("audrec: unknown event %d\n", id);
- }
-}
-
-struct msm_adsp_ops audpre_adsp_ops = {
- .event = audpre_dsp_event,
-};
-
-struct msm_adsp_ops audrec_adsp_ops = {
- .event = audrec_dsp_event,
-};
-
-
-#define audio_send_queue_pre(audio, cmd, len) \
- msm_adsp_write(audio->audpre, QDSP_uPAudPreProcCmdQueue, cmd, len)
-#define audio_send_queue_recbs(audio, cmd, len) \
- msm_adsp_write(audio->audrec, QDSP_uPAudRecBitStreamQueue, cmd, len)
-#define audio_send_queue_rec(audio, cmd, len) \
- msm_adsp_write(audio->audrec, \
- QDSP_uPAudRecCmdQueue, cmd, len)
-
-static int audio_dsp_set_agc(struct audio_in *audio)
-{
- audpreproc_cmd_cfg_agc_params cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_CMD_CFG_AGC_PARAMS;
-
- if (audio->agc_enable) {
- /* cmd.tx_agc_param_mask = 0xFE00 from sample code */
- cmd.tx_agc_param_mask =
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_SLOPE) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_TH) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_SLOPE) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_EXP_TH) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_AIG_FLAG) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_COMP_STATIC_GAIN) |
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_TX_AGC_ENA_FLAG);
- cmd.tx_agc_enable_flag =
- AUDPREPROC_CMD_TX_AGC_ENA_FLAG_ENA;
- memcpy(&cmd.static_gain, &audio->agc.agc_params[0],
- sizeof(uint16_t) * 6);
- /* cmd.param_mask = 0xFFF0 from sample code */
- cmd.param_mask =
- (1 << AUDPREPROC_CMD_PARAM_MASK_RMS_TAY) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_RELEASEK) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_DELAY) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_ATTACKK) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_SLOW) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_LEAKRATE_FAST) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_AIG_RELEASEK) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_AIG_MIN) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_AIG_MAX) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_LEAK_UP) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_LEAK_DOWN) |
- (1 << AUDPREPROC_CMD_PARAM_MASK_AIG_ATTACKK);
- memcpy(&cmd.aig_attackk, &audio->agc.agc_params[6],
- sizeof(uint16_t) * 14);
-
- } else {
- cmd.tx_agc_param_mask =
- (1 << AUDPREPROC_CMD_TX_AGC_PARAM_MASK_TX_AGC_ENA_FLAG);
- cmd.tx_agc_enable_flag =
- AUDPREPROC_CMD_TX_AGC_ENA_FLAG_DIS;
- }
-#if DEBUG
- pr_info("cmd_id = 0x%04x\n", cmd.cmd_id);
- pr_info("tx_agc_param_mask = 0x%04x\n", cmd.tx_agc_param_mask);
- pr_info("tx_agc_enable_flag = 0x%04x\n", cmd.tx_agc_enable_flag);
- pr_info("static_gain = 0x%04x\n", cmd.static_gain);
- pr_info("adaptive_gain_flag = 0x%04x\n", cmd.adaptive_gain_flag);
- pr_info("expander_th = 0x%04x\n", cmd.expander_th);
- pr_info("expander_slope = 0x%04x\n", cmd.expander_slope);
- pr_info("compressor_th = 0x%04x\n", cmd.compressor_th);
- pr_info("compressor_slope = 0x%04x\n", cmd.compressor_slope);
- pr_info("param_mask = 0x%04x\n", cmd.param_mask);
- pr_info("aig_attackk = 0x%04x\n", cmd.aig_attackk);
- pr_info("aig_leak_down = 0x%04x\n", cmd.aig_leak_down);
- pr_info("aig_leak_up = 0x%04x\n", cmd.aig_leak_up);
- pr_info("aig_max = 0x%04x\n", cmd.aig_max);
- pr_info("aig_min = 0x%04x\n", cmd.aig_min);
- pr_info("aig_releasek = 0x%04x\n", cmd.aig_releasek);
- pr_info("aig_leakrate_fast = 0x%04x\n", cmd.aig_leakrate_fast);
- pr_info("aig_leakrate_slow = 0x%04x\n", cmd.aig_leakrate_slow);
- pr_info("attackk_msw = 0x%04x\n", cmd.attackk_msw);
- pr_info("attackk_lsw = 0x%04x\n", cmd.attackk_lsw);
- pr_info("delay = 0x%04x\n", cmd.delay);
- pr_info("releasek_msw = 0x%04x\n", cmd.releasek_msw);
- pr_info("releasek_lsw = 0x%04x\n", cmd.releasek_lsw);
- pr_info("rms_tav = 0x%04x\n", cmd.rms_tav);
-#endif
- return audio_send_queue_pre(audio, &cmd, sizeof(cmd));
-}
-
-static int audio_dsp_set_ns(struct audio_in *audio)
-{
- audpreproc_cmd_cfg_ns_params cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_CMD_CFG_NS_PARAMS;
-
- if (audio->ns_enable) {
- /* cmd.ec_mode_new is fixed as 0x0064 when enable from sample code */
- cmd.ec_mode_new =
- AUDPREPROC_CMD_EC_MODE_NEW_NS_ENA |
- AUDPREPROC_CMD_EC_MODE_NEW_HB_ENA |
- AUDPREPROC_CMD_EC_MODE_NEW_VA_ENA;
- memcpy(&cmd.dens_gamma_n, &audio->ns.ns_params,
- sizeof(audio->ns.ns_params));
- } else {
- cmd.ec_mode_new =
- AUDPREPROC_CMD_EC_MODE_NEW_NLMS_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_DES_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_NS_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_CNI_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_NLES_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_HB_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_VA_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_PCD_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_FEHI_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_NEHI_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_NLPP_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_FNE_DIS |
- AUDPREPROC_CMD_EC_MODE_NEW_PRENLMS_DIS;
- }
-#if DEBUG
- pr_info("cmd_id = 0x%04x\n", cmd.cmd_id);
- pr_info("ec_mode_new = 0x%04x\n", cmd.ec_mode_new);
- pr_info("dens_gamma_n = 0x%04x\n", cmd.dens_gamma_n);
- pr_info("dens_nfe_block_size = 0x%04x\n", cmd.dens_nfe_block_size);
- pr_info("dens_limit_ns = 0x%04x\n", cmd.dens_limit_ns);
- pr_info("dens_limit_ns_d = 0x%04x\n", cmd.dens_limit_ns_d);
- pr_info("wb_gamma_e = 0x%04x\n", cmd.wb_gamma_e);
- pr_info("wb_gamma_n = 0x%04x\n", cmd.wb_gamma_n);
-#endif
- return audio_send_queue_pre(audio, &cmd, sizeof(cmd));
-}
-
-static int audio_dsp_set_tx_iir(struct audio_in *audio)
-{
- struct audpre_cmd_iir_config_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPREPROC_CMD_CFG_IIR_TUNING_FILTER_PARAMS;
-
- if (audio->iir_enable) {
- cmd.active_flag = AUDPREPROC_CMD_IIR_ACTIVE_FLAG_ENA;
- cmd.num_bands = audio->iir.num_bands;
- memcpy(&cmd.iir_params, &audio->iir.iir_params,
- sizeof(audio->iir.iir_params));
- } else {
- cmd.active_flag = AUDPREPROC_CMD_IIR_ACTIVE_FLAG_DIS;
- }
-#if DEBUG
- pr_info("cmd_id = 0x%04x\n", cmd.cmd_id);
- pr_info("active_flag = 0x%04x\n", cmd.active_flag);
-#endif
- return audio_send_queue_pre(audio, &cmd, sizeof(cmd));
-}
-
-static int audio_in_dsp_enable(struct audio_in *audio, int enable)
-{
- audrec_cmd_cfg cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDREC_CMD_CFG;
- cmd.type_0 = enable ? AUDREC_CMD_TYPE_0_ENA : AUDREC_CMD_TYPE_0_DIS;
- cmd.type_0 |= (AUDREC_CMD_TYPE_0_UPDATE | audio->type);
- cmd.type_1 = 0;
-
- return audio_send_queue_rec(audio, &cmd, sizeof(cmd));
-}
-
-static int audio_in_encoder_config(struct audio_in *audio)
-{
- audrec_cmd_arec0param_cfg cmd;
- uint16_t *data = (void *) audio->data;
- unsigned n;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDREC_CMD_AREC0PARAM_CFG;
- cmd.ptr_to_extpkt_buffer_msw = audio->phys >> 16;
- cmd.ptr_to_extpkt_buffer_lsw = audio->phys;
- cmd.buf_len = FRAME_NUM; /* Both WAV and AAC use 8 frames */
- cmd.samp_rate_index = audio->samp_rate_index;
- cmd.stereo_mode = audio->channel_mode; /* 0 for mono, 1 for stereo */
-
- /* FIXME have no idea why cmd.rec_quality is fixed
- * as 0x1C00 from sample code
- */
- cmd.rec_quality = 0x1C00;
-
- /* prepare buffer pointers:
- * Mono: 1024 samples + 4 halfword header
- * Stereo: 2048 samples + 4 halfword header
- * AAC
- * Mono/Stere: 768 + 4 halfword header
- */
- for (n = 0; n < FRAME_NUM; n++) {
- audio->in[n].data = data + 4;
- if (audio->type == AUDREC_CMD_TYPE_0_INDEX_WAV)
- data += (4 + (audio->channel_mode ? 2048 : 1024));
- else if (audio->type == AUDREC_CMD_TYPE_0_INDEX_AAC)
- data += (4 + 768);
- }
-
- return audio_send_queue_rec(audio, &cmd, sizeof(cmd));
-}
-
-static int audio_dsp_read_buffer(struct audio_in *audio, uint32_t read_cnt)
-{
- audrec_cmd_packet_ext_ptr cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDREC_CMD_PACKET_EXT_PTR;
- /* Both WAV and AAC use AUDREC_CMD_TYPE_0 */
- cmd.type = AUDREC_CMD_TYPE_0;
- cmd.curr_rec_count_msw = read_cnt >> 16;
- cmd.curr_rec_count_lsw = read_cnt;
-
- return audio_send_queue_recbs(audio, &cmd, sizeof(cmd));
-}
-
-/* ------------------- device --------------------- */
-
-static void audio_enable_agc(struct audio_in *audio, int enable)
-{
- if (audio->agc_enable != enable) {
- audio->agc_enable = enable;
- if (audio->running)
- audio_dsp_set_agc(audio);
- }
-}
-
-static void audio_enable_ns(struct audio_in *audio, int enable)
-{
- if (audio->ns_enable != enable) {
- audio->ns_enable = enable;
- if (audio->running)
- audio_dsp_set_ns(audio);
- }
-}
-
-static void audio_enable_tx_iir(struct audio_in *audio, int enable)
-{
- if (audio->iir_enable != enable) {
- audio->iir_enable = enable;
- if (audio->running)
- audio_dsp_set_tx_iir(audio);
- }
-}
-
-static void audio_flush(struct audio_in *audio)
-{
- int i;
-
- audio->dsp_cnt = 0;
- audio->in_head = 0;
- audio->in_tail = 0;
- audio->in_count = 0;
- for (i = 0; i < FRAME_NUM; i++) {
- audio->in[i].size = 0;
- audio->in[i].read = 0;
- }
-}
-
-static long audio_in_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- struct audio_in *audio = file->private_data;
- int rc;
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = atomic_read(&audio->in_bytes);
- if (copy_to_user((void *) arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
-
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audio_in_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audio_in_disable(audio);
- audio->stopped = 1;
- break;
- case AUDIO_FLUSH:
- if (audio->stopped) {
- /* Make sure we're stopped and we wake any threads
- * that might be blocked holding the read_lock.
- * While audio->stopped read threads will always
- * exit immediately.
- */
- wake_up(&audio->wait);
- mutex_lock(&audio->read_lock);
- audio_flush(audio);
- mutex_unlock(&audio->read_lock);
- }
- case AUDIO_SET_CONFIG: {
- struct msm_audio_config cfg;
- if (copy_from_user(&cfg, (void *) arg, sizeof(cfg))) {
- rc = -EFAULT;
- break;
- }
- if (cfg.channel_count == 1) {
- cfg.channel_count = AUDREC_CMD_STEREO_MODE_MONO;
- } else if (cfg.channel_count == 2) {
- cfg.channel_count = AUDREC_CMD_STEREO_MODE_STEREO;
- } else {
- rc = -EINVAL;
- break;
- }
-
- if (cfg.type == 0) {
- cfg.type = AUDREC_CMD_TYPE_0_INDEX_WAV;
- } else if (cfg.type == 1) {
- cfg.type = AUDREC_CMD_TYPE_0_INDEX_AAC;
- } else {
- rc = -EINVAL;
- break;
- }
- audio->samp_rate = convert_samp_rate(cfg.sample_rate);
- audio->samp_rate_index =
- convert_dsp_samp_index(cfg.sample_rate);
- audio->channel_mode = cfg.channel_count;
- audio->buffer_size =
- audio->channel_mode ? STEREO_DATA_SIZE
- : MONO_DATA_SIZE;
- audio->type = cfg.type;
- rc = 0;
- break;
- }
- case AUDIO_GET_CONFIG: {
- struct msm_audio_config cfg;
- cfg.buffer_size = audio->buffer_size;
- cfg.buffer_count = FRAME_NUM;
- cfg.sample_rate = convert_samp_index(audio->samp_rate);
- if (audio->channel_mode == AUDREC_CMD_STEREO_MODE_MONO)
- cfg.channel_count = 1;
- else
- cfg.channel_count = 2;
- if (audio->type == AUDREC_CMD_TYPE_0_INDEX_WAV)
- cfg.type = 0;
- else
- cfg.type = 1;
- cfg.unused[0] = 0;
- cfg.unused[1] = 0;
- cfg.unused[2] = 0;
- if (copy_to_user((void *) arg, &cfg, sizeof(cfg)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audio_in_read(struct file *file,
- char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio_in *audio = file->private_data;
- unsigned long flags;
- const char __user *start = buf;
- void *data;
- uint32_t index;
- uint32_t size;
- int rc = 0;
-
- mutex_lock(&audio->read_lock);
- while (count > 0) {
- rc = wait_event_interruptible(
- audio->wait, (audio->in_count > 0) || audio->stopped);
- if (rc < 0)
- break;
-
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
-
- index = audio->in_tail;
- data = (uint8_t *) audio->in[index].data;
- size = audio->in[index].size;
- if (count >= size) {
- if (copy_to_user(buf, data, size)) {
- rc = -EFAULT;
- break;
- }
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (index != audio->in_tail) {
- /* overrun -- data is invalid and we need to retry */
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- continue;
- }
- audio->in[index].size = 0;
- audio->in_tail = (audio->in_tail + 1) & (FRAME_NUM - 1);
- audio->in_count--;
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- count -= size;
- buf += size;
- if (audio->type == AUDREC_CMD_TYPE_0_INDEX_AAC)
- break;
- } else {
- pr_err("audio_in: short read\n");
- break;
- }
- if (audio->type == AUDREC_CMD_TYPE_0_INDEX_AAC)
- break; /* AAC only read one frame */
- }
- mutex_unlock(&audio->read_lock);
-
- if (buf > start)
- return buf - start;
-
- return rc;
-}
-
-static ssize_t audio_in_write(struct file *file,
- const char __user *buf,
- size_t count, loff_t *pos)
-{
- return -EINVAL;
-}
-
-static int audio_in_release(struct inode *inode, struct file *file)
-{
- struct audio_in *audio = file->private_data;
-
- mutex_lock(&audio->lock);
- audio_in_disable(audio);
- audio_flush(audio);
- msm_adsp_put(audio->audrec);
- msm_adsp_put(audio->audpre);
- audio->audrec = NULL;
- audio->audpre = NULL;
- audio->opened = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio_in the_audio_in;
-
-static int audio_in_open(struct inode *inode, struct file *file)
-{
- struct audio_in *audio = &the_audio_in;
- int rc;
-
- mutex_lock(&audio->lock);
- if (audio->opened) {
- rc = -EBUSY;
- goto done;
- }
-
- /* Settings will be re-config at AUDIO_SET_CONFIG,
- * but at least we need to have initial config
- */
- audio->samp_rate = RPC_AUD_DEF_SAMPLE_RATE_11025;
- audio->samp_rate_index = AUDREC_CMD_SAMP_RATE_INDX_11025;
- audio->channel_mode = AUDREC_CMD_STEREO_MODE_MONO;
- audio->buffer_size = MONO_DATA_SIZE;
- audio->type = AUDREC_CMD_TYPE_0_INDEX_WAV;
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto done;
- rc = msm_adsp_get("AUDPREPROCTASK", &audio->audpre,
- &audpre_adsp_ops, audio);
- if (rc)
- goto done;
- rc = msm_adsp_get("AUDRECTASK", &audio->audrec,
- &audrec_adsp_ops, audio);
- if (rc)
- goto done;
-
- audio->dsp_cnt = 0;
- audio->stopped = 0;
-
- audio_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
-done:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static long audpre_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct audio_in *audio = file->private_data;
- int rc = 0, enable;
- uint16_t enable_mask;
-#if DEBUG
- int i;
-#endif
-
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_ENABLE_AUDPRE: {
- if (copy_from_user(&enable_mask, (void *) arg,
- sizeof(enable_mask)))
- goto out_fault;
-
- enable = (enable_mask & AGC_ENABLE) ? 1 : 0;
- audio_enable_agc(audio, enable);
- enable = (enable_mask & NS_ENABLE) ? 1 : 0;
- audio_enable_ns(audio, enable);
- enable = (enable_mask & IIR_ENABLE) ? 1 : 0;
- audio_enable_tx_iir(audio, enable);
- break;
- }
- case AUDIO_SET_AGC: {
- if (copy_from_user(&audio->agc, (void *) arg,
- sizeof(audio->agc)))
- goto out_fault;
-#if DEBUG
- pr_info("set agc\n");
- for (i = 0; i < AGC_PARAM_SIZE; i++) \
- pr_info("agc_params[%d] = 0x%04x\n", i,
- audio->agc.agc_params[i]);
-#endif
- break;
- }
- case AUDIO_SET_NS: {
- if (copy_from_user(&audio->ns, (void *) arg,
- sizeof(audio->ns)))
- goto out_fault;
-#if DEBUG
- pr_info("set ns\n");
- for (i = 0; i < NS_PARAM_SIZE; i++) \
- pr_info("ns_params[%d] = 0x%04x\n",
- i, audio->ns.ns_params[i]);
-#endif
- break;
- }
- case AUDIO_SET_TX_IIR: {
- if (copy_from_user(&audio->iir, (void *) arg,
- sizeof(audio->iir)))
- goto out_fault;
-#if DEBUG
- pr_info("set iir\n");
- pr_info("iir.num_bands = 0x%04x\n", audio->iir.num_bands);
- for (i = 0; i < IIR_PARAM_SIZE; i++) \
- pr_info("iir_params[%d] = 0x%04x\n",
- i, audio->iir.iir_params[i]);
-#endif
- break;
- }
- default:
- rc = -EINVAL;
- }
-
- goto out;
-
-out_fault:
- rc = -EFAULT;
-out:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static int audpre_open(struct inode *inode, struct file *file)
-{
- struct audio_in *audio = &the_audio_in;
- file->private_data = audio;
- return 0;
-}
-
-static struct file_operations audio_fops = {
- .owner = THIS_MODULE,
- .open = audio_in_open,
- .release = audio_in_release,
- .read = audio_in_read,
- .write = audio_in_write,
- .unlocked_ioctl = audio_in_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct file_operations audpre_fops = {
- .owner = THIS_MODULE,
- .open = audpre_open,
- .unlocked_ioctl = audpre_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_in_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_pcm_in",
- .fops = &audio_fops,
-};
-
-struct miscdevice audpre_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_audpre",
- .fops = &audpre_fops,
-};
-
-static int __init audio_in_init(void)
-{
- int rc;
- the_audio_in.data = dma_alloc_coherent(NULL, DMASZ,
- &the_audio_in.phys, GFP_KERNEL);
- if (!the_audio_in.data) {
- printk(KERN_ERR "%s: Unable to allocate DMA buffer\n",
- __func__);
- return -ENOMEM;
- }
-
- mutex_init(&the_audio_in.lock);
- mutex_init(&the_audio_in.read_lock);
- spin_lock_init(&the_audio_in.dsp_lock);
- init_waitqueue_head(&the_audio_in.wait);
- rc = misc_register(&audio_in_misc);
- if (!rc) {
- rc = misc_register(&audpre_misc);
- if (rc < 0)
- misc_deregister(&audio_in_misc);
- }
- return rc;
-}
-
-device_initcall(audio_in_init);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audio_mp3.c
- *
- * mp3 audio output device
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <linux/delay.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-
-#include <linux/msm_audio.h>
-
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-#include <mach/qdsp5/qdsp5audplaycmdi.h>
-#include <mach/qdsp5/qdsp5audplaymsg.h>
-
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-#ifdef DEBUG
-#define dprintk(format, arg...) \
-printk(KERN_DEBUG format, ## arg)
-#else
-#define dprintk(format, arg...) do {} while (0)
-#endif
-
-/* Size must be power of 2 */
-#define BUFSZ_MAX 32768
-#define BUFSZ_MIN 4096
-#define DMASZ_MAX (BUFSZ_MAX * 2)
-#define DMASZ_MIN (BUFSZ_MIN * 2)
-
-#define AUDPLAY_INVALID_READ_PTR_OFFSET 0xFFFF
-#define AUDDEC_DEC_MP3 2
-
-#define PCM_BUFSZ_MIN 4800 /* Hold one stereo MP3 frame */
-#define PCM_BUF_MAX_COUNT 5 /* DSP only accepts 5 buffers at most
- but support 2 buffers currently */
-#define ROUTING_MODE_FTRT 1
-#define ROUTING_MODE_RT 2
-/* Decoder status received from AUDPPTASK */
-#define AUDPP_DEC_STATUS_SLEEP 0
-#define AUDPP_DEC_STATUS_INIT 1
-#define AUDPP_DEC_STATUS_CFG 2
-#define AUDPP_DEC_STATUS_PLAY 3
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used; /* Input usage actual DSP produced PCM size */
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[2];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
- unsigned out_dma_sz;
-
- atomic_t out_bytes;
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t write_wait;
-
- /* Host PCM section */
- struct buffer in[PCM_BUF_MAX_COUNT];
- struct mutex read_lock;
- wait_queue_head_t read_wait; /* Wait queue for read */
- char *read_data; /* pointer to reader buffer */
- dma_addr_t read_phys; /* physical address of reader buffer */
- uint8_t read_next; /* index to input buffers to be read next */
- uint8_t fill_next; /* index to buffer that DSP should be filling */
- uint8_t pcm_buf_count; /* number of pcm buffer allocated */
- /* ---- End of Host PCM section */
-
- struct msm_adsp_module *audplay;
-
- /* configuration to use on next enable */
- uint32_t out_sample_rate;
- uint32_t out_channel_mode;
-
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- int rflush; /* Read flush */
- int wflush; /* Write flush */
- int opened;
- int enabled;
- int running;
- int stopped; /* set when stopped, cleared on flush */
- int pcm_feedback;
- int buf_refresh;
-
- int reserved; /* A byte is being reserved */
- char rsv_byte; /* Handle odd length user data */
-
- unsigned volume;
-
- uint16_t dec_id;
- uint32_t read_ptr_offset;
-};
-
-static int auddec_dsp_config(struct audio *audio, int enable);
-static void audpp_cmd_cfg_adec_params(struct audio *audio);
-static void audpp_cmd_cfg_routing_mode(struct audio *audio);
-static void audplay_send_data(struct audio *audio, unsigned needed);
-static void audplay_config_hostpcm(struct audio *audio);
-static void audplay_buffer_refresh(struct audio *audio);
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg);
-
-/* must be called with audio->lock held */
-static int audio_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- pr_info("audio_enable()\n");
-
- if (audio->enabled)
- return 0;
-
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_PLAYBACK;
- cfg.codec = RPC_AUD_DEF_CODEC_MP3;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audplay)) {
- pr_err("audio: msm_adsp_enable(audplay) failed\n");
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- if (audpp_enable(audio->dec_id, audio_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- msm_adsp_disable(audio->audplay);
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audio_disable(struct audio *audio)
-{
- pr_info("audio_disable()\n");
- if (audio->enabled) {
- audio->enabled = 0;
- auddec_dsp_config(audio, 0);
- wake_up(&audio->write_wait);
- wake_up(&audio->read_wait);
- msm_adsp_disable(audio->audplay);
- audpp_disable(audio->dec_id, audio);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audio_update_pcm_buf_entry(struct audio *audio, uint32_t *payload)
-{
- uint8_t index;
- unsigned long flags;
-
- if (audio->rflush) {
- audio->buf_refresh = 1;
- return;
- }
- spin_lock_irqsave(&audio->dsp_lock, flags);
- for (index = 0; index < payload[1]; index++) {
- if (audio->in[audio->fill_next].addr ==
- payload[2 + index * 2]) {
- pr_info("audio_update_pcm_buf_entry: in[%d] ready\n",
- audio->fill_next);
- audio->in[audio->fill_next].used =
- payload[3 + index * 2];
- if ((++audio->fill_next) == audio->pcm_buf_count)
- audio->fill_next = 0;
-
- } else {
- pr_err
- ("audio_update_pcm_buf_entry: expected=%x ret=%x\n"
- , audio->in[audio->fill_next].addr,
- payload[1 + index * 2]);
- break;
- }
- }
- if (audio->in[audio->fill_next].used == 0) {
- audplay_buffer_refresh(audio);
- } else {
- pr_info("audio_update_pcm_buf_entry: read cannot keep up\n");
- audio->buf_refresh = 1;
- }
- wake_up(&audio->read_wait);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-
-}
-
-static void audplay_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent) (void *ptr, size_t len))
-{
- struct audio *audio = data;
- uint32_t msg[28];
- getevent(msg, sizeof(msg));
-
- dprintk("audplay_dsp_event: msg_id=%x\n", id);
-
- switch (id) {
- case AUDPLAY_MSG_DEC_NEEDS_DATA:
- audplay_send_data(audio, 1);
- break;
-
- case AUDPLAY_MSG_BUFFER_UPDATE:
- audio_update_pcm_buf_entry(audio, msg);
- break;
-
- default:
- pr_err("unexpected message from decoder \n");
- break;
- }
-}
-
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned status = msg[1];
-
- switch (status) {
- case AUDPP_DEC_STATUS_SLEEP:
- pr_info("decoder status: sleep \n");
- break;
-
- case AUDPP_DEC_STATUS_INIT:
- pr_info("decoder status: init \n");
- audpp_cmd_cfg_routing_mode(audio);
- break;
-
- case AUDPP_DEC_STATUS_CFG:
- pr_info("decoder status: cfg \n");
- break;
- case AUDPP_DEC_STATUS_PLAY:
- pr_info("decoder status: play \n");
- if (audio->pcm_feedback) {
- audplay_config_hostpcm(audio);
- audplay_buffer_refresh(audio);
- }
- break;
- default:
- pr_err("unknown decoder status \n");
- break;
- }
- break;
- }
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- pr_info("audio_dsp_event: CFG_MSG ENABLE\n");
- auddec_dsp_config(audio, 1);
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(audio->dec_id, audio->volume,
- 0);
- audpp_avsync(audio->dec_id, 22050);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- pr_info("audio_dsp_event: CFG_MSG DISABLE\n");
- audpp_avsync(audio->dec_id, 0);
- audio->running = 0;
- } else {
- pr_err("audio_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- pr_info("audio_dsp_event: ROUTING_ACK mode=%d\n", msg[1]);
- audpp_cmd_cfg_adec_params(audio);
- break;
-
- case AUDPP_MSG_FLUSH_ACK:
- dprintk("%s: FLUSH_ACK\n", __func__);
- audio->wflush = 0;
- audio->rflush = 0;
- if (audio->pcm_feedback)
- audplay_buffer_refresh(audio);
- break;
-
- default:
- pr_err("audio_dsp_event: UNKNOWN (%d)\n", id);
- }
-
-}
-
-
-struct msm_adsp_ops audplay_adsp_ops = {
- .event = audplay_dsp_event,
-};
-
-
-#define audplay_send_queue0(audio, cmd, len) \
- msm_adsp_write(audio->audplay, QDSP_uPAudPlay0BitStreamCtrlQueue, \
- cmd, len)
-
-static int auddec_dsp_config(struct audio *audio, int enable)
-{
- audpp_cmd_cfg_dec_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_CFG_DEC_TYPE;
- if (enable)
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_ENA_DEC_V |
- AUDDEC_DEC_MP3;
- else
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_DIS_DEC_V;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_adec_params(struct audio *audio)
-{
- audpp_cmd_cfg_adec_params_mp3 cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.cmd_id = AUDPP_CMD_CFG_ADEC_PARAMS;
- cmd.common.length = AUDPP_CMD_CFG_ADEC_PARAMS_MP3_LEN;
- cmd.common.dec_id = audio->dec_id;
- cmd.common.input_sampling_frequency = audio->out_sample_rate;
-
- audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_routing_mode(struct audio *audio)
-{
- struct audpp_cmd_routing_mode cmd;
- pr_info("audpp_cmd_cfg_routing_mode()\n");
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_ROUTING_MODE;
- cmd.object_number = audio->dec_id;
- if (audio->pcm_feedback)
- cmd.routing_mode = ROUTING_MODE_FTRT;
- else
- cmd.routing_mode = ROUTING_MODE_RT;
-
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static int audplay_dsp_send_data_avail(struct audio *audio,
- unsigned idx, unsigned len)
-{
- audplay_cmd_bitstream_data_avail cmd;
-
- cmd.cmd_id = AUDPLAY_CMD_BITSTREAM_DATA_AVAIL;
- cmd.decoder_id = audio->dec_id;
- cmd.buf_ptr = audio->out[idx].addr;
- cmd.buf_size = len/2;
- cmd.partition_number = 0;
- return audplay_send_queue0(audio, &cmd, sizeof(cmd));
-}
-
-static void audplay_buffer_refresh(struct audio *audio)
-{
- struct audplay_cmd_buffer_refresh refresh_cmd;
-
- refresh_cmd.cmd_id = AUDPLAY_CMD_BUFFER_REFRESH;
- refresh_cmd.num_buffers = 1;
- refresh_cmd.buf0_address = audio->in[audio->fill_next].addr;
- refresh_cmd.buf0_length = audio->in[audio->fill_next].size -
- (audio->in[audio->fill_next].size % 576); /* Mp3 frame size */
- refresh_cmd.buf_read_count = 0;
- pr_info("audplay_buffer_fresh: buf0_addr=%x buf0_len=%d\n",
- refresh_cmd.buf0_address, refresh_cmd.buf0_length);
- (void)audplay_send_queue0(audio, &refresh_cmd, sizeof(refresh_cmd));
-}
-
-static void audplay_config_hostpcm(struct audio *audio)
-{
- struct audplay_cmd_hpcm_buf_cfg cfg_cmd;
-
- pr_info("audplay_config_hostpcm()\n");
- cfg_cmd.cmd_id = AUDPLAY_CMD_HPCM_BUF_CFG;
- cfg_cmd.max_buffers = 1;
- cfg_cmd.byte_swap = 0;
- cfg_cmd.hostpcm_config = (0x8000) | (0x4000);
- cfg_cmd.feedback_frequency = 1;
- cfg_cmd.partition_number = 0;
- (void)audplay_send_queue0(audio, &cfg_cmd, sizeof(cfg_cmd));
-
-}
-
-static void audplay_send_data(struct audio *audio, unsigned needed)
-{
- struct buffer *frame;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (!audio->running)
- goto done;
-
- if (audio->wflush) {
- audio->out_needed = 1;
- goto done;
- }
-
- if (needed && !audio->wflush) {
- /* We were called from the callback because the DSP
- * requested more data. Note that the DSP does want
- * more data, and if a buffer was in-flight, mark it
- * as available (since the DSP must now be done with
- * it).
- */
- audio->out_needed = 1;
- frame = audio->out + audio->out_tail;
- if (frame->used == 0xffffffff) {
- dprintk("frame %d free\n", audio->out_tail);
- frame->used = 0;
- audio->out_tail ^= 1;
- wake_up(&audio->write_wait);
- }
- }
-
- if (audio->out_needed) {
- /* If the DSP currently wants data and we have a
- * buffer available, we will send it and reset
- * the needed flag. We'll mark the buffer as in-flight
- * so that it won't be recycled until the next buffer
- * is requested
- */
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- BUG_ON(frame->used == 0xffffffff);
- dprintk("frame %d busy\n", audio->out_tail);
- audplay_dsp_send_data_avail(audio, audio->out_tail,
- frame->used);
- frame->used = 0xffffffff;
- audio->out_needed = 0;
- }
- }
-done:
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-}
-
-/* ------------------- device --------------------- */
-
-static void audio_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->reserved = 0;
- atomic_set(&audio->out_bytes, 0);
-}
-
-static void audio_flush_pcm_buf(struct audio *audio)
-{
- uint8_t index;
-
- for (index = 0; index < PCM_BUF_MAX_COUNT; index++)
- audio->in[index].used = 0;
-
- audio->read_next = 0;
- audio->fill_next = 0;
-}
-
-static void audio_ioport_reset(struct audio *audio)
-{
- /* Make sure read/write thread are free from
- * sleep and knowing that system is not able
- * to process io request at the moment
- */
- wake_up(&audio->write_wait);
- mutex_lock(&audio->write_lock);
- audio_flush(audio);
- mutex_unlock(&audio->write_lock);
- wake_up(&audio->read_wait);
- mutex_lock(&audio->read_lock);
- audio_flush_pcm_buf(audio);
- mutex_unlock(&audio->read_lock);
-}
-
-static long audio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0;
-
- pr_info("audio_ioctl() cmd = %d\n", cmd);
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = audpp_avsync_byte_count(audio->dec_id);
- stats.sample_count = audpp_avsync_sample_count(audio->dec_id);
- if (copy_to_user((void *) arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(audio->dec_id, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- return 0;
- }
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audio_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audio_disable(audio);
- audio->stopped = 1;
- audio_ioport_reset(audio);
- audio->stopped = 0;
- break;
- case AUDIO_FLUSH:
- dprintk("%s: AUDIO_FLUSH\n", __func__);
- audio->rflush = 1;
- audio->wflush = 1;
- audio_ioport_reset(audio);
- audio->rflush = 0;
- audio->wflush = 0;
-
- if (audio->buf_refresh) {
- audio->buf_refresh = 0;
- audplay_buffer_refresh(audio);
- }
- break;
-
- case AUDIO_SET_CONFIG: {
- struct msm_audio_config config;
- if (copy_from_user(&config, (void *) arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if (config.channel_count == 1) {
- config.channel_count = AUDPP_CMD_PCM_INTF_MONO_V;
- } else if (config.channel_count == 2) {
- config.channel_count = AUDPP_CMD_PCM_INTF_STEREO_V;
- } else {
- rc = -EINVAL;
- break;
- }
- audio->out_sample_rate = config.sample_rate;
- audio->out_channel_mode = config.channel_count;
- rc = 0;
- break;
- }
- case AUDIO_GET_CONFIG: {
- struct msm_audio_config config;
- config.buffer_size = (audio->out_dma_sz >> 1);
- config.buffer_count = 2;
- config.sample_rate = audio->out_sample_rate;
- if (audio->out_channel_mode == AUDPP_CMD_PCM_INTF_MONO_V) {
- config.channel_count = 1;
- } else {
- config.channel_count = 2;
- }
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void *) arg, &config, sizeof(config))) {
- rc = -EFAULT;
- } else {
- rc = 0;
- }
- break;
- }
- case AUDIO_GET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- config.pcm_feedback = 0;
- config.buffer_count = PCM_BUF_MAX_COUNT;
- config.buffer_size = PCM_BUFSZ_MIN;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
- if (copy_from_user
- (&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if ((config.buffer_count > PCM_BUF_MAX_COUNT) ||
- (config.buffer_count == 1))
- config.buffer_count = PCM_BUF_MAX_COUNT;
-
- if (config.buffer_size < PCM_BUFSZ_MIN)
- config.buffer_size = PCM_BUFSZ_MIN;
-
- /* Check if pcm feedback is required */
- if ((config.pcm_feedback) && (!audio->read_data)) {
- pr_info("ioctl: allocate PCM buffer %d\n",
- config.buffer_count *
- config.buffer_size);
- audio->read_data =
- dma_alloc_coherent(NULL,
- config.buffer_size *
- config.buffer_count,
- &audio->read_phys,
- GFP_KERNEL);
- if (!audio->read_data) {
- pr_err("audio_mp3: malloc pcm buf failed\n");
- rc = -1;
- } else {
- uint8_t index;
- uint32_t offset = 0;
- audio->pcm_feedback = 1;
- audio->buf_refresh = 0;
- audio->pcm_buf_count =
- config.buffer_count;
- audio->read_next = 0;
- audio->fill_next = 0;
-
- for (index = 0;
- index < config.buffer_count;
- index++) {
- audio->in[index].data =
- audio->read_data + offset;
- audio->in[index].addr =
- audio->read_phys + offset;
- audio->in[index].size =
- config.buffer_size;
- audio->in[index].used = 0;
- offset += config.buffer_size;
- }
- rc = 0;
- }
- } else {
- rc = 0;
- }
- break;
- }
- case AUDIO_PAUSE:
- dprintk("%s: AUDIO_PAUSE %ld\n", __func__, arg);
- rc = audpp_pause(audio->dec_id, (int) arg);
- break;
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audio_read(struct file *file, char __user *buf, size_t count,
- loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- int rc = 0;
-
- if (!audio->pcm_feedback)
- return 0; /* PCM feedback disabled. Nothing to read */
-
- mutex_lock(&audio->read_lock);
- pr_info("audio_read() %d \n", count);
- while (count > 0) {
- rc = wait_event_interruptible(audio->read_wait,
- (audio->in[audio->read_next].
- used > 0) || (audio->stopped)
- || (audio->rflush));
-
- if (rc < 0)
- break;
-
- if (audio->stopped || audio->rflush) {
- rc = -EBUSY;
- break;
- }
-
- if (count < audio->in[audio->read_next].used) {
- /* Read must happen in frame boundary. Since
- * driver does not know frame size, read count
- * must be greater or equal
- * to size of PCM samples
- */
- pr_info("audio_read: no partial frame done reading\n");
- break;
- } else {
- pr_info("audio_read: read from in[%d]\n",
- audio->read_next);
- if (copy_to_user
- (buf, audio->in[audio->read_next].data,
- audio->in[audio->read_next].used)) {
- pr_err("audio_read: invalid addr %x \n",
- (unsigned int)buf);
- rc = -EFAULT;
- break;
- }
- count -= audio->in[audio->read_next].used;
- buf += audio->in[audio->read_next].used;
- audio->in[audio->read_next].used = 0;
- if ((++audio->read_next) == audio->pcm_buf_count)
- audio->read_next = 0;
- if (audio->in[audio->read_next].used == 0)
- break; /* No data ready at this moment
- * Exit while loop to prevent
- * output thread sleep too long
- */
- }
- }
-
- /* don't feed output buffer to HW decoder during flushing
- * buffer refresh command will be sent once flush completes
- * send buf refresh command here can confuse HW decoder
- */
- if (audio->buf_refresh && !audio->rflush) {
- audio->buf_refresh = 0;
- pr_info("audio_read: kick start pcm feedback again\n");
- audplay_buffer_refresh(audio);
- }
-
- mutex_unlock(&audio->read_lock);
-
- if (buf > start)
- rc = buf - start;
-
- pr_info("audio_read: read %d bytes\n", rc);
- return rc;
-}
-
-static ssize_t audio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- char *cpy_ptr;
- int rc = 0;
- unsigned dsize;
-
- mutex_lock(&audio->write_lock);
- while (count > 0) {
- frame = audio->out + audio->out_head;
- cpy_ptr = frame->data;
- dsize = 0;
- rc = wait_event_interruptible(audio->write_wait,
- (frame->used == 0)
- || (audio->stopped)
- || (audio->wflush));
- if (rc < 0)
- break;
- if (audio->stopped || audio->wflush) {
- rc = -EBUSY;
- break;
- }
-
- if (audio->reserved) {
- dprintk("%s: append reserved byte %x\n",
- __func__, audio->rsv_byte);
- *cpy_ptr = audio->rsv_byte;
- xfer = (count > (frame->size - 1)) ?
- frame->size - 1 : count;
- cpy_ptr++;
- dsize = 1;
- audio->reserved = 0;
- } else
- xfer = (count > frame->size) ? frame->size : count;
-
- if (copy_from_user(cpy_ptr, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
-
- dsize += xfer;
- if (dsize & 1) {
- audio->rsv_byte = ((char *) frame->data)[dsize - 1];
- dprintk("%s: odd length buf reserve last byte %x\n",
- __func__, audio->rsv_byte);
- audio->reserved = 1;
- dsize--;
- }
- count -= xfer;
- buf += xfer;
-
- if (dsize > 0) {
- audio->out_head ^= 1;
- frame->used = dsize;
- audplay_send_data(audio, 0);
- }
- }
- mutex_unlock(&audio->write_lock);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audio_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- dprintk("audio_release()\n");
-
- mutex_lock(&audio->lock);
- audio_disable(audio);
- audio_flush(audio);
- audio_flush_pcm_buf(audio);
- msm_adsp_put(audio->audplay);
- audio->audplay = NULL;
- audio->opened = 0;
- audio->reserved = 0;
- dma_free_coherent(NULL, audio->out_dma_sz, audio->data, audio->phys);
- audio->data = NULL;
- if (audio->read_data != NULL) {
- dma_free_coherent(NULL,
- audio->in[0].size * audio->pcm_buf_count,
- audio->read_data, audio->read_phys);
- audio->read_data = NULL;
- }
- audio->pcm_feedback = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio the_mp3_audio;
-
-static int audio_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_mp3_audio;
- int rc;
- unsigned pmem_sz;
-
- mutex_lock(&audio->lock);
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- rc = -EBUSY;
- goto done;
- }
-
- pmem_sz = DMASZ_MAX;
-
- while (pmem_sz >= DMASZ_MIN) {
- audio->data = dma_alloc_coherent(NULL, pmem_sz,
- &audio->phys, GFP_KERNEL);
- if (audio->data)
- break;
- else if (pmem_sz == DMASZ_MIN) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto done;
- } else
- pmem_sz >>= 1;
- }
-
- dprintk("%s: allocated %d bytes DMA buffer\n", __func__, pmem_sz);
-
- rc = audmgr_open(&audio->audmgr);
- if (rc) {
- dma_free_coherent(NULL, pmem_sz,
- audio->data, audio->phys);
- goto done;
- }
-
- rc = msm_adsp_get("AUDPLAY0TASK", &audio->audplay, &audplay_adsp_ops,
- audio);
- if (rc) {
- pr_err("audio: failed to get audplay0 dsp module\n");
- dma_free_coherent(NULL, pmem_sz,
- audio->data, audio->phys);
- audmgr_close(&audio->audmgr);
- goto done;
- }
-
- audio->out_dma_sz = pmem_sz;
- pmem_sz >>= 1; /* Shift by 1 to get size of ping pong buffer */
-
- audio->out_sample_rate = 44100;
- audio->out_channel_mode = AUDPP_CMD_PCM_INTF_STEREO_V;
- audio->dec_id = 0;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = pmem_sz;
-
- audio->out[1].data = audio->data + pmem_sz;
- audio->out[1].addr = audio->phys + pmem_sz;
- audio->out[1].size = pmem_sz;
-
- audio->volume = 0x2000; /* equal to Q13 number 1.0 Unit Gain */
-
- audio_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
-done:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static struct file_operations audio_mp3_fops = {
- .owner = THIS_MODULE,
- .open = audio_open,
- .release = audio_release,
- .read = audio_read,
- .write = audio_write,
- .unlocked_ioctl = audio_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_mp3_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_mp3",
- .fops = &audio_mp3_fops,
-};
-
-static int __init audio_init(void)
-{
- mutex_init(&the_mp3_audio.lock);
- mutex_init(&the_mp3_audio.write_lock);
- mutex_init(&the_mp3_audio.read_lock);
- spin_lock_init(&the_mp3_audio.dsp_lock);
- init_waitqueue_head(&the_mp3_audio.write_wait);
- init_waitqueue_head(&the_mp3_audio.read_wait);
- the_mp3_audio.read_data = NULL;
- return misc_register(&audio_mp3_misc);
-}
-
-device_initcall(audio_init);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audio_out.c
- *
- * pcm audio output device
- *
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/wakelock.h>
-#include <linux/gfp.h>
-
-#include <linux/msm_audio.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-
-#include "evlog.h"
-
-#define LOG_AUDIO_EVENTS 1
-#define LOG_AUDIO_FAULTS 0
-
-enum {
- EV_NULL,
- EV_OPEN,
- EV_WRITE,
- EV_RETURN,
- EV_IOCTL,
- EV_WRITE_WAIT,
- EV_WAIT_EVENT,
- EV_FILL_BUFFER,
- EV_SEND_BUFFER,
- EV_DSP_EVENT,
- EV_ENABLE,
-};
-
-#if (LOG_AUDIO_EVENTS != 1)
-static inline void LOG(unsigned id, unsigned arg) {}
-#else
-static const char *pcm_log_strings[] = {
- "NULL",
- "OPEN",
- "WRITE",
- "RETURN",
- "IOCTL",
- "WRITE_WAIT",
- "WAIT_EVENT",
- "FILL_BUFFER",
- "SEND_BUFFER",
- "DSP_EVENT",
- "ENABLE",
-};
-
-DECLARE_LOG(pcm_log, 64, pcm_log_strings);
-
-static int __init _pcm_log_init(void)
-{
- return ev_log_init(&pcm_log);
-}
-module_init(_pcm_log_init);
-
-#define LOG(id,arg) ev_log_write(&pcm_log, id, arg)
-#endif
-
-
-
-
-
-#define BUFSZ (960 * 5)
-#define DMASZ (BUFSZ * 2)
-
-#define AUDPP_CMD_CFG_OBJ_UPDATE 0x8000
-#define AUDPP_CMD_EQ_FLAG_DIS 0x0000
-#define AUDPP_CMD_EQ_FLAG_ENA -1
-#define AUDPP_CMD_IIR_FLAG_DIS 0x0000
-#define AUDPP_CMD_IIR_FLAG_ENA -1
-
-#define AUDPP_CMD_IIR_TUNING_FILTER 1
-#define AUDPP_CMD_EQUALIZER 2
-#define AUDPP_CMD_ADRC 3
-
-#define ADRC_ENABLE 0x0001
-#define EQ_ENABLE 0x0002
-#define IIR_ENABLE 0x0004
-
-struct adrc_filter {
- uint16_t compression_th;
- uint16_t compression_slope;
- uint16_t rms_time;
- uint16_t attack_const_lsw;
- uint16_t attack_const_msw;
- uint16_t release_const_lsw;
- uint16_t release_const_msw;
- uint16_t adrc_system_delay;
-};
-
-struct eqalizer {
- uint16_t num_bands;
- uint16_t eq_params[132];
-};
-
-struct rx_iir_filter {
- uint16_t num_bands;
- uint16_t iir_params[48];
-};
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- uint16_t eq_flag;
- uint16_t num_bands;
- uint16_t eq_params[132];
-} audpp_cmd_cfg_object_params_eq;
-
-typedef struct {
- audpp_cmd_cfg_object_params_common common;
- uint16_t active_flag;
- uint16_t num_bands;
- uint16_t iir_params[48];
-} audpp_cmd_cfg_object_params_rx_iir;
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used;
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[2];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
-
- atomic_t out_bytes;
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t wait;
-
- /* configuration to use on next enable */
- uint32_t out_sample_rate;
- uint32_t out_channel_mode;
- uint32_t out_weight;
- uint32_t out_buffer_size;
-
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- int opened;
- int enabled;
- int running;
- int stopped; /* set when stopped, cleared on flush */
- unsigned volume;
-
- int adrc_enable;
- struct adrc_filter adrc;
-
- int eq_enable;
- struct eqalizer eq;
-
- int rx_iir_enable;
- struct rx_iir_filter iir;
-};
-
-static void audio_prevent_sleep(struct audio *audio)
-{
- printk(KERN_INFO "++++++++++++++++++++++++++++++\n");
-}
-
-static void audio_allow_sleep(struct audio *audio)
-{
- printk(KERN_INFO "------------------------------\n");
-}
-
-static int audio_dsp_out_enable(struct audio *audio, int yes);
-static int audio_dsp_send_buffer(struct audio *audio, unsigned id, unsigned len);
-static int audio_dsp_set_adrc(struct audio *audio);
-static int audio_dsp_set_eq(struct audio *audio);
-static int audio_dsp_set_rx_iir(struct audio *audio);
-
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg);
-
-/* must be called with audio->lock held */
-static int audio_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- pr_info("audio_enable()\n");
-
- if (audio->enabled)
- return 0;
-
- /* refuse to start if we're not ready */
- if (!audio->out[0].used || !audio->out[1].used)
- return -EIO;
-
- /* we start buffers 0 and 1, so buffer 0 will be the
- * next one the dsp will want
- */
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_HOST_PCM;
- cfg.codec = RPC_AUD_DEF_CODEC_PCM;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- audio_prevent_sleep(audio);
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0) {
- audio_allow_sleep(audio);
- return rc;
- }
-
- if (audpp_enable(-1, audio_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- audmgr_disable(&audio->audmgr);
- audio_allow_sleep(audio);
- return -ENODEV;
- }
-
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audio_disable(struct audio *audio)
-{
- pr_info("audio_disable()\n");
- if (audio->enabled) {
- audio->enabled = 0;
- audio_dsp_out_enable(audio, 0);
-
- audpp_disable(-1, audio);
-
- wake_up(&audio->wait);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- audio_allow_sleep(audio);
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audio_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
- struct buffer *frame;
- unsigned long flags;
-
- LOG(EV_DSP_EVENT, id);
- switch (id) {
- case AUDPP_MSG_HOST_PCM_INTF_MSG: {
- unsigned id = msg[2];
- unsigned idx = msg[3] - 1;
-
- /* pr_info("audio_dsp_event: HOST_PCM id %d idx %d\n", id, idx); */
- if (id != AUDPP_MSG_HOSTPCM_ID_ARM_RX) {
- pr_err("bogus id\n");
- break;
- }
- if (idx > 1) {
- pr_err("bogus buffer idx\n");
- break;
- }
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (audio->running) {
- atomic_add(audio->out[idx].used, &audio->out_bytes);
- audio->out[idx].used = 0;
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- audio_dsp_send_buffer(
- audio, audio->out_tail, frame->used);
- audio->out_tail ^= 1;
- } else {
- audio->out_needed++;
- }
- wake_up(&audio->wait);
- }
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- break;
- }
- case AUDPP_MSG_PCMDMAMISSED:
- pr_info("audio_dsp_event: PCMDMAMISSED %d\n", msg[0]);
- break;
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- LOG(EV_ENABLE, 1);
- pr_info("audio_dsp_event: CFG_MSG ENABLE\n");
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(5, audio->volume, 0);
- audio_dsp_set_adrc(audio);
- audio_dsp_set_eq(audio);
- audio_dsp_set_rx_iir(audio);
- audio_dsp_out_enable(audio, 1);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- LOG(EV_ENABLE, 0);
- pr_info("audio_dsp_event: CFG_MSG DISABLE\n");
- audio->running = 0;
- } else {
- pr_err("audio_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- default:
- pr_err("audio_dsp_event: UNKNOWN (%d)\n", id);
- }
-}
-
-static int audio_dsp_out_enable(struct audio *audio, int yes)
-{
- audpp_cmd_pcm_intf cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_PCM_INTF_2;
- cmd.object_num = AUDPP_CMD_PCM_INTF_OBJECT_NUM;
- cmd.config = AUDPP_CMD_PCM_INTF_CONFIG_CMD_V;
- cmd.intf_type = AUDPP_CMD_PCM_INTF_RX_ENA_ARMTODSP_V;
-
- if (yes) {
- cmd.write_buf1LSW = audio->out[0].addr;
- cmd.write_buf1MSW = audio->out[0].addr >> 16;
- cmd.write_buf1_len = audio->out[0].size;
- cmd.write_buf2LSW = audio->out[1].addr;
- cmd.write_buf2MSW = audio->out[1].addr >> 16;
- cmd.write_buf2_len = audio->out[1].size;
- cmd.arm_to_rx_flag = AUDPP_CMD_PCM_INTF_ENA_V;
- cmd.weight_decoder_to_rx = audio->out_weight;
- cmd.weight_arm_to_rx = 1;
- cmd.partition_number_arm_to_dsp = 0;
- cmd.sample_rate = audio->out_sample_rate;
- cmd.channel_mode = audio->out_channel_mode;
- }
-
- return audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static int audio_dsp_send_buffer(struct audio *audio, unsigned idx, unsigned len)
-{
- audpp_cmd_pcm_intf_send_buffer cmd;
-
- cmd.cmd_id = AUDPP_CMD_PCM_INTF_2;
- cmd.host_pcm_object = AUDPP_CMD_PCM_INTF_OBJECT_NUM;
- cmd.config = AUDPP_CMD_PCM_INTF_BUFFER_CMD_V;
- cmd.intf_type = AUDPP_CMD_PCM_INTF_RX_ENA_ARMTODSP_V;
- cmd.dsp_to_arm_buf_id = 0;
- cmd.arm_to_dsp_buf_id = idx + 1;
- cmd.arm_to_dsp_buf_len = len;
-
- LOG(EV_SEND_BUFFER, idx);
- return audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static int audio_dsp_set_adrc(struct audio *audio)
-{
- audpp_cmd_cfg_object_params_adrc cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.comman_cfg = AUDPP_CMD_CFG_OBJ_UPDATE;
- cmd.common.command_type = AUDPP_CMD_ADRC;
-
- if (audio->adrc_enable) {
- cmd.adrc_flag = AUDPP_CMD_ADRC_FLAG_ENA;
- cmd.compression_th = audio->adrc.compression_th;
- cmd.compression_slope = audio->adrc.compression_slope;
- cmd.rms_time = audio->adrc.rms_time;
- cmd.attack_const_lsw = audio->adrc.attack_const_lsw;
- cmd.attack_const_msw = audio->adrc.attack_const_msw;
- cmd.release_const_lsw = audio->adrc.release_const_lsw;
- cmd.release_const_msw = audio->adrc.release_const_msw;
- cmd.adrc_system_delay = audio->adrc.adrc_system_delay;
- } else {
- cmd.adrc_flag = AUDPP_CMD_ADRC_FLAG_DIS;
- }
- return audpp_send_queue3(&cmd, sizeof(cmd));
-}
-
-static int audio_dsp_set_eq(struct audio *audio)
-{
- audpp_cmd_cfg_object_params_eq cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.comman_cfg = AUDPP_CMD_CFG_OBJ_UPDATE;
- cmd.common.command_type = AUDPP_CMD_EQUALIZER;
-
- if (audio->eq_enable) {
- cmd.eq_flag = AUDPP_CMD_EQ_FLAG_ENA;
- cmd.num_bands = audio->eq.num_bands;
- memcpy(&cmd.eq_params, audio->eq.eq_params,
- sizeof(audio->eq.eq_params));
- } else {
- cmd.eq_flag = AUDPP_CMD_EQ_FLAG_DIS;
- }
- return audpp_send_queue3(&cmd, sizeof(cmd));
-}
-
-static int audio_dsp_set_rx_iir(struct audio *audio)
-{
- audpp_cmd_cfg_object_params_rx_iir cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.comman_cfg = AUDPP_CMD_CFG_OBJ_UPDATE;
- cmd.common.command_type = AUDPP_CMD_IIR_TUNING_FILTER;
-
- if (audio->rx_iir_enable) {
- cmd.active_flag = AUDPP_CMD_IIR_FLAG_ENA;
- cmd.num_bands = audio->iir.num_bands;
- memcpy(&cmd.iir_params, audio->iir.iir_params,
- sizeof(audio->iir.iir_params));
- } else {
- cmd.active_flag = AUDPP_CMD_IIR_FLAG_DIS;
- }
-
- return audpp_send_queue3(&cmd, sizeof(cmd));
-}
-
-/* ------------------- device --------------------- */
-
-static int audio_enable_adrc(struct audio *audio, int enable)
-{
- if (audio->adrc_enable != enable) {
- audio->adrc_enable = enable;
- if (audio->running)
- audio_dsp_set_adrc(audio);
- }
- return 0;
-}
-
-static int audio_enable_eq(struct audio *audio, int enable)
-{
- if (audio->eq_enable != enable) {
- audio->eq_enable = enable;
- if (audio->running)
- audio_dsp_set_eq(audio);
- }
- return 0;
-}
-
-static int audio_enable_rx_iir(struct audio *audio, int enable)
-{
- if (audio->rx_iir_enable != enable) {
- audio->rx_iir_enable = enable;
- if (audio->running)
- audio_dsp_set_rx_iir(audio);
- }
- return 0;
-}
-
-static void audio_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->stopped = 0;
-}
-
-static long audio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc;
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = atomic_read(&audio->out_bytes);
- if (copy_to_user((void*) arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(6, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- }
-
- LOG(EV_IOCTL, cmd);
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audio_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audio_disable(audio);
- audio->stopped = 1;
- break;
- case AUDIO_FLUSH:
- if (audio->stopped) {
- /* Make sure we're stopped and we wake any threads
- * that might be blocked holding the write_lock.
- * While audio->stopped write threads will always
- * exit immediately.
- */
- wake_up(&audio->wait);
- mutex_lock(&audio->write_lock);
- audio_flush(audio);
- mutex_unlock(&audio->write_lock);
- }
- case AUDIO_SET_CONFIG: {
- struct msm_audio_config config;
- if (copy_from_user(&config, (void*) arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if (config.channel_count == 1) {
- config.channel_count = AUDPP_CMD_PCM_INTF_MONO_V;
- } else if (config.channel_count == 2) {
- config.channel_count= AUDPP_CMD_PCM_INTF_STEREO_V;
- } else {
- rc = -EINVAL;
- break;
- }
- audio->out_sample_rate = config.sample_rate;
- audio->out_channel_mode = config.channel_count;
- rc = 0;
- break;
- }
- case AUDIO_GET_CONFIG: {
- struct msm_audio_config config;
- config.buffer_size = BUFSZ;
- config.buffer_count = 2;
- config.sample_rate = audio->out_sample_rate;
- if (audio->out_channel_mode == AUDPP_CMD_PCM_INTF_MONO_V) {
- config.channel_count = 1;
- } else {
- config.channel_count = 2;
- }
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void*) arg, &config, sizeof(config))) {
- rc = -EFAULT;
- } else {
- rc = 0;
- }
- break;
- }
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audio_read(struct file *file, char __user *buf, size_t count, loff_t *pos)
-{
- return -EINVAL;
-}
-
-static inline int rt_policy(int policy)
-{
- if (unlikely(policy == SCHED_FIFO) || unlikely(policy == SCHED_RR))
- return 1;
- return 0;
-}
-
-static inline int task_has_rt_policy(struct task_struct *p)
-{
- return rt_policy(p->policy);
-}
-
-static ssize_t audio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct sched_param s = { .sched_priority = 1 };
- struct audio *audio = file->private_data;
- unsigned long flags;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- int old_prio = current->rt_priority;
- int old_policy = current->policy;
- int cap_nice = cap_raised(current_cap(), CAP_SYS_NICE);
- int rc = 0;
-
- LOG(EV_WRITE, count | (audio->running << 28) | (audio->stopped << 24));
-
- /* just for this write, set us real-time */
- if (!task_has_rt_policy(current)) {
- struct cred *new = prepare_creds();
- cap_raise(new->cap_effective, CAP_SYS_NICE);
- commit_creds(new);
- sched_setscheduler(current, SCHED_RR, &s);
- }
-
- mutex_lock(&audio->write_lock);
- while (count > 0) {
- frame = audio->out + audio->out_head;
-
- LOG(EV_WAIT_EVENT, 0);
- rc = wait_event_interruptible(audio->wait,
- (frame->used == 0) || (audio->stopped));
- LOG(EV_WAIT_EVENT, 1);
-
- if (rc < 0)
- break;
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
- xfer = count > frame->size ? frame->size : count;
- if (copy_from_user(frame->data, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
- frame->used = xfer;
- audio->out_head ^= 1;
- count -= xfer;
- buf += xfer;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- LOG(EV_FILL_BUFFER, audio->out_head ^ 1);
- frame = audio->out + audio->out_tail;
- if (frame->used && audio->out_needed) {
- audio_dsp_send_buffer(audio, audio->out_tail, frame->used);
- audio->out_tail ^= 1;
- audio->out_needed--;
- }
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- }
-
- mutex_unlock(&audio->write_lock);
-
- /* restore scheduling policy and priority */
- if (!rt_policy(old_policy)) {
- struct sched_param v = { .sched_priority = old_prio };
- sched_setscheduler(current, old_policy, &v);
- if (likely(!cap_nice)) {
- struct cred *new = prepare_creds();
- cap_lower(new->cap_effective, CAP_SYS_NICE);
- commit_creds(new);
- sched_setscheduler(current, SCHED_RR, &s);
- }
- }
-
- LOG(EV_RETURN,(buf > start) ? (buf - start) : rc);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audio_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- LOG(EV_OPEN, 0);
- mutex_lock(&audio->lock);
- audio_disable(audio);
- audio_flush(audio);
- audio->opened = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static struct audio the_audio;
-
-static int audio_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_audio;
- int rc;
-
- mutex_lock(&audio->lock);
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- rc = -EBUSY;
- goto done;
- }
-
- if (!audio->data) {
- audio->data = dma_alloc_coherent(NULL, DMASZ,
- &audio->phys, GFP_KERNEL);
- if (!audio->data) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto done;
- }
- }
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto done;
-
- audio->out_buffer_size = BUFSZ;
- audio->out_sample_rate = 44100;
- audio->out_channel_mode = AUDPP_CMD_PCM_INTF_STEREO_V;
- audio->out_weight = 100;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = BUFSZ;
-
- audio->out[1].data = audio->data + BUFSZ;
- audio->out[1].addr = audio->phys + BUFSZ;
- audio->out[1].size = BUFSZ;
-
- audio->volume = 0x2000;
-
- audio_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
- LOG(EV_OPEN, 1);
-done:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static long audpp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0, enable;
- uint16_t enable_mask;
-
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_ENABLE_AUDPP:
- if (copy_from_user(&enable_mask, (void *) arg, sizeof(enable_mask)))
- goto out_fault;
-
- enable = (enable_mask & ADRC_ENABLE)? 1 : 0;
- audio_enable_adrc(audio, enable);
- enable = (enable_mask & EQ_ENABLE)? 1 : 0;
- audio_enable_eq(audio, enable);
- enable = (enable_mask & IIR_ENABLE)? 1 : 0;
- audio_enable_rx_iir(audio, enable);
- break;
-
- case AUDIO_SET_ADRC:
- if (copy_from_user(&audio->adrc, (void*) arg, sizeof(audio->adrc)))
- goto out_fault;
- break;
-
- case AUDIO_SET_EQ:
- if (copy_from_user(&audio->eq, (void*) arg, sizeof(audio->eq)))
- goto out_fault;
- break;
-
- case AUDIO_SET_RX_IIR:
- if (copy_from_user(&audio->iir, (void*) arg, sizeof(audio->iir)))
- goto out_fault;
- break;
-
- default:
- rc = -EINVAL;
- }
-
- goto out;
-
- out_fault:
- rc = -EFAULT;
- out:
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static int audpp_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_audio;
-
- file->private_data = audio;
- return 0;
-}
-
-static struct file_operations audio_fops = {
- .owner = THIS_MODULE,
- .open = audio_open,
- .release = audio_release,
- .read = audio_read,
- .write = audio_write,
- .unlocked_ioctl = audio_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct file_operations audpp_fops = {
- .owner = THIS_MODULE,
- .open = audpp_open,
- .unlocked_ioctl = audpp_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_pcm_out",
- .fops = &audio_fops,
-};
-
-struct miscdevice audpp_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_pcm_ctl",
- .fops = &audpp_fops,
-};
-
-static int __init audio_init(void)
-{
- mutex_init(&the_audio.lock);
- mutex_init(&the_audio.write_lock);
- spin_lock_init(&the_audio.dsp_lock);
- init_waitqueue_head(&the_audio.wait);
- return (misc_register(&audio_misc) || misc_register(&audpp_misc));
-}
-
-device_initcall(audio_init);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audio_qcelp.c
- *
- * qcelp 13k audio decoder device
- *
- * Copyright (c) 2008 QUALCOMM USA, INC.
- *
- * This code is based in part on audio_mp3.c, which is
- * Copyright (C) 2008 Google, Inc.
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- * See the GNU General Public License for more details.
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, you can find it at http://www.fsf.org.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-#include <linux/msm_audio.h>
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-#include <mach/qdsp5/qdsp5audplaycmdi.h>
-#include <mach/qdsp5/qdsp5audplaymsg.h>
-
-#include "audmgr.h"
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-#ifdef DEBUG
-#define dprintk(format, arg...) \
-printk(KERN_DEBUG format, ## arg)
-#else
-#define dprintk(format, arg...) do {} while (0)
-#endif
-
-#define BUFSZ 1080 /* QCELP 13K Hold 600ms packet data = 36 * 30 */
-#define BUF_COUNT 2
-#define DMASZ (BUFSZ * BUF_COUNT)
-
-#define PCM_BUFSZ_MIN 1600 /* 100ms worth of data */
-#define PCM_BUF_MAX_COUNT 5
-
-#define AUDDEC_DEC_QCELP 9
-
-#define ROUTING_MODE_FTRT 1
-#define ROUTING_MODE_RT 2
-/* Decoder status received from AUDPPTASK */
-#define AUDPP_DEC_STATUS_SLEEP 0
-#define AUDPP_DEC_STATUS_INIT 1
-#define AUDPP_DEC_STATUS_CFG 2
-#define AUDPP_DEC_STATUS_PLAY 3
-
-struct buffer {
- void *data;
- unsigned size;
- unsigned used; /* Input usage actual DSP produced PCM size */
- unsigned addr;
-};
-
-struct audio {
- struct buffer out[BUF_COUNT];
-
- spinlock_t dsp_lock;
-
- uint8_t out_head;
- uint8_t out_tail;
- uint8_t out_needed; /* number of buffers the dsp is waiting for */
-
- struct mutex lock;
- struct mutex write_lock;
- wait_queue_head_t write_wait;
-
- /* Host PCM section - START */
- struct buffer in[PCM_BUF_MAX_COUNT];
- struct mutex read_lock;
- wait_queue_head_t read_wait; /* Wait queue for read */
- char *read_data; /* pointer to reader buffer */
- dma_addr_t read_phys; /* physical address of reader buffer */
- uint8_t read_next; /* index to input buffers to be read next */
- uint8_t fill_next; /* index to buffer that DSP should be filling */
- uint8_t pcm_buf_count; /* number of pcm buffer allocated */
- /* Host PCM section - END */
-
- struct msm_adsp_module *audplay;
-
- struct audmgr audmgr;
-
- /* data allocated for various buffers */
- char *data;
- dma_addr_t phys;
-
- uint8_t opened:1;
- uint8_t enabled:1;
- uint8_t running:1;
- uint8_t stopped:1; /* set when stopped, cleared on flush */
- uint8_t pcm_feedback:1; /* set when non-tunnel mode */
- uint8_t buf_refresh:1;
-
- unsigned volume;
-
- uint16_t dec_id;
-};
-
-static struct audio the_qcelp_audio;
-
-static int auddec_dsp_config(struct audio *audio, int enable);
-static void audpp_cmd_cfg_adec_params(struct audio *audio);
-static void audpp_cmd_cfg_routing_mode(struct audio *audio);
-static void audqcelp_send_data(struct audio *audio, unsigned needed);
-static void audqcelp_config_hostpcm(struct audio *audio);
-static void audqcelp_buffer_refresh(struct audio *audio);
-static void audqcelp_dsp_event(void *private, unsigned id, uint16_t *msg);
-
-/* must be called with audio->lock held */
-static int audqcelp_enable(struct audio *audio)
-{
- struct audmgr_config cfg;
- int rc;
-
- dprintk("audqcelp_enable()\n");
-
- if (audio->enabled)
- return 0;
-
- audio->out_tail = 0;
- audio->out_needed = 0;
-
- cfg.tx_rate = RPC_AUD_DEF_SAMPLE_RATE_NONE;
- cfg.rx_rate = RPC_AUD_DEF_SAMPLE_RATE_48000;
- cfg.def_method = RPC_AUD_DEF_METHOD_PLAYBACK;
- cfg.codec = RPC_AUD_DEF_CODEC_13K;
- cfg.snd_method = RPC_SND_METHOD_MIDI;
-
- rc = audmgr_enable(&audio->audmgr, &cfg);
- if (rc < 0)
- return rc;
-
- if (msm_adsp_enable(audio->audplay)) {
- pr_err("audio: msm_adsp_enable(audplay) failed\n");
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
-
- if (audpp_enable(audio->dec_id, audqcelp_dsp_event, audio)) {
- pr_err("audio: audpp_enable() failed\n");
- msm_adsp_disable(audio->audplay);
- audmgr_disable(&audio->audmgr);
- return -ENODEV;
- }
- audio->enabled = 1;
- return 0;
-}
-
-/* must be called with audio->lock held */
-static int audqcelp_disable(struct audio *audio)
-{
- dprintk("audqcelp_disable()\n");
- if (audio->enabled) {
- audio->enabled = 0;
- auddec_dsp_config(audio, 0);
- wake_up(&audio->write_wait);
- wake_up(&audio->read_wait);
- msm_adsp_disable(audio->audplay);
- audpp_disable(audio->dec_id, audio);
- audmgr_disable(&audio->audmgr);
- audio->out_needed = 0;
- }
- return 0;
-}
-
-/* ------------------- dsp --------------------- */
-static void audqcelp_update_pcm_buf_entry(struct audio *audio,
- uint32_t *payload)
-{
- uint8_t index;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- for (index = 0; index < payload[1]; index++) {
- if (audio->in[audio->fill_next].addr ==
- payload[2 + index * 2]) {
- dprintk("audqcelp_update_pcm_buf_entry: in[%d] ready\n",
- audio->fill_next);
- audio->in[audio->fill_next].used =
- payload[3 + index * 2];
- if ((++audio->fill_next) == audio->pcm_buf_count)
- audio->fill_next = 0;
- } else {
- pr_err(
- "audqcelp_update_pcm_buf_entry: expected=%x ret=%x\n",
- audio->in[audio->fill_next].addr,
- payload[1 + index * 2]);
- break;
- }
- }
- if (audio->in[audio->fill_next].used == 0) {
- audqcelp_buffer_refresh(audio);
- } else {
- dprintk("audqcelp_update_pcm_buf_entry: read cannot keep up\n");
- audio->buf_refresh = 1;
- }
-
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- wake_up(&audio->read_wait);
-}
-
-static void audplay_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent) (void *ptr, size_t len))
-{
- struct audio *audio = data;
- uint32_t msg[28];
- getevent(msg, sizeof(msg));
-
- dprintk("audplay_dsp_event: msg_id=%x\n", id);
-
- switch (id) {
- case AUDPLAY_MSG_DEC_NEEDS_DATA:
- audqcelp_send_data(audio, 1);
- break;
-
- case AUDPLAY_MSG_BUFFER_UPDATE:
- audqcelp_update_pcm_buf_entry(audio, msg);
- break;
-
- default:
- pr_err("unexpected message from decoder \n");
- }
-}
-
-static void audqcelp_dsp_event(void *private, unsigned id, uint16_t *msg)
-{
- struct audio *audio = private;
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned status = msg[1];
-
- switch (status) {
- case AUDPP_DEC_STATUS_SLEEP:
- dprintk("decoder status: sleep \n");
- break;
-
- case AUDPP_DEC_STATUS_INIT:
- dprintk("decoder status: init \n");
- audpp_cmd_cfg_routing_mode(audio);
- break;
-
- case AUDPP_DEC_STATUS_CFG:
- dprintk("decoder status: cfg \n");
- break;
- case AUDPP_DEC_STATUS_PLAY:
- dprintk("decoder status: play \n");
- if (audio->pcm_feedback) {
- audqcelp_config_hostpcm(audio);
- audqcelp_buffer_refresh(audio);
- }
- break;
- default:
- pr_err("unknown decoder status \n");
- }
- break;
- }
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- dprintk("audqcelp_dsp_event: CFG_MSG ENABLE\n");
- auddec_dsp_config(audio, 1);
- audio->out_needed = 0;
- audio->running = 1;
- audpp_set_volume_and_pan(audio->dec_id, audio->volume,
- 0);
- audpp_avsync(audio->dec_id, 22050);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- dprintk("audqcelp_dsp_event: CFG_MSG DISABLE\n");
- audpp_avsync(audio->dec_id, 0);
- audio->running = 0;
- } else {
- pr_err("audqcelp_dsp_event: CFG_MSG %d?\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- dprintk("audqcelp_dsp_event: ROUTING_ACK mode=%d\n", msg[1]);
- audpp_cmd_cfg_adec_params(audio);
- break;
- default:
- pr_err("audqcelp_dsp_event: UNKNOWN (%d)\n", id);
- }
-
-}
-
-struct msm_adsp_ops audplay_adsp_ops_qcelp = {
- .event = audplay_dsp_event,
-};
-
-#define audplay_send_queue0(audio, cmd, len) \
- msm_adsp_write(audio->audplay, QDSP_uPAudPlay0BitStreamCtrlQueue, \
- cmd, len)
-
-static int auddec_dsp_config(struct audio *audio, int enable)
-{
- audpp_cmd_cfg_dec_type cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_CFG_DEC_TYPE;
- if (enable)
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC |
- AUDPP_CMD_ENA_DEC_V | AUDDEC_DEC_QCELP;
- else
- cmd.dec0_cfg = AUDPP_CMD_UPDATDE_CFG_DEC | AUDPP_CMD_DIS_DEC_V;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_adec_params(struct audio *audio)
-{
- struct audpp_cmd_cfg_adec_params_v13k cmd;
-
- memset(&cmd, 0, sizeof(cmd));
- cmd.common.cmd_id = AUDPP_CMD_CFG_ADEC_PARAMS;
- cmd.common.length = AUDPP_CMD_CFG_ADEC_PARAMS_V13K_LEN;
- cmd.common.dec_id = audio->dec_id;
- cmd.common.input_sampling_frequency = 8000;
- cmd.stereo_cfg = AUDPP_CMD_PCM_INTF_MONO_V;
-
- audpp_send_queue2(&cmd, sizeof(cmd));
-}
-
-static void audpp_cmd_cfg_routing_mode(struct audio *audio)
-{
- struct audpp_cmd_routing_mode cmd;
- dprintk("audpp_cmd_cfg_routing_mode()\n");
- memset(&cmd, 0, sizeof(cmd));
- cmd.cmd_id = AUDPP_CMD_ROUTING_MODE;
- cmd.object_number = audio->dec_id;
- if (audio->pcm_feedback)
- cmd.routing_mode = ROUTING_MODE_FTRT;
- else
- cmd.routing_mode = ROUTING_MODE_RT;
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static int audplay_dsp_send_data_avail(struct audio *audio,
- unsigned idx, unsigned len)
-{
- audplay_cmd_bitstream_data_avail cmd;
-
- cmd.cmd_id = AUDPLAY_CMD_BITSTREAM_DATA_AVAIL;
- cmd.decoder_id = audio->dec_id;
- cmd.buf_ptr = audio->out[idx].addr;
- cmd.buf_size = len / 2;
- cmd.partition_number = 0;
- return audplay_send_queue0(audio, &cmd, sizeof(cmd));
-}
-
-static void audqcelp_buffer_refresh(struct audio *audio)
-{
- struct audplay_cmd_buffer_refresh refresh_cmd;
-
- refresh_cmd.cmd_id = AUDPLAY_CMD_BUFFER_REFRESH;
- refresh_cmd.num_buffers = 1;
- refresh_cmd.buf0_address = audio->in[audio->fill_next].addr;
- refresh_cmd.buf0_length = audio->in[audio->fill_next].size;
- refresh_cmd.buf_read_count = 0;
- dprintk("audplay_buffer_fresh: buf0_addr=%x buf0_len=%d\n",
- refresh_cmd.buf0_address, refresh_cmd.buf0_length);
-
- (void)audplay_send_queue0(audio, &refresh_cmd, sizeof(refresh_cmd));
-}
-
-static void audqcelp_config_hostpcm(struct audio *audio)
-{
- struct audplay_cmd_hpcm_buf_cfg cfg_cmd;
-
- dprintk("audqcelp_config_hostpcm()\n");
- cfg_cmd.cmd_id = AUDPLAY_CMD_HPCM_BUF_CFG;
- cfg_cmd.max_buffers = audio->pcm_buf_count;
- cfg_cmd.byte_swap = 0;
- cfg_cmd.hostpcm_config = (0x8000) | (0x4000);
- cfg_cmd.feedback_frequency = 1;
- cfg_cmd.partition_number = 0;
-
- (void)audplay_send_queue0(audio, &cfg_cmd, sizeof(cfg_cmd));
-}
-
-static void audqcelp_send_data(struct audio *audio, unsigned needed)
-{
- struct buffer *frame;
- unsigned long flags;
-
- spin_lock_irqsave(&audio->dsp_lock, flags);
- if (!audio->running)
- goto done;
-
- if (needed) {
- /* We were called from the callback because the DSP
- * requested more data. Note that the DSP does want
- * more data, and if a buffer was in-flight, mark it
- * as available (since the DSP must now be done with
- * it).
- */
- audio->out_needed = 1;
- frame = audio->out + audio->out_tail;
- if (frame->used == 0xffffffff) {
- dprintk("frame %d free\n", audio->out_tail);
- frame->used = 0;
- audio->out_tail ^= 1;
- wake_up(&audio->write_wait);
- }
- }
-
- if (audio->out_needed) {
- /* If the DSP currently wants data and we have a
- * buffer available, we will send it and reset
- * the needed flag. We'll mark the buffer as in-flight
- * so that it won't be recycled until the next buffer
- * is requested
- */
-
- frame = audio->out + audio->out_tail;
- if (frame->used) {
- BUG_ON(frame->used == 0xffffffff);
- dprintk("frame %d busy\n", audio->out_tail);
- audplay_dsp_send_data_avail(audio, audio->out_tail,
- frame->used);
- frame->used = 0xffffffff;
- audio->out_needed = 0;
- }
- }
- done:
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
-}
-
-/* ------------------- device --------------------- */
-
-static void audqcelp_flush(struct audio *audio)
-{
- audio->out[0].used = 0;
- audio->out[1].used = 0;
- audio->out_head = 0;
- audio->out_tail = 0;
- audio->stopped = 0;
-}
-
-static void audqcelp_flush_pcm_buf(struct audio *audio)
-{
- uint8_t index;
-
- for (index = 0; index < PCM_BUF_MAX_COUNT; index++)
- audio->in[index].used = 0;
-
- audio->read_next = 0;
- audio->fill_next = 0;
-}
-
-static long audqcelp_ioctl(struct file *file, unsigned int cmd,
- unsigned long arg)
-{
- struct audio *audio = file->private_data;
- int rc = 0;
-
- dprintk("audqcelp_ioctl() cmd = %d\n", cmd);
-
- if (cmd == AUDIO_GET_STATS) {
- struct msm_audio_stats stats;
- stats.byte_count = audpp_avsync_byte_count(audio->dec_id);
- stats.sample_count = audpp_avsync_sample_count(audio->dec_id);
- if (copy_to_user((void *)arg, &stats, sizeof(stats)))
- return -EFAULT;
- return 0;
- }
- if (cmd == AUDIO_SET_VOLUME) {
- unsigned long flags;
- spin_lock_irqsave(&audio->dsp_lock, flags);
- audio->volume = arg;
- if (audio->running)
- audpp_set_volume_and_pan(audio->dec_id, arg, 0);
- spin_unlock_irqrestore(&audio->dsp_lock, flags);
- return 0;
- }
- mutex_lock(&audio->lock);
- switch (cmd) {
- case AUDIO_START:
- rc = audqcelp_enable(audio);
- break;
- case AUDIO_STOP:
- rc = audqcelp_disable(audio);
- audio->stopped = 1;
- break;
- case AUDIO_FLUSH:
- if (audio->stopped) {
- /* Make sure we're stopped and we wake any threads
- * that might be blocked holding the write_lock.
- * While audio->stopped write threads will always
- * exit immediately.
- */
- wake_up(&audio->write_wait);
- mutex_lock(&audio->write_lock);
- audqcelp_flush(audio);
- mutex_unlock(&audio->write_lock);
- wake_up(&audio->read_wait);
- mutex_lock(&audio->read_lock);
- audqcelp_flush_pcm_buf(audio);
- mutex_unlock(&audio->read_lock);
- break;
- }
- break;
- case AUDIO_SET_CONFIG:
- dprintk("AUDIO_SET_CONFIG not applicable \n");
- break;
- case AUDIO_GET_CONFIG:{
- struct msm_audio_config config;
- config.buffer_size = BUFSZ;
- config.buffer_count = BUF_COUNT;
- config.sample_rate = 8000;
- config.channel_count = 1;
- config.unused[0] = 0;
- config.unused[1] = 0;
- config.unused[2] = 0;
- config.unused[3] = 0;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
-
- break;
- }
- case AUDIO_GET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
-
- config.pcm_feedback = 0;
- config.buffer_count = PCM_BUF_MAX_COUNT;
- config.buffer_size = PCM_BUFSZ_MIN;
- if (copy_to_user((void *)arg, &config,
- sizeof(config)))
- rc = -EFAULT;
- else
- rc = 0;
- break;
- }
- case AUDIO_SET_PCM_CONFIG:{
- struct msm_audio_pcm_config config;
-
- if (copy_from_user(&config, (void *)arg,
- sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- if ((config.buffer_count > PCM_BUF_MAX_COUNT) ||
- (config.buffer_count == 1))
- config.buffer_count = PCM_BUF_MAX_COUNT;
-
- if (config.buffer_size < PCM_BUFSZ_MIN)
- config.buffer_size = PCM_BUFSZ_MIN;
-
- /* Check if pcm feedback is required */
- if ((config.pcm_feedback) && (!audio->read_data)) {
- dprintk(
- "audqcelp_ioctl: allocate PCM buf %d\n",
- config.buffer_count * config.buffer_size);
- audio->read_data = dma_alloc_coherent(NULL,
- config.buffer_size * config.buffer_count,
- &audio->read_phys, GFP_KERNEL);
- if (!audio->read_data) {
- pr_err(
- "audqcelp_ioctl: no mem for pcm buf\n"
- );
- rc = -ENOMEM;
- } else {
- uint8_t index;
- uint32_t offset = 0;
-
- audio->pcm_feedback = 1;
- audio->buf_refresh = 0;
- audio->pcm_buf_count =
- config.buffer_count;
- audio->read_next = 0;
- audio->fill_next = 0;
-
- for (index = 0;
- index < config.buffer_count; index++) {
- audio->in[index].data =
- audio->read_data + offset;
- audio->in[index].addr =
- audio->read_phys + offset;
- audio->in[index].size =
- config.buffer_size;
- audio->in[index].used = 0;
- offset += config.buffer_size;
- }
- rc = 0;
- }
- } else {
- rc = 0;
- }
- break;
- }
- case AUDIO_PAUSE:
- dprintk("%s: AUDIO_PAUSE %ld\n", __func__, arg);
- rc = audpp_pause(audio->dec_id, (int) arg);
- break;
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static ssize_t audqcelp_read(struct file *file, char __user *buf, size_t count,
- loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- int rc = 0;
-
- if (!audio->pcm_feedback)
- return 0; /* PCM feedback is not enabled. Nothing to read */
-
- mutex_lock(&audio->read_lock);
- dprintk("audqcelp_read() %d \n", count);
- while (count > 0) {
- rc = wait_event_interruptible(audio->read_wait,
- (audio->in[audio->read_next].used > 0) ||
- (audio->stopped));
- if (rc < 0)
- break;
-
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
-
- if (count < audio->in[audio->read_next].used) {
- /* Read must happen in frame boundary. Since driver does
- not know frame size, read count must be greater or equal
- to size of PCM samples */
- dprintk("audqcelp_read:read stop - partial frame\n");
- break;
- } else {
- dprintk("audqcelp_read: read from in[%d]\n",
- audio->read_next);
- if (copy_to_user(buf,
- audio->in[audio->read_next].data,
- audio->in[audio->read_next].used)) {
- pr_err("audqcelp_read: invalid addr %x \n",
- (unsigned int)buf);
- rc = -EFAULT;
- break;
- }
- count -= audio->in[audio->read_next].used;
- buf += audio->in[audio->read_next].used;
- audio->in[audio->read_next].used = 0;
- if ((++audio->read_next) == audio->pcm_buf_count)
- audio->read_next = 0;
- }
- }
-
- if (audio->buf_refresh) {
- audio->buf_refresh = 0;
- dprintk("audqcelp_read: kick start pcm feedback again\n");
- audqcelp_buffer_refresh(audio);
- }
-
- mutex_unlock(&audio->read_lock);
-
- if (buf > start)
- rc = buf - start;
-
- dprintk("audqcelp_read: read %d bytes\n", rc);
- return rc;
-}
-
-static ssize_t audqcelp_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct audio *audio = file->private_data;
- const char __user *start = buf;
- struct buffer *frame;
- size_t xfer;
- int rc = 0;
-
- if (count & 1)
- return -EINVAL;
- dprintk("audqcelp_write() \n");
- mutex_lock(&audio->write_lock);
- while (count > 0) {
- frame = audio->out + audio->out_head;
- rc = wait_event_interruptible(audio->write_wait,
- (frame->used == 0)
- || (audio->stopped));
- dprintk("audqcelp_write() buffer available\n");
- if (rc < 0)
- break;
- if (audio->stopped) {
- rc = -EBUSY;
- break;
- }
- xfer = (count > frame->size) ? frame->size : count;
- if (copy_from_user(frame->data, buf, xfer)) {
- rc = -EFAULT;
- break;
- }
-
- frame->used = xfer;
- audio->out_head ^= 1;
- count -= xfer;
- buf += xfer;
-
- audqcelp_send_data(audio, 0);
-
- }
- mutex_unlock(&audio->write_lock);
- if (buf > start)
- return buf - start;
- return rc;
-}
-
-static int audqcelp_release(struct inode *inode, struct file *file)
-{
- struct audio *audio = file->private_data;
-
- dprintk("audqcelp_release()\n");
-
- mutex_lock(&audio->lock);
- audqcelp_disable(audio);
- audqcelp_flush(audio);
- audqcelp_flush_pcm_buf(audio);
- msm_adsp_put(audio->audplay);
- audio->audplay = NULL;
- audio->opened = 0;
- if (audio->data)
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- audio->data = NULL;
- if (audio->read_data) {
- dma_free_coherent(NULL,
- audio->in[0].size * audio->pcm_buf_count,
- audio->read_data, audio->read_phys);
- audio->read_data = NULL;
- }
- audio->pcm_feedback = 0;
- mutex_unlock(&audio->lock);
- return 0;
-}
-
-static int audqcelp_open(struct inode *inode, struct file *file)
-{
- struct audio *audio = &the_qcelp_audio;
- int rc;
-
- mutex_lock(&audio->lock);
-
- if (audio->opened) {
- pr_err("audio: busy\n");
- rc = -EBUSY;
- goto done;
- }
-
- audio->data = dma_alloc_coherent(NULL, DMASZ,
- &audio->phys, GFP_KERNEL);
- if (!audio->data) {
- pr_err("audio: could not allocate DMA buffers\n");
- rc = -ENOMEM;
- goto done;
- }
-
- rc = audmgr_open(&audio->audmgr);
- if (rc)
- goto err;
-
- rc = msm_adsp_get("AUDPLAY0TASK", &audio->audplay,
- &audplay_adsp_ops_qcelp, audio);
- if (rc) {
- pr_err("audio: failed to get audplay0 dsp module\n");
- audmgr_close(&audio->audmgr);
- goto err;
- }
-
- audio->dec_id = 0;
-
- audio->out[0].data = audio->data + 0;
- audio->out[0].addr = audio->phys + 0;
- audio->out[0].size = BUFSZ;
-
- audio->out[1].data = audio->data + BUFSZ;
- audio->out[1].addr = audio->phys + BUFSZ;
- audio->out[1].size = BUFSZ;
-
- audio->volume = 0x2000; /* Q13 1.0 */
-
- audqcelp_flush(audio);
-
- file->private_data = audio;
- audio->opened = 1;
- rc = 0;
-done:
- mutex_unlock(&audio->lock);
- return rc;
-err:
- dma_free_coherent(NULL, DMASZ, audio->data, audio->phys);
- mutex_unlock(&audio->lock);
- return rc;
-}
-
-static struct file_operations audio_qcelp_fops = {
- .owner = THIS_MODULE,
- .open = audqcelp_open,
- .release = audqcelp_release,
- .read = audqcelp_read,
- .write = audqcelp_write,
- .unlocked_ioctl = audqcelp_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice audio_qcelp_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_qcelp",
- .fops = &audio_qcelp_fops,
-};
-
-static int __init audqcelp_init(void)
-{
- mutex_init(&the_qcelp_audio.lock);
- mutex_init(&the_qcelp_audio.write_lock);
- mutex_init(&the_qcelp_audio.read_lock);
- spin_lock_init(&the_qcelp_audio.dsp_lock);
- init_waitqueue_head(&the_qcelp_audio.write_wait);
- init_waitqueue_head(&the_qcelp_audio.read_wait);
- the_qcelp_audio.read_data = NULL;
- return misc_register(&audio_qcelp_misc);
-}
-
-static void __exit audqcelp_exit(void)
-{
- misc_deregister(&audio_qcelp_misc);
-}
-
-module_init(audqcelp_init);
-module_exit(audqcelp_exit);
-
-MODULE_DESCRIPTION("MSM QCELP 13K driver");
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("QUALCOMM");
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audmgr.c
- *
- * interface to "audmgr" service on the baseband cpu
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/kthread.h>
-#include <linux/wait.h>
-
-#include <asm/atomic.h>
-#include <mach/msm_rpcrouter.h>
-
-#include "audmgr.h"
-
-#define STATE_CLOSED 0
-#define STATE_DISABLED 1
-#define STATE_ENABLING 2
-#define STATE_ENABLED 3
-#define STATE_DISABLING 4
-#define STATE_ERROR 5
-
-static void rpc_ack(struct msm_rpc_endpoint *ept, uint32_t xid)
-{
- uint32_t rep[6];
-
- rep[0] = cpu_to_be32(xid);
- rep[1] = cpu_to_be32(1);
- rep[2] = cpu_to_be32(RPCMSG_REPLYSTAT_ACCEPTED);
- rep[3] = cpu_to_be32(RPC_ACCEPTSTAT_SUCCESS);
- rep[4] = 0;
- rep[5] = 0;
-
- msm_rpc_write(ept, rep, sizeof(rep));
-}
-
-static void process_audmgr_callback(struct audmgr *am,
- struct rpc_audmgr_cb_func_ptr *args,
- int len)
-{
- if (len < (sizeof(uint32_t) * 3))
- return;
- if (be32_to_cpu(args->set_to_one) != 1)
- return;
-
- switch (be32_to_cpu(args->status)) {
- case RPC_AUDMGR_STATUS_READY:
- if (len < sizeof(uint32_t) * 4)
- break;
- am->handle = be32_to_cpu(args->u.handle);
- pr_info("audmgr: rpc READY handle=0x%08x\n", am->handle);
- break;
- case RPC_AUDMGR_STATUS_CODEC_CONFIG: {
- uint32_t volume;
- if (len < sizeof(uint32_t) * 4)
- break;
- volume = be32_to_cpu(args->u.volume);
- pr_info("audmgr: rpc CODEC_CONFIG volume=0x%08x\n", volume);
- am->state = STATE_ENABLED;
- wake_up(&am->wait);
- break;
- }
- case RPC_AUDMGR_STATUS_PENDING:
- pr_err("audmgr: PENDING?\n");
- break;
- case RPC_AUDMGR_STATUS_SUSPEND:
- pr_err("audmgr: SUSPEND?\n");
- break;
- case RPC_AUDMGR_STATUS_FAILURE:
- pr_err("audmgr: FAILURE\n");
- break;
- case RPC_AUDMGR_STATUS_VOLUME_CHANGE:
- pr_err("audmgr: VOLUME_CHANGE?\n");
- break;
- case RPC_AUDMGR_STATUS_DISABLED:
- pr_err("audmgr: DISABLED\n");
- am->state = STATE_DISABLED;
- wake_up(&am->wait);
- break;
- case RPC_AUDMGR_STATUS_ERROR:
- pr_err("audmgr: ERROR?\n");
- am->state = STATE_ERROR;
- wake_up(&am->wait);
- break;
- default:
- break;
- }
-}
-
-static void process_rpc_request(uint32_t proc, uint32_t xid,
- void *data, int len, void *private)
-{
- struct audmgr *am = private;
- uint32_t *x = data;
-
- if (0) {
- int n = len / 4;
- pr_info("rpc_call proc %d:", proc);
- while (n--)
- printk(" %08x", be32_to_cpu(*x++));
- printk("\n");
- }
-
- if (proc == AUDMGR_CB_FUNC_PTR)
- process_audmgr_callback(am, data, len);
- else
- pr_err("audmgr: unknown rpc proc %d\n", proc);
- rpc_ack(am->ept, xid);
-}
-
-#define RPC_TYPE_REQUEST 0
-#define RPC_TYPE_REPLY 1
-
-#define RPC_VERSION 2
-
-#define RPC_COMMON_HDR_SZ (sizeof(uint32_t) * 2)
-#define RPC_REQUEST_HDR_SZ (sizeof(struct rpc_request_hdr))
-#define RPC_REPLY_HDR_SZ (sizeof(uint32_t) * 3)
-#define RPC_REPLY_SZ (sizeof(uint32_t) * 6)
-
-static int audmgr_rpc_thread(void *data)
-{
- struct audmgr *am = data;
- struct rpc_request_hdr *hdr = NULL;
- uint32_t type;
- int len;
-
- pr_info("audmgr_rpc_thread() start\n");
-
- while (!kthread_should_stop()) {
- if (hdr) {
- kfree(hdr);
- hdr = NULL;
- }
- len = msm_rpc_read(am->ept, (void **) &hdr, -1, -1);
- if (len < 0) {
- pr_err("audmgr: rpc read failed (%d)\n", len);
- break;
- }
- if (len < RPC_COMMON_HDR_SZ)
- continue;
-
- type = be32_to_cpu(hdr->type);
- if (type == RPC_TYPE_REPLY) {
- struct rpc_reply_hdr *rep = (void *) hdr;
- uint32_t status;
- if (len < RPC_REPLY_HDR_SZ)
- continue;
- status = be32_to_cpu(rep->reply_stat);
- if (status == RPCMSG_REPLYSTAT_ACCEPTED) {
- status = be32_to_cpu(rep->data.acc_hdr.accept_stat);
- pr_info("audmgr: rpc_reply status %d\n", status);
- } else {
- pr_info("audmgr: rpc_reply denied!\n");
- }
- /* process reply */
- continue;
- }
-
- if (len < RPC_REQUEST_HDR_SZ)
- continue;
-
- process_rpc_request(be32_to_cpu(hdr->procedure),
- be32_to_cpu(hdr->xid),
- (void *) (hdr + 1),
- len - sizeof(*hdr),
- data);
- }
- pr_info("audmgr_rpc_thread() exit\n");
- if (hdr) {
- kfree(hdr);
- hdr = NULL;
- }
- am->task = NULL;
- wake_up(&am->wait);
- return 0;
-}
-
-struct audmgr_enable_msg {
- struct rpc_request_hdr hdr;
- struct rpc_audmgr_enable_client_args args;
-};
-
-struct audmgr_disable_msg {
- struct rpc_request_hdr hdr;
- uint32_t handle;
-};
-
-int audmgr_open(struct audmgr *am)
-{
- int rc;
-
- if (am->state != STATE_CLOSED)
- return 0;
-
- am->ept = msm_rpc_connect(AUDMGR_PROG,
- AUDMGR_VERS,
- MSM_RPC_UNINTERRUPTIBLE);
-
- init_waitqueue_head(&am->wait);
-
- if (IS_ERR(am->ept)) {
- rc = PTR_ERR(am->ept);
- am->ept = NULL;
- pr_err("audmgr: failed to connect to audmgr svc\n");
- return rc;
- }
-
- am->task = kthread_run(audmgr_rpc_thread, am, "audmgr_rpc");
- if (IS_ERR(am->task)) {
- rc = PTR_ERR(am->task);
- am->task = NULL;
- msm_rpc_close(am->ept);
- am->ept = NULL;
- return rc;
- }
-
- am->state = STATE_DISABLED;
- return 0;
-}
-EXPORT_SYMBOL(audmgr_open);
-
-int audmgr_close(struct audmgr *am)
-{
- return -EBUSY;
-}
-EXPORT_SYMBOL(audmgr_close);
-
-int audmgr_enable(struct audmgr *am, struct audmgr_config *cfg)
-{
- struct audmgr_enable_msg msg;
- int rc;
-
- if (am->state == STATE_ENABLED)
- return 0;
-
- if (am->state == STATE_DISABLING)
- pr_err("audmgr: state is DISABLING in enable?\n");
- am->state = STATE_ENABLING;
-
- msg.args.set_to_one = cpu_to_be32(1);
- msg.args.tx_sample_rate = cpu_to_be32(cfg->tx_rate);
- msg.args.rx_sample_rate = cpu_to_be32(cfg->rx_rate);
- msg.args.def_method = cpu_to_be32(cfg->def_method);
- msg.args.codec_type = cpu_to_be32(cfg->codec);
- msg.args.snd_method = cpu_to_be32(cfg->snd_method);
- msg.args.cb_func = cpu_to_be32(0x11111111);
- msg.args.client_data = cpu_to_be32(0x11223344);
-
- msm_rpc_setup_req(&msg.hdr, AUDMGR_PROG, msm_rpc_get_vers(am->ept),
- AUDMGR_ENABLE_CLIENT);
-
- rc = msm_rpc_write(am->ept, &msg, sizeof(msg));
- if (rc < 0)
- return rc;
-
- rc = wait_event_timeout(am->wait, am->state != STATE_ENABLING, 15 * HZ);
- if (rc == 0) {
- pr_err("audmgr_enable: ARM9 did not reply to RPC am->state = %d\n", am->state);
- BUG();
- }
- if (am->state == STATE_ENABLED)
- return 0;
-
- pr_err("audmgr: unexpected state %d while enabling?!\n", am->state);
- return -ENODEV;
-}
-EXPORT_SYMBOL(audmgr_enable);
-
-int audmgr_disable(struct audmgr *am)
-{
- struct audmgr_disable_msg msg;
- int rc;
-
- if (am->state == STATE_DISABLED)
- return 0;
-
- msm_rpc_setup_req(&msg.hdr, AUDMGR_PROG, msm_rpc_get_vers(am->ept),
- AUDMGR_DISABLE_CLIENT);
- msg.handle = cpu_to_be32(am->handle);
-
- am->state = STATE_DISABLING;
-
- rc = msm_rpc_write(am->ept, &msg, sizeof(msg));
- if (rc < 0)
- return rc;
-
- rc = wait_event_timeout(am->wait, am->state != STATE_DISABLING, 15 * HZ);
- if (rc == 0) {
- pr_err("audmgr_disable: ARM9 did not reply to RPC am->state = %d\n", am->state);
- BUG();
- }
-
- if (am->state == STATE_DISABLED)
- return 0;
-
- pr_err("audmgr: unexpected state %d while disabling?!\n", am->state);
- return -ENODEV;
-}
-EXPORT_SYMBOL(audmgr_disable);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audmgr.h
- *
- * Copyright 2008 (c) QUALCOMM Incorporated.
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_MSM_AUDMGR_H
-#define _ARCH_ARM_MACH_MSM_AUDMGR_H
-
-#if CONFIG_MSM_AMSS_VERSION==6350
-#include "audmgr_new.h"
-#else
-
-enum rpc_aud_def_sample_rate_type {
- RPC_AUD_DEF_SAMPLE_RATE_NONE,
- RPC_AUD_DEF_SAMPLE_RATE_8000,
- RPC_AUD_DEF_SAMPLE_RATE_11025,
- RPC_AUD_DEF_SAMPLE_RATE_12000,
- RPC_AUD_DEF_SAMPLE_RATE_16000,
- RPC_AUD_DEF_SAMPLE_RATE_22050,
- RPC_AUD_DEF_SAMPLE_RATE_24000,
- RPC_AUD_DEF_SAMPLE_RATE_32000,
- RPC_AUD_DEF_SAMPLE_RATE_44100,
- RPC_AUD_DEF_SAMPLE_RATE_48000,
- RPC_AUD_DEF_SAMPLE_RATE_MAX,
-};
-
-enum rpc_aud_def_method_type {
- RPC_AUD_DEF_METHOD_NONE,
- RPC_AUD_DEF_METHOD_KEY_BEEP,
- RPC_AUD_DEF_METHOD_PLAYBACK,
- RPC_AUD_DEF_METHOD_VOICE,
- RPC_AUD_DEF_METHOD_RECORD,
- RPC_AUD_DEF_METHOD_HOST_PCM,
- RPC_AUD_DEF_METHOD_MIDI_OUT,
- RPC_AUD_DEF_METHOD_RECORD_SBC,
- RPC_AUD_DEF_METHOD_DTMF_RINGER,
- RPC_AUD_DEF_METHOD_MAX,
-};
-
-enum rpc_aud_def_codec_type {
- RPC_AUD_DEF_CODEC_NONE,
- RPC_AUD_DEF_CODEC_DTMF,
- RPC_AUD_DEF_CODEC_MIDI,
- RPC_AUD_DEF_CODEC_MP3,
- RPC_AUD_DEF_CODEC_PCM,
- RPC_AUD_DEF_CODEC_AAC,
- RPC_AUD_DEF_CODEC_WMA,
- RPC_AUD_DEF_CODEC_RA,
- RPC_AUD_DEF_CODEC_ADPCM,
- RPC_AUD_DEF_CODEC_GAUDIO,
- RPC_AUD_DEF_CODEC_VOC_EVRC,
- RPC_AUD_DEF_CODEC_VOC_13K,
- RPC_AUD_DEF_CODEC_VOC_4GV_NB,
- RPC_AUD_DEF_CODEC_VOC_AMR,
- RPC_AUD_DEF_CODEC_VOC_EFR,
- RPC_AUD_DEF_CODEC_VOC_FR,
- RPC_AUD_DEF_CODEC_VOC_HR,
- RPC_AUD_DEF_CODEC_VOC,
- RPC_AUD_DEF_CODEC_SBC,
- RPC_AUD_DEF_CODEC_VOC_PCM,
- RPC_AUD_DEF_CODEC_AMR_WB,
- RPC_AUD_DEF_CODEC_AMR_WB_PLUS,
- RPC_AUD_DEF_CODEC_MAX,
-};
-
-enum rpc_snd_method_type {
- RPC_SND_METHOD_VOICE = 0,
- RPC_SND_METHOD_KEY_BEEP,
- RPC_SND_METHOD_MESSAGE,
- RPC_SND_METHOD_RING,
- RPC_SND_METHOD_MIDI,
- RPC_SND_METHOD_AUX,
- RPC_SND_METHOD_MAX,
-};
-
-enum rpc_voc_codec_type {
- RPC_VOC_CODEC_DEFAULT,
- RPC_VOC_CODEC_ON_CHIP_0 = RPC_VOC_CODEC_DEFAULT,
- RPC_VOC_CODEC_ON_CHIP_1,
- RPC_VOC_CODEC_STEREO_HEADSET,
- RPC_VOC_CODEC_ON_CHIP_AUX,
- RPC_VOC_CODEC_BT_OFF_BOARD,
- RPC_VOC_CODEC_BT_A2DP,
- RPC_VOC_CODEC_OFF_BOARD,
- RPC_VOC_CODEC_SDAC,
- RPC_VOC_CODEC_RX_EXT_SDAC_TX_INTERNAL,
- RPC_VOC_CODEC_IN_STEREO_SADC_OUT_MONO_HANDSET,
- RPC_VOC_CODEC_IN_STEREO_SADC_OUT_STEREO_HEADSET,
- RPC_VOC_CODEC_TX_INT_SADC_RX_EXT_AUXPCM,
- RPC_VOC_CODEC_EXT_STEREO_SADC_OUT_MONO_HANDSET,
- RPC_VOC_CODEC_EXT_STEREO_SADC_OUT_STEREO_HEADSET,
- RPC_VOC_CODEC_TTY_ON_CHIP_1,
- RPC_VOC_CODEC_TTY_OFF_BOARD,
- RPC_VOC_CODEC_TTY_VCO,
- RPC_VOC_CODEC_TTY_HCO,
- RPC_VOC_CODEC_ON_CHIP_0_DUAL_MIC,
- RPC_VOC_CODEC_MAX,
- RPC_VOC_CODEC_NONE,
-};
-
-enum rpc_audmgr_status_type {
- RPC_AUDMGR_STATUS_READY,
- RPC_AUDMGR_STATUS_CODEC_CONFIG,
- RPC_AUDMGR_STATUS_PENDING,
- RPC_AUDMGR_STATUS_SUSPEND,
- RPC_AUDMGR_STATUS_FAILURE,
- RPC_AUDMGR_STATUS_VOLUME_CHANGE,
- RPC_AUDMGR_STATUS_DISABLED,
- RPC_AUDMGR_STATUS_ERROR,
-};
-
-struct rpc_audmgr_enable_client_args {
- uint32_t set_to_one;
- uint32_t tx_sample_rate;
- uint32_t rx_sample_rate;
- uint32_t def_method;
- uint32_t codec_type;
- uint32_t snd_method;
-
- uint32_t cb_func;
- uint32_t client_data;
-};
-
-#define AUDMGR_ENABLE_CLIENT 2
-#define AUDMGR_DISABLE_CLIENT 3
-#define AUDMGR_SUSPEND_EVENT_RSP 4
-#define AUDMGR_REGISTER_OPERATION_LISTENER 5
-#define AUDMGR_UNREGISTER_OPERATION_LISTENER 6
-#define AUDMGR_REGISTER_CODEC_LISTENER 7
-#define AUDMGR_GET_RX_SAMPLE_RATE 8
-#define AUDMGR_GET_TX_SAMPLE_RATE 9
-#define AUDMGR_SET_DEVICE_MODE 10
-
-#if CONFIG_MSM_AMSS_VERSION < 6220
-#define AUDMGR_PROG_VERS "rs30000013:46255756"
-#define AUDMGR_PROG 0x30000013
-#define AUDMGR_VERS 0x46255756
-#else
-#define AUDMGR_PROG_VERS "rs30000013:e94e8f0c"
-#define AUDMGR_PROG 0x30000013
-#define AUDMGR_VERS 0xe94e8f0c
-#endif
-
-struct rpc_audmgr_cb_func_ptr {
- uint32_t cb_id;
- uint32_t set_to_one;
- uint32_t status;
- union {
- uint32_t handle;
- uint32_t volume;
-
- } u;
-};
-
-#define AUDMGR_CB_FUNC_PTR 1
-#define AUDMGR_OPR_LSTNR_CB_FUNC_PTR 2
-#define AUDMGR_CODEC_LSTR_FUNC_PTR 3
-
-#if CONFIG_MSM_AMSS_VERSION < 6220
-#define AUDMGR_CB_PROG 0x31000013
-#define AUDMGR_CB_VERS 0x5fa922a9
-#else
-#define AUDMGR_CB_PROG 0x31000013
-#define AUDMGR_CB_VERS 0x21570ba7
-#endif
-
-struct audmgr {
- wait_queue_head_t wait;
- uint32_t handle;
- struct msm_rpc_endpoint *ept;
- struct task_struct *task;
- int state;
-};
-
-struct audmgr_config {
- uint32_t tx_rate;
- uint32_t rx_rate;
- uint32_t def_method;
- uint32_t codec;
- uint32_t snd_method;
-};
-
-int audmgr_open(struct audmgr *am);
-int audmgr_close(struct audmgr *am);
-int audmgr_enable(struct audmgr *am, struct audmgr_config *cfg);
-int audmgr_disable(struct audmgr *am);
-
-typedef void (*audpp_event_func)(void *private, unsigned id, uint16_t *msg);
-
-int audpp_enable(int id, audpp_event_func func, void *private);
-void audpp_disable(int id, void *private);
-
-int audpp_send_queue1(void *cmd, unsigned len);
-int audpp_send_queue2(void *cmd, unsigned len);
-int audpp_send_queue3(void *cmd, unsigned len);
-
-int audpp_pause(unsigned id, int pause);
-int audpp_set_volume_and_pan(unsigned id, unsigned volume, int pan);
-void audpp_avsync(int id, unsigned rate);
-unsigned audpp_avsync_sample_count(int id);
-unsigned audpp_avsync_byte_count(int id);
-
-#endif
-#endif
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/audmgr.h
- *
- * Copyright 2008 (c) QUALCOMM Incorporated.
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_MSM_AUDMGR_NEW_H
-#define _ARCH_ARM_MACH_MSM_AUDMGR_NEW_H
-
-enum rpc_aud_def_sample_rate_type {
- RPC_AUD_DEF_SAMPLE_RATE_NONE,
- RPC_AUD_DEF_SAMPLE_RATE_8000,
- RPC_AUD_DEF_SAMPLE_RATE_11025,
- RPC_AUD_DEF_SAMPLE_RATE_12000,
- RPC_AUD_DEF_SAMPLE_RATE_16000,
- RPC_AUD_DEF_SAMPLE_RATE_22050,
- RPC_AUD_DEF_SAMPLE_RATE_24000,
- RPC_AUD_DEF_SAMPLE_RATE_32000,
- RPC_AUD_DEF_SAMPLE_RATE_44100,
- RPC_AUD_DEF_SAMPLE_RATE_48000,
- RPC_AUD_DEF_SAMPLE_RATE_MAX,
-};
-
-enum rpc_aud_def_method_type {
- RPC_AUD_DEF_METHOD_NONE,
- RPC_AUD_DEF_METHOD_KEY_BEEP,
- RPC_AUD_DEF_METHOD_PLAYBACK,
- RPC_AUD_DEF_METHOD_VOICE,
- RPC_AUD_DEF_METHOD_RECORD,
- RPC_AUD_DEF_METHOD_HOST_PCM,
- RPC_AUD_DEF_METHOD_MIDI_OUT,
- RPC_AUD_DEF_METHOD_RECORD_SBC,
- RPC_AUD_DEF_METHOD_DTMF_RINGER,
- RPC_AUD_DEF_METHOD_MAX,
-};
-
-enum rpc_aud_def_codec_type {
- RPC_AUD_DEF_CODEC_NONE,
- RPC_AUD_DEF_CODEC_DTMF,
- RPC_AUD_DEF_CODEC_MIDI,
- RPC_AUD_DEF_CODEC_MP3,
- RPC_AUD_DEF_CODEC_PCM,
- RPC_AUD_DEF_CODEC_AAC,
- RPC_AUD_DEF_CODEC_WMA,
- RPC_AUD_DEF_CODEC_RA,
- RPC_AUD_DEF_CODEC_ADPCM,
- RPC_AUD_DEF_CODEC_GAUDIO,
- RPC_AUD_DEF_CODEC_VOC_EVRC,
- RPC_AUD_DEF_CODEC_VOC_13K,
- RPC_AUD_DEF_CODEC_VOC_4GV_NB,
- RPC_AUD_DEF_CODEC_VOC_AMR,
- RPC_AUD_DEF_CODEC_VOC_EFR,
- RPC_AUD_DEF_CODEC_VOC_FR,
- RPC_AUD_DEF_CODEC_VOC_HR,
- RPC_AUD_DEF_CODEC_VOC_CDMA,
- RPC_AUD_DEF_CODEC_VOC_CDMA_WB,
- RPC_AUD_DEF_CODEC_VOC_UMTS,
- RPC_AUD_DEF_CODEC_VOC_UMTS_WB,
- RPC_AUD_DEF_CODEC_SBC,
- RPC_AUD_DEF_CODEC_VOC_PCM,
- RPC_AUD_DEF_CODEC_AMR_WB,
- RPC_AUD_DEF_CODEC_AMR_WB_PLUS,
- RPC_AUD_DEF_CODEC_AAC_BSAC,
- RPC_AUD_DEF_CODEC_MAX,
- RPC_AUD_DEF_CODEC_AMR_NB,
- RPC_AUD_DEF_CODEC_13K,
- RPC_AUD_DEF_CODEC_EVRC,
- RPC_AUD_DEF_CODEC_MAX_002,
-};
-
-enum rpc_snd_method_type {
- RPC_SND_METHOD_VOICE = 0,
- RPC_SND_METHOD_KEY_BEEP,
- RPC_SND_METHOD_MESSAGE,
- RPC_SND_METHOD_RING,
- RPC_SND_METHOD_MIDI,
- RPC_SND_METHOD_AUX,
- RPC_SND_METHOD_MAX,
-};
-
-enum rpc_voc_codec_type {
- RPC_VOC_CODEC_DEFAULT,
- RPC_VOC_CODEC_ON_CHIP_0 = RPC_VOC_CODEC_DEFAULT,
- RPC_VOC_CODEC_ON_CHIP_1,
- RPC_VOC_CODEC_STEREO_HEADSET,
- RPC_VOC_CODEC_ON_CHIP_AUX,
- RPC_VOC_CODEC_BT_OFF_BOARD,
- RPC_VOC_CODEC_BT_A2DP,
- RPC_VOC_CODEC_OFF_BOARD,
- RPC_VOC_CODEC_SDAC,
- RPC_VOC_CODEC_RX_EXT_SDAC_TX_INTERNAL,
- RPC_VOC_CODEC_IN_STEREO_SADC_OUT_MONO_HANDSET,
- RPC_VOC_CODEC_IN_STEREO_SADC_OUT_STEREO_HEADSET,
- RPC_VOC_CODEC_TX_INT_SADC_RX_EXT_AUXPCM,
- RPC_VOC_CODEC_EXT_STEREO_SADC_OUT_MONO_HANDSET,
- RPC_VOC_CODEC_EXT_STEREO_SADC_OUT_STEREO_HEADSET,
- RPC_VOC_CODEC_TTY_ON_CHIP_1,
- RPC_VOC_CODEC_TTY_OFF_BOARD,
- RPC_VOC_CODEC_TTY_VCO,
- RPC_VOC_CODEC_TTY_HCO,
- RPC_VOC_CODEC_ON_CHIP_0_DUAL_MIC,
- RPC_VOC_CODEC_MAX,
- RPC_VOC_CODEC_NONE,
-};
-
-enum rpc_audmgr_status_type {
- RPC_AUDMGR_STATUS_READY,
- RPC_AUDMGR_STATUS_CODEC_CONFIG,
- RPC_AUDMGR_STATUS_PENDING,
- RPC_AUDMGR_STATUS_SUSPEND,
- RPC_AUDMGR_STATUS_FAILURE,
- RPC_AUDMGR_STATUS_VOLUME_CHANGE,
- RPC_AUDMGR_STATUS_DISABLED,
- RPC_AUDMGR_STATUS_ERROR,
-};
-
-struct rpc_audmgr_enable_client_args {
- uint32_t set_to_one;
- uint32_t tx_sample_rate;
- uint32_t rx_sample_rate;
- uint32_t def_method;
- uint32_t codec_type;
- uint32_t snd_method;
-
- uint32_t cb_func;
- uint32_t client_data;
-};
-
-#define AUDMGR_ENABLE_CLIENT 2
-#define AUDMGR_DISABLE_CLIENT 3
-#define AUDMGR_SUSPEND_EVENT_RSP 4
-#define AUDMGR_REGISTER_OPERATION_LISTENER 5
-#define AUDMGR_UNREGISTER_OPERATION_LISTENER 6
-#define AUDMGR_REGISTER_CODEC_LISTENER 7
-#define AUDMGR_GET_RX_SAMPLE_RATE 8
-#define AUDMGR_GET_TX_SAMPLE_RATE 9
-#define AUDMGR_SET_DEVICE_MODE 10
-
-#define AUDMGR_PROG 0x30000013
-#define AUDMGR_VERS MSM_RPC_VERS(1,0)
-
-struct rpc_audmgr_cb_func_ptr {
- uint32_t cb_id;
- uint32_t status; /* Audmgr status */
- uint32_t set_to_one; /* Pointer status (1 = valid, 0 = invalid) */
- uint32_t disc;
- /* disc = AUDMGR_STATUS_READY => data=handle
- disc = AUDMGR_STATUS_CODEC_CONFIG => data = handle
- disc = AUDMGR_STATUS_DISABLED => data =status_disabled
- disc = AUDMGR_STATUS_VOLUME_CHANGE => data = volume-change */
- union {
- uint32_t handle;
- uint32_t volume;
- uint32_t status_disabled;
- uint32_t volume_change;
- } u;
-};
-
-#define AUDMGR_CB_FUNC_PTR 1
-#define AUDMGR_OPR_LSTNR_CB_FUNC_PTR 2
-#define AUDMGR_CODEC_LSTR_FUNC_PTR 3
-
-#define AUDMGR_CB_PROG 0x31000013
-#define AUDMGR_CB_VERS 0xf8e3e2d9
-
-struct audmgr {
- wait_queue_head_t wait;
- uint32_t handle;
- struct msm_rpc_endpoint *ept;
- struct task_struct *task;
- int state;
-};
-
-struct audmgr_config {
- uint32_t tx_rate;
- uint32_t rx_rate;
- uint32_t def_method;
- uint32_t codec;
- uint32_t snd_method;
-};
-
-int audmgr_open(struct audmgr *am);
-int audmgr_close(struct audmgr *am);
-int audmgr_enable(struct audmgr *am, struct audmgr_config *cfg);
-int audmgr_disable(struct audmgr *am);
-
-typedef void (*audpp_event_func)(void *private, unsigned id, uint16_t *msg);
-
-int audpp_enable(int id, audpp_event_func func, void *private);
-void audpp_disable(int id, void *private);
-
-int audpp_send_queue1(void *cmd, unsigned len);
-int audpp_send_queue2(void *cmd, unsigned len);
-int audpp_send_queue3(void *cmd, unsigned len);
-
-int audpp_set_volume_and_pan(unsigned id, unsigned volume, int pan);
-int audpp_pause(unsigned id, int pause);
-int audpp_flush(unsigned id);
-void audpp_avsync(int id, unsigned rate);
-unsigned audpp_avsync_sample_count(int id);
-unsigned audpp_avsync_byte_count(int id);
-
-#endif
+++ /dev/null
-
-/* arch/arm/mach-msm/qdsp5/audpp.c
- *
- * common code to deal with the AUDPP dsp task (audio postproc)
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/wait.h>
-#include <linux/delay.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/msm_adsp.h>
-
-#include "audmgr.h"
-
-#include <mach/qdsp5/qdsp5audppcmdi.h>
-#include <mach/qdsp5/qdsp5audppmsg.h>
-
-/* for queue ids - should be relative to module number*/
-#include "adsp.h"
-
-#include "evlog.h"
-
-
-enum {
- EV_NULL,
- EV_ENABLE,
- EV_DISABLE,
- EV_EVENT,
- EV_DATA,
-};
-
-static const char *dsp_log_strings[] = {
- "NULL",
- "ENABLE",
- "DISABLE",
- "EVENT",
- "DATA",
-};
-
-DECLARE_LOG(dsp_log, 64, dsp_log_strings);
-
-static int __init _dsp_log_init(void)
-{
- return ev_log_init(&dsp_log);
-}
-module_init(_dsp_log_init);
-#define LOG(id,arg) ev_log_write(&dsp_log, id, arg)
-
-static DEFINE_MUTEX(audpp_lock);
-
-#define CH_COUNT 5
-#define AUDPP_CLNT_MAX_COUNT 6
-#define AUDPP_AVSYNC_INFO_SIZE 7
-
-struct audpp_state {
- struct msm_adsp_module *mod;
- audpp_event_func func[AUDPP_CLNT_MAX_COUNT];
- void *private[AUDPP_CLNT_MAX_COUNT];
- struct mutex *lock;
- unsigned open_count;
- unsigned enabled;
-
- /* which channels are actually enabled */
- unsigned avsync_mask;
-
- /* flags, 48 bits sample/bytes counter per channel */
- uint16_t avsync[CH_COUNT * AUDPP_CLNT_MAX_COUNT + 1];
-};
-
-struct audpp_state the_audpp_state = {
- .lock = &audpp_lock,
-};
-
-int audpp_send_queue1(void *cmd, unsigned len)
-{
- return msm_adsp_write(the_audpp_state.mod,
- QDSP_uPAudPPCmd1Queue, cmd, len);
-}
-EXPORT_SYMBOL(audpp_send_queue1);
-
-int audpp_send_queue2(void *cmd, unsigned len)
-{
- return msm_adsp_write(the_audpp_state.mod,
- QDSP_uPAudPPCmd2Queue, cmd, len);
-}
-EXPORT_SYMBOL(audpp_send_queue2);
-
-int audpp_send_queue3(void *cmd, unsigned len)
-{
- return msm_adsp_write(the_audpp_state.mod,
- QDSP_uPAudPPCmd3Queue, cmd, len);
-}
-EXPORT_SYMBOL(audpp_send_queue3);
-
-static int audpp_dsp_config(int enable)
-{
- audpp_cmd_cfg cmd;
-
- cmd.cmd_id = AUDPP_CMD_CFG;
- cmd.cfg = enable ? AUDPP_CMD_CFG_ENABLE : AUDPP_CMD_CFG_SLEEP;
-
- return audpp_send_queue1(&cmd, sizeof(cmd));
-}
-
-static void audpp_broadcast(struct audpp_state *audpp, unsigned id,
- uint16_t *msg)
-{
- unsigned n;
- for (n = 0; n < AUDPP_CLNT_MAX_COUNT; n++) {
- if (audpp->func[n])
- audpp->func[n] (audpp->private[n], id, msg);
- }
-}
-
-static void audpp_notify_clnt(struct audpp_state *audpp, unsigned clnt_id,
- unsigned id, uint16_t *msg)
-{
- if (clnt_id < AUDPP_CLNT_MAX_COUNT && audpp->func[clnt_id])
- audpp->func[clnt_id] (audpp->private[clnt_id], id, msg);
-}
-
-static void audpp_dsp_event(void *data, unsigned id, size_t len,
- void (*getevent)(void *ptr, size_t len))
-{
- struct audpp_state *audpp = data;
- uint16_t msg[8];
-
- if (id == AUDPP_MSG_AVSYNC_MSG) {
- getevent(audpp->avsync, sizeof(audpp->avsync));
-
- /* mask off any channels we're not watching to avoid
- * cases where we might get one last update after
- * disabling avsync and end up in an odd state when
- * we next read...
- */
- audpp->avsync[0] &= audpp->avsync_mask;
- return;
- }
-
- getevent(msg, sizeof(msg));
-
- LOG(EV_EVENT, (id << 16) | msg[0]);
- LOG(EV_DATA, (msg[1] << 16) | msg[2]);
-
- switch (id) {
- case AUDPP_MSG_STATUS_MSG:{
- unsigned cid = msg[0];
- pr_info("audpp: status %d %d %d\n", cid, msg[1],
- msg[2]);
- if ((cid < 5) && audpp->func[cid])
- audpp->func[cid] (audpp->private[cid], id, msg);
- break;
- }
- case AUDPP_MSG_HOST_PCM_INTF_MSG:
- if (audpp->func[5])
- audpp->func[5] (audpp->private[5], id, msg);
- break;
- case AUDPP_MSG_PCMDMAMISSED:
- pr_err("audpp: DMA missed obj=%x\n", msg[0]);
- break;
- case AUDPP_MSG_CFG_MSG:
- if (msg[0] == AUDPP_MSG_ENA_ENA) {
- pr_info("audpp: ENABLE\n");
- audpp->enabled = 1;
- audpp_broadcast(audpp, id, msg);
- } else if (msg[0] == AUDPP_MSG_ENA_DIS) {
- pr_info("audpp: DISABLE\n");
- audpp->enabled = 0;
- audpp_broadcast(audpp, id, msg);
- } else {
- pr_err("audpp: invalid config msg %d\n", msg[0]);
- }
- break;
- case AUDPP_MSG_ROUTING_ACK:
- audpp_broadcast(audpp, id, msg);
- break;
- case AUDPP_MSG_FLUSH_ACK:
- audpp_notify_clnt(audpp, msg[0], id, msg);
- break;
- default:
- pr_info("audpp: unhandled msg id %x\n", id);
- }
-}
-
-static struct msm_adsp_ops adsp_ops = {
- .event = audpp_dsp_event,
-};
-
-static void audpp_fake_event(struct audpp_state *audpp, int id,
- unsigned event, unsigned arg)
-{
- uint16_t msg[1];
- msg[0] = arg;
- audpp->func[id] (audpp->private[id], event, msg);
-}
-
-int audpp_enable(int id, audpp_event_func func, void *private)
-{
- struct audpp_state *audpp = &the_audpp_state;
- int res = 0;
-
- if (id < -1 || id > 4)
- return -EINVAL;
-
- if (id == -1)
- id = 5;
-
- mutex_lock(audpp->lock);
- if (audpp->func[id]) {
- res = -EBUSY;
- goto out;
- }
-
- audpp->func[id] = func;
- audpp->private[id] = private;
-
- LOG(EV_ENABLE, 1);
- if (audpp->open_count++ == 0) {
- pr_info("audpp: enable\n");
- res = msm_adsp_get("AUDPPTASK", &audpp->mod, &adsp_ops, audpp);
- if (res < 0) {
- pr_err("audpp: cannot open AUDPPTASK\n");
- audpp->open_count = 0;
- audpp->func[id] = NULL;
- audpp->private[id] = NULL;
- goto out;
- }
- LOG(EV_ENABLE, 2);
- msm_adsp_enable(audpp->mod);
- audpp_dsp_config(1);
- } else {
- unsigned long flags;
- local_irq_save(flags);
- if (audpp->enabled)
- audpp_fake_event(audpp, id,
- AUDPP_MSG_CFG_MSG, AUDPP_MSG_ENA_ENA);
- local_irq_restore(flags);
- }
-
- res = 0;
-out:
- mutex_unlock(audpp->lock);
- return res;
-}
-EXPORT_SYMBOL(audpp_enable);
-
-void audpp_disable(int id, void *private)
-{
- struct audpp_state *audpp = &the_audpp_state;
- unsigned long flags;
-
- if (id < -1 || id > 4)
- return;
-
- if (id == -1)
- id = 5;
-
- mutex_lock(audpp->lock);
- LOG(EV_DISABLE, 1);
- if (!audpp->func[id])
- goto out;
- if (audpp->private[id] != private)
- goto out;
-
- local_irq_save(flags);
- audpp_fake_event(audpp, id, AUDPP_MSG_CFG_MSG, AUDPP_MSG_ENA_DIS);
- audpp->func[id] = NULL;
- audpp->private[id] = NULL;
- local_irq_restore(flags);
-
- if (--audpp->open_count == 0) {
- pr_info("audpp: disable\n");
- LOG(EV_DISABLE, 2);
- audpp_dsp_config(0);
- msm_adsp_disable(audpp->mod);
- msm_adsp_put(audpp->mod);
- audpp->mod = NULL;
- }
-out:
- mutex_unlock(audpp->lock);
-}
-EXPORT_SYMBOL(audpp_disable);
-
-#define BAD_ID(id) ((id < 0) || (id >= CH_COUNT))
-
-void audpp_avsync(int id, unsigned rate)
-{
- unsigned long flags;
- audpp_cmd_avsync cmd;
-
- if (BAD_ID(id))
- return;
-
- local_irq_save(flags);
- if (rate)
- the_audpp_state.avsync_mask |= (1 << id);
- else
- the_audpp_state.avsync_mask &= (~(1 << id));
- the_audpp_state.avsync[0] &= the_audpp_state.avsync_mask;
- local_irq_restore(flags);
-
- cmd.cmd_id = AUDPP_CMD_AVSYNC;
- cmd.object_number = id;
- cmd.interrupt_interval_lsw = rate;
- cmd.interrupt_interval_msw = rate >> 16;
- audpp_send_queue1(&cmd, sizeof(cmd));
-}
-EXPORT_SYMBOL(audpp_avsync);
-
-unsigned audpp_avsync_sample_count(int id)
-{
- uint16_t *avsync = the_audpp_state.avsync;
- unsigned val;
- unsigned long flags;
- unsigned mask;
-
- if (BAD_ID(id))
- return 0;
-
- mask = 1 << id;
- id = id * AUDPP_AVSYNC_INFO_SIZE + 2;
- local_irq_save(flags);
- if (avsync[0] & mask)
- val = (avsync[id] << 16) | avsync[id + 1];
- else
- val = 0;
- local_irq_restore(flags);
-
- return val;
-}
-EXPORT_SYMBOL(audpp_avsync_sample_count);
-
-unsigned audpp_avsync_byte_count(int id)
-{
- uint16_t *avsync = the_audpp_state.avsync;
- unsigned val;
- unsigned long flags;
- unsigned mask;
-
- if (BAD_ID(id))
- return 0;
-
- mask = 1 << id;
- id = id * AUDPP_AVSYNC_INFO_SIZE + 5;
- local_irq_save(flags);
- if (avsync[0] & mask)
- val = (avsync[id] << 16) | avsync[id + 1];
- else
- val = 0;
- local_irq_restore(flags);
-
- return val;
-}
-EXPORT_SYMBOL(audpp_avsync_byte_count);
-
-#define AUDPP_CMD_CFG_OBJ_UPDATE 0x8000
-#define AUDPP_CMD_VOLUME_PAN 0
-
-int audpp_set_volume_and_pan(unsigned id, unsigned volume, int pan)
-{
- /* cmd, obj_cfg[7], cmd_type, volume, pan */
- uint16_t cmd[11];
-
- if (id > 6)
- return -EINVAL;
-
- memset(cmd, 0, sizeof(cmd));
- cmd[0] = AUDPP_CMD_CFG_OBJECT_PARAMS;
- cmd[1 + id] = AUDPP_CMD_CFG_OBJ_UPDATE;
- cmd[8] = AUDPP_CMD_VOLUME_PAN;
- cmd[9] = volume;
- cmd[10] = pan;
-
- return audpp_send_queue3(cmd, sizeof(cmd));
-}
-EXPORT_SYMBOL(audpp_set_volume_and_pan);
-
-int audpp_pause(unsigned id, int pause)
-{
- /* pause 1 = pause 0 = resume */
- u16 pause_cmd[AUDPP_CMD_DEC_CTRL_LEN / sizeof(unsigned short)];
-
- if (id >= CH_COUNT)
- return -EINVAL;
-
- memset(pause_cmd, 0, sizeof(pause_cmd));
-
- pause_cmd[0] = AUDPP_CMD_DEC_CTRL;
- if (pause == 1)
- pause_cmd[1 + id] = AUDPP_CMD_UPDATE_V | AUDPP_CMD_PAUSE_V;
- else if (pause == 0)
- pause_cmd[1 + id] = AUDPP_CMD_UPDATE_V | AUDPP_CMD_RESUME_V;
- else
- return -EINVAL;
-
- return audpp_send_queue1(pause_cmd, sizeof(pause_cmd));
-}
-EXPORT_SYMBOL(audpp_pause);
-
-int audpp_flush(unsigned id)
-{
- u16 flush_cmd[AUDPP_CMD_DEC_CTRL_LEN / sizeof(unsigned short)];
-
- if (id >= CH_COUNT)
- return -EINVAL;
-
- memset(flush_cmd, 0, sizeof(flush_cmd));
-
- flush_cmd[0] = AUDPP_CMD_DEC_CTRL;
- flush_cmd[1 + id] = AUDPP_CMD_UPDATE_V | AUDPP_CMD_FLUSH_V;
-
- return audpp_send_queue1(flush_cmd, sizeof(flush_cmd));
-}
-EXPORT_SYMBOL(audpp_flush);
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/evlog.h
- *
- * simple event log debugging facility
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/fs.h>
-#include <linux/hrtimer.h>
-#include <linux/debugfs.h>
-
-#define EV_LOG_ENTRY_NAME(n) n##_entry
-
-#define DECLARE_LOG(_name, _size, _str) \
-static struct ev_entry EV_LOG_ENTRY_NAME(_name)[_size]; \
-static struct ev_log _name = { \
- .name = #_name, \
- .strings = _str, \
- .num_strings = ARRAY_SIZE(_str), \
- .entry = EV_LOG_ENTRY_NAME(_name), \
- .max = ARRAY_SIZE(EV_LOG_ENTRY_NAME(_name)), \
-}
-
-struct ev_entry {
- ktime_t when;
- uint32_t id;
- uint32_t arg;
-};
-
-struct ev_log {
- struct ev_entry *entry;
- unsigned max;
- unsigned next;
- unsigned fault;
- const char **strings;
- unsigned num_strings;
- const char *name;
-};
-
-static char ev_buf[4096];
-
-static ssize_t ev_log_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- struct ev_log *log = file->private_data;
- struct ev_entry *entry;
- unsigned long flags;
- int size = 0;
- unsigned n, id, max;
- ktime_t now, t;
-
- max = log->max;
- now = ktime_get();
- local_irq_save(flags);
- n = (log->next - 1) & (max - 1);
- entry = log->entry;
- while (n != log->next) {
- t = ktime_sub(now, entry[n].when);
- id = entry[n].id;
- if (id) {
- const char *str;
- if (id < log->num_strings)
- str = log->strings[id];
- else
- str = "UNKNOWN";
- size += scnprintf(ev_buf + size, 4096 - size,
- "%8d.%03d %08x %s\n",
- t.tv.sec, t.tv.nsec / 1000000,
- entry[n].arg, str);
- }
- n = (n - 1) & (max - 1);
- }
- log->fault = 0;
- local_irq_restore(flags);
- return simple_read_from_buffer(buf, count, ppos, ev_buf, size);
-}
-
-static void ev_log_write(struct ev_log *log, unsigned id, unsigned arg)
-{
- struct ev_entry *entry;
- unsigned long flags;
- local_irq_save(flags);
-
- if (log->fault) {
- if (log->fault == 1)
- goto done;
- log->fault--;
- }
-
- entry = log->entry + log->next;
- entry->when = ktime_get();
- entry->id = id;
- entry->arg = arg;
- log->next = (log->next + 1) & (log->max - 1);
-done:
- local_irq_restore(flags);
-}
-
-static void ev_log_freeze(struct ev_log *log, unsigned count)
-{
- unsigned long flags;
- local_irq_save(flags);
- log->fault = count;
- local_irq_restore(flags);
-}
-
-static int ev_log_open(struct inode *inode, struct file *file)
-{
- file->private_data = inode->i_private;
- return 0;
-}
-
-static const struct file_operations ev_log_ops = {
- .read = ev_log_read,
- .open = ev_log_open,
- .llseek = default_llseek,
-};
-
-static int ev_log_init(struct ev_log *log)
-{
- debugfs_create_file(log->name, 0444, 0, log, &ev_log_ops);
- return 0;
-}
-
+++ /dev/null
-/* arch/arm/mach-msm/qdsp5/snd.c
- *
- * interface to "snd" service on the baseband cpu
- *
- * Copyright (C) 2008 HTC Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/uaccess.h>
-#include <linux/kthread.h>
-#include <linux/delay.h>
-#include <linux/msm_audio.h>
-
-#include <asm/atomic.h>
-#include <asm/ioctls.h>
-#include <mach/board.h>
-#include <mach/msm_rpcrouter.h>
-
-struct snd_ctxt {
- struct mutex lock;
- int opened;
- struct msm_rpc_endpoint *ept;
- struct msm_snd_endpoints *snd_epts;
-};
-
-static struct snd_ctxt the_snd;
-
-#define RPC_SND_PROG 0x30000002
-#define RPC_SND_CB_PROG 0x31000002
-#if CONFIG_MSM_AMSS_VERSION == 6210
-#define RPC_SND_VERS 0x94756085 /* 2490720389 */
-#elif (CONFIG_MSM_AMSS_VERSION == 6220) || \
- (CONFIG_MSM_AMSS_VERSION == 6225)
-#define RPC_SND_VERS 0xaa2b1a44 /* 2854951492 */
-#elif CONFIG_MSM_AMSS_VERSION == 6350
-#define RPC_SND_VERS MSM_RPC_VERS(1,0)
-#endif
-
-#define SND_SET_DEVICE_PROC 2
-#define SND_SET_VOLUME_PROC 3
-
-struct rpc_snd_set_device_args {
- uint32_t device;
- uint32_t ear_mute;
- uint32_t mic_mute;
-
- uint32_t cb_func;
- uint32_t client_data;
-};
-
-struct rpc_snd_set_volume_args {
- uint32_t device;
- uint32_t method;
- uint32_t volume;
-
- uint32_t cb_func;
- uint32_t client_data;
-};
-
-struct snd_set_device_msg {
- struct rpc_request_hdr hdr;
- struct rpc_snd_set_device_args args;
-};
-
-struct snd_set_volume_msg {
- struct rpc_request_hdr hdr;
- struct rpc_snd_set_volume_args args;
-};
-
-struct snd_endpoint *get_snd_endpoints(int *size);
-
-static inline int check_mute(int mute)
-{
- return (mute == SND_MUTE_MUTED ||
- mute == SND_MUTE_UNMUTED) ? 0 : -EINVAL;
-}
-
-static int get_endpoint(struct snd_ctxt *snd, unsigned long arg)
-{
- int rc = 0, index;
- struct msm_snd_endpoint ept;
-
- if (copy_from_user(&ept, (void __user *)arg, sizeof(ept))) {
- pr_err("snd_ioctl get endpoint: invalid read pointer.\n");
- return -EFAULT;
- }
-
- index = ept.id;
- if (index < 0 || index >= snd->snd_epts->num) {
- pr_err("snd_ioctl get endpoint: invalid index!\n");
- return -EINVAL;
- }
-
- ept.id = snd->snd_epts->endpoints[index].id;
- strncpy(ept.name,
- snd->snd_epts->endpoints[index].name,
- sizeof(ept.name));
-
- if (copy_to_user((void __user *)arg, &ept, sizeof(ept))) {
- pr_err("snd_ioctl get endpoint: invalid write pointer.\n");
- rc = -EFAULT;
- }
-
- return rc;
-}
-
-static long snd_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct snd_set_device_msg dmsg;
- struct snd_set_volume_msg vmsg;
- struct msm_snd_device_config dev;
- struct msm_snd_volume_config vol;
- struct snd_ctxt *snd = file->private_data;
- int rc = 0;
-
- mutex_lock(&snd->lock);
- switch (cmd) {
- case SND_SET_DEVICE:
- if (copy_from_user(&dev, (void __user *) arg, sizeof(dev))) {
- pr_err("snd_ioctl set device: invalid pointer.\n");
- rc = -EFAULT;
- break;
- }
-
- dmsg.args.device = cpu_to_be32(dev.device);
- dmsg.args.ear_mute = cpu_to_be32(dev.ear_mute);
- dmsg.args.mic_mute = cpu_to_be32(dev.mic_mute);
- if (check_mute(dev.ear_mute) < 0 ||
- check_mute(dev.mic_mute) < 0) {
- pr_err("snd_ioctl set device: invalid mute status.\n");
- rc = -EINVAL;
- break;
- }
- dmsg.args.cb_func = -1;
- dmsg.args.client_data = 0;
-
- pr_info("snd_set_device %d %d %d\n", dev.device,
- dev.ear_mute, dev.mic_mute);
-
- rc = msm_rpc_call(snd->ept,
- SND_SET_DEVICE_PROC,
- &dmsg, sizeof(dmsg), 5 * HZ);
- break;
-
- case SND_SET_VOLUME:
- if (copy_from_user(&vol, (void __user *) arg, sizeof(vol))) {
- pr_err("snd_ioctl set volume: invalid pointer.\n");
- rc = -EFAULT;
- break;
- }
-
- vmsg.args.device = cpu_to_be32(vol.device);
- vmsg.args.method = cpu_to_be32(vol.method);
- if (vol.method != SND_METHOD_VOICE) {
- pr_err("snd_ioctl set volume: invalid method.\n");
- rc = -EINVAL;
- break;
- }
-
- vmsg.args.volume = cpu_to_be32(vol.volume);
- vmsg.args.cb_func = -1;
- vmsg.args.client_data = 0;
-
- pr_info("snd_set_volume %d %d %d\n", vol.device,
- vol.method, vol.volume);
-
- rc = msm_rpc_call(snd->ept,
- SND_SET_VOLUME_PROC,
- &vmsg, sizeof(vmsg), 5 * HZ);
- break;
-
- case SND_GET_NUM_ENDPOINTS:
- if (copy_to_user((void __user *)arg,
- &snd->snd_epts->num, sizeof(unsigned))) {
- pr_err("snd_ioctl get endpoint: invalid pointer.\n");
- rc = -EFAULT;
- }
- break;
-
- case SND_GET_ENDPOINT:
- rc = get_endpoint(snd, arg);
- break;
-
- default:
- pr_err("snd_ioctl unknown command.\n");
- rc = -EINVAL;
- break;
- }
- mutex_unlock(&snd->lock);
-
- return rc;
-}
-
-static int snd_release(struct inode *inode, struct file *file)
-{
- struct snd_ctxt *snd = file->private_data;
-
- mutex_lock(&snd->lock);
- snd->opened = 0;
- mutex_unlock(&snd->lock);
- return 0;
-}
-
-static int snd_open(struct inode *inode, struct file *file)
-{
- struct snd_ctxt *snd = &the_snd;
- int rc = 0;
-
- mutex_lock(&snd->lock);
- if (snd->opened == 0) {
- if (snd->ept == NULL) {
- snd->ept = msm_rpc_connect(RPC_SND_PROG, RPC_SND_VERS,
- MSM_RPC_UNINTERRUPTIBLE);
- if (IS_ERR(snd->ept)) {
- rc = PTR_ERR(snd->ept);
- snd->ept = NULL;
- pr_err("snd: failed to connect snd svc\n");
- goto err;
- }
- }
- file->private_data = snd;
- snd->opened = 1;
- } else {
- pr_err("snd already opened.\n");
- rc = -EBUSY;
- }
-
-err:
- mutex_unlock(&snd->lock);
- return rc;
-}
-
-static struct file_operations snd_fops = {
- .owner = THIS_MODULE,
- .open = snd_open,
- .release = snd_release,
- .unlocked_ioctl = snd_ioctl,
- .llseek = noop_llseek,
-};
-
-struct miscdevice snd_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_snd",
- .fops = &snd_fops,
-};
-
-static int snd_probe(struct platform_device *pdev)
-{
- struct snd_ctxt *snd = &the_snd;
- mutex_init(&snd->lock);
- snd->snd_epts = (struct msm_snd_endpoints *)pdev->dev.platform_data;
- return misc_register(&snd_misc);
-}
-
-static struct platform_driver snd_plat_driver = {
- .probe = snd_probe,
- .driver = {
- .name = "msm_snd",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init snd_init(void)
-{
- return platform_driver_register(&snd_plat_driver);
-}
-
-module_init(snd_init);
+++ /dev/null
-/*
- * Support for synaptics touchscreen.
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Arve Hjønnevåg <arve@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * http://www.synaptics.com/sites/default/files/511_000099_01F.pdf
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#ifdef CONFIG_HAS_EARLYSUSPEND
-#include <linux/earlysuspend.h>
-#endif
-#include <linux/hrtimer.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include "synaptics_i2c_rmi.h"
-
-static struct workqueue_struct *synaptics_wq;
-
-struct synaptics_ts_data {
- u16 addr;
- struct i2c_client *client;
- struct input_dev *input_dev;
- int use_irq;
- struct hrtimer timer;
- struct work_struct work;
- u16 max[2];
- int snap_state[2][2];
- int snap_down_on[2];
- int snap_down_off[2];
- int snap_up_on[2];
- int snap_up_off[2];
- int snap_down[2];
- int snap_up[2];
- u32 flags;
- int (*power)(int on);
-#ifdef CONFIG_HAS_EARLYSUSPEND
- struct early_suspend early_suspend;
-#endif
-};
-
-static int i2c_set(struct synaptics_ts_data *ts, u8 reg, u8 val, char *msg)
-{
- int ret = i2c_smbus_write_byte_data(ts->client, reg, val);
- if (ret < 0)
- pr_err("i2c_smbus_write_byte_data failed (%s)\n", msg);
- return ret;
-}
-
-static int i2c_read(struct synaptics_ts_data *ts, u8 reg, char *msg)
-{
- int ret = i2c_smbus_read_byte_data(ts->client, reg);
- if (ret < 0)
- pr_err("i2c_smbus_read_byte_data failed (%s)\n", msg);
- return ret;
-}
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void synaptics_ts_early_suspend(struct early_suspend *h);
-static void synaptics_ts_late_resume(struct early_suspend *h);
-#endif
-
-static int synaptics_init_panel(struct synaptics_ts_data *ts)
-{
- int ret;
-
- ret = i2c_set(ts, 0xff, 0x10, "set page select");
- if (ret == 0)
- ret = i2c_set(ts, 0x41, 0x04, "set No Clip Z");
-
- ret = i2c_set(ts, 0xff, 0x04, "fallback page select");
- ret = i2c_set(ts, 0xf0, 0x81, "select 80 reports per second");
- return ret;
-}
-
-static void decode_report(struct synaptics_ts_data *ts, u8 *buf)
-{
-/*
- * This sensor sends two 6-byte absolute finger reports, an optional
- * 2-byte relative report followed by a status byte. This function
- * reads the two finger reports and transforms the coordinates
- * according the platform data so they can be aligned with the lcd
- * behind the touchscreen. Typically we flip the y-axis since the
- * sensor uses the bottom left corner as the origin, but if the sensor
- * is mounted upside down the platform data will request that the
- * x-axis should be flipped instead. The snap to inactive edge border
- * are used to allow tapping the edges of the screen on the G1. The
- * active area of the touchscreen is smaller than the lcd. When the
- * finger gets close the edge of the screen we snap it to the
- * edge. This allows ui elements at the edge of the screen to be hit,
- * and it prevents hitting ui elements that are not at the edge of the
- * screen when the finger is touching the edge.
- */
- int pos[2][2];
- int f, a;
- int base = 2;
- int z = buf[1];
- int finger = buf[0] & 7;
-
- for (f = 0; f < 2; f++) {
- u32 flip_flag = SYNAPTICS_FLIP_X;
- for (a = 0; a < 2; a++) {
- int p = buf[base + 1];
- p |= (u16)(buf[base] & 0x1f) << 8;
- if (ts->flags & flip_flag)
- p = ts->max[a] - p;
- if (ts->flags & SYNAPTICS_SNAP_TO_INACTIVE_EDGE) {
- if (ts->snap_state[f][a]) {
- if (p <= ts->snap_down_off[a])
- p = ts->snap_down[a];
- else if (p >= ts->snap_up_off[a])
- p = ts->snap_up[a];
- else
- ts->snap_state[f][a] = 0;
- } else {
- if (p <= ts->snap_down_on[a]) {
- p = ts->snap_down[a];
- ts->snap_state[f][a] = 1;
- } else if (p >= ts->snap_up_on[a]) {
- p = ts->snap_up[a];
- ts->snap_state[f][a] = 1;
- }
- }
- }
- pos[f][a] = p;
- base += 2;
- flip_flag <<= 1;
- }
- base += 2;
- if (ts->flags & SYNAPTICS_SWAP_XY)
- swap(pos[f][0], pos[f][1]);
- }
- if (z) {
- input_report_abs(ts->input_dev, ABS_X, pos[0][0]);
- input_report_abs(ts->input_dev, ABS_Y, pos[0][1]);
- }
- input_report_abs(ts->input_dev, ABS_PRESSURE, z);
- input_report_key(ts->input_dev, BTN_TOUCH, finger);
- input_sync(ts->input_dev);
-}
-
-static void synaptics_ts_work_func(struct work_struct *work)
-{
- int i;
- int ret;
- int bad_data = 0;
- struct i2c_msg msg[2];
- u8 start_reg = 0;
- u8 buf[15];
- struct synaptics_ts_data *ts =
- container_of(work, struct synaptics_ts_data, work);
-
- msg[0].addr = ts->client->addr;
- msg[0].flags = 0;
- msg[0].len = 1;
- msg[0].buf = &start_reg;
- msg[1].addr = ts->client->addr;
- msg[1].flags = I2C_M_RD;
- msg[1].len = sizeof(buf);
- msg[1].buf = buf;
-
- for (i = 0; i < ((ts->use_irq && !bad_data) ? 1 : 10); i++) {
- ret = i2c_transfer(ts->client->adapter, msg, 2);
- if (ret < 0) {
- pr_err("ts_work: i2c_transfer failed\n");
- bad_data = 1;
- continue;
- }
- if ((buf[14] & 0xc0) != 0x40) {
- pr_warning("synaptics_ts_work_func:"
- " bad read %x %x %x %x %x %x %x %x %x"
- " %x %x %x %x %x %x, ret %d\n",
- buf[0], buf[1], buf[2], buf[3],
- buf[4], buf[5], buf[6], buf[7],
- buf[8], buf[9], buf[10], buf[11],
- buf[12], buf[13], buf[14], ret);
- if (bad_data)
- synaptics_init_panel(ts);
- bad_data = 1;
- continue;
- }
- bad_data = 0;
- if ((buf[14] & 1) == 0)
- break;
-
- decode_report(ts, buf);
- }
-}
-
-static enum hrtimer_restart synaptics_ts_timer_func(struct hrtimer *timer)
-{
- struct synaptics_ts_data *ts =
- container_of(timer, struct synaptics_ts_data, timer);
-
- queue_work(synaptics_wq, &ts->work);
-
- hrtimer_start(&ts->timer, ktime_set(0, 12500000), HRTIMER_MODE_REL);
- return HRTIMER_NORESTART;
-}
-
-static irqreturn_t synaptics_ts_irq_handler(int irq, void *dev_id)
-{
- struct synaptics_ts_data *ts = dev_id;
-
- synaptics_ts_work_func(&ts->work);
- return IRQ_HANDLED;
-}
-
-static int detect(struct synaptics_ts_data *ts, u32 *panel_version)
-{
- int ret;
- int retry = 10;
-
- ret = i2c_set(ts, 0xf4, 0x01, "reset device");
-
- while (retry-- > 0) {
- ret = i2c_smbus_read_byte_data(ts->client, 0xe4);
- if (ret >= 0)
- break;
- msleep(100);
- }
- if (ret < 0) {
- pr_err("i2c_smbus_read_byte_data failed\n");
- return ret;
- }
-
- *panel_version = ret << 8;
- ret = i2c_read(ts, 0xe5, "product minor");
- if (ret < 0)
- return ret;
- *panel_version |= ret;
-
- ret = i2c_read(ts, 0xe3, "property");
- if (ret < 0)
- return ret;
-
- pr_info("synaptics: version %x, product property %x\n",
- *panel_version, ret);
- return 0;
-}
-
-static void compute_areas(struct synaptics_ts_data *ts,
- struct synaptics_i2c_rmi_platform_data *pdata,
- u16 max_x, u16 max_y)
-{
- int inactive_area_left;
- int inactive_area_right;
- int inactive_area_top;
- int inactive_area_bottom;
- int snap_left_on;
- int snap_left_off;
- int snap_right_on;
- int snap_right_off;
- int snap_top_on;
- int snap_top_off;
- int snap_bottom_on;
- int snap_bottom_off;
- int fuzz_x;
- int fuzz_y;
- int fuzz_p;
- int fuzz_w;
- int swapped = !!(ts->flags & SYNAPTICS_SWAP_XY);
-
- inactive_area_left = pdata->inactive_left;
- inactive_area_right = pdata->inactive_right;
- inactive_area_top = pdata->inactive_top;
- inactive_area_bottom = pdata->inactive_bottom;
- snap_left_on = pdata->snap_left_on;
- snap_left_off = pdata->snap_left_off;
- snap_right_on = pdata->snap_right_on;
- snap_right_off = pdata->snap_right_off;
- snap_top_on = pdata->snap_top_on;
- snap_top_off = pdata->snap_top_off;
- snap_bottom_on = pdata->snap_bottom_on;
- snap_bottom_off = pdata->snap_bottom_off;
- fuzz_x = pdata->fuzz_x;
- fuzz_y = pdata->fuzz_y;
- fuzz_p = pdata->fuzz_p;
- fuzz_w = pdata->fuzz_w;
-
- inactive_area_left = inactive_area_left * max_x / 0x10000;
- inactive_area_right = inactive_area_right * max_x / 0x10000;
- inactive_area_top = inactive_area_top * max_y / 0x10000;
- inactive_area_bottom = inactive_area_bottom * max_y / 0x10000;
- snap_left_on = snap_left_on * max_x / 0x10000;
- snap_left_off = snap_left_off * max_x / 0x10000;
- snap_right_on = snap_right_on * max_x / 0x10000;
- snap_right_off = snap_right_off * max_x / 0x10000;
- snap_top_on = snap_top_on * max_y / 0x10000;
- snap_top_off = snap_top_off * max_y / 0x10000;
- snap_bottom_on = snap_bottom_on * max_y / 0x10000;
- snap_bottom_off = snap_bottom_off * max_y / 0x10000;
- fuzz_x = fuzz_x * max_x / 0x10000;
- fuzz_y = fuzz_y * max_y / 0x10000;
-
-
- ts->snap_down[swapped] = -inactive_area_left;
- ts->snap_up[swapped] = max_x + inactive_area_right;
- ts->snap_down[!swapped] = -inactive_area_top;
- ts->snap_up[!swapped] = max_y + inactive_area_bottom;
- ts->snap_down_on[swapped] = snap_left_on;
- ts->snap_down_off[swapped] = snap_left_off;
- ts->snap_up_on[swapped] = max_x - snap_right_on;
- ts->snap_up_off[swapped] = max_x - snap_right_off;
- ts->snap_down_on[!swapped] = snap_top_on;
- ts->snap_down_off[!swapped] = snap_top_off;
- ts->snap_up_on[!swapped] = max_y - snap_bottom_on;
- ts->snap_up_off[!swapped] = max_y - snap_bottom_off;
- pr_info("synaptics_ts_probe: max_x %d, max_y %d\n", max_x, max_y);
- pr_info("synaptics_ts_probe: inactive_x %d %d, inactive_y %d %d\n",
- inactive_area_left, inactive_area_right,
- inactive_area_top, inactive_area_bottom);
- pr_info("synaptics_ts_probe: snap_x %d-%d %d-%d, snap_y %d-%d %d-%d\n",
- snap_left_on, snap_left_off, snap_right_on, snap_right_off,
- snap_top_on, snap_top_off, snap_bottom_on, snap_bottom_off);
-
- input_set_abs_params(ts->input_dev, ABS_X,
- -inactive_area_left, max_x + inactive_area_right,
- fuzz_x, 0);
- input_set_abs_params(ts->input_dev, ABS_Y,
- -inactive_area_top, max_y + inactive_area_bottom,
- fuzz_y, 0);
- input_set_abs_params(ts->input_dev, ABS_PRESSURE, 0, 255, fuzz_p, 0);
-}
-
-static struct synaptics_i2c_rmi_platform_data fake_pdata;
-
-static int __devinit synaptics_ts_probe(
- struct i2c_client *client, const struct i2c_device_id *id)
-{
- struct synaptics_ts_data *ts;
- u8 buf0[4];
- u8 buf1[8];
- struct i2c_msg msg[2];
- int ret = 0;
- struct synaptics_i2c_rmi_platform_data *pdata;
- u32 panel_version = 0;
- u16 max_x, max_y;
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
- pr_err("synaptics_ts_probe: need I2C_FUNC_I2C\n");
- ret = -ENODEV;
- goto err_check_functionality_failed;
- }
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
- pr_err("synaptics_ts_probe: need I2C_FUNC_SMBUS_WORD_DATA\n");
- ret = -ENODEV;
- goto err_check_functionality_failed;
- }
-
- if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
- pr_err("synaptics_ts_probe: need I2C_FUNC_SMBUS_WORD_DATA\n");
- ret = -ENODEV;
- goto err_check_functionality_failed;
- }
-
- ts = kzalloc(sizeof(*ts), GFP_KERNEL);
- if (ts == NULL) {
- ret = -ENOMEM;
- goto err_alloc_data_failed;
- }
- INIT_WORK(&ts->work, synaptics_ts_work_func);
- ts->client = client;
- i2c_set_clientdata(client, ts);
- pdata = client->dev.platform_data;
- if (pdata)
- ts->power = pdata->power;
- else
- pdata = &fake_pdata;
-
- if (ts->power) {
- ret = ts->power(1);
- if (ret < 0) {
- pr_err("synaptics_ts_probe power on failed\n");
- goto err_power_failed;
- }
- }
-
- ret = detect(ts, &panel_version);
- if (ret)
- goto err_detect_failed;
-
- while (pdata->version > panel_version)
- pdata++;
- ts->flags = pdata->flags;
-
- ret = i2c_read(ts, 0xf0, "device control");
- if (ret < 0)
- goto err_detect_failed;
- pr_info("synaptics: device control %x\n", ret);
-
- ret = i2c_read(ts, 0xf1, "interrupt enable");
- if (ret < 0)
- goto err_detect_failed;
- pr_info("synaptics_ts_probe: interrupt enable %x\n", ret);
-
- ret = i2c_set(ts, 0xf1, 0, "disable interrupt");
- if (ret < 0)
- goto err_detect_failed;
-
- msg[0].addr = ts->client->addr;
- msg[0].flags = 0;
- msg[0].len = 1;
- msg[0].buf = buf0;
- buf0[0] = 0xe0;
- msg[1].addr = ts->client->addr;
- msg[1].flags = I2C_M_RD;
- msg[1].len = 8;
- msg[1].buf = buf1;
- ret = i2c_transfer(ts->client->adapter, msg, 2);
- if (ret < 0) {
- pr_err("i2c_transfer failed\n");
- goto err_detect_failed;
- }
- pr_info("synaptics_ts_probe: 0xe0: %x %x %x %x %x %x %x %x\n",
- buf1[0], buf1[1], buf1[2], buf1[3],
- buf1[4], buf1[5], buf1[6], buf1[7]);
-
- ret = i2c_set(ts, 0xff, 0x10, "page select = 0x10");
- if (ret < 0)
- goto err_detect_failed;
-
- ret = i2c_smbus_read_word_data(ts->client, 0x04);
- if (ret < 0) {
- pr_err("i2c_smbus_read_word_data failed\n");
- goto err_detect_failed;
- }
- ts->max[0] = max_x = (ret >> 8 & 0xff) | ((ret & 0x1f) << 8);
- ret = i2c_smbus_read_word_data(ts->client, 0x06);
- if (ret < 0) {
- pr_err("i2c_smbus_read_word_data failed\n");
- goto err_detect_failed;
- }
- ts->max[1] = max_y = (ret >> 8 & 0xff) | ((ret & 0x1f) << 8);
- if (ts->flags & SYNAPTICS_SWAP_XY)
- swap(max_x, max_y);
-
- /* will also switch back to page 0x04 */
- ret = synaptics_init_panel(ts);
- if (ret < 0) {
- pr_err("synaptics_init_panel failed\n");
- goto err_detect_failed;
- }
-
- ts->input_dev = input_allocate_device();
- if (ts->input_dev == NULL) {
- ret = -ENOMEM;
- pr_err("synaptics: Failed to allocate input device\n");
- goto err_input_dev_alloc_failed;
- }
- ts->input_dev->name = "synaptics-rmi-touchscreen";
- ts->input_dev->phys = "msm/input0";
- ts->input_dev->id.bustype = BUS_I2C;
-
- __set_bit(EV_SYN, ts->input_dev->evbit);
- __set_bit(EV_KEY, ts->input_dev->evbit);
- __set_bit(BTN_TOUCH, ts->input_dev->keybit);
- __set_bit(EV_ABS, ts->input_dev->evbit);
-
- compute_areas(ts, pdata, max_x, max_y);
-
-
- ret = input_register_device(ts->input_dev);
- if (ret) {
- pr_err("synaptics: Unable to register %s input device\n",
- ts->input_dev->name);
- goto err_input_register_device_failed;
- }
- if (client->irq) {
- ret = request_threaded_irq(client->irq, NULL,
- synaptics_ts_irq_handler,
- IRQF_TRIGGER_LOW|IRQF_ONESHOT,
- client->name, ts);
- if (ret == 0) {
- ret = i2c_set(ts, 0xf1, 0x01, "enable abs int");
- if (ret)
- free_irq(client->irq, ts);
- }
- if (ret == 0)
- ts->use_irq = 1;
- else
- dev_err(&client->dev, "request_irq failed\n");
- }
- if (!ts->use_irq) {
- hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- ts->timer.function = synaptics_ts_timer_func;
- hrtimer_start(&ts->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
- }
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
- ts->early_suspend.suspend = synaptics_ts_early_suspend;
- ts->early_suspend.resume = synaptics_ts_late_resume;
- register_early_suspend(&ts->early_suspend);
-#endif
-
- pr_info("synaptics: Start touchscreen %s in %s mode\n",
- ts->input_dev->name, ts->use_irq ? "interrupt" : "polling");
-
- return 0;
-
-err_input_register_device_failed:
- input_free_device(ts->input_dev);
-
-err_input_dev_alloc_failed:
-err_detect_failed:
-err_power_failed:
- kfree(ts);
-err_alloc_data_failed:
-err_check_functionality_failed:
- return ret;
-}
-
-static int synaptics_ts_remove(struct i2c_client *client)
-{
- struct synaptics_ts_data *ts = i2c_get_clientdata(client);
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ts->early_suspend);
-#endif
- if (ts->use_irq)
- free_irq(client->irq, ts);
- else
- hrtimer_cancel(&ts->timer);
- input_unregister_device(ts->input_dev);
- kfree(ts);
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int synaptics_ts_suspend(struct i2c_client *client, pm_message_t mesg)
-{
- int ret;
- struct synaptics_ts_data *ts = i2c_get_clientdata(client);
-
- if (ts->use_irq)
- disable_irq(client->irq);
- else
- hrtimer_cancel(&ts->timer);
- ret = cancel_work_sync(&ts->work);
- if (ret && ts->use_irq) /* if work was pending disable-count is now 2 */
- enable_irq(client->irq);
- i2c_set(ts, 0xf1, 0, "disable interrupt");
- i2c_set(ts, 0xf0, 0x86, "deep sleep");
-
- if (ts->power) {
- ret = ts->power(0);
- if (ret < 0)
- pr_err("synaptics_ts_suspend power off failed\n");
- }
- return 0;
-}
-
-static int synaptics_ts_resume(struct i2c_client *client)
-{
- int ret;
- struct synaptics_ts_data *ts = i2c_get_clientdata(client);
-
- if (ts->power) {
- ret = ts->power(1);
- if (ret < 0)
- pr_err("synaptics_ts_resume power on failed\n");
- }
-
- synaptics_init_panel(ts);
-
- if (ts->use_irq) {
- enable_irq(client->irq);
- i2c_set(ts, 0xf1, 0x01, "enable abs int");
- } else
- hrtimer_start(&ts->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
-
- return 0;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void synaptics_ts_early_suspend(struct early_suspend *h)
-{
- struct synaptics_ts_data *ts;
- ts = container_of(h, struct synaptics_ts_data, early_suspend);
- synaptics_ts_suspend(ts->client, PMSG_SUSPEND);
-}
-
-static void synaptics_ts_late_resume(struct early_suspend *h)
-{
- struct synaptics_ts_data *ts;
- ts = container_of(h, struct synaptics_ts_data, early_suspend);
- synaptics_ts_resume(ts->client);
-}
-#endif
-#else
-#define synaptics_ts_suspend NULL
-#define synaptics_ts_resume NULL
-#endif
-
-
-
-static const struct i2c_device_id synaptics_ts_id[] = {
- { SYNAPTICS_I2C_RMI_NAME, 0 },
- { }
-};
-
-static struct i2c_driver synaptics_ts_driver = {
- .probe = synaptics_ts_probe,
- .remove = synaptics_ts_remove,
-#ifndef CONFIG_HAS_EARLYSUSPEND
- .suspend = synaptics_ts_suspend,
- .resume = synaptics_ts_resume,
-#endif
- .id_table = synaptics_ts_id,
- .driver = {
- .name = SYNAPTICS_I2C_RMI_NAME,
- },
-};
-
-static int __devinit synaptics_ts_init(void)
-{
- synaptics_wq = create_singlethread_workqueue("synaptics_wq");
- if (!synaptics_wq)
- return -ENOMEM;
- return i2c_add_driver(&synaptics_ts_driver);
-}
-
-static void __exit synaptics_ts_exit(void)
-{
- i2c_del_driver(&synaptics_ts_driver);
- if (synaptics_wq)
- destroy_workqueue(synaptics_wq);
-}
-
-module_init(synaptics_ts_init);
-module_exit(synaptics_ts_exit);
-
-MODULE_DESCRIPTION("Synaptics Touchscreen Driver");
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Arve Hjønnevåg <arve@android.com>");
+++ /dev/null
-/*
- * include/linux/synaptics_i2c_rmi.h - platform data structure for f75375s sensor
- *
- * Copyright (C) 2008 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _LINUX_SYNAPTICS_I2C_RMI_H
-#define _LINUX_SYNAPTICS_I2C_RMI_H
-
-#define SYNAPTICS_I2C_RMI_NAME "synaptics-rmi-ts"
-
-enum {
- SYNAPTICS_FLIP_X = 1UL << 0,
- SYNAPTICS_FLIP_Y = 1UL << 1,
- SYNAPTICS_SWAP_XY = 1UL << 2,
- SYNAPTICS_SNAP_TO_INACTIVE_EDGE = 1UL << 3,
-};
-
-struct synaptics_i2c_rmi_platform_data {
- uint32_t version; /* Use this entry for panels with */
- /* (major << 8 | minor) version or above. */
- /* If non-zero another array entry follows */
- int (*power)(int on); /* Only valid in first array entry */
- uint32_t flags;
- uint32_t inactive_left; /* 0x10000 = screen width */
- uint32_t inactive_right; /* 0x10000 = screen width */
- uint32_t inactive_top; /* 0x10000 = screen height */
- uint32_t inactive_bottom; /* 0x10000 = screen height */
- uint32_t snap_left_on; /* 0x10000 = screen width */
- uint32_t snap_left_off; /* 0x10000 = screen width */
- uint32_t snap_right_on; /* 0x10000 = screen width */
- uint32_t snap_right_off; /* 0x10000 = screen width */
- uint32_t snap_top_on; /* 0x10000 = screen height */
- uint32_t snap_top_off; /* 0x10000 = screen height */
- uint32_t snap_bottom_on; /* 0x10000 = screen height */
- uint32_t snap_bottom_off; /* 0x10000 = screen height */
- uint32_t fuzz_x; /* 0x10000 = screen width */
- uint32_t fuzz_y; /* 0x10000 = screen height */
- int fuzz_p;
- int fuzz_w;
-};
-
-#endif /* _LINUX_SYNAPTICS_I2C_RMI_H */
/*
* Some VFS magic here...
*/
-static int pohmelfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *pohmelfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, pohmelfs_fill_super,
- mnt);
+ return mount_nodev(fs_type, flags, data, pohmelfs_fill_super);
}
/*
static struct file_system_type pohmel_fs_type = {
.owner = THIS_MODULE,
.name = "pohmel",
- .get_sb = pohmelfs_get_sb,
+ .mount = pohmelfs_mount,
.kill_sb = pohmelfs_kill_super,
};
return error;
}
-static int smb_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *smb_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, smb_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, smb_fill_super);
}
static struct file_system_type smb_fs_type = {
.owner = THIS_MODULE,
.name = "smbfs",
- .get_sb = smb_get_sb,
+ .mount = smb_mount,
.kill_sb = kill_anon_super,
.fs_flags = FS_BINARY_MOUNTDATA,
};
/* --------------------------------------------------------------------- */
-static int usb_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *usb_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, usbfs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, usbfs_fill_super);
}
static struct file_system_type usb_fs_type = {
.owner = THIS_MODULE,
.name = "usbfs",
- .get_sb = usb_get_sb,
+ .mount = usb_mount,
.kill_sb = kill_litter_super,
};
/* "mount -t functionfs dev_name /dev/function" ends up here */
-static int
-ffs_fs_get_sb(struct file_system_type *t, int flags,
- const char *dev_name, void *opts, struct vfsmount *mnt)
+static struct dentry *
+ffs_fs_mount(struct file_system_type *t, int flags,
+ const char *dev_name, void *opts)
{
struct ffs_sb_fill_data data = {
.perms = {
ret = functionfs_check_dev_callback(dev_name);
if (unlikely(ret < 0))
- return ret;
+ return ERR_PTR(ret);
ret = ffs_fs_parse_opts(&data, opts);
if (unlikely(ret < 0))
- return ret;
+ return ERR_PTR(ret);
data.dev_name = dev_name;
- return get_sb_single(t, flags, &data, ffs_sb_fill, mnt);
+ return mount_single(t, flags, &data, ffs_sb_fill);
}
static void
static struct file_system_type ffs_fs_type = {
.owner = THIS_MODULE,
.name = "functionfs",
- .get_sb = ffs_fs_get_sb,
+ .mount = ffs_fs_mount,
.kill_sb = ffs_fs_kill_sb,
};
}
/* "mount -t gadgetfs path /dev/gadget" ends up here */
-static int
-gadgetfs_get_sb (struct file_system_type *t, int flags,
- const char *path, void *opts, struct vfsmount *mnt)
+static struct dentry *
+gadgetfs_mount (struct file_system_type *t, int flags,
+ const char *path, void *opts)
{
- return get_sb_single (t, flags, opts, gadgetfs_fill_super, mnt);
+ return mount_single (t, flags, opts, gadgetfs_fill_super);
}
static void
static struct file_system_type gadgetfs_type = {
.owner = THIS_MODULE,
.name = shortname,
- .get_sb = gadgetfs_get_sb,
+ .mount = gadgetfs_mount,
.kill_sb = gadgetfs_kill_sb,
};
* - iff DATA transfer is active, carrier is "on"
* - tx queueing enabled if open *and* carrier is "on"
*/
- netif_stop_queue(net);
netif_carrier_off(net);
dev->gadget = g;
INFO(dev, "MAC %pM\n", net->dev_addr);
INFO(dev, "HOST MAC %pM\n", dev->host_mac);
+ netif_stop_queue(net);
the_dev = dev;
}
config USB_EHCI_BIG_ENDIAN_MMIO
bool
- depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || \
- XPS_USB_HCD_XILINX || PPC_MPC512x)
+ depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
+ ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
+ PPC_MPC512x || CPU_CAVIUM_OCTEON)
default y
config USB_EHCI_BIG_ENDIAN_DESC
To compile this driver as a module, choose M here: the
module will be called "imx21-hcd".
+config USB_OCTEON_EHCI
+ bool "Octeon on-chip EHCI support"
+ depends on USB && USB_EHCI_HCD && CPU_CAVIUM_OCTEON
+ default n
+ select USB_EHCI_BIG_ENDIAN_MMIO
+ help
+ Enable support for the Octeon II SOC's on-chip EHCI
+ controller. It is needed for high-speed (480Mbit/sec)
+ USB 2.0 device support. All CN6XXX based chips with USB are
+ supported.
+
+config USB_OCTEON_OHCI
+ bool "Octeon on-chip OHCI support"
+ depends on USB && USB_OHCI_HCD && CPU_CAVIUM_OCTEON
+ default USB_OCTEON_EHCI
+ select USB_OHCI_BIG_ENDIAN_MMIO
+ select USB_OHCI_LITTLE_ENDIAN
+ help
+ Enable support for the Octeon II SOC's on-chip OHCI
+ controller. It is needed for low-speed USB 1.0 device
+ support. All CN6XXX based chips with USB are supported.
+
+config USB_OCTEON2_COMMON
+ bool
+ default y if USB_OCTEON_EHCI || USB_OCTEON_OHCI
obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
+obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o
#define PLATFORM_DRIVER ehci_atmel_driver
#endif
+#ifdef CONFIG_USB_OCTEON_EHCI
+#include "ehci-octeon.c"
+#define PLATFORM_DRIVER ehci_octeon_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
!defined(XILINX_OF_PLATFORM_DRIVER)
--- /dev/null
+/*
+ * EHCI HCD glue for Cavium Octeon II SOCs.
+ *
+ * Loosely based on ehci-au1xxx.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+#define OCTEON_EHCI_HCD_NAME "octeon-ehci"
+
+/* Common clock init code. */
+void octeon2_usb_clocks_start(void);
+void octeon2_usb_clocks_stop(void);
+
+static void ehci_octeon_start(void)
+{
+ union cvmx_uctlx_ehci_ctl ehci_ctl;
+
+ octeon2_usb_clocks_start();
+
+ ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
+ /* Use 64-bit addressing. */
+ ehci_ctl.s.ehci_64b_addr_en = 1;
+ ehci_ctl.s.l2c_addr_msb = 0;
+ ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
+ ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
+ cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
+}
+
+static void ehci_octeon_stop(void)
+{
+ octeon2_usb_clocks_stop();
+}
+
+static const struct hc_driver ehci_octeon_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "Octeon EHCI",
+ .hcd_priv_size = sizeof(struct ehci_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = ehci_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+
+ /*
+ * basic lifecycle operations
+ */
+ .reset = ehci_init,
+ .start = ehci_run,
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ehci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static u64 ehci_octeon_dma_mask = DMA_BIT_MASK(64);
+
+static int ehci_octeon_drv_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci;
+ struct resource *res_mem;
+ int irq;
+ int ret;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "No irq assigned\n");
+ return -ENODEV;
+ }
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res_mem == NULL) {
+ dev_err(&pdev->dev, "No register space assigned\n");
+ return -ENODEV;
+ }
+
+ /*
+ * We can DMA from anywhere. But the descriptors must be in
+ * the lower 4GB.
+ */
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ pdev->dev.dma_mask = &ehci_octeon_dma_mask;
+
+ hcd = usb_create_hcd(&ehci_octeon_hc_driver, &pdev->dev, "octeon");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res_mem->start;
+ hcd->rsrc_len = res_mem->end - res_mem->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+ OCTEON_EHCI_HCD_NAME)) {
+ dev_err(&pdev->dev, "request_mem_region failed\n");
+ ret = -EBUSY;
+ goto err1;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto err2;
+ }
+
+ ehci_octeon_start();
+
+ ehci = hcd_to_ehci(hcd);
+
+ /* Octeon EHCI matches CPU endianness. */
+#ifdef __BIG_ENDIAN
+ ehci->big_endian_mmio = 1;
+#endif
+
+ ehci->caps = hcd->regs;
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ /* cache this readonly data; minimize chip reads */
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+ if (ret) {
+ dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
+ goto err3;
+ }
+
+ platform_set_drvdata(pdev, hcd);
+
+ /* root ports should always stay powered */
+ ehci_port_power(ehci, 1);
+
+ return 0;
+err3:
+ ehci_octeon_stop();
+
+ iounmap(hcd->regs);
+err2:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err1:
+ usb_put_hcd(hcd);
+ return ret;
+}
+
+static int ehci_octeon_drv_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ usb_remove_hcd(hcd);
+
+ ehci_octeon_stop();
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver ehci_octeon_driver = {
+ .probe = ehci_octeon_drv_probe,
+ .remove = ehci_octeon_drv_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+ .driver = {
+ .name = OCTEON_EHCI_HCD_NAME,
+ .owner = THIS_MODULE,
+ }
+};
+
+MODULE_ALIAS("platform:" OCTEON_EHCI_HCD_NAME);
--- /dev/null
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+
+#include <asm/atomic.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+static atomic_t octeon2_usb_clock_start_cnt = ATOMIC_INIT(0);
+
+void octeon2_usb_clocks_start(void)
+{
+ u64 div;
+ union cvmx_uctlx_if_ena if_ena;
+ union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
+ union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
+ union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
+ int i;
+ unsigned long io_clk_64_to_ns;
+
+ if (atomic_inc_return(&octeon2_usb_clock_start_cnt) != 1)
+ return;
+
+ io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
+
+ /*
+ * Step 1: Wait for voltages stable. That surely happened
+ * before starting the kernel.
+ *
+ * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
+ */
+ if_ena.u64 = 0;
+ if_ena.s.en = 1;
+ cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
+
+ /* Step 3: Configure the reference clock, PHY, and HCLK */
+ clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
+ /* 3a */
+ clk_rst_ctl.s.p_por = 1;
+ clk_rst_ctl.s.hrst = 0;
+ clk_rst_ctl.s.p_prst = 0;
+ clk_rst_ctl.s.h_clkdiv_rst = 0;
+ clk_rst_ctl.s.o_clkdiv_rst = 0;
+ clk_rst_ctl.s.h_clkdiv_en = 0;
+ clk_rst_ctl.s.o_clkdiv_en = 0;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* 3b */
+ /* 12MHz crystal. */
+ clk_rst_ctl.s.p_refclk_sel = 0;
+ clk_rst_ctl.s.p_refclk_div = 0;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* 3c */
+ div = octeon_get_io_clock_rate() / 130000000ull;
+
+ switch (div) {
+ case 0:
+ div = 1;
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ break;
+ case 5:
+ div = 4;
+ break;
+ case 6:
+ case 7:
+ div = 6;
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ div = 8;
+ break;
+ default:
+ div = 12;
+ break;
+ }
+ clk_rst_ctl.s.h_div = div;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+ /* Read it back, */
+ clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
+ clk_rst_ctl.s.h_clkdiv_en = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+ /* 3d */
+ clk_rst_ctl.s.h_clkdiv_rst = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* 3e: delay 64 io clocks */
+ ndelay(io_clk_64_to_ns);
+
+ /*
+ * Step 4: Program the power-on reset field in the UCTL
+ * clock-reset-control register.
+ */
+ clk_rst_ctl.s.p_por = 0;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* Step 5: Wait 1 ms for the PHY clock to start. */
+ mdelay(1);
+
+ /*
+ * Step 6: Program the reset input from automatic test
+ * equipment field in the UPHY CSR
+ */
+ uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
+ uphy_ctl_status.s.ate_reset = 1;
+ cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
+
+ /* Step 7: Wait for at least 10ns. */
+ ndelay(10);
+
+ /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
+ uphy_ctl_status.s.ate_reset = 0;
+ cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
+
+ /*
+ * Step 9: Wait for at least 20ns for UPHY to output PHY clock
+ * signals and OHCI_CLK48
+ */
+ ndelay(20);
+
+ /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
+ /* 10a */
+ clk_rst_ctl.s.o_clkdiv_rst = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* 10b */
+ clk_rst_ctl.s.o_clkdiv_en = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* 10c */
+ ndelay(io_clk_64_to_ns);
+
+ /*
+ * Step 11: Program the PHY reset field:
+ * UCTL0_CLK_RST_CTL[P_PRST] = 1
+ */
+ clk_rst_ctl.s.p_prst = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* Step 12: Wait 1 uS. */
+ udelay(1);
+
+ /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
+ clk_rst_ctl.s.hrst = 1;
+ cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+
+ /* Now we can set some other registers. */
+
+ for (i = 0; i <= 1; i++) {
+ port_ctl_status.u64 =
+ cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
+ /* Set txvreftune to 15 to obtain complient 'eye' diagram. */
+ port_ctl_status.s.txvreftune = 15;
+ cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
+ port_ctl_status.u64);
+ }
+}
+EXPORT_SYMBOL(octeon2_usb_clocks_start);
+
+void octeon2_usb_clocks_stop(void)
+{
+ union cvmx_uctlx_if_ena if_ena;
+
+ if (atomic_dec_return(&octeon2_usb_clock_start_cnt) != 0)
+ return;
+
+ if_ena.u64 = 0;
+ if_ena.s.en = 0;
+ cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
+}
+EXPORT_SYMBOL(octeon2_usb_clocks_stop);
#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
#endif
+#ifdef CONFIG_USB_OCTEON_OHCI
+#include "ohci-octeon.c"
+#define PLATFORM_DRIVER ohci_octeon_driver
+#endif
+
#if !defined(PCI_DRIVER) && \
!defined(PLATFORM_DRIVER) && \
!defined(OMAP1_PLATFORM_DRIVER) && \
--- /dev/null
+/*
+ * EHCI HCD glue for Cavium Octeon II SOCs.
+ *
+ * Loosely based on ehci-au1xxx.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2010 Cavium Networks
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-uctlx-defs.h>
+
+#define OCTEON_OHCI_HCD_NAME "octeon-ohci"
+
+/* Common clock init code. */
+void octeon2_usb_clocks_start(void);
+void octeon2_usb_clocks_stop(void);
+
+static void ohci_octeon_hw_start(void)
+{
+ union cvmx_uctlx_ohci_ctl ohci_ctl;
+
+ octeon2_usb_clocks_start();
+
+ ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
+ ohci_ctl.s.l2c_addr_msb = 0;
+ ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
+ ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
+ cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
+
+}
+
+static void ohci_octeon_hw_stop(void)
+{
+ /* Undo ohci_octeon_start() */
+ octeon2_usb_clocks_stop();
+}
+
+static int __devinit ohci_octeon_start(struct usb_hcd *hcd)
+{
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+ int ret;
+
+ ret = ohci_init(ohci);
+
+ if (ret < 0)
+ return ret;
+
+ ret = ohci_run(ohci);
+
+ if (ret < 0) {
+ ohci_err(ohci, "can't start %s", hcd->self.bus_name);
+ ohci_stop(hcd);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct hc_driver ohci_octeon_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "Octeon OHCI",
+ .hcd_priv_size = sizeof(struct ohci_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = ohci_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ /*
+ * basic lifecycle operations
+ */
+ .start = ohci_octeon_start,
+ .stop = ohci_stop,
+ .shutdown = ohci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ohci_urb_enqueue,
+ .urb_dequeue = ohci_urb_dequeue,
+ .endpoint_disable = ohci_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ohci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ohci_hub_status_data,
+ .hub_control = ohci_hub_control,
+
+ .start_port_reset = ohci_start_port_reset,
+};
+
+static int ohci_octeon_drv_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct ohci_hcd *ohci;
+ void *reg_base;
+ struct resource *res_mem;
+ int irq;
+ int ret;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "No irq assigned\n");
+ return -ENODEV;
+ }
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res_mem == NULL) {
+ dev_err(&pdev->dev, "No register space assigned\n");
+ return -ENODEV;
+ }
+
+ /* Ohci is a 32-bit device. */
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+ hcd = usb_create_hcd(&ohci_octeon_hc_driver, &pdev->dev, "octeon");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res_mem->start;
+ hcd->rsrc_len = res_mem->end - res_mem->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+ OCTEON_OHCI_HCD_NAME)) {
+ dev_err(&pdev->dev, "request_mem_region failed\n");
+ ret = -EBUSY;
+ goto err1;
+ }
+
+ reg_base = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!reg_base) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = -ENOMEM;
+ goto err2;
+ }
+
+ ohci_octeon_hw_start();
+
+ hcd->regs = reg_base;
+
+ ohci = hcd_to_ohci(hcd);
+
+ /* Octeon OHCI matches CPU endianness. */
+#ifdef __BIG_ENDIAN
+ ohci->flags |= OHCI_QUIRK_BE_MMIO;
+#endif
+
+ ohci_hcd_init(ohci);
+
+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+ if (ret) {
+ dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
+ goto err3;
+ }
+
+ platform_set_drvdata(pdev, hcd);
+
+ return 0;
+
+err3:
+ ohci_octeon_hw_stop();
+
+ iounmap(hcd->regs);
+err2:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err1:
+ usb_put_hcd(hcd);
+ return ret;
+}
+
+static int ohci_octeon_drv_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ usb_remove_hcd(hcd);
+
+ ohci_octeon_hw_stop();
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver ohci_octeon_driver = {
+ .probe = ohci_octeon_drv_probe,
+ .remove = ohci_octeon_drv_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+ .driver = {
+ .name = OCTEON_OHCI_HCD_NAME,
+ .owner = THIS_MODULE,
+ }
+};
+
+MODULE_ALIAS("platform:" OCTEON_OHCI_HCD_NAME);
static void mddi_wait_interrupt(struct mddi_info *mddi, uint32_t intmask)
{
if (mddi_wait_interrupt_timeout(mddi, intmask, HZ/10) == 0)
- printk(KERN_INFO KERN_ERR "mddi_wait_interrupt %d, timeout "
+ printk(KERN_INFO "mddi_wait_interrupt %d, timeout "
"waiting for %x, INT = %x, STAT = %x gotint = %x\n",
current->pid, intmask, mddi_readl(INT), mddi_readl(STAT),
mddi->got_int);
if (mddi->flags & FLAG_HAVE_CAPS)
break;
- printk(KERN_INFO KERN_ERR "mddi_init, timeout waiting for "
- "caps\n");
+ printk(KERN_INFO "mddi_init, timeout waiting for caps\n");
}
return mddi->flags & FLAG_HAVE_CAPS;
}
mdp_irq_mask &= ~(mask);
/* if no one is waiting on the interrupt, disable it */
if (!mdp_irq_mask) {
- disable_irq(mdp->irq);
+ disable_irq_nosync(mdp->irq);
if (clk)
clk_disable(clk);
}
/* register mdp device */
mdp->mdp_dev.dev.parent = &pdev->dev;
mdp->mdp_dev.dev.class = mdp_class;
+ dev_set_name(&mdp->mdp_dev.dev, "mdp%d", pdev->id);
/* if you can remove the platform device you'd have to implement
* this:
u32 linelength;
bool yuv;
- /* Select data format */
+ /*
+ * Select data format. MIPI DSI is not hot-pluggable, so, we just use
+ * the default videomode. If this ever becomes a problem, We'll have to
+ * move this to mipi_display_on() above and use info->var.xres
+ */
switch (pdata->data_format) {
case MIPI_RGB888:
pctype = 0;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg.xres * 3;
+ linelength = ch->lcd_cfg[0].xres * 3;
yuv = false;
break;
case MIPI_RGB565:
pctype = 1;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg.xres * 2;
+ linelength = ch->lcd_cfg[0].xres * 2;
yuv = false;
break;
case MIPI_RGB666_LP:
pctype = 2;
datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg.xres * 3;
+ linelength = ch->lcd_cfg[0].xres * 3;
yuv = false;
break;
case MIPI_RGB666:
pctype = 3;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
- linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
+ linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
yuv = false;
break;
case MIPI_BGR888:
pctype = 8;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg.xres * 3;
+ linelength = ch->lcd_cfg[0].xres * 3;
yuv = false;
break;
case MIPI_BGR565:
pctype = 9;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg.xres * 2;
+ linelength = ch->lcd_cfg[0].xres * 2;
yuv = false;
break;
case MIPI_BGR666_LP:
pctype = 0xa;
datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg.xres * 3;
+ linelength = ch->lcd_cfg[0].xres * 3;
yuv = false;
break;
case MIPI_BGR666:
pctype = 0xb;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
- linelength = (ch->lcd_cfg.xres * 18 + 7) / 8;
+ linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
yuv = false;
break;
case MIPI_YUYV:
pctype = 4;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg.xres * 2;
+ linelength = ch->lcd_cfg[0].xres * 2;
yuv = true;
break;
case MIPI_UYVY:
pctype = 5;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg.xres * 2;
+ linelength = ch->lcd_cfg[0].xres * 2;
yuv = true;
break;
case MIPI_YUV420_L:
pctype = 6;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
- linelength = (ch->lcd_cfg.xres * 12 + 7) / 8;
+ linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
yuv = true;
break;
case MIPI_YUV420:
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
/* Length of U/V line */
- linelength = (ch->lcd_cfg.xres + 1) / 2;
+ linelength = (ch->lcd_cfg[0].xres + 1) / 2;
yuv = true;
break;
default:
iowrite32(0x00e00000, base + 0x8024); /* VMCTR2 */
/*
* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
- * sh_mobile_lcdc_info.ch[0].lcd_cfg.xres), HSALEN = 1 - default
+ * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
* (unused, since VMCTR2[HSABM] = 0)
*/
iowrite32(1 | (linelength << 16), base + 0x8028); /* VMLEN1 */
#include <video/sh_mobile_hdmi.h>
#include <video/sh_mobile_lcdc.h>
+#include "sh_mobile_lcdcfb.h"
+
#define HDMI_SYSTEM_CTRL 0x00 /* System control */
#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
struct sh_hdmi {
void __iomem *base;
- enum hotplug_state hp_state;
+ enum hotplug_state hp_state; /* hot-plug status */
+ bool preprogrammed_mode; /* use a pre-programmed VIC or the external mode */
struct clk *hdmi_clk;
struct device *dev;
struct fb_info *info;
+ struct mutex mutex; /* Protect the info pointer */
struct delayed_work edid_work;
struct fb_var_screeninfo var;
+ struct fb_monspecs monspec;
};
static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
*/
/* External video parameter settings */
-static void hdmi_external_video_param(struct sh_hdmi *hdmi)
+static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
{
struct fb_var_screeninfo *var = &hdmi->var;
u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
sync |= 8;
- pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
- htotal, hblank, hdelay, var->hsync_len,
- vtotal, vblank, vdelay, var->vsync_len, sync);
+ dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
+ htotal, hblank, hdelay, var->hsync_len,
+ vtotal, vblank, vdelay, var->vsync_len, sync);
hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
- /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
+ /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
+ if (!hdmi->preprogrammed_mode)
+ hdmi_write(hdmi, sync | 1 | (voffset << 4),
+ HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
}
/**
}
/**
- * sh_hdmi_phy_config()
+ * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
*/
static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
{
- /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
- hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
- hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
- hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
- /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
- hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
- hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
- hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
- hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
- hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
- hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+ if (hdmi->var.yres > 480) {
+ /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
+ /*
+ * [1:0] Speed_A
+ * [3:2] Speed_B
+ * [4] PLLA_Bypass
+ * [6] DRV_TEST_EN
+ * [7] DRV_TEST_IN
+ */
+ hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
+ /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
+ /*
+ * [2:0] BGR_I_OFFSET
+ * [6:4] BGR_V_OFFSET
+ */
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
+ /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
+ hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
+ /*
+ * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
+ * LPF capacitance, LPF resistance[1]
+ */
+ hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
+ /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
+ hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
+ /*
+ * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
+ * LPF capacitance, LPF resistance[1]
+ */
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
+ /* DRV_CONFIG, PE_CONFIG */
+ hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
+ /*
+ * [2:0] AMON_SEL (4 == LPF voltage)
+ * [4] PLLA_CONFIG[16]
+ * [5] PLLB_CONFIG[16]
+ */
+ hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+ } else {
+ /* for 480p8bit 27MHz */
+ hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
+ hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
+ hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
+ hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
+ hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
+ hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
+ hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
+ hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
+ }
}
/**
*/
static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
{
+ u8 vic;
+
/* AVI InfoFrame */
hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
/*
- * C = No Data
- * M = 16:9 Picture Aspect Ratio
- * R = Same as picture aspect ratio
+ * [7:6] C = Colorimetry: no data
+ * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
+ * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
*/
hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
/*
* VIC = 1280 x 720p: ignored if external config is used
- * Send 2 for 720 x 480p, 16 for 1080p
+ * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
*/
- hdmi_write(hdmi, 4, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
+ if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
+ vic = 16;
+ else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
+ vic = 2;
+ else
+ vic = 4;
+ hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
/* PR = No Repetition */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
}
-/**
- * sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
- */
-static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
-{
- int i;
-
- /* Gamut Metadata Packet */
- hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
-
- /* Packet Type = 0x0A */
- hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
- /* Gamut Packet is not used, so default value */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
- /* Gamut Packet is not used, so default value */
- hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
-
- /* GBD bytes 0 through 27 */
- for (i = 0; i <= 27; i++)
- /* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
-}
-
-/**
- * sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
- */
-static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
-{
- int i;
-
- /* Audio Content Protection Packet (ACP) */
- hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
-
- /* Packet Type = 0x04 */
- hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
- /* ACP_Type */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
- /* Reserved (0) */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
-
- /* GBD bytes 0 through 27 */
- for (i = 0; i <= 27; i++)
- /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
-}
-
-/**
- * sh_hdmi_isrc1_setup() - ISRC1 Packet
- */
-static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
-{
- int i;
-
- /* ISRC1 Packet */
- hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
-
- /* Packet Type = 0x05 */
- hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
- /* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
- /* Reserved (0) */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
-
- /* PB0 UPC_EAN_ISRC_0-15 */
- /* Bytes PB16-PB27 shall be set to a value of 0. */
- for (i = 0; i <= 27; i++)
- /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
-}
-
-/**
- * sh_hdmi_isrc2_setup() - ISRC2 Packet
- */
-static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
-{
- int i;
-
- /* ISRC2 Packet */
- hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
-
- /* HB0 Packet Type = 0x06 */
- hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
- /* Reserved (0) */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
- /* Reserved (0) */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
-
- /* PB0 UPC_EAN_ISRC_16-31 */
- /* Bytes PB16-PB27 shall be set to a value of 0. */
- for (i = 0; i <= 27; i++)
- /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
- hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
-}
-
/**
* sh_hdmi_configure() - Initialise HDMI for output
*/
/* Audio InfoFrame */
sh_hdmi_audio_infoframe_setup(hdmi);
- /* Gamut Metadata packet */
- sh_hdmi_gamut_metadata_setup(hdmi);
-
- /* Audio Content Protection (ACP) Packet */
- sh_hdmi_acp_setup(hdmi);
-
- /* ISRC1 Packet */
- sh_hdmi_isrc1_setup(hdmi);
-
- /* ISRC2 Packet */
- sh_hdmi_isrc2_setup(hdmi);
-
/*
* Control packet auto send with VSYNC control: auto send
* General control, Gamut metadata, ISRC, and ACP packets
hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
}
-static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
+static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
+ const struct fb_videomode *mode)
{
- struct fb_var_screeninfo *var = &hdmi->var;
- struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
- struct fb_videomode *lcd_cfg = &pdata->lcd_chan->lcd_cfg;
- unsigned long height = var->height, width = var->width;
- int i;
+ long target = PICOS2KHZ(mode->pixclock) * 1000,
+ rate = clk_round_rate(hdmi->hdmi_clk, target);
+ unsigned long rate_error = rate > 0 ? abs(rate - target) : ULONG_MAX;
+
+ dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
+ mode->left_margin, mode->xres,
+ mode->right_margin, mode->hsync_len,
+ mode->upper_margin, mode->yres,
+ mode->lower_margin, mode->vsync_len);
+
+ dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz\n", target,
+ rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
+ mode->refresh);
+
+ return rate_error;
+}
+
+static int sh_hdmi_read_edid(struct sh_hdmi *hdmi)
+{
+ struct fb_var_screeninfo tmpvar;
+ struct fb_var_screeninfo *var = &tmpvar;
+ const struct fb_videomode *mode, *found = NULL;
+ struct fb_info *info = hdmi->info;
+ struct fb_modelist *modelist = NULL;
+ unsigned int f_width = 0, f_height = 0, f_refresh = 0;
+ unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
+ bool exact_match = false;
u8 edid[128];
+ char *forced;
+ int i;
/* Read EDID */
- pr_debug("Read back EDID code:");
+ dev_dbg(hdmi->dev, "Read back EDID code:");
for (i = 0; i < 128; i++) {
edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
#ifdef DEBUG
#ifdef DEBUG
printk(KERN_CONT "\n");
#endif
- fb_parse_edid(edid, var);
- pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
- var->left_margin, var->xres, var->right_margin, var->hsync_len,
- var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
- PICOS2KHZ(var->pixclock));
-
- /* FIXME: Use user-provided configuration instead of EDID */
- var->width = width;
- var->xres = lcd_cfg->xres;
- var->xres_virtual = lcd_cfg->xres;
- var->left_margin = lcd_cfg->left_margin;
- var->right_margin = lcd_cfg->right_margin;
- var->hsync_len = lcd_cfg->hsync_len;
- var->height = height;
- var->yres = lcd_cfg->yres;
- var->yres_virtual = lcd_cfg->yres * 2;
- var->upper_margin = lcd_cfg->upper_margin;
- var->lower_margin = lcd_cfg->lower_margin;
- var->vsync_len = lcd_cfg->vsync_len;
- var->sync = lcd_cfg->sync;
- var->pixclock = lcd_cfg->pixclock;
-
- hdmi_external_video_param(hdmi);
+
+ fb_edid_to_monspecs(edid, &hdmi->monspec);
+
+ fb_get_options("sh_mobile_lcdc", &forced);
+ if (forced && *forced) {
+ /* Only primitive parsing so far */
+ i = sscanf(forced, "%ux%u@%u",
+ &f_width, &f_height, &f_refresh);
+ if (i < 2) {
+ f_width = 0;
+ f_height = 0;
+ }
+ dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
+ f_width, f_height, f_refresh);
+ }
+
+ /* Walk monitor modes to find the best or the exact match */
+ for (i = 0, mode = hdmi->monspec.modedb;
+ f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
+ i++, mode++) {
+ unsigned long rate_error = sh_hdmi_rate_error(hdmi, mode);
+
+ /* No interest in unmatching modes */
+ if (f_width != mode->xres || f_height != mode->yres)
+ continue;
+ if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
+ /*
+ * Exact match if either the refresh rate matches or it
+ * hasn't been specified and we've found a mode, for
+ * which we can configure the clock precisely
+ */
+ exact_match = true;
+ else if (found && found_rate_error <= rate_error)
+ /*
+ * We otherwise search for the closest matching clock
+ * rate - either if no refresh rate has been specified
+ * or we cannot find an exactly matching one
+ */
+ continue;
+
+ /* Check if supported: sufficient fb memory, supported clock-rate */
+ fb_videomode_to_var(var, mode);
+
+ if (info && info->fbops->fb_check_var &&
+ info->fbops->fb_check_var(var, info)) {
+ exact_match = false;
+ continue;
+ }
+
+ found = mode;
+ found_rate_error = rate_error;
+ }
+
+ /*
+ * TODO 1: if no ->info is present, postpone running the config until
+ * after ->info first gets registered.
+ * TODO 2: consider registering the HDMI platform device from the LCDC
+ * driver, and passing ->info with HDMI platform data.
+ */
+ if (info && !found) {
+ modelist = hdmi->info->modelist.next &&
+ !list_empty(&hdmi->info->modelist) ?
+ list_entry(hdmi->info->modelist.next,
+ struct fb_modelist, list) :
+ NULL;
+
+ if (modelist) {
+ found = &modelist->mode;
+ found_rate_error = sh_hdmi_rate_error(hdmi, found);
+ }
+ }
+
+ /* No cookie today */
+ if (!found)
+ return -ENXIO;
+
+ dev_info(hdmi->dev, "Using %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
+ modelist ? "default" : "EDID", found->xres, found->yres,
+ found->refresh, PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
+
+ if ((found->xres == 720 && found->yres == 480) ||
+ (found->xres == 1280 && found->yres == 720) ||
+ (found->xres == 1920 && found->yres == 1080))
+ hdmi->preprogrammed_mode = true;
+ else
+ hdmi->preprogrammed_mode = false;
+
+ fb_videomode_to_var(&hdmi->var, found);
+ sh_hdmi_external_video_param(hdmi);
+
+ return 0;
}
static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
if (printk_ratelimit())
- pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
- irq, status1, mask1, status2, mask2);
+ dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
+ irq, status1, mask1, status2, mask2);
if (!((status1 & mask1) | (status2 & mask2))) {
return IRQ_NONE;
udelay(500);
msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
- pr_debug("MSENS 0x%x\n", msens);
+ dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
/* Check, if hot plug & MSENS pin status are both high */
if ((msens & 0xC0) == 0xC0) {
/* Display plug in */
return IRQ_HANDLED;
}
-static void hdmi_display_on(void *arg, struct fb_info *info)
+/* locking: called with info->lock held, or before register_framebuffer() */
+static void sh_hdmi_display_on(void *arg, struct fb_info *info)
{
+ /*
+ * info is guaranteed to be valid, when we are called, because our
+ * FB_EVENT_FB_UNBIND notify is also called with info->lock held
+ */
struct sh_hdmi *hdmi = arg;
struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+ struct sh_mobile_lcdc_chan *ch = info->par;
- if (info->var.xres != 1280 || info->var.yres != 720) {
- dev_warn(info->device, "Unsupported framebuffer geometry %ux%u\n",
- info->var.xres, info->var.yres);
- return;
- }
+ dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
+ pdata->lcd_dev, info->state);
+
+ /* No need to lock */
+ hdmi->info = info;
- pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
/*
- * FIXME: not a good place to store fb_info. And we cannot nullify it
- * even on monitor disconnect. What should the lifecycle be?
+ * hp_state can be set to
+ * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
+ * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
+ * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
*/
- hdmi->info = info;
switch (hdmi->hp_state) {
case HDMI_HOTPLUG_EDID_DONE:
/* PS mode d->e. All functions are active */
hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
- pr_debug("HDMI running\n");
+ dev_dbg(hdmi->dev, "HDMI running\n");
break;
case HDMI_HOTPLUG_DISCONNECTED:
info->state = FBINFO_STATE_SUSPENDED;
default:
- hdmi->var = info->var;
+ hdmi->var = ch->display_var;
}
}
-static void hdmi_display_off(void *arg)
+/* locking: called with info->lock held */
+static void sh_hdmi_display_off(void *arg)
{
struct sh_hdmi *hdmi = arg;
struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
- pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
+ dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
/* PS mode e->a */
hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
}
+static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
+{
+ struct fb_info *info = hdmi->info;
+ struct sh_mobile_lcdc_chan *ch = info->par;
+ struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
+ struct fb_videomode mode1, mode2;
+
+ fb_var_to_videomode(&mode1, old_var);
+ fb_var_to_videomode(&mode2, new_var);
+
+ dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
+ mode1.xres, mode1.yres, mode2.xres, mode2.yres);
+
+ if (fb_mode_is_equal(&mode1, &mode2))
+ return false;
+
+ dev_dbg(info->dev, "Switching %u -> %u lines\n",
+ mode1.yres, mode2.yres);
+ *old_var = *new_var;
+
+ return true;
+}
+
+/**
+ * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
+ * @hdmi: driver context
+ * @pixclock: pixel clock period in picoseconds
+ * return: configured positive rate if successful
+ * 0 if couldn't set the rate, but managed to enable the clock
+ * negative error, if couldn't enable the clock
+ */
+static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long pixclock)
+{
+ long rate;
+ int ret;
+
+ rate = PICOS2KHZ(pixclock) * 1000;
+ rate = clk_round_rate(hdmi->hdmi_clk, rate);
+ if (rate > 0) {
+ ret = clk_set_rate(hdmi->hdmi_clk, rate);
+ if (ret < 0) {
+ dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", rate, ret);
+ rate = 0;
+ } else {
+ dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", rate);
+ }
+ } else {
+ rate = 0;
+ dev_warn(hdmi->dev, "Cannot get suitable rate: %ld\n", rate);
+ }
+
+ ret = clk_enable(hdmi->hdmi_clk);
+ if (ret < 0) {
+ dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
+ return ret;
+ }
+
+ return rate;
+}
+
/* Hotplug interrupt occurred, read EDID */
-static void edid_work_fn(struct work_struct *work)
+static void sh_hdmi_edid_work_fn(struct work_struct *work)
{
struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
+ struct sh_mobile_lcdc_chan *ch;
+ int ret;
- pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
- pdata->lcd_dev, hdmi->hp_state);
+ dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
+ pdata->lcd_dev, hdmi->hp_state);
if (!pdata->lcd_dev)
return;
+ mutex_lock(&hdmi->mutex);
+
if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
- pm_runtime_get_sync(hdmi->dev);
/* A device has been plugged in */
- sh_hdmi_read_edid(hdmi);
+ pm_runtime_get_sync(hdmi->dev);
+
+ ret = sh_hdmi_read_edid(hdmi);
+ if (ret < 0)
+ goto out;
+
+ /* Reconfigure the clock */
+ clk_disable(hdmi->hdmi_clk);
+ ret = sh_hdmi_clk_configure(hdmi, hdmi->var.pixclock);
+ if (ret < 0)
+ goto out;
+
msleep(10);
sh_hdmi_configure(hdmi);
/* Switched to another (d) power-save mode */
msleep(10);
if (!hdmi->info)
- return;
+ goto out;
+
+ ch = hdmi->info->par;
acquire_console_sem();
/* HDMI plug in */
- hdmi->info->var = hdmi->var;
- if (hdmi->info->state != FBINFO_STATE_RUNNING)
+ if (!sh_hdmi_must_reconfigure(hdmi) &&
+ hdmi->info->state == FBINFO_STATE_RUNNING) {
+ /*
+ * First activation with the default monitor - just turn
+ * on, if we run a resume here, the logo disappears
+ */
+ if (lock_fb_info(hdmi->info)) {
+ sh_hdmi_display_on(hdmi, hdmi->info);
+ unlock_fb_info(hdmi->info);
+ }
+ } else {
+ /* New monitor or have to wake up */
fb_set_suspend(hdmi->info, 0);
- else
- hdmi_display_on(hdmi, hdmi->info);
+ }
release_console_sem();
} else {
+ ret = 0;
if (!hdmi->info)
- return;
+ goto out;
acquire_console_sem();
release_console_sem();
pm_runtime_put(hdmi->dev);
+ fb_destroy_modedb(hdmi->monspec.modedb);
}
- pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
+out:
+ if (ret < 0)
+ hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
+ mutex_unlock(&hdmi->mutex);
+
+ dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
+}
+
+static int sh_hdmi_notify(struct notifier_block *nb,
+ unsigned long action, void *data);
+
+static struct notifier_block sh_hdmi_notifier = {
+ .notifier_call = sh_hdmi_notify,
+};
+
+static int sh_hdmi_notify(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct fb_event *event = data;
+ struct fb_info *info = event->info;
+ struct sh_mobile_lcdc_chan *ch = info->par;
+ struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
+ struct sh_hdmi *hdmi = board_cfg->board_data;
+
+ if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
+ return NOTIFY_DONE;
+
+ switch(action) {
+ case FB_EVENT_FB_REGISTERED:
+ /* Unneeded, activation taken care by sh_hdmi_display_on() */
+ break;
+ case FB_EVENT_FB_UNREGISTERED:
+ /*
+ * We are called from unregister_framebuffer() with the
+ * info->lock held. This is bad for us, because we can race with
+ * the scheduled work, which has to call fb_set_suspend(), which
+ * takes info->lock internally, so, sh_hdmi_edid_work_fn()
+ * cannot take and hold info->lock for the whole function
+ * duration. Using an additional lock creates a classical AB-BA
+ * lock up. Therefore, we have to release the info->lock
+ * temporarily, synchronise with the work queue and re-acquire
+ * the info->lock.
+ */
+ unlock_fb_info(hdmi->info);
+ mutex_lock(&hdmi->mutex);
+ hdmi->info = NULL;
+ mutex_unlock(&hdmi->mutex);
+ lock_fb_info(hdmi->info);
+ return NOTIFY_OK;
+ }
+ return NOTIFY_DONE;
}
static int __init sh_hdmi_probe(struct platform_device *pdev)
{
struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct sh_mobile_lcdc_board_cfg *board_cfg;
int irq = platform_get_irq(pdev, 0), ret;
struct sh_hdmi *hdmi;
long rate;
return -ENOMEM;
}
- ret = snd_soc_register_codec(&pdev->dev,
- &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
- if (ret < 0)
- goto esndreg;
+ mutex_init(&hdmi->mutex);
hdmi->dev = &pdev->dev;
goto egetclk;
}
- rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg.pixclock) * 1000;
-
- rate = clk_round_rate(hdmi->hdmi_clk, rate);
+ /* Some arbitrary relaxed pixclock just to get things started */
+ rate = sh_hdmi_clk_configure(hdmi, 37037);
if (rate < 0) {
ret = rate;
- dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
goto erate;
}
- ret = clk_set_rate(hdmi->hdmi_clk, rate);
- if (ret < 0) {
- dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
- goto erate;
- }
-
- pr_debug("HDMI set frequency %lu\n", rate);
-
- ret = clk_enable(hdmi->hdmi_clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
- goto eclkenable;
- }
-
- dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
+ dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
dev_err(&pdev->dev, "HDMI register region already claimed\n");
platform_set_drvdata(pdev, hdmi);
-#if 1
/* Product and revision IDs are 0 in sh-mobile version */
dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
-#endif
/* Set up LCDC callbacks */
- pdata->lcd_chan->board_cfg.board_data = hdmi;
- pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
- pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
+ board_cfg = &pdata->lcd_chan->board_cfg;
+ board_cfg->owner = THIS_MODULE;
+ board_cfg->board_data = hdmi;
+ board_cfg->display_on = sh_hdmi_display_on;
+ board_cfg->display_off = sh_hdmi_display_off;
- INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
+ INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
pm_runtime_enable(&pdev->dev);
pm_runtime_resume(&pdev->dev);
goto ereqirq;
}
+ ret = snd_soc_register_codec(&pdev->dev,
+ &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "codec registration failed\n");
+ goto ecodec;
+ }
+
return 0;
+ecodec:
+ free_irq(irq, hdmi);
ereqirq:
pm_runtime_disable(&pdev->dev);
iounmap(hdmi->base);
release_mem_region(res->start, resource_size(res));
ereqreg:
clk_disable(hdmi->hdmi_clk);
-eclkenable:
erate:
clk_put(hdmi->hdmi_clk);
egetclk:
- snd_soc_unregister_codec(&pdev->dev);
-esndreg:
+ mutex_destroy(&hdmi->mutex);
kfree(hdmi);
return ret;
struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
int irq = platform_get_irq(pdev, 0);
snd_soc_unregister_codec(&pdev->dev);
- pdata->lcd_chan->board_cfg.display_on = NULL;
- pdata->lcd_chan->board_cfg.display_off = NULL;
- pdata->lcd_chan->board_cfg.board_data = NULL;
+ board_cfg->display_on = NULL;
+ board_cfg->display_off = NULL;
+ board_cfg->board_data = NULL;
+ board_cfg->owner = NULL;
+ /* No new work will be scheduled, wait for running ISR */
free_irq(irq, hdmi);
- pm_runtime_disable(&pdev->dev);
+ /* Wait for already scheduled work */
cancel_delayed_work_sync(&hdmi->edid_work);
+ pm_runtime_disable(&pdev->dev);
clk_disable(hdmi->hdmi_clk);
clk_put(hdmi->hdmi_clk);
iounmap(hdmi->base);
release_mem_region(res->start, resource_size(res));
+ mutex_destroy(&hdmi->mutex);
kfree(hdmi);
return 0;
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
-#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/vmalloc.h>
#include <linux/ioctl.h>
#include <linux/slab.h>
+#include <linux/console.h>
#include <video/sh_mobile_lcdc.h>
#include <asm/atomic.h>
-#define PALETTE_NR 16
+#include "sh_mobile_lcdcfb.h"
+
#define SIDE_B_OFFSET 0x1000
#define MIRROR_OFFSET 0x2000
};
#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
-/* per-channel registers */
-enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
- LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
- LDHAJR,
- NR_CH_REGS };
+#define DEFAULT_XRES 1280
+#define DEFAULT_YRES 1024
static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x400,
#define LDRCNTR_MRC 0x00000001
#define LDSR_MRS 0x00000100
-struct sh_mobile_lcdc_priv;
-struct sh_mobile_lcdc_chan {
- struct sh_mobile_lcdc_priv *lcdc;
- unsigned long *reg_offs;
- unsigned long ldmt1r_value;
- unsigned long enabled; /* ME and SE in LDCNT2R */
- struct sh_mobile_lcdc_chan_cfg cfg;
- u32 pseudo_palette[PALETTE_NR];
- unsigned long saved_ch_regs[NR_CH_REGS];
- struct fb_info *info;
- dma_addr_t dma_handle;
- struct fb_deferred_io defio;
- struct scatterlist *sglist;
- unsigned long frame_end;
- unsigned long pan_offset;
- wait_queue_head_t frame_end_wait;
- struct completion vsync_completion;
+static const struct fb_videomode default_720p = {
+ .name = "HDMI 720p",
+ .xres = 1280,
+ .yres = 720,
+
+ .left_margin = 200,
+ .right_margin = 88,
+ .hsync_len = 48,
+
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+
+ .pixclock = 13468,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
};
struct sh_mobile_lcdc_priv {
static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
{
- struct fb_var_screeninfo *var = &ch->info->var;
- unsigned long h_total, hsync_pos;
+ struct fb_var_screeninfo *var = &ch->info->var, *display_var = &ch->display_var;
+ unsigned long h_total, hsync_pos, display_h_total;
u32 tmp;
tmp = ch->ldmt1r_value;
lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
/* horizontal configuration */
- h_total = var->xres + var->hsync_len +
- var->left_margin + var->right_margin;
+ h_total = display_var->xres + display_var->hsync_len +
+ display_var->left_margin + display_var->right_margin;
tmp = h_total / 8; /* HTCN */
- tmp |= (var->xres / 8) << 16; /* HDCN */
+ tmp |= (min(display_var->xres, var->xres) / 8) << 16; /* HDCN */
lcdc_write_chan(ch, LDHCNR, tmp);
- hsync_pos = var->xres + var->right_margin;
+ hsync_pos = display_var->xres + display_var->right_margin;
tmp = hsync_pos / 8; /* HSYNP */
- tmp |= (var->hsync_len / 8) << 16; /* HSYNW */
+ tmp |= (display_var->hsync_len / 8) << 16; /* HSYNW */
lcdc_write_chan(ch, LDHSYNR, tmp);
/* vertical configuration */
- tmp = var->yres + var->vsync_len +
- var->upper_margin + var->lower_margin; /* VTLN */
- tmp |= var->yres << 16; /* VDLN */
+ tmp = display_var->yres + display_var->vsync_len +
+ display_var->upper_margin + display_var->lower_margin; /* VTLN */
+ tmp |= min(display_var->yres, var->yres) << 16; /* VDLN */
lcdc_write_chan(ch, LDVLNR, tmp);
- tmp = var->yres + var->lower_margin; /* VSYNP */
- tmp |= var->vsync_len << 16; /* VSYNW */
+ tmp = display_var->yres + display_var->lower_margin; /* VSYNP */
+ tmp |= display_var->vsync_len << 16; /* VSYNW */
lcdc_write_chan(ch, LDVSYNR, tmp);
/* Adjust horizontal synchronisation for HDMI */
- tmp = ((var->xres & 7) << 24) |
- ((h_total & 7) << 16) |
- ((var->hsync_len & 7) << 8) |
+ display_h_total = display_var->xres + display_var->hsync_len +
+ display_var->left_margin + display_var->right_margin;
+ tmp = ((display_var->xres & 7) << 24) |
+ ((display_h_total & 7) << 16) |
+ ((display_var->hsync_len & 7) << 8) |
hsync_pos;
lcdc_write_chan(ch, LDHAJR, tmp);
}
static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
{
struct sh_mobile_lcdc_chan *ch;
- struct fb_videomode *lcd_cfg;
struct sh_mobile_lcdc_board_cfg *board_cfg;
unsigned long tmp;
int k, m;
m = 1 << 6;
tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
- lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
+ /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider denominator */
+ lcdc_write_chan(ch, LDDCKPAT1R, 0);
lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
}
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
- lcd_cfg = &ch->cfg.lcd_cfg;
if (!ch->enabled)
continue;
/* set bpp format in PKF[4:0] */
tmp = lcdc_read_chan(ch, LDDFR);
- tmp &= ~(0x0001001f);
+ tmp &= ~0x0001001f;
tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
lcdc_write_chan(ch, LDDFR, tmp);
continue;
board_cfg = &ch->cfg.board_cfg;
- if (board_cfg->display_on)
+ if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
board_cfg->display_on(board_cfg->board_data, ch->info);
+ module_put(board_cfg->owner);
+ }
}
return 0;
* flush frame, and wait for frame end interrupt
* clean up deferred io and enable clock
*/
- if (ch->info->fbdefio) {
+ if (ch->info && ch->info->fbdefio) {
ch->frame_end = 0;
schedule_delayed_work(&ch->info->deferred_work, 0);
wait_event(ch->frame_end_wait, ch->frame_end);
}
board_cfg = &ch->cfg.board_cfg;
- if (board_cfg->display_off)
+ if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
board_cfg->display_off(board_cfg->board_data);
+ module_put(board_cfg->owner);
+ }
}
/* stop the lcdc */
return PTR_ERR(priv->dot_clk);
}
}
- atomic_set(&priv->hw_usecnt, -1);
/* Runtime PM support involves two step for this driver:
* 1) Enable Runtime PM
return retval;
}
+static void sh_mobile_fb_reconfig(struct fb_info *info)
+{
+ struct sh_mobile_lcdc_chan *ch = info->par;
+ struct fb_videomode mode1, mode2;
+ struct fb_event event;
+ int evnt = FB_EVENT_MODE_CHANGE_ALL;
+
+ if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
+ /* More framebuffer users are active */
+ return;
+
+ fb_var_to_videomode(&mode1, &ch->display_var);
+ fb_var_to_videomode(&mode2, &info->var);
+
+ if (fb_mode_is_equal(&mode1, &mode2))
+ return;
+
+ /* Display has been re-plugged, framebuffer is free now, reconfigure */
+ if (fb_set_var(info, &ch->display_var) < 0)
+ /* Couldn't reconfigure, hopefully, can continue as before */
+ return;
+
+ info->fix.line_length = mode2.xres * (ch->cfg.bpp / 8);
+
+ /*
+ * fb_set_var() calls the notifier change internally, only if
+ * FBINFO_MISC_USEREVENT flag is set. Since we do not want to fake a
+ * user event, we have to call the chain ourselves.
+ */
+ event.info = info;
+ event.data = &mode2;
+ fb_notifier_call_chain(evnt, &event);
+}
+
+/*
+ * Locking: both .fb_release() and .fb_open() are called with info->lock held if
+ * user == 1, or with console sem held, if user == 0.
+ */
+static int sh_mobile_release(struct fb_info *info, int user)
+{
+ struct sh_mobile_lcdc_chan *ch = info->par;
+
+ mutex_lock(&ch->open_lock);
+ dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
+
+ ch->use_count--;
+
+ /* Nothing to reconfigure, when called from fbcon */
+ if (user) {
+ acquire_console_sem();
+ sh_mobile_fb_reconfig(info);
+ release_console_sem();
+ }
+
+ mutex_unlock(&ch->open_lock);
+
+ return 0;
+}
+
+static int sh_mobile_open(struct fb_info *info, int user)
+{
+ struct sh_mobile_lcdc_chan *ch = info->par;
+
+ mutex_lock(&ch->open_lock);
+ ch->use_count++;
+
+ dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
+ mutex_unlock(&ch->open_lock);
+
+ return 0;
+}
+
+static int sh_mobile_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ struct sh_mobile_lcdc_chan *ch = info->par;
+
+ if (var->xres < 160 || var->xres > 1920 ||
+ var->yres < 120 || var->yres > 1080 ||
+ var->left_margin < 32 || var->left_margin > 320 ||
+ var->right_margin < 12 || var->right_margin > 240 ||
+ var->upper_margin < 12 || var->upper_margin > 120 ||
+ var->lower_margin < 1 || var->lower_margin > 64 ||
+ var->hsync_len < 32 || var->hsync_len > 240 ||
+ var->vsync_len < 2 || var->vsync_len > 64 ||
+ var->pixclock < 6000 || var->pixclock > 40000 ||
+ var->xres * var->yres * (ch->cfg.bpp / 8) * 2 > info->fix.smem_len) {
+ dev_warn(info->dev, "Invalid info: %u %u %u %u %u %u %u %u %u!\n",
+ var->xres, var->yres,
+ var->left_margin, var->right_margin,
+ var->upper_margin, var->lower_margin,
+ var->hsync_len, var->vsync_len,
+ var->pixclock);
+ return -EINVAL;
+ }
+ return 0;
+}
static struct fb_ops sh_mobile_lcdc_ops = {
.owner = THIS_MODULE,
.fb_imageblit = sh_mobile_lcdc_imageblit,
.fb_pan_display = sh_mobile_fb_pan_display,
.fb_ioctl = sh_mobile_ioctl,
+ .fb_open = sh_mobile_open,
+ .fb_release = sh_mobile_release,
+ .fb_check_var = sh_mobile_check_var,
};
static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
.runtime_resume = sh_mobile_lcdc_runtime_resume,
};
+/* locking: called with info->lock held */
static int sh_mobile_lcdc_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
struct fb_info *info = event->info;
struct sh_mobile_lcdc_chan *ch = info->par;
struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
- struct fb_var_screeninfo *var;
+ int ret;
if (&ch->lcdc->notifier != nb)
- return 0;
+ return NOTIFY_DONE;
dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
__func__, action, event->data);
switch(action) {
case FB_EVENT_SUSPEND:
- if (board_cfg->display_off)
+ if (try_module_get(board_cfg->owner) && board_cfg->display_off) {
board_cfg->display_off(board_cfg->board_data);
+ module_put(board_cfg->owner);
+ }
pm_runtime_put(info->device);
+ sh_mobile_lcdc_stop(ch->lcdc);
break;
case FB_EVENT_RESUME:
- var = &info->var;
+ mutex_lock(&ch->open_lock);
+ sh_mobile_fb_reconfig(info);
+ mutex_unlock(&ch->open_lock);
/* HDMI must be enabled before LCDC configuration */
- if (board_cfg->display_on)
- board_cfg->display_on(board_cfg->board_data, ch->info);
-
- /* Check if the new display is not in our modelist */
- if (ch->info->modelist.next &&
- !fb_match_mode(var, &ch->info->modelist)) {
- struct fb_videomode mode;
- int ret;
-
- /* Can we handle this display? */
- if (var->xres > ch->cfg.lcd_cfg.xres ||
- var->yres > ch->cfg.lcd_cfg.yres)
- return -ENOMEM;
-
- /* Add to the modelist */
- fb_var_to_videomode(&mode, var);
- ret = fb_add_videomode(&mode, &ch->info->modelist);
- if (ret < 0)
- return ret;
+ if (try_module_get(board_cfg->owner) && board_cfg->display_on) {
+ board_cfg->display_on(board_cfg->board_data, info);
+ module_put(board_cfg->owner);
}
- pm_runtime_get_sync(info->device);
-
- sh_mobile_lcdc_geometry(ch);
-
- break;
+ ret = sh_mobile_lcdc_start(ch->lcdc);
+ if (!ret)
+ pm_runtime_get_sync(info->device);
}
- return 0;
+ return NOTIFY_OK;
}
static int sh_mobile_lcdc_remove(struct platform_device *pdev);
{
struct fb_info *info;
struct sh_mobile_lcdc_priv *priv;
- struct sh_mobile_lcdc_info *pdata;
- struct sh_mobile_lcdc_chan_cfg *cfg;
+ struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
struct resource *res;
int error;
void *buf;
int i, j;
- if (!pdev->dev.platform_data) {
+ if (!pdata) {
dev_err(&pdev->dev, "no platform data defined\n");
return -EINVAL;
}
}
priv->irq = i;
- pdata = pdev->dev.platform_data;
+ atomic_set(&priv->hw_usecnt, -1);
j = 0;
for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
- priv->ch[j].lcdc = priv;
- memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
+ struct sh_mobile_lcdc_chan *ch = priv->ch + j;
+
+ ch->lcdc = priv;
+ memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
- error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
+ error = sh_mobile_lcdc_check_interface(ch);
if (error) {
dev_err(&pdev->dev, "unsupported interface type\n");
goto err1;
}
- init_waitqueue_head(&priv->ch[j].frame_end_wait);
- init_completion(&priv->ch[j].vsync_completion);
- priv->ch[j].pan_offset = 0;
+ init_waitqueue_head(&ch->frame_end_wait);
+ init_completion(&ch->vsync_completion);
+ ch->pan_offset = 0;
switch (pdata->ch[i].chan) {
case LCDC_CHAN_MAINLCD:
- priv->ch[j].enabled = 1 << 1;
- priv->ch[j].reg_offs = lcdc_offs_mainlcd;
+ ch->enabled = 1 << 1;
+ ch->reg_offs = lcdc_offs_mainlcd;
j++;
break;
case LCDC_CHAN_SUBLCD:
- priv->ch[j].enabled = 1 << 2;
- priv->ch[j].reg_offs = lcdc_offs_sublcd;
+ ch->enabled = 1 << 2;
+ ch->reg_offs = lcdc_offs_sublcd;
j++;
break;
}
for (i = 0; i < j; i++) {
struct fb_var_screeninfo *var;
- struct fb_videomode *lcd_cfg;
- cfg = &priv->ch[i].cfg;
+ const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
+ struct sh_mobile_lcdc_chan *ch = priv->ch + i;
+ struct sh_mobile_lcdc_chan_cfg *cfg = &ch->cfg;
+ const struct fb_videomode *mode = cfg->lcd_cfg;
+ unsigned long max_size = 0;
+ int k;
- priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
- if (!priv->ch[i].info) {
+ ch->info = framebuffer_alloc(0, &pdev->dev);
+ if (!ch->info) {
dev_err(&pdev->dev, "unable to allocate fb_info\n");
error = -ENOMEM;
break;
}
- info = priv->ch[i].info;
+ info = ch->info;
var = &info->var;
- lcd_cfg = &cfg->lcd_cfg;
info->fbops = &sh_mobile_lcdc_ops;
- var->xres = var->xres_virtual = lcd_cfg->xres;
- var->yres = lcd_cfg->yres;
+ info->par = ch;
+
+ mutex_init(&ch->open_lock);
+
+ for (k = 0, lcd_cfg = mode;
+ k < cfg->num_cfg && lcd_cfg;
+ k++, lcd_cfg++) {
+ unsigned long size = lcd_cfg->yres * lcd_cfg->xres;
+
+ if (size > max_size) {
+ max_cfg = lcd_cfg;
+ max_size = size;
+ }
+ }
+
+ if (!mode)
+ max_size = DEFAULT_XRES * DEFAULT_YRES;
+ else if (max_cfg)
+ dev_dbg(&pdev->dev, "Found largest videomode %ux%u\n",
+ max_cfg->xres, max_cfg->yres);
+
+ info->fix = sh_mobile_lcdc_fix;
+ info->fix.smem_len = max_size * (cfg->bpp / 8) * 2;
+
+ if (!mode)
+ mode = &default_720p;
+
+ fb_videomode_to_var(var, mode);
/* Default Y virtual resolution is 2x panel size */
var->yres_virtual = var->yres * 2;
- var->width = cfg->lcd_size_cfg.width;
- var->height = cfg->lcd_size_cfg.height;
var->activate = FB_ACTIVATE_NOW;
- var->left_margin = lcd_cfg->left_margin;
- var->right_margin = lcd_cfg->right_margin;
- var->upper_margin = lcd_cfg->upper_margin;
- var->lower_margin = lcd_cfg->lower_margin;
- var->hsync_len = lcd_cfg->hsync_len;
- var->vsync_len = lcd_cfg->vsync_len;
- var->sync = lcd_cfg->sync;
- var->pixclock = lcd_cfg->pixclock;
error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
if (error)
break;
- info->fix = sh_mobile_lcdc_fix;
- info->fix.line_length = lcd_cfg->xres * (cfg->bpp / 8);
- info->fix.smem_len = info->fix.line_length *
- var->yres_virtual;
-
buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
- &priv->ch[i].dma_handle, GFP_KERNEL);
+ &ch->dma_handle, GFP_KERNEL);
if (!buf) {
dev_err(&pdev->dev, "unable to allocate buffer\n");
error = -ENOMEM;
break;
}
- info->pseudo_palette = &priv->ch[i].pseudo_palette;
+ info->pseudo_palette = &ch->pseudo_palette;
info->flags = FBINFO_FLAG_DEFAULT;
error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
if (error < 0) {
dev_err(&pdev->dev, "unable to allocate cmap\n");
dma_free_coherent(&pdev->dev, info->fix.smem_len,
- buf, priv->ch[i].dma_handle);
+ buf, ch->dma_handle);
break;
}
- memset(buf, 0, info->fix.smem_len);
- info->fix.smem_start = priv->ch[i].dma_handle;
+ info->fix.smem_start = ch->dma_handle;
+ info->fix.line_length = var->xres * (cfg->bpp / 8);
info->screen_base = buf;
info->device = &pdev->dev;
- info->par = &priv->ch[i];
+ ch->display_var = *var;
}
if (error)
for (i = 0; i < j; i++) {
struct sh_mobile_lcdc_chan *ch = priv->ch + i;
+ const struct fb_videomode *mode = ch->cfg.lcd_cfg;
+
+ if (!mode)
+ mode = &default_720p;
info = ch->info;
}
}
+ fb_videomode_to_modelist(mode, ch->cfg.num_cfg, &info->modelist);
error = register_framebuffer(info);
if (error < 0)
goto err1;
pdev->name,
(ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
"mainlcd" : "sublcd",
- (int) ch->cfg.lcd_cfg.xres,
- (int) ch->cfg.lcd_cfg.yres,
+ info->var.xres, info->var.yres,
ch->cfg.bpp);
/* deferred io mode: disable clock to save power */
--- /dev/null
+#ifndef SH_MOBILE_LCDCFB_H
+#define SH_MOBILE_LCDCFB_H
+
+#include <linux/completion.h>
+#include <linux/fb.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+
+/* per-channel registers */
+enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
+ LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
+ LDHAJR,
+ NR_CH_REGS };
+
+#define PALETTE_NR 16
+
+struct sh_mobile_lcdc_priv;
+struct fb_info;
+
+struct sh_mobile_lcdc_chan {
+ struct sh_mobile_lcdc_priv *lcdc;
+ unsigned long *reg_offs;
+ unsigned long ldmt1r_value;
+ unsigned long enabled; /* ME and SE in LDCNT2R */
+ struct sh_mobile_lcdc_chan_cfg cfg;
+ u32 pseudo_palette[PALETTE_NR];
+ unsigned long saved_ch_regs[NR_CH_REGS];
+ struct fb_info *info;
+ dma_addr_t dma_handle;
+ struct fb_deferred_io defio;
+ struct scatterlist *sglist;
+ unsigned long frame_end;
+ unsigned long pan_offset;
+ wait_queue_head_t frame_end_wait;
+ struct completion vsync_completion;
+ struct fb_var_screeninfo display_var;
+ int use_count;
+ struct mutex open_lock; /* protects the use counter */
+};
+
+#endif
countdown_reset = periods > 2 ? periods - 2 : 0;
heartbeat = t;
- timeout_cnt = ((octeon_get_clock_rate() >> 8) * timeout_sec) >> 8;
+ timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
}
static int octeon_wdt_set_heartbeat(int t)
max_timeout_sec = 6;
do {
max_timeout_sec--;
- timeout_cnt = ((octeon_get_clock_rate() >> 8) * max_timeout_sec) >> 8;
+ timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * max_timeout_sec) >> 8;
} while (timeout_cnt > 65535);
BUG_ON(timeout_cnt == 0);
return rc;
}
-static int xenfs_get_sb(struct file_system_type *fs_type,
+static int xenfs_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_single(fs_type, flags, data, xenfs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, xenfs_fill_super);
}
static struct file_system_type xenfs_type = {
.owner = THIS_MODULE,
.name = "xenfs",
- .get_sb = xenfs_get_sb,
+ .mount = xenfs_mount,
.kill_sb = kill_litter_super,
};
* v9fs_fill_super - populate superblock with info
* @sb: superblock
* @v9ses: session information
- * @flags: flags propagated from v9fs_get_sb()
+ * @flags: flags propagated from v9fs_mount()
*
*/
}
/**
- * v9fs_get_sb - mount a superblock
+ * v9fs_mount - mount a superblock
* @fs_type: file system type
* @flags: mount flags
* @dev_name: device name that was mounted
* @data: mount options
- * @mnt: mountpoint record to be instantiated
*
*/
-static int v9fs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *v9fs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
struct super_block *sb = NULL;
struct inode *inode = NULL;
v9ses = kzalloc(sizeof(struct v9fs_session_info), GFP_KERNEL);
if (!v9ses)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
fid = v9fs_session_init(v9ses, dev_name, data);
if (IS_ERR(fid)) {
v9fs_fid_add(root, fid);
P9_DPRINTK(P9_DEBUG_VFS, " simple set mount, return 0\n");
- simple_set_mnt(mnt, sb);
- return 0;
+ return dget(sb->s_root);
clunk_fid:
p9_client_clunk(fid);
close_session:
v9fs_session_close(v9ses);
kfree(v9ses);
- return retval;
+ return ERR_PTR(retval);
+
release_sb:
/*
* we will do the session_close and root dentry release
*/
p9_client_clunk(fid);
deactivate_locked_super(sb);
- return retval;
+ return ERR_PTR(retval);
}
/**
struct file_system_type v9fs_fs_type = {
.name = "9p",
- .get_sb = v9fs_get_sb,
+ .mount = v9fs_mount,
.kill_sb = v9fs_kill_super,
.owner = THIS_MODULE,
.fs_flags = FS_RENAME_DOES_D_MOVE,
return -EINVAL;
}
-static int adfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *adfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, adfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, adfs_fill_super);
}
static struct file_system_type adfs_fs_type = {
.owner = THIS_MODULE,
.name = "adfs",
- .get_sb = adfs_get_sb,
+ .mount = adfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return 0;
}
-static int affs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *affs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, affs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, affs_fill_super);
}
static struct file_system_type affs_fs_type = {
.owner = THIS_MODULE,
.name = "affs",
- .get_sb = affs_get_sb,
+ .mount = affs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
#define AFS_FS_MAGIC 0x6B414653 /* 'kAFS' */
static void afs_i_init_once(void *foo);
-static int afs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name,
- void *data, struct vfsmount *mnt);
+static struct dentry *afs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data);
static struct inode *afs_alloc_inode(struct super_block *sb);
static void afs_put_super(struct super_block *sb);
static void afs_destroy_inode(struct inode *inode);
struct file_system_type afs_fs_type = {
.owner = THIS_MODULE,
.name = "afs",
- .get_sb = afs_get_sb,
+ .mount = afs_mount,
.kill_sb = kill_anon_super,
.fs_flags = 0,
};
/*
* get an AFS superblock
*/
-static int afs_get_sb(struct file_system_type *fs_type,
- int flags,
- const char *dev_name,
- void *options,
- struct vfsmount *mnt)
+static struct dentry *afs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *options)
{
struct afs_mount_params params;
struct super_block *sb;
ASSERTCMP(sb->s_flags, &, MS_ACTIVE);
}
- simple_set_mnt(mnt, sb);
afs_put_volume(params.volume);
afs_put_cell(params.cell);
kfree(new_opts);
_leave(" = 0 [%p]", sb);
- return 0;
+ return dget(sb->s_root);
error:
afs_put_volume(params.volume);
key_put(params.key);
kfree(new_opts);
_leave(" = %d", ret);
- return ret;
+ return ERR_PTR(ret);
}
/*
static struct inode *anon_inode_inode;
static const struct file_operations anon_inode_fops;
-static int anon_inodefs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *anon_inodefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "anon_inode:", NULL, ANON_INODE_FS_MAGIC,
- mnt);
+ return mount_pseudo(fs_type, "anon_inode:", NULL, ANON_INODE_FS_MAGIC);
}
/*
static struct file_system_type anon_inode_fs_type = {
.name = "anon_inodefs",
- .get_sb = anon_inodefs_get_sb,
+ .mount = anon_inodefs_mount,
.kill_sb = kill_anon_super,
};
static const struct dentry_operations anon_inodefs_dentry_operations = {
#include <linux/init.h>
#include "autofs_i.h"
-static int autofs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *autofs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, autofs4_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, autofs4_fill_super);
}
static struct file_system_type autofs_fs_type = {
.owner = THIS_MODULE,
.name = "autofs",
- .get_sb = autofs_get_sb,
+ .mount = autofs_mount,
.kill_sb = autofs4_kill_sb,
};
return 0;
}
-static int
-befs_get_sb(struct file_system_type *fs_type, int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+static struct dentry *
+befs_mount(struct file_system_type *fs_type, int flags, const char *dev_name,
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, befs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, befs_fill_super);
}
static struct file_system_type befs_fs_type = {
.owner = THIS_MODULE,
.name = "befs",
- .get_sb = befs_get_sb,
+ .mount = befs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return ret;
}
-static int bfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *bfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, bfs_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, bfs_fill_super);
}
static struct file_system_type bfs_fs_type = {
.owner = THIS_MODULE,
.name = "bfs",
- .get_sb = bfs_get_sb,
+ .mount = bfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return err;
}
-static int bm_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *bm_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, bm_fill_super, mnt);
+ return mount_single(fs_type, flags, data, bm_fill_super);
}
static struct linux_binfmt misc_format = {
static struct file_system_type bm_fs_type = {
.owner = THIS_MODULE,
.name = "binfmt_misc",
- .get_sb = bm_get_sb,
+ .mount = bm_mount,
.kill_sb = kill_litter_super,
};
.evict_inode = bdev_evict_inode,
};
-static int bd_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *bd_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "bdev:", &bdev_sops, 0x62646576, mnt);
+ return mount_pseudo(fs_type, "bdev:", &bdev_sops, 0x62646576);
}
static struct file_system_type bd_type = {
.name = "bdev",
- .get_sb = bd_get_sb,
+ .mount = bd_mount,
.kill_sb = kill_anon_super,
};
*/
static void end_compressed_bio_read(struct bio *bio, int err)
{
- struct extent_io_tree *tree;
struct compressed_bio *cb = bio->bi_private;
struct inode *inode;
struct page *page;
/* ok, we're the last bio for this extent, lets start
* the decompression.
*/
- tree = &BTRFS_I(inode)->io_tree;
ret = btrfs_zlib_decompress_biovec(cb->compressed_pages,
cb->start,
cb->orig_bio->bi_io_vec,
struct extent_buffer **cow_ret, u64 new_root_objectid)
{
struct extent_buffer *cow;
- u32 nritems;
int ret = 0;
int level;
struct btrfs_disk_key disk_key;
WARN_ON(root->ref_cows && trans->transid != root->last_trans);
level = btrfs_header_level(buf);
- nritems = btrfs_header_nritems(buf);
if (level == 0)
btrfs_item_key(buf, &disk_key, 0);
else
int wret;
int pslot;
int orig_slot = path->slots[level];
- int err_on_enospc = 0;
u64 orig_ptr;
if (level == 0)
BTRFS_NODEPTRS_PER_BLOCK(root) / 4)
return 0;
- if (btrfs_header_nritems(mid) < 2)
- err_on_enospc = 1;
+ btrfs_header_nritems(mid);
left = read_node_slot(root, parent, pslot - 1);
if (left) {
wret = push_node_left(trans, root, left, mid, 1);
if (wret < 0)
ret = wret;
- if (btrfs_header_nritems(mid) < 2)
- err_on_enospc = 1;
+ btrfs_header_nritems(mid);
}
/*
int wret;
int pslot;
int orig_slot = path->slots[level];
- u64 orig_ptr;
if (level == 0)
return 1;
mid = path->nodes[level];
WARN_ON(btrfs_header_generation(mid) != trans->transid);
- orig_ptr = btrfs_node_blockptr(mid, orig_slot);
if (level < BTRFS_MAX_LEVEL - 1)
parent = path->nodes[level + 1];
blocksize = btrfs_level_size(root, level - 1);
tmp = btrfs_find_tree_block(root, blocknr, blocksize);
- if (tmp && btrfs_buffer_uptodate(tmp, gen)) {
- /*
- * we found an up to date block without sleeping, return
- * right away
- */
- *eb_ret = tmp;
- return 0;
+ if (tmp) {
+ if (btrfs_buffer_uptodate(tmp, 0)) {
+ if (btrfs_buffer_uptodate(tmp, gen)) {
+ /*
+ * we found an up to date block without
+ * sleeping, return
+ * right away
+ */
+ *eb_ret = tmp;
+ return 0;
+ }
+ /* the pages were up to date, but we failed
+ * the generation number check. Do a full
+ * read for the generation number that is correct.
+ * We must do this without dropping locks so
+ * we can trust our generation number
+ */
+ free_extent_buffer(tmp);
+ tmp = read_tree_block(root, blocknr, blocksize, gen);
+ if (tmp && btrfs_buffer_uptodate(tmp, gen)) {
+ *eb_ret = tmp;
+ return 0;
+ }
+ free_extent_buffer(tmp);
+ btrfs_release_path(NULL, p);
+ return -EIO;
+ }
}
/*
btrfs_unlock_up_safe(p, level + 1);
btrfs_set_path_blocking(p);
- if (tmp)
- free_extent_buffer(tmp);
+ free_extent_buffer(tmp);
if (p->reada)
reada_for_search(root, p, level, slot, key->objectid);
{
struct btrfs_disk_key disk_key;
struct extent_buffer *right = path->nodes[0];
- int slot;
int i;
int push_space = 0;
int push_items = 0;
u32 this_item_size;
u32 old_left_item_size;
- slot = path->slots[1];
-
if (empty)
nr = min(right_nritems, max_slot);
else
{
int ret = 0;
int slot;
- int slot_orig;
struct extent_buffer *leaf;
struct btrfs_item *item;
u32 nritems;
unsigned int size_diff;
int i;
- slot_orig = path->slots[0];
leaf = path->nodes[0];
slot = path->slots[0];
{
int ret = 0;
int slot;
- int slot_orig;
struct extent_buffer *leaf;
struct btrfs_item *item;
u32 nritems;
unsigned int old_size;
int i;
- slot_orig = path->slots[0];
leaf = path->nodes[0];
nritems = btrfs_header_nritems(leaf);
struct btrfs_key *cpu_key, u32 *data_size,
int nr)
{
- struct extent_buffer *leaf;
int ret = 0;
int slot;
int i;
if (ret < 0)
goto out;
- leaf = path->nodes[0];
slot = path->slots[0];
BUG_ON(slot < 0);
*/
#define BTRFS_EXTENT_CSUM_OBJECTID -10ULL
+/* For storing free space cache */
+#define BTRFS_FREE_SPACE_OBJECTID -11ULL
+
/* dummy objectid represents multiple objectids */
#define BTRFS_MULTIPLE_OBJECTIDS -255ULL
/* additional stripes go here */
} __attribute__ ((__packed__));
+#define BTRFS_FREE_SPACE_EXTENT 1
+#define BTRFS_FREE_SPACE_BITMAP 2
+
+struct btrfs_free_space_entry {
+ __le64 offset;
+ __le64 bytes;
+ u8 type;
+} __attribute__ ((__packed__));
+
+struct btrfs_free_space_header {
+ struct btrfs_disk_key location;
+ __le64 generation;
+ __le64 num_entries;
+ __le64 num_bitmaps;
+} __attribute__ ((__packed__));
+
static inline unsigned long btrfs_chunk_item_size(int num_stripes)
{
BUG_ON(num_stripes == 0);
char label[BTRFS_LABEL_SIZE];
+ __le64 cache_generation;
+
/* future expansion */
- __le64 reserved[32];
+ __le64 reserved[31];
u8 sys_chunk_array[BTRFS_SYSTEM_CHUNK_ARRAY_SIZE];
} __attribute__ ((__packed__));
* ones specified below then we will fail to mount
*/
#define BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF (1ULL << 0)
-#define BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL (2ULL << 0)
+#define BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL (1ULL << 1)
+#define BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS (1ULL << 2)
#define BTRFS_FEATURE_COMPAT_SUPP 0ULL
#define BTRFS_FEATURE_COMPAT_RO_SUPP 0ULL
-#define BTRFS_FEATURE_INCOMPAT_SUPP \
- (BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF | \
- BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL)
+#define BTRFS_FEATURE_INCOMPAT_SUPP \
+ (BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF | \
+ BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL | \
+ BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS)
/*
* A leaf is full of items. offset and size tell us where to find
struct btrfs_space_info {
u64 flags;
- u64 total_bytes; /* total bytes in the space */
+ u64 total_bytes; /* total bytes in the space,
+ this doesn't take mirrors into account */
u64 bytes_used; /* total bytes used,
this does't take mirrors into account */
u64 bytes_pinned; /* total bytes pinned, will be freed when the
u64 bytes_may_use; /* number of bytes that may be used for
delalloc/allocations */
u64 disk_used; /* total bytes used on disk */
+ u64 disk_total; /* total bytes on disk, takes mirrors into
+ account */
int full; /* indicates that we cannot allocate any more
chunks for this space */
BTRFS_CACHE_FINISHED = 2,
};
+enum btrfs_disk_cache_state {
+ BTRFS_DC_WRITTEN = 0,
+ BTRFS_DC_ERROR = 1,
+ BTRFS_DC_CLEAR = 2,
+ BTRFS_DC_SETUP = 3,
+ BTRFS_DC_NEED_WRITE = 4,
+};
+
struct btrfs_caching_control {
struct list_head list;
struct mutex mutex;
struct btrfs_key key;
struct btrfs_block_group_item item;
struct btrfs_fs_info *fs_info;
+ struct inode *inode;
spinlock_t lock;
u64 pinned;
u64 reserved;
int extents_thresh;
int free_extents;
int total_bitmaps;
- int ro;
- int dirty;
+ int ro:1;
+ int dirty:1;
+ int iref:1;
+
+ int disk_cache_state;
/* cache tracking stuff */
int cached;
struct btrfs_transaction *running_transaction;
wait_queue_head_t transaction_throttle;
wait_queue_head_t transaction_wait;
+ wait_queue_head_t transaction_blocked_wait;
wait_queue_head_t async_submit_wait;
struct btrfs_super_block super_copy;
struct btrfs_workers endio_meta_workers;
struct btrfs_workers endio_meta_write_workers;
struct btrfs_workers endio_write_workers;
+ struct btrfs_workers endio_freespace_worker;
struct btrfs_workers submit_workers;
/*
* fixup workers take dirty pages that didn't properly go through
#define BTRFS_MOUNT_NOSSD (1 << 9)
#define BTRFS_MOUNT_DISCARD (1 << 10)
#define BTRFS_MOUNT_FORCE_COMPRESS (1 << 11)
+#define BTRFS_MOUNT_SPACE_CACHE (1 << 12)
+#define BTRFS_MOUNT_CLEAR_CACHE (1 << 13)
+#define BTRFS_MOUNT_USER_SUBVOL_RM_ALLOWED (1 << 14)
#define btrfs_clear_opt(o, opt) ((o) &= ~BTRFS_MOUNT_##opt)
#define btrfs_set_opt(o, opt) ((o) |= BTRFS_MOUNT_##opt)
write_eb_member(eb, item, struct btrfs_dir_item, location, key);
}
+BTRFS_SETGET_FUNCS(free_space_entries, struct btrfs_free_space_header,
+ num_entries, 64);
+BTRFS_SETGET_FUNCS(free_space_bitmaps, struct btrfs_free_space_header,
+ num_bitmaps, 64);
+BTRFS_SETGET_FUNCS(free_space_generation, struct btrfs_free_space_header,
+ generation, 64);
+
+static inline void btrfs_free_space_key(struct extent_buffer *eb,
+ struct btrfs_free_space_header *h,
+ struct btrfs_disk_key *key)
+{
+ read_eb_member(eb, h, struct btrfs_free_space_header, location, key);
+}
+
+static inline void btrfs_set_free_space_key(struct extent_buffer *eb,
+ struct btrfs_free_space_header *h,
+ struct btrfs_disk_key *key)
+{
+ write_eb_member(eb, h, struct btrfs_free_space_header, location, key);
+}
+
/* struct btrfs_disk_key */
BTRFS_SETGET_STACK_FUNCS(disk_key_objectid, struct btrfs_disk_key,
objectid, 64);
incompat_flags, 64);
BTRFS_SETGET_STACK_FUNCS(super_csum_type, struct btrfs_super_block,
csum_type, 16);
+BTRFS_SETGET_STACK_FUNCS(super_cache_generation, struct btrfs_super_block,
+ cache_generation, 64);
static inline int btrfs_super_csum_size(struct btrfs_super_block *s)
{
return file->f_path.dentry;
}
+static inline bool btrfs_mixed_space_info(struct btrfs_space_info *space_info)
+{
+ return ((space_info->flags & BTRFS_BLOCK_GROUP_METADATA) &&
+ (space_info->flags & BTRFS_BLOCK_GROUP_DATA));
+}
+
/* extent-tree.c */
void btrfs_put_block_group(struct btrfs_block_group_cache *cache);
int btrfs_run_delayed_refs(struct btrfs_trans_handle *trans,
void btrfs_free_reserved_data_space(struct inode *inode, u64 bytes);
int btrfs_trans_reserve_metadata(struct btrfs_trans_handle *trans,
struct btrfs_root *root,
- int num_items, int *retries);
+ int num_items);
void btrfs_trans_release_metadata(struct btrfs_trans_handle *trans,
struct btrfs_root *root);
int btrfs_orphan_reserve_metadata(struct btrfs_trans_handle *trans,
int btrfs_block_rsv_add(struct btrfs_trans_handle *trans,
struct btrfs_root *root,
struct btrfs_block_rsv *block_rsv,
- u64 num_bytes, int *retries);
+ u64 num_bytes);
int btrfs_block_rsv_check(struct btrfs_trans_handle *trans,
struct btrfs_root *root,
struct btrfs_block_rsv *block_rsv,
struct btrfs_block_group_cache *cache);
int btrfs_set_block_group_rw(struct btrfs_root *root,
struct btrfs_block_group_cache *cache);
+void btrfs_put_block_group_cache(struct btrfs_fs_info *info);
/* ctree.c */
int btrfs_bin_search(struct extent_buffer *eb, struct btrfs_key *key,
int level, int *slot);
u32 min_type);
int btrfs_start_delalloc_inodes(struct btrfs_root *root, int delay_iput);
-int btrfs_start_one_delalloc_inode(struct btrfs_root *root, int delay_iput);
+int btrfs_start_one_delalloc_inode(struct btrfs_root *root, int delay_iput,
+ int sync);
int btrfs_set_extent_delalloc(struct inode *inode, u64 start, u64 end,
struct extent_state **cached_state);
int btrfs_writepages(struct address_space *mapping,
int btrfs_prealloc_file_range(struct inode *inode, int mode,
u64 start, u64 num_bytes, u64 min_size,
loff_t actual_len, u64 *alloc_hint);
+int btrfs_prealloc_file_range_trans(struct inode *inode,
+ struct btrfs_trans_handle *trans, int mode,
+ u64 start, u64 num_bytes, u64 min_size,
+ loff_t actual_len, u64 *alloc_hint);
extern const struct dentry_operations btrfs_dentry_operations;
/* ioctl.c */
ret = btrfs_truncate_item(trans, root, path,
item_len - sub_item_len, 1);
}
- return 0;
+ return ret;
}
struct extent_io_tree *tree;
u64 start = (u64)page->index << PAGE_CACHE_SHIFT;
u64 found_start;
- int found_level;
unsigned long len;
struct extent_buffer *eb;
int ret;
WARN_ON(1);
goto err;
}
- found_level = btrfs_header_level(eb);
-
csum_tree_block(root, eb, 0);
err:
free_extent_buffer(eb);
end_io_wq->work.flags = 0;
if (bio->bi_rw & REQ_WRITE) {
- if (end_io_wq->metadata)
+ if (end_io_wq->metadata == 1)
btrfs_queue_worker(&fs_info->endio_meta_write_workers,
&end_io_wq->work);
+ else if (end_io_wq->metadata == 2)
+ btrfs_queue_worker(&fs_info->endio_freespace_worker,
+ &end_io_wq->work);
else
btrfs_queue_worker(&fs_info->endio_write_workers,
&end_io_wq->work);
}
}
+/*
+ * For the metadata arg you want
+ *
+ * 0 - if data
+ * 1 - if normal metadta
+ * 2 - if writing to the free space cache area
+ */
int btrfs_bio_wq_end_io(struct btrfs_fs_info *info, struct bio *bio,
int metadata)
{
static void run_one_async_start(struct btrfs_work *work)
{
- struct btrfs_fs_info *fs_info;
struct async_submit_bio *async;
async = container_of(work, struct async_submit_bio, work);
- fs_info = BTRFS_I(async->inode)->root->fs_info;
async->submit_bio_start(async->inode, async->rw, async->bio,
async->mirror_num, async->bio_flags,
async->bio_offset);
u32 blocksize, u64 parent_transid)
{
struct extent_buffer *buf = NULL;
- struct inode *btree_inode = root->fs_info->btree_inode;
- struct extent_io_tree *io_tree;
int ret;
- io_tree = &BTRFS_I(btree_inode)->io_tree;
-
buf = btrfs_find_create_tree_block(root, bytenr, blocksize);
if (!buf)
return NULL;
u64 start = 0;
struct page *page;
struct extent_io_tree *io_tree = NULL;
- struct btrfs_fs_info *info = NULL;
struct bio_vec *bvec;
int i;
int ret;
buf_len = page->private >> 2;
start = page_offset(page) + bvec->bv_offset;
io_tree = &BTRFS_I(page->mapping->host)->io_tree;
- info = BTRFS_I(page->mapping->host)->root->fs_info;
}
/* are we fully contained in this bio? */
if (buf_len <= length)
init_waitqueue_head(&fs_info->transaction_throttle);
init_waitqueue_head(&fs_info->transaction_wait);
+ init_waitqueue_head(&fs_info->transaction_blocked_wait);
init_waitqueue_head(&fs_info->async_submit_wait);
__setup_root(4096, 4096, 4096, 4096, tree_root,
fs_info, BTRFS_ROOT_TREE_OBJECTID);
-
bh = btrfs_read_dev_super(fs_devices->latest_bdev);
if (!bh)
goto fail_iput;
btrfs_init_workers(&fs_info->endio_write_workers, "endio-write",
fs_info->thread_pool_size,
&fs_info->generic_worker);
+ btrfs_init_workers(&fs_info->endio_freespace_worker, "freespace-write",
+ 1, &fs_info->generic_worker);
/*
* endios are largely parallel and should have a very
btrfs_start_workers(&fs_info->endio_meta_workers, 1);
btrfs_start_workers(&fs_info->endio_meta_write_workers, 1);
btrfs_start_workers(&fs_info->endio_write_workers, 1);
+ btrfs_start_workers(&fs_info->endio_freespace_worker, 1);
fs_info->bdi.ra_pages *= btrfs_super_num_devices(disk_super);
fs_info->bdi.ra_pages = max(fs_info->bdi.ra_pages,
if (!(sb->s_flags & MS_RDONLY)) {
down_read(&fs_info->cleanup_work_sem);
btrfs_orphan_cleanup(fs_info->fs_root);
+ btrfs_orphan_cleanup(fs_info->tree_root);
up_read(&fs_info->cleanup_work_sem);
}
btrfs_stop_workers(&fs_info->endio_meta_workers);
btrfs_stop_workers(&fs_info->endio_meta_write_workers);
btrfs_stop_workers(&fs_info->endio_write_workers);
+ btrfs_stop_workers(&fs_info->endio_freespace_worker);
btrfs_stop_workers(&fs_info->submit_workers);
fail_iput:
invalidate_inode_pages2(fs_info->btree_inode->i_mapping);
fs_info->closing = 1;
smp_mb();
+ btrfs_put_block_group_cache(fs_info);
if (!(fs_info->sb->s_flags & MS_RDONLY)) {
ret = btrfs_commit_super(root);
if (ret)
btrfs_stop_workers(&fs_info->endio_meta_workers);
btrfs_stop_workers(&fs_info->endio_meta_write_workers);
btrfs_stop_workers(&fs_info->endio_write_workers);
+ btrfs_stop_workers(&fs_info->endio_freespace_worker);
btrfs_stop_workers(&fs_info->submit_workers);
btrfs_close_devices(fs_info->fs_devices);
return NULL;
}
+ /* We're loading it the fast way, so we don't have a caching_ctl. */
+ if (!cache->caching_ctl) {
+ spin_unlock(&cache->lock);
+ return NULL;
+ }
+
ctl = cache->caching_ctl;
atomic_inc(&ctl->count);
spin_unlock(&cache->lock);
return 0;
}
-static int cache_block_group(struct btrfs_block_group_cache *cache)
+static int cache_block_group(struct btrfs_block_group_cache *cache,
+ struct btrfs_trans_handle *trans,
+ int load_cache_only)
{
struct btrfs_fs_info *fs_info = cache->fs_info;
struct btrfs_caching_control *caching_ctl;
if (cache->cached != BTRFS_CACHE_NO)
return 0;
+ /*
+ * We can't do the read from on-disk cache during a commit since we need
+ * to have the normal tree locking.
+ */
+ if (!trans->transaction->in_commit) {
+ spin_lock(&cache->lock);
+ if (cache->cached != BTRFS_CACHE_NO) {
+ spin_unlock(&cache->lock);
+ return 0;
+ }
+ cache->cached = BTRFS_CACHE_STARTED;
+ spin_unlock(&cache->lock);
+
+ ret = load_free_space_cache(fs_info, cache);
+
+ spin_lock(&cache->lock);
+ if (ret == 1) {
+ cache->cached = BTRFS_CACHE_FINISHED;
+ cache->last_byte_to_unpin = (u64)-1;
+ } else {
+ cache->cached = BTRFS_CACHE_NO;
+ }
+ spin_unlock(&cache->lock);
+ if (ret == 1)
+ return 0;
+ }
+
+ if (load_cache_only)
+ return 0;
+
caching_ctl = kzalloc(sizeof(*caching_ctl), GFP_KERNEL);
BUG_ON(!caching_ctl);
rcu_read_lock();
list_for_each_entry_rcu(found, head, list) {
- if (found->flags == flags) {
+ if (found->flags & flags) {
rcu_read_unlock();
return found;
}
return num;
}
+static u64 div_factor_fine(u64 num, int factor)
+{
+ if (factor == 100)
+ return num;
+ num *= factor;
+ do_div(num, 100);
+ return num;
+}
+
u64 btrfs_find_block_group(struct btrfs_root *root,
u64 search_start, u64 search_hint, int owner)
{
return cache;
}
+static int cache_save_setup(struct btrfs_block_group_cache *block_group,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_path *path)
+{
+ struct btrfs_root *root = block_group->fs_info->tree_root;
+ struct inode *inode = NULL;
+ u64 alloc_hint = 0;
+ int num_pages = 0;
+ int retries = 0;
+ int ret = 0;
+
+ /*
+ * If this block group is smaller than 100 megs don't bother caching the
+ * block group.
+ */
+ if (block_group->key.offset < (100 * 1024 * 1024)) {
+ spin_lock(&block_group->lock);
+ block_group->disk_cache_state = BTRFS_DC_WRITTEN;
+ spin_unlock(&block_group->lock);
+ return 0;
+ }
+
+again:
+ inode = lookup_free_space_inode(root, block_group, path);
+ if (IS_ERR(inode) && PTR_ERR(inode) != -ENOENT) {
+ ret = PTR_ERR(inode);
+ btrfs_release_path(root, path);
+ goto out;
+ }
+
+ if (IS_ERR(inode)) {
+ BUG_ON(retries);
+ retries++;
+
+ if (block_group->ro)
+ goto out_free;
+
+ ret = create_free_space_inode(root, trans, block_group, path);
+ if (ret)
+ goto out_free;
+ goto again;
+ }
+
+ /*
+ * We want to set the generation to 0, that way if anything goes wrong
+ * from here on out we know not to trust this cache when we load up next
+ * time.
+ */
+ BTRFS_I(inode)->generation = 0;
+ ret = btrfs_update_inode(trans, root, inode);
+ WARN_ON(ret);
+
+ if (i_size_read(inode) > 0) {
+ ret = btrfs_truncate_free_space_cache(root, trans, path,
+ inode);
+ if (ret)
+ goto out_put;
+ }
+
+ spin_lock(&block_group->lock);
+ if (block_group->cached != BTRFS_CACHE_FINISHED) {
+ spin_unlock(&block_group->lock);
+ goto out_put;
+ }
+ spin_unlock(&block_group->lock);
+
+ num_pages = (int)div64_u64(block_group->key.offset, 1024 * 1024 * 1024);
+ if (!num_pages)
+ num_pages = 1;
+
+ /*
+ * Just to make absolutely sure we have enough space, we're going to
+ * preallocate 12 pages worth of space for each block group. In
+ * practice we ought to use at most 8, but we need extra space so we can
+ * add our header and have a terminator between the extents and the
+ * bitmaps.
+ */
+ num_pages *= 16;
+ num_pages *= PAGE_CACHE_SIZE;
+
+ ret = btrfs_check_data_free_space(inode, num_pages);
+ if (ret)
+ goto out_put;
+
+ ret = btrfs_prealloc_file_range_trans(inode, trans, 0, 0, num_pages,
+ num_pages, num_pages,
+ &alloc_hint);
+ btrfs_free_reserved_data_space(inode, num_pages);
+out_put:
+ iput(inode);
+out_free:
+ btrfs_release_path(root, path);
+out:
+ spin_lock(&block_group->lock);
+ if (ret)
+ block_group->disk_cache_state = BTRFS_DC_ERROR;
+ else
+ block_group->disk_cache_state = BTRFS_DC_SETUP;
+ spin_unlock(&block_group->lock);
+
+ return ret;
+}
+
int btrfs_write_dirty_block_groups(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
if (!path)
return -ENOMEM;
+again:
+ while (1) {
+ cache = btrfs_lookup_first_block_group(root->fs_info, last);
+ while (cache) {
+ if (cache->disk_cache_state == BTRFS_DC_CLEAR)
+ break;
+ cache = next_block_group(root, cache);
+ }
+ if (!cache) {
+ if (last == 0)
+ break;
+ last = 0;
+ continue;
+ }
+ err = cache_save_setup(cache, trans, path);
+ last = cache->key.objectid + cache->key.offset;
+ btrfs_put_block_group(cache);
+ }
+
while (1) {
if (last == 0) {
err = btrfs_run_delayed_refs(trans, root,
cache = btrfs_lookup_first_block_group(root->fs_info, last);
while (cache) {
+ if (cache->disk_cache_state == BTRFS_DC_CLEAR) {
+ btrfs_put_block_group(cache);
+ goto again;
+ }
+
if (cache->dirty)
break;
cache = next_block_group(root, cache);
continue;
}
+ if (cache->disk_cache_state == BTRFS_DC_SETUP)
+ cache->disk_cache_state = BTRFS_DC_NEED_WRITE;
cache->dirty = 0;
last = cache->key.objectid + cache->key.offset;
btrfs_put_block_group(cache);
}
+ while (1) {
+ /*
+ * I don't think this is needed since we're just marking our
+ * preallocated extent as written, but just in case it can't
+ * hurt.
+ */
+ if (last == 0) {
+ err = btrfs_run_delayed_refs(trans, root,
+ (unsigned long)-1);
+ BUG_ON(err);
+ }
+
+ cache = btrfs_lookup_first_block_group(root->fs_info, last);
+ while (cache) {
+ /*
+ * Really this shouldn't happen, but it could if we
+ * couldn't write the entire preallocated extent and
+ * splitting the extent resulted in a new block.
+ */
+ if (cache->dirty) {
+ btrfs_put_block_group(cache);
+ goto again;
+ }
+ if (cache->disk_cache_state == BTRFS_DC_NEED_WRITE)
+ break;
+ cache = next_block_group(root, cache);
+ }
+ if (!cache) {
+ if (last == 0)
+ break;
+ last = 0;
+ continue;
+ }
+
+ btrfs_write_out_cache(root, trans, cache, path);
+
+ /*
+ * If we didn't have an error then the cache state is still
+ * NEED_WRITE, so we can set it to WRITTEN.
+ */
+ if (cache->disk_cache_state == BTRFS_DC_NEED_WRITE)
+ cache->disk_cache_state = BTRFS_DC_WRITTEN;
+ last = cache->key.objectid + cache->key.offset;
+ btrfs_put_block_group(cache);
+ }
+
btrfs_free_path(path);
return 0;
}
if (found) {
spin_lock(&found->lock);
found->total_bytes += total_bytes;
+ found->disk_total += total_bytes * factor;
found->bytes_used += bytes_used;
found->disk_used += bytes_used * factor;
found->full = 0;
BTRFS_BLOCK_GROUP_SYSTEM |
BTRFS_BLOCK_GROUP_METADATA);
found->total_bytes = total_bytes;
+ found->disk_total = total_bytes * factor;
found->bytes_used = bytes_used;
found->disk_used = bytes_used * factor;
found->bytes_pinned = 0;
struct btrfs_space_info *data_sinfo;
struct btrfs_root *root = BTRFS_I(inode)->root;
u64 used;
- int ret = 0, committed = 0;
+ int ret = 0, committed = 0, alloc_chunk = 1;
/* make sure bytes are sectorsize aligned */
bytes = (bytes + root->sectorsize - 1) & ~((u64)root->sectorsize - 1);
+ if (root == root->fs_info->tree_root) {
+ alloc_chunk = 0;
+ committed = 1;
+ }
+
data_sinfo = BTRFS_I(inode)->space_info;
if (!data_sinfo)
goto alloc;
* if we don't have enough free bytes in this space then we need
* to alloc a new chunk.
*/
- if (!data_sinfo->full) {
+ if (!data_sinfo->full && alloc_chunk) {
u64 alloc_target;
data_sinfo->force_alloc = 1;
rcu_read_unlock();
}
-static int should_alloc_chunk(struct btrfs_space_info *sinfo,
- u64 alloc_bytes)
+static int should_alloc_chunk(struct btrfs_root *root,
+ struct btrfs_space_info *sinfo, u64 alloc_bytes)
{
u64 num_bytes = sinfo->total_bytes - sinfo->bytes_readonly;
+ u64 thresh;
if (sinfo->bytes_used + sinfo->bytes_reserved +
alloc_bytes + 256 * 1024 * 1024 < num_bytes)
alloc_bytes < div_factor(num_bytes, 8))
return 0;
+ thresh = btrfs_super_total_bytes(&root->fs_info->super_copy);
+ thresh = max_t(u64, 256 * 1024 * 1024, div_factor_fine(thresh, 5));
+
+ if (num_bytes > thresh && sinfo->bytes_used < div_factor(num_bytes, 3))
+ return 0;
+
return 1;
}
goto out;
}
- if (!force && !should_alloc_chunk(space_info, alloc_bytes)) {
+ if (!force && !should_alloc_chunk(extent_root, space_info,
+ alloc_bytes)) {
spin_unlock(&space_info->lock);
goto out;
}
spin_unlock(&space_info->lock);
+ /*
+ * If we have mixed data/metadata chunks we want to make sure we keep
+ * allocating mixed chunks instead of individual chunks.
+ */
+ if (btrfs_mixed_space_info(space_info))
+ flags |= (BTRFS_BLOCK_GROUP_DATA | BTRFS_BLOCK_GROUP_METADATA);
+
/*
* if we're doing a data chunk, go ahead and make sure that
* we keep a reasonable number of metadata chunks allocated in the
return ret;
}
-static int maybe_allocate_chunk(struct btrfs_trans_handle *trans,
- struct btrfs_root *root,
- struct btrfs_space_info *sinfo, u64 num_bytes)
-{
- int ret;
- int end_trans = 0;
-
- if (sinfo->full)
- return 0;
-
- spin_lock(&sinfo->lock);
- ret = should_alloc_chunk(sinfo, num_bytes + 2 * 1024 * 1024);
- spin_unlock(&sinfo->lock);
- if (!ret)
- return 0;
-
- if (!trans) {
- trans = btrfs_join_transaction(root, 1);
- BUG_ON(IS_ERR(trans));
- end_trans = 1;
- }
-
- ret = do_chunk_alloc(trans, root->fs_info->extent_root,
- num_bytes + 2 * 1024 * 1024,
- get_alloc_profile(root, sinfo->flags), 0);
-
- if (end_trans)
- btrfs_end_transaction(trans, root);
-
- return ret == 1 ? 1 : 0;
-}
-
/*
* shrink metadata reservation for delalloc
*/
static int shrink_delalloc(struct btrfs_trans_handle *trans,
- struct btrfs_root *root, u64 to_reclaim)
+ struct btrfs_root *root, u64 to_reclaim, int sync)
{
struct btrfs_block_rsv *block_rsv;
+ struct btrfs_space_info *space_info;
u64 reserved;
u64 max_reclaim;
u64 reclaimed = 0;
int pause = 1;
- int ret;
+ int nr_pages = (2 * 1024 * 1024) >> PAGE_CACHE_SHIFT;
block_rsv = &root->fs_info->delalloc_block_rsv;
- spin_lock(&block_rsv->lock);
- reserved = block_rsv->reserved;
- spin_unlock(&block_rsv->lock);
+ space_info = block_rsv->space_info;
+
+ smp_mb();
+ reserved = space_info->bytes_reserved;
if (reserved == 0)
return 0;
max_reclaim = min(reserved, to_reclaim);
while (1) {
- ret = btrfs_start_one_delalloc_inode(root, trans ? 1 : 0);
- if (!ret) {
- __set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(pause);
- pause <<= 1;
- if (pause > HZ / 10)
- pause = HZ / 10;
- } else {
- pause = 1;
- }
+ /* have the flusher threads jump in and do some IO */
+ smp_mb();
+ nr_pages = min_t(unsigned long, nr_pages,
+ root->fs_info->delalloc_bytes >> PAGE_CACHE_SHIFT);
+ writeback_inodes_sb_nr_if_idle(root->fs_info->sb, nr_pages);
- spin_lock(&block_rsv->lock);
- if (reserved > block_rsv->reserved)
- reclaimed = reserved - block_rsv->reserved;
- reserved = block_rsv->reserved;
- spin_unlock(&block_rsv->lock);
+ spin_lock(&space_info->lock);
+ if (reserved > space_info->bytes_reserved)
+ reclaimed += reserved - space_info->bytes_reserved;
+ reserved = space_info->bytes_reserved;
+ spin_unlock(&space_info->lock);
if (reserved == 0 || reclaimed >= max_reclaim)
break;
if (trans && trans->transaction->blocked)
return -EAGAIN;
+
+ __set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(pause);
+ pause <<= 1;
+ if (pause > HZ / 10)
+ pause = HZ / 10;
+
}
return reclaimed >= to_reclaim;
}
-static int should_retry_reserve(struct btrfs_trans_handle *trans,
- struct btrfs_root *root,
- struct btrfs_block_rsv *block_rsv,
- u64 num_bytes, int *retries)
+/*
+ * Retries tells us how many times we've called reserve_metadata_bytes. The
+ * idea is if this is the first call (retries == 0) then we will add to our
+ * reserved count if we can't make the allocation in order to hold our place
+ * while we go and try and free up space. That way for retries > 1 we don't try
+ * and add space, we just check to see if the amount of unused space is >= the
+ * total space, meaning that our reservation is valid.
+ *
+ * However if we don't intend to retry this reservation, pass -1 as retries so
+ * that it short circuits this logic.
+ */
+static int reserve_metadata_bytes(struct btrfs_trans_handle *trans,
+ struct btrfs_root *root,
+ struct btrfs_block_rsv *block_rsv,
+ u64 orig_bytes, int flush)
{
struct btrfs_space_info *space_info = block_rsv->space_info;
- int ret;
+ u64 unused;
+ u64 num_bytes = orig_bytes;
+ int retries = 0;
+ int ret = 0;
+ bool reserved = false;
+ bool committed = false;
- if ((*retries) > 2)
- return -ENOSPC;
+again:
+ ret = -ENOSPC;
+ if (reserved)
+ num_bytes = 0;
- ret = maybe_allocate_chunk(trans, root, space_info, num_bytes);
- if (ret)
- return 1;
+ spin_lock(&space_info->lock);
+ unused = space_info->bytes_used + space_info->bytes_reserved +
+ space_info->bytes_pinned + space_info->bytes_readonly +
+ space_info->bytes_may_use;
- if (trans && trans->transaction->in_commit)
- return -ENOSPC;
+ /*
+ * The idea here is that we've not already over-reserved the block group
+ * then we can go ahead and save our reservation first and then start
+ * flushing if we need to. Otherwise if we've already overcommitted
+ * lets start flushing stuff first and then come back and try to make
+ * our reservation.
+ */
+ if (unused <= space_info->total_bytes) {
+ unused -= space_info->total_bytes;
+ if (unused >= num_bytes) {
+ if (!reserved)
+ space_info->bytes_reserved += orig_bytes;
+ ret = 0;
+ } else {
+ /*
+ * Ok set num_bytes to orig_bytes since we aren't
+ * overocmmitted, this way we only try and reclaim what
+ * we need.
+ */
+ num_bytes = orig_bytes;
+ }
+ } else {
+ /*
+ * Ok we're over committed, set num_bytes to the overcommitted
+ * amount plus the amount of bytes that we need for this
+ * reservation.
+ */
+ num_bytes = unused - space_info->total_bytes +
+ (orig_bytes * (retries + 1));
+ }
- ret = shrink_delalloc(trans, root, num_bytes);
- if (ret)
- return ret;
+ /*
+ * Couldn't make our reservation, save our place so while we're trying
+ * to reclaim space we can actually use it instead of somebody else
+ * stealing it from us.
+ */
+ if (ret && !reserved) {
+ space_info->bytes_reserved += orig_bytes;
+ reserved = true;
+ }
- spin_lock(&space_info->lock);
- if (space_info->bytes_pinned < num_bytes)
- ret = 1;
spin_unlock(&space_info->lock);
- if (ret)
- return -ENOSPC;
-
- (*retries)++;
- if (trans)
- return -EAGAIN;
+ if (!ret)
+ return 0;
- trans = btrfs_join_transaction(root, 1);
- BUG_ON(IS_ERR(trans));
- ret = btrfs_commit_transaction(trans, root);
- BUG_ON(ret);
+ if (!flush)
+ goto out;
- return 1;
-}
+ /*
+ * We do synchronous shrinking since we don't actually unreserve
+ * metadata until after the IO is completed.
+ */
+ ret = shrink_delalloc(trans, root, num_bytes, 1);
+ if (ret > 0)
+ return 0;
+ else if (ret < 0)
+ goto out;
-static int reserve_metadata_bytes(struct btrfs_block_rsv *block_rsv,
- u64 num_bytes)
-{
- struct btrfs_space_info *space_info = block_rsv->space_info;
- u64 unused;
- int ret = -ENOSPC;
+ /*
+ * So if we were overcommitted it's possible that somebody else flushed
+ * out enough space and we simply didn't have enough space to reclaim,
+ * so go back around and try again.
+ */
+ if (retries < 2) {
+ retries++;
+ goto again;
+ }
spin_lock(&space_info->lock);
- unused = space_info->bytes_used + space_info->bytes_reserved +
- space_info->bytes_pinned + space_info->bytes_readonly;
+ /*
+ * Not enough space to be reclaimed, don't bother committing the
+ * transaction.
+ */
+ if (space_info->bytes_pinned < orig_bytes)
+ ret = -ENOSPC;
+ spin_unlock(&space_info->lock);
+ if (ret)
+ goto out;
- if (unused < space_info->total_bytes)
- unused = space_info->total_bytes - unused;
- else
- unused = 0;
+ ret = -EAGAIN;
+ if (trans || committed)
+ goto out;
- if (unused >= num_bytes) {
- if (block_rsv->priority >= 10) {
- space_info->bytes_reserved += num_bytes;
- ret = 0;
- } else {
- if ((unused + block_rsv->reserved) *
- block_rsv->priority >=
- (num_bytes + block_rsv->reserved) * 10) {
- space_info->bytes_reserved += num_bytes;
- ret = 0;
- }
- }
+ ret = -ENOSPC;
+ trans = btrfs_join_transaction(root, 1);
+ if (IS_ERR(trans))
+ goto out;
+ ret = btrfs_commit_transaction(trans, root);
+ if (!ret) {
+ trans = NULL;
+ committed = true;
+ goto again;
+ }
+
+out:
+ if (reserved) {
+ spin_lock(&space_info->lock);
+ space_info->bytes_reserved -= orig_bytes;
+ spin_unlock(&space_info->lock);
}
- spin_unlock(&space_info->lock);
return ret;
}
{
struct btrfs_block_rsv *block_rsv;
struct btrfs_fs_info *fs_info = root->fs_info;
- u64 alloc_target;
block_rsv = kmalloc(sizeof(*block_rsv), GFP_NOFS);
if (!block_rsv)
return NULL;
btrfs_init_block_rsv(block_rsv);
-
- alloc_target = btrfs_get_alloc_profile(root, 0);
block_rsv->space_info = __find_space_info(fs_info,
BTRFS_BLOCK_GROUP_METADATA);
-
return block_rsv;
}
int btrfs_block_rsv_add(struct btrfs_trans_handle *trans,
struct btrfs_root *root,
struct btrfs_block_rsv *block_rsv,
- u64 num_bytes, int *retries)
+ u64 num_bytes)
{
int ret;
if (num_bytes == 0)
return 0;
-again:
- ret = reserve_metadata_bytes(block_rsv, num_bytes);
+
+ ret = reserve_metadata_bytes(trans, root, block_rsv, num_bytes, 1);
if (!ret) {
block_rsv_add_bytes(block_rsv, num_bytes, 1);
return 0;
}
- ret = should_retry_reserve(trans, root, block_rsv, num_bytes, retries);
- if (ret > 0)
- goto again;
-
return ret;
}
return 0;
if (block_rsv->refill_used) {
- ret = reserve_metadata_bytes(block_rsv, num_bytes);
+ ret = reserve_metadata_bytes(trans, root, block_rsv,
+ num_bytes, 0);
if (!ret) {
block_rsv_add_bytes(block_rsv, num_bytes, 0);
return 0;
sinfo = __find_space_info(fs_info, BTRFS_BLOCK_GROUP_METADATA);
spin_lock(&sinfo->lock);
+ if (sinfo->flags & BTRFS_BLOCK_GROUP_DATA)
+ data_used = 0;
meta_used = sinfo->bytes_used;
spin_unlock(&sinfo->lock);
block_rsv->size = num_bytes;
num_bytes = sinfo->bytes_used + sinfo->bytes_pinned +
- sinfo->bytes_reserved + sinfo->bytes_readonly;
+ sinfo->bytes_reserved + sinfo->bytes_readonly +
+ sinfo->bytes_may_use;
if (sinfo->total_bytes > num_bytes) {
num_bytes = sinfo->total_bytes - num_bytes;
int btrfs_trans_reserve_metadata(struct btrfs_trans_handle *trans,
struct btrfs_root *root,
- int num_items, int *retries)
+ int num_items)
{
u64 num_bytes;
int ret;
num_bytes = calc_trans_metadata_size(root, num_items);
ret = btrfs_block_rsv_add(trans, root, &root->fs_info->trans_block_rsv,
- num_bytes, retries);
+ num_bytes);
if (!ret) {
trans->bytes_reserved += num_bytes;
trans->block_rsv = &root->fs_info->trans_block_rsv;
struct btrfs_block_rsv *block_rsv = &root->fs_info->delalloc_block_rsv;
u64 to_reserve;
int nr_extents;
- int retries = 0;
int ret;
if (btrfs_transaction_in_commit(root->fs_info))
schedule_timeout(1);
num_bytes = ALIGN(num_bytes, root->sectorsize);
-again:
+
spin_lock(&BTRFS_I(inode)->accounting_lock);
nr_extents = atomic_read(&BTRFS_I(inode)->outstanding_extents) + 1;
if (nr_extents > BTRFS_I(inode)->reserved_extents) {
nr_extents = 0;
to_reserve = 0;
}
+ spin_unlock(&BTRFS_I(inode)->accounting_lock);
to_reserve += calc_csum_metadata_size(inode, num_bytes);
- ret = reserve_metadata_bytes(block_rsv, to_reserve);
- if (ret) {
- spin_unlock(&BTRFS_I(inode)->accounting_lock);
- ret = should_retry_reserve(NULL, root, block_rsv, to_reserve,
- &retries);
- if (ret > 0)
- goto again;
+ ret = reserve_metadata_bytes(NULL, root, block_rsv, to_reserve, 1);
+ if (ret)
return ret;
- }
+ spin_lock(&BTRFS_I(inode)->accounting_lock);
BTRFS_I(inode)->reserved_extents += nr_extents;
atomic_inc(&BTRFS_I(inode)->outstanding_extents);
spin_unlock(&BTRFS_I(inode)->accounting_lock);
block_rsv_add_bytes(block_rsv, to_reserve, 1);
if (block_rsv->size > 512 * 1024 * 1024)
- shrink_delalloc(NULL, root, to_reserve);
+ shrink_delalloc(NULL, root, to_reserve, 0);
return 0;
}
struct btrfs_root *root,
u64 bytenr, u64 num_bytes, int alloc)
{
- struct btrfs_block_group_cache *cache;
+ struct btrfs_block_group_cache *cache = NULL;
struct btrfs_fs_info *info = root->fs_info;
- int factor;
u64 total = num_bytes;
u64 old_val;
u64 byte_in_group;
+ int factor;
/* block accounting for super block */
spin_lock(&info->delalloc_lock);
factor = 2;
else
factor = 1;
+ /*
+ * If this block group has free space cache written out, we
+ * need to make sure to load it if we are removing space. This
+ * is because we need the unpinning stage to actually add the
+ * space back to the block group, otherwise we will leak space.
+ */
+ if (!alloc && cache->cached == BTRFS_CACHE_NO)
+ cache_block_group(cache, trans, 1);
+
byte_in_group = bytenr - cache->key.objectid;
WARN_ON(byte_in_group > cache->key.offset);
spin_lock(&cache->space_info->lock);
spin_lock(&cache->lock);
+
+ if (btrfs_super_cache_generation(&info->super_copy) != 0 &&
+ cache->disk_cache_state < BTRFS_DC_CLEAR)
+ cache->disk_cache_state = BTRFS_DC_CLEAR;
+
cache->dirty = 1;
old_val = btrfs_block_group_used(&cache->item);
num_bytes = min(total, cache->key.offset - byte_in_group);
bool found_uncached_bg = false;
bool failed_cluster_refill = false;
bool failed_alloc = false;
+ bool use_cluster = true;
u64 ideal_cache_percent = 0;
u64 ideal_cache_offset = 0;
return -ENOSPC;
}
+ /*
+ * If the space info is for both data and metadata it means we have a
+ * small filesystem and we can't use the clustering stuff.
+ */
+ if (btrfs_mixed_space_info(space_info))
+ use_cluster = false;
+
if (orig_root->ref_cows || empty_size)
allowed_chunk_alloc = 1;
- if (data & BTRFS_BLOCK_GROUP_METADATA) {
+ if (data & BTRFS_BLOCK_GROUP_METADATA && use_cluster) {
last_ptr = &root->fs_info->meta_alloc_cluster;
if (!btrfs_test_opt(root, SSD))
empty_cluster = 64 * 1024;
}
- if ((data & BTRFS_BLOCK_GROUP_DATA) && btrfs_test_opt(root, SSD)) {
+ if ((data & BTRFS_BLOCK_GROUP_DATA) && use_cluster &&
+ btrfs_test_opt(root, SSD)) {
last_ptr = &root->fs_info->data_alloc_cluster;
}
if (unlikely(block_group->cached == BTRFS_CACHE_NO)) {
u64 free_percent;
+ ret = cache_block_group(block_group, trans, 1);
+ if (block_group->cached == BTRFS_CACHE_FINISHED)
+ goto have_block_group;
+
free_percent = btrfs_block_group_used(&block_group->item);
free_percent *= 100;
free_percent = div64_u64(free_percent,
if (loop > LOOP_CACHING_NOWAIT ||
(loop > LOOP_FIND_IDEAL &&
atomic_read(&space_info->caching_threads) < 2)) {
- ret = cache_block_group(block_group);
+ ret = cache_block_group(block_group, trans, 0);
BUG_ON(ret);
}
found_uncached_bg = true;
u64 num_bytes = ins->offset;
block_group = btrfs_lookup_block_group(root->fs_info, ins->objectid);
- cache_block_group(block_group);
+ cache_block_group(block_group, trans, 0);
caching_ctl = get_caching_control(block_group);
if (!caching_ctl) {
block_rsv = get_block_rsv(trans, root);
if (block_rsv->size == 0) {
- ret = reserve_metadata_bytes(block_rsv, blocksize);
+ ret = reserve_metadata_bytes(trans, root, block_rsv,
+ blocksize, 0);
if (ret)
return ERR_PTR(ret);
return block_rsv;
if (!ret)
return block_rsv;
- WARN_ON(1);
- printk(KERN_INFO"block_rsv size %llu reserved %llu freed %llu %llu\n",
- block_rsv->size, block_rsv->reserved,
- block_rsv->freed[0], block_rsv->freed[1]);
-
return ERR_PTR(-ENOSPC);
}
u64 generation;
u64 refs;
u64 flags;
- u64 last = 0;
u32 nritems;
u32 blocksize;
struct btrfs_key key;
generation);
if (ret)
break;
- last = bytenr + blocksize;
nread++;
}
wc->reada_slot = slot;
return ret;
}
+void btrfs_put_block_group_cache(struct btrfs_fs_info *info)
+{
+ struct btrfs_block_group_cache *block_group;
+ u64 last = 0;
+
+ while (1) {
+ struct inode *inode;
+
+ block_group = btrfs_lookup_first_block_group(info, last);
+ while (block_group) {
+ spin_lock(&block_group->lock);
+ if (block_group->iref)
+ break;
+ spin_unlock(&block_group->lock);
+ block_group = next_block_group(info->tree_root,
+ block_group);
+ }
+ if (!block_group) {
+ if (last == 0)
+ break;
+ last = 0;
+ continue;
+ }
+
+ inode = block_group->inode;
+ block_group->iref = 0;
+ block_group->inode = NULL;
+ spin_unlock(&block_group->lock);
+ iput(inode);
+ last = block_group->key.objectid + block_group->key.offset;
+ btrfs_put_block_group(block_group);
+ }
+}
+
int btrfs_free_block_groups(struct btrfs_fs_info *info)
{
struct btrfs_block_group_cache *block_group;
struct btrfs_key key;
struct btrfs_key found_key;
struct extent_buffer *leaf;
+ int need_clear = 0;
+ u64 cache_gen;
root = info->extent_root;
key.objectid = 0;
if (!path)
return -ENOMEM;
+ cache_gen = btrfs_super_cache_generation(&root->fs_info->super_copy);
+ if (cache_gen != 0 &&
+ btrfs_super_generation(&root->fs_info->super_copy) != cache_gen)
+ need_clear = 1;
+ if (btrfs_test_opt(root, CLEAR_CACHE))
+ need_clear = 1;
+ if (!btrfs_test_opt(root, SPACE_CACHE) && cache_gen)
+ printk(KERN_INFO "btrfs: disk space caching is enabled\n");
+
while (1) {
ret = find_first_block_group(root, path, &key);
if (ret > 0)
INIT_LIST_HEAD(&cache->list);
INIT_LIST_HEAD(&cache->cluster_list);
+ if (need_clear)
+ cache->disk_cache_state = BTRFS_DC_CLEAR;
+
/*
* we only want to have 32k of ram per block group for keeping
* track of free space, and if we pass 1/2 of that we want to
cache->key.offset = size;
cache->key.type = BTRFS_BLOCK_GROUP_ITEM_KEY;
cache->sectorsize = root->sectorsize;
+ cache->fs_info = root->fs_info;
/*
* we only want to have 32k of ram per block group for keeping track
struct btrfs_path *path;
struct btrfs_block_group_cache *block_group;
struct btrfs_free_cluster *cluster;
+ struct btrfs_root *tree_root = root->fs_info->tree_root;
struct btrfs_key key;
+ struct inode *inode;
int ret;
+ int factor;
root = root->fs_info->extent_root;
BUG_ON(!block_group->ro);
memcpy(&key, &block_group->key, sizeof(key));
+ if (block_group->flags & (BTRFS_BLOCK_GROUP_DUP |
+ BTRFS_BLOCK_GROUP_RAID1 |
+ BTRFS_BLOCK_GROUP_RAID10))
+ factor = 2;
+ else
+ factor = 1;
/* make sure this block group isn't part of an allocation cluster */
cluster = &root->fs_info->data_alloc_cluster;
path = btrfs_alloc_path();
BUG_ON(!path);
+ inode = lookup_free_space_inode(root, block_group, path);
+ if (!IS_ERR(inode)) {
+ btrfs_orphan_add(trans, inode);
+ clear_nlink(inode);
+ /* One for the block groups ref */
+ spin_lock(&block_group->lock);
+ if (block_group->iref) {
+ block_group->iref = 0;
+ block_group->inode = NULL;
+ spin_unlock(&block_group->lock);
+ iput(inode);
+ } else {
+ spin_unlock(&block_group->lock);
+ }
+ /* One for our lookup ref */
+ iput(inode);
+ }
+
+ key.objectid = BTRFS_FREE_SPACE_OBJECTID;
+ key.offset = block_group->key.objectid;
+ key.type = 0;
+
+ ret = btrfs_search_slot(trans, tree_root, &key, path, -1, 1);
+ if (ret < 0)
+ goto out;
+ if (ret > 0)
+ btrfs_release_path(tree_root, path);
+ if (ret == 0) {
+ ret = btrfs_del_item(trans, tree_root, path);
+ if (ret)
+ goto out;
+ btrfs_release_path(tree_root, path);
+ }
+
spin_lock(&root->fs_info->block_group_cache_lock);
rb_erase(&block_group->cache_node,
&root->fs_info->block_group_cache_tree);
spin_lock(&block_group->space_info->lock);
block_group->space_info->total_bytes -= block_group->key.offset;
block_group->space_info->bytes_readonly -= block_group->key.offset;
+ block_group->space_info->disk_total -= block_group->key.offset * factor;
spin_unlock(&block_group->space_info->lock);
+ memcpy(&key, &block_group->key, sizeof(key));
+
btrfs_clear_space_info_full(root->fs_info);
btrfs_put_block_group(block_group);
struct address_space *mapping, gfp_t mask)
{
tree->state = RB_ROOT;
- tree->buffer = RB_ROOT;
+ INIT_RADIX_TREE(&tree->buffer, GFP_ATOMIC);
tree->ops = NULL;
tree->dirty_bytes = 0;
spin_lock_init(&tree->lock);
return ret;
}
-static struct extent_buffer *buffer_tree_insert(struct extent_io_tree *tree,
- u64 offset, struct rb_node *node)
-{
- struct rb_root *root = &tree->buffer;
- struct rb_node **p = &root->rb_node;
- struct rb_node *parent = NULL;
- struct extent_buffer *eb;
-
- while (*p) {
- parent = *p;
- eb = rb_entry(parent, struct extent_buffer, rb_node);
-
- if (offset < eb->start)
- p = &(*p)->rb_left;
- else if (offset > eb->start)
- p = &(*p)->rb_right;
- else
- return eb;
- }
-
- rb_link_node(node, parent, p);
- rb_insert_color(node, root);
- return NULL;
-}
-
-static struct extent_buffer *buffer_search(struct extent_io_tree *tree,
- u64 offset)
-{
- struct rb_root *root = &tree->buffer;
- struct rb_node *n = root->rb_node;
- struct extent_buffer *eb;
-
- while (n) {
- eb = rb_entry(n, struct extent_buffer, rb_node);
- if (offset < eb->start)
- n = n->rb_left;
- else if (offset > eb->start)
- n = n->rb_right;
- else
- return eb;
- }
- return NULL;
-}
-
static void merge_cb(struct extent_io_tree *tree, struct extent_state *new,
struct extent_state *other)
{
struct page *page = bvec->bv_page;
struct extent_io_tree *tree = bio->bi_private;
u64 start;
- u64 end;
start = ((u64)page->index << PAGE_CACHE_SHIFT) + bvec->bv_offset;
- end = start + bvec->bv_len - 1;
bio->bi_private = NULL;
u64 last_byte = i_size_read(inode);
u64 block_start;
u64 iosize;
- u64 unlock_start;
sector_t sector;
struct extent_state *cached_state = NULL;
struct extent_map *em;
if (tree->ops && tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, start,
page_end, NULL, 1);
- unlock_start = page_end + 1;
goto done;
}
if (tree->ops && tree->ops->writepage_end_io_hook)
tree->ops->writepage_end_io_hook(page, cur,
page_end, NULL, 1);
- unlock_start = page_end + 1;
break;
}
em = epd->get_extent(inode, page, pg_offset, cur,
cur += iosize;
pg_offset += iosize;
- unlock_start = cur;
continue;
}
/* leave this out until we have a page_mkwrite call */
pgoff_t index;
pgoff_t end; /* Inclusive */
int scanned = 0;
- int range_whole = 0;
pagevec_init(&pvec, 0);
if (wbc->range_cyclic) {
} else {
index = wbc->range_start >> PAGE_CACHE_SHIFT;
end = wbc->range_end >> PAGE_CACHE_SHIFT;
- if (wbc->range_start == 0 && wbc->range_end == LLONG_MAX)
- range_whole = 1;
scanned = 1;
}
retry:
NULL, 1,
end_bio_extent_preparewrite, 0,
0, 0);
+ if (ret && !err)
+ err = ret;
iocount++;
block_start = block_start + iosize;
} else {
kmem_cache_free(extent_buffer_cache, eb);
}
+/*
+ * Helper for releasing extent buffer page.
+ */
+static void btrfs_release_extent_buffer_page(struct extent_buffer *eb,
+ unsigned long start_idx)
+{
+ unsigned long index;
+ struct page *page;
+
+ if (!eb->first_page)
+ return;
+
+ index = num_extent_pages(eb->start, eb->len);
+ if (start_idx >= index)
+ return;
+
+ do {
+ index--;
+ page = extent_buffer_page(eb, index);
+ if (page)
+ page_cache_release(page);
+ } while (index != start_idx);
+}
+
+/*
+ * Helper for releasing the extent buffer.
+ */
+static inline void btrfs_release_extent_buffer(struct extent_buffer *eb)
+{
+ btrfs_release_extent_buffer_page(eb, 0);
+ __free_extent_buffer(eb);
+}
+
struct extent_buffer *alloc_extent_buffer(struct extent_io_tree *tree,
u64 start, unsigned long len,
struct page *page0,
struct page *p;
struct address_space *mapping = tree->mapping;
int uptodate = 1;
+ int ret;
- spin_lock(&tree->buffer_lock);
- eb = buffer_search(tree, start);
- if (eb) {
- atomic_inc(&eb->refs);
- spin_unlock(&tree->buffer_lock);
+ rcu_read_lock();
+ eb = radix_tree_lookup(&tree->buffer, start >> PAGE_CACHE_SHIFT);
+ if (eb && atomic_inc_not_zero(&eb->refs)) {
+ rcu_read_unlock();
mark_page_accessed(eb->first_page);
return eb;
}
- spin_unlock(&tree->buffer_lock);
+ rcu_read_unlock();
eb = __alloc_extent_buffer(tree, start, len, mask);
if (!eb)
if (uptodate)
set_bit(EXTENT_BUFFER_UPTODATE, &eb->bflags);
+ ret = radix_tree_preload(GFP_NOFS & ~__GFP_HIGHMEM);
+ if (ret)
+ goto free_eb;
+
spin_lock(&tree->buffer_lock);
- exists = buffer_tree_insert(tree, start, &eb->rb_node);
- if (exists) {
+ ret = radix_tree_insert(&tree->buffer, start >> PAGE_CACHE_SHIFT, eb);
+ if (ret == -EEXIST) {
+ exists = radix_tree_lookup(&tree->buffer,
+ start >> PAGE_CACHE_SHIFT);
/* add one reference for the caller */
atomic_inc(&exists->refs);
spin_unlock(&tree->buffer_lock);
+ radix_tree_preload_end();
goto free_eb;
}
/* add one reference for the tree */
atomic_inc(&eb->refs);
spin_unlock(&tree->buffer_lock);
+ radix_tree_preload_end();
return eb;
free_eb:
if (!atomic_dec_and_test(&eb->refs))
return exists;
- for (index = 1; index < i; index++)
- page_cache_release(extent_buffer_page(eb, index));
- page_cache_release(extent_buffer_page(eb, 0));
- __free_extent_buffer(eb);
+ btrfs_release_extent_buffer(eb);
return exists;
}
{
struct extent_buffer *eb;
- spin_lock(&tree->buffer_lock);
- eb = buffer_search(tree, start);
- if (eb)
- atomic_inc(&eb->refs);
- spin_unlock(&tree->buffer_lock);
-
- if (eb)
+ rcu_read_lock();
+ eb = radix_tree_lookup(&tree->buffer, start >> PAGE_CACHE_SHIFT);
+ if (eb && atomic_inc_not_zero(&eb->refs)) {
+ rcu_read_unlock();
mark_page_accessed(eb->first_page);
+ return eb;
+ }
+ rcu_read_unlock();
- return eb;
+ return NULL;
}
void free_extent_buffer(struct extent_buffer *eb)
}
}
+static inline void btrfs_release_extent_buffer_rcu(struct rcu_head *head)
+{
+ struct extent_buffer *eb =
+ container_of(head, struct extent_buffer, rcu_head);
+
+ btrfs_release_extent_buffer(eb);
+}
+
int try_release_extent_buffer(struct extent_io_tree *tree, struct page *page)
{
u64 start = page_offset(page);
struct extent_buffer *eb;
int ret = 1;
- unsigned long i;
- unsigned long num_pages;
spin_lock(&tree->buffer_lock);
- eb = buffer_search(tree, start);
+ eb = radix_tree_lookup(&tree->buffer, start >> PAGE_CACHE_SHIFT);
if (!eb)
goto out;
- if (atomic_read(&eb->refs) > 1) {
+ if (test_bit(EXTENT_BUFFER_DIRTY, &eb->bflags)) {
ret = 0;
goto out;
}
- if (test_bit(EXTENT_BUFFER_DIRTY, &eb->bflags)) {
+
+ /*
+ * set @eb->refs to 0 if it is already 1, and then release the @eb.
+ * Or go back.
+ */
+ if (atomic_cmpxchg(&eb->refs, 1, 0) != 1) {
ret = 0;
goto out;
}
- /* at this point we can safely release the extent buffer */
- num_pages = num_extent_pages(eb->start, eb->len);
- for (i = 0; i < num_pages; i++)
- page_cache_release(extent_buffer_page(eb, i));
- rb_erase(&eb->rb_node, &tree->buffer);
- __free_extent_buffer(eb);
+
+ radix_tree_delete(&tree->buffer, start >> PAGE_CACHE_SHIFT);
out:
spin_unlock(&tree->buffer_lock);
+
+ /* at this point we can safely release the extent buffer */
+ if (atomic_read(&eb->refs) == 0)
+ call_rcu(&eb->rcu_head, btrfs_release_extent_buffer_rcu);
return ret;
}
struct extent_io_tree {
struct rb_root state;
- struct rb_root buffer;
+ struct radix_tree_root buffer;
struct address_space *mapping;
u64 dirty_bytes;
spinlock_t lock;
unsigned long bflags;
atomic_t refs;
struct list_head leak_list;
- struct rb_node rb_node;
+ struct rcu_head rcu_head;
/* the spinlock is used to protect most operations */
spinlock_t lock;
goto out;
}
if (IS_ERR(rb_node)) {
- em = ERR_PTR(PTR_ERR(rb_node));
+ em = ERR_CAST(rb_node);
goto out;
}
em = rb_entry(rb_node, struct extent_map, rb_node);
goto out;
}
if (IS_ERR(rb_node)) {
- em = ERR_PTR(PTR_ERR(rb_node));
+ em = ERR_CAST(rb_node);
goto out;
}
em = rb_entry(rb_node, struct extent_map, rb_node);
#include "ctree.h"
#include "free-space-cache.h"
#include "transaction.h"
+#include "disk-io.h"
#define BITS_PER_BITMAP (PAGE_CACHE_SIZE * 8)
#define MAX_CACHE_BYTES_PER_GIG (32 * 1024)
+static void recalculate_thresholds(struct btrfs_block_group_cache
+ *block_group);
+static int link_free_space(struct btrfs_block_group_cache *block_group,
+ struct btrfs_free_space *info);
+
+struct inode *lookup_free_space_inode(struct btrfs_root *root,
+ struct btrfs_block_group_cache
+ *block_group, struct btrfs_path *path)
+{
+ struct btrfs_key key;
+ struct btrfs_key location;
+ struct btrfs_disk_key disk_key;
+ struct btrfs_free_space_header *header;
+ struct extent_buffer *leaf;
+ struct inode *inode = NULL;
+ int ret;
+
+ spin_lock(&block_group->lock);
+ if (block_group->inode)
+ inode = igrab(block_group->inode);
+ spin_unlock(&block_group->lock);
+ if (inode)
+ return inode;
+
+ key.objectid = BTRFS_FREE_SPACE_OBJECTID;
+ key.offset = block_group->key.objectid;
+ key.type = 0;
+
+ ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
+ if (ret < 0)
+ return ERR_PTR(ret);
+ if (ret > 0) {
+ btrfs_release_path(root, path);
+ return ERR_PTR(-ENOENT);
+ }
+
+ leaf = path->nodes[0];
+ header = btrfs_item_ptr(leaf, path->slots[0],
+ struct btrfs_free_space_header);
+ btrfs_free_space_key(leaf, header, &disk_key);
+ btrfs_disk_key_to_cpu(&location, &disk_key);
+ btrfs_release_path(root, path);
+
+ inode = btrfs_iget(root->fs_info->sb, &location, root, NULL);
+ if (!inode)
+ return ERR_PTR(-ENOENT);
+ if (IS_ERR(inode))
+ return inode;
+ if (is_bad_inode(inode)) {
+ iput(inode);
+ return ERR_PTR(-ENOENT);
+ }
+
+ spin_lock(&block_group->lock);
+ if (!root->fs_info->closing) {
+ block_group->inode = igrab(inode);
+ block_group->iref = 1;
+ }
+ spin_unlock(&block_group->lock);
+
+ return inode;
+}
+
+int create_free_space_inode(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_block_group_cache *block_group,
+ struct btrfs_path *path)
+{
+ struct btrfs_key key;
+ struct btrfs_disk_key disk_key;
+ struct btrfs_free_space_header *header;
+ struct btrfs_inode_item *inode_item;
+ struct extent_buffer *leaf;
+ u64 objectid;
+ int ret;
+
+ ret = btrfs_find_free_objectid(trans, root, 0, &objectid);
+ if (ret < 0)
+ return ret;
+
+ ret = btrfs_insert_empty_inode(trans, root, path, objectid);
+ if (ret)
+ return ret;
+
+ leaf = path->nodes[0];
+ inode_item = btrfs_item_ptr(leaf, path->slots[0],
+ struct btrfs_inode_item);
+ btrfs_item_key(leaf, &disk_key, path->slots[0]);
+ memset_extent_buffer(leaf, 0, (unsigned long)inode_item,
+ sizeof(*inode_item));
+ btrfs_set_inode_generation(leaf, inode_item, trans->transid);
+ btrfs_set_inode_size(leaf, inode_item, 0);
+ btrfs_set_inode_nbytes(leaf, inode_item, 0);
+ btrfs_set_inode_uid(leaf, inode_item, 0);
+ btrfs_set_inode_gid(leaf, inode_item, 0);
+ btrfs_set_inode_mode(leaf, inode_item, S_IFREG | 0600);
+ btrfs_set_inode_flags(leaf, inode_item, BTRFS_INODE_NOCOMPRESS |
+ BTRFS_INODE_PREALLOC | BTRFS_INODE_NODATASUM);
+ btrfs_set_inode_nlink(leaf, inode_item, 1);
+ btrfs_set_inode_transid(leaf, inode_item, trans->transid);
+ btrfs_set_inode_block_group(leaf, inode_item,
+ block_group->key.objectid);
+ btrfs_mark_buffer_dirty(leaf);
+ btrfs_release_path(root, path);
+
+ key.objectid = BTRFS_FREE_SPACE_OBJECTID;
+ key.offset = block_group->key.objectid;
+ key.type = 0;
+
+ ret = btrfs_insert_empty_item(trans, root, path, &key,
+ sizeof(struct btrfs_free_space_header));
+ if (ret < 0) {
+ btrfs_release_path(root, path);
+ return ret;
+ }
+ leaf = path->nodes[0];
+ header = btrfs_item_ptr(leaf, path->slots[0],
+ struct btrfs_free_space_header);
+ memset_extent_buffer(leaf, 0, (unsigned long)header, sizeof(*header));
+ btrfs_set_free_space_key(leaf, header, &disk_key);
+ btrfs_mark_buffer_dirty(leaf);
+ btrfs_release_path(root, path);
+
+ return 0;
+}
+
+int btrfs_truncate_free_space_cache(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_path *path,
+ struct inode *inode)
+{
+ loff_t oldsize;
+ int ret = 0;
+
+ trans->block_rsv = root->orphan_block_rsv;
+ ret = btrfs_block_rsv_check(trans, root,
+ root->orphan_block_rsv,
+ 0, 5);
+ if (ret)
+ return ret;
+
+ oldsize = i_size_read(inode);
+ btrfs_i_size_write(inode, 0);
+ truncate_pagecache(inode, oldsize, 0);
+
+ /*
+ * We don't need an orphan item because truncating the free space cache
+ * will never be split across transactions.
+ */
+ ret = btrfs_truncate_inode_items(trans, root, inode,
+ 0, BTRFS_EXTENT_DATA_KEY);
+ if (ret) {
+ WARN_ON(1);
+ return ret;
+ }
+
+ return btrfs_update_inode(trans, root, inode);
+}
+
+static int readahead_cache(struct inode *inode)
+{
+ struct file_ra_state *ra;
+ unsigned long last_index;
+
+ ra = kzalloc(sizeof(*ra), GFP_NOFS);
+ if (!ra)
+ return -ENOMEM;
+
+ file_ra_state_init(ra, inode->i_mapping);
+ last_index = (i_size_read(inode) - 1) >> PAGE_CACHE_SHIFT;
+
+ page_cache_sync_readahead(inode->i_mapping, ra, NULL, 0, last_index);
+
+ kfree(ra);
+
+ return 0;
+}
+
+int load_free_space_cache(struct btrfs_fs_info *fs_info,
+ struct btrfs_block_group_cache *block_group)
+{
+ struct btrfs_root *root = fs_info->tree_root;
+ struct inode *inode;
+ struct btrfs_free_space_header *header;
+ struct extent_buffer *leaf;
+ struct page *page;
+ struct btrfs_path *path;
+ u32 *checksums = NULL, *crc;
+ char *disk_crcs = NULL;
+ struct btrfs_key key;
+ struct list_head bitmaps;
+ u64 num_entries;
+ u64 num_bitmaps;
+ u64 generation;
+ u32 cur_crc = ~(u32)0;
+ pgoff_t index = 0;
+ unsigned long first_page_offset;
+ int num_checksums;
+ int ret = 0;
+
+ /*
+ * If we're unmounting then just return, since this does a search on the
+ * normal root and not the commit root and we could deadlock.
+ */
+ smp_mb();
+ if (fs_info->closing)
+ return 0;
+
+ /*
+ * If this block group has been marked to be cleared for one reason or
+ * another then we can't trust the on disk cache, so just return.
+ */
+ spin_lock(&block_group->lock);
+ if (block_group->disk_cache_state != BTRFS_DC_WRITTEN) {
+ spin_unlock(&block_group->lock);
+ return 0;
+ }
+ spin_unlock(&block_group->lock);
+
+ INIT_LIST_HEAD(&bitmaps);
+
+ path = btrfs_alloc_path();
+ if (!path)
+ return 0;
+
+ inode = lookup_free_space_inode(root, block_group, path);
+ if (IS_ERR(inode)) {
+ btrfs_free_path(path);
+ return 0;
+ }
+
+ /* Nothing in the space cache, goodbye */
+ if (!i_size_read(inode)) {
+ btrfs_free_path(path);
+ goto out;
+ }
+
+ key.objectid = BTRFS_FREE_SPACE_OBJECTID;
+ key.offset = block_group->key.objectid;
+ key.type = 0;
+
+ ret = btrfs_search_slot(NULL, root, &key, path, 0, 0);
+ if (ret) {
+ btrfs_free_path(path);
+ goto out;
+ }
+
+ leaf = path->nodes[0];
+ header = btrfs_item_ptr(leaf, path->slots[0],
+ struct btrfs_free_space_header);
+ num_entries = btrfs_free_space_entries(leaf, header);
+ num_bitmaps = btrfs_free_space_bitmaps(leaf, header);
+ generation = btrfs_free_space_generation(leaf, header);
+ btrfs_free_path(path);
+
+ if (BTRFS_I(inode)->generation != generation) {
+ printk(KERN_ERR "btrfs: free space inode generation (%llu) did"
+ " not match free space cache generation (%llu) for "
+ "block group %llu\n",
+ (unsigned long long)BTRFS_I(inode)->generation,
+ (unsigned long long)generation,
+ (unsigned long long)block_group->key.objectid);
+ goto out;
+ }
+
+ if (!num_entries)
+ goto out;
+
+ /* Setup everything for doing checksumming */
+ num_checksums = i_size_read(inode) / PAGE_CACHE_SIZE;
+ checksums = crc = kzalloc(sizeof(u32) * num_checksums, GFP_NOFS);
+ if (!checksums)
+ goto out;
+ first_page_offset = (sizeof(u32) * num_checksums) + sizeof(u64);
+ disk_crcs = kzalloc(first_page_offset, GFP_NOFS);
+ if (!disk_crcs)
+ goto out;
+
+ ret = readahead_cache(inode);
+ if (ret) {
+ ret = 0;
+ goto out;
+ }
+
+ while (1) {
+ struct btrfs_free_space_entry *entry;
+ struct btrfs_free_space *e;
+ void *addr;
+ unsigned long offset = 0;
+ unsigned long start_offset = 0;
+ int need_loop = 0;
+
+ if (!num_entries && !num_bitmaps)
+ break;
+
+ if (index == 0) {
+ start_offset = first_page_offset;
+ offset = start_offset;
+ }
+
+ page = grab_cache_page(inode->i_mapping, index);
+ if (!page) {
+ ret = 0;
+ goto free_cache;
+ }
+
+ if (!PageUptodate(page)) {
+ btrfs_readpage(NULL, page);
+ lock_page(page);
+ if (!PageUptodate(page)) {
+ unlock_page(page);
+ page_cache_release(page);
+ printk(KERN_ERR "btrfs: error reading free "
+ "space cache: %llu\n",
+ (unsigned long long)
+ block_group->key.objectid);
+ goto free_cache;
+ }
+ }
+ addr = kmap(page);
+
+ if (index == 0) {
+ u64 *gen;
+
+ memcpy(disk_crcs, addr, first_page_offset);
+ gen = addr + (sizeof(u32) * num_checksums);
+ if (*gen != BTRFS_I(inode)->generation) {
+ printk(KERN_ERR "btrfs: space cache generation"
+ " (%llu) does not match inode (%llu) "
+ "for block group %llu\n",
+ (unsigned long long)*gen,
+ (unsigned long long)
+ BTRFS_I(inode)->generation,
+ (unsigned long long)
+ block_group->key.objectid);
+ kunmap(page);
+ unlock_page(page);
+ page_cache_release(page);
+ goto free_cache;
+ }
+ crc = (u32 *)disk_crcs;
+ }
+ entry = addr + start_offset;
+
+ /* First lets check our crc before we do anything fun */
+ cur_crc = ~(u32)0;
+ cur_crc = btrfs_csum_data(root, addr + start_offset, cur_crc,
+ PAGE_CACHE_SIZE - start_offset);
+ btrfs_csum_final(cur_crc, (char *)&cur_crc);
+ if (cur_crc != *crc) {
+ printk(KERN_ERR "btrfs: crc mismatch for page %lu in "
+ "block group %llu\n", index,
+ (unsigned long long)block_group->key.objectid);
+ kunmap(page);
+ unlock_page(page);
+ page_cache_release(page);
+ goto free_cache;
+ }
+ crc++;
+
+ while (1) {
+ if (!num_entries)
+ break;
+
+ need_loop = 1;
+ e = kzalloc(sizeof(struct btrfs_free_space), GFP_NOFS);
+ if (!e) {
+ kunmap(page);
+ unlock_page(page);
+ page_cache_release(page);
+ goto free_cache;
+ }
+
+ e->offset = le64_to_cpu(entry->offset);
+ e->bytes = le64_to_cpu(entry->bytes);
+ if (!e->bytes) {
+ kunmap(page);
+ kfree(e);
+ unlock_page(page);
+ page_cache_release(page);
+ goto free_cache;
+ }
+
+ if (entry->type == BTRFS_FREE_SPACE_EXTENT) {
+ spin_lock(&block_group->tree_lock);
+ ret = link_free_space(block_group, e);
+ spin_unlock(&block_group->tree_lock);
+ BUG_ON(ret);
+ } else {
+ e->bitmap = kzalloc(PAGE_CACHE_SIZE, GFP_NOFS);
+ if (!e->bitmap) {
+ kunmap(page);
+ kfree(e);
+ unlock_page(page);
+ page_cache_release(page);
+ goto free_cache;
+ }
+ spin_lock(&block_group->tree_lock);
+ ret = link_free_space(block_group, e);
+ block_group->total_bitmaps++;
+ recalculate_thresholds(block_group);
+ spin_unlock(&block_group->tree_lock);
+ list_add_tail(&e->list, &bitmaps);
+ }
+
+ num_entries--;
+ offset += sizeof(struct btrfs_free_space_entry);
+ if (offset + sizeof(struct btrfs_free_space_entry) >=
+ PAGE_CACHE_SIZE)
+ break;
+ entry++;
+ }
+
+ /*
+ * We read an entry out of this page, we need to move on to the
+ * next page.
+ */
+ if (need_loop) {
+ kunmap(page);
+ goto next;
+ }
+
+ /*
+ * We add the bitmaps at the end of the entries in order that
+ * the bitmap entries are added to the cache.
+ */
+ e = list_entry(bitmaps.next, struct btrfs_free_space, list);
+ list_del_init(&e->list);
+ memcpy(e->bitmap, addr, PAGE_CACHE_SIZE);
+ kunmap(page);
+ num_bitmaps--;
+next:
+ unlock_page(page);
+ page_cache_release(page);
+ index++;
+ }
+
+ ret = 1;
+out:
+ kfree(checksums);
+ kfree(disk_crcs);
+ iput(inode);
+ return ret;
+
+free_cache:
+ /* This cache is bogus, make sure it gets cleared */
+ spin_lock(&block_group->lock);
+ block_group->disk_cache_state = BTRFS_DC_CLEAR;
+ spin_unlock(&block_group->lock);
+ btrfs_remove_free_space_cache(block_group);
+ goto out;
+}
+
+int btrfs_write_out_cache(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_block_group_cache *block_group,
+ struct btrfs_path *path)
+{
+ struct btrfs_free_space_header *header;
+ struct extent_buffer *leaf;
+ struct inode *inode;
+ struct rb_node *node;
+ struct list_head *pos, *n;
+ struct page *page;
+ struct extent_state *cached_state = NULL;
+ struct list_head bitmap_list;
+ struct btrfs_key key;
+ u64 bytes = 0;
+ u32 *crc, *checksums;
+ pgoff_t index = 0, last_index = 0;
+ unsigned long first_page_offset;
+ int num_checksums;
+ int entries = 0;
+ int bitmaps = 0;
+ int ret = 0;
+
+ root = root->fs_info->tree_root;
+
+ INIT_LIST_HEAD(&bitmap_list);
+
+ spin_lock(&block_group->lock);
+ if (block_group->disk_cache_state < BTRFS_DC_SETUP) {
+ spin_unlock(&block_group->lock);
+ return 0;
+ }
+ spin_unlock(&block_group->lock);
+
+ inode = lookup_free_space_inode(root, block_group, path);
+ if (IS_ERR(inode))
+ return 0;
+
+ if (!i_size_read(inode)) {
+ iput(inode);
+ return 0;
+ }
+
+ last_index = (i_size_read(inode) - 1) >> PAGE_CACHE_SHIFT;
+ filemap_write_and_wait(inode->i_mapping);
+ btrfs_wait_ordered_range(inode, inode->i_size &
+ ~(root->sectorsize - 1), (u64)-1);
+
+ /* We need a checksum per page. */
+ num_checksums = i_size_read(inode) / PAGE_CACHE_SIZE;
+ crc = checksums = kzalloc(sizeof(u32) * num_checksums, GFP_NOFS);
+ if (!crc) {
+ iput(inode);
+ return 0;
+ }
+
+ /* Since the first page has all of our checksums and our generation we
+ * need to calculate the offset into the page that we can start writing
+ * our entries.
+ */
+ first_page_offset = (sizeof(u32) * num_checksums) + sizeof(u64);
+
+ node = rb_first(&block_group->free_space_offset);
+ if (!node)
+ goto out_free;
+
+ /*
+ * Lock all pages first so we can lock the extent safely.
+ *
+ * NOTE: Because we hold the ref the entire time we're going to write to
+ * the page find_get_page should never fail, so we don't do a check
+ * after find_get_page at this point. Just putting this here so people
+ * know and don't freak out.
+ */
+ while (index <= last_index) {
+ page = grab_cache_page(inode->i_mapping, index);
+ if (!page) {
+ pgoff_t i = 0;
+
+ while (i < index) {
+ page = find_get_page(inode->i_mapping, i);
+ unlock_page(page);
+ page_cache_release(page);
+ page_cache_release(page);
+ i++;
+ }
+ goto out_free;
+ }
+ index++;
+ }
+
+ index = 0;
+ lock_extent_bits(&BTRFS_I(inode)->io_tree, 0, i_size_read(inode) - 1,
+ 0, &cached_state, GFP_NOFS);
+
+ /* Write out the extent entries */
+ do {
+ struct btrfs_free_space_entry *entry;
+ void *addr;
+ unsigned long offset = 0;
+ unsigned long start_offset = 0;
+
+ if (index == 0) {
+ start_offset = first_page_offset;
+ offset = start_offset;
+ }
+
+ page = find_get_page(inode->i_mapping, index);
+
+ addr = kmap(page);
+ entry = addr + start_offset;
+
+ memset(addr, 0, PAGE_CACHE_SIZE);
+ while (1) {
+ struct btrfs_free_space *e;
+
+ e = rb_entry(node, struct btrfs_free_space, offset_index);
+ entries++;
+
+ entry->offset = cpu_to_le64(e->offset);
+ entry->bytes = cpu_to_le64(e->bytes);
+ if (e->bitmap) {
+ entry->type = BTRFS_FREE_SPACE_BITMAP;
+ list_add_tail(&e->list, &bitmap_list);
+ bitmaps++;
+ } else {
+ entry->type = BTRFS_FREE_SPACE_EXTENT;
+ }
+ node = rb_next(node);
+ if (!node)
+ break;
+ offset += sizeof(struct btrfs_free_space_entry);
+ if (offset + sizeof(struct btrfs_free_space_entry) >=
+ PAGE_CACHE_SIZE)
+ break;
+ entry++;
+ }
+ *crc = ~(u32)0;
+ *crc = btrfs_csum_data(root, addr + start_offset, *crc,
+ PAGE_CACHE_SIZE - start_offset);
+ kunmap(page);
+
+ btrfs_csum_final(*crc, (char *)crc);
+ crc++;
+
+ bytes += PAGE_CACHE_SIZE;
+
+ ClearPageChecked(page);
+ set_page_extent_mapped(page);
+ SetPageUptodate(page);
+ set_page_dirty(page);
+
+ /*
+ * We need to release our reference we got for grab_cache_page,
+ * except for the first page which will hold our checksums, we
+ * do that below.
+ */
+ if (index != 0) {
+ unlock_page(page);
+ page_cache_release(page);
+ }
+
+ page_cache_release(page);
+
+ index++;
+ } while (node);
+
+ /* Write out the bitmaps */
+ list_for_each_safe(pos, n, &bitmap_list) {
+ void *addr;
+ struct btrfs_free_space *entry =
+ list_entry(pos, struct btrfs_free_space, list);
+
+ page = find_get_page(inode->i_mapping, index);
+
+ addr = kmap(page);
+ memcpy(addr, entry->bitmap, PAGE_CACHE_SIZE);
+ *crc = ~(u32)0;
+ *crc = btrfs_csum_data(root, addr, *crc, PAGE_CACHE_SIZE);
+ kunmap(page);
+ btrfs_csum_final(*crc, (char *)crc);
+ crc++;
+ bytes += PAGE_CACHE_SIZE;
+
+ ClearPageChecked(page);
+ set_page_extent_mapped(page);
+ SetPageUptodate(page);
+ set_page_dirty(page);
+ unlock_page(page);
+ page_cache_release(page);
+ page_cache_release(page);
+ list_del_init(&entry->list);
+ index++;
+ }
+
+ /* Zero out the rest of the pages just to make sure */
+ while (index <= last_index) {
+ void *addr;
+
+ page = find_get_page(inode->i_mapping, index);
+
+ addr = kmap(page);
+ memset(addr, 0, PAGE_CACHE_SIZE);
+ kunmap(page);
+ ClearPageChecked(page);
+ set_page_extent_mapped(page);
+ SetPageUptodate(page);
+ set_page_dirty(page);
+ unlock_page(page);
+ page_cache_release(page);
+ page_cache_release(page);
+ bytes += PAGE_CACHE_SIZE;
+ index++;
+ }
+
+ btrfs_set_extent_delalloc(inode, 0, bytes - 1, &cached_state);
+
+ /* Write the checksums and trans id to the first page */
+ {
+ void *addr;
+ u64 *gen;
+
+ page = find_get_page(inode->i_mapping, 0);
+
+ addr = kmap(page);
+ memcpy(addr, checksums, sizeof(u32) * num_checksums);
+ gen = addr + (sizeof(u32) * num_checksums);
+ *gen = trans->transid;
+ kunmap(page);
+ ClearPageChecked(page);
+ set_page_extent_mapped(page);
+ SetPageUptodate(page);
+ set_page_dirty(page);
+ unlock_page(page);
+ page_cache_release(page);
+ page_cache_release(page);
+ }
+ BTRFS_I(inode)->generation = trans->transid;
+
+ unlock_extent_cached(&BTRFS_I(inode)->io_tree, 0,
+ i_size_read(inode) - 1, &cached_state, GFP_NOFS);
+
+ filemap_write_and_wait(inode->i_mapping);
+
+ key.objectid = BTRFS_FREE_SPACE_OBJECTID;
+ key.offset = block_group->key.objectid;
+ key.type = 0;
+
+ ret = btrfs_search_slot(trans, root, &key, path, 1, 1);
+ if (ret < 0) {
+ ret = 0;
+ clear_extent_bit(&BTRFS_I(inode)->io_tree, 0, bytes - 1,
+ EXTENT_DIRTY | EXTENT_DELALLOC |
+ EXTENT_DO_ACCOUNTING, 0, 0, NULL, GFP_NOFS);
+ goto out_free;
+ }
+ leaf = path->nodes[0];
+ if (ret > 0) {
+ struct btrfs_key found_key;
+ BUG_ON(!path->slots[0]);
+ path->slots[0]--;
+ btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
+ if (found_key.objectid != BTRFS_FREE_SPACE_OBJECTID ||
+ found_key.offset != block_group->key.objectid) {
+ ret = 0;
+ clear_extent_bit(&BTRFS_I(inode)->io_tree, 0, bytes - 1,
+ EXTENT_DIRTY | EXTENT_DELALLOC |
+ EXTENT_DO_ACCOUNTING, 0, 0, NULL,
+ GFP_NOFS);
+ btrfs_release_path(root, path);
+ goto out_free;
+ }
+ }
+ header = btrfs_item_ptr(leaf, path->slots[0],
+ struct btrfs_free_space_header);
+ btrfs_set_free_space_entries(leaf, header, entries);
+ btrfs_set_free_space_bitmaps(leaf, header, bitmaps);
+ btrfs_set_free_space_generation(leaf, header, trans->transid);
+ btrfs_mark_buffer_dirty(leaf);
+ btrfs_release_path(root, path);
+
+ ret = 1;
+
+out_free:
+ if (ret == 0) {
+ invalidate_inode_pages2_range(inode->i_mapping, 0, index);
+ spin_lock(&block_group->lock);
+ block_group->disk_cache_state = BTRFS_DC_ERROR;
+ spin_unlock(&block_group->lock);
+ BTRFS_I(inode)->generation = 0;
+ }
+ kfree(checksums);
+ btrfs_update_inode(trans, root, inode);
+ iput(inode);
+ return ret;
+}
+
static inline unsigned long offset_to_bit(u64 bitmap_start, u64 sectorsize,
u64 offset)
{
struct list_head list;
};
+struct inode *lookup_free_space_inode(struct btrfs_root *root,
+ struct btrfs_block_group_cache
+ *block_group, struct btrfs_path *path);
+int create_free_space_inode(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_block_group_cache *block_group,
+ struct btrfs_path *path);
+
+int btrfs_truncate_free_space_cache(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_path *path,
+ struct inode *inode);
+int load_free_space_cache(struct btrfs_fs_info *fs_info,
+ struct btrfs_block_group_cache *block_group);
+int btrfs_write_out_cache(struct btrfs_root *root,
+ struct btrfs_trans_handle *trans,
+ struct btrfs_block_group_cache *block_group,
+ struct btrfs_path *path);
int btrfs_add_free_space(struct btrfs_block_group_cache *block_group,
u64 bytenr, u64 size);
int btrfs_remove_free_space(struct btrfs_block_group_cache *block_group,
struct btrfs_root *root = BTRFS_I(inode)->root;
struct btrfs_trans_handle *trans;
u64 num_bytes;
- u64 orig_start;
- u64 disk_num_bytes;
u64 blocksize = root->sectorsize;
u64 actual_end;
u64 isize = i_size_read(inode);
int i;
int will_compress;
- orig_start = start;
-
actual_end = min_t(u64, isize, end + 1);
again:
will_compress = 0;
total_compressed = min(total_compressed, max_uncompressed);
num_bytes = (end - start + blocksize) & ~(blocksize - 1);
num_bytes = max(blocksize, num_bytes);
- disk_num_bytes = num_bytes;
total_in = 0;
ret = 0;
if (total_compressed >= total_in) {
will_compress = 0;
} else {
- disk_num_bytes = total_compressed;
num_bytes = total_in;
}
}
u64 disk_num_bytes;
u64 cur_alloc_size;
u64 blocksize = root->sectorsize;
- u64 actual_end;
- u64 isize = i_size_read(inode);
struct btrfs_key ins;
struct extent_map *em;
struct extent_map_tree *em_tree = &BTRFS_I(inode)->extent_tree;
int ret = 0;
+ BUG_ON(root == root->fs_info->tree_root);
trans = btrfs_join_transaction(root, 1);
BUG_ON(!trans);
btrfs_set_trans_block_group(trans, inode);
trans->block_rsv = &root->fs_info->delalloc_block_rsv;
- actual_end = min_t(u64, isize, end + 1);
-
num_bytes = (end - start + blocksize) & ~(blocksize - 1);
num_bytes = max(blocksize, num_bytes);
disk_num_bytes = num_bytes;
int type;
int nocow;
int check_prev = 1;
+ bool nolock = false;
path = btrfs_alloc_path();
BUG_ON(!path);
- trans = btrfs_join_transaction(root, 1);
+ if (root == root->fs_info->tree_root) {
+ nolock = true;
+ trans = btrfs_join_transaction_nolock(root, 1);
+ } else {
+ trans = btrfs_join_transaction(root, 1);
+ }
BUG_ON(!trans);
cow_start = (u64)-1;
BUG_ON(ret);
}
- ret = btrfs_end_transaction(trans, root);
- BUG_ON(ret);
+ if (nolock) {
+ ret = btrfs_end_transaction_nolock(trans, root);
+ BUG_ON(ret);
+ } else {
+ ret = btrfs_end_transaction(trans, root);
+ BUG_ON(ret);
+ }
btrfs_free_path(path);
return 0;
}
if (!(state->state & EXTENT_DELALLOC) && (*bits & EXTENT_DELALLOC)) {
struct btrfs_root *root = BTRFS_I(inode)->root;
u64 len = state->end + 1 - state->start;
+ int do_list = (root->root_key.objectid !=
+ BTRFS_ROOT_TREE_OBJECTID);
if (*bits & EXTENT_FIRST_DELALLOC)
*bits &= ~EXTENT_FIRST_DELALLOC;
spin_lock(&root->fs_info->delalloc_lock);
BTRFS_I(inode)->delalloc_bytes += len;
root->fs_info->delalloc_bytes += len;
- if (list_empty(&BTRFS_I(inode)->delalloc_inodes)) {
+ if (do_list && list_empty(&BTRFS_I(inode)->delalloc_inodes)) {
list_add_tail(&BTRFS_I(inode)->delalloc_inodes,
&root->fs_info->delalloc_inodes);
}
if ((state->state & EXTENT_DELALLOC) && (*bits & EXTENT_DELALLOC)) {
struct btrfs_root *root = BTRFS_I(inode)->root;
u64 len = state->end + 1 - state->start;
+ int do_list = (root->root_key.objectid !=
+ BTRFS_ROOT_TREE_OBJECTID);
if (*bits & EXTENT_FIRST_DELALLOC)
*bits &= ~EXTENT_FIRST_DELALLOC;
if (*bits & EXTENT_DO_ACCOUNTING)
btrfs_delalloc_release_metadata(inode, len);
- if (root->root_key.objectid != BTRFS_DATA_RELOC_TREE_OBJECTID)
+ if (root->root_key.objectid != BTRFS_DATA_RELOC_TREE_OBJECTID
+ && do_list)
btrfs_free_reserved_data_space(inode, len);
spin_lock(&root->fs_info->delalloc_lock);
root->fs_info->delalloc_bytes -= len;
BTRFS_I(inode)->delalloc_bytes -= len;
- if (BTRFS_I(inode)->delalloc_bytes == 0 &&
+ if (do_list && BTRFS_I(inode)->delalloc_bytes == 0 &&
!list_empty(&BTRFS_I(inode)->delalloc_inodes)) {
list_del_init(&BTRFS_I(inode)->delalloc_inodes);
}
if (map_length < length + size)
return 1;
- return 0;
+ return ret;
}
/*
skip_sum = BTRFS_I(inode)->flags & BTRFS_INODE_NODATASUM;
- ret = btrfs_bio_wq_end_io(root->fs_info, bio, 0);
+ if (root == root->fs_info->tree_root)
+ ret = btrfs_bio_wq_end_io(root->fs_info, bio, 2);
+ else
+ ret = btrfs_bio_wq_end_io(root->fs_info, bio, 0);
BUG_ON(ret);
if (!(rw & REQ_WRITE)) {
struct extent_state *cached_state = NULL;
int compressed = 0;
int ret;
+ bool nolock = false;
ret = btrfs_dec_test_ordered_pending(inode, &ordered_extent, start,
end - start + 1);
return 0;
BUG_ON(!ordered_extent);
+ nolock = (root == root->fs_info->tree_root);
+
if (test_bit(BTRFS_ORDERED_NOCOW, &ordered_extent->flags)) {
BUG_ON(!list_empty(&ordered_extent->list));
ret = btrfs_ordered_update_i_size(inode, 0, ordered_extent);
if (!ret) {
- trans = btrfs_join_transaction(root, 1);
+ if (nolock)
+ trans = btrfs_join_transaction_nolock(root, 1);
+ else
+ trans = btrfs_join_transaction(root, 1);
+ BUG_ON(!trans);
btrfs_set_trans_block_group(trans, inode);
trans->block_rsv = &root->fs_info->delalloc_block_rsv;
ret = btrfs_update_inode(trans, root, inode);
ordered_extent->file_offset + ordered_extent->len - 1,
0, &cached_state, GFP_NOFS);
- trans = btrfs_join_transaction(root, 1);
+ if (nolock)
+ trans = btrfs_join_transaction_nolock(root, 1);
+ else
+ trans = btrfs_join_transaction(root, 1);
btrfs_set_trans_block_group(trans, inode);
trans->block_rsv = &root->fs_info->delalloc_block_rsv;
ordered_extent->len);
BUG_ON(ret);
} else {
+ BUG_ON(root == root->fs_info->tree_root);
ret = insert_reserved_file_extent(trans, inode,
ordered_extent->file_offset,
ordered_extent->start,
ret = btrfs_update_inode(trans, root, inode);
BUG_ON(ret);
out:
- btrfs_delalloc_release_metadata(inode, ordered_extent->len);
- if (trans)
- btrfs_end_transaction(trans, root);
+ if (nolock) {
+ if (trans)
+ btrfs_end_transaction_nolock(trans, root);
+ } else {
+ btrfs_delalloc_release_metadata(inode, ordered_extent->len);
+ if (trans)
+ btrfs_end_transaction(trans, root);
+ }
+
/* once for us */
btrfs_put_ordered_extent(ordered_extent);
/* once for the tree */
{
struct btrfs_path *path;
struct extent_buffer *leaf;
- struct btrfs_item *item;
struct btrfs_key key, found_key;
struct btrfs_trans_handle *trans;
struct inode *inode;
/* pull out the item */
leaf = path->nodes[0];
- item = btrfs_item_nr(leaf, path->slots[0]);
btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
/* make sure the item matches what we want */
ret = btrfs_del_dir_entries_in_log(trans, root, name, name_len,
dir, index);
- BUG_ON(ret);
+ if (ret == -ENOENT)
+ ret = 0;
err:
btrfs_free_path(path);
if (ret)
{
struct extent_buffer *eb;
int level;
- int ret;
u64 refs = 1;
+ int uninitialized_var(ret);
for (level = 0; level < BTRFS_MAX_LEVEL; level++) {
if (!path->nodes[level])
if (refs > 1)
return 1;
}
- return 0;
+ return ret; /* XXX callers? */
}
/*
BUG_ON(new_size > 0 && min_type != BTRFS_EXTENT_DATA_KEY);
- if (root->ref_cows)
+ if (root->ref_cows || root == root->fs_info->tree_root)
btrfs_drop_extent_cache(inode, new_size & (~mask), (u64)-1, 0);
path = btrfs_alloc_path();
} else {
break;
}
- if (found_extent && root->ref_cows) {
+ if (found_extent && (root->ref_cows ||
+ root == root->fs_info->tree_root)) {
btrfs_set_path_blocking(path);
ret = btrfs_free_extent(trans, root, extent_start,
extent_num_bytes, 0,
int ret;
truncate_inode_pages(&inode->i_data, 0);
- if (inode->i_nlink && btrfs_root_refs(&root->root_item) != 0)
+ if (inode->i_nlink && (btrfs_root_refs(&root->root_item) != 0 ||
+ root == root->fs_info->tree_root))
goto no_delete;
if (is_bad_inode(inode)) {
}
spin_unlock(&root->inode_lock);
- if (empty && btrfs_root_refs(&root->root_item) == 0) {
+ /*
+ * Free space cache has inodes in the tree root, but the tree root has a
+ * root_refs of 0, so this could end up dropping the tree root as a
+ * snapshot, so we need the extra !root->fs_info->tree_root check to
+ * make sure we don't drop it.
+ */
+ if (empty && btrfs_root_refs(&root->root_item) == 0 &&
+ root != root->fs_info->tree_root) {
synchronize_srcu(&root->fs_info->subvol_srcu);
spin_lock(&root->inode_lock);
empty = RB_EMPTY_ROOT(&root->inode_tree);
struct btrfs_root *root = BTRFS_I(inode)->root;
struct btrfs_trans_handle *trans;
int ret = 0;
+ bool nolock = false;
if (BTRFS_I(inode)->dummy_inode)
return 0;
+ smp_mb();
+ nolock = (root->fs_info->closing && root == root->fs_info->tree_root);
+
if (wbc->sync_mode == WB_SYNC_ALL) {
- trans = btrfs_join_transaction(root, 1);
+ if (nolock)
+ trans = btrfs_join_transaction_nolock(root, 1);
+ else
+ trans = btrfs_join_transaction(root, 1);
btrfs_set_trans_block_group(trans, inode);
- ret = btrfs_commit_transaction(trans, root);
+ if (nolock)
+ ret = btrfs_end_transaction_nolock(trans, root);
+ else
+ ret = btrfs_commit_transaction(trans, root);
}
return ret;
}
struct btrfs_root *root = BTRFS_I(inode)->root;
struct btrfs_dio_private *dip;
struct bio_vec *bvec = bio->bi_io_vec;
- u64 start;
int skip_sum;
int write = rw & REQ_WRITE;
int ret = 0;
dip->inode = inode;
dip->logical_offset = file_offset;
- start = dip->logical_offset;
dip->bytes = 0;
do {
dip->bytes += bvec->bv_len;
spin_unlock(&root->fs_info->ordered_extent_lock);
}
+ if (root == root->fs_info->tree_root) {
+ struct btrfs_block_group_cache *block_group;
+
+ block_group = btrfs_lookup_block_group(root->fs_info,
+ BTRFS_I(inode)->block_group);
+ if (block_group && block_group->inode == inode) {
+ spin_lock(&block_group->lock);
+ block_group->inode = NULL;
+ spin_unlock(&block_group->lock);
+ btrfs_put_block_group(block_group);
+ } else if (block_group) {
+ btrfs_put_block_group(block_group);
+ }
+ }
+
spin_lock(&root->orphan_lock);
if (!list_empty(&BTRFS_I(inode)->i_orphan)) {
printk(KERN_INFO "BTRFS: inode %lu still on the orphan list\n",
{
struct btrfs_root *root = BTRFS_I(inode)->root;
- if (btrfs_root_refs(&root->root_item) == 0)
+ if (btrfs_root_refs(&root->root_item) == 0 &&
+ root != root->fs_info->tree_root)
return 1;
else
return generic_drop_inode(inode);
return 0;
}
-int btrfs_start_one_delalloc_inode(struct btrfs_root *root, int delay_iput)
+int btrfs_start_one_delalloc_inode(struct btrfs_root *root, int delay_iput,
+ int sync)
{
struct btrfs_inode *binode;
struct inode *inode = NULL;
spin_unlock(&root->fs_info->delalloc_lock);
if (inode) {
- write_inode_now(inode, 0);
+ if (sync) {
+ filemap_write_and_wait(inode->i_mapping);
+ /*
+ * We have to do this because compression doesn't
+ * actually set PG_writeback until it submits the pages
+ * for IO, which happens in an async thread, so we could
+ * race and not actually wait for any writeback pages
+ * because they've not been submitted yet. Technically
+ * this could still be the case for the ordered stuff
+ * since the async thread may not have started to do its
+ * work yet. If this becomes the case then we need to
+ * figure out a way to make sure that in writepage we
+ * wait for any async pages to be submitted before
+ * returning so that fdatawait does what its supposed to
+ * do.
+ */
+ btrfs_wait_ordered_range(inode, 0, (u64)-1);
+ } else {
+ filemap_flush(inode->i_mapping);
+ }
if (delay_iput)
btrfs_add_delayed_iput(inode);
else
return err;
}
-int btrfs_prealloc_file_range(struct inode *inode, int mode,
- u64 start, u64 num_bytes, u64 min_size,
- loff_t actual_len, u64 *alloc_hint)
+static int __btrfs_prealloc_file_range(struct inode *inode, int mode,
+ u64 start, u64 num_bytes, u64 min_size,
+ loff_t actual_len, u64 *alloc_hint,
+ struct btrfs_trans_handle *trans)
{
- struct btrfs_trans_handle *trans;
struct btrfs_root *root = BTRFS_I(inode)->root;
struct btrfs_key ins;
u64 cur_offset = start;
int ret = 0;
+ bool own_trans = true;
+ if (trans)
+ own_trans = false;
while (num_bytes > 0) {
- trans = btrfs_start_transaction(root, 3);
- if (IS_ERR(trans)) {
- ret = PTR_ERR(trans);
- break;
+ if (own_trans) {
+ trans = btrfs_start_transaction(root, 3);
+ if (IS_ERR(trans)) {
+ ret = PTR_ERR(trans);
+ break;
+ }
}
ret = btrfs_reserve_extent(trans, root, num_bytes, min_size,
0, *alloc_hint, (u64)-1, &ins, 1);
if (ret) {
- btrfs_end_transaction(trans, root);
+ if (own_trans)
+ btrfs_end_transaction(trans, root);
break;
}
ret = btrfs_update_inode(trans, root, inode);
BUG_ON(ret);
- btrfs_end_transaction(trans, root);
+ if (own_trans)
+ btrfs_end_transaction(trans, root);
}
return ret;
}
+int btrfs_prealloc_file_range(struct inode *inode, int mode,
+ u64 start, u64 num_bytes, u64 min_size,
+ loff_t actual_len, u64 *alloc_hint)
+{
+ return __btrfs_prealloc_file_range(inode, mode, start, num_bytes,
+ min_size, actual_len, alloc_hint,
+ NULL);
+}
+
+int btrfs_prealloc_file_range_trans(struct inode *inode,
+ struct btrfs_trans_handle *trans, int mode,
+ u64 start, u64 num_bytes, u64 min_size,
+ loff_t actual_len, u64 *alloc_hint)
+{
+ return __btrfs_prealloc_file_range(inode, mode, start, num_bytes,
+ min_size, actual_len, alloc_hint, trans);
+}
+
static long btrfs_fallocate(struct inode *inode, int mode,
loff_t offset, loff_t len)
{
static noinline int create_subvol(struct btrfs_root *root,
struct dentry *dentry,
- char *name, int namelen)
+ char *name, int namelen,
+ u64 *async_transid)
{
struct btrfs_trans_handle *trans;
struct btrfs_key key;
d_instantiate(dentry, btrfs_lookup_dentry(dir, dentry));
fail:
- err = btrfs_commit_transaction(trans, root);
+ if (async_transid) {
+ *async_transid = trans->transid;
+ err = btrfs_commit_transaction_async(trans, root, 1);
+ } else {
+ err = btrfs_commit_transaction(trans, root);
+ }
if (err && !ret)
ret = err;
return ret;
}
-static int create_snapshot(struct btrfs_root *root, struct dentry *dentry)
+static int create_snapshot(struct btrfs_root *root, struct dentry *dentry,
+ char *name, int namelen, u64 *async_transid)
{
struct inode *inode;
struct btrfs_pending_snapshot *pending_snapshot;
list_add(&pending_snapshot->list,
&trans->transaction->pending_snapshots);
- ret = btrfs_commit_transaction(trans, root->fs_info->extent_root);
+ if (async_transid) {
+ *async_transid = trans->transid;
+ ret = btrfs_commit_transaction_async(trans,
+ root->fs_info->extent_root, 1);
+ } else {
+ ret = btrfs_commit_transaction(trans,
+ root->fs_info->extent_root);
+ }
BUG_ON(ret);
ret = pending_snapshot->error;
return ret;
}
+/* copy of check_sticky in fs/namei.c()
+* It's inline, so penalty for filesystems that don't use sticky bit is
+* minimal.
+*/
+static inline int btrfs_check_sticky(struct inode *dir, struct inode *inode)
+{
+ uid_t fsuid = current_fsuid();
+
+ if (!(dir->i_mode & S_ISVTX))
+ return 0;
+ if (inode->i_uid == fsuid)
+ return 0;
+ if (dir->i_uid == fsuid)
+ return 0;
+ return !capable(CAP_FOWNER);
+}
+
+/* copy of may_delete in fs/namei.c()
+ * Check whether we can remove a link victim from directory dir, check
+ * whether the type of victim is right.
+ * 1. We can't do it if dir is read-only (done in permission())
+ * 2. We should have write and exec permissions on dir
+ * 3. We can't remove anything from append-only dir
+ * 4. We can't do anything with immutable dir (done in permission())
+ * 5. If the sticky bit on dir is set we should either
+ * a. be owner of dir, or
+ * b. be owner of victim, or
+ * c. have CAP_FOWNER capability
+ * 6. If the victim is append-only or immutable we can't do antyhing with
+ * links pointing to it.
+ * 7. If we were asked to remove a directory and victim isn't one - ENOTDIR.
+ * 8. If we were asked to remove a non-directory and victim isn't one - EISDIR.
+ * 9. We can't remove a root or mountpoint.
+ * 10. We don't allow removal of NFS sillyrenamed files; it's handled by
+ * nfs_async_unlink().
+ */
+
+static int btrfs_may_delete(struct inode *dir,struct dentry *victim,int isdir)
+{
+ int error;
+
+ if (!victim->d_inode)
+ return -ENOENT;
+
+ BUG_ON(victim->d_parent->d_inode != dir);
+ audit_inode_child(victim, dir);
+
+ error = inode_permission(dir, MAY_WRITE | MAY_EXEC);
+ if (error)
+ return error;
+ if (IS_APPEND(dir))
+ return -EPERM;
+ if (btrfs_check_sticky(dir, victim->d_inode)||
+ IS_APPEND(victim->d_inode)||
+ IS_IMMUTABLE(victim->d_inode) || IS_SWAPFILE(victim->d_inode))
+ return -EPERM;
+ if (isdir) {
+ if (!S_ISDIR(victim->d_inode->i_mode))
+ return -ENOTDIR;
+ if (IS_ROOT(victim))
+ return -EBUSY;
+ } else if (S_ISDIR(victim->d_inode->i_mode))
+ return -EISDIR;
+ if (IS_DEADDIR(dir))
+ return -ENOENT;
+ if (victim->d_flags & DCACHE_NFSFS_RENAMED)
+ return -EBUSY;
+ return 0;
+}
+
/* copy of may_create in fs/namei.c() */
static inline int btrfs_may_create(struct inode *dir, struct dentry *child)
{
*/
static noinline int btrfs_mksubvol(struct path *parent,
char *name, int namelen,
- struct btrfs_root *snap_src)
+ struct btrfs_root *snap_src,
+ u64 *async_transid)
{
struct inode *dir = parent->dentry->d_inode;
struct dentry *dentry;
goto out_up_read;
if (snap_src) {
- error = create_snapshot(snap_src, dentry);
+ error = create_snapshot(snap_src, dentry,
+ name, namelen, async_transid);
} else {
error = create_subvol(BTRFS_I(dir)->root, dentry,
- name, namelen);
+ name, namelen, async_transid);
}
if (!error)
fsnotify_mkdir(dir, dentry);
char *sizestr;
char *devstr = NULL;
int ret = 0;
- int namelen;
int mod = 0;
if (root->fs_info->sb->s_flags & MS_RDONLY)
return PTR_ERR(vol_args);
vol_args->name[BTRFS_PATH_NAME_MAX] = '\0';
- namelen = strlen(vol_args->name);
mutex_lock(&root->fs_info->volume_mutex);
sizestr = vol_args->name;
return ret;
}
-static noinline int btrfs_ioctl_snap_create(struct file *file,
- void __user *arg, int subvol)
+static noinline int btrfs_ioctl_snap_create_transid(struct file *file,
+ char *name,
+ unsigned long fd,
+ int subvol,
+ u64 *transid)
{
struct btrfs_root *root = BTRFS_I(fdentry(file)->d_inode)->root;
- struct btrfs_ioctl_vol_args *vol_args;
struct file *src_file;
int namelen;
int ret = 0;
if (root->fs_info->sb->s_flags & MS_RDONLY)
return -EROFS;
- vol_args = memdup_user(arg, sizeof(*vol_args));
- if (IS_ERR(vol_args))
- return PTR_ERR(vol_args);
-
- vol_args->name[BTRFS_PATH_NAME_MAX] = '\0';
- namelen = strlen(vol_args->name);
- if (strchr(vol_args->name, '/')) {
+ namelen = strlen(name);
+ if (strchr(name, '/')) {
ret = -EINVAL;
goto out;
}
if (subvol) {
- ret = btrfs_mksubvol(&file->f_path, vol_args->name, namelen,
- NULL);
+ ret = btrfs_mksubvol(&file->f_path, name, namelen,
+ NULL, transid);
} else {
struct inode *src_inode;
- src_file = fget(vol_args->fd);
+ src_file = fget(fd);
if (!src_file) {
ret = -EINVAL;
goto out;
fput(src_file);
goto out;
}
- ret = btrfs_mksubvol(&file->f_path, vol_args->name, namelen,
- BTRFS_I(src_inode)->root);
+ ret = btrfs_mksubvol(&file->f_path, name, namelen,
+ BTRFS_I(src_inode)->root,
+ transid);
fput(src_file);
}
out:
+ return ret;
+}
+
+static noinline int btrfs_ioctl_snap_create(struct file *file,
+ void __user *arg, int subvol,
+ int async)
+{
+ struct btrfs_ioctl_vol_args *vol_args = NULL;
+ struct btrfs_ioctl_async_vol_args *async_vol_args = NULL;
+ char *name;
+ u64 fd;
+ u64 transid = 0;
+ int ret;
+
+ if (async) {
+ async_vol_args = memdup_user(arg, sizeof(*async_vol_args));
+ if (IS_ERR(async_vol_args))
+ return PTR_ERR(async_vol_args);
+
+ name = async_vol_args->name;
+ fd = async_vol_args->fd;
+ async_vol_args->name[BTRFS_SNAPSHOT_NAME_MAX] = '\0';
+ } else {
+ vol_args = memdup_user(arg, sizeof(*vol_args));
+ if (IS_ERR(vol_args))
+ return PTR_ERR(vol_args);
+ name = vol_args->name;
+ fd = vol_args->fd;
+ vol_args->name[BTRFS_PATH_NAME_MAX] = '\0';
+ }
+
+ ret = btrfs_ioctl_snap_create_transid(file, name, fd,
+ subvol, &transid);
+
+ if (!ret && async) {
+ if (copy_to_user(arg +
+ offsetof(struct btrfs_ioctl_async_vol_args,
+ transid), &transid, sizeof(transid)))
+ return -EFAULT;
+ }
+
kfree(vol_args);
+ kfree(async_vol_args);
+
return ret;
}
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
- args = kmalloc(sizeof(*args), GFP_KERNEL);
- if (!args)
- return -ENOMEM;
+ args = memdup_user(argp, sizeof(*args));
+ if (IS_ERR(args))
+ return PTR_ERR(args);
- if (copy_from_user(args, argp, sizeof(*args))) {
- kfree(args);
- return -EFAULT;
- }
inode = fdentry(file)->d_inode;
ret = search_ioctl(inode, args);
if (ret == 0 && copy_to_user(argp, args, sizeof(*args)))
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
- args = kmalloc(sizeof(*args), GFP_KERNEL);
- if (!args)
- return -ENOMEM;
+ args = memdup_user(argp, sizeof(*args));
+ if (IS_ERR(args))
+ return PTR_ERR(args);
- if (copy_from_user(args, argp, sizeof(*args))) {
- kfree(args);
- return -EFAULT;
- }
inode = fdentry(file)->d_inode;
if (args->treeid == 0)
int ret;
int err = 0;
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
-
vol_args = memdup_user(arg, sizeof(*vol_args));
if (IS_ERR(vol_args))
return PTR_ERR(vol_args);
}
inode = dentry->d_inode;
+ dest = BTRFS_I(inode)->root;
+ if (!capable(CAP_SYS_ADMIN)){
+ /*
+ * Regular user. Only allow this with a special mount
+ * option, when the user has write+exec access to the
+ * subvol root, and when rmdir(2) would have been
+ * allowed.
+ *
+ * Note that this is _not_ check that the subvol is
+ * empty or doesn't contain data that we wouldn't
+ * otherwise be able to delete.
+ *
+ * Users who want to delete empty subvols should try
+ * rmdir(2).
+ */
+ err = -EPERM;
+ if (!btrfs_test_opt(root, USER_SUBVOL_RM_ALLOWED))
+ goto out_dput;
+
+ /*
+ * Do not allow deletion if the parent dir is the same
+ * as the dir to be deleted. That means the ioctl
+ * must be called on the dentry referencing the root
+ * of the subvol, not a random directory contained
+ * within it.
+ */
+ err = -EINVAL;
+ if (root == dest)
+ goto out_dput;
+
+ err = inode_permission(inode, MAY_WRITE | MAY_EXEC);
+ if (err)
+ goto out_dput;
+
+ /* check if subvolume may be deleted by a non-root user */
+ err = btrfs_may_delete(dir, dentry, 1);
+ if (err)
+ goto out_dput;
+ }
+
if (inode->i_ino != BTRFS_FIRST_FREE_OBJECTID) {
err = -EINVAL;
goto out_dput;
}
- dest = BTRFS_I(inode)->root;
-
mutex_lock(&inode->i_mutex);
err = d_invalidate(dentry);
if (err)
BUG_ON(ret);
}
- ret = btrfs_commit_transaction(trans, root);
+ ret = btrfs_end_transaction(trans, root);
BUG_ON(ret);
inode->i_flags |= S_DEAD;
out_up_write:
path->reada = 2;
if (inode < src) {
- mutex_lock(&inode->i_mutex);
- mutex_lock(&src->i_mutex);
+ mutex_lock_nested(&inode->i_mutex, I_MUTEX_PARENT);
+ mutex_lock_nested(&src->i_mutex, I_MUTEX_CHILD);
} else {
- mutex_lock(&src->i_mutex);
- mutex_lock(&inode->i_mutex);
+ mutex_lock_nested(&src->i_mutex, I_MUTEX_PARENT);
+ mutex_lock_nested(&inode->i_mutex, I_MUTEX_CHILD);
}
/* determine range to clone */
while (1) {
struct btrfs_ordered_extent *ordered;
lock_extent(&BTRFS_I(src)->io_tree, off, off+len, GFP_NOFS);
- ordered = btrfs_lookup_first_ordered_extent(inode, off+len);
- if (BTRFS_I(src)->delalloc_bytes == 0 && !ordered)
+ ordered = btrfs_lookup_first_ordered_extent(src, off+len);
+ if (!ordered &&
+ !test_range_bit(&BTRFS_I(src)->io_tree, off, off+len,
+ EXTENT_DELALLOC, 0, NULL))
break;
unlock_extent(&BTRFS_I(src)->io_tree, off, off+len, GFP_NOFS);
if (ordered)
btrfs_put_ordered_extent(ordered);
- btrfs_wait_ordered_range(src, off, off+len);
+ btrfs_wait_ordered_range(src, off, len);
}
/* clone data */
}
btrfs_release_path(root, path);
- if (key.offset + datal < off ||
+ if (key.offset + datal <= off ||
key.offset >= off+len)
goto next;
return 0;
}
+static void get_block_group_info(struct list_head *groups_list,
+ struct btrfs_ioctl_space_info *space)
+{
+ struct btrfs_block_group_cache *block_group;
+
+ space->total_bytes = 0;
+ space->used_bytes = 0;
+ space->flags = 0;
+ list_for_each_entry(block_group, groups_list, list) {
+ space->flags = block_group->flags;
+ space->total_bytes += block_group->key.offset;
+ space->used_bytes +=
+ btrfs_block_group_used(&block_group->item);
+ }
+}
+
long btrfs_ioctl_space_info(struct btrfs_root *root, void __user *arg)
{
struct btrfs_ioctl_space_args space_args;
struct btrfs_ioctl_space_info *dest_orig;
struct btrfs_ioctl_space_info *user_dest;
struct btrfs_space_info *info;
+ u64 types[] = {BTRFS_BLOCK_GROUP_DATA,
+ BTRFS_BLOCK_GROUP_SYSTEM,
+ BTRFS_BLOCK_GROUP_METADATA,
+ BTRFS_BLOCK_GROUP_DATA | BTRFS_BLOCK_GROUP_METADATA};
+ int num_types = 4;
int alloc_size;
int ret = 0;
int slot_count = 0;
+ int i, c;
if (copy_from_user(&space_args,
(struct btrfs_ioctl_space_args __user *)arg,
sizeof(space_args)))
return -EFAULT;
- /* first we count slots */
- rcu_read_lock();
- list_for_each_entry_rcu(info, &root->fs_info->space_info, list)
- slot_count++;
- rcu_read_unlock();
+ for (i = 0; i < num_types; i++) {
+ struct btrfs_space_info *tmp;
+
+ info = NULL;
+ rcu_read_lock();
+ list_for_each_entry_rcu(tmp, &root->fs_info->space_info,
+ list) {
+ if (tmp->flags == types[i]) {
+ info = tmp;
+ break;
+ }
+ }
+ rcu_read_unlock();
+
+ if (!info)
+ continue;
+
+ down_read(&info->groups_sem);
+ for (c = 0; c < BTRFS_NR_RAID_TYPES; c++) {
+ if (!list_empty(&info->block_groups[c]))
+ slot_count++;
+ }
+ up_read(&info->groups_sem);
+ }
/* space_slots == 0 means they are asking for a count */
if (space_args.space_slots == 0) {
space_args.total_spaces = slot_count;
goto out;
}
+
+ slot_count = min_t(int, space_args.space_slots, slot_count);
+
alloc_size = sizeof(*dest) * slot_count;
+
/* we generally have at most 6 or so space infos, one for each raid
* level. So, a whole page should be more than enough for everyone
*/
dest_orig = dest;
/* now we have a buffer to copy into */
- rcu_read_lock();
- list_for_each_entry_rcu(info, &root->fs_info->space_info, list) {
- /* make sure we don't copy more than we allocated
- * in our buffer
- */
- if (slot_count == 0)
- break;
- slot_count--;
-
- /* make sure userland has enough room in their buffer */
- if (space_args.total_spaces >= space_args.space_slots)
- break;
+ for (i = 0; i < num_types; i++) {
+ struct btrfs_space_info *tmp;
+
+ info = NULL;
+ rcu_read_lock();
+ list_for_each_entry_rcu(tmp, &root->fs_info->space_info,
+ list) {
+ if (tmp->flags == types[i]) {
+ info = tmp;
+ break;
+ }
+ }
+ rcu_read_unlock();
- space.flags = info->flags;
- space.total_bytes = info->total_bytes;
- space.used_bytes = info->bytes_used;
- memcpy(dest, &space, sizeof(space));
- dest++;
- space_args.total_spaces++;
+ if (!info)
+ continue;
+ down_read(&info->groups_sem);
+ for (c = 0; c < BTRFS_NR_RAID_TYPES; c++) {
+ if (!list_empty(&info->block_groups[c])) {
+ get_block_group_info(&info->block_groups[c],
+ &space);
+ memcpy(dest, &space, sizeof(space));
+ dest++;
+ space_args.total_spaces++;
+ }
+ }
+ up_read(&info->groups_sem);
}
- rcu_read_unlock();
user_dest = (struct btrfs_ioctl_space_info *)
(arg + sizeof(struct btrfs_ioctl_space_args));
return 0;
}
+static noinline long btrfs_ioctl_start_sync(struct file *file, void __user *argp)
+{
+ struct btrfs_root *root = BTRFS_I(file->f_dentry->d_inode)->root;
+ struct btrfs_trans_handle *trans;
+ u64 transid;
+
+ trans = btrfs_start_transaction(root, 0);
+ transid = trans->transid;
+ btrfs_commit_transaction_async(trans, root, 0);
+
+ if (argp)
+ if (copy_to_user(argp, &transid, sizeof(transid)))
+ return -EFAULT;
+ return 0;
+}
+
+static noinline long btrfs_ioctl_wait_sync(struct file *file, void __user *argp)
+{
+ struct btrfs_root *root = BTRFS_I(file->f_dentry->d_inode)->root;
+ u64 transid;
+
+ if (argp) {
+ if (copy_from_user(&transid, argp, sizeof(transid)))
+ return -EFAULT;
+ } else {
+ transid = 0; /* current trans */
+ }
+ return btrfs_wait_for_commit(root, transid);
+}
+
long btrfs_ioctl(struct file *file, unsigned int
cmd, unsigned long arg)
{
case FS_IOC_GETVERSION:
return btrfs_ioctl_getversion(file, argp);
case BTRFS_IOC_SNAP_CREATE:
- return btrfs_ioctl_snap_create(file, argp, 0);
+ return btrfs_ioctl_snap_create(file, argp, 0, 0);
+ case BTRFS_IOC_SNAP_CREATE_ASYNC:
+ return btrfs_ioctl_snap_create(file, argp, 0, 1);
case BTRFS_IOC_SUBVOL_CREATE:
- return btrfs_ioctl_snap_create(file, argp, 1);
+ return btrfs_ioctl_snap_create(file, argp, 1, 0);
case BTRFS_IOC_SNAP_DESTROY:
return btrfs_ioctl_snap_destroy(file, argp);
case BTRFS_IOC_DEFAULT_SUBVOL:
case BTRFS_IOC_SYNC:
btrfs_sync_fs(file->f_dentry->d_sb, 1);
return 0;
+ case BTRFS_IOC_START_SYNC:
+ return btrfs_ioctl_start_sync(file, argp);
+ case BTRFS_IOC_WAIT_SYNC:
+ return btrfs_ioctl_wait_sync(file, argp);
}
return -ENOTTY;
#define BTRFS_IOCTL_MAGIC 0x94
#define BTRFS_VOL_NAME_MAX 255
-#define BTRFS_PATH_NAME_MAX 4087
/* this should be 4k */
+#define BTRFS_PATH_NAME_MAX 4087
struct btrfs_ioctl_vol_args {
__s64 fd;
char name[BTRFS_PATH_NAME_MAX + 1];
};
+#define BTRFS_SNAPSHOT_NAME_MAX 4079
+struct btrfs_ioctl_async_vol_args {
+ __s64 fd;
+ __u64 transid;
+ char name[BTRFS_SNAPSHOT_NAME_MAX + 1];
+};
+
#define BTRFS_INO_LOOKUP_PATH_MAX 4080
struct btrfs_ioctl_ino_lookup_args {
__u64 treeid;
#define BTRFS_IOC_DEFAULT_SUBVOL _IOW(BTRFS_IOCTL_MAGIC, 19, u64)
#define BTRFS_IOC_SPACE_INFO _IOWR(BTRFS_IOCTL_MAGIC, 20, \
struct btrfs_ioctl_space_args)
+#define BTRFS_IOC_START_SYNC _IOR(BTRFS_IOCTL_MAGIC, 24, __u64)
+#define BTRFS_IOC_WAIT_SYNC _IOW(BTRFS_IOCTL_MAGIC, 22, __u64)
+#define BTRFS_IOC_SNAP_CREATE_ASYNC _IOW(BTRFS_IOCTL_MAGIC, 23, \
+ struct btrfs_ioctl_async_vol_args)
#endif
{
u64 end;
u64 orig_end;
- u64 wait_end;
struct btrfs_ordered_extent *ordered;
int found;
if (orig_end > INT_LIMIT(loff_t))
orig_end = INT_LIMIT(loff_t);
}
- wait_end = orig_end;
again:
/* start IO across the range first to instantiate any delalloc
* extents
#include "locking.h"
#include "btrfs_inode.h"
#include "async-thread.h"
+#include "free-space-cache.h"
/*
* backref_node, mapping_node and tree_block start with this
u64 search_start;
u64 extents_found;
- int block_rsv_retries;
-
unsigned int stage:8;
unsigned int create_reloc_tree:1;
unsigned int merge_reloc_tree:1;
LIST_HEAD(reloc_roots);
u64 num_bytes = 0;
int ret;
- int retries = 0;
mutex_lock(&root->fs_info->trans_mutex);
rc->merging_rsv_size += root->nodesize * (BTRFS_MAX_LEVEL - 1) * 2;
if (!err) {
num_bytes = rc->merging_rsv_size;
ret = btrfs_block_rsv_add(NULL, root, rc->block_rsv,
- num_bytes, &retries);
+ num_bytes);
if (ret)
err = ret;
}
btrfs_end_transaction(trans, rc->extent_root);
btrfs_block_rsv_release(rc->extent_root,
rc->block_rsv, num_bytes);
- retries = 0;
goto again;
}
}
num_bytes = calcu_metadata_size(rc, node, 1) * 2;
trans->block_rsv = rc->block_rsv;
- ret = btrfs_block_rsv_add(trans, root, rc->block_rsv, num_bytes,
- &rc->block_rsv_retries);
+ ret = btrfs_block_rsv_add(trans, root, rc->block_rsv, num_bytes);
if (ret) {
if (ret == -EAGAIN)
rc->commit_transaction = 1;
return ret;
}
- rc->block_rsv_retries = 0;
return 0;
}
BUG_ON(item_size != sizeof(struct btrfs_extent_item_v0));
ret = get_ref_objectid_v0(rc, path, extent_key,
&ref_owner, NULL);
+ if (ret < 0)
+ return ret;
BUG_ON(ref_owner >= BTRFS_MAX_LEVEL);
level = (int)ref_owner;
/* FIXME: get real generation */
return ret;
}
+static int delete_block_group_cache(struct btrfs_fs_info *fs_info,
+ struct inode *inode, u64 ino)
+{
+ struct btrfs_key key;
+ struct btrfs_path *path;
+ struct btrfs_root *root = fs_info->tree_root;
+ struct btrfs_trans_handle *trans;
+ unsigned long nr;
+ int ret = 0;
+
+ if (inode)
+ goto truncate;
+
+ key.objectid = ino;
+ key.type = BTRFS_INODE_ITEM_KEY;
+ key.offset = 0;
+
+ inode = btrfs_iget(fs_info->sb, &key, root, NULL);
+ if (!inode || IS_ERR(inode) || is_bad_inode(inode)) {
+ if (inode && !IS_ERR(inode))
+ iput(inode);
+ return -ENOENT;
+ }
+
+truncate:
+ path = btrfs_alloc_path();
+ if (!path) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ trans = btrfs_join_transaction(root, 0);
+ if (IS_ERR(trans)) {
+ btrfs_free_path(path);
+ goto out;
+ }
+
+ ret = btrfs_truncate_free_space_cache(root, trans, path, inode);
+
+ btrfs_free_path(path);
+ nr = trans->blocks_used;
+ btrfs_end_transaction(trans, root);
+ btrfs_btree_balance_dirty(root, nr);
+out:
+ iput(inode);
+ return ret;
+}
+
/*
* helper to add tree blocks for backref of type BTRFS_EXTENT_DATA_REF_KEY
* this function scans fs tree to find blocks reference the data extent
int counted;
int ret;
- path = btrfs_alloc_path();
- if (!path)
- return -ENOMEM;
-
ref_root = btrfs_extent_data_ref_root(leaf, ref);
ref_objectid = btrfs_extent_data_ref_objectid(leaf, ref);
ref_offset = btrfs_extent_data_ref_offset(leaf, ref);
ref_count = btrfs_extent_data_ref_count(leaf, ref);
+ /*
+ * This is an extent belonging to the free space cache, lets just delete
+ * it and redo the search.
+ */
+ if (ref_root == BTRFS_ROOT_TREE_OBJECTID) {
+ ret = delete_block_group_cache(rc->extent_root->fs_info,
+ NULL, ref_objectid);
+ if (ret != -ENOENT)
+ return ret;
+ ret = 0;
+ }
+
+ path = btrfs_alloc_path();
+ if (!path)
+ return -ENOMEM;
+
root = read_fs_root(rc->extent_root->fs_info, ref_root);
if (IS_ERR(root)) {
err = PTR_ERR(root);
* is no reservation in transaction handle.
*/
ret = btrfs_block_rsv_add(NULL, rc->extent_root, rc->block_rsv,
- rc->extent_root->nodesize * 256,
- &rc->block_rsv_retries);
+ rc->extent_root->nodesize * 256);
if (ret)
return ret;
rc->extents_found = 0;
rc->nodes_relocated = 0;
rc->merging_rsv_size = 0;
- rc->block_rsv_retries = 0;
rc->create_reloc_tree = 1;
set_reloc_control(rc);
{
struct btrfs_fs_info *fs_info = extent_root->fs_info;
struct reloc_control *rc;
+ struct inode *inode;
+ struct btrfs_path *path;
int ret;
int rw = 0;
int err = 0;
rw = 1;
}
+ path = btrfs_alloc_path();
+ if (!path) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ inode = lookup_free_space_inode(fs_info->tree_root, rc->block_group,
+ path);
+ btrfs_free_path(path);
+
+ if (!IS_ERR(inode))
+ ret = delete_block_group_cache(fs_info, inode, 0);
+ else
+ ret = PTR_ERR(inode);
+
+ if (ret && ret != -ENOENT) {
+ err = ret;
+ goto out;
+ }
+
rc->data_inode = create_reloc_inode(fs_info, rc->block_group);
if (IS_ERR(rc->data_inode)) {
err = PTR_ERR(rc->data_inode);
btrfs_add_ordered_sum(inode, ordered, sums);
}
btrfs_put_ordered_extent(ordered);
- return 0;
+ return ret;
}
void btrfs_reloc_cow_block(struct btrfs_trans_handle *trans,
int btrfs_find_dead_roots(struct btrfs_root *root, u64 objectid)
{
struct btrfs_root *dead_root;
- struct btrfs_item *item;
struct btrfs_root_item *ri;
struct btrfs_key key;
struct btrfs_key found_key;
nritems = btrfs_header_nritems(leaf);
slot = path->slots[0];
}
- item = btrfs_item_nr(leaf, slot);
btrfs_item_key_to_cpu(leaf, &key, slot);
if (btrfs_key_type(&key) != BTRFS_ROOT_ITEM_KEY)
goto next;
ret = close_ctree(root);
sb->s_fs_info = NULL;
+
+ (void)ret; /* FIXME: need to fix VFS to return error? */
}
enum {
Opt_nodatacow, Opt_max_inline, Opt_alloc_start, Opt_nobarrier, Opt_ssd,
Opt_nossd, Opt_ssd_spread, Opt_thread_pool, Opt_noacl, Opt_compress,
Opt_compress_force, Opt_notreelog, Opt_ratio, Opt_flushoncommit,
- Opt_discard, Opt_err,
+ Opt_discard, Opt_space_cache, Opt_clear_cache, Opt_err,
+ Opt_user_subvol_rm_allowed,
};
static match_table_t tokens = {
{Opt_flushoncommit, "flushoncommit"},
{Opt_ratio, "metadata_ratio=%d"},
{Opt_discard, "discard"},
+ {Opt_space_cache, "space_cache"},
+ {Opt_clear_cache, "clear_cache"},
+ {Opt_user_subvol_rm_allowed, "user_subvol_rm_allowed"},
{Opt_err, NULL},
};
case Opt_discard:
btrfs_set_opt(info->mount_opt, DISCARD);
break;
+ case Opt_space_cache:
+ printk(KERN_INFO "btrfs: enabling disk space caching\n");
+ btrfs_set_opt(info->mount_opt, SPACE_CACHE);
+ case Opt_clear_cache:
+ printk(KERN_INFO "btrfs: force clearing of disk cache\n");
+ btrfs_set_opt(info->mount_opt, CLEAR_CACHE);
+ break;
+ case Opt_user_subvol_rm_allowed:
+ btrfs_set_opt(info->mount_opt, USER_SUBVOL_RM_ALLOWED);
+ break;
case Opt_err:
printk(KERN_INFO "btrfs: unrecognized mount option "
"'%s'\n", p);
find_root:
new_root = btrfs_read_fs_root_no_name(root->fs_info, &location);
if (IS_ERR(new_root))
- return ERR_PTR(PTR_ERR(new_root));
+ return ERR_CAST(new_root);
if (btrfs_root_refs(&new_root->root_item) == 0)
return ERR_PTR(-ENOENT);
{
struct inode *inode;
struct dentry *root_dentry;
- struct btrfs_super_block *disk_super;
struct btrfs_root *tree_root;
struct btrfs_key key;
int err;
return PTR_ERR(tree_root);
}
sb->s_fs_info = tree_root;
- disk_super = &tree_root->fs_info->super_copy;
key.objectid = BTRFS_FIRST_FREE_OBJECTID;
key.type = BTRFS_INODE_ITEM_KEY;
* Note: This is based on get_sb_bdev from fs/super.c with a few additions
* for multiple device setup. Make sure to keep it in sync.
*/
-static int btrfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *btrfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
struct block_device *bdev = NULL;
struct super_block *s;
char *subvol_name = NULL;
u64 subvol_objectid = 0;
int error = 0;
- int found = 0;
if (!(flags & MS_RDONLY))
mode |= FMODE_WRITE;
&subvol_name, &subvol_objectid,
&fs_devices);
if (error)
- return error;
+ return ERR_PTR(error);
error = btrfs_scan_one_device(dev_name, mode, fs_type, &fs_devices);
if (error)
goto error_close_devices;
}
- found = 1;
btrfs_close_devices(fs_devices);
} else {
char b[BDEVNAME_SIZE];
if (IS_ERR(root)) {
error = PTR_ERR(root);
deactivate_locked_super(s);
- goto error;
+ goto error_free_subvol_name;
}
/* if they gave us a subvolume name bind mount into that */
if (strcmp(subvol_name, ".")) {
deactivate_locked_super(s);
error = PTR_ERR(new_root);
dput(root);
- goto error_close_devices;
+ goto error_free_subvol_name;
}
if (!new_root->d_inode) {
dput(root);
dput(new_root);
deactivate_locked_super(s);
error = -ENXIO;
- goto error_close_devices;
+ goto error_free_subvol_name;
}
dput(root);
root = new_root;
}
- mnt->mnt_sb = s;
- mnt->mnt_root = root;
-
kfree(subvol_name);
- return 0;
+ return root;
error_s:
error = PTR_ERR(s);
btrfs_close_devices(fs_devices);
error_free_subvol_name:
kfree(subvol_name);
-error:
- return error;
+ return ERR_PTR(error);
}
static int btrfs_remount(struct super_block *sb, int *flags, char *data)
struct list_head *head = &root->fs_info->space_info;
struct btrfs_space_info *found;
u64 total_used = 0;
+ u64 total_used_data = 0;
int bits = dentry->d_sb->s_blocksize_bits;
__be32 *fsid = (__be32 *)root->fs_info->fsid;
rcu_read_lock();
- list_for_each_entry_rcu(found, head, list)
+ list_for_each_entry_rcu(found, head, list) {
+ if (found->flags & (BTRFS_BLOCK_GROUP_METADATA |
+ BTRFS_BLOCK_GROUP_SYSTEM))
+ total_used_data += found->disk_total;
+ else
+ total_used_data += found->disk_used;
total_used += found->disk_used;
+ }
rcu_read_unlock();
buf->f_namelen = BTRFS_NAME_LEN;
buf->f_blocks = btrfs_super_total_bytes(disk_super) >> bits;
buf->f_bfree = buf->f_blocks - (total_used >> bits);
- buf->f_bavail = buf->f_bfree;
+ buf->f_bavail = buf->f_blocks - (total_used_data >> bits);
buf->f_bsize = dentry->d_sb->s_blocksize;
buf->f_type = BTRFS_SUPER_MAGIC;
static struct file_system_type btrfs_fs_type = {
.owner = THIS_MODULE,
.name = "btrfs",
- .get_sb = btrfs_get_sb,
+ .mount = btrfs_mount,
.kill_sb = kill_anon_super,
.fs_flags = FS_REQUIRES_DEV,
};
TRANS_START,
TRANS_JOIN,
TRANS_USERSPACE,
+ TRANS_JOIN_NOLOCK,
};
static int may_wait_transaction(struct btrfs_root *root, int type)
{
struct btrfs_trans_handle *h;
struct btrfs_transaction *cur_trans;
- int retries = 0;
int ret;
again:
h = kmem_cache_alloc(btrfs_trans_handle_cachep, GFP_NOFS);
if (!h)
return ERR_PTR(-ENOMEM);
- mutex_lock(&root->fs_info->trans_mutex);
+ if (type != TRANS_JOIN_NOLOCK)
+ mutex_lock(&root->fs_info->trans_mutex);
if (may_wait_transaction(root, type))
wait_current_trans(root);
cur_trans = root->fs_info->running_transaction;
cur_trans->use_count++;
- mutex_unlock(&root->fs_info->trans_mutex);
+ if (type != TRANS_JOIN_NOLOCK)
+ mutex_unlock(&root->fs_info->trans_mutex);
h->transid = cur_trans->transid;
h->transaction = cur_trans;
}
if (num_items > 0) {
- ret = btrfs_trans_reserve_metadata(h, root, num_items,
- &retries);
+ ret = btrfs_trans_reserve_metadata(h, root, num_items);
if (ret == -EAGAIN) {
btrfs_commit_transaction(h, root);
goto again;
}
}
- mutex_lock(&root->fs_info->trans_mutex);
+ if (type != TRANS_JOIN_NOLOCK)
+ mutex_lock(&root->fs_info->trans_mutex);
record_root_in_trans(h, root);
- mutex_unlock(&root->fs_info->trans_mutex);
+ if (type != TRANS_JOIN_NOLOCK)
+ mutex_unlock(&root->fs_info->trans_mutex);
if (!current->journal_info && type != TRANS_USERSPACE)
current->journal_info = h;
return start_transaction(root, 0, TRANS_JOIN);
}
+struct btrfs_trans_handle *btrfs_join_transaction_nolock(struct btrfs_root *root,
+ int num_blocks)
+{
+ return start_transaction(root, 0, TRANS_JOIN_NOLOCK);
+}
+
struct btrfs_trans_handle *btrfs_start_ioctl_transaction(struct btrfs_root *r,
int num_blocks)
{
return 0;
}
+int btrfs_wait_for_commit(struct btrfs_root *root, u64 transid)
+{
+ struct btrfs_transaction *cur_trans = NULL, *t;
+ int ret;
+
+ mutex_lock(&root->fs_info->trans_mutex);
+
+ ret = 0;
+ if (transid) {
+ if (transid <= root->fs_info->last_trans_committed)
+ goto out_unlock;
+
+ /* find specified transaction */
+ list_for_each_entry(t, &root->fs_info->trans_list, list) {
+ if (t->transid == transid) {
+ cur_trans = t;
+ break;
+ }
+ if (t->transid > transid)
+ break;
+ }
+ ret = -EINVAL;
+ if (!cur_trans)
+ goto out_unlock; /* bad transid */
+ } else {
+ /* find newest transaction that is committing | committed */
+ list_for_each_entry_reverse(t, &root->fs_info->trans_list,
+ list) {
+ if (t->in_commit) {
+ if (t->commit_done)
+ goto out_unlock;
+ cur_trans = t;
+ break;
+ }
+ }
+ if (!cur_trans)
+ goto out_unlock; /* nothing committing|committed */
+ }
+
+ cur_trans->use_count++;
+ mutex_unlock(&root->fs_info->trans_mutex);
+
+ wait_for_commit(root, cur_trans);
+
+ mutex_lock(&root->fs_info->trans_mutex);
+ put_transaction(cur_trans);
+ ret = 0;
+out_unlock:
+ mutex_unlock(&root->fs_info->trans_mutex);
+ return ret;
+}
+
#if 0
/*
* rate limit against the drop_snapshot code. This helps to slow down new
}
static int __btrfs_end_transaction(struct btrfs_trans_handle *trans,
- struct btrfs_root *root, int throttle)
+ struct btrfs_root *root, int throttle, int lock)
{
struct btrfs_transaction *cur_trans = trans->transaction;
struct btrfs_fs_info *info = root->fs_info;
btrfs_trans_release_metadata(trans, root);
- if (!root->fs_info->open_ioctl_trans &&
+ if (lock && !root->fs_info->open_ioctl_trans &&
should_end_transaction(trans, root))
trans->transaction->blocked = 1;
- if (cur_trans->blocked && !cur_trans->in_commit) {
+ if (lock && cur_trans->blocked && !cur_trans->in_commit) {
if (throttle)
return btrfs_commit_transaction(trans, root);
else
wake_up_process(info->transaction_kthread);
}
- mutex_lock(&info->trans_mutex);
+ if (lock)
+ mutex_lock(&info->trans_mutex);
WARN_ON(cur_trans != info->running_transaction);
WARN_ON(cur_trans->num_writers < 1);
cur_trans->num_writers--;
+ smp_mb();
if (waitqueue_active(&cur_trans->writer_wait))
wake_up(&cur_trans->writer_wait);
put_transaction(cur_trans);
- mutex_unlock(&info->trans_mutex);
+ if (lock)
+ mutex_unlock(&info->trans_mutex);
if (current->journal_info == trans)
current->journal_info = NULL;
int btrfs_end_transaction(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
- return __btrfs_end_transaction(trans, root, 0);
+ return __btrfs_end_transaction(trans, root, 0, 1);
}
int btrfs_end_transaction_throttle(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
- return __btrfs_end_transaction(trans, root, 1);
+ return __btrfs_end_transaction(trans, root, 1, 1);
+}
+
+int btrfs_end_transaction_nolock(struct btrfs_trans_handle *trans,
+ struct btrfs_root *root)
+{
+ return __btrfs_end_transaction(trans, root, 0, 0);
}
/*
struct extent_buffer *tmp;
struct extent_buffer *old;
int ret;
- int retries = 0;
u64 to_reserve = 0;
u64 index = 0;
u64 objectid;
if (to_reserve > 0) {
ret = btrfs_block_rsv_add(trans, root, &pending->block_rsv,
- to_reserve, &retries);
+ to_reserve);
if (ret) {
pending->error = ret;
goto fail;
super->root = root_item->bytenr;
super->generation = root_item->generation;
super->root_level = root_item->level;
+ if (super->cache_generation != 0 || btrfs_test_opt(root, SPACE_CACHE))
+ super->cache_generation = root_item->generation;
}
int btrfs_transaction_in_commit(struct btrfs_fs_info *info)
return ret;
}
+/*
+ * wait for the current transaction commit to start and block subsequent
+ * transaction joins
+ */
+static void wait_current_trans_commit_start(struct btrfs_root *root,
+ struct btrfs_transaction *trans)
+{
+ DEFINE_WAIT(wait);
+
+ if (trans->in_commit)
+ return;
+
+ while (1) {
+ prepare_to_wait(&root->fs_info->transaction_blocked_wait, &wait,
+ TASK_UNINTERRUPTIBLE);
+ if (trans->in_commit) {
+ finish_wait(&root->fs_info->transaction_blocked_wait,
+ &wait);
+ break;
+ }
+ mutex_unlock(&root->fs_info->trans_mutex);
+ schedule();
+ mutex_lock(&root->fs_info->trans_mutex);
+ finish_wait(&root->fs_info->transaction_blocked_wait, &wait);
+ }
+}
+
+/*
+ * wait for the current transaction to start and then become unblocked.
+ * caller holds ref.
+ */
+static void wait_current_trans_commit_start_and_unblock(struct btrfs_root *root,
+ struct btrfs_transaction *trans)
+{
+ DEFINE_WAIT(wait);
+
+ if (trans->commit_done || (trans->in_commit && !trans->blocked))
+ return;
+
+ while (1) {
+ prepare_to_wait(&root->fs_info->transaction_wait, &wait,
+ TASK_UNINTERRUPTIBLE);
+ if (trans->commit_done ||
+ (trans->in_commit && !trans->blocked)) {
+ finish_wait(&root->fs_info->transaction_wait,
+ &wait);
+ break;
+ }
+ mutex_unlock(&root->fs_info->trans_mutex);
+ schedule();
+ mutex_lock(&root->fs_info->trans_mutex);
+ finish_wait(&root->fs_info->transaction_wait,
+ &wait);
+ }
+}
+
+/*
+ * commit transactions asynchronously. once btrfs_commit_transaction_async
+ * returns, any subsequent transaction will not be allowed to join.
+ */
+struct btrfs_async_commit {
+ struct btrfs_trans_handle *newtrans;
+ struct btrfs_root *root;
+ struct delayed_work work;
+};
+
+static void do_async_commit(struct work_struct *work)
+{
+ struct btrfs_async_commit *ac =
+ container_of(work, struct btrfs_async_commit, work.work);
+
+ btrfs_commit_transaction(ac->newtrans, ac->root);
+ kfree(ac);
+}
+
+int btrfs_commit_transaction_async(struct btrfs_trans_handle *trans,
+ struct btrfs_root *root,
+ int wait_for_unblock)
+{
+ struct btrfs_async_commit *ac;
+ struct btrfs_transaction *cur_trans;
+
+ ac = kmalloc(sizeof(*ac), GFP_NOFS);
+ BUG_ON(!ac);
+
+ INIT_DELAYED_WORK(&ac->work, do_async_commit);
+ ac->root = root;
+ ac->newtrans = btrfs_join_transaction(root, 0);
+
+ /* take transaction reference */
+ mutex_lock(&root->fs_info->trans_mutex);
+ cur_trans = trans->transaction;
+ cur_trans->use_count++;
+ mutex_unlock(&root->fs_info->trans_mutex);
+
+ btrfs_end_transaction(trans, root);
+ schedule_delayed_work(&ac->work, 0);
+
+ /* wait for transaction to start and unblock */
+ mutex_lock(&root->fs_info->trans_mutex);
+ if (wait_for_unblock)
+ wait_current_trans_commit_start_and_unblock(root, cur_trans);
+ else
+ wait_current_trans_commit_start(root, cur_trans);
+ put_transaction(cur_trans);
+ mutex_unlock(&root->fs_info->trans_mutex);
+
+ return 0;
+}
+
+/*
+ * btrfs_transaction state sequence:
+ * in_commit = 0, blocked = 0 (initial)
+ * in_commit = 1, blocked = 1
+ * blocked = 0
+ * commit_done = 1
+ */
int btrfs_commit_transaction(struct btrfs_trans_handle *trans,
struct btrfs_root *root)
{
unsigned long joined = 0;
- unsigned long timeout = 1;
struct btrfs_transaction *cur_trans;
struct btrfs_transaction *prev_trans = NULL;
DEFINE_WAIT(wait);
trans->transaction->in_commit = 1;
trans->transaction->blocked = 1;
+ wake_up(&root->fs_info->transaction_blocked_wait);
+
if (cur_trans->list.prev != &root->fs_info->trans_list) {
prev_trans = list_entry(cur_trans->list.prev,
struct btrfs_transaction, list);
snap_pending = 1;
WARN_ON(cur_trans != trans->transaction);
- if (cur_trans->num_writers > 1)
- timeout = MAX_SCHEDULE_TIMEOUT;
- else if (should_grow)
- timeout = 1;
-
mutex_unlock(&root->fs_info->trans_mutex);
if (flush_on_commit || snap_pending) {
TASK_UNINTERRUPTIBLE);
smp_mb();
- if (cur_trans->num_writers > 1 || should_grow)
- schedule_timeout(timeout);
+ if (cur_trans->num_writers > 1)
+ schedule_timeout(MAX_SCHEDULE_TIMEOUT);
+ else if (should_grow)
+ schedule_timeout(1);
mutex_lock(&root->fs_info->trans_mutex);
finish_wait(&cur_trans->writer_wait, &wait);
int btrfs_end_transaction(struct btrfs_trans_handle *trans,
struct btrfs_root *root);
+int btrfs_end_transaction_nolock(struct btrfs_trans_handle *trans,
+ struct btrfs_root *root);
struct btrfs_trans_handle *btrfs_start_transaction(struct btrfs_root *root,
int num_items);
struct btrfs_trans_handle *btrfs_join_transaction(struct btrfs_root *root,
int num_blocks);
+struct btrfs_trans_handle *btrfs_join_transaction_nolock(struct btrfs_root *root,
+ int num_blocks);
struct btrfs_trans_handle *btrfs_start_ioctl_transaction(struct btrfs_root *r,
int num_blocks);
+int btrfs_wait_for_commit(struct btrfs_root *root, u64 transid);
int btrfs_write_and_wait_transaction(struct btrfs_trans_handle *trans,
struct btrfs_root *root);
int btrfs_commit_tree_roots(struct btrfs_trans_handle *trans,
int btrfs_clean_old_snapshots(struct btrfs_root *root);
int btrfs_commit_transaction(struct btrfs_trans_handle *trans,
struct btrfs_root *root);
+int btrfs_commit_transaction_async(struct btrfs_trans_handle *trans,
+ struct btrfs_root *root,
+ int wait_for_unblock);
int btrfs_end_transaction_throttle(struct btrfs_trans_handle *trans,
struct btrfs_root *root);
int btrfs_should_end_transaction(struct btrfs_trans_handle *trans,
int ret = 0;
int wret;
int level;
- int orig_level;
int is_extent = 0;
int next_key_ret = 0;
u64 last_ret = 0;
return -ENOMEM;
level = btrfs_header_level(root->node);
- orig_level = level;
if (level == 0)
goto out;
{
struct inode *dir;
int ret;
- struct btrfs_key location;
struct btrfs_inode_ref *ref;
struct btrfs_dir_item *di;
struct inode *inode;
unsigned long ref_ptr;
unsigned long ref_end;
- location.objectid = key->objectid;
- location.type = BTRFS_INODE_ITEM_KEY;
- location.offset = 0;
-
/*
* it is possible that we didn't log all the parent directories
* for a given inode. If we don't find the dir, just don't
struct btrfs_path *path;
struct btrfs_root *root = wc->replay_dest;
struct btrfs_key key;
- u32 item_size;
int level;
int i;
int ret;
nritems = btrfs_header_nritems(eb);
for (i = 0; i < nritems; i++) {
btrfs_item_key_to_cpu(eb, &key, i);
- item_size = btrfs_item_size_nr(eb, i);
/* inode keys are done during the first stage */
if (key.type == BTRFS_INODE_ITEM_KEY &&
struct walk_control *wc)
{
u64 root_owner;
- u64 root_gen;
u64 bytenr;
u64 ptr_gen;
struct extent_buffer *next;
parent = path->nodes[*level];
root_owner = btrfs_header_owner(parent);
- root_gen = btrfs_header_generation(parent);
next = btrfs_find_create_tree_block(root, bytenr, blocksize);
struct walk_control *wc)
{
u64 root_owner;
- u64 root_gen;
int i;
int slot;
int ret;
for (i = *level; i < BTRFS_MAX_LEVEL - 1 && path->nodes[i]; i++) {
slot = path->slots[i];
if (slot + 1 < btrfs_header_nritems(path->nodes[i])) {
- struct extent_buffer *node;
- node = path->nodes[i];
path->slots[i]++;
*level = i;
WARN_ON(*level == 0);
parent = path->nodes[*level + 1];
root_owner = btrfs_header_owner(parent);
- root_gen = btrfs_header_generation(parent);
wc->process_func(root, path->nodes[*level], wc,
btrfs_header_generation(path->nodes[*level]));
if (wc->free) {
}
btrfs_end_log_trans(root);
- return 0;
+ return err;
}
/* see comments for btrfs_del_dir_entries_in_log */
struct btrfs_key max_key;
struct btrfs_root *log = root->log_root;
struct extent_buffer *src = NULL;
- u32 size;
int err = 0;
int ret;
int nritems;
break;
src = path->nodes[0];
- size = btrfs_item_size_nr(src, path->slots[0]);
if (ins_nr && ins_start_slot + ins_nr == path->slots[0]) {
ins_nr++;
goto next_slot;
u64 size_to_free;
struct btrfs_path *path;
struct btrfs_key key;
- struct btrfs_chunk *chunk;
struct btrfs_root *chunk_root = dev_root->fs_info->chunk_root;
struct btrfs_trans_handle *trans;
struct btrfs_key found_key;
if (found_key.objectid != key.objectid)
break;
- chunk = btrfs_item_ptr(path->nodes[0],
- path->slots[0],
- struct btrfs_chunk);
/* chunk zero is special */
if (found_key.offset == 0)
break;
}
bio->bi_sector = multi->stripes[dev_nr].physical >> 9;
dev = multi->stripes[dev_nr].dev;
- BUG_ON(rw == WRITE && !dev->writeable);
- if (dev && dev->bdev) {
+ if (dev && dev->bdev && (rw != WRITE || dev->writeable)) {
bio->bi_bdev = dev->bdev;
if (async_submit)
schedule_bio(root, dev, rw, bio);
struct inode *inode = dentry->d_inode;
struct btrfs_root *root = BTRFS_I(inode)->root;
struct btrfs_path *path;
- struct btrfs_item *item;
struct extent_buffer *leaf;
struct btrfs_dir_item *di;
int ret = 0, slot, advance;
}
advance = 1;
- item = btrfs_item_nr(leaf, slot);
btrfs_item_key_to_cpu(leaf, &found_key, slot);
/* check to make sure this item is what we want */
int nr_pages = 0;
struct page *in_page = NULL;
struct page *out_page = NULL;
- int out_written = 0;
- int in_read = 0;
unsigned long bytes_left;
*out_pages = 0;
workspace->def_strm.avail_out = PAGE_CACHE_SIZE;
workspace->def_strm.avail_in = min(len, PAGE_CACHE_SIZE);
- out_written = 0;
- in_read = 0;
-
while (workspace->def_strm.total_in < len) {
ret = zlib_deflate(&workspace->def_strm, Z_SYNC_FLUSH);
if (ret != Z_OK) {
/*
* mount: join the ceph cluster, and open root directory.
*/
-static int ceph_mount(struct ceph_fs_client *fsc, struct vfsmount *mnt,
+static struct dentry *ceph_real_mount(struct ceph_fs_client *fsc,
const char *path)
{
int err;
}
}
- mnt->mnt_root = root;
- mnt->mnt_sb = fsc->sb;
-
fsc->mount_state = CEPH_MOUNT_MOUNTED;
dout("mount success\n");
- err = 0;
+ mutex_unlock(&fsc->client->mount_mutex);
+ return root;
out:
mutex_unlock(&fsc->client->mount_mutex);
- return err;
+ return ERR_PTR(err);
fail:
if (first) {
return err;
}
-static int ceph_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *ceph_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
struct super_block *sb;
struct ceph_fs_client *fsc;
+ struct dentry *res;
int err;
int (*compare_super)(struct super_block *, void *) = ceph_compare_super;
const char *path = NULL;
struct ceph_mount_options *fsopt = NULL;
struct ceph_options *opt = NULL;
- dout("ceph_get_sb\n");
+ dout("ceph_mount\n");
err = parse_mount_options(&fsopt, &opt, flags, data, dev_name, &path);
- if (err < 0)
+ if (err < 0) {
+ res = ERR_PTR(err);
goto out_final;
+ }
/* create client (which we may/may not use) */
fsc = create_fs_client(fsopt, opt);
if (IS_ERR(fsc)) {
- err = PTR_ERR(fsc);
+ res = ERR_CAST(fsc);
kfree(fsopt);
kfree(opt);
goto out_final;
}
err = ceph_mdsc_init(fsc);
- if (err < 0)
+ if (err < 0) {
+ res = ERR_PTR(err);
goto out;
+ }
if (ceph_test_opt(fsc->client, NOSHARE))
compare_super = NULL;
sb = sget(fs_type, compare_super, ceph_set_super, fsc);
if (IS_ERR(sb)) {
- err = PTR_ERR(sb);
+ res = ERR_CAST(sb);
goto out;
}
} else {
dout("get_sb using new client %p\n", fsc);
err = ceph_register_bdi(sb, fsc);
- if (err < 0)
+ if (err < 0) {
+ res = ERR_PTR(err);
goto out_splat;
+ }
}
- err = ceph_mount(fsc, mnt, path);
- if (err < 0)
+ res = ceph_real_mount(fsc, path);
+ if (IS_ERR(res))
goto out_splat;
- dout("root %p inode %p ino %llx.%llx\n", mnt->mnt_root,
- mnt->mnt_root->d_inode, ceph_vinop(mnt->mnt_root->d_inode));
- return 0;
+ dout("root %p inode %p ino %llx.%llx\n", res,
+ res->d_inode, ceph_vinop(res->d_inode));
+ return res;
out_splat:
ceph_mdsc_close_sessions(fsc->mdsc);
ceph_mdsc_destroy(fsc);
destroy_fs_client(fsc);
out_final:
- dout("ceph_get_sb fail %d\n", err);
- return err;
+ dout("ceph_mount fail %ld\n", PTR_ERR(res));
+ return res;
}
static void ceph_kill_sb(struct super_block *s)
static struct file_system_type ceph_fs_type = {
.owner = THIS_MODULE,
.name = "ceph",
- .get_sb = ceph_get_sb,
+ .mount = ceph_mount,
.kill_sb = ceph_kill_sb,
.fs_flags = FS_RENAME_DOES_D_MOVE,
};
tristate "CIFS support (advanced network filesystem, SMBFS successor)"
depends on INET
select NLS
+ select CRYPTO
+ select CRYPTO_MD5
+ select CRYPTO_ARC4
help
This is the client VFS module for the Common Internet File System
(CIFS) protocol which is the successor to the Server Message Block
unsigned char *p24);
static int cifs_calculate_signature(const struct smb_hdr *cifs_pdu,
- const struct session_key *key, char *signature)
+ struct TCP_Server_Info *server, char *signature)
{
- struct MD5Context context;
+ int rc;
- if ((cifs_pdu == NULL) || (signature == NULL) || (key == NULL))
+ if (cifs_pdu == NULL || signature == NULL || server == NULL)
return -EINVAL;
- cifs_MD5_init(&context);
- cifs_MD5_update(&context, (char *)&key->data, key->len);
- cifs_MD5_update(&context, cifs_pdu->Protocol, cifs_pdu->smb_buf_length);
+ if (!server->secmech.sdescmd5) {
+ cERROR(1, "%s: Can't generate signature\n", __func__);
+ return -1;
+ }
+
+ rc = crypto_shash_init(&server->secmech.sdescmd5->shash);
+ if (rc) {
+ cERROR(1, "%s: Oould not init md5\n", __func__);
+ return rc;
+ }
+
+ crypto_shash_update(&server->secmech.sdescmd5->shash,
+ server->session_key.response, server->session_key.len);
+
+ crypto_shash_update(&server->secmech.sdescmd5->shash,
+ cifs_pdu->Protocol, cifs_pdu->smb_buf_length);
+
+ rc = crypto_shash_final(&server->secmech.sdescmd5->shash, signature);
- cifs_MD5_final(signature, &context);
return 0;
}
server->sequence_number++;
spin_unlock(&GlobalMid_Lock);
- rc = cifs_calculate_signature(cifs_pdu, &server->session_key,
- smb_signature);
+ rc = cifs_calculate_signature(cifs_pdu, server, smb_signature);
if (rc)
memset(cifs_pdu->Signature.SecuritySignature, 0, 8);
else
}
static int cifs_calc_signature2(const struct kvec *iov, int n_vec,
- const struct session_key *key, char *signature)
+ struct TCP_Server_Info *server, char *signature)
{
- struct MD5Context context;
int i;
+ int rc;
- if ((iov == NULL) || (signature == NULL) || (key == NULL))
+ if (iov == NULL || signature == NULL || server == NULL)
return -EINVAL;
- cifs_MD5_init(&context);
- cifs_MD5_update(&context, (char *)&key->data, key->len);
+ if (!server->secmech.sdescmd5) {
+ cERROR(1, "%s: Can't generate signature\n", __func__);
+ return -1;
+ }
+
+ rc = crypto_shash_init(&server->secmech.sdescmd5->shash);
+ if (rc) {
+ cERROR(1, "%s: Oould not init md5\n", __func__);
+ return rc;
+ }
+
+ crypto_shash_update(&server->secmech.sdescmd5->shash,
+ server->session_key.response, server->session_key.len);
+
for (i = 0; i < n_vec; i++) {
if (iov[i].iov_len == 0)
continue;
if (i == 0) {
if (iov[0].iov_len <= 8) /* cmd field at offset 9 */
break; /* nothing to sign or corrupt header */
- cifs_MD5_update(&context, iov[0].iov_base+4,
- iov[0].iov_len-4);
+ crypto_shash_update(&server->secmech.sdescmd5->shash,
+ iov[i].iov_base + 4, iov[i].iov_len - 4);
} else
- cifs_MD5_update(&context, iov[i].iov_base, iov[i].iov_len);
+ crypto_shash_update(&server->secmech.sdescmd5->shash,
+ iov[i].iov_base, iov[i].iov_len);
}
- cifs_MD5_final(signature, &context);
+ rc = crypto_shash_final(&server->secmech.sdescmd5->shash, signature);
- return 0;
+ return rc;
}
-
int cifs_sign_smb2(struct kvec *iov, int n_vec, struct TCP_Server_Info *server,
__u32 *pexpected_response_sequence_number)
{
server->sequence_number++;
spin_unlock(&GlobalMid_Lock);
- rc = cifs_calc_signature2(iov, n_vec, &server->session_key,
- smb_signature);
+ rc = cifs_calc_signature2(iov, n_vec, server, smb_signature);
if (rc)
memset(cifs_pdu->Signature.SecuritySignature, 0, 8);
else
}
int cifs_verify_signature(struct smb_hdr *cifs_pdu,
- const struct session_key *session_key,
+ struct TCP_Server_Info *server,
__u32 expected_sequence_number)
{
unsigned int rc;
char server_response_sig[8];
char what_we_think_sig_should_be[20];
- if (cifs_pdu == NULL || session_key == NULL)
+ if (cifs_pdu == NULL || server == NULL)
return -EINVAL;
if (cifs_pdu->Command == SMB_COM_NEGOTIATE)
cpu_to_le32(expected_sequence_number);
cifs_pdu->Signature.Sequence.Reserved = 0;
- rc = cifs_calculate_signature(cifs_pdu, session_key,
+ rc = cifs_calculate_signature(cifs_pdu, server,
what_we_think_sig_should_be);
if (rc)
}
-/* We fill in key by putting in 40 byte array which was allocated by caller */
-int cifs_calculate_session_key(struct session_key *key, const char *rn,
- const char *password)
+/* first calculate 24 bytes ntlm response and then 16 byte session key */
+int setup_ntlm_response(struct cifsSesInfo *ses)
{
- char temp_key[16];
- if ((key == NULL) || (rn == NULL))
+ unsigned int temp_len = CIFS_SESS_KEY_SIZE + CIFS_AUTH_RESP_SIZE;
+ char temp_key[CIFS_SESS_KEY_SIZE];
+
+ if (!ses)
return -EINVAL;
- E_md4hash(password, temp_key);
- mdfour(key->data.ntlm, temp_key, 16);
- memcpy(key->data.ntlm+16, rn, CIFS_SESS_KEY_SIZE);
- key->len = 40;
+ ses->auth_key.response = kmalloc(temp_len, GFP_KERNEL);
+ if (!ses->auth_key.response) {
+ cERROR(1, "NTLM can't allocate (%u bytes) memory", temp_len);
+ return -ENOMEM;
+ }
+ ses->auth_key.len = temp_len;
+
+ SMBNTencrypt(ses->password, ses->server->cryptkey,
+ ses->auth_key.response + CIFS_SESS_KEY_SIZE);
+
+ E_md4hash(ses->password, temp_key);
+ mdfour(ses->auth_key.response, temp_key, CIFS_SESS_KEY_SIZE);
+
return 0;
}
* two times the unicode length of a server name +
* size of a timestamp (which is 8 bytes).
*/
- ses->tilen = size + 2 * (2 * dlen) + 2 * (2 * wlen) + 8;
- ses->tiblob = kzalloc(ses->tilen, GFP_KERNEL);
- if (!ses->tiblob) {
- ses->tilen = 0;
+ ses->auth_key.len = size + 2 * (2 * dlen) + 2 * (2 * wlen) + 8;
+ ses->auth_key.response = kzalloc(ses->auth_key.len, GFP_KERNEL);
+ if (!ses->auth_key.response) {
+ ses->auth_key.len = 0;
cERROR(1, "Challenge target info allocation failure");
return -ENOMEM;
}
- blobptr = ses->tiblob;
+ blobptr = ses->auth_key.response;
attrptr = (struct ntlmssp2_name *) blobptr;
attrptr->type = cpu_to_le16(NTLMSSP_AV_NB_DOMAIN_NAME);
* about target string i.e. for some, just user name might suffice.
*/
static int
-find_domain_name(struct cifsSesInfo *ses)
+find_domain_name(struct cifsSesInfo *ses, const struct nls_table *nls_cp)
{
unsigned int attrsize;
unsigned int type;
unsigned char *blobend;
struct ntlmssp2_name *attrptr;
- if (!ses->tilen || !ses->tiblob)
+ if (!ses->auth_key.len || !ses->auth_key.response)
return 0;
- blobptr = ses->tiblob;
- blobend = ses->tiblob + ses->tilen;
+ blobptr = ses->auth_key.response;
+ blobend = blobptr + ses->auth_key.len;
while (blobptr + onesize < blobend) {
attrptr = (struct ntlmssp2_name *) blobptr;
if (!attrsize)
break;
if (!ses->domainName) {
- struct nls_table *default_nls;
ses->domainName =
kmalloc(attrsize + 1, GFP_KERNEL);
if (!ses->domainName)
return -ENOMEM;
- default_nls = load_nls_default();
cifs_from_ucs2(ses->domainName,
(__le16 *)blobptr, attrsize, attrsize,
- default_nls, false);
- unload_nls(default_nls);
+ nls_cp, false);
break;
}
}
return 0;
}
-static int calc_ntlmv2_hash(struct cifsSesInfo *ses,
+static int calc_ntlmv2_hash(struct cifsSesInfo *ses, char *ntlmv2_hash,
const struct nls_table *nls_cp)
{
int rc = 0;
int len;
- char nt_hash[16];
- struct HMACMD5Context *pctxt;
+ char nt_hash[CIFS_NTHASH_SIZE];
wchar_t *user;
wchar_t *domain;
+ wchar_t *server;
- pctxt = kmalloc(sizeof(struct HMACMD5Context), GFP_KERNEL);
-
- if (pctxt == NULL)
- return -ENOMEM;
+ if (!ses->server->secmech.sdeschmacmd5) {
+ cERROR(1, "calc_ntlmv2_hash: can't generate ntlmv2 hash\n");
+ return -1;
+ }
/* calculate md4 hash of password */
E_md4hash(ses->password, nt_hash);
- /* convert Domainname to unicode and uppercase */
- hmac_md5_init_limK_to_64(nt_hash, 16, pctxt);
+ crypto_shash_setkey(ses->server->secmech.hmacmd5, nt_hash,
+ CIFS_NTHASH_SIZE);
+
+ rc = crypto_shash_init(&ses->server->secmech.sdeschmacmd5->shash);
+ if (rc) {
+ cERROR(1, "calc_ntlmv2_hash: could not init hmacmd5\n");
+ return rc;
+ }
/* convert ses->userName to unicode and uppercase */
len = strlen(ses->userName);
user = kmalloc(2 + (len * 2), GFP_KERNEL);
- if (user == NULL)
+ if (user == NULL) {
+ cERROR(1, "calc_ntlmv2_hash: user mem alloc failure\n");
+ rc = -ENOMEM;
goto calc_exit_2;
+ }
len = cifs_strtoUCS((__le16 *)user, ses->userName, len, nls_cp);
UniStrupr(user);
- hmac_md5_update((char *)user, 2*len, pctxt);
+
+ crypto_shash_update(&ses->server->secmech.sdeschmacmd5->shash,
+ (char *)user, 2 * len);
/* convert ses->domainName to unicode and uppercase */
if (ses->domainName) {
len = strlen(ses->domainName);
domain = kmalloc(2 + (len * 2), GFP_KERNEL);
- if (domain == NULL)
+ if (domain == NULL) {
+ cERROR(1, "calc_ntlmv2_hash: domain mem alloc failure");
+ rc = -ENOMEM;
goto calc_exit_1;
+ }
len = cifs_strtoUCS((__le16 *)domain, ses->domainName, len,
nls_cp);
- /* the following line was removed since it didn't work well
- with lower cased domain name that passed as an option.
- Maybe converting the domain name earlier makes sense */
- /* UniStrupr(domain); */
-
- hmac_md5_update((char *)domain, 2*len, pctxt);
-
+ crypto_shash_update(&ses->server->secmech.sdeschmacmd5->shash,
+ (char *)domain, 2 * len);
kfree(domain);
+ } else if (ses->serverName) {
+ len = strlen(ses->serverName);
+
+ server = kmalloc(2 + (len * 2), GFP_KERNEL);
+ if (server == NULL) {
+ cERROR(1, "calc_ntlmv2_hash: server mem alloc failure");
+ rc = -ENOMEM;
+ goto calc_exit_1;
+ }
+ len = cifs_strtoUCS((__le16 *)server, ses->serverName, len,
+ nls_cp);
+ crypto_shash_update(&ses->server->secmech.sdeschmacmd5->shash,
+ (char *)server, 2 * len);
+ kfree(server);
}
+
+ rc = crypto_shash_final(&ses->server->secmech.sdeschmacmd5->shash,
+ ntlmv2_hash);
+
calc_exit_1:
kfree(user);
calc_exit_2:
- /* BB FIXME what about bytes 24 through 40 of the signing key?
- compare with the NTLM example */
- hmac_md5_final(ses->ntlmv2_hash, pctxt);
+ return rc;
+}
+
+static int
+CalcNTLMv2_response(const struct cifsSesInfo *ses, char *ntlmv2_hash)
+{
+ int rc;
+ unsigned int offset = CIFS_SESS_KEY_SIZE + 8;
+
+ if (!ses->server->secmech.sdeschmacmd5) {
+ cERROR(1, "calc_ntlmv2_hash: can't generate ntlmv2 hash\n");
+ return -1;
+ }
+
+ crypto_shash_setkey(ses->server->secmech.hmacmd5,
+ ntlmv2_hash, CIFS_HMAC_MD5_HASH_SIZE);
+
+ rc = crypto_shash_init(&ses->server->secmech.sdeschmacmd5->shash);
+ if (rc) {
+ cERROR(1, "CalcNTLMv2_response: could not init hmacmd5");
+ return rc;
+ }
+
+ if (ses->server->secType == RawNTLMSSP)
+ memcpy(ses->auth_key.response + offset,
+ ses->ntlmssp->cryptkey, CIFS_SERVER_CHALLENGE_SIZE);
+ else
+ memcpy(ses->auth_key.response + offset,
+ ses->server->cryptkey, CIFS_SERVER_CHALLENGE_SIZE);
+ crypto_shash_update(&ses->server->secmech.sdeschmacmd5->shash,
+ ses->auth_key.response + offset, ses->auth_key.len - offset);
+
+ rc = crypto_shash_final(&ses->server->secmech.sdeschmacmd5->shash,
+ ses->auth_key.response + CIFS_SESS_KEY_SIZE);
- kfree(pctxt);
return rc;
}
+
int
-setup_ntlmv2_rsp(struct cifsSesInfo *ses, char *resp_buf,
- const struct nls_table *nls_cp)
+setup_ntlmv2_rsp(struct cifsSesInfo *ses, const struct nls_table *nls_cp)
{
int rc;
- struct ntlmv2_resp *buf = (struct ntlmv2_resp *)resp_buf;
- struct HMACMD5Context context;
-
- buf->blob_signature = cpu_to_le32(0x00000101);
- buf->reserved = 0;
- buf->time = cpu_to_le64(cifs_UnixTimeToNT(CURRENT_TIME));
- get_random_bytes(&buf->client_chal, sizeof(buf->client_chal));
- buf->reserved2 = 0;
+ int baselen;
+ unsigned int tilen;
+ struct ntlmv2_resp *buf;
+ char ntlmv2_hash[16];
+ unsigned char *tiblob = NULL; /* target info blob */
if (ses->server->secType == RawNTLMSSP) {
if (!ses->domainName) {
- rc = find_domain_name(ses);
+ rc = find_domain_name(ses, nls_cp);
if (rc) {
cERROR(1, "error %d finding domain name", rc);
goto setup_ntlmv2_rsp_ret;
rc = build_avpair_blob(ses, nls_cp);
if (rc) {
cERROR(1, "error %d building av pair blob", rc);
- return rc;
+ goto setup_ntlmv2_rsp_ret;
}
}
- /* calculate buf->ntlmv2_hash */
- rc = calc_ntlmv2_hash(ses, nls_cp);
+ baselen = CIFS_SESS_KEY_SIZE + sizeof(struct ntlmv2_resp);
+ tilen = ses->auth_key.len;
+ tiblob = ses->auth_key.response;
+
+ ses->auth_key.response = kmalloc(baselen + tilen, GFP_KERNEL);
+ if (!ses->auth_key.response) {
+ rc = ENOMEM;
+ ses->auth_key.len = 0;
+ cERROR(1, "%s: Can't allocate auth blob", __func__);
+ goto setup_ntlmv2_rsp_ret;
+ }
+ ses->auth_key.len += baselen;
+
+ buf = (struct ntlmv2_resp *)
+ (ses->auth_key.response + CIFS_SESS_KEY_SIZE);
+ buf->blob_signature = cpu_to_le32(0x00000101);
+ buf->reserved = 0;
+ buf->time = cpu_to_le64(cifs_UnixTimeToNT(CURRENT_TIME));
+ get_random_bytes(&buf->client_chal, sizeof(buf->client_chal));
+ buf->reserved2 = 0;
+
+ memcpy(ses->auth_key.response + baselen, tiblob, tilen);
+
+ /* calculate ntlmv2_hash */
+ rc = calc_ntlmv2_hash(ses, ntlmv2_hash, nls_cp);
if (rc) {
cERROR(1, "could not get v2 hash rc %d", rc);
goto setup_ntlmv2_rsp_ret;
}
- CalcNTLMv2_response(ses, resp_buf);
+
+ /* calculate first part of the client response (CR1) */
+ rc = CalcNTLMv2_response(ses, ntlmv2_hash);
+ if (rc) {
+ cERROR(1, "Could not calculate CR1 rc: %d", rc);
+ goto setup_ntlmv2_rsp_ret;
+ }
/* now calculate the session key for NTLMv2 */
- hmac_md5_init_limK_to_64(ses->ntlmv2_hash, 16, &context);
- hmac_md5_update(resp_buf, 16, &context);
- hmac_md5_final(ses->auth_key.data.ntlmv2.key, &context);
+ crypto_shash_setkey(ses->server->secmech.hmacmd5,
+ ntlmv2_hash, CIFS_HMAC_MD5_HASH_SIZE);
+
+ rc = crypto_shash_init(&ses->server->secmech.sdeschmacmd5->shash);
+ if (rc) {
+ cERROR(1, "%s: Could not init hmacmd5\n", __func__);
+ goto setup_ntlmv2_rsp_ret;
+ }
- memcpy(&ses->auth_key.data.ntlmv2.resp, resp_buf,
- sizeof(struct ntlmv2_resp));
- ses->auth_key.len = 16 + sizeof(struct ntlmv2_resp);
+ crypto_shash_update(&ses->server->secmech.sdeschmacmd5->shash,
+ ses->auth_key.response + CIFS_SESS_KEY_SIZE,
+ CIFS_HMAC_MD5_HASH_SIZE);
- return 0;
+ rc = crypto_shash_final(&ses->server->secmech.sdeschmacmd5->shash,
+ ses->auth_key.response);
setup_ntlmv2_rsp_ret:
- kfree(ses->tiblob);
- ses->tiblob = NULL;
- ses->tilen = 0;
+ kfree(tiblob);
return rc;
}
-void CalcNTLMv2_response(const struct cifsSesInfo *ses,
- char *v2_session_response)
+int
+calc_seckey(struct cifsSesInfo *ses)
{
- struct HMACMD5Context context;
- /* rest of v2 struct already generated */
- memcpy(v2_session_response + 8, ses->cryptKey, 8);
- hmac_md5_init_limK_to_64(ses->ntlmv2_hash, 16, &context);
+ int rc;
+ struct crypto_blkcipher *tfm_arc4;
+ struct scatterlist sgin, sgout;
+ struct blkcipher_desc desc;
+ unsigned char sec_key[CIFS_SESS_KEY_SIZE]; /* a nonce */
+
+ get_random_bytes(sec_key, CIFS_SESS_KEY_SIZE);
+
+ tfm_arc4 = crypto_alloc_blkcipher("ecb(arc4)", 0, CRYPTO_ALG_ASYNC);
+ if (!tfm_arc4 || IS_ERR(tfm_arc4)) {
+ cERROR(1, "could not allocate crypto API arc4\n");
+ return PTR_ERR(tfm_arc4);
+ }
- hmac_md5_update(v2_session_response+8,
- sizeof(struct ntlmv2_resp) - 8, &context);
+ desc.tfm = tfm_arc4;
- if (ses->tilen)
- hmac_md5_update(ses->tiblob, ses->tilen, &context);
+ crypto_blkcipher_setkey(tfm_arc4, ses->auth_key.response,
+ CIFS_SESS_KEY_SIZE);
- hmac_md5_final(v2_session_response, &context);
-/* cifs_dump_mem("v2_sess_rsp: ", v2_session_response, 32); */
+ sg_init_one(&sgin, sec_key, CIFS_SESS_KEY_SIZE);
+ sg_init_one(&sgout, ses->ntlmssp->ciphertext, CIFS_CPHTXT_SIZE);
+
+ rc = crypto_blkcipher_encrypt(&desc, &sgout, &sgin, CIFS_CPHTXT_SIZE);
+ if (rc) {
+ cERROR(1, "could not encrypt session key rc: %d\n", rc);
+ crypto_free_blkcipher(tfm_arc4);
+ return rc;
+ }
+
+ /* make secondary_key/nonce as session key */
+ memcpy(ses->auth_key.response, sec_key, CIFS_SESS_KEY_SIZE);
+ /* and make len as that of session key only */
+ ses->auth_key.len = CIFS_SESS_KEY_SIZE;
+
+ crypto_free_blkcipher(tfm_arc4);
+
+ return 0;
+}
+
+void
+cifs_crypto_shash_release(struct TCP_Server_Info *server)
+{
+ if (server->secmech.md5)
+ crypto_free_shash(server->secmech.md5);
+
+ if (server->secmech.hmacmd5)
+ crypto_free_shash(server->secmech.hmacmd5);
+
+ kfree(server->secmech.sdeschmacmd5);
+
+ kfree(server->secmech.sdescmd5);
+}
+
+int
+cifs_crypto_shash_allocate(struct TCP_Server_Info *server)
+{
+ int rc;
+ unsigned int size;
+
+ server->secmech.hmacmd5 = crypto_alloc_shash("hmac(md5)", 0, 0);
+ if (!server->secmech.hmacmd5 ||
+ IS_ERR(server->secmech.hmacmd5)) {
+ cERROR(1, "could not allocate crypto hmacmd5\n");
+ return PTR_ERR(server->secmech.hmacmd5);
+ }
+
+ server->secmech.md5 = crypto_alloc_shash("md5", 0, 0);
+ if (!server->secmech.md5 || IS_ERR(server->secmech.md5)) {
+ cERROR(1, "could not allocate crypto md5\n");
+ rc = PTR_ERR(server->secmech.md5);
+ goto crypto_allocate_md5_fail;
+ }
+
+ size = sizeof(struct shash_desc) +
+ crypto_shash_descsize(server->secmech.hmacmd5);
+ server->secmech.sdeschmacmd5 = kmalloc(size, GFP_KERNEL);
+ if (!server->secmech.sdeschmacmd5) {
+ cERROR(1, "cifs_crypto_shash_allocate: can't alloc hmacmd5\n");
+ rc = -ENOMEM;
+ goto crypto_allocate_hmacmd5_sdesc_fail;
+ }
+ server->secmech.sdeschmacmd5->shash.tfm = server->secmech.hmacmd5;
+ server->secmech.sdeschmacmd5->shash.flags = 0x0;
+
+
+ size = sizeof(struct shash_desc) +
+ crypto_shash_descsize(server->secmech.md5);
+ server->secmech.sdescmd5 = kmalloc(size, GFP_KERNEL);
+ if (!server->secmech.sdescmd5) {
+ cERROR(1, "cifs_crypto_shash_allocate: can't alloc md5\n");
+ rc = -ENOMEM;
+ goto crypto_allocate_md5_sdesc_fail;
+ }
+ server->secmech.sdescmd5->shash.tfm = server->secmech.md5;
+ server->secmech.sdescmd5->shash.flags = 0x0;
+
+ return 0;
+
+crypto_allocate_md5_sdesc_fail:
+ kfree(server->secmech.sdeschmacmd5);
+
+crypto_allocate_hmacmd5_sdesc_fail:
+ crypto_free_shash(server->secmech.md5);
+
+crypto_allocate_md5_fail:
+ crypto_free_shash(server->secmech.hmacmd5);
+
+ return rc;
}
return NULL;
cifs_inode->cifsAttrs = 0x20; /* default */
cifs_inode->time = 0;
- cifs_inode->write_behind_rc = 0;
/* Until the file is open and we have gotten oplock
info back from the server, can not assume caching of
file data or metadata */
#endif
};
-static int
-cifs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *
+cifs_do_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
int rc;
struct super_block *sb;
cFYI(1, "Devname: %s flags: %d ", dev_name, flags);
if (IS_ERR(sb))
- return PTR_ERR(sb);
+ return ERR_CAST(sb);
sb->s_flags = flags;
rc = cifs_read_super(sb, data, dev_name, flags & MS_SILENT ? 1 : 0);
if (rc) {
deactivate_locked_super(sb);
- return rc;
+ return ERR_PTR(rc);
}
sb->s_flags |= MS_ACTIVE;
- simple_set_mnt(mnt, sb);
- return 0;
+ return dget(sb->s_root);
}
static ssize_t cifs_file_aio_write(struct kiocb *iocb, const struct iovec *iov,
struct file_system_type cifs_fs_type = {
.owner = THIS_MODULE,
.name = "cifs",
- .get_sb = cifs_get_sb,
+ .mount = cifs_do_mount,
.kill_sb = kill_anon_super,
/* .fs_flags */
};
extern const struct export_operations cifs_export_ops;
#endif /* EXPERIMENTAL */
-#define CIFS_VERSION "1.67"
+#define CIFS_VERSION "1.68"
#endif /* _CIFSFS_H */
#include <linux/workqueue.h>
#include "cifs_fs_sb.h"
#include "cifsacl.h"
+#include <crypto/internal/hash.h>
+#include <linux/scatterlist.h>
+
/*
* The sizes of various internal tables and strings
*/
* CIFS vfs client Status information (based on what we know.)
*/
- /* associated with each tcp and smb session */
+/* associated with each tcp and smb session */
enum statusEnum {
CifsNew = 0,
CifsGood,
struct session_key {
unsigned int len;
- union {
- char ntlm[CIFS_SESS_KEY_SIZE + 16];
- char krb5[CIFS_SESS_KEY_SIZE + 16]; /* BB: length correct? */
- struct {
- char key[16];
- struct ntlmv2_resp resp;
- } ntlmv2;
- } data;
+ char *response;
+};
+
+/* crypto security descriptor definition */
+struct sdesc {
+ struct shash_desc shash;
+ char ctx[];
+};
+
+/* crypto hashing related structure/fields, not specific to a sec mech */
+struct cifs_secmech {
+ struct crypto_shash *hmacmd5; /* hmac-md5 hash function */
+ struct crypto_shash *md5; /* md5 hash function */
+ struct sdesc *sdeschmacmd5; /* ctxt to generate ntlmv2 hash, CR1 */
+ struct sdesc *sdescmd5; /* ctxt to generate cifs/smb signature */
+};
+
+/* per smb session structure/fields */
+struct ntlmssp_auth {
+ __u32 client_flags; /* sent by client in type 1 ntlmsssp exchange */
+ __u32 server_flags; /* sent by server in type 2 ntlmssp exchange */
+ unsigned char ciphertext[CIFS_CPHTXT_SIZE]; /* sent to server */
+ char cryptkey[CIFS_CRYPTO_KEY_SIZE]; /* used by ntlmssp */
};
struct cifs_cred {
int capabilities; /* allow selective disabling of caps by smb sess */
int timeAdj; /* Adjust for difference in server time zone in sec */
__u16 CurrentMid; /* multiplex id - rotating counter */
+ char cryptkey[CIFS_CRYPTO_KEY_SIZE]; /* used by ntlm, ntlmv2 etc */
/* 16th byte of RFC1001 workstation name is always null */
char workstation_RFC1001_name[RFC1001_NAME_LEN_WITH_NULL];
__u32 sequence_number; /* needed for CIFS PDU signature */
struct session_key session_key;
unsigned long lstrp; /* when we got last response from this server */
u16 dialect; /* dialect index that server chose */
+ struct cifs_secmech secmech; /* crypto sec mech functs, descriptors */
/* extended security flavors that server supports */
bool sec_kerberos; /* supports plain Kerberos */
bool sec_mskerberos; /* supports legacy MS Kerberos */
char userName[MAX_USERNAME_SIZE + 1];
char *domainName;
char *password;
- char cryptKey[CIFS_CRYPTO_KEY_SIZE];
struct session_key auth_key;
- char ntlmv2_hash[16];
- unsigned int tilen; /* length of the target info blob */
- unsigned char *tiblob; /* target info blob in challenge response */
+ struct ntlmssp_auth *ntlmssp; /* ciphertext, flags, server challenge */
bool need_reconnect:1; /* connection reset, uid now invalid */
};
/* no more than one of the following three session flags may be set */
struct list_head llist; /* list of byte range locks we have. */
bool invalidHandle:1; /* file closed via session abend */
bool oplock_break_cancelled:1;
- atomic_t count; /* reference count */
+ int count; /* refcount protected by cifs_file_list_lock */
struct mutex fh_mutex; /* prevents reopen race after dead ses*/
struct cifs_search_info srch_inf;
struct work_struct oplock_break; /* work for oplock breaks */
};
-/* Take a reference on the file private data */
+/*
+ * Take a reference on the file private data. Must be called with
+ * cifs_file_list_lock held.
+ */
static inline void cifsFileInfo_get(struct cifsFileInfo *cifs_file)
{
- atomic_inc(&cifs_file->count);
+ ++cifs_file->count;
}
void cifsFileInfo_put(struct cifsFileInfo *cifs_file);
struct list_head lockList;
/* BB add in lists for dirty pages i.e. write caching info for oplock */
struct list_head openFileList;
- int write_behind_rc;
__u32 cifsAttrs; /* e.g. DOS archive bit, sparse, compressed, system */
unsigned long time; /* jiffies of last update/check of inode */
bool clientCanCacheRead:1; /* read oplock */
* GlobalMid_Lock protects:
* list operations on pending_mid_q and oplockQ
* updates to XID counters, multiplex id and SMB sequence numbers
- * GlobalSMBSesLock protects:
+ * cifs_file_list_lock protects:
* list operations on tcp and SMB session lists and tCon lists
* f_owner.lock protects certain per file struct operations
* mapping->page_lock protects certain per page operations
*/
#define CIFS_CRYPTO_KEY_SIZE (8)
+/*
+ * Size of the ntlm client response
+ */
+#define CIFS_AUTH_RESP_SIZE (24)
+
/*
* Size of the session key (crypto key encrypted with the password
*/
-#define CIFS_SESS_KEY_SIZE (24)
+#define CIFS_SESS_KEY_SIZE (16)
+
+#define CIFS_CLIENT_CHALLENGE_SIZE (8)
+#define CIFS_SERVER_CHALLENGE_SIZE (8)
+#define CIFS_HMAC_MD5_HASH_SIZE (16)
+#define CIFS_CPHTXT_SIZE (16)
+#define CIFS_NTHASH_SIZE (16)
/*
* Maximum user name length
extern int cifs_sign_smb2(struct kvec *iov, int n_vec, struct TCP_Server_Info *,
__u32 *);
extern int cifs_verify_signature(struct smb_hdr *,
- const struct session_key *session_key,
+ struct TCP_Server_Info *server,
__u32 expected_sequence_number);
-extern int cifs_calculate_session_key(struct session_key *key, const char *rn,
- const char *pass);
-extern void CalcNTLMv2_response(const struct cifsSesInfo *, char *);
-extern int setup_ntlmv2_rsp(struct cifsSesInfo *, char *,
- const struct nls_table *);
+extern void SMBNTencrypt(unsigned char *, unsigned char *, unsigned char *);
+extern int setup_ntlm_response(struct cifsSesInfo *);
+extern int setup_ntlmv2_rsp(struct cifsSesInfo *, const struct nls_table *);
+extern int cifs_crypto_shash_allocate(struct TCP_Server_Info *);
+extern void cifs_crypto_shash_release(struct TCP_Server_Info *);
+extern int calc_seckey(struct cifsSesInfo *);
+
#ifdef CONFIG_CIFS_WEAK_PW_HASH
extern void calc_lanman_hash(const char *password, const char *cryptkey,
bool encrypt, char *lnm_session_key);
if (rsp->EncryptionKeyLength ==
cpu_to_le16(CIFS_CRYPTO_KEY_SIZE)) {
- memcpy(ses->cryptKey, rsp->EncryptionKey,
+ memcpy(ses->server->cryptkey, rsp->EncryptionKey,
CIFS_CRYPTO_KEY_SIZE);
} else if (server->secMode & SECMODE_PW_ENCRYPT) {
rc = -EIO; /* need cryptkey unless plain text */
server->timeAdj = (int)(__s16)le16_to_cpu(pSMBr->ServerTimeZone);
server->timeAdj *= 60;
if (pSMBr->EncryptionKeyLength == CIFS_CRYPTO_KEY_SIZE) {
- memcpy(ses->cryptKey, pSMBr->u.EncryptionKey,
+ memcpy(ses->server->cryptkey, pSMBr->u.EncryptionKey,
CIFS_CRYPTO_KEY_SIZE);
} else if ((pSMBr->hdr.Flags2 & SMBFLG2_EXT_SEC)
&& (pSMBr->EncryptionKeyLength == 0)) {
}
server->sequence_number = 0;
server->session_estab = false;
+ kfree(server->session_key.response);
+ server->session_key.response = NULL;
+ server->session_key.len = 0;
spin_lock(&GlobalMid_Lock);
list_for_each(tmp, &server->pending_mid_q) {
}
i = cifs_convert_address((struct sockaddr *)&vol->srcaddr,
value, strlen(value));
- if (i < 0) {
+ if (i == 0) {
printk(KERN_WARNING "CIFS: Could not parse"
" srcaddr: %s\n",
value);
server->tcpStatus = CifsExiting;
spin_unlock(&GlobalMid_Lock);
+ cifs_crypto_shash_release(server);
cifs_fscache_release_client_cookie(server);
+ kfree(server->session_key.response);
+ server->session_key.response = NULL;
+ server->session_key.len = 0;
+
task = xchg(&server->tsk, NULL);
if (task)
force_sig(SIGKILL, task);
goto out_err;
}
+ rc = cifs_crypto_shash_allocate(tcp_ses);
+ if (rc) {
+ cERROR(1, "could not setup hash structures rc %d", rc);
+ goto out_err;
+ }
+
tcp_ses->hostname = extract_hostname(volume_info->UNC);
if (IS_ERR(tcp_ses->hostname)) {
rc = PTR_ERR(tcp_ses->hostname);
- goto out_err;
+ goto out_err_crypto_release;
}
tcp_ses->noblocksnd = volume_info->noblocksnd;
}
if (rc < 0) {
cERROR(1, "Error connecting to socket. Aborting operation");
- goto out_err;
+ goto out_err_crypto_release;
}
/*
rc = PTR_ERR(tcp_ses->tsk);
cERROR(1, "error %d create cifsd thread", rc);
module_put(THIS_MODULE);
- goto out_err;
+ goto out_err_crypto_release;
}
/* thread spawned, put it on the list */
return tcp_ses;
+out_err_crypto_release:
+ cifs_crypto_shash_release(tcp_ses);
+
out_err:
if (tcp_ses) {
if (!IS_ERR(tcp_ses->hostname))
if (ses == NULL)
goto get_ses_fail;
- ses->tilen = 0;
- ses->tiblob = NULL;
/* new SMB session uses our server ref */
ses->server = server;
if (server->addr.sockAddr6.sin6_family == AF_INET6)
goto get_ses_fail;
}
if (volume_info->domainname) {
- int len = strlen(volume_info->domainname);
- ses->domainName = kmalloc(len + 1, GFP_KERNEL);
- if (ses->domainName)
- strcpy(ses->domainName, volume_info->domainname);
+ ses->domainName = kstrdup(volume_info->domainname, GFP_KERNEL);
+ if (!ses->domainName)
+ goto get_ses_fail;
}
ses->cred_uid = volume_info->cred_uid;
ses->linux_uid = volume_info->linux_uid;
#ifdef CONFIG_CIFS_WEAK_PW_HASH
if ((global_secflags & CIFSSEC_MAY_LANMAN) &&
(ses->server->secType == LANMAN))
- calc_lanman_hash(tcon->password, ses->cryptKey,
+ calc_lanman_hash(tcon->password, ses->server->cryptkey,
ses->server->secMode &
SECMODE_PW_ENCRYPT ? true : false,
bcc_ptr);
else
#endif /* CIFS_WEAK_PW_HASH */
- SMBNTencrypt(tcon->password, ses->cryptKey, bcc_ptr);
+ SMBNTencrypt(tcon->password, ses->server->cryptkey, bcc_ptr);
bcc_ptr += CIFS_SESS_KEY_SIZE;
if (ses->capabilities & CAP_UNICODE) {
} else {
mutex_lock(&ses->server->srv_mutex);
if (!server->session_estab) {
- memcpy(&server->session_key.data,
- &ses->auth_key.data, ses->auth_key.len);
+ server->session_key.response = ses->auth_key.response;
server->session_key.len = ses->auth_key.len;
- ses->server->session_estab = true;
+ server->sequence_number = 0x2;
+ server->session_estab = true;
+ ses->auth_key.response = NULL;
}
mutex_unlock(&server->srv_mutex);
spin_unlock(&GlobalMid_Lock);
}
+ kfree(ses->auth_key.response);
+ ses->auth_key.response = NULL;
+ ses->auth_key.len = 0;
+ kfree(ses->ntlmssp);
+ ses->ntlmssp = NULL;
+
return rc;
}
/* BB no need to lock inode until after invalidate
since namei code should already have it locked? */
rc = filemap_write_and_wait(inode->i_mapping);
- if (rc != 0)
- pCifsInode->write_behind_rc = rc;
+ mapping_set_error(inode->i_mapping, rc);
}
cFYI(1, "invalidating remote inode since open detected it "
"changed");
if (pCifsFile == NULL)
return pCifsFile;
+ pCifsFile->count = 1;
pCifsFile->netfid = fileHandle;
pCifsFile->pid = current->tgid;
pCifsFile->uid = current_fsuid();
mutex_init(&pCifsFile->fh_mutex);
mutex_init(&pCifsFile->lock_mutex);
INIT_LIST_HEAD(&pCifsFile->llist);
- atomic_set(&pCifsFile->count, 1);
INIT_WORK(&pCifsFile->oplock_break, cifs_oplock_break);
spin_lock(&cifs_file_list_lock);
/*
* Release a reference on the file private data. This may involve closing
- * the filehandle out on the server.
+ * the filehandle out on the server. Must be called without holding
+ * cifs_file_list_lock.
*/
void cifsFileInfo_put(struct cifsFileInfo *cifs_file)
{
struct cifsLockInfo *li, *tmp;
spin_lock(&cifs_file_list_lock);
- if (!atomic_dec_and_test(&cifs_file->count)) {
+ if (--cifs_file->count > 0) {
spin_unlock(&cifs_file_list_lock);
return;
}
if (can_flush) {
rc = filemap_write_and_wait(inode->i_mapping);
- if (rc != 0)
- CIFS_I(inode)->write_behind_rc = rc;
+ mapping_set_error(inode->i_mapping, rc);
pCifsInode->clientCanCacheAll = false;
pCifsInode->clientCanCacheRead = false;
if (!experimEnabled && tcon->ses->server->secMode &
(SECMODE_SIGN_REQUIRED | SECMODE_SIGN_ENABLED)) {
cifsFileInfo_put(open_file);
+ kfree(iov);
return generic_writepages(mapping, wbc);
}
cifsFileInfo_put(open_file);
if (rc || bytes_written < bytes_to_write) {
cERROR(1, "Write2 ret %d, wrote %d",
rc, bytes_written);
- /* BB what if continued retry is
- requested via mount flags? */
- if (rc == -ENOSPC)
- set_bit(AS_ENOSPC, &mapping->flags);
- else
- set_bit(AS_EIO, &mapping->flags);
+ mapping_set_error(mapping, rc);
} else {
cifs_stats_bytes_written(tcon, bytes_written);
}
rc = filemap_write_and_wait(inode->i_mapping);
if (rc == 0) {
- rc = CIFS_I(inode)->write_behind_rc;
- CIFS_I(inode)->write_behind_rc = 0;
+ struct cifs_sb_info *cifs_sb = CIFS_SB(inode->i_sb);
+
tcon = tlink_tcon(smbfile->tlink);
- if (!rc && tcon && smbfile &&
- !(CIFS_SB(inode->i_sb)->mnt_cifs_flags & CIFS_MOUNT_NOSSYNC))
+ if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_NOSSYNC))
rc = CIFSSMBFlush(xid, tcon, smbfile->netfid);
}
struct inode *inode = file->f_path.dentry->d_inode;
int rc = 0;
- /* Rather than do the steps manually:
- lock the inode for writing
- loop through pages looking for write behind data (dirty pages)
- coalesce into contiguous 16K (or smaller) chunks to write to server
- send to server (prefer in parallel)
- deal with writebehind errors
- unlock inode for writing
- filemapfdatawrite appears easier for the time being */
-
- rc = filemap_fdatawrite(inode->i_mapping);
- /* reset wb rc if we were able to write out dirty pages */
- if (!rc) {
- rc = CIFS_I(inode)->write_behind_rc;
- CIFS_I(inode)->write_behind_rc = 0;
- }
+ if (file->f_mode & FMODE_WRITE)
+ rc = filemap_write_and_wait(inode->i_mapping);
cFYI(1, "Flush inode %p file %p rc %d", inode, file, rc);
oplock_break);
struct inode *inode = cfile->dentry->d_inode;
struct cifsInodeInfo *cinode = CIFS_I(inode);
- int rc, waitrc = 0;
+ int rc = 0;
if (inode && S_ISREG(inode->i_mode)) {
if (cinode->clientCanCacheRead)
break_lease(inode, O_WRONLY);
rc = filemap_fdatawrite(inode->i_mapping);
if (cinode->clientCanCacheRead == 0) {
- waitrc = filemap_fdatawait(inode->i_mapping);
+ rc = filemap_fdatawait(inode->i_mapping);
+ mapping_set_error(inode->i_mapping, rc);
invalidate_remote_inode(inode);
}
- if (!rc)
- rc = waitrc;
- if (rc)
- cinode->write_behind_rc = rc;
cFYI(1, "Oplock flush inode %p rc %d", inode, rc);
}
/*
* We might have kicked in before is_valid_oplock_break()
* finished grabbing reference for us. Make sure it's done by
- * waiting for GlobalSMSSeslock.
+ * waiting for cifs_file_list_lock.
*/
spin_lock(&cifs_file_list_lock);
spin_unlock(&cifs_file_list_lock);
cifs_oplock_break_put(cfile);
}
+/* must be called while holding cifs_file_list_lock */
void cifs_oplock_break_get(struct cifsFileInfo *cfile)
{
cifs_sb_active(cfile->dentry->d_sb);
/* write back any cached data */
if (inode->i_mapping && inode->i_mapping->nrpages != 0) {
rc = filemap_write_and_wait(inode->i_mapping);
- if (rc)
- cifs_i->write_behind_rc = rc;
+ mapping_set_error(inode->i_mapping, rc);
}
invalidate_remote_inode(inode);
cifs_fscache_reset_inode_cookie(inode);
* the flush returns error?
*/
rc = filemap_write_and_wait(inode->i_mapping);
- if (rc != 0) {
- cifsInode->write_behind_rc = rc;
- rc = 0;
- }
+ mapping_set_error(inode->i_mapping, rc);
+ rc = 0;
if (attrs->ia_valid & ATTR_SIZE) {
rc = cifs_set_file_size(inode, attrs, xid, full_path);
* the flush returns error?
*/
rc = filemap_write_and_wait(inode->i_mapping);
- if (rc != 0) {
- cifsInode->write_behind_rc = rc;
- rc = 0;
- }
+ mapping_set_error(inode->i_mapping, rc);
+ rc = 0;
if (attrs->ia_valid & ATTR_SIZE) {
rc = cifs_set_file_size(inode, attrs, xid, full_path);
* cifs_oplock_break_put() can't be called
* from here. Get reference after queueing
* succeeded. cifs_oplock_break() will
- * synchronize using GlobalSMSSeslock.
+ * synchronize using cifs_file_list_lock.
*/
if (queue_work(system_nrt_wq,
&netfile->oplock_break))
#include <linux/slab.h>
#include "cifs_spnego.h"
-extern void SMBNTencrypt(unsigned char *passwd, unsigned char *c8,
- unsigned char *p24);
-
/*
* Checks if this is the first smb session to be reconnected after
* the socket has been reestablished (so we know whether to use vc 0).
return -EINVAL;
}
- memcpy(ses->cryptKey, pblob->Challenge, CIFS_CRYPTO_KEY_SIZE);
+ memcpy(ses->ntlmssp->cryptkey, pblob->Challenge, CIFS_CRYPTO_KEY_SIZE);
/* BB we could decode pblob->NegotiateFlags; some may be useful */
/* In particular we can examine sign flags */
/* BB spec says that if AvId field of MsvAvTimestamp is populated then
we must set the MIC field of the AUTHENTICATE_MESSAGE */
-
+ ses->ntlmssp->server_flags = le32_to_cpu(pblob->NegotiateFlags);
tioffset = cpu_to_le16(pblob->TargetInfoArray.BufferOffset);
tilen = cpu_to_le16(pblob->TargetInfoArray.Length);
- ses->tilen = tilen;
- if (ses->tilen) {
- ses->tiblob = kmalloc(tilen, GFP_KERNEL);
- if (!ses->tiblob) {
+ if (tilen) {
+ ses->auth_key.response = kmalloc(tilen, GFP_KERNEL);
+ if (!ses->auth_key.response) {
cERROR(1, "Challenge target info allocation failure");
- ses->tilen = 0;
return -ENOMEM;
}
- memcpy(ses->tiblob, bcc_ptr + tioffset, ses->tilen);
+ memcpy(ses->auth_key.response, bcc_ptr + tioffset, tilen);
+ ses->auth_key.len = tilen;
}
return 0;
NTLMSSP_NEGOTIATE_128 | NTLMSSP_NEGOTIATE_UNICODE |
NTLMSSP_NEGOTIATE_NTLM;
if (ses->server->secMode &
- (SECMODE_SIGN_REQUIRED | SECMODE_SIGN_ENABLED))
+ (SECMODE_SIGN_REQUIRED | SECMODE_SIGN_ENABLED)) {
flags |= NTLMSSP_NEGOTIATE_SIGN;
- if (ses->server->secMode & SECMODE_SIGN_REQUIRED)
- flags |= NTLMSSP_NEGOTIATE_ALWAYS_SIGN;
+ if (!ses->server->session_estab)
+ flags |= NTLMSSP_NEGOTIATE_KEY_XCH |
+ NTLMSSP_NEGOTIATE_EXTENDED_SEC;
+ }
sec_blob->NegotiateFlags |= cpu_to_le32(flags);
const struct nls_table *nls_cp)
{
int rc;
- unsigned int size;
AUTHENTICATE_MESSAGE *sec_blob = (AUTHENTICATE_MESSAGE *)pbuffer;
__u32 flags;
unsigned char *tmp;
- struct ntlmv2_resp ntlmv2_response = {};
memcpy(sec_blob->Signature, NTLMSSP_SIGNATURE, 8);
sec_blob->MessageType = NtLmAuthenticate;
sec_blob->LmChallengeResponse.MaximumLength = 0;
sec_blob->NtChallengeResponse.BufferOffset = cpu_to_le32(tmp - pbuffer);
- rc = setup_ntlmv2_rsp(ses, (char *)&ntlmv2_response, nls_cp);
+ rc = setup_ntlmv2_rsp(ses, nls_cp);
if (rc) {
cERROR(1, "Error %d during NTLMSSP authentication", rc);
goto setup_ntlmv2_ret;
}
- size = sizeof(struct ntlmv2_resp);
- memcpy(tmp, (char *)&ntlmv2_response, size);
- tmp += size;
- if (ses->tilen > 0) {
- memcpy(tmp, ses->tiblob, ses->tilen);
- tmp += ses->tilen;
- }
+ memcpy(tmp, ses->auth_key.response + CIFS_SESS_KEY_SIZE,
+ ses->auth_key.len - CIFS_SESS_KEY_SIZE);
+ tmp += ses->auth_key.len - CIFS_SESS_KEY_SIZE;
- sec_blob->NtChallengeResponse.Length = cpu_to_le16(size + ses->tilen);
+ sec_blob->NtChallengeResponse.Length =
+ cpu_to_le16(ses->auth_key.len - CIFS_SESS_KEY_SIZE);
sec_blob->NtChallengeResponse.MaximumLength =
- cpu_to_le16(size + ses->tilen);
- kfree(ses->tiblob);
- ses->tiblob = NULL;
- ses->tilen = 0;
+ cpu_to_le16(ses->auth_key.len - CIFS_SESS_KEY_SIZE);
if (ses->domainName == NULL) {
sec_blob->DomainName.BufferOffset = cpu_to_le32(tmp - pbuffer);
sec_blob->WorkstationName.MaximumLength = 0;
tmp += 2;
- sec_blob->SessionKey.BufferOffset = cpu_to_le32(tmp - pbuffer);
- sec_blob->SessionKey.Length = 0;
- sec_blob->SessionKey.MaximumLength = 0;
+ if ((ses->ntlmssp->server_flags & NTLMSSP_NEGOTIATE_KEY_XCH) &&
+ !calc_seckey(ses)) {
+ memcpy(tmp, ses->ntlmssp->ciphertext, CIFS_CPHTXT_SIZE);
+ sec_blob->SessionKey.BufferOffset = cpu_to_le32(tmp - pbuffer);
+ sec_blob->SessionKey.Length = cpu_to_le16(CIFS_CPHTXT_SIZE);
+ sec_blob->SessionKey.MaximumLength =
+ cpu_to_le16(CIFS_CPHTXT_SIZE);
+ tmp += CIFS_CPHTXT_SIZE;
+ } else {
+ sec_blob->SessionKey.BufferOffset = cpu_to_le32(tmp - pbuffer);
+ sec_blob->SessionKey.Length = 0;
+ sec_blob->SessionKey.MaximumLength = 0;
+ }
setup_ntlmv2_ret:
*buflen = tmp - pbuffer;
return -EINVAL;
type = ses->server->secType;
-
cFYI(1, "sess setup type %d", type);
+ if (type == RawNTLMSSP) {
+ /* if memory allocation is successful, caller of this function
+ * frees it.
+ */
+ ses->ntlmssp = kmalloc(sizeof(struct ntlmssp_auth), GFP_KERNEL);
+ if (!ses->ntlmssp)
+ return -ENOMEM;
+ }
+
ssetup_ntlmssp_authenticate:
if (phase == NtLmChallenge)
phase = NtLmAuthenticate; /* if ntlmssp, now final phase */
/* no capabilities flags in old lanman negotiation */
pSMB->old_req.PasswordLength = cpu_to_le16(CIFS_SESS_KEY_SIZE);
- /* BB calculate hash with password */
- /* and copy into bcc */
- calc_lanman_hash(ses->password, ses->cryptKey,
+ /* Calculate hash with password and copy into bcc_ptr.
+ * Encryption Key (stored as in cryptkey) gets used if the
+ * security mode bit in Negottiate Protocol response states
+ * to use challenge/response method (i.e. Password bit is 1).
+ */
+
+ calc_lanman_hash(ses->password, ses->server->cryptkey,
ses->server->secMode & SECMODE_PW_ENCRYPT ?
true : false, lnm_session_key);
ascii_ssetup_strings(&bcc_ptr, ses, nls_cp);
#endif
} else if (type == NTLM) {
- char ntlm_session_key[CIFS_SESS_KEY_SIZE];
-
pSMB->req_no_secext.Capabilities = cpu_to_le32(capabilities);
pSMB->req_no_secext.CaseInsensitivePasswordLength =
- cpu_to_le16(CIFS_SESS_KEY_SIZE);
+ cpu_to_le16(CIFS_AUTH_RESP_SIZE);
pSMB->req_no_secext.CaseSensitivePasswordLength =
- cpu_to_le16(CIFS_SESS_KEY_SIZE);
+ cpu_to_le16(CIFS_AUTH_RESP_SIZE);
+
+ /* calculate ntlm response and session key */
+ rc = setup_ntlm_response(ses);
+ if (rc) {
+ cERROR(1, "Error %d during NTLM authentication", rc);
+ goto ssetup_exit;
+ }
- /* calculate session key */
- SMBNTencrypt(ses->password, ses->cryptKey, ntlm_session_key);
+ /* copy ntlm response */
+ memcpy(bcc_ptr, ses->auth_key.response + CIFS_SESS_KEY_SIZE,
+ CIFS_AUTH_RESP_SIZE);
+ bcc_ptr += CIFS_AUTH_RESP_SIZE;
+ memcpy(bcc_ptr, ses->auth_key.response + CIFS_SESS_KEY_SIZE,
+ CIFS_AUTH_RESP_SIZE);
+ bcc_ptr += CIFS_AUTH_RESP_SIZE;
- cifs_calculate_session_key(&ses->auth_key,
- ntlm_session_key, ses->password);
- /* copy session key */
- memcpy(bcc_ptr, (char *)ntlm_session_key, CIFS_SESS_KEY_SIZE);
- bcc_ptr += CIFS_SESS_KEY_SIZE;
- memcpy(bcc_ptr, (char *)ntlm_session_key, CIFS_SESS_KEY_SIZE);
- bcc_ptr += CIFS_SESS_KEY_SIZE;
if (ses->capabilities & CAP_UNICODE) {
/* unicode strings must be word aligned */
if (iov[0].iov_len % 2) {
} else
ascii_ssetup_strings(&bcc_ptr, ses, nls_cp);
} else if (type == NTLMv2) {
- char *v2_sess_key =
- kmalloc(sizeof(struct ntlmv2_resp), GFP_KERNEL);
-
- /* BB FIXME change all users of v2_sess_key to
- struct ntlmv2_resp */
-
- if (v2_sess_key == NULL) {
- rc = -ENOMEM;
- goto ssetup_exit;
- }
-
pSMB->req_no_secext.Capabilities = cpu_to_le32(capabilities);
/* LM2 password would be here if we supported it */
pSMB->req_no_secext.CaseInsensitivePasswordLength = 0;
- /* cpu_to_le16(LM2_SESS_KEY_SIZE); */
- /* calculate session key */
- rc = setup_ntlmv2_rsp(ses, v2_sess_key, nls_cp);
+ /* calculate nlmv2 response and session key */
+ rc = setup_ntlmv2_rsp(ses, nls_cp);
if (rc) {
cERROR(1, "Error %d during NTLMv2 authentication", rc);
- kfree(v2_sess_key);
goto ssetup_exit;
}
- memcpy(bcc_ptr, (char *)v2_sess_key,
- sizeof(struct ntlmv2_resp));
- bcc_ptr += sizeof(struct ntlmv2_resp);
- kfree(v2_sess_key);
+ memcpy(bcc_ptr, ses->auth_key.response + CIFS_SESS_KEY_SIZE,
+ ses->auth_key.len - CIFS_SESS_KEY_SIZE);
+ bcc_ptr += ses->auth_key.len - CIFS_SESS_KEY_SIZE;
+
/* set case sensitive password length after tilen may get
* assigned, tilen is 0 otherwise.
*/
pSMB->req_no_secext.CaseSensitivePasswordLength =
- cpu_to_le16(sizeof(struct ntlmv2_resp) + ses->tilen);
- if (ses->tilen > 0) {
- memcpy(bcc_ptr, ses->tiblob, ses->tilen);
- bcc_ptr += ses->tilen;
- /* we never did allocate ses->domainName to free */
- kfree(ses->tiblob);
- ses->tiblob = NULL;
- ses->tilen = 0;
- }
+ cpu_to_le16(ses->auth_key.len - CIFS_SESS_KEY_SIZE);
if (ses->capabilities & CAP_UNICODE) {
if (iov[0].iov_len % 2) {
} else if (type == Kerberos) {
#ifdef CONFIG_CIFS_UPCALL
struct cifs_spnego_msg *msg;
+
spnego_key = cifs_get_spnego_key(ses);
if (IS_ERR(spnego_key)) {
rc = PTR_ERR(spnego_key);
rc = -EKEYREJECTED;
goto ssetup_exit;
}
- /* bail out if key is too long */
- if (msg->sesskey_len >
- sizeof(ses->auth_key.data.krb5)) {
- cERROR(1, "Kerberos signing key too long (%u bytes)",
- msg->sesskey_len);
- rc = -EOVERFLOW;
+
+ ses->auth_key.response = kmalloc(msg->sesskey_len, GFP_KERNEL);
+ if (!ses->auth_key.response) {
+ cERROR(1, "Kerberos can't allocate (%u bytes) memory",
+ msg->sesskey_len);
+ rc = -ENOMEM;
goto ssetup_exit;
}
+ memcpy(ses->auth_key.response, msg->data, msg->sesskey_len);
ses->auth_key.len = msg->sesskey_len;
- memcpy(ses->auth_key.data.krb5, msg->data, msg->sesskey_len);
+
pSMB->req.hdr.Flags2 |= SMBFLG2_EXT_SEC;
capabilities |= CAP_EXTENDED_SECURITY;
pSMB->req.Capabilities = cpu_to_le32(capabilities);
CIFS_STD_OP /* not long */ | CIFS_LOG_ERROR);
/* SMB request buf freed in SendReceive2 */
- cFYI(1, "ssetup rc from sendrecv2 is %d", rc);
-
pSMB = (SESSION_SETUP_ANDX *)iov[0].iov_base;
smb_buf = (struct smb_hdr *)iov[0].iov_base;
(ses->server->secMode & (SECMODE_SIGN_REQUIRED |
SECMODE_SIGN_ENABLED))) {
rc = cifs_verify_signature(midQ->resp_buf,
- &ses->server->session_key,
+ ses->server,
midQ->sequence_number+1);
if (rc) {
cERROR(1, "Unexpected SMB signature");
(ses->server->secMode & (SECMODE_SIGN_REQUIRED |
SECMODE_SIGN_ENABLED))) {
rc = cifs_verify_signature(out_buf,
- &ses->server->session_key,
+ ses->server,
midQ->sequence_number+1);
if (rc) {
cERROR(1, "Unexpected SMB signature");
(ses->server->secMode & (SECMODE_SIGN_REQUIRED |
SECMODE_SIGN_ENABLED))) {
rc = cifs_verify_signature(out_buf,
- &ses->server->session_key,
+ ses->server,
midQ->sequence_number+1);
if (rc) {
cERROR(1, "Unexpected SMB signature");
/* init_coda: used by filesystems.c to register coda */
-static int coda_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *coda_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, coda_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, coda_fill_super);
}
struct file_system_type coda_fs_type = {
.owner = THIS_MODULE,
.name = "coda",
- .get_sb = coda_get_sb,
+ .mount = coda_mount,
.kill_sb = kill_anon_super,
.fs_flags = FS_BINARY_MOUNTDATA,
};
#include <linux/eventpoll.h>
#include <linux/fs_struct.h>
#include <linux/slab.h>
+#include <linux/pagemap.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
/*
* Single unix specification:
* We should -EINVAL if an element length is not >= 0 and fitting an
- * ssize_t. The total length is fitting an ssize_t
+ * ssize_t.
*
- * Be careful here because iov_len is a size_t not an ssize_t
+ * In Linux, the total length is limited to MAX_RW_COUNT, there is
+ * no overflow possibility.
*/
tot_len = 0;
ret = -EINVAL;
for (seg = 0; seg < nr_segs; seg++) {
- compat_ssize_t tmp = tot_len;
compat_uptr_t buf;
compat_ssize_t len;
}
if (len < 0) /* size_t not fitting in compat_ssize_t .. */
goto out;
- tot_len += len;
- if (tot_len < tmp) /* maths overflow on the compat_ssize_t */
- goto out;
if (!access_ok(vrfy_dir(type), compat_ptr(buf), len)) {
ret = -EFAULT;
goto out;
}
+ if (len > MAX_RW_COUNT - tot_len)
+ len = MAX_RW_COUNT - tot_len;
+ tot_len += len;
iov->iov_base = compat_ptr(buf);
iov->iov_len = (compat_size_t) len;
uvector++;
return 0;
}
-static int configfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *configfs_do_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, configfs_fill_super, mnt);
+ return mount_single(fs_type, flags, data, configfs_fill_super);
}
static struct file_system_type configfs_fs_type = {
.owner = THIS_MODULE,
.name = "configfs",
- .get_sb = configfs_get_sb,
+ .mount = configfs_do_mount,
.kill_sb = kill_litter_super,
};
.statfs = cramfs_statfs,
};
-static int cramfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *cramfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, cramfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, cramfs_fill_super);
}
static struct file_system_type cramfs_fs_type = {
.owner = THIS_MODULE,
.name = "cramfs",
- .get_sb = cramfs_get_sb,
+ .mount = cramfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return simple_fill_super(sb, DEBUGFS_MAGIC, debug_files);
}
-static int debug_get_sb(struct file_system_type *fs_type,
+static struct dentry *debug_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_single(fs_type, flags, data, debug_fill_super, mnt);
+ return mount_single(fs_type, flags, data, debug_fill_super);
}
static struct file_system_type debug_fs_type = {
.owner = THIS_MODULE,
.name = "debugfs",
- .get_sb = debug_get_sb,
+ .mount = debug_mount,
.kill_sb = kill_litter_super,
};
}
/*
- * devpts_get_sb()
+ * devpts_mount()
*
* If the '-o newinstance' mount option was specified, mount a new
* (private) instance of devpts. PTYs created in this instance are
* semantics in devpts while preserving backward compatibility of the
* current 'single-namespace' semantics. i.e all mounts of devpts
* without the 'newinstance' mount option should bind to the initial
- * kernel mount, like get_sb_single().
+ * kernel mount, like mount_single().
*
* Mounts with 'newinstance' option create a new, private namespace.
*
* NOTE:
*
- * For single-mount semantics, devpts cannot use get_sb_single(),
- * because get_sb_single()/sget() find and use the super-block from
+ * For single-mount semantics, devpts cannot use mount_single(),
+ * because mount_single()/sget() find and use the super-block from
* the most recent mount of devpts. But that recent mount may be a
- * 'newinstance' mount and get_sb_single() would pick the newinstance
+ * 'newinstance' mount and mount_single() would pick the newinstance
* super-block instead of the initial super-block.
*/
-static int devpts_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *devpts_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
int error;
struct pts_mount_opts opts;
error = parse_mount_options(data, PARSE_MOUNT, &opts);
if (error)
- return error;
+ return ERR_PTR(error);
if (opts.newinstance)
s = sget(fs_type, NULL, set_anon_super, NULL);
s = sget(fs_type, compare_init_pts_sb, set_anon_super, NULL);
if (IS_ERR(s))
- return PTR_ERR(s);
+ return ERR_CAST(s);
if (!s->s_root) {
s->s_flags = flags;
if (error)
goto out_undo_sget;
- simple_set_mnt(mnt, s);
-
- return 0;
+ return dget(s->s_root);
out_undo_sget:
deactivate_locked_super(s);
- return error;
+ return ERR_PTR(error);
}
#else
* This supports only the legacy single-instance semantics (no
* multiple-instance semantics)
*/
-static int devpts_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *devpts_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, devpts_fill_super, mnt);
+ return mount_single(fs_type, flags, data, devpts_fill_super);
}
#endif
static struct file_system_type devpts_fs_type = {
.name = "devpts",
- .get_sb = devpts_get_sb,
+ .mount = devpts_mount,
.kill_sb = devpts_kill_sb,
};
#define ECRYPTFS_GLOBAL_ENCRYPT_FILENAMES 0x00000010
#define ECRYPTFS_GLOBAL_ENCFN_USE_MOUNT_FNEK 0x00000020
#define ECRYPTFS_GLOBAL_ENCFN_USE_FEK 0x00000040
+#define ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY 0x00000080
u32 flags;
struct list_head global_auth_tok_list;
struct mutex global_auth_tok_list_mutex;
#include <linux/crypto.h>
#include <linux/fs_stack.h>
#include <linux/slab.h>
+#include <linux/xattr.h>
#include <asm/unaligned.h>
#include "ecryptfs_kernel.h"
struct vfsmount *lower_mnt = ecryptfs_dentry_to_lower_mnt(dentry);
struct dentry *dentry_save;
struct vfsmount *vfsmount_save;
+ unsigned int flags_save;
int rc;
dentry_save = nd->path.dentry;
vfsmount_save = nd->path.mnt;
+ flags_save = nd->flags;
nd->path.dentry = lower_dentry;
nd->path.mnt = lower_mnt;
+ nd->flags &= ~LOOKUP_OPEN;
rc = vfs_create(lower_dir_inode, lower_dentry, mode, nd);
nd->path.dentry = dentry_save;
nd->path.mnt = vfsmount_save;
+ nd->flags = flags_save;
return rc;
}
rc = -EOPNOTSUPP;
goto out;
}
- mutex_lock(&lower_dentry->d_inode->i_mutex);
- rc = lower_dentry->d_inode->i_op->setxattr(lower_dentry, name, value,
- size, flags);
- mutex_unlock(&lower_dentry->d_inode->i_mutex);
+
+ rc = vfs_setxattr(lower_dentry, name, value, size, flags);
out:
return rc;
}
*/
static int
ecryptfs_find_auth_tok_for_sig(
+ struct key **auth_tok_key,
struct ecryptfs_auth_tok **auth_tok,
struct ecryptfs_mount_crypt_stat *mount_crypt_stat,
char *sig)
struct ecryptfs_global_auth_tok *global_auth_tok;
int rc = 0;
+ (*auth_tok_key) = NULL;
(*auth_tok) = NULL;
if (ecryptfs_find_global_auth_tok_for_sig(&global_auth_tok,
mount_crypt_stat, sig)) {
- struct key *auth_tok_key;
- rc = ecryptfs_keyring_auth_tok_for_sig(&auth_tok_key, auth_tok,
+ /* if the flag ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY is set in the
+ * mount_crypt_stat structure, we prevent to use auth toks that
+ * are not inserted through the ecryptfs_add_global_auth_tok
+ * function.
+ */
+ if (mount_crypt_stat->flags
+ & ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY)
+ return -EINVAL;
+
+ rc = ecryptfs_keyring_auth_tok_for_sig(auth_tok_key, auth_tok,
sig);
} else
(*auth_tok) = global_auth_tok->global_auth_tok;
char *filename, size_t filename_size)
{
struct ecryptfs_write_tag_70_packet_silly_stack *s;
+ struct key *auth_tok_key = NULL;
int rc = 0;
s = kmalloc(sizeof(*s), GFP_KERNEL);
}
dest[s->i++] = s->cipher_code;
rc = ecryptfs_find_auth_tok_for_sig(
+ &auth_tok_key,
&s->auth_tok, mount_crypt_stat,
mount_crypt_stat->global_default_fnek_sig);
if (rc) {
out_unlock:
mutex_unlock(s->tfm_mutex);
out:
+ if (auth_tok_key)
+ key_put(auth_tok_key);
kfree(s);
return rc;
}
char *data, size_t max_packet_size)
{
struct ecryptfs_parse_tag_70_packet_silly_stack *s;
+ struct key *auth_tok_key = NULL;
int rc = 0;
(*packet_size) = 0;
* >= ECRYPTFS_MAX_IV_BYTES. */
memset(s->iv, 0, ECRYPTFS_MAX_IV_BYTES);
s->desc.info = s->iv;
- rc = ecryptfs_find_auth_tok_for_sig(&s->auth_tok, mount_crypt_stat,
+ rc = ecryptfs_find_auth_tok_for_sig(&auth_tok_key,
+ &s->auth_tok, mount_crypt_stat,
s->fnek_sig_hex);
if (rc) {
printk(KERN_ERR "%s: Error attempting to find auth tok for "
(*filename_size) = 0;
(*filename) = NULL;
}
+ if (auth_tok_key)
+ key_put(auth_tok_key);
kfree(s);
return rc;
}
ECRYPTFS_VERSION_MAJOR,
ECRYPTFS_VERSION_MINOR);
rc = -EINVAL;
- goto out;
+ goto out_release_key;
}
if ((*auth_tok)->token_type != ECRYPTFS_PASSWORD
&& (*auth_tok)->token_type != ECRYPTFS_PRIVATE_KEY) {
printk(KERN_ERR "Invalid auth_tok structure "
"returned from key query\n");
rc = -EINVAL;
- goto out;
+ goto out_release_key;
+ }
+out_release_key:
+ if (rc) {
+ key_put(*auth_tok_key);
+ (*auth_tok_key) = NULL;
}
out:
return rc;
struct ecryptfs_auth_tok_list_item *auth_tok_list_item;
size_t tag_11_contents_size;
size_t tag_11_packet_size;
+ struct key *auth_tok_key = NULL;
int rc = 0;
INIT_LIST_HEAD(&auth_tok_list);
* just one will be sufficient to decrypt to get the FEK. */
find_next_matching_auth_tok:
found_auth_tok = 0;
+ if (auth_tok_key) {
+ key_put(auth_tok_key);
+ auth_tok_key = NULL;
+ }
list_for_each_entry(auth_tok_list_item, &auth_tok_list, list) {
candidate_auth_tok = &auth_tok_list_item->auth_tok;
if (unlikely(ecryptfs_verbosity > 0)) {
rc = -EINVAL;
goto out_wipe_list;
}
- ecryptfs_find_auth_tok_for_sig(&matching_auth_tok,
+ rc = ecryptfs_find_auth_tok_for_sig(&auth_tok_key,
+ &matching_auth_tok,
crypt_stat->mount_crypt_stat,
candidate_auth_tok_sig);
- if (matching_auth_tok) {
+ if (!rc) {
found_auth_tok = 1;
goto found_matching_auth_tok;
}
out_wipe_list:
wipe_auth_tok_list(&auth_tok_list);
out:
+ if (auth_tok_key)
+ key_put(auth_tok_key);
return rc;
}
ecryptfs_opt_passthrough, ecryptfs_opt_xattr_metadata,
ecryptfs_opt_encrypted_view, ecryptfs_opt_fnek_sig,
ecryptfs_opt_fn_cipher, ecryptfs_opt_fn_cipher_key_bytes,
- ecryptfs_opt_unlink_sigs, ecryptfs_opt_err };
+ ecryptfs_opt_unlink_sigs, ecryptfs_opt_mount_auth_tok_only,
+ ecryptfs_opt_err };
static const match_table_t tokens = {
{ecryptfs_opt_sig, "sig=%s"},
{ecryptfs_opt_fn_cipher, "ecryptfs_fn_cipher=%s"},
{ecryptfs_opt_fn_cipher_key_bytes, "ecryptfs_fn_key_bytes=%u"},
{ecryptfs_opt_unlink_sigs, "ecryptfs_unlink_sigs"},
+ {ecryptfs_opt_mount_auth_tok_only, "ecryptfs_mount_auth_tok_only"},
{ecryptfs_opt_err, NULL}
};
case ecryptfs_opt_unlink_sigs:
mount_crypt_stat->flags |= ECRYPTFS_UNLINK_SIGS;
break;
+ case ecryptfs_opt_mount_auth_tok_only:
+ mount_crypt_stat->flags |=
+ ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY;
+ break;
case ecryptfs_opt_err:
default:
printk(KERN_WARNING
* ecryptfs_interpose to perform most of the linking
* ecryptfs_interpose(): links the lower filesystem into ecryptfs (inode.c)
*/
-static int ecryptfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *raw_data,
- struct vfsmount *mnt)
+static struct dentry *ecryptfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *raw_data)
{
struct super_block *s;
struct ecryptfs_sb_info *sbi;
err = "Reading sb failed";
goto out;
}
- simple_set_mnt(mnt, s);
- return 0;
+ return dget(s->s_root);
out:
if (sbi) {
kmem_cache_free(ecryptfs_sb_info_cache, sbi);
}
printk(KERN_ERR "%s; rc = [%d]\n", err, rc);
- return rc;
+ return ERR_PTR(rc);
}
/**
static struct file_system_type ecryptfs_fs_type = {
.owner = THIS_MODULE,
.name = "ecryptfs",
- .get_sb = ecryptfs_get_sb,
+ .mount = ecryptfs_mount,
.kill_sb = ecryptfs_kill_block_super,
.fs_flags = 0
};
seq_printf(m, ",ecryptfs_encrypted_view");
if (mount_crypt_stat->flags & ECRYPTFS_UNLINK_SIGS)
seq_printf(m, ",ecryptfs_unlink_sigs");
+ if (mount_crypt_stat->flags & ECRYPTFS_GLOBAL_MOUNT_AUTH_TOK_ONLY)
+ seq_printf(m, ",ecryptfs_mount_auth_tok_only");
return 0;
}
static int efs_statfs(struct dentry *dentry, struct kstatfs *buf);
static int efs_fill_super(struct super_block *s, void *d, int silent);
-static int efs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *efs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, efs_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, efs_fill_super);
}
static struct file_system_type efs_fs_type = {
.owner = THIS_MODULE,
.name = "efs",
- .get_sb = efs_get_sb,
+ .mount = efs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
/*
* Set up the superblock (calls exofs_fill_super eventually)
*/
-static int exofs_get_sb(struct file_system_type *type,
+static struct dentry *exofs_mount(struct file_system_type *type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
struct exofs_mountopt opts;
int ret;
ret = parse_options(data, &opts);
if (ret)
- return ret;
+ return ERR_PTR(ret);
opts.dev_name = dev_name;
- return get_sb_nodev(type, flags, &opts, exofs_fill_super, mnt);
+ return mount_nodev(type, flags, &opts, exofs_fill_super);
}
/*
static struct file_system_type exofs_type = {
.owner = THIS_MODULE,
.name = "exofs",
- .get_sb = exofs_get_sb,
+ .mount = exofs_mount,
.kill_sb = generic_shutdown_super,
};
return 0;
}
-static int ext2_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ext2_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ext2_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ext2_fill_super);
}
#ifdef CONFIG_QUOTA
static struct file_system_type ext2_fs_type = {
.owner = THIS_MODULE,
.name = "ext2",
- .get_sb = ext2_get_sb,
+ .mount = ext2_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
#endif
-static int ext3_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ext3_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ext3_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ext3_fill_super);
}
static struct file_system_type ext3_fs_type = {
.owner = THIS_MODULE,
.name = "ext3",
- .get_sb = ext3_get_sb,
+ .mount = ext3_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
static int ext4_unfreeze(struct super_block *sb);
static void ext4_write_super(struct super_block *sb);
static int ext4_freeze(struct super_block *sb);
-static int ext4_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt);
+static struct dentry *ext4_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data);
static void ext4_destroy_lazyinit_thread(void);
static void ext4_unregister_li_request(struct super_block *sb);
static struct file_system_type ext3_fs_type = {
.owner = THIS_MODULE,
.name = "ext3",
- .get_sb = ext4_get_sb,
+ .mount = ext4_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
#endif
-static int ext4_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ext4_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ext4_fill_super,mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ext4_fill_super);
}
#if !defined(CONFIG_EXT2_FS) && !defined(CONFIG_EXT2_FS_MODULE) && defined(CONFIG_EXT4_USE_FOR_EXT23)
static struct file_system_type ext2_fs_type = {
.owner = THIS_MODULE,
.name = "ext2",
- .get_sb = ext4_get_sb,
+ .mount = ext4_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
static struct file_system_type ext4_fs_type = {
.owner = THIS_MODULE,
.name = "ext4",
- .get_sb = ext4_get_sb,
+ .mount = ext4_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return 0;
}
-static int msdos_get_sb(struct file_system_type *fs_type,
+static struct dentry *msdos_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, msdos_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, msdos_fill_super);
}
static struct file_system_type msdos_fs_type = {
.owner = THIS_MODULE,
.name = "msdos",
- .get_sb = msdos_get_sb,
+ .mount = msdos_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return 0;
}
-static int vfat_get_sb(struct file_system_type *fs_type,
+static struct dentry *vfat_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, vfat_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, vfat_fill_super);
}
static struct file_system_type vfat_fs_type = {
.owner = THIS_MODULE,
.name = "vfat",
- .get_sb = vfat_get_sb,
+ .mount = vfat_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
/*
* The usual module blurb.
*/
-static int vxfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *vxfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, vxfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, vxfs_fill_super);
}
static struct file_system_type vxfs_fs_type = {
.owner = THIS_MODULE,
.name = "vxfs",
- .get_sb = vxfs_get_sb,
+ .mount = vxfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return work;
}
+/*
+ * Add in the number of potentially dirty inodes, because each inode
+ * write can dirty pagecache in the underlying blockdev.
+ */
+static unsigned long get_nr_dirty_pages(void)
+{
+ return global_page_state(NR_FILE_DIRTY) +
+ global_page_state(NR_UNSTABLE_NFS) +
+ get_nr_dirty_inodes();
+}
+
static long wb_check_old_data_flush(struct bdi_writeback *wb)
{
unsigned long expired;
return 0;
wb->last_old_flush = jiffies;
- /*
- * Add in the number of potentially dirty inodes, because each inode
- * write can dirty pagecache in the underlying blockdev.
- */
- nr_pages = global_page_state(NR_FILE_DIRTY) +
- global_page_state(NR_UNSTABLE_NFS) +
- get_nr_dirty_inodes();
+ nr_pages = get_nr_dirty_pages();
if (nr_pages) {
struct wb_writeback_work work = {
}
/**
- * writeback_inodes_sb - writeback dirty inodes from given super_block
+ * writeback_inodes_sb_nr - writeback dirty inodes from given super_block
* @sb: the superblock
+ * @nr: the number of pages to write
*
* Start writeback on some inodes on this super_block. No guarantees are made
* on how many (if any) will be written, and this function does not wait
- * for IO completion of submitted IO. The number of pages submitted is
- * returned.
+ * for IO completion of submitted IO.
*/
-void writeback_inodes_sb(struct super_block *sb)
+void writeback_inodes_sb_nr(struct super_block *sb, unsigned long nr)
{
- unsigned long nr_dirty = global_page_state(NR_FILE_DIRTY);
- unsigned long nr_unstable = global_page_state(NR_UNSTABLE_NFS);
DECLARE_COMPLETION_ONSTACK(done);
struct wb_writeback_work work = {
.sb = sb,
.sync_mode = WB_SYNC_NONE,
.done = &done,
+ .nr_pages = nr,
};
WARN_ON(!rwsem_is_locked(&sb->s_umount));
-
- work.nr_pages = nr_dirty + nr_unstable + get_nr_dirty_inodes();
-
bdi_queue_work(sb->s_bdi, &work);
wait_for_completion(&done);
}
+EXPORT_SYMBOL(writeback_inodes_sb_nr);
+
+/**
+ * writeback_inodes_sb - writeback dirty inodes from given super_block
+ * @sb: the superblock
+ *
+ * Start writeback on some inodes on this super_block. No guarantees are made
+ * on how many (if any) will be written, and this function does not wait
+ * for IO completion of submitted IO.
+ */
+void writeback_inodes_sb(struct super_block *sb)
+{
+ return writeback_inodes_sb_nr(sb, get_nr_dirty_pages());
+}
EXPORT_SYMBOL(writeback_inodes_sb);
/**
}
EXPORT_SYMBOL(writeback_inodes_sb_if_idle);
+/**
+ * writeback_inodes_sb_if_idle - start writeback if none underway
+ * @sb: the superblock
+ * @nr: the number of pages to write
+ *
+ * Invoke writeback_inodes_sb if no writeback is currently underway.
+ * Returns 1 if writeback was started, 0 if not.
+ */
+int writeback_inodes_sb_nr_if_idle(struct super_block *sb,
+ unsigned long nr)
+{
+ if (!writeback_in_progress(sb->s_bdi)) {
+ down_read(&sb->s_umount);
+ writeback_inodes_sb_nr(sb, nr);
+ up_read(&sb->s_umount);
+ return 1;
+ } else
+ return 0;
+}
+EXPORT_SYMBOL(writeback_inodes_sb_nr_if_idle);
+
/**
* sync_inodes_sb - sync sb inode pages
* @sb: the superblock
return 0;
}
-static int fuse_ctl_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *raw_data,
- struct vfsmount *mnt)
+static struct dentry *fuse_ctl_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *raw_data)
{
- return get_sb_single(fs_type, flags, raw_data,
- fuse_ctl_fill_super, mnt);
+ return mount_single(fs_type, flags, raw_data, fuse_ctl_fill_super);
}
static void fuse_ctl_kill_sb(struct super_block *sb)
static struct file_system_type fuse_ctl_fs_type = {
.owner = THIS_MODULE,
.name = "fusectl",
- .get_sb = fuse_ctl_get_sb,
+ .mount = fuse_ctl_mount,
.kill_sb = fuse_ctl_kill_sb,
};
return err;
}
-static int fuse_get_sb(struct file_system_type *fs_type,
+static struct dentry *fuse_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *raw_data, struct vfsmount *mnt)
+ void *raw_data)
{
- return get_sb_nodev(fs_type, flags, raw_data, fuse_fill_super, mnt);
+ return mount_nodev(fs_type, flags, raw_data, fuse_fill_super);
}
static void fuse_kill_sb_anon(struct super_block *sb)
.owner = THIS_MODULE,
.name = "fuse",
.fs_flags = FS_HAS_SUBTYPE,
- .get_sb = fuse_get_sb,
+ .mount = fuse_mount,
.kill_sb = fuse_kill_sb_anon,
};
#ifdef CONFIG_BLOCK
-static int fuse_get_sb_blk(struct file_system_type *fs_type,
+static struct dentry *fuse_mount_blk(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *raw_data, struct vfsmount *mnt)
+ void *raw_data)
{
- return get_sb_bdev(fs_type, flags, dev_name, raw_data, fuse_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, raw_data, fuse_fill_super);
}
static void fuse_kill_sb_blk(struct super_block *sb)
static struct file_system_type fuseblk_fs_type = {
.owner = THIS_MODULE,
.name = "fuseblk",
- .get_sb = fuse_get_sb_blk,
+ .mount = fuse_mount_blk,
.kill_sb = fuse_kill_sb_blk,
.fs_flags = FS_REQUIRES_DEV | FS_HAS_SUBTYPE,
};
}
/**
- * gfs2_get_sb - Get the GFS2 superblock
+ * gfs2_mount - Get the GFS2 superblock
* @fs_type: The GFS2 filesystem type
* @flags: Mount flags
* @dev_name: The name of the device
* @data: The mount arguments
- * @mnt: The vfsmnt for this mount
*
* Q. Why not use get_sb_bdev() ?
* A. We need to select one of two root directories to mount, independent
* Returns: 0 or -ve on error
*/
-static int gfs2_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *gfs2_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
struct block_device *bdev;
struct super_block *s;
bdev = open_bdev_exclusive(dev_name, mode, fs_type);
if (IS_ERR(bdev))
- return PTR_ERR(bdev);
+ return ERR_CAST(bdev);
/*
* once the super is inserted into the list by sget, s_umount
if (IS_ERR(s))
goto error_bdev;
+ if (s->s_root)
+ close_bdev_exclusive(bdev, mode);
+
memset(&args, 0, sizeof(args));
args.ar_quota = GFS2_QUOTA_DEFAULT;
args.ar_data = GFS2_DATA_DEFAULT;
error = gfs2_mount_args(&args, data);
if (error) {
printk(KERN_WARNING "GFS2: can't parse mount arguments\n");
- if (s->s_root)
- goto error_super;
- deactivate_locked_super(s);
- return error;
+ goto error_super;
}
if (s->s_root) {
error = -EBUSY;
if ((flags ^ s->s_flags) & MS_RDONLY)
goto error_super;
- close_bdev_exclusive(bdev, mode);
} else {
char b[BDEVNAME_SIZE];
strlcpy(s->s_id, bdevname(bdev, b), sizeof(s->s_id));
sb_set_blocksize(s, block_size(bdev));
error = fill_super(s, &args, flags & MS_SILENT ? 1 : 0);
- if (error) {
- deactivate_locked_super(s);
- return error;
- }
+ if (error)
+ goto error_super;
s->s_flags |= MS_ACTIVE;
bdev->bd_super = s;
}
sdp = s->s_fs_info;
- mnt->mnt_sb = s;
if (args.ar_meta)
- mnt->mnt_root = dget(sdp->sd_master_dir);
+ return dget(sdp->sd_master_dir);
else
- mnt->mnt_root = dget(sdp->sd_root_dir);
- return 0;
+ return dget(sdp->sd_root_dir);
error_super:
deactivate_locked_super(s);
+ return ERR_PTR(error);
error_bdev:
close_bdev_exclusive(bdev, mode);
- return error;
+ return ERR_PTR(error);
}
static int set_meta_super(struct super_block *s, void *ptr)
return -EINVAL;
}
-static int gfs2_get_sb_meta(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *gfs2_mount_meta(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
struct super_block *s;
struct gfs2_sbd *sdp;
if (error) {
printk(KERN_WARNING "GFS2: path_lookup on %s returned error %d\n",
dev_name, error);
- return error;
+ return ERR_PTR(error);
}
s = sget(&gfs2_fs_type, test_gfs2_super, set_meta_super,
path.dentry->d_inode->i_sb->s_bdev);
path_put(&path);
if (IS_ERR(s)) {
printk(KERN_WARNING "GFS2: gfs2 mount does not exist\n");
- return PTR_ERR(s);
+ return ERR_CAST(s);
}
if ((flags ^ s->s_flags) & MS_RDONLY) {
deactivate_locked_super(s);
- return -EBUSY;
+ return ERR_PTR(-EBUSY);
}
sdp = s->s_fs_info;
- mnt->mnt_sb = s;
- mnt->mnt_root = dget(sdp->sd_master_dir);
- return 0;
+ return dget(sdp->sd_master_dir);
}
static void gfs2_kill_sb(struct super_block *sb)
struct file_system_type gfs2_fs_type = {
.name = "gfs2",
.fs_flags = FS_REQUIRES_DEV,
- .get_sb = gfs2_get_sb,
+ .mount = gfs2_mount,
.kill_sb = gfs2_kill_sb,
.owner = THIS_MODULE,
};
struct file_system_type gfs2meta_fs_type = {
.name = "gfs2meta",
.fs_flags = FS_REQUIRES_DEV,
- .get_sb = gfs2_get_sb_meta,
+ .mount = gfs2_mount_meta,
.owner = THIS_MODULE,
};
return res;
}
-static int hfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *hfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, hfs_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, hfs_fill_super);
}
static struct file_system_type hfs_fs_type = {
.owner = THIS_MODULE,
.name = "hfs",
- .get_sb = hfs_get_sb,
+ .mount = hfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
#define HFSPLUS_INODE_SIZE sizeof(struct hfsplus_inode_info)
-static int hfsplus_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *hfsplus_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, hfsplus_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, hfsplus_fill_super);
}
static struct file_system_type hfsplus_fs_type = {
.owner = THIS_MODULE,
.name = "hfsplus",
- .get_sb = hfsplus_get_sb,
+ .mount = hfsplus_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return err;
}
-static int hostfs_read_sb(struct file_system_type *type,
+static struct dentry *hostfs_read_sb(struct file_system_type *type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_nodev(type, flags, data, hostfs_fill_sb_common, mnt);
+ return mount_nodev(type, flags, data, hostfs_fill_sb_common);
}
static void hostfs_kill_sb(struct super_block *s)
static struct file_system_type hostfs_type = {
.owner = THIS_MODULE,
.name = "hostfs",
- .get_sb = hostfs_read_sb,
+ .mount = hostfs_read_sb,
.kill_sb = hostfs_kill_sb,
.fs_flags = 0,
};
return -EINVAL;
}
-static int hpfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *hpfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, hpfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, hpfs_fill_super);
}
static struct file_system_type hpfs_fs_type = {
.owner = THIS_MODULE,
.name = "hpfs",
- .get_sb = hpfs_get_sb,
+ .mount = hpfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return(err);
}
-static int hppfs_read_super(struct file_system_type *type,
+static struct dentry *hppfs_read_super(struct file_system_type *type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_nodev(type, flags, data, hppfs_fill_super, mnt);
+ return mount_nodev(type, flags, data, hppfs_fill_super);
}
static struct file_system_type hppfs_type = {
.owner = THIS_MODULE,
.name = "hppfs",
- .get_sb = hppfs_read_super,
+ .mount = hppfs_read_super,
.kill_sb = kill_anon_super,
.fs_flags = 0,
};
}
}
-static int hugetlbfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *hugetlbfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, hugetlbfs_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, hugetlbfs_fill_super);
}
static struct file_system_type hugetlbfs_fs_type = {
.name = "hugetlbfs",
- .get_sb = hugetlbfs_get_sb,
+ .mount = hugetlbfs_mount,
.kill_sb = kill_litter_super,
};
* inode.c
*/
extern int get_nr_dirty_inodes(void);
-extern int evict_inodes(struct super_block *);
+extern void evict_inodes(struct super_block *);
extern int invalidate_inodes(struct super_block *);
return inode;
}
-static int isofs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *isofs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, isofs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, isofs_fill_super);
}
static struct file_system_type iso9660_fs_type = {
.owner = THIS_MODULE,
.name = "iso9660",
- .get_sb = isofs_get_sb,
+ .mount = isofs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
static inline struct jffs2_inode_cache *
first_inode_chain(int *i, struct jffs2_sb_info *c)
{
- for (; *i < INOCACHE_HASHSIZE; (*i)++) {
+ for (; *i < c->inocache_hashsize; (*i)++) {
if (c->inocache_list[*i])
return c->inocache_list[*i];
}
spin_unlock(&jffs2_compressor_list_lock);
*datalen = orig_slen;
*cdatalen = orig_dlen;
- compr_ret = this->compress(data_in, output_buf, datalen, cdatalen, NULL);
+ compr_ret = this->compress(data_in, output_buf, datalen, cdatalen);
spin_lock(&jffs2_compressor_list_lock);
this->usecount--;
if (!compr_ret) {
spin_unlock(&jffs2_compressor_list_lock);
*datalen = orig_slen;
*cdatalen = orig_dlen;
- compr_ret = this->compress(data_in, this->compr_buf, datalen, cdatalen, NULL);
+ compr_ret = this->compress(data_in, this->compr_buf, datalen, cdatalen);
spin_lock(&jffs2_compressor_list_lock);
this->usecount--;
if (!compr_ret) {
if (comprtype == this->compr) {
this->usecount++;
spin_unlock(&jffs2_compressor_list_lock);
- ret = this->decompress(cdata_in, data_out, cdatalen, datalen, NULL);
+ ret = this->decompress(cdata_in, data_out, cdatalen, datalen);
spin_lock(&jffs2_compressor_list_lock);
if (ret) {
printk(KERN_WARNING "Decompressor \"%s\" returned %d\n", this->name, ret);
char *name;
char compr; /* JFFS2_COMPR_XXX */
int (*compress)(unsigned char *data_in, unsigned char *cpage_out,
- uint32_t *srclen, uint32_t *destlen, void *model);
+ uint32_t *srclen, uint32_t *destlen);
int (*decompress)(unsigned char *cdata_in, unsigned char *data_out,
- uint32_t cdatalen, uint32_t datalen, void *model);
+ uint32_t cdatalen, uint32_t datalen);
int usecount;
int disabled; /* if set the compressor won't compress */
unsigned char *compr_buf; /* used by size compr. mode */
}
static int jffs2_lzo_compress(unsigned char *data_in, unsigned char *cpage_out,
- uint32_t *sourcelen, uint32_t *dstlen, void *model)
+ uint32_t *sourcelen, uint32_t *dstlen)
{
size_t compress_size;
int ret;
}
static int jffs2_lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
- uint32_t srclen, uint32_t destlen, void *model)
+ uint32_t srclen, uint32_t destlen)
{
size_t dl = destlen;
int ret;
/* _compress returns the compressed size, -1 if bigger */
static int jffs2_rtime_compress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t *sourcelen, uint32_t *dstlen,
- void *model)
+ uint32_t *sourcelen, uint32_t *dstlen)
{
short positions[256];
int outpos = 0;
static int jffs2_rtime_decompress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t srclen, uint32_t destlen,
- void *model)
+ uint32_t srclen, uint32_t destlen)
{
short positions[256];
int outpos = 0;
#if 0
/* _compress returns the compressed size, -1 if bigger */
int jffs2_rubinmips_compress(unsigned char *data_in, unsigned char *cpage_out,
- uint32_t *sourcelen, uint32_t *dstlen, void *model)
+ uint32_t *sourcelen, uint32_t *dstlen)
{
return rubin_do_compress(BIT_DIVIDER_MIPS, bits_mips, data_in,
cpage_out, sourcelen, dstlen);
#endif
static int jffs2_dynrubin_compress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t *sourcelen, uint32_t *dstlen,
- void *model)
+ uint32_t *sourcelen, uint32_t *dstlen)
{
int bits[8];
unsigned char histo[256];
static int jffs2_rubinmips_decompress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t sourcelen, uint32_t dstlen,
- void *model)
+ uint32_t sourcelen, uint32_t dstlen)
{
rubin_do_decompress(BIT_DIVIDER_MIPS, bits_mips, data_in,
cpage_out, sourcelen, dstlen);
static int jffs2_dynrubin_decompress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t sourcelen, uint32_t dstlen,
- void *model)
+ uint32_t sourcelen, uint32_t dstlen)
{
int bits[8];
int c;
static int jffs2_zlib_compress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t *sourcelen, uint32_t *dstlen,
- void *model)
+ uint32_t *sourcelen, uint32_t *dstlen)
{
int ret;
static int jffs2_zlib_decompress(unsigned char *data_in,
unsigned char *cpage_out,
- uint32_t srclen, uint32_t destlen,
- void *model)
+ uint32_t srclen, uint32_t destlen)
{
int ret;
int wbits = MAX_WBITS;
}
/* We use f->target field to store the target path. */
- f->target = kmalloc(targetlen + 1, GFP_KERNEL);
+ f->target = kmemdup(target, targetlen + 1, GFP_KERNEL);
if (!f->target) {
printk(KERN_WARNING "Can't allocate %d bytes of memory\n", targetlen + 1);
mutex_unlock(&f->sem);
goto fail;
}
- memcpy(f->target, target, targetlen + 1);
D1(printk(KERN_DEBUG "jffs2_symlink: symlink's target '%s' cached\n", (char *)f->target));
/* No data here. Only a metadata node, which will be
}
/* Be nice */
- yield();
+ cond_resched();
mutex_lock(&c->erase_free_sem);
spin_lock(&c->erase_completion_lock);
}
return inode;
}
+static int calculate_inocache_hashsize(uint32_t flash_size)
+{
+ /*
+ * Pick a inocache hash size based on the size of the medium.
+ * Count how many megabytes we're dealing with, apply a hashsize twice
+ * that size, but rounding down to the usual big powers of 2. And keep
+ * to sensible bounds.
+ */
+
+ int size_mb = flash_size / 1024 / 1024;
+ int hashsize = (size_mb * 2) & ~0x3f;
+
+ if (hashsize < INOCACHE_HASHSIZE_MIN)
+ return INOCACHE_HASHSIZE_MIN;
+ if (hashsize > INOCACHE_HASHSIZE_MAX)
+ return INOCACHE_HASHSIZE_MAX;
+
+ return hashsize;
+}
int jffs2_do_fill_super(struct super_block *sb, void *data, int silent)
{
if (ret)
return ret;
- c->inocache_list = kcalloc(INOCACHE_HASHSIZE, sizeof(struct jffs2_inode_cache *), GFP_KERNEL);
+ c->inocache_hashsize = calculate_inocache_hashsize(c->flash_size);
+ c->inocache_list = kcalloc(c->inocache_hashsize, sizeof(struct jffs2_inode_cache *), GFP_KERNEL);
if (!c->inocache_list) {
ret = -ENOMEM;
goto out_wbuf;
if (!list_empty(&c->erase_complete_list) ||
!list_empty(&c->erase_pending_list)) {
spin_unlock(&c->erase_completion_lock);
+ mutex_unlock(&c->alloc_sem);
D1(printk(KERN_DEBUG "jffs2_garbage_collect_pass() erasing pending blocks\n"));
- if (jffs2_erase_pending_blocks(c, 1)) {
- mutex_unlock(&c->alloc_sem);
+ if (jffs2_erase_pending_blocks(c, 1))
return 0;
- }
+
D1(printk(KERN_DEBUG "No progress from erasing blocks; doing GC anyway\n"));
spin_lock(&c->erase_completion_lock);
+ mutex_lock(&c->alloc_sem);
}
/* First, work out which block we're garbage-collecting */
wait_queue_head_t erase_wait; /* For waiting for erases to complete */
wait_queue_head_t inocache_wq;
+ int inocache_hashsize;
struct jffs2_inode_cache **inocache_list;
spinlock_t inocache_lock;
{
struct jffs2_inode_cache *ret;
- ret = c->inocache_list[ino % INOCACHE_HASHSIZE];
+ ret = c->inocache_list[ino % c->inocache_hashsize];
while (ret && ret->ino < ino) {
ret = ret->next;
}
dbg_inocache("add %p (ino #%u)\n", new, new->ino);
- prev = &c->inocache_list[new->ino % INOCACHE_HASHSIZE];
+ prev = &c->inocache_list[new->ino % c->inocache_hashsize];
while ((*prev) && (*prev)->ino < new->ino) {
prev = &(*prev)->next;
dbg_inocache("del %p (ino #%u)\n", old, old->ino);
spin_lock(&c->inocache_lock);
- prev = &c->inocache_list[old->ino % INOCACHE_HASHSIZE];
+ prev = &c->inocache_list[old->ino % c->inocache_hashsize];
while ((*prev) && (*prev)->ino < old->ino) {
prev = &(*prev)->next;
int i;
struct jffs2_inode_cache *this, *next;
- for (i=0; i<INOCACHE_HASHSIZE; i++) {
+ for (i=0; i < c->inocache_hashsize; i++) {
this = c->inocache_list[i];
while (this) {
next = this->next;
#define RAWNODE_CLASS_XATTR_DATUM 1
#define RAWNODE_CLASS_XATTR_REF 2
-#define INOCACHE_HASHSIZE 128
+#define INOCACHE_HASHSIZE_MIN 128
+#define INOCACHE_HASHSIZE_MAX 1024
#define write_ofs(c) ((c)->nextblock->offset + (c)->sector_size - (c)->nextblock->free_size)
#include "summary.h"
#include "debug.h"
-#define DEFAULT_EMPTY_SCAN_SIZE 1024
+#define DEFAULT_EMPTY_SCAN_SIZE 256
#define noisy_printk(noise, args...) do { \
if (*(noise)) { \
unsigned char *buf, uint32_t buf_size, struct jffs2_summary *s) {
struct jffs2_unknown_node *node;
struct jffs2_unknown_node crcnode;
- uint32_t ofs, prevofs;
+ uint32_t ofs, prevofs, max_ofs;
uint32_t hdr_crc, buf_ofs, buf_len;
int err;
int noise = 0;
/* We temporarily use 'ofs' as a pointer into the buffer/jeb */
ofs = 0;
-
- /* Scan only 4KiB of 0xFF before declaring it's empty */
- while(ofs < EMPTY_SCAN_SIZE(c->sector_size) && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF)
+ max_ofs = EMPTY_SCAN_SIZE(c->sector_size);
+ /* Scan only EMPTY_SCAN_SIZE of 0xFF before declaring it's empty */
+ while(ofs < max_ofs && *(uint32_t *)(&buf[ofs]) == 0xFFFFFFFF)
ofs += 4;
- if (ofs == EMPTY_SCAN_SIZE(c->sector_size)) {
+ if (ofs == max_ofs) {
#ifdef CONFIG_JFFS2_FS_WRITEBUFFER
if (jffs2_cleanmarker_oob(c)) {
/* scan oob, take care of cleanmarker */
return ret;
}
-static int jffs2_get_sb(struct file_system_type *fs_type,
+static struct dentry *jffs2_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_mtd(fs_type, flags, dev_name, data, jffs2_fill_super,
- mnt);
+ return mount_mtd(fs_type, flags, dev_name, data, jffs2_fill_super);
}
static void jffs2_put_super (struct super_block *sb)
static struct file_system_type jffs2_fs_type = {
.owner = THIS_MODULE,
.name = "jffs2",
- .get_sb = jffs2_get_sb,
+ .mount = jffs2_mount,
.kill_sb = jffs2_kill_sb,
};
return 0;
}
-static int jfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *jfs_do_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, jfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, jfs_fill_super);
}
static int jfs_sync_fs(struct super_block *sb, int wait)
static struct file_system_type jfs_fs_type = {
.owner = THIS_MODULE,
.name = "jfs",
- .get_sb = jfs_get_sb,
+ .mount = jfs_do_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
* Common helper for pseudo-filesystems (sockfs, pipefs, bdev - stuff that
* will never be mountable)
*/
-int get_sb_pseudo(struct file_system_type *fs_type, char *name,
- const struct super_operations *ops, unsigned long magic,
- struct vfsmount *mnt)
+struct dentry *mount_pseudo(struct file_system_type *fs_type, char *name,
+ const struct super_operations *ops, unsigned long magic)
{
struct super_block *s = sget(fs_type, NULL, set_anon_super, NULL);
struct dentry *dentry;
struct qstr d_name = {.name = name, .len = strlen(name)};
if (IS_ERR(s))
- return PTR_ERR(s);
+ return ERR_CAST(s);
s->s_flags = MS_NOUSER;
s->s_maxbytes = MAX_LFS_FILESIZE;
d_instantiate(dentry, root);
s->s_root = dentry;
s->s_flags |= MS_ACTIVE;
- simple_set_mnt(mnt, s);
- return 0;
+ return dget(s->s_root);
Enomem:
deactivate_locked_super(s);
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
}
int simple_link(struct dentry *old_dentry, struct inode *dir, struct dentry *dentry)
EXPORT_SYMBOL(dcache_dir_open);
EXPORT_SYMBOL(dcache_readdir);
EXPORT_SYMBOL(generic_read_dir);
-EXPORT_SYMBOL(get_sb_pseudo);
+EXPORT_SYMBOL(mount_pseudo);
EXPORT_SYMBOL(simple_write_begin);
EXPORT_SYMBOL(simple_write_end);
EXPORT_SYMBOL(simple_dir_inode_operations);
EXPORT_SYMBOL_GPL(locks_release_private);
/* Free a lock which is not in use. */
-static void locks_free_lock(struct file_lock *fl)
+void locks_free_lock(struct file_lock *fl)
{
BUG_ON(waitqueue_active(&fl->fl_wait));
BUG_ON(!list_empty(&fl->fl_block));
locks_release_private(fl);
kmem_cache_free(filelock_cache, fl);
}
+EXPORT_SYMBOL(locks_free_lock);
void locks_init_lock(struct file_lock *fl)
{
fl->fl_ops->fl_copy_lock(new, fl);
new->fl_ops = fl->fl_ops;
}
- if (fl->fl_lmops) {
- if (fl->fl_lmops->fl_copy_lock)
- fl->fl_lmops->fl_copy_lock(new, fl);
+ if (fl->fl_lmops)
new->fl_lmops = fl->fl_lmops;
- }
}
/*
struct inode *inode = dentry->d_inode;
int error, rdlease_count = 0, wrlease_count = 0;
+ lease = *flp;
+
+ error = -EACCES;
if ((current_fsuid() != inode->i_uid) && !capable(CAP_LEASE))
- return -EACCES;
+ goto out;
+ error = -EINVAL;
if (!S_ISREG(inode->i_mode))
- return -EINVAL;
+ goto out;
error = security_file_lock(filp, arg);
if (error)
- return error;
+ goto out;
time_out_leases(inode);
BUG_ON(!(*flp)->fl_lmops->fl_break);
- lease = *flp;
-
if (arg != F_UNLCK) {
error = -EAGAIN;
if ((arg == F_RDLCK) && (atomic_read(&inode->i_writecount) > 0))
goto out;
if (my_before != NULL) {
- *flp = *my_before;
error = lease->fl_lmops->fl_change(my_before, arg);
+ if (!error)
+ *flp = *my_before;
goto out;
}
return 0;
out:
- locks_free_lock(lease);
return error;
}
EXPORT_SYMBOL(generic_setlease);
}
EXPORT_SYMBOL_GPL(vfs_setlease);
-/**
- * fcntl_setlease - sets a lease on an open file
- * @fd: open file descriptor
- * @filp: file pointer
- * @arg: type of lease to obtain
- *
- * Call this fcntl to establish a lease on the file.
- * Note that you also need to call %F_SETSIG to
- * receive a signal when the lease is broken.
- */
-int fcntl_setlease(unsigned int fd, struct file *filp, long arg)
+static int do_fcntl_delete_lease(struct file *filp)
+{
+ struct file_lock fl, *flp = &fl;
+
+ lease_init(filp, F_UNLCK, flp);
+
+ return vfs_setlease(filp, F_UNLCK, &flp);
+}
+
+static int do_fcntl_add_lease(unsigned int fd, struct file *filp, long arg)
{
struct file_lock *fl;
struct fasync_struct *new;
}
lock_flocks();
error = __vfs_setlease(filp, arg, &fl);
- if (error || arg == F_UNLCK)
- goto out_unlock;
+ if (error) {
+ unlock_flocks();
+ locks_free_lock(fl);
+ goto out_free_fasync;
+ }
/*
* fasync_insert_entry() returns the old entry if any.
fl->fl_type = F_UNLCK | F_INPROGRESS;
fl->fl_break_time = jiffies - 10;
time_out_leases(inode);
- goto out_unlock;
+ } else {
+ error = __f_setown(filp, task_pid(current), PIDTYPE_PID, 0);
}
-
- error = __f_setown(filp, task_pid(current), PIDTYPE_PID, 0);
-out_unlock:
unlock_flocks();
+
+out_free_fasync:
if (new)
fasync_free(new);
return error;
}
+/**
+ * fcntl_setlease - sets a lease on an open file
+ * @fd: open file descriptor
+ * @filp: file pointer
+ * @arg: type of lease to obtain
+ *
+ * Call this fcntl to establish a lease on the file.
+ * Note that you also need to call %F_SETSIG to
+ * receive a signal when the lease is broken.
+ */
+int fcntl_setlease(unsigned int fd, struct file *filp, long arg)
+{
+ if (arg == F_UNLCK)
+ return do_fcntl_delete_lease(filp);
+ return do_fcntl_add_lease(fd, filp, arg);
+}
+
/**
* flock_lock_file_wait - Apply a FLOCK-style lock to a file
* @filp: The file to apply the lock to
return sync_request(page, bdev, WRITE);
}
-static void bdev_put_device(struct super_block *sb)
+static void bdev_put_device(struct logfs_super *s)
{
- close_bdev_exclusive(logfs_super(sb)->s_bdev, FMODE_READ|FMODE_WRITE);
+ close_bdev_exclusive(s->s_bdev, FMODE_READ|FMODE_WRITE);
}
static int bdev_can_write_buf(struct super_block *sb, u64 ofs)
.put_device = bdev_put_device,
};
-int logfs_get_sb_bdev(struct file_system_type *type, int flags,
- const char *devname, struct vfsmount *mnt)
+int logfs_get_sb_bdev(struct logfs_super *p, struct file_system_type *type,
+ const char *devname)
{
struct block_device *bdev;
if (MAJOR(bdev->bd_dev) == MTD_BLOCK_MAJOR) {
int mtdnr = MINOR(bdev->bd_dev);
close_bdev_exclusive(bdev, FMODE_READ|FMODE_WRITE);
- return logfs_get_sb_mtd(type, flags, mtdnr, mnt);
+ return logfs_get_sb_mtd(p, mtdnr);
}
- return logfs_get_sb_device(type, flags, NULL, bdev, &bd_devops, mnt);
+ p->s_bdev = bdev;
+ p->s_mtd = NULL;
+ p->s_devops = &bd_devops;
+ return 0;
}
__mtd_writeseg(sb, ofs, ofs >> PAGE_SHIFT, len >> PAGE_SHIFT);
}
-static void mtd_put_device(struct super_block *sb)
+static void mtd_put_device(struct logfs_super *s)
{
- put_mtd_device(logfs_super(sb)->s_mtd);
+ put_mtd_device(s->s_mtd);
}
static int mtd_can_write_buf(struct super_block *sb, u64 ofs)
.put_device = mtd_put_device,
};
-int logfs_get_sb_mtd(struct file_system_type *type, int flags,
- int mtdnr, struct vfsmount *mnt)
+int logfs_get_sb_mtd(struct logfs_super *s, int mtdnr)
{
- struct mtd_info *mtd;
- const struct logfs_device_ops *devops = &mtd_devops;
-
- mtd = get_mtd_device(NULL, mtdnr);
+ struct mtd_info *mtd = get_mtd_device(NULL, mtdnr);
if (IS_ERR(mtd))
return PTR_ERR(mtd);
- return logfs_get_sb_device(type, flags, mtd, NULL, devops, mnt);
+
+ s->s_bdev = NULL;
+ s->s_mtd = mtd;
+ s->s_devops = &mtd_devops;
+ return 0;
}
int (*erase_segment)(struct logfs_area *area);
};
+struct logfs_super; /* forward */
/**
* struct logfs_device_ops - device access operations
*
int ensure_write);
int (*can_write_buf)(struct super_block *sb, u64 ofs);
void (*sync)(struct super_block *sb);
- void (*put_device)(struct super_block *sb);
+ void (*put_device)(struct logfs_super *s);
};
/**
/* dev_bdev.c */
#ifdef CONFIG_BLOCK
-int logfs_get_sb_bdev(struct file_system_type *type, int flags,
- const char *devname, struct vfsmount *mnt);
+int logfs_get_sb_bdev(struct logfs_super *s,
+ struct file_system_type *type,
+ const char *devname);
#else
-static inline int logfs_get_sb_bdev(struct file_system_type *type, int flags,
- const char *devname, struct vfsmount *mnt)
+static inline int logfs_get_sb_bdev(struct logfs_super *s,
+ struct file_system_type *type,
+ const char *devname)
{
return -ENODEV;
}
/* dev_mtd.c */
#ifdef CONFIG_MTD
-int logfs_get_sb_mtd(struct file_system_type *type, int flags,
- int mtdnr, struct vfsmount *mnt);
+int logfs_get_sb_mtd(struct logfs_super *s, int mtdnr)
#else
-static inline int logfs_get_sb_mtd(struct file_system_type *type, int flags,
- int mtdnr, struct vfsmount *mnt)
+static inline int logfs_get_sb_mtd(struct logfs_super *s, int mtdnr)
{
return -ENODEV;
}
void logfs_crash_dump(struct super_block *sb);
void *memchr_inv(const void *s, int c, size_t n);
int logfs_statfs(struct dentry *dentry, struct kstatfs *stats);
-int logfs_get_sb_device(struct file_system_type *type, int flags,
- struct mtd_info *mtd, struct block_device *bdev,
- const struct logfs_device_ops *devops, struct vfsmount *mnt);
int logfs_check_ds(struct logfs_disk_super *ds);
int logfs_write_sb(struct super_block *sb);
return 0;
}
-static int logfs_get_sb_final(struct super_block *sb, struct vfsmount *mnt)
+static int logfs_get_sb_final(struct super_block *sb)
{
struct logfs_super *super = logfs_super(sb);
struct inode *rootdir;
}
log_super("LogFS: Finished mounting\n");
- simple_set_mnt(mnt, sb);
return 0;
fail:
logfs_cleanup_rw(sb);
if (super->s_erase_page)
__free_page(super->s_erase_page);
- super->s_devops->put_device(sb);
+ super->s_devops->put_device(super);
logfs_mempool_destroy(super->s_btree_pool);
logfs_mempool_destroy(super->s_alias_pool);
kfree(super);
log_super("LogFS: Finished unmounting\n");
}
-int logfs_get_sb_device(struct file_system_type *type, int flags,
- struct mtd_info *mtd, struct block_device *bdev,
- const struct logfs_device_ops *devops, struct vfsmount *mnt)
+static struct dentry *logfs_get_sb_device(struct logfs_super *super,
+ struct file_system_type *type, int flags)
{
- struct logfs_super *super;
struct super_block *sb;
int err = -ENOMEM;
static int mount_count;
log_super("LogFS: Start mount %x\n", mount_count++);
- super = kzalloc(sizeof(*super), GFP_KERNEL);
- if (!super)
- goto err0;
- super->s_mtd = mtd;
- super->s_bdev = bdev;
err = -EINVAL;
sb = sget(type, logfs_sb_test, logfs_sb_set, super);
- if (IS_ERR(sb))
- goto err0;
+ if (IS_ERR(sb)) {
+ super->s_devops->put_device(super);
+ kfree(super);
+ return ERR_CAST(sb);
+ }
if (sb->s_root) {
/* Device is already in use */
- err = 0;
- simple_set_mnt(mnt, sb);
- goto err0;
+ super->s_devops->put_device(super);
+ kfree(super);
+ return dget(sb->s_root);
}
- super->s_devops = devops;
-
/*
* sb->s_maxbytes is limited to 8TB. On 32bit systems, the page cache
* only covers 16TB and the upper 8TB are used for indirect blocks.
goto err1;
sb->s_flags |= MS_ACTIVE;
- err = logfs_get_sb_final(sb, mnt);
- if (err)
+ err = logfs_get_sb_final(sb);
+ if (err) {
deactivate_locked_super(sb);
- return err;
+ return ERR_PTR(err);
+ }
+ return dget(sb->s_root);
err1:
/* no ->s_root, no ->put_super() */
iput(super->s_segfile_inode);
iput(super->s_mapping_inode);
deactivate_locked_super(sb);
- return err;
-err0:
- kfree(super);
- //devops->put_device(sb);
- return err;
+ return ERR_PTR(err);
}
-static int logfs_get_sb(struct file_system_type *type, int flags,
- const char *devname, void *data, struct vfsmount *mnt)
+static struct dentry *logfs_mount(struct file_system_type *type, int flags,
+ const char *devname, void *data)
{
ulong mtdnr;
+ struct logfs_super *super;
+ int err;
- if (!devname)
- return logfs_get_sb_bdev(type, flags, devname, mnt);
- if (strncmp(devname, "mtd", 3))
- return logfs_get_sb_bdev(type, flags, devname, mnt);
+ super = kzalloc(sizeof(*super), GFP_KERNEL);
+ if (!super)
+ return ERR_PTR(-ENOMEM);
- {
+ if (!devname)
+ err = logfs_get_sb_bdev(super, type, devname);
+ else if (strncmp(devname, "mtd", 3))
+ err = logfs_get_sb_bdev(super, type, devname);
+ else {
char *garbage;
mtdnr = simple_strtoul(devname+3, &garbage, 0);
if (*garbage)
- return -EINVAL;
+ err = -EINVAL;
+ else
+ err = logfs_get_sb_mtd(super, mtdnr);
+ }
+
+ if (err) {
+ kfree(super);
+ return ERR_PTR(err);
}
- return logfs_get_sb_mtd(type, flags, mtdnr, mnt);
+ return logfs_get_sb_device(super, type, flags);
}
static struct file_system_type logfs_fs_type = {
.owner = THIS_MODULE,
.name = "logfs",
- .get_sb = logfs_get_sb,
+ .mount = logfs_mount,
.kill_sb = logfs_kill_sb,
.fs_flags = FS_REQUIRES_DEV,
V2_minix_truncate(inode);
}
-static int minix_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *minix_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, minix_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, minix_fill_super);
}
static struct file_system_type minix_fs_type = {
.owner = THIS_MODULE,
.name = "minix",
- .get_sb = minix_get_sb,
+ .mount = minix_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
*/
if (will_truncate)
mnt_drop_write(nd->path.mnt);
+ path_put(&nd->path);
return filp;
exit:
}
filp = nameidata_to_filp(nd);
mnt_drop_write(nd->path.mnt);
+ path_put(&nd->path);
if (!IS_ERR(filp)) {
error = ima_file_check(filp, acc_mode);
if (error) {
return result;
}
-static int ncp_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ncp_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, ncp_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, ncp_fill_super);
}
static struct file_system_type ncp_fs_type = {
.owner = THIS_MODULE,
.name = "ncpfs",
- .get_sb = ncp_get_sb,
+ .mount = ncp_mount,
.kill_sb = kill_anon_super,
.fs_flags = FS_BINARY_MOUNTDATA,
};
dprintk("NFS: setlease(%s/%s, arg=%ld)\n",
file->f_path.dentry->d_parent->d_name.name,
file->f_path.dentry->d_name.name, arg);
-
return -EINVAL;
}
static int nfs_show_options(struct seq_file *, struct vfsmount *);
static int nfs_show_stats(struct seq_file *, struct vfsmount *);
static int nfs_get_sb(struct file_system_type *, int, const char *, void *, struct vfsmount *);
-static int nfs_xdev_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
+static struct dentry *nfs_xdev_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *raw_data);
static void nfs_put_super(struct super_block *);
static void nfs_kill_super(struct super_block *);
static int nfs_remount(struct super_block *sb, int *flags, char *raw_data);
struct file_system_type nfs_xdev_fs_type = {
.owner = THIS_MODULE,
.name = "nfs",
- .get_sb = nfs_xdev_get_sb,
+ .mount = nfs_xdev_mount,
.kill_sb = nfs_kill_super,
.fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA,
};
struct nfs_parsed_mount_data *data, struct vfsmount *mnt);
static int nfs4_get_sb(struct file_system_type *fs_type,
int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
-static int nfs4_remote_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
-static int nfs4_xdev_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
+static struct dentry *nfs4_remote_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *raw_data);
+static struct dentry *nfs4_xdev_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *raw_data);
static int nfs4_referral_get_sb(struct file_system_type *fs_type,
int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
-static int nfs4_remote_referral_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt);
+static struct dentry *nfs4_remote_referral_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *raw_data);
static void nfs4_kill_super(struct super_block *sb);
static struct file_system_type nfs4_fs_type = {
static struct file_system_type nfs4_remote_fs_type = {
.owner = THIS_MODULE,
.name = "nfs4",
- .get_sb = nfs4_remote_get_sb,
+ .mount = nfs4_remote_mount,
.kill_sb = nfs4_kill_super,
.fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA,
};
struct file_system_type nfs4_xdev_fs_type = {
.owner = THIS_MODULE,
.name = "nfs4",
- .get_sb = nfs4_xdev_get_sb,
+ .mount = nfs4_xdev_mount,
.kill_sb = nfs4_kill_super,
.fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA,
};
static struct file_system_type nfs4_remote_referral_fs_type = {
.owner = THIS_MODULE,
.name = "nfs4",
- .get_sb = nfs4_remote_referral_get_sb,
+ .mount = nfs4_remote_referral_mount,
.kill_sb = nfs4_kill_super,
.fs_flags = FS_RENAME_DOES_D_MOVE|FS_REVAL_DOT|FS_BINARY_MOUNTDATA,
};
/*
* Clone an NFS2/3 server record on xdev traversal (FSID-change)
*/
-static int nfs_xdev_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *raw_data,
- struct vfsmount *mnt)
+static struct dentry *
+nfs_xdev_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *raw_data)
{
struct nfs_clone_mount *data = raw_data;
struct super_block *s;
};
int error;
- dprintk("--> nfs_xdev_get_sb()\n");
+ dprintk("--> nfs_xdev_mount()\n");
/* create a new volume representation */
server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr);
}
s->s_flags |= MS_ACTIVE;
- mnt->mnt_sb = s;
- mnt->mnt_root = mntroot;
/* clone any lsm security options from the parent to the new sb */
security_sb_clone_mnt_opts(data->sb, s);
- dprintk("<-- nfs_xdev_get_sb() = 0\n");
- return 0;
+ dprintk("<-- nfs_xdev_mount() = 0\n");
+ return mntroot;
out_err_nosb:
nfs_free_server(server);
out_err_noserver:
- dprintk("<-- nfs_xdev_get_sb() = %d [error]\n", error);
- return error;
+ dprintk("<-- nfs_xdev_mount() = %d [error]\n", error);
+ return ERR_PTR(error);
error_splat_super:
if (server && !s->s_root)
bdi_unregister(&server->backing_dev_info);
error_splat_bdi:
deactivate_locked_super(s);
- dprintk("<-- nfs_xdev_get_sb() = %d [splat]\n", error);
- return error;
+ dprintk("<-- nfs_xdev_mount() = %d [splat]\n", error);
+ return ERR_PTR(error);
}
#ifdef CONFIG_NFS_V4
/*
* Get the superblock for the NFS4 root partition
*/
-static int nfs4_remote_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data, struct vfsmount *mnt)
+static struct dentry *
+nfs4_remote_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *raw_data)
{
struct nfs_parsed_mount_data *data = raw_data;
struct super_block *s;
goto error_splat_root;
s->s_flags |= MS_ACTIVE;
- mnt->mnt_sb = s;
- mnt->mnt_root = mntroot;
- error = 0;
+
+ security_free_mnt_opts(&data->lsm_opts);
+ nfs_free_fhandle(mntfh);
+ return mntroot;
out:
security_free_mnt_opts(&data->lsm_opts);
out_free_fh:
nfs_free_fhandle(mntfh);
- return error;
+ return ERR_PTR(error);
out_free:
nfs_free_server(server);
/*
* Clone an NFS4 server record on xdev traversal (FSID-change)
*/
-static int nfs4_xdev_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *raw_data,
- struct vfsmount *mnt)
+static struct dentry *
+nfs4_xdev_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *raw_data)
{
struct nfs_clone_mount *data = raw_data;
struct super_block *s;
};
int error;
- dprintk("--> nfs4_xdev_get_sb()\n");
+ dprintk("--> nfs4_xdev_mount()\n");
/* create a new volume representation */
server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr);
}
s->s_flags |= MS_ACTIVE;
- mnt->mnt_sb = s;
- mnt->mnt_root = mntroot;
security_sb_clone_mnt_opts(data->sb, s);
- dprintk("<-- nfs4_xdev_get_sb() = 0\n");
- return 0;
+ dprintk("<-- nfs4_xdev_mount() = 0\n");
+ return mntroot;
out_err_nosb:
nfs_free_server(server);
out_err_noserver:
- dprintk("<-- nfs4_xdev_get_sb() = %d [error]\n", error);
- return error;
+ dprintk("<-- nfs4_xdev_mount() = %d [error]\n", error);
+ return ERR_PTR(error);
error_splat_super:
if (server && !s->s_root)
bdi_unregister(&server->backing_dev_info);
error_splat_bdi:
deactivate_locked_super(s);
- dprintk("<-- nfs4_xdev_get_sb() = %d [splat]\n", error);
- return error;
+ dprintk("<-- nfs4_xdev_mount() = %d [splat]\n", error);
+ return ERR_PTR(error);
}
-static int nfs4_remote_referral_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *raw_data,
- struct vfsmount *mnt)
+static struct dentry *
+nfs4_remote_referral_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *raw_data)
{
struct nfs_clone_mount *data = raw_data;
struct super_block *s;
}
s->s_flags |= MS_ACTIVE;
- mnt->mnt_sb = s;
- mnt->mnt_root = mntroot;
security_sb_clone_mnt_opts(data->sb, s);
nfs_free_fhandle(mntfh);
dprintk("<-- nfs4_referral_get_sb() = 0\n");
- return 0;
+ return mntroot;
out_err_nosb:
nfs_free_server(server);
nfs_free_fhandle(mntfh);
out_err_nofh:
dprintk("<-- nfs4_referral_get_sb() = %d [error]\n", error);
- return error;
+ return ERR_PTR(error);
error_splat_super:
if (server && !s->s_root)
deactivate_locked_super(s);
nfs_free_fhandle(mntfh);
dprintk("<-- nfs4_referral_get_sb() = %d [splat]\n", error);
- return error;
+ return ERR_PTR(error);
}
/*
/* set up nfs_renamedata */
data->old_dir = old_dir;
- atomic_inc(&old_dir->i_count);
+ ihold(old_dir);
data->new_dir = new_dir;
- atomic_inc(&new_dir->i_count);
+ ihold(new_dir);
data->old_dentry = dget(old_dentry);
data->new_dentry = dget(new_dentry);
nfs_fattr_init(&data->old_fattr);
dp->dl_flock = NULL;
}
-/*
- * Set the delegation file_lock back pointer.
- *
- * Called from setlease() with lock_kernel() held.
- */
-static
-void nfsd_copy_lock_deleg_cb(struct file_lock *new, struct file_lock *fl)
-{
- struct nfs4_delegation *dp = (struct nfs4_delegation *)new->fl_owner;
-
- dprintk("NFSD: nfsd_copy_lock_deleg_cb: new fl %p dp %p\n", new, dp);
- if (!dp)
- return;
- dp->dl_flock = new;
-}
-
/*
* Called from setlease() with lock_kernel() held
*/
static const struct lock_manager_operations nfsd_lease_mng_ops = {
.fl_break = nfsd_break_deleg_cb,
.fl_release_private = nfsd_release_deleg_cb,
- .fl_copy_lock = nfsd_copy_lock_deleg_cb,
.fl_mylease = nfsd_same_client_deleg_cb,
.fl_change = nfsd_change_deleg_cb,
};
fl->fl_file = find_readable_file(stp->st_file);
BUG_ON(!fl->fl_file);
fl->fl_pid = current->tgid;
+ dp->dl_flock = fl;
/* vfs_setlease checks to see if delegation should be handed out.
* the lock_manager callbacks fl_mylease and fl_change are used
*/
if ((status = vfs_setlease(fl->fl_file, fl->fl_type, &fl))) {
dprintk("NFSD: setlease failed [%d], no delegation\n", status);
+ dp->dl_flock = NULL;
+ locks_free_lock(fl);
unhash_delegation(dp);
flag = NFS4_OPEN_DELEGATE_NONE;
goto out;
return simple_fill_super(sb, 0x6e667364, nfsd_files);
}
-static int nfsd_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *nfsd_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, nfsd_fill_super, mnt);
+ return mount_single(fs_type, flags, data, nfsd_fill_super);
}
static struct file_system_type nfsd_fs_type = {
.owner = THIS_MODULE,
.name = "nfsd",
- .get_sb = nfsd_get_sb,
+ .mount = nfsd_mount,
.kill_sb = kill_litter_super,
};
return (void *)s->s_bdev == data;
}
-static int
-nilfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *
+nilfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
struct nilfs_super_data sd;
struct super_block *s;
sd.bdev = open_bdev_exclusive(dev_name, mode, fs_type);
if (IS_ERR(sd.bdev))
- return PTR_ERR(sd.bdev);
+ return ERR_CAST(sd.bdev);
sd.cno = 0;
sd.flags = flags;
if (!s_new)
close_bdev_exclusive(sd.bdev, mode);
- mnt->mnt_sb = s;
- mnt->mnt_root = root_dentry;
- return 0;
+ return root_dentry;
failed_super:
deactivate_locked_super(s);
failed:
if (!s_new)
close_bdev_exclusive(sd.bdev, mode);
- return err;
+ return ERR_PTR(err);
}
struct file_system_type nilfs_fs_type = {
.owner = THIS_MODULE,
.name = "nilfs2",
- .get_sb = nilfs_get_sb,
+ .mount = nilfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
source "fs/notify/dnotify/Kconfig"
source "fs/notify/inotify/Kconfig"
-#source "fs/notify/fanotify/Kconfig"
+source "fs/notify/fanotify/Kconfig"
BUILD_BUG_ON(FAN_Q_OVERFLOW != FS_Q_OVERFLOW);
BUILD_BUG_ON(FAN_OPEN_PERM != FS_OPEN_PERM);
BUILD_BUG_ON(FAN_ACCESS_PERM != FS_ACCESS_PERM);
+ BUILD_BUG_ON(FAN_ONDIR != FS_ISDIR);
pr_debug("%s: group=%p event=%p\n", __func__, group, event);
__u32 event_mask, void *data, int data_type)
{
__u32 marks_mask, marks_ignored_mask;
+ struct path *path = data;
pr_debug("%s: group=%p to_tell=%p inode_mark=%p vfsmnt_mark=%p "
"mask=%x data=%p data_type=%d\n", __func__, group, to_tell,
inode_mark, vfsmnt_mark, event_mask, data, data_type);
- /* sorry, fanotify only gives a damn about files and dirs */
- if (!S_ISREG(to_tell->i_mode) &&
- !S_ISDIR(to_tell->i_mode))
- return false;
-
/* if we don't have enough info to send an event to userspace say no */
if (data_type != FSNOTIFY_EVENT_PATH)
return false;
+ /* sorry, fanotify only gives a damn about files and dirs */
+ if (!S_ISREG(path->dentry->d_inode->i_mode) &&
+ !S_ISDIR(path->dentry->d_inode->i_mode))
+ return false;
+
if (inode_mark && vfsmnt_mark) {
marks_mask = (vfsmnt_mark->mask | inode_mark->mask);
marks_ignored_mask = (vfsmnt_mark->ignored_mask | inode_mark->ignored_mask);
BUG();
}
+ if (S_ISDIR(path->dentry->d_inode->i_mode) &&
+ (marks_ignored_mask & FS_ISDIR))
+ return false;
+
if (event_mask & marks_mask & ~marks_ignored_mask)
return true;
return false;
}
+static void fanotify_free_group_priv(struct fsnotify_group *group)
+{
+ struct user_struct *user;
+
+ user = group->fanotify_data.user;
+ atomic_dec(&user->fanotify_listeners);
+ free_uid(user);
+}
+
const struct fsnotify_ops fanotify_fsnotify_ops = {
.handle_event = fanotify_handle_event,
.should_send_event = fanotify_should_send_event,
- .free_group_priv = NULL,
+ .free_group_priv = fanotify_free_group_priv,
.free_event_priv = NULL,
.freeing_mark = NULL,
};
#include <asm/ioctls.h>
+#define FANOTIFY_DEFAULT_MAX_EVENTS 16384
+#define FANOTIFY_DEFAULT_MAX_MARKS 8192
+#define FANOTIFY_DEFAULT_MAX_LISTENERS 128
+
extern const struct fsnotify_ops fanotify_fsnotify_ops;
static struct kmem_cache *fanotify_mark_cache __read_mostly;
ret = -EAGAIN;
if (file->f_flags & O_NONBLOCK)
break;
- ret = -EINTR;
+ ret = -ERESTARTSYS;
if (signal_pending(current))
break;
static int fanotify_release(struct inode *ignored, struct file *file)
{
struct fsnotify_group *group = file->private_data;
- struct fanotify_response_event *re, *lre;
-
- pr_debug("%s: file=%p group=%p\n", __func__, file, group);
#ifdef CONFIG_FANOTIFY_ACCESS_PERMISSIONS
+ struct fanotify_response_event *re, *lre;
+
mutex_lock(&group->fanotify_data.access_mutex);
group->fanotify_data.bypass_perm = true;
__u32 mask,
unsigned int flags)
{
- __u32 oldmask;
+ __u32 oldmask = -1;
spin_lock(&fsn_mark->lock);
if (!(flags & FAN_MARK_IGNORED_MASK)) {
oldmask = fsn_mark->mask;
fsnotify_set_mark_mask_locked(fsn_mark, (oldmask | mask));
} else {
- oldmask = fsn_mark->ignored_mask;
- fsnotify_set_mark_ignored_mask_locked(fsn_mark, (oldmask | mask));
+ __u32 tmask = fsn_mark->ignored_mask | mask;
+ fsnotify_set_mark_ignored_mask_locked(fsn_mark, tmask);
if (flags & FAN_MARK_IGNORED_SURV_MODIFY)
fsn_mark->flags |= FSNOTIFY_MARK_FLAG_IGNORED_SURV_MODIFY;
}
+
+ if (!(flags & FAN_MARK_ONDIR)) {
+ __u32 tmask = fsn_mark->ignored_mask | FAN_ONDIR;
+ fsnotify_set_mark_ignored_mask_locked(fsn_mark, tmask);
+ }
+
spin_unlock(&fsn_mark->lock);
return mask & ~oldmask;
if (!fsn_mark) {
int ret;
+ if (atomic_read(&group->num_marks) > group->fanotify_data.max_marks)
+ return -ENOSPC;
+
fsn_mark = kmem_cache_alloc(fanotify_mark_cache, GFP_KERNEL);
if (!fsn_mark)
return -ENOMEM;
pr_debug("%s: group=%p inode=%p\n", __func__, group, inode);
+ /*
+ * If some other task has this inode open for write we should not add
+ * an ignored mark, unless that ignored mark is supposed to survive
+ * modification changes anyway.
+ */
+ if ((flags & FAN_MARK_IGNORED_MASK) &&
+ !(flags & FAN_MARK_IGNORED_SURV_MODIFY) &&
+ (atomic_read(&inode->i_writecount) > 0))
+ return 0;
+
fsn_mark = fsnotify_find_inode_mark(group, inode);
if (!fsn_mark) {
int ret;
+ if (atomic_read(&group->num_marks) > group->fanotify_data.max_marks)
+ return -ENOSPC;
+
fsn_mark = kmem_cache_alloc(fanotify_mark_cache, GFP_KERNEL);
if (!fsn_mark)
return -ENOMEM;
{
struct fsnotify_group *group;
int f_flags, fd;
+ struct user_struct *user;
pr_debug("%s: flags=%d event_f_flags=%d\n",
__func__, flags, event_f_flags);
if (flags & ~FAN_ALL_INIT_FLAGS)
return -EINVAL;
+ user = get_current_user();
+ if (atomic_read(&user->fanotify_listeners) > FANOTIFY_DEFAULT_MAX_LISTENERS) {
+ free_uid(user);
+ return -EMFILE;
+ }
+
f_flags = O_RDWR | FMODE_NONOTIFY;
if (flags & FAN_CLOEXEC)
f_flags |= O_CLOEXEC;
if (IS_ERR(group))
return PTR_ERR(group);
+ group->fanotify_data.user = user;
+ atomic_inc(&user->fanotify_listeners);
+
group->fanotify_data.f_flags = event_f_flags;
#ifdef CONFIG_FANOTIFY_ACCESS_PERMISSIONS
mutex_init(&group->fanotify_data.access_mutex);
init_waitqueue_head(&group->fanotify_data.access_waitq);
INIT_LIST_HEAD(&group->fanotify_data.access_list);
#endif
+ switch (flags & FAN_ALL_CLASS_BITS) {
+ case FAN_CLASS_NOTIF:
+ group->priority = FS_PRIO_0;
+ break;
+ case FAN_CLASS_CONTENT:
+ group->priority = FS_PRIO_1;
+ break;
+ case FAN_CLASS_PRE_CONTENT:
+ group->priority = FS_PRIO_2;
+ break;
+ default:
+ fd = -EINVAL;
+ goto out_put_group;
+ }
+
+ if (flags & FAN_UNLIMITED_QUEUE) {
+ fd = -EPERM;
+ if (!capable(CAP_SYS_ADMIN))
+ goto out_put_group;
+ group->max_events = UINT_MAX;
+ } else {
+ group->max_events = FANOTIFY_DEFAULT_MAX_EVENTS;
+ }
+
+ if (flags & FAN_UNLIMITED_MARKS) {
+ fd = -EPERM;
+ if (!capable(CAP_SYS_ADMIN))
+ goto out_put_group;
+ group->fanotify_data.max_marks = UINT_MAX;
+ } else {
+ group->fanotify_data.max_marks = FANOTIFY_DEFAULT_MAX_MARKS;
+ }
fd = anon_inode_getfd("[fanotify]", &fanotify_fops, group, f_flags);
if (fd < 0)
default:
return -EINVAL;
}
+
+ if (mask & FAN_ONDIR) {
+ flags |= FAN_MARK_ONDIR;
+ mask &= ~FAN_ONDIR;
+ }
+
#ifdef CONFIG_FANOTIFY_ACCESS_PERMISSIONS
if (mask & ~(FAN_ALL_EVENTS | FAN_ALL_PERM_EVENTS | FAN_EVENT_ON_CHILD))
#else
ret = -EINVAL;
if (unlikely(filp->f_op != &fanotify_fops))
goto fput_and_out;
+ group = filp->private_data;
+
+ /*
+ * group->priority == FS_PRIO_0 == FAN_CLASS_NOTIF. These are not
+ * allowed to set permissions events.
+ */
+ ret = -EINVAL;
+ if (mask & FAN_ALL_PERM_EVENTS &&
+ group->priority == FS_PRIO_0)
+ goto fput_and_out;
ret = fanotify_find_path(dfd, pathname, &path, flags);
if (ret)
inode = path.dentry->d_inode;
else
mnt = path.mnt;
- group = filp->private_data;
/* create/update an inode mark */
switch (flags & (FAN_MARK_ADD | FAN_MARK_REMOVE | FAN_MARK_FLUSH)) {
}
/* Notify this dentry's parent about a child's events. */
-void __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
+int __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
{
struct dentry *parent;
struct inode *p_inode;
+ int ret = 0;
if (!dentry)
dentry = path->dentry;
if (!(dentry->d_flags & DCACHE_FSNOTIFY_PARENT_WATCHED))
- return;
+ return 0;
parent = dget_parent(dentry);
p_inode = parent->d_inode;
mask |= FS_EVENT_ON_CHILD;
if (path)
- fsnotify(p_inode, mask, path, FSNOTIFY_EVENT_PATH,
- dentry->d_name.name, 0);
+ ret = fsnotify(p_inode, mask, path, FSNOTIFY_EVENT_PATH,
+ dentry->d_name.name, 0);
else
- fsnotify(p_inode, mask, dentry->d_inode, FSNOTIFY_EVENT_INODE,
- dentry->d_name.name, 0);
+ ret = fsnotify(p_inode, mask, dentry->d_inode, FSNOTIFY_EVENT_INODE,
+ dentry->d_name.name, 0);
}
dput(parent);
+
+ return ret;
}
EXPORT_SYMBOL_GPL(__fsnotify_parent);
if (inode_group > vfsmount_group) {
/* handle inode */
- send_to_group(to_tell, NULL, inode_mark, NULL, mask, data,
- data_is, cookie, file_name, &event);
+ ret = send_to_group(to_tell, NULL, inode_mark, NULL, mask, data,
+ data_is, cookie, file_name, &event);
/* we didn't use the vfsmount_mark */
vfsmount_group = NULL;
} else if (vfsmount_group > inode_group) {
- send_to_group(to_tell, mnt, NULL, vfsmount_mark, mask, data,
- data_is, cookie, file_name, &event);
+ ret = send_to_group(to_tell, mnt, NULL, vfsmount_mark, mask, data,
+ data_is, cookie, file_name, &event);
inode_group = NULL;
} else {
- send_to_group(to_tell, mnt, inode_mark, vfsmount_mark,
- mask, data, data_is, cookie, file_name,
- &event);
+ ret = send_to_group(to_tell, mnt, inode_mark, vfsmount_mark,
+ mask, data, data_is, cookie, file_name,
+ &event);
}
+ if (ret && (mask & ALL_FSNOTIFY_PERM_EVENTS))
+ goto out;
+
if (inode_group)
inode_node = srcu_dereference(inode_node->next,
&fsnotify_mark_srcu);
vfsmount_node = srcu_dereference(vfsmount_node->next,
&fsnotify_mark_srcu);
}
-
+ ret = 0;
+out:
srcu_read_unlock(&fsnotify_mark_srcu, idx);
/*
* fsnotify_create_event() took a reference so the event can't be cleaned
* Attach an initialized mark to a given inode.
* These marks may be used for the fsnotify backend to determine which
* event types should be delivered to which group and for which inodes. These
- * marks are ordered according to the group's location in memory.
+ * marks are ordered according to priority, highest number first, and then by
+ * the group's location in memory.
*/
int fsnotify_add_inode_mark(struct fsnotify_mark *mark,
struct fsnotify_group *group, struct inode *inode,
goto out;
}
- if (mark->group < lmark->group)
+ if (mark->group->priority < lmark->group->priority)
+ continue;
+
+ if ((mark->group->priority == lmark->group->priority) &&
+ (mark->group < lmark->group))
continue;
hlist_add_before_rcu(&mark->i.i_list, &lmark->i.i_list);
BUILD_BUG_ON(IN_Q_OVERFLOW != FS_Q_OVERFLOW);
BUILD_BUG_ON(IN_IGNORED != FS_IN_IGNORED);
BUILD_BUG_ON(IN_EXCL_UNLINK != FS_EXCL_UNLINK);
- BUILD_BUG_ON(IN_ISDIR != FS_IN_ISDIR);
+ BUILD_BUG_ON(IN_ISDIR != FS_ISDIR);
BUILD_BUG_ON(IN_ONESHOT != FS_IN_ONESHOT);
BUG_ON(hweight32(ALL_INOTIFY_BITS) != 21);
goto out;
}
- if (mark->group < lmark->group)
+ if (mark->group->priority < lmark->group->priority)
+ continue;
+
+ if ((mark->group->priority == lmark->group->priority) &&
+ (mark->group < lmark->group))
continue;
hlist_add_before_rcu(&mark->m.m_list, &lmark->m.m_list);
/* Driver wide mutex. */
DEFINE_MUTEX(ntfs_lock);
-static int ntfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ntfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ntfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ntfs_fill_super);
}
static struct file_system_type ntfs_fs_type = {
.owner = THIS_MODULE,
.name = "ntfs",
- .get_sb = ntfs_get_sb,
+ .mount = ntfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
.setattr = dlmfs_file_setattr,
};
-static int dlmfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *dlmfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, dlmfs_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, dlmfs_fill_super);
}
static struct file_system_type dlmfs_fs_type = {
.owner = THIS_MODULE,
.name = "ocfs2_dlmfs",
- .get_sb = dlmfs_get_sb,
+ .mount = dlmfs_mount,
.kill_sb = kill_litter_super,
};
return status;
}
-static int ocfs2_get_sb(struct file_system_type *fs_type,
+static struct dentry *ocfs2_mount(struct file_system_type *fs_type,
int flags,
const char *dev_name,
- void *data,
- struct vfsmount *mnt)
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ocfs2_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ocfs2_fill_super);
}
static void ocfs2_kill_sb(struct super_block *sb)
static struct file_system_type ocfs2_fs_type = {
.owner = THIS_MODULE,
.name = "ocfs2",
- .get_sb = ocfs2_get_sb, /* is this called when we mount
- * the fs? */
+ .mount = ocfs2_mount,
.kill_sb = ocfs2_kill_sb,
.fs_flags = FS_REQUIRES_DEV|FS_RENAME_DOES_D_MOVE,
return ret;
}
-static int omfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name,
- void *data, struct vfsmount *m)
+static struct dentry *omfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, omfs_fill_super, m);
+ return mount_bdev(fs_type, flags, dev_name, data, omfs_fill_super);
}
static struct file_system_type omfs_fs_type = {
.owner = THIS_MODULE,
.name = "omfs",
- .get_sb = omfs_get_sb,
+ .mount = omfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
/* Pick up the filp from the open intent */
filp = nd->intent.open.file;
/* Has the filesystem initialised the file for us? */
- if (filp->f_path.dentry == NULL)
+ if (filp->f_path.dentry == NULL) {
+ path_get(&nd->path);
filp = __dentry_open(nd->path.dentry, nd->path.mnt, filp,
NULL, cred);
- else
- path_put(&nd->path);
+ }
return filp;
}
return ret;
}
-static int openprom_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *openprom_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, openprom_fill_super, mnt);
+ return mount_single(fs_type, flags, data, openprom_fill_super)
}
static struct file_system_type openprom_fs_type = {
.owner = THIS_MODULE,
.name = "openpromfs",
- .get_sb = openprom_get_sb,
+ .mount = openprom_mount,
.kill_sb = kill_anon_super,
};
* any operations on the root directory. However, we need a non-trivial
* d_name - pipe: will go nicely and kill the special-casing in procfs.
*/
-static int pipefs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *pipefs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "pipe:", NULL, PIPEFS_MAGIC, mnt);
+ return mount_pseudo(fs_type, "pipe:", NULL, PIPEFS_MAGIC);
}
static struct file_system_type pipe_fs_type = {
.name = "pipefs",
- .get_sb = pipefs_get_sb,
+ .mount = pipefs_mount,
.kill_sb = kill_anon_super,
};
return set_anon_super(sb, NULL);
}
-static int proc_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *proc_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
int err;
struct super_block *sb;
sb = sget(fs_type, proc_test_super, proc_set_super, ns);
if (IS_ERR(sb))
- return PTR_ERR(sb);
+ return ERR_CAST(sb);
if (!sb->s_root) {
sb->s_flags = flags;
err = proc_fill_super(sb);
if (err) {
deactivate_locked_super(sb);
- return err;
+ return ERR_PTR(err);
}
ei = PROC_I(sb->s_root->d_inode);
}
sb->s_flags |= MS_ACTIVE;
- ns->proc_mnt = mnt;
}
- simple_set_mnt(mnt, sb);
- return 0;
+ return dget(sb->s_root);
}
static void proc_kill_sb(struct super_block *sb)
static struct file_system_type proc_fs_type = {
.name = "proc",
- .get_sb = proc_get_sb,
+ .mount = proc_mount,
.kill_sb = proc_kill_sb,
};
return;
}
+ init_pid_ns.proc_mnt = proc_mnt;
proc_symlink("mounts", NULL, "self/mounts");
proc_net_init();
if (IS_ERR(mnt))
return PTR_ERR(mnt);
+ ns->proc_mnt = mnt;
return 0;
}
kmem_cache_destroy(qnx4_inode_cachep);
}
-static int qnx4_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *qnx4_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, qnx4_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, qnx4_fill_super);
}
static struct file_system_type qnx4_fs_type = {
.owner = THIS_MODULE,
.name = "qnx4",
- .get_sb = qnx4_get_sb,
+ .mount = qnx4_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return err;
}
-int ramfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+struct dentry *ramfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, ramfs_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, ramfs_fill_super);
}
-static int rootfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *rootfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags|MS_NOUSER, data, ramfs_fill_super,
- mnt);
+ return mount_nodev(fs_type, flags|MS_NOUSER, data, ramfs_fill_super);
}
static void ramfs_kill_sb(struct super_block *sb)
static struct file_system_type ramfs_fs_type = {
.name = "ramfs",
- .get_sb = ramfs_get_sb,
+ .mount = ramfs_mount,
.kill_sb = ramfs_kill_sb,
};
static struct file_system_type rootfs_fs_type = {
.name = "rootfs",
- .get_sb = rootfs_get_sb,
+ .mount = rootfs_mount,
.kill_sb = kill_litter_super,
};
* them to something that fits in "int" so that others
* won't have to do range checks all the time.
*/
-#define MAX_RW_COUNT (INT_MAX & PAGE_CACHE_MASK)
-
int rw_verify_area(int read_write, struct file *file, loff_t *ppos, size_t count)
{
struct inode *inode;
unsigned long nr_segs, unsigned long fast_segs,
struct iovec *fast_pointer,
struct iovec **ret_pointer)
- {
+{
unsigned long seg;
- ssize_t ret;
+ ssize_t ret;
struct iovec *iov = fast_pointer;
- /*
- * SuS says "The readv() function *may* fail if the iovcnt argument
- * was less than or equal to 0, or greater than {IOV_MAX}. Linux has
- * traditionally returned zero for zero segments, so...
- */
+ /*
+ * SuS says "The readv() function *may* fail if the iovcnt argument
+ * was less than or equal to 0, or greater than {IOV_MAX}. Linux has
+ * traditionally returned zero for zero segments, so...
+ */
if (nr_segs == 0) {
ret = 0;
- goto out;
+ goto out;
}
- /*
- * First get the "struct iovec" from user memory and
- * verify all the pointers
- */
+ /*
+ * First get the "struct iovec" from user memory and
+ * verify all the pointers
+ */
if (nr_segs > UIO_MAXIOV) {
ret = -EINVAL;
- goto out;
+ goto out;
}
if (nr_segs > fast_segs) {
- iov = kmalloc(nr_segs*sizeof(struct iovec), GFP_KERNEL);
+ iov = kmalloc(nr_segs*sizeof(struct iovec), GFP_KERNEL);
if (iov == NULL) {
ret = -ENOMEM;
- goto out;
+ goto out;
}
- }
+ }
if (copy_from_user(iov, uvector, nr_segs*sizeof(*uvector))) {
ret = -EFAULT;
- goto out;
+ goto out;
}
- /*
+ /*
* According to the Single Unix Specification we should return EINVAL
* if an element length is < 0 when cast to ssize_t or if the
* total length would overflow the ssize_t return value of the
* system call.
- */
+ *
+ * Linux caps all read/write calls to MAX_RW_COUNT, and avoids the
+ * overflow case.
+ */
ret = 0;
- for (seg = 0; seg < nr_segs; seg++) {
- void __user *buf = iov[seg].iov_base;
- ssize_t len = (ssize_t)iov[seg].iov_len;
+ for (seg = 0; seg < nr_segs; seg++) {
+ void __user *buf = iov[seg].iov_base;
+ ssize_t len = (ssize_t)iov[seg].iov_len;
/* see if we we're about to use an invalid len or if
* it's about to overflow ssize_t */
- if (len < 0 || (ret + len < ret)) {
+ if (len < 0) {
ret = -EINVAL;
- goto out;
+ goto out;
}
if (unlikely(!access_ok(vrfy_dir(type), buf, len))) {
ret = -EFAULT;
- goto out;
+ goto out;
+ }
+ if (len > MAX_RW_COUNT - ret) {
+ len = MAX_RW_COUNT - ret;
+ iov[seg].iov_len = len;
}
-
ret += len;
- }
+ }
out:
*ret_pointer = iov;
return ret;
#endif
-static int get_super_block(struct file_system_type *fs_type,
+static struct dentry *get_super_block(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, reiserfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, reiserfs_fill_super);
}
static int __init init_reiserfs_fs(void)
struct file_system_type reiserfs_fs_type = {
.owner = THIS_MODULE,
.name = "reiserfs",
- .get_sb = get_super_block,
+ .mount = get_super_block,
.kill_sb = reiserfs_kill_sb,
.fs_flags = FS_REQUIRES_DEV,
};
/*
* get a superblock for mounting
*/
-static int romfs_get_sb(struct file_system_type *fs_type,
+static struct dentry *romfs_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- int ret = -EINVAL;
+ struct dentry *ret = ERR_PTR(-EINVAL);
#ifdef CONFIG_ROMFS_ON_MTD
- ret = get_sb_mtd(fs_type, flags, dev_name, data, romfs_fill_super,
- mnt);
+ ret = mount_mtd(fs_type, flags, dev_name, data, romfs_fill_super);
#endif
#ifdef CONFIG_ROMFS_ON_BLOCK
- if (ret == -EINVAL)
- ret = get_sb_bdev(fs_type, flags, dev_name, data,
- romfs_fill_super, mnt);
+ if (ret == ERR_PTR(-EINVAL))
+ ret = mount_bdev(fs_type, flags, dev_name, data,
+ romfs_fill_super);
#endif
return ret;
}
static struct file_system_type romfs_fs_type = {
.owner = THIS_MODULE,
.name = "romfs",
- .get_sb = romfs_get_sb,
+ .mount = romfs_mount,
.kill_sb = romfs_kill_sb,
.fs_flags = FS_REQUIRES_DEV,
};
}
-static int squashfs_get_sb(struct file_system_type *fs_type, int flags,
- const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *squashfs_mount(struct file_system_type *fs_type, int flags,
+ const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, squashfs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, squashfs_fill_super);
}
static struct file_system_type squashfs_fs_type = {
.owner = THIS_MODULE,
.name = "squashfs",
- .get_sb = squashfs_get_sb,
+ .mount = squashfs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV
};
strncmp(target, name, name_size) == 0) {
/* found xattr */
if (type & SQUASHFS_XATTR_VALUE_OOL) {
- __le64 xattr;
+ __le64 xattr_val;
+ u64 xattr;
/* val is a reference to the real location */
err = squashfs_read_metadata(sb, &val, &start,
&offset, sizeof(val));
if (err < 0)
goto failed;
- err = squashfs_read_metadata(sb, &xattr, &start,
- &offset, sizeof(xattr));
+ err = squashfs_read_metadata(sb, &xattr_val,
+ &start, &offset, sizeof(xattr_val));
if (err < 0)
goto failed;
- xattr = le64_to_cpu(xattr);
+ xattr = le64_to_cpu(xattr_val);
start = SQUASHFS_XATTR_BLK(xattr) +
msblk->xattr_table;
offset = SQUASHFS_XATTR_OFFSET(xattr);
extern __le64 *squashfs_read_xattr_id_table(struct super_block *, u64,
u64 *, int *);
extern int squashfs_xattr_lookup(struct super_block *, unsigned int, int *,
- int *, unsigned long long *);
+ unsigned int *, unsigned long long *);
#else
static inline __le64 *squashfs_read_xattr_id_table(struct super_block *sb,
u64 start, u64 *xattr_table_start, int *xattr_ids)
}
static inline int squashfs_xattr_lookup(struct super_block *sb,
- unsigned int index, int *count, int *size,
+ unsigned int index, int *count, unsigned int *size,
unsigned long long *xattr)
{
return 0;
#include "squashfs_fs_sb.h"
#include "squashfs_fs_i.h"
#include "squashfs.h"
+#include "xattr.h"
/*
* Map xattr id using the xattr id look up table
return set_anon_super(sb, NULL);
}
-int get_sb_ns(struct file_system_type *fs_type, int flags, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+struct dentry *mount_ns(struct file_system_type *fs_type, int flags,
+ void *data, int (*fill_super)(struct super_block *, void *, int))
{
struct super_block *sb;
sb = sget(fs_type, ns_test_super, ns_set_super, data);
if (IS_ERR(sb))
- return PTR_ERR(sb);
+ return ERR_CAST(sb);
if (!sb->s_root) {
int err;
err = fill_super(sb, data, flags & MS_SILENT ? 1 : 0);
if (err) {
deactivate_locked_super(sb);
- return err;
+ return ERR_PTR(err);
}
sb->s_flags |= MS_ACTIVE;
}
- simple_set_mnt(mnt, sb);
- return 0;
+ return dget(sb->s_root);
}
-EXPORT_SYMBOL(get_sb_ns);
+EXPORT_SYMBOL(mount_ns);
#ifdef CONFIG_BLOCK
static int set_bdev_super(struct super_block *s, void *data)
return (void *)s->s_bdev == data;
}
-int get_sb_bdev(struct file_system_type *fs_type,
+struct dentry *mount_bdev(struct file_system_type *fs_type,
int flags, const char *dev_name, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct block_device *bdev;
struct super_block *s;
bdev = open_bdev_exclusive(dev_name, mode, fs_type);
if (IS_ERR(bdev))
- return PTR_ERR(bdev);
+ return ERR_CAST(bdev);
/*
* once the super is inserted into the list by sget, s_umount
bdev->bd_super = s;
}
- simple_set_mnt(mnt, s);
- return 0;
+ return dget(s->s_root);
error_s:
error = PTR_ERR(s);
error_bdev:
close_bdev_exclusive(bdev, mode);
error:
- return error;
+ return ERR_PTR(error);
+}
+EXPORT_SYMBOL(mount_bdev);
+
+int get_sb_bdev(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data,
+ int (*fill_super)(struct super_block *, void *, int),
+ struct vfsmount *mnt)
+{
+ struct dentry *root;
+
+ root = mount_bdev(fs_type, flags, dev_name, data, fill_super);
+ if (IS_ERR(root))
+ return PTR_ERR(root);
+ mnt->mnt_root = root;
+ mnt->mnt_sb = root->d_sb;
+ return 0;
}
EXPORT_SYMBOL(get_sb_bdev);
EXPORT_SYMBOL(kill_block_super);
#endif
-int get_sb_nodev(struct file_system_type *fs_type,
+struct dentry *mount_nodev(struct file_system_type *fs_type,
int flags, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
int error;
struct super_block *s = sget(fs_type, NULL, set_anon_super, NULL);
if (IS_ERR(s))
- return PTR_ERR(s);
+ return ERR_CAST(s);
s->s_flags = flags;
error = fill_super(s, data, flags & MS_SILENT ? 1 : 0);
if (error) {
deactivate_locked_super(s);
- return error;
+ return ERR_PTR(error);
}
s->s_flags |= MS_ACTIVE;
- simple_set_mnt(mnt, s);
- return 0;
+ return dget(s->s_root);
}
+EXPORT_SYMBOL(mount_nodev);
+int get_sb_nodev(struct file_system_type *fs_type,
+ int flags, void *data,
+ int (*fill_super)(struct super_block *, void *, int),
+ struct vfsmount *mnt)
+{
+ struct dentry *root;
+
+ root = mount_nodev(fs_type, flags, data, fill_super);
+ if (IS_ERR(root))
+ return PTR_ERR(root);
+ mnt->mnt_root = root;
+ mnt->mnt_sb = root->d_sb;
+ return 0;
+}
EXPORT_SYMBOL(get_sb_nodev);
static int compare_single(struct super_block *s, void *p)
return 1;
}
-int get_sb_single(struct file_system_type *fs_type,
+struct dentry *mount_single(struct file_system_type *fs_type,
int flags, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt)
+ int (*fill_super)(struct super_block *, void *, int))
{
struct super_block *s;
int error;
s = sget(fs_type, compare_single, set_anon_super, NULL);
if (IS_ERR(s))
- return PTR_ERR(s);
+ return ERR_CAST(s);
if (!s->s_root) {
s->s_flags = flags;
error = fill_super(s, data, flags & MS_SILENT ? 1 : 0);
if (error) {
deactivate_locked_super(s);
- return error;
+ return ERR_PTR(error);
}
s->s_flags |= MS_ACTIVE;
} else {
do_remount_sb(s, flags, data, 0);
}
- simple_set_mnt(mnt, s);
+ return dget(s->s_root);
+}
+EXPORT_SYMBOL(mount_single);
+
+int get_sb_single(struct file_system_type *fs_type,
+ int flags, void *data,
+ int (*fill_super)(struct super_block *, void *, int),
+ struct vfsmount *mnt)
+{
+ struct dentry *root;
+ root = mount_single(fs_type, flags, data, fill_super);
+ if (IS_ERR(root))
+ return PTR_ERR(root);
+ mnt->mnt_root = root;
+ mnt->mnt_sb = root->d_sb;
return 0;
}
vfs_kern_mount(struct file_system_type *type, int flags, const char *name, void *data)
{
struct vfsmount *mnt;
+ struct dentry *root;
char *secdata = NULL;
int error;
goto out_free_secdata;
}
- error = type->get_sb(type, flags, name, data, mnt);
- if (error < 0)
- goto out_free_secdata;
+ if (type->mount) {
+ root = type->mount(type, flags, name, data);
+ if (IS_ERR(root)) {
+ error = PTR_ERR(root);
+ goto out_free_secdata;
+ }
+ mnt->mnt_root = root;
+ mnt->mnt_sb = root->d_sb;
+ } else {
+ error = type->get_sb(type, flags, name, data, mnt);
+ if (error < 0)
+ goto out_free_secdata;
+ }
BUG_ON(!mnt->mnt_sb);
WARN_ON(!mnt->mnt_sb->s_bdi);
mnt->mnt_sb->s_flags |= MS_BORN;
#include "sysfs.h"
-static struct vfsmount *sysfs_mount;
+static struct vfsmount *sysfs_mnt;
struct kmem_cache *sysfs_dir_cachep;
static const struct super_operations sysfs_ops = {
return error;
}
-static int sysfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *sysfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
struct sysfs_super_info *info;
enum kobj_ns_type type;
struct super_block *sb;
int error;
- error = -ENOMEM;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
- goto out;
+ return ERR_PTR(-ENOMEM);
for (type = KOBJ_NS_TYPE_NONE; type < KOBJ_NS_TYPES; type++)
info->ns[type] = kobj_ns_current(type);
sb = sget(fs_type, sysfs_test_super, sysfs_set_super, info);
if (IS_ERR(sb) || sb->s_fs_info != info)
kfree(info);
- if (IS_ERR(sb)) {
- error = PTR_ERR(sb);
- goto out;
- }
+ if (IS_ERR(sb))
+ return ERR_CAST(sb);
if (!sb->s_root) {
sb->s_flags = flags;
error = sysfs_fill_super(sb, data, flags & MS_SILENT ? 1 : 0);
if (error) {
deactivate_locked_super(sb);
- goto out;
+ return ERR_PTR(error);
}
sb->s_flags |= MS_ACTIVE;
}
- simple_set_mnt(mnt, sb);
- error = 0;
-out:
- return error;
+ return dget(sb->s_root);
}
static void sysfs_kill_sb(struct super_block *sb)
static struct file_system_type sysfs_fs_type = {
.name = "sysfs",
- .get_sb = sysfs_get_sb,
+ .mount = sysfs_mount,
.kill_sb = sysfs_kill_sb,
};
err = register_filesystem(&sysfs_fs_type);
if (!err) {
- sysfs_mount = kern_mount(&sysfs_fs_type);
- if (IS_ERR(sysfs_mount)) {
+ sysfs_mnt = kern_mount(&sysfs_fs_type);
+ if (IS_ERR(sysfs_mnt)) {
printk(KERN_ERR "sysfs: could not mount!\n");
- err = PTR_ERR(sysfs_mount);
- sysfs_mount = NULL;
+ err = PTR_ERR(sysfs_mnt);
+ sysfs_mnt = NULL;
unregister_filesystem(&sysfs_fs_type);
goto out_err;
}
/* Every kernel module contains stuff like this. */
-static int sysv_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *sysv_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, sysv_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, sysv_fill_super);
}
-static int v7_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *v7_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, v7_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, v7_fill_super);
}
static struct file_system_type sysv_fs_type = {
.owner = THIS_MODULE,
.name = "sysv",
- .get_sb = sysv_get_sb,
+ .mount = sysv_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
static struct file_system_type v7_fs_type = {
.owner = THIS_MODULE,
.name = "v7",
- .get_sb = v7_get_sb,
+ .mount = v7_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
return c->vi.cdev == *dev;
}
-static int ubifs_get_sb(struct file_system_type *fs_type, int flags,
- const char *name, void *data, struct vfsmount *mnt)
+static struct dentry *ubifs_mount(struct file_system_type *fs_type, int flags,
+ const char *name, void *data)
{
struct ubi_volume_desc *ubi;
struct ubi_volume_info vi;
if (IS_ERR(ubi)) {
dbg_err("cannot open \"%s\", error %d",
name, (int)PTR_ERR(ubi));
- return PTR_ERR(ubi);
+ return ERR_CAST(ubi);
}
ubi_get_volume_info(ubi, &vi);
/* 'fill_super()' opens ubi again so we must close it here */
ubi_close_volume(ubi);
- simple_set_mnt(mnt, sb);
- return 0;
+ return dget(sb->s_root);
out_deact:
deactivate_locked_super(sb);
out_close:
ubi_close_volume(ubi);
- return err;
+ return ERR_PTR(err);
}
static struct file_system_type ubifs_fs_type = {
.name = "ubifs",
.owner = THIS_MODULE,
- .get_sb = ubifs_get_sb,
+ .mount = ubifs_mount,
.kill_sb = kill_anon_super,
};
}
/* UDF filesystem type */
-static int udf_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *udf_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, udf_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, udf_fill_super);
}
static struct file_system_type udf_fstype = {
.owner = THIS_MODULE,
.name = "udf",
- .get_sb = udf_get_sb,
+ .mount = udf_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
.show_options = ufs_show_options,
};
-static int ufs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *ufs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, ufs_fill_super, mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, ufs_fill_super);
}
static struct file_system_type ufs_fs_type = {
.owner = THIS_MODULE,
.name = "ufs",
- .get_sb = ufs_get_sb,
+ .mount = ufs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
goto out_free_sb;
}
-STATIC int
-xfs_fs_get_sb(
+STATIC struct dentry *
+xfs_fs_mount(
struct file_system_type *fs_type,
int flags,
const char *dev_name,
- void *data,
- struct vfsmount *mnt)
+ void *data)
{
- return get_sb_bdev(fs_type, flags, dev_name, data, xfs_fs_fill_super,
- mnt);
+ return mount_bdev(fs_type, flags, dev_name, data, xfs_fs_fill_super);
}
static const struct super_operations xfs_super_operations = {
static struct file_system_type xfs_fs_type = {
.owner = THIS_MODULE,
.name = "xfs",
- .get_sb = xfs_fs_get_sb,
+ .mount = xfs_fs_mount,
.kill_sb = kill_block_super,
.fs_flags = FS_REQUIRES_DEV,
};
__NR_fchown32,
__NR_lchown32,
#endif
+__NR_link,
+#ifdef __NR_linkat
+__NR_linkat,
+#endif
header-y += ext2_fs.h
header-y += fadvise.h
header-y += falloc.h
+header-y += fanotify.h
header-y += fb.h
header-y += fcntl.h
header-y += fd.h
#define AUDIT_EOE 1320 /* End of multi-record event */
#define AUDIT_BPRM_FCAPS 1321 /* Information about fcaps increasing perms */
#define AUDIT_CAPSET 1322 /* Record showing argument to sys_capset */
+#define AUDIT_MMAP 1323 /* Record showing descriptor and flags in mmap */
#define AUDIT_AVC 1400 /* SE Linux avc denial or grant */
#define AUDIT_SELINUX_ERR 1401 /* Internal SE Linux Errors */
const struct cred *new,
const struct cred *old);
extern void __audit_log_capset(pid_t pid, const struct cred *new, const struct cred *old);
+extern void __audit_mmap_fd(int fd, int flags);
static inline void audit_ipc_obj(struct kern_ipc_perm *ipcp)
{
__audit_log_capset(pid, new, old);
}
+static inline void audit_mmap_fd(int fd, int flags)
+{
+ if (unlikely(!audit_dummy_context()))
+ __audit_mmap_fd(fd, flags);
+}
+
extern int audit_n_rules;
extern int audit_signals;
#else
#define audit_mq_getsetattr(d,s) ((void)0)
#define audit_log_bprm_fcaps(b, ncr, ocr) ({ 0; })
#define audit_log_capset(pid, ncr, ocr) ((void)0)
+#define audit_mmap_fd(fd, flags) ((void)0)
#define audit_ptrace(t) ((void)0)
#define audit_n_rules 0
#define audit_signals 0
* @dccps_hc_rx_insert_options - receiver wants to add options when acking
* @dccps_hc_tx_insert_options - sender wants to add options when sending
* @dccps_server_timewait - server holds timewait state on close (RFC 4340, 8.3)
- * @dccps_xmit_timer - timer for when CCID is not ready to send
+ * @dccps_xmitlet - tasklet scheduled by the TX CCID to dequeue data packets
+ * @dccps_xmit_timer - used by the TX CCID to delay sending (rate-based pacing)
* @dccps_syn_rtt - RTT sample from Request/Response exchange (in usecs)
*/
struct dccp_sock {
__u8 dccps_hc_rx_insert_options:1;
__u8 dccps_hc_tx_insert_options:1;
__u8 dccps_server_timewait:1;
+ struct tasklet_struct dccps_xmitlet;
struct timer_list dccps_xmit_timer;
};
/* the following events that user-space can register for */
#define FAN_ACCESS 0x00000001 /* File was accessed */
#define FAN_MODIFY 0x00000002 /* File was modified */
-#define FAN_CLOSE_WRITE 0x00000008 /* Unwrittable file closed */
-#define FAN_CLOSE_NOWRITE 0x00000010 /* Writtable file closed */
+#define FAN_CLOSE_WRITE 0x00000008 /* Writtable file closed */
+#define FAN_CLOSE_NOWRITE 0x00000010 /* Unwrittable file closed */
#define FAN_OPEN 0x00000020 /* File was opened */
-#define FAN_EVENT_ON_CHILD 0x08000000 /* interested in child events */
-
-/* FIXME currently Q's have no limit.... */
#define FAN_Q_OVERFLOW 0x00004000 /* Event queued overflowed */
#define FAN_OPEN_PERM 0x00010000 /* File open in perm check */
#define FAN_ACCESS_PERM 0x00020000 /* File accessed in perm check */
+#define FAN_ONDIR 0x40000000 /* event occurred against dir */
+
+#define FAN_EVENT_ON_CHILD 0x08000000 /* interested in child events */
+
/* helper events */
#define FAN_CLOSE (FAN_CLOSE_WRITE | FAN_CLOSE_NOWRITE) /* close */
#define FAN_CLOEXEC 0x00000001
#define FAN_NONBLOCK 0x00000002
-#define FAN_ALL_INIT_FLAGS (FAN_CLOEXEC | FAN_NONBLOCK)
+/* These are NOT bitwise flags. Both bits are used togther. */
+#define FAN_CLASS_NOTIF 0x00000000
+#define FAN_CLASS_CONTENT 0x00000004
+#define FAN_CLASS_PRE_CONTENT 0x00000008
+#define FAN_ALL_CLASS_BITS (FAN_CLASS_NOTIF | FAN_CLASS_CONTENT | \
+ FAN_CLASS_PRE_CONTENT)
+
+#define FAN_UNLIMITED_QUEUE 0x00000010
+#define FAN_UNLIMITED_MARKS 0x00000020
+
+#define FAN_ALL_INIT_FLAGS (FAN_CLOEXEC | FAN_NONBLOCK | \
+ FAN_ALL_CLASS_BITS | FAN_UNLIMITED_QUEUE |\
+ FAN_UNLIMITED_MARKS)
/* flags used for fanotify_modify_mark() */
#define FAN_MARK_ADD 0x00000001
#define FAN_MARK_IGNORED_MASK 0x00000020
#define FAN_MARK_IGNORED_SURV_MODIFY 0x00000040
#define FAN_MARK_FLUSH 0x00000080
+#ifdef __KERNEL__
+/* not valid from userspace, only kernel internal */
+#define FAN_MARK_ONDIR 0x00000100
+#endif
#define FAN_ALL_MARK_FLAGS (FAN_MARK_ADD |\
FAN_MARK_REMOVE |\
FAN_MARK_ONLYDIR |\
FAN_MARK_MOUNT |\
FAN_MARK_IGNORED_MASK |\
- FAN_MARK_IGNORED_SURV_MODIFY)
+ FAN_MARK_IGNORED_SURV_MODIFY |\
+ FAN_MARK_FLUSH)
/*
* All of the events - we build the list by hand so that we can add flags in
struct fanotify_event_metadata {
__u32 event_len;
__u32 vers;
- __u64 mask;
+ __aligned_u64 mask;
__s32 fd;
__s32 pid;
-} __attribute__ ((packed));
+};
struct fanotify_response {
__s32 fd;
int (*fl_compare_owner)(struct file_lock *, struct file_lock *);
void (*fl_notify)(struct file_lock *); /* unblock callback */
int (*fl_grant)(struct file_lock *, struct file_lock *, int);
- void (*fl_copy_lock)(struct file_lock *, struct file_lock *);
void (*fl_release_private)(struct file_lock *);
void (*fl_break)(struct file_lock *);
int (*fl_mylease)(struct file_lock *, struct file_lock *);
extern int fcntl_getlease(struct file *filp);
/* fs/locks.c */
+void locks_free_lock(struct file_lock *fl);
extern void locks_init_lock(struct file_lock *);
extern struct file_lock * locks_alloc_lock(void);
extern void locks_copy_lock(struct file_lock *, struct file_lock *);
int fs_flags;
int (*get_sb) (struct file_system_type *, int,
const char *, void *, struct vfsmount *);
+ struct dentry *(*mount) (struct file_system_type *, int,
+ const char *, void *);
void (*kill_sb) (struct super_block *);
struct module *owner;
struct file_system_type * next;
struct lock_class_key i_alloc_sem_key;
};
-extern int get_sb_ns(struct file_system_type *fs_type, int flags, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt);
+extern struct dentry *mount_ns(struct file_system_type *fs_type, int flags,
+ void *data, int (*fill_super)(struct super_block *, void *, int));
+extern struct dentry *mount_bdev(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data,
+ int (*fill_super)(struct super_block *, void *, int));
extern int get_sb_bdev(struct file_system_type *fs_type,
int flags, const char *dev_name, void *data,
int (*fill_super)(struct super_block *, void *, int),
struct vfsmount *mnt);
+extern struct dentry *mount_single(struct file_system_type *fs_type,
+ int flags, void *data,
+ int (*fill_super)(struct super_block *, void *, int));
extern int get_sb_single(struct file_system_type *fs_type,
int flags, void *data,
int (*fill_super)(struct super_block *, void *, int),
struct vfsmount *mnt);
+extern struct dentry *mount_nodev(struct file_system_type *fs_type,
+ int flags, void *data,
+ int (*fill_super)(struct super_block *, void *, int));
extern int get_sb_nodev(struct file_system_type *fs_type,
int flags, void *data,
int (*fill_super)(struct super_block *, void *, int),
int (*test)(struct super_block *,void *),
int (*set)(struct super_block *,void *),
void *data);
-extern int get_sb_pseudo(struct file_system_type *, char *,
- const struct super_operations *ops, unsigned long,
- struct vfsmount *mnt);
+extern struct dentry *mount_pseudo(struct file_system_type *, char *,
+ const struct super_operations *ops, unsigned long);
extern void simple_set_mnt(struct vfsmount *mnt, struct super_block *sb);
static inline void sb_mark_dirty(struct super_block *sb)
/* /sys/fs */
extern struct kobject *fs_kobj;
+#define MAX_RW_COUNT (INT_MAX & PAGE_CACHE_MASK)
extern int rw_verify_area(int, struct file *, loff_t *, size_t);
#define FLOCK_VERIFY_READ 1
}
/* Notify this dentry's parent about a child's events. */
-static inline void fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
+static inline int fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
{
if (!dentry)
dentry = path->dentry;
- __fsnotify_parent(path, dentry, mask);
+ return __fsnotify_parent(path, dentry, mask);
}
/* simple call site for access decisions */
struct path *path = &file->f_path;
struct inode *inode = path->dentry->d_inode;
__u32 fsnotify_mask = 0;
+ int ret;
if (file->f_mode & FMODE_NONOTIFY)
return 0;
else
BUG();
+ ret = fsnotify_parent(path, NULL, fsnotify_mask);
+ if (ret)
+ return ret;
+
return fsnotify(inode, fsnotify_mask, path, FSNOTIFY_EVENT_PATH, NULL, 0);
}
old_dir_mask |= FS_DN_RENAME;
if (isdir) {
- old_dir_mask |= FS_IN_ISDIR;
- new_dir_mask |= FS_IN_ISDIR;
+ old_dir_mask |= FS_ISDIR;
+ new_dir_mask |= FS_ISDIR;
}
fsnotify(old_dir, old_dir_mask, old_dir, FSNOTIFY_EVENT_INODE, old_name, fs_cookie);
__u32 mask = FS_DELETE;
if (isdir)
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
fsnotify_parent(NULL, dentry, mask);
}
*/
static inline void fsnotify_mkdir(struct inode *inode, struct dentry *dentry)
{
- __u32 mask = (FS_CREATE | FS_IN_ISDIR);
+ __u32 mask = (FS_CREATE | FS_ISDIR);
struct inode *d_inode = dentry->d_inode;
audit_inode_child(dentry, inode);
__u32 mask = FS_ACCESS;
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
if (!(file->f_mode & FMODE_NONOTIFY)) {
fsnotify_parent(path, NULL, mask);
__u32 mask = FS_MODIFY;
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
if (!(file->f_mode & FMODE_NONOTIFY)) {
fsnotify_parent(path, NULL, mask);
__u32 mask = FS_OPEN;
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
- if (!(file->f_mode & FMODE_NONOTIFY)) {
- fsnotify_parent(path, NULL, mask);
- fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0);
- }
+ /* FMODE_NONOTIFY must never be set from user */
+ file->f_mode &= ~FMODE_NONOTIFY;
+
+ fsnotify_parent(path, NULL, mask);
+ fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0);
}
/*
__u32 mask = (mode & FMODE_WRITE) ? FS_CLOSE_WRITE : FS_CLOSE_NOWRITE;
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
if (!(file->f_mode & FMODE_NONOTIFY)) {
fsnotify_parent(path, NULL, mask);
__u32 mask = FS_ATTRIB;
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
fsnotify_parent(NULL, dentry, mask);
fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0);
if (mask) {
if (S_ISDIR(inode->i_mode))
- mask |= FS_IN_ISDIR;
+ mask |= FS_ISDIR;
fsnotify_parent(NULL, dentry, mask);
fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0);
#define FS_ACCESS_PERM 0x00020000 /* access event in a permissions hook */
#define FS_EXCL_UNLINK 0x04000000 /* do not send events if object is unlinked */
-#define FS_IN_ISDIR 0x40000000 /* event occurred against dir */
+#define FS_ISDIR 0x40000000 /* event occurred against dir */
#define FS_IN_ONESHOT 0x80000000 /* only send event once */
#define FS_DN_RENAME 0x10000000 /* file renamed */
#define FS_MOVE (FS_MOVED_FROM | FS_MOVED_TO)
+#define ALL_FSNOTIFY_PERM_EVENTS (FS_OPEN_PERM | FS_ACCESS_PERM)
+
#define ALL_FSNOTIFY_EVENTS (FS_ACCESS | FS_MODIFY | FS_ATTRIB | \
FS_CLOSE_WRITE | FS_CLOSE_NOWRITE | FS_OPEN | \
FS_MOVED_FROM | FS_MOVED_TO | FS_CREATE | \
FS_DELETE | FS_DELETE_SELF | FS_MOVE_SELF | \
FS_UNMOUNT | FS_Q_OVERFLOW | FS_IN_IGNORED | \
FS_OPEN_PERM | FS_ACCESS_PERM | FS_EXCL_UNLINK | \
- FS_IN_ISDIR | FS_IN_ONESHOT | FS_DN_RENAME | \
+ FS_ISDIR | FS_IN_ONESHOT | FS_DN_RENAME | \
FS_DN_MULTISHOT | FS_EVENT_ON_CHILD)
struct fsnotify_group;
wait_queue_head_t notification_waitq; /* read() on the notification file blocks on this waitq */
unsigned int q_len; /* events on the queue */
unsigned int max_events; /* maximum events allowed on the list */
+ /*
+ * Valid fsnotify group priorities. Events are send in order from highest
+ * priority to lowest priority. We default to the lowest priority.
+ */
+ #define FS_PRIO_0 0 /* normal notifiers, no permissions */
+ #define FS_PRIO_1 1 /* fanotify content based access control */
+ #define FS_PRIO_2 2 /* fanotify pre-content access */
+ unsigned int priority;
/* stores all fastpath marks assoc with this group so they can be cleaned on unregister */
spinlock_t mark_lock; /* protect marks_list */
bool bypass_perm; /* protected by access_mutex */
#endif /* CONFIG_FANOTIFY_ACCESS_PERMISSIONS */
int f_flags;
+ unsigned int max_marks;
+ struct user_struct *user;
} fanotify_data;
#endif /* CONFIG_FANOTIFY */
};
struct fsnotify_inode_mark i;
struct fsnotify_vfsmount_mark m;
};
- __u32 ignored_mask; /* events types to ignore */
struct list_head free_g_list; /* tmp list used when freeing this mark */
+ __u32 ignored_mask; /* events types to ignore */
#define FSNOTIFY_MARK_FLAG_INODE 0x01
#define FSNOTIFY_MARK_FLAG_VFSMOUNT 0x02
#define FSNOTIFY_MARK_FLAG_OBJECT_PINNED 0x04
/* main fsnotify call to send events */
extern int fsnotify(struct inode *to_tell, __u32 mask, void *data, int data_is,
const unsigned char *name, u32 cookie);
-extern void __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask);
+extern int __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask);
extern void __fsnotify_inode_delete(struct inode *inode);
extern void __fsnotify_vfsmount_delete(struct vfsmount *mnt);
extern u32 fsnotify_get_cookie(void);
return 0;
}
-static inline void __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
-{}
+static inline int __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask)
+{
+ return 0;
+}
static inline void __fsnotify_inode_delete(struct inode *inode)
{}
irq_free_descs(irq, 1);
}
+static inline int irq_reserve_irq(unsigned int irq)
+{
+ return irq_reserve_irqs(irq, 1);
+}
+
#endif /* CONFIG_GENERIC_HARDIRQS */
#endif /* !CONFIG_S390 */
else
#ifdef CONFIG_SMP
-#define irq_node(irq) (irq_to_desc(irq)->node)
+#define irq_node(irq) (irq_get_irq_data(irq)->node)
#else
#define irq_node(irq) 0
#endif
#ifndef _LINUX_JUMP_LABEL_H
#define _LINUX_JUMP_LABEL_H
-#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_HAVE_ARCH_JUMP_LABEL)
+#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_JUMP_LABEL)
# include <asm/jump_label.h>
# define HAVE_JUMP_LABEL
#endif
extern struct jump_entry __start___jump_table[];
extern struct jump_entry __stop___jump_table[];
+extern void jump_label_lock(void);
+extern void jump_label_unlock(void);
extern void arch_jump_label_transform(struct jump_entry *entry,
enum jump_label_type type);
extern void arch_jump_label_text_poke_early(jump_label_t addr);
return 0;
}
+static inline void jump_label_lock(void) {}
+static inline void jump_label_unlock(void) {}
+
#endif
#define COND_STMT(key, stmt) \
*/
extern int kgdb_skipexception(int exception, struct pt_regs *regs);
-/**
- * kgdb_disable_hw_debug - (optional) Disable hardware debugging hook
- * @regs: Current &struct pt_regs.
- *
- * This function will be called if the particular architecture must
- * disable hardware debugging while it is processing gdb packets or
- * handling exception.
- */
-extern void kgdb_disable_hw_debug(struct pt_regs *regs);
-
struct tasklet_struct;
struct task_struct;
struct uart_port;
* breakpoint.
* @remove_hw_breakpoint: Allow an architecture to specify how to remove a
* hardware breakpoint.
+ * @disable_hw_break: Allow an architecture to specify how to disable
+ * hardware breakpoints for a single cpu.
* @remove_all_hw_break: Allow an architecture to specify how to remove all
* hardware breakpoints.
* @correct_hw_break: Allow an architecture to specify how to correct the
int (*remove_breakpoint)(unsigned long, char *);
int (*set_hw_breakpoint)(unsigned long, int, enum kgdb_bptype);
int (*remove_hw_breakpoint)(unsigned long, int, enum kgdb_bptype);
+ void (*disable_hw_break)(struct pt_regs *regs);
void (*remove_all_hw_break)(void);
void (*correct_hw_break)(void);
};
#define MARVELL_PHY_ID_88E1121R 0x01410cb0
#define MARVELL_PHY_ID_88E1145 0x01410cd0
#define MARVELL_PHY_ID_88E1240 0x01410e30
-#define MARVELL_PHY_ID_88EC048 0x01410e90
+#define MARVELL_PHY_ID_88E1318S 0x01410e90
/* struct phy_device dev_flags definitions */
#define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x00000001
#define NAND_BBT_PERCHIP 0x00000080
/* bbt has a version counter at offset veroffs */
#define NAND_BBT_VERSION 0x00000100
-/* Create a bbt if none axists */
+/* Create a bbt if none exists */
#define NAND_BBT_CREATE 0x00000200
/* Search good / bad pattern through all pages of a block */
#define NAND_BBT_SCANALLPAGES 0x00000400
#define NAND_BBT_SCANBYTE1AND6 0x00100000
/* The nand_bbt_descr was created dynamicaly and must be freed */
#define NAND_BBT_DYNAMICSTRUCT 0x00200000
+/* The bad block table does not OOB for marker */
+#define NAND_BBT_NO_OOB 0x00400000
/* The maximum number of blocks to scan for a bbt */
#define NAND_BBT_SCAN_MAXBLOCKS 4
must be of the same type. */
int mfr, id;
int numchips;
+ map_word sector_erase_cmd;
unsigned long chipshift; /* Because they're of the same type */
const char *im_name; /* inter_module name for cmdset_setup */
struct flchip chips[0]; /* per-chip data structure for each chip */
--- /dev/null
+/*
+ * incude/mtd/fsmc.h
+ *
+ * ST Microelectronics
+ * Flexible Static Memory Controller (FSMC)
+ * platform data interface and header file
+ *
+ * Copyright © 2010 ST Microelectronics
+ * Vipin Kumar <vipin.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MTD_FSMC_H
+#define __MTD_FSMC_H
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/types.h>
+#include <linux/mtd/partitions.h>
+#include <asm/param.h>
+
+#define FSMC_NAND_BW8 1
+#define FSMC_NAND_BW16 2
+
+/*
+ * The placement of the Command Latch Enable (CLE) and
+ * Address Latch Enable (ALE) is twised around in the
+ * SPEAR310 implementation.
+ */
+#if defined(CONFIG_MACH_SPEAR310)
+#define PLAT_NAND_CLE (1 << 17)
+#define PLAT_NAND_ALE (1 << 16)
+#else
+#define PLAT_NAND_CLE (1 << 16)
+#define PLAT_NAND_ALE (1 << 17)
+#endif
+
+#define FSMC_MAX_NOR_BANKS 4
+#define FSMC_MAX_NAND_BANKS 4
+
+#define FSMC_FLASH_WIDTH8 1
+#define FSMC_FLASH_WIDTH16 2
+
+struct fsmc_nor_bank_regs {
+ uint32_t ctrl;
+ uint32_t ctrl_tim;
+};
+
+/* ctrl register definitions */
+#define BANK_ENABLE (1 << 0)
+#define MUXED (1 << 1)
+#define NOR_DEV (2 << 2)
+#define WIDTH_8 (0 << 4)
+#define WIDTH_16 (1 << 4)
+#define RSTPWRDWN (1 << 6)
+#define WPROT (1 << 7)
+#define WRT_ENABLE (1 << 12)
+#define WAIT_ENB (1 << 13)
+
+/* ctrl_tim register definitions */
+
+struct fsms_nand_bank_regs {
+ uint32_t pc;
+ uint32_t sts;
+ uint32_t comm;
+ uint32_t attrib;
+ uint32_t ioata;
+ uint32_t ecc1;
+ uint32_t ecc2;
+ uint32_t ecc3;
+};
+
+#define FSMC_NOR_REG_SIZE 0x40
+
+struct fsmc_regs {
+ struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
+ uint8_t reserved_1[0x40 - 0x20];
+ struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
+ uint8_t reserved_2[0xfe0 - 0xc0];
+ uint32_t peripid0; /* 0xfe0 */
+ uint32_t peripid1; /* 0xfe4 */
+ uint32_t peripid2; /* 0xfe8 */
+ uint32_t peripid3; /* 0xfec */
+ uint32_t pcellid0; /* 0xff0 */
+ uint32_t pcellid1; /* 0xff4 */
+ uint32_t pcellid2; /* 0xff8 */
+ uint32_t pcellid3; /* 0xffc */
+};
+
+#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
+
+/* pc register definitions */
+#define FSMC_RESET (1 << 0)
+#define FSMC_WAITON (1 << 1)
+#define FSMC_ENABLE (1 << 2)
+#define FSMC_DEVTYPE_NAND (1 << 3)
+#define FSMC_DEVWID_8 (0 << 4)
+#define FSMC_DEVWID_16 (1 << 4)
+#define FSMC_ECCEN (1 << 6)
+#define FSMC_ECCPLEN_512 (0 << 7)
+#define FSMC_ECCPLEN_256 (1 << 7)
+#define FSMC_TCLR_1 (1 << 9)
+#define FSMC_TAR_1 (1 << 13)
+
+/* sts register definitions */
+#define FSMC_CODE_RDY (1 << 15)
+
+/* comm register definitions */
+#define FSMC_TSET_0 (0 << 0)
+#define FSMC_TWAIT_6 (6 << 8)
+#define FSMC_THOLD_4 (4 << 16)
+#define FSMC_THIZ_1 (1 << 24)
+
+/* peripid2 register definitions */
+#define FSMC_REVISION_MSK (0xf)
+#define FSMC_REVISION_SHFT (0x4)
+
+#define FSMC_VER1 1
+#define FSMC_VER2 2
+#define FSMC_VER3 3
+#define FSMC_VER4 4
+#define FSMC_VER5 5
+#define FSMC_VER6 6
+#define FSMC_VER7 7
+#define FSMC_VER8 8
+
+static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
+{
+ return (readl(®s->peripid2) >> FSMC_REVISION_SHFT) &
+ FSMC_REVISION_MSK;
+}
+
+/*
+ * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
+ * and it has to be read consecutively and immediately after the 512
+ * byte data block for hardware to generate the error bit offsets
+ * Managing the ecc bytes in the following way is easier. This way is
+ * similar to oobfree structure maintained already in u-boot nand driver
+ */
+#define MAX_ECCPLACE_ENTRIES 32
+
+struct fsmc_nand_eccplace {
+ uint8_t offset;
+ uint8_t length;
+};
+
+struct fsmc_eccplace {
+ struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
+};
+
+/**
+ * fsmc_nand_platform_data - platform specific NAND controller config
+ * @partitions: partition table for the platform, use a default fallback
+ * if this is NULL
+ * @nr_partitions: the number of partitions in the previous entry
+ * @options: different options for the driver
+ * @width: bus width
+ * @bank: default bank
+ * @select_bank: callback to select a certain bank, this is
+ * platform-specific. If the controller only supports one bank
+ * this may be set to NULL
+ */
+struct fsmc_nand_platform_data {
+ struct mtd_partition *partitions;
+ unsigned int nr_partitions;
+ unsigned int options;
+ unsigned int width;
+ unsigned int bank;
+ void (*select_bank)(uint32_t bank, uint32_t busw);
+};
+
+extern int __init fsmc_nor_init(struct platform_device *pdev,
+ unsigned long base, uint32_t bank, uint32_t width);
+extern void __init fsmc_init_board_info(struct platform_device *pdev,
+ struct mtd_partition *partitions, unsigned int nr_partitions,
+ unsigned int width);
+
+#endif /* __MTD_FSMC_H */
__u16 firstEUN;
__u16 lastEUN;
__u16 numfreeEUNs;
- __u16 LastFreeEUN; /* To speed up finding a free EUN */
+ __u16 LastFreeEUN; /* To speed up finding a free EUN */
int head,sect,cyl;
- __u16 *PUtable; /* Physical Unit Table */
- __u16 *VUtable; /* Virtual Unit Table */
- unsigned int nb_blocks; /* number of physical blocks */
- unsigned int nb_boot_blocks; /* number of blocks used by the bios */
- struct erase_info instr;
- struct nand_ecclayout oobinfo;
+ __u16 *PUtable; /* Physical Unit Table */
+ __u16 *VUtable; /* Virtual Unit Table */
+ unsigned int nb_blocks; /* number of physical blocks */
+ unsigned int nb_boot_blocks; /* number of blocks used by the bios */
+ struct erase_info instr;
+ struct nand_ecclayout oobinfo;
};
int INFTL_mount(struct INFTLrecord *s);
uint8_t *oobbuf;
};
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE 448
+/*
+ * Internal ECC layout control structure. For historical reasons, there is a
+ * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained
+ * for export to user-space via the ECCGETLAYOUT ioctl.
+ * nand_ecclayout should be expandable in the future simply by the above macros.
+ */
+struct nand_ecclayout {
+ __u32 eccbytes;
+ __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
+ __u32 oobavail;
+ struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+};
+
struct mtd_info {
u_char type;
uint32_t flags;
struct mtd_info;
struct nand_flash_dev;
/* Scan and identify a NAND device */
-extern int nand_scan (struct mtd_info *mtd, int max_chips);
-/* Separate phases of nand_scan(), allowing board driver to intervene
- * and override command or ECC setup according to flash type */
+extern int nand_scan(struct mtd_info *mtd, int max_chips);
+/*
+ * Separate phases of nand_scan(), allowing board driver to intervene
+ * and override command or ECC setup according to flash type.
+ */
extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
struct nand_flash_dev *table);
extern int nand_scan_tail(struct mtd_info *mtd);
/* Free resources held by the NAND device */
-extern void nand_release (struct mtd_info *mtd);
+extern void nand_release(struct mtd_info *mtd);
/* Internal helper for board drivers which need to override command function */
extern void nand_wait_ready(struct mtd_info *mtd);
/* The maximum number of NAND chips in an array */
#define NAND_MAX_CHIPS 8
-/* This constant declares the max. oobsize / page, which
+/*
+ * This constant declares the max. oobsize / page, which
* is supported now. If you add a chip with bigger oobsize/page
* adjust this accordingly.
*/
-#define NAND_MAX_OOBSIZE 256
-#define NAND_MAX_PAGESIZE 4096
+#define NAND_MAX_OOBSIZE 576
+#define NAND_MAX_PAGESIZE 8192
/*
* Constants for hardware specific CLE/ALE/NCE function
#define NAND_CMD_RNDIN 0x85
#define NAND_CMD_READID 0x90
#define NAND_CMD_ERASE2 0xd0
+#define NAND_CMD_PARAM 0xec
#define NAND_CMD_RESET 0xff
#define NAND_CMD_LOCK 0x2a
#define NAND_GET_DEVICE 0x80
-/* Option constants for bizarre disfunctionality and real
-* features
-*/
+/*
+ * Option constants for bizarre disfunctionality and real
+ * features.
+ */
/* Chip can not auto increment pages */
#define NAND_NO_AUTOINCR 0x00000001
/* Buswitdh is 16 bit */
#define NAND_CACHEPRG 0x00000008
/* Chip has copy back function */
#define NAND_COPYBACK 0x00000010
-/* AND Chip which has 4 banks and a confusing page / block
- * assignment. See Renesas datasheet for further information */
+/*
+ * AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information.
+ */
#define NAND_IS_AND 0x00000020
-/* Chip has a array of 4 pages which can be read without
- * additional ready /busy waits */
+/*
+ * Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits.
+ */
#define NAND_4PAGE_ARRAY 0x00000040
-/* Chip requires that BBT is periodically rewritten to prevent
+/*
+ * Chip requires that BBT is periodically rewritten to prevent
* bits from adjacent blocks from 'leaking' in altering data.
- * This happens with the Renesas AG-AND chips, possibly others. */
+ * This happens with the Renesas AG-AND chips, possibly others.
+ */
#define BBT_AUTO_REFRESH 0x00000080
-/* Chip does not require ready check on read. True
+/*
+ * Chip does not require ready check on read. True
* for all large page devices, as they do not support
- * autoincrement.*/
+ * autoincrement.
+ */
#define NAND_NO_READRDY 0x00000100
/* Chip does not allow subpage writes */
#define NAND_NO_SUBPAGE_WRITE 0x00000200
#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
/* Non chip related options */
-/* Use a flash based bad block table. This option is passed to the
- * default bad block table function. */
+/*
+ * Use a flash based bad block table. OOB identifier is saved in OOB area.
+ * This option is passed to the default bad block table function.
+ */
#define NAND_USE_FLASH_BBT 0x00010000
/* This option skips the bbt scan during initialization. */
#define NAND_SKIP_BBTSCAN 0x00020000
-/* This option is defined if the board driver allocates its own buffers
- (e.g. because it needs them DMA-coherent */
+/*
+ * This option is defined if the board driver allocates its own buffers
+ * (e.g. because it needs them DMA-coherent).
+ */
#define NAND_OWN_BUFFERS 0x00040000
/* Chip may not exist, so silence any errors in scan */
#define NAND_SCAN_SILENT_NODEV 0x00080000
+/*
+ * If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
+ * the OOB area.
+ */
+#define NAND_USE_FLASH_BBT_NO_OOB 0x00100000
+/* Create an empty BBT with no vendor information if the BBT is available */
+#define NAND_CREATE_EMPTY_BBT 0x00200000
/* Options set by nand scan */
/* Nand scan has allocated controller struct */
/* Keep gcc happy */
struct nand_chip;
+struct nand_onfi_params {
+ /* rev info and features block */
+ /* 'O' 'N' 'F' 'I' */
+ u8 sig[4];
+ __le16 revision;
+ __le16 features;
+ __le16 opt_cmd;
+ u8 reserved[22];
+
+ /* manufacturer information block */
+ char manufacturer[12];
+ char model[20];
+ u8 jedec_id;
+ __le16 date_code;
+ u8 reserved2[13];
+
+ /* memory organization block */
+ __le32 byte_per_page;
+ __le16 spare_bytes_per_page;
+ __le32 data_bytes_per_ppage;
+ __le16 spare_bytes_per_ppage;
+ __le32 pages_per_block;
+ __le32 blocks_per_lun;
+ u8 lun_count;
+ u8 addr_cycles;
+ u8 bits_per_cell;
+ __le16 bb_per_lun;
+ __le16 block_endurance;
+ u8 guaranteed_good_blocks;
+ __le16 guaranteed_block_endurance;
+ u8 programs_per_page;
+ u8 ppage_attr;
+ u8 ecc_bits;
+ u8 interleaved_bits;
+ u8 interleaved_ops;
+ u8 reserved3[13];
+
+ /* electrical parameter block */
+ u8 io_pin_capacitance_max;
+ __le16 async_timing_mode;
+ __le16 program_cache_timing_mode;
+ __le16 t_prog;
+ __le16 t_bers;
+ __le16 t_r;
+ __le16 t_ccs;
+ __le16 src_sync_timing_mode;
+ __le16 src_ssync_features;
+ __le16 clk_pin_capacitance_typ;
+ __le16 io_pin_capacitance_typ;
+ __le16 input_pin_capacitance_typ;
+ u8 input_pin_capacitance_max;
+ u8 driver_strenght_support;
+ __le16 t_int_r;
+ __le16 t_ald;
+ u8 reserved4[7];
+
+ /* vendor */
+ u8 reserved5[90];
+
+ __le16 crc;
+} __attribute__((packed));
+
+#define ONFI_CRC_BASE 0x4F4E
+
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
* @lock: protection lock
* @active: the mtd device which holds the controller currently
- * @wq: wait queue to sleep on if a NAND operation is in progress
- * used instead of the per chip wait queue when a hw controller is available
+ * @wq: wait queue to sleep on if a NAND operation is in
+ * progress used instead of the per chip wait queue
+ * when a hw controller is available.
*/
struct nand_hw_control {
- spinlock_t lock;
+ spinlock_t lock;
struct nand_chip *active;
wait_queue_head_t wq;
};
* @correct: function for ecc correction, matching to ecc generator (sw/hw)
* @read_page_raw: function to read a raw page without ECC
* @write_page_raw: function to write a raw page without ECC
- * @read_page: function to read a page according to the ecc generator requirements
+ * @read_page: function to read a page according to the ecc generator
+ * requirements.
* @read_subpage: function to read parts of the page covered by ECC.
- * @write_page: function to write a page according to the ecc generator requirements
+ * @write_page: function to write a page according to the ecc generator
+ * requirements.
* @read_oob: function to read chip OOB data
* @write_oob: function to write chip OOB data
*/
struct nand_ecc_ctrl {
- nand_ecc_modes_t mode;
- int steps;
- int size;
- int bytes;
- int total;
- int prepad;
- int postpad;
+ nand_ecc_modes_t mode;
+ int steps;
+ int size;
+ int bytes;
+ int total;
+ int prepad;
+ int postpad;
struct nand_ecclayout *layout;
- void (*hwctl)(struct mtd_info *mtd, int mode);
- int (*calculate)(struct mtd_info *mtd,
- const uint8_t *dat,
- uint8_t *ecc_code);
- int (*correct)(struct mtd_info *mtd, uint8_t *dat,
- uint8_t *read_ecc,
- uint8_t *calc_ecc);
- int (*read_page_raw)(struct mtd_info *mtd,
- struct nand_chip *chip,
- uint8_t *buf, int page);
- void (*write_page_raw)(struct mtd_info *mtd,
- struct nand_chip *chip,
- const uint8_t *buf);
- int (*read_page)(struct mtd_info *mtd,
- struct nand_chip *chip,
- uint8_t *buf, int page);
- int (*read_subpage)(struct mtd_info *mtd,
- struct nand_chip *chip,
- uint32_t offs, uint32_t len,
- uint8_t *buf);
- void (*write_page)(struct mtd_info *mtd,
- struct nand_chip *chip,
- const uint8_t *buf);
- int (*read_oob)(struct mtd_info *mtd,
- struct nand_chip *chip,
- int page,
- int sndcmd);
- int (*write_oob)(struct mtd_info *mtd,
- struct nand_chip *chip,
- int page);
+ void (*hwctl)(struct mtd_info *mtd, int mode);
+ int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code);
+ int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+ uint8_t *calc_ecc);
+ int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page);
+ void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf);
+ int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page);
+ int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offs, uint32_t len, uint8_t *buf);
+ void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf);
+ int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
+ int sndcmd);
+ int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
+ int page);
};
/**
/**
* struct nand_chip - NAND Private Flash Chip Data
- * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
- * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
+ * flash device
+ * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
+ * flash device.
* @read_byte: [REPLACEABLE] read one byte from the chip
* @read_word: [REPLACEABLE] read one word from the chip
* @write_buf: [REPLACEABLE] write data from the buffer to the chip
* @read_buf: [REPLACEABLE] read data from the chip into the buffer
- * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
+ * @verify_buf: [REPLACEABLE] verify buffer contents against the chip
+ * data.
* @select_chip: [REPLACEABLE] select chip nr
* @block_bad: [REPLACEABLE] check, if the block is bad
* @block_markbad: [REPLACEABLE] mark the block bad
* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
* ALE/CLE/nCE. Also used to write command and address
- * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
- * If set to NULL no access to ready/busy is available and the ready/busy information
- * is read from the chip status register
- * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
- * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
+ * @init_size: [BOARDSPECIFIC] hardwarespecific funtion for setting
+ * mtd->oobsize, mtd->writesize and so on.
+ * @id_data contains the 8 bytes values of NAND_CMD_READID.
+ * Return with the bus width.
+ * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
+ * device ready/busy line. If set to NULL no access to
+ * ready/busy is available and the ready/busy information
+ * is read from the chip status register.
+ * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
+ * commands to the chip.
+ * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
+ * ready.
* @ecc: [BOARDSPECIFIC] ecc control ctructure
* @buffers: buffer structure for read/write
* @hwcontrol: platform-specific hardware control structure
* @ops: oob operation operands
- * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
+ * @erase_cmd: [INTERN] erase command write function, selectable due
+ * to AND support.
* @scan_bbt: [REPLACEABLE] function to scan bad block table
- * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering
+ * data from array to read regs (tR).
* @state: [INTERN] the current state of the NAND device
* @oob_poi: poison value buffer
- * @page_shift: [INTERN] number of address bits in a page (column address bits)
+ * @page_shift: [INTERN] number of address bits in a page (column
+ * address bits).
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
* @chip_shift: [INTERN] number of address bits in one chip
- * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
- * special functionality. See the defines for further explanation
- * @badblockpos: [INTERN] position of the bad block marker in the oob area
+ * @options: [BOARDSPECIFIC] various chip options. They can partly
+ * be set to inform nand_scan about special functionality.
+ * See the defines for further explanation.
+ * @badblockpos: [INTERN] position of the bad block marker in the oob
+ * area.
* @cellinfo: [INTERN] MLC/multichip data from chip ident
* @numchips: [INTERN] number of physical chips
* @chipsize: [INTERN] the size of one chip for multichip arrays
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
- * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
+ * @pagebuf: [INTERN] holds the pagenumber which is currently in
+ * data_buf.
* @subpagesize: [INTERN] holds the subpagesize
+ * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
+ * non 0 if ONFI supported.
+ * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
+ * supported, 0 otherwise.
* @ecclayout: [REPLACEABLE] the default ecc placement scheme
* @bbt: [INTERN] bad block table pointer
- * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
+ * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
+ * lookup.
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
- * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
- * @controller: [REPLACEABLE] a pointer to a hardware controller structure
- * which is shared among multiple independend devices
+ * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
+ * bad block scan.
+ * @controller: [REPLACEABLE] a pointer to a hardware controller
+ * structure which is shared among multiple independend
+ * devices.
* @priv: [OPTIONAL] pointer to private chip date
- * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
- * (determine if errors are correctable)
+ * @errstat: [OPTIONAL] hardware specific function to perform
+ * additional error status checks (determine if errors are
+ * correctable).
* @write_page: [REPLACEABLE] High-level page write function
*/
struct nand_chip {
- void __iomem *IO_ADDR_R;
- void __iomem *IO_ADDR_W;
-
- uint8_t (*read_byte)(struct mtd_info *mtd);
- u16 (*read_word)(struct mtd_info *mtd);
- void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
- void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
- int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
- void (*select_chip)(struct mtd_info *mtd, int chip);
- int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
- int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
- void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
- unsigned int ctrl);
- int (*dev_ready)(struct mtd_info *mtd);
- void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
- int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
- void (*erase_cmd)(struct mtd_info *mtd, int page);
- int (*scan_bbt)(struct mtd_info *mtd);
- int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
- int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int page, int cached, int raw);
-
- int chip_delay;
- unsigned int options;
-
- int page_shift;
- int phys_erase_shift;
- int bbt_erase_shift;
- int chip_shift;
- int numchips;
- uint64_t chipsize;
- int pagemask;
- int pagebuf;
- int subpagesize;
- uint8_t cellinfo;
- int badblockpos;
- int badblockbits;
-
- flstate_t state;
-
- uint8_t *oob_poi;
- struct nand_hw_control *controller;
- struct nand_ecclayout *ecclayout;
+ void __iomem *IO_ADDR_R;
+ void __iomem *IO_ADDR_W;
+
+ uint8_t (*read_byte)(struct mtd_info *mtd);
+ u16 (*read_word)(struct mtd_info *mtd);
+ void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+ void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+ int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+ void (*select_chip)(struct mtd_info *mtd, int chip);
+ int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+ int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+ void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+ int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
+ u8 *id_data);
+ int (*dev_ready)(struct mtd_info *mtd);
+ void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
+ int page_addr);
+ int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+ void (*erase_cmd)(struct mtd_info *mtd, int page);
+ int (*scan_bbt)(struct mtd_info *mtd);
+ int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
+ int status, int page);
+ int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int page, int cached, int raw);
+
+ int chip_delay;
+ unsigned int options;
+
+ int page_shift;
+ int phys_erase_shift;
+ int bbt_erase_shift;
+ int chip_shift;
+ int numchips;
+ uint64_t chipsize;
+ int pagemask;
+ int pagebuf;
+ int subpagesize;
+ uint8_t cellinfo;
+ int badblockpos;
+ int badblockbits;
+
+ int onfi_version;
+ struct nand_onfi_params onfi_params;
+
+ flstate_t state;
+
+ uint8_t *oob_poi;
+ struct nand_hw_control *controller;
+ struct nand_ecclayout *ecclayout;
struct nand_ecc_ctrl ecc;
struct nand_buffers *buffers;
struct mtd_oob_ops ops;
- uint8_t *bbt;
- struct nand_bbt_descr *bbt_td;
- struct nand_bbt_descr *bbt_md;
+ uint8_t *bbt;
+ struct nand_bbt_descr *bbt_td;
+ struct nand_bbt_descr *bbt_md;
- struct nand_bbt_descr *badblock_pattern;
+ struct nand_bbt_descr *badblock_pattern;
- void *priv;
+ void *priv;
};
/*
*/
struct nand_manufacturers {
int id;
- char * name;
+ char *name;
};
extern struct nand_flash_dev nand_flash_ids[];
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
int allowbbt);
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
- size_t * retlen, uint8_t * buf);
+ size_t *retlen, uint8_t *buf);
/**
* struct platform_nand_chip - chip level device structure
* @priv: hardware controller specific settings
*/
struct platform_nand_chip {
- int nr_chips;
- int chip_offset;
- int nr_partitions;
- struct mtd_partition *partitions;
- struct nand_ecclayout *ecclayout;
- int chip_delay;
- unsigned int options;
- const char **part_probe_types;
- void (*set_parts)(uint64_t size,
- struct platform_nand_chip *chip);
- void *priv;
+ int nr_chips;
+ int chip_offset;
+ int nr_partitions;
+ struct mtd_partition *partitions;
+ struct nand_ecclayout *ecclayout;
+ int chip_delay;
+ unsigned int options;
+ const char **part_probe_types;
+ void (*set_parts)(uint64_t size, struct platform_nand_chip *chip);
+ void *priv;
};
/* Keep gcc happy */
* All fields are optional and depend on the hardware driver requirements
*/
struct platform_nand_ctrl {
- int (*probe)(struct platform_device *pdev);
- void (*remove)(struct platform_device *pdev);
- void (*hwcontrol)(struct mtd_info *mtd, int cmd);
- int (*dev_ready)(struct mtd_info *mtd);
- void (*select_chip)(struct mtd_info *mtd, int chip);
- void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
- unsigned int ctrl);
- void (*write_buf)(struct mtd_info *mtd,
- const uint8_t *buf, int len);
- void (*read_buf)(struct mtd_info *mtd,
- uint8_t *buf, int len);
- void *priv;
+ int (*probe)(struct platform_device *pdev);
+ void (*remove)(struct platform_device *pdev);
+ void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+ int (*dev_ready)(struct mtd_info *mtd);
+ void (*select_chip)(struct mtd_info *mtd, int chip);
+ void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+ void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+ void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+ void *priv;
};
/**
* @ctrl: controller level device structure
*/
struct platform_nand_data {
- struct platform_nand_chip chip;
- struct platform_nand_ctrl ctrl;
+ struct platform_nand_chip chip;
+ struct platform_nand_ctrl ctrl;
};
/* Some helpers to access the data structures */
uint64_t size; /* partition size */
uint64_t offset; /* offset within the master MTD space */
uint32_t mask_flags; /* master MTD flags to mask out for this partition */
- struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/
+ struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */
};
#define MTDPART_OFS_NXTBLK (-2)
static inline int mtd_has_cmdlinepart(void) { return 0; }
#endif
+int mtd_is_master(struct mtd_info *mtd);
+int mtd_add_partition(struct mtd_info *master, char *name,
+ long long offset, long long length);
+int mtd_del_partition(struct mtd_info *master, int partno);
+
#endif
#include <linux/fs.h>
#include <linux/mount.h>
-extern int get_sb_mtd(struct file_system_type *fs_type, int flags,
+extern struct dentry *mount_mtd(struct file_system_type *fs_type, int flags,
const char *dev_name, void *data,
- int (*fill_super)(struct super_block *, void *, int),
- struct vfsmount *mnt);
+ int (*fill_super)(struct super_block *, void *, int));
extern void kill_mtd_super(struct super_block *sb);
struct inode *ramfs_get_inode(struct super_block *sb, const struct inode *dir,
int mode, dev_t dev);
-extern int ramfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt);
+extern struct dentry *ramfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data);
#ifndef CONFIG_MMU
extern int ramfs_nommu_expand_for_mapping(struct inode *inode, size_t newsize);
atomic_t inotify_watches; /* How many inotify watches does this user have? */
atomic_t inotify_devs; /* How many inotify devs does this user have opened? */
#endif
+#ifdef CONFIG_FANOTIFY
+ atomic_t fanotify_listeners;
+#endif
#ifdef CONFIG_EPOLL
atomic_t epoll_watches; /* The number of file descriptors currently watched */
#endif
struct task_struct *task);
#ifdef CONFIG_FAIR_GROUP_SCHED
- void (*moved_group) (struct task_struct *p, int on_rq);
+ void (*task_move_group) (struct task_struct *p, int on_rq);
#endif
};
int offset,
unsigned int len, __wsum *csump);
-extern long verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode);
+extern int verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode);
extern int memcpy_toiovec(struct iovec *v, unsigned char *kdata, int len);
extern int memcpy_toiovecend(const struct iovec *v, unsigned char *kdata,
int offset, int len);
extern void tty_audit_fork(struct signal_struct *sig);
extern void tty_audit_tiocsti(struct tty_struct *tty, char ch);
extern void tty_audit_push(struct tty_struct *tty);
-extern void tty_audit_push_task(struct task_struct *tsk,
- uid_t loginuid, u32 sessionid);
+extern int tty_audit_push_task(struct task_struct *tsk,
+ uid_t loginuid, u32 sessionid);
#else
static inline void tty_audit_add_data(struct tty_struct *tty,
unsigned char *data, size_t size)
static inline void tty_audit_push(struct tty_struct *tty)
{
}
-static inline void tty_audit_push_task(struct task_struct *tsk,
- uid_t loginuid, u32 sessionid)
+static inline int tty_audit_push_task(struct task_struct *tsk,
+ uid_t loginuid, u32 sessionid)
{
+ return 0;
}
#endif
struct bdi_writeback;
int inode_wait(void *);
void writeback_inodes_sb(struct super_block *);
+void writeback_inodes_sb_nr(struct super_block *, unsigned long nr);
int writeback_inodes_sb_if_idle(struct super_block *);
+int writeback_inodes_sb_nr_if_idle(struct super_block *, unsigned long nr);
void sync_inodes_sb(struct super_block *);
void writeback_inodes_wb(struct bdi_writeback *wb,
struct writeback_control *wbc);
#define MTD_NANDFLASH 4
#define MTD_DATAFLASH 6
#define MTD_UBIVOLUME 7
+#define MTD_MLCNANDFLASH 8
#define MTD_WRITEABLE 0x400 /* Device is writeable */
#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */
#define OTPGETREGIONCOUNT _IOW('M', 14, int)
#define OTPGETREGIONINFO _IOW('M', 15, struct otp_info)
#define OTPLOCK _IOR('M', 16, struct otp_info)
-#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout)
+#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout_user)
#define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats)
#define MTDFILEMODE _IO('M', 19)
#define MEMERASE64 _IOW('M', 20, struct erase_info_user64)
};
#define MTD_MAX_OOBFREE_ENTRIES 8
+#define MTD_MAX_ECCPOS_ENTRIES 64
/*
- * ECC layout control structure. Exported to userspace for
- * diagnosis and to allow creation of raw images
+ * OBSOLETE: ECC layout control structure. Exported to user-space via ioctl
+ * ECCGETLAYOUT for backwards compatbility and should not be mistaken as a
+ * complete set of ECC information. The ioctl truncates the larger internal
+ * structure to retain binary compatibility with the static declaration of the
+ * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of
+ * the user struct, not the MAX size of the internal struct nand_ecclayout.
*/
-struct nand_ecclayout {
+struct nand_ecclayout_user {
__u32 eccbytes;
- __u32 eccpos[64];
+ __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES];
__u32 oobavail;
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
};
typedef struct erase_info_user erase_info_t;
typedef struct region_info_user region_info_t;
typedef struct nand_oobinfo nand_oobinfo_t;
-typedef struct nand_ecclayout nand_ecclayout_t;
+typedef struct nand_ecclayout_user nand_ecclayout_t;
#endif /* __MTD_USER_H__ */
extern void fib_table_select_default(struct fib_table *table,
const struct flowi *flp,
struct fib_result *res);
+extern void fib_free_table(struct fib_table *tb);
+
#ifndef CONFIG_IP_MULTIPLE_TABLES
unsigned long (*read_data)(void *handle);
};
+struct module;
struct sh_mobile_lcdc_board_cfg {
+ struct module *owner;
void *board_data;
int (*setup_sys)(void *board_data, void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
int interface_type; /* selects RGBn or SYSn I/F, see above */
int clock_divider;
unsigned long flags; /* LCDC_FLAGS_... */
- struct fb_videomode lcd_cfg;
+ const struct fb_videomode *lcd_cfg;
+ int num_cfg;
struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg;
struct sh_mobile_lcdc_board_cfg board_cfg;
struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
return error;
}
-static int mqueue_get_sb(struct file_system_type *fs_type,
+static struct dentry *mqueue_mount(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
if (!(flags & MS_KERNMOUNT))
data = current->nsproxy->ipc_ns;
- return get_sb_ns(fs_type, flags, data, mqueue_fill_super, mnt);
+ return mount_ns(fs_type, flags, data, mqueue_fill_super);
}
static void init_once(void *foo)
static struct file_system_type mqueue_fs_type = {
.name = "mqueue",
- .get_sb = mqueue_get_sb,
+ .mount = mqueue_mount,
.kill_sb = kill_litter_super,
};
{
struct shmid_ds out;
+ memset(&out, 0, sizeof(out));
ipc64_perm_to_ipc_perm(&in->shm_perm, &out.shm_perm);
out.shm_segsz = in->shm_segsz;
out.shm_atime = in->shm_atime;
struct task_struct *tsk;
int err;
- read_lock(&tasklist_lock);
+ rcu_read_lock();
tsk = find_task_by_vpid(pid);
- err = -ESRCH;
- if (!tsk)
- goto out;
- err = 0;
-
- spin_lock_irq(&tsk->sighand->siglock);
- if (!tsk->signal->audit_tty)
- err = -EPERM;
- spin_unlock_irq(&tsk->sighand->siglock);
- if (err)
- goto out;
-
- tty_audit_push_task(tsk, loginuid, sessionid);
-out:
- read_unlock(&tasklist_lock);
+ if (!tsk) {
+ rcu_read_unlock();
+ return -ESRCH;
+ }
+ get_task_struct(tsk);
+ rcu_read_unlock();
+ err = tty_audit_push_task(tsk, loginuid, sessionid);
+ put_task_struct(tsk);
return err;
}
}
struct sk_buff *audit_make_reply(int pid, int seq, int type, int done,
- int multi, void *payload, int size)
+ int multi, const void *payload, int size)
{
struct sk_buff *skb;
struct nlmsghdr *nlh;
* Allocates an skb, builds the netlink message, and sends it to the pid.
* No failure notifications.
*/
-void audit_send_reply(int pid, int seq, int type, int done, int multi,
- void *payload, int size)
+static void audit_send_reply(int pid, int seq, int type, int done, int multi,
+ const void *payload, int size)
{
struct sk_buff *skb;
struct task_struct *tsk;
case AUDIT_TTY_GET: {
struct audit_tty_status s;
struct task_struct *tsk;
+ unsigned long flags;
- read_lock(&tasklist_lock);
+ rcu_read_lock();
tsk = find_task_by_vpid(pid);
- if (!tsk)
- err = -ESRCH;
- else {
- spin_lock_irq(&tsk->sighand->siglock);
+ if (tsk && lock_task_sighand(tsk, &flags)) {
s.enabled = tsk->signal->audit_tty != 0;
- spin_unlock_irq(&tsk->sighand->siglock);
- }
- read_unlock(&tasklist_lock);
- audit_send_reply(NETLINK_CB(skb).pid, seq, AUDIT_TTY_GET, 0, 0,
- &s, sizeof(s));
+ unlock_task_sighand(tsk, &flags);
+ } else
+ err = -ESRCH;
+ rcu_read_unlock();
+
+ if (!err)
+ audit_send_reply(NETLINK_CB(skb).pid, seq,
+ AUDIT_TTY_GET, 0, 0, &s, sizeof(s));
break;
}
case AUDIT_TTY_SET: {
struct audit_tty_status *s;
struct task_struct *tsk;
+ unsigned long flags;
if (nlh->nlmsg_len < sizeof(struct audit_tty_status))
return -EINVAL;
s = data;
if (s->enabled != 0 && s->enabled != 1)
return -EINVAL;
- read_lock(&tasklist_lock);
+ rcu_read_lock();
tsk = find_task_by_vpid(pid);
- if (!tsk)
- err = -ESRCH;
- else {
- spin_lock_irq(&tsk->sighand->siglock);
+ if (tsk && lock_task_sighand(tsk, &flags)) {
tsk->signal->audit_tty = s->enabled != 0;
- spin_unlock_irq(&tsk->sighand->siglock);
- }
- read_unlock(&tasklist_lock);
+ unlock_task_sighand(tsk, &flags);
+ } else
+ err = -ESRCH;
+ rcu_read_unlock();
break;
}
default:
int *dirlen);
extern struct sk_buff * audit_make_reply(int pid, int seq, int type,
int done, int multi,
- void *payload, int size);
-extern void audit_send_reply(int pid, int seq, int type,
- int done, int multi,
- void *payload, int size);
+ const void *payload, int size);
extern void audit_panic(const char *message);
struct audit_netlink_list {
{
struct audit_chunk *chunk = find_chunk(p);
struct fsnotify_mark *entry = &chunk->mark;
- struct audit_chunk *new;
+ struct audit_chunk *new = NULL;
struct audit_tree *owner;
int size = chunk->count - 1;
int i, j;
spin_unlock(&hash_lock);
+ if (size)
+ new = alloc_chunk(size);
+
spin_lock(&entry->lock);
if (chunk->dead || !entry->i.inode) {
spin_unlock(&entry->lock);
+ if (new)
+ free_chunk(new);
goto out;
}
goto out;
}
- new = alloc_chunk(size);
if (!new)
goto Fallback;
+
fsnotify_duplicate_mark(&new->mark, entry);
if (fsnotify_add_mark(&new->mark, new->mark.group, new->mark.i.inode, NULL, 1)) {
free_chunk(new);
};
/* fsnotify handle. */
-struct fsnotify_group *audit_watch_group;
+static struct fsnotify_group *audit_watch_group;
/* fsnotify events we care about. */
#define AUDIT_FS_WATCH (FS_MOVE | FS_CREATE | FS_DELETE | FS_DELETE_SELF |\
}
}
-void audit_remove_watch(struct audit_watch *watch)
+static void audit_remove_watch(struct audit_watch *watch)
{
list_del(&watch->wlist);
audit_put_parent(watch->parent);
case AUDIT_LOGINUID:
result = audit_comparator(cb->loginuid, f->op, f->val);
break;
+ case AUDIT_SUBJ_USER:
+ case AUDIT_SUBJ_ROLE:
+ case AUDIT_SUBJ_TYPE:
+ case AUDIT_SUBJ_SEN:
+ case AUDIT_SUBJ_CLR:
+ if (f->lsm_rule)
+ result = security_audit_rule_match(cb->sid,
+ f->type,
+ f->op,
+ f->lsm_rule,
+ NULL);
+ break;
}
if (!result)
pid_t pid;
struct audit_cap_data cap;
} capset;
+ struct {
+ int fd;
+ int flags;
+ } mmap;
};
int fds[2];
audit_log_cap(ab, "cap_pp", &context->capset.cap.permitted);
audit_log_cap(ab, "cap_pe", &context->capset.cap.effective);
break; }
+ case AUDIT_MMAP: {
+ audit_log_format(ab, "fd=%d flags=0x%x", context->mmap.fd,
+ context->mmap.flags);
+ break; }
}
audit_log_end(ab);
}
context->type = AUDIT_CAPSET;
}
+void __audit_mmap_fd(int fd, int flags)
+{
+ struct audit_context *context = current->audit_context;
+ context->mmap.fd = fd;
+ context->mmap.flags = flags;
+ context->type = AUDIT_MMAP;
+}
+
/**
* audit_core_dumps - record information about processes that end abnormally
* @signr: signal value
return 0;
}
-static int cgroup_get_sb(struct file_system_type *fs_type,
+static struct dentry *cgroup_mount(struct file_system_type *fs_type,
int flags, const char *unused_dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
struct cgroup_sb_opts opts;
struct cgroupfs_root *root;
drop_parsed_module_refcounts(opts.subsys_bits);
}
- simple_set_mnt(mnt, sb);
kfree(opts.release_agent);
kfree(opts.name);
- return 0;
+ return dget(sb->s_root);
drop_new_super:
deactivate_locked_super(sb);
out_err:
kfree(opts.release_agent);
kfree(opts.name);
- return ret;
+ return ERR_PTR(ret);
}
static void cgroup_kill_sb(struct super_block *sb) {
static struct file_system_type cgroup_fs_type = {
.name = "cgroup",
- .get_sb = cgroup_get_sb,
+ .mount = cgroup_mount,
.kill_sb = cgroup_kill_sb,
};
* users. If someone tries to mount the "cpuset" filesystem, we
* silently switch it to mount "cgroup" instead
*/
-static int cpuset_get_sb(struct file_system_type *fs_type,
- int flags, const char *unused_dev_name,
- void *data, struct vfsmount *mnt)
+static struct dentry *cpuset_mount(struct file_system_type *fs_type,
+ int flags, const char *unused_dev_name, void *data)
{
struct file_system_type *cgroup_fs = get_fs_type("cgroup");
- int ret = -ENODEV;
+ struct dentry *ret = ERR_PTR(-ENODEV);
if (cgroup_fs) {
char mountopts[] =
"cpuset,noprefix,"
"release_agent=/sbin/cpuset_release_agent";
- ret = cgroup_fs->get_sb(cgroup_fs, flags,
- unused_dev_name, mountopts, mnt);
+ ret = cgroup_fs->mount(cgroup_fs, flags,
+ unused_dev_name, mountopts);
put_filesystem(cgroup_fs);
}
return ret;
static struct file_system_type cpuset_fs_type = {
.name = "cpuset",
- .get_sb = cpuset_get_sb,
+ .mount = cpuset_mount,
};
/*
return 0;
}
-/**
- * kgdb_disable_hw_debug - Disable hardware debugging while we in kgdb.
- * @regs: Current &struct pt_regs.
- *
- * This function will be called if the particular architecture must
- * disable hardware debugging while it is processing gdb packets or
- * handling exception.
- */
-void __weak kgdb_disable_hw_debug(struct pt_regs *regs)
-{
-}
-
/*
* Some architectures need cache flushes when we set/clear a
* breakpoint:
atomic_inc(&masters_in_kgdb);
else
atomic_inc(&slaves_in_kgdb);
- kgdb_disable_hw_debug(ks->linux_regs);
+
+ if (arch_kgdb_ops.disable_hw_break)
+ arch_kgdb_ops.disable_hw_break(regs);
acquirelock:
/*
/* special case below */
} else {
kdb_printf("\nEntering kdb (current=0x%p, pid %d) ",
- kdb_current, kdb_current->pid);
+ kdb_current, kdb_current ? kdb_current->pid : 0);
#if defined(CONFIG_SMP)
kdb_printf("on processor %d ", raw_smp_processor_id());
#endif
*/
static int kdb_per_cpu(int argc, const char **argv)
{
- char buf[256], fmtstr[64];
- kdb_symtab_t symtab;
- cpumask_t suppress = CPU_MASK_NONE;
- int cpu, diag;
- unsigned long addr, val, bytesperword = 0, whichcpu = ~0UL;
+ char fmtstr[64];
+ int cpu, diag, nextarg = 1;
+ unsigned long addr, symaddr, val, bytesperword = 0, whichcpu = ~0UL;
if (argc < 1 || argc > 3)
return KDB_ARGCOUNT;
- snprintf(buf, sizeof(buf), "per_cpu__%s", argv[1]);
- if (!kdbgetsymval(buf, &symtab)) {
- kdb_printf("%s is not a per_cpu variable\n", argv[1]);
- return KDB_BADADDR;
- }
+ diag = kdbgetaddrarg(argc, argv, &nextarg, &symaddr, NULL, NULL);
+ if (diag)
+ return diag;
+
if (argc >= 2) {
diag = kdbgetularg(argv[2], &bytesperword);
if (diag)
#define KDB_PCU(cpu) 0
#endif
#endif
-
for_each_online_cpu(cpu) {
+ if (KDB_FLAG(CMD_INTERRUPT))
+ return 0;
+
if (whichcpu != ~0UL && whichcpu != cpu)
continue;
- addr = symtab.sym_start + KDB_PCU(cpu);
+ addr = symaddr + KDB_PCU(cpu);
diag = kdb_getword(&val, addr, bytesperword);
if (diag) {
kdb_printf("%5d " kdb_bfd_vma_fmt0 " - unable to "
"read, diag=%d\n", cpu, addr, diag);
continue;
}
-#ifdef CONFIG_SMP
- if (!val) {
- cpu_set(cpu, suppress);
- continue;
- }
-#endif /* CONFIG_SMP */
kdb_printf("%5d ", cpu);
kdb_md_line(fmtstr, addr,
bytesperword == KDB_WORD_SIZE,
1, bytesperword, 1, 1, 0);
}
- if (cpus_weight(suppress) == 0)
- return 0;
- kdb_printf("Zero suppressed cpu(s):");
- for (cpu = first_cpu(suppress); cpu < num_possible_cpus();
- cpu = next_cpu(cpu, suppress)) {
- kdb_printf(" %d", cpu);
- if (cpu == num_possible_cpus() - 1 ||
- next_cpu(cpu, suppress) != cpu + 1)
- continue;
- while (cpu < num_possible_cpus() &&
- next_cpu(cpu, suppress) == cpu + 1)
- ++cpu;
- kdb_printf("-%d", cpu);
- }
- kdb_printf("\n");
-
#undef KDB_PCU
-
return 0;
}
if (!desc)
return;
+ if (WARN(!desc->irq_data.chip || !desc->irq_data.chip->irq_enable,
+ KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq))
+ return;
+
chip_bus_lock(desc);
raw_spin_lock_irqsave(&desc->lock, flags);
__enable_irq(desc, irq, false);
struct module *mod;
};
+void jump_label_lock(void)
+{
+ mutex_lock(&jump_label_mutex);
+}
+
+void jump_label_unlock(void)
+{
+ mutex_unlock(&jump_label_mutex);
+}
+
static int jump_label_cmp(const void *a, const void *b)
{
const struct jump_entry *jea = a;
struct jump_label_module_entry *e_module;
int count;
- mutex_lock(&jump_label_mutex);
+ jump_label_lock();
entry = get_jump_label_entry((jump_label_t)key);
if (entry) {
count = entry->nr_entries;
count = e_module->nr_entries;
iter = e_module->table;
while (count--) {
- if (kernel_text_address(iter->code))
+ if (iter->key &&
+ kernel_text_address(iter->code))
arch_jump_label_transform(iter, type);
iter++;
}
}
}
- mutex_unlock(&jump_label_mutex);
+ jump_label_unlock();
}
static int addr_conflict(struct jump_entry *entry, void *start, void *end)
* overlaps with any of the jump label patch addresses. Code
* that wants to modify kernel text should first verify that
* it does not overlap with any of the jump label addresses.
+ * Caller must hold jump_label_mutex.
*
* returns 1 if there is an overlap, 0 otherwise
*/
struct jump_entry *iter_stop = __start___jump_table;
int conflict = 0;
- mutex_lock(&jump_label_mutex);
iter = iter_start;
while (iter < iter_stop) {
if (addr_conflict(iter, start, end)) {
conflict = module_conflict(start, end);
#endif
out:
- mutex_unlock(&jump_label_mutex);
return conflict;
}
+/*
+ * Not all archs need this.
+ */
+void __weak arch_jump_label_text_poke_early(jump_label_t addr)
+{
+}
+
static __init int init_jump_label(void)
{
int ret;
struct jump_entry *iter_stop = __stop___jump_table;
struct jump_entry *iter;
- mutex_lock(&jump_label_mutex);
+ jump_label_lock();
ret = build_jump_label_hashtable(__start___jump_table,
__stop___jump_table);
iter = iter_start;
arch_jump_label_text_poke_early(iter->code);
iter++;
}
- mutex_unlock(&jump_label_mutex);
+ jump_label_unlock();
return ret;
}
early_initcall(init_jump_label);
}
}
+static void remove_jump_label_module_init(struct module *mod)
+{
+ struct hlist_head *head;
+ struct hlist_node *node, *node_next, *module_node, *module_node_next;
+ struct jump_label_entry *e;
+ struct jump_label_module_entry *e_module;
+ struct jump_entry *iter;
+ int i, count;
+
+ /* if the module doesn't have jump label entries, just return */
+ if (!mod->num_jump_entries)
+ return;
+
+ for (i = 0; i < JUMP_LABEL_TABLE_SIZE; i++) {
+ head = &jump_label_table[i];
+ hlist_for_each_entry_safe(e, node, node_next, head, hlist) {
+ hlist_for_each_entry_safe(e_module, module_node,
+ module_node_next,
+ &(e->modules), hlist) {
+ if (e_module->mod != mod)
+ continue;
+ count = e_module->nr_entries;
+ iter = e_module->table;
+ while (count--) {
+ if (within_module_init(iter->code, mod))
+ iter->key = 0;
+ iter++;
+ }
+ }
+ }
+ }
+}
+
static int
jump_label_module_notify(struct notifier_block *self, unsigned long val,
void *data)
switch (val) {
case MODULE_STATE_COMING:
- mutex_lock(&jump_label_mutex);
+ jump_label_lock();
ret = add_jump_label_module(mod);
if (ret)
remove_jump_label_module(mod);
- mutex_unlock(&jump_label_mutex);
+ jump_label_unlock();
break;
case MODULE_STATE_GOING:
- mutex_lock(&jump_label_mutex);
+ jump_label_lock();
remove_jump_label_module(mod);
- mutex_unlock(&jump_label_mutex);
+ jump_label_unlock();
+ break;
+ case MODULE_STATE_LIVE:
+ jump_label_lock();
+ remove_jump_label_module_init(mod);
+ jump_label_unlock();
break;
}
return ret;
if (ret)
return ret;
+ jump_label_lock();
preempt_disable();
if (!kernel_text_address((unsigned long) p->addr) ||
in_kprobes_functions((unsigned long) p->addr) ||
ftrace_text_reserved(p->addr, p->addr) ||
- jump_label_text_reserved(p->addr, p->addr)) {
- preempt_enable();
- return -EINVAL;
- }
+ jump_label_text_reserved(p->addr, p->addr))
+ goto fail_with_jump_label;
/* User can pass only KPROBE_FLAG_DISABLED to register_kprobe */
p->flags &= KPROBE_FLAG_DISABLED;
* We must hold a refcount of the probed module while updating
* its code to prohibit unexpected unloading.
*/
- if (unlikely(!try_module_get(probed_mod))) {
- preempt_enable();
- return -EINVAL;
- }
+ if (unlikely(!try_module_get(probed_mod)))
+ goto fail_with_jump_label;
+
/*
* If the module freed .init.text, we couldn't insert
* kprobes in there.
if (within_module_init((unsigned long)p->addr, probed_mod) &&
probed_mod->state != MODULE_STATE_COMING) {
module_put(probed_mod);
- preempt_enable();
- return -EINVAL;
+ goto fail_with_jump_label;
}
}
preempt_enable();
+ jump_label_unlock();
p->nmissed = 0;
INIT_LIST_HEAD(&p->list);
mutex_lock(&kprobe_mutex);
+ jump_label_lock(); /* needed to call jump_label_text_reserved() */
+
get_online_cpus(); /* For avoiding text_mutex deadlock. */
mutex_lock(&text_mutex);
out:
mutex_unlock(&text_mutex);
put_online_cpus();
+ jump_label_unlock();
mutex_unlock(&kprobe_mutex);
if (probed_mod)
module_put(probed_mod);
return ret;
+
+fail_with_jump_label:
+ preempt_enable();
+ jump_label_unlock();
+ return -EINVAL;
}
EXPORT_SYMBOL_GPL(register_kprobe);
if (unlikely(running))
tsk->sched_class->put_prev_task(rq, tsk);
- set_task_rq(tsk, task_cpu(tsk));
-
#ifdef CONFIG_FAIR_GROUP_SCHED
- if (tsk->sched_class->moved_group)
- tsk->sched_class->moved_group(tsk, on_rq);
+ if (tsk->sched_class->task_move_group)
+ tsk->sched_class->task_move_group(tsk, on_rq);
+ else
#endif
+ set_task_rq(tsk, task_cpu(tsk));
if (unlikely(running))
tsk->sched_class->set_curr_task(rq);
}
#ifdef CONFIG_FAIR_GROUP_SCHED
-static void moved_group_fair(struct task_struct *p, int on_rq)
+static void task_move_group_fair(struct task_struct *p, int on_rq)
{
- struct cfs_rq *cfs_rq = task_cfs_rq(p);
-
- update_curr(cfs_rq);
+ /*
+ * If the task was not on the rq at the time of this cgroup movement
+ * it must have been asleep, sleeping tasks keep their ->vruntime
+ * absolute on their old rq until wakeup (needed for the fair sleeper
+ * bonus in place_entity()).
+ *
+ * If it was on the rq, we've just 'preempted' it, which does convert
+ * ->vruntime to a relative base.
+ *
+ * Make sure both cases convert their relative position when migrating
+ * to another cgroup's rq. This does somewhat interfere with the
+ * fair sleeper stuff for the first placement, but who cares.
+ */
+ if (!on_rq)
+ p->se.vruntime -= cfs_rq_of(&p->se)->min_vruntime;
+ set_task_rq(p, task_cpu(p));
if (!on_rq)
- place_entity(cfs_rq, &p->se, 1);
+ p->se.vruntime += cfs_rq_of(&p->se)->min_vruntime;
}
#endif
.get_rr_interval = get_rr_interval_fair,
#ifdef CONFIG_FAIR_GROUP_SCHED
- .moved_group = moved_group_fair,
+ .task_move_group = task_move_group_fair,
#endif
};
}
/*
- * Called when a process is dequeued from the active array and given
- * the cpu. We should note that with the exception of interactive
- * tasks, the expired queue will become the active queue after the active
- * queue is empty, without explicitly dequeuing and requeuing tasks in the
- * expired queue. (Interactive tasks may be requeued directly to the
- * active queue, thus delaying tasks in the expired queue from running;
- * see scheduler_tick()).
- *
- * Though we are interested in knowing how long it was from the *first* time a
+ * We are interested in knowing how long it was from the *first* time a
* task was queued to the time that it finally hit a cpu, we call this routine
* from dequeue_task() to account for possible rq->clock skew across cpus. The
* delta taken on each cpu would annul the skew.
}
/*
- * Called when a process is queued into either the active or expired
- * array. The time is noted and later used to determine how long we
- * had to wait for us to reach the cpu. Since the expired queue will
- * become the active queue after active queue is empty, without dequeuing
- * and requeuing any tasks, we are interested in queuing to either. It
- * is unusual but not impossible for tasks to be dequeued and immediately
- * requeued in the same or another array: this can happen in sched_yield(),
- * set_user_nice(), and even load_balance() as it moves tasks from runqueue
- * to runqueue.
- *
* This function is only called from enqueue_task(), but also only updates
* the timestamp if it is already not set. It's assumed that
* sched_info_dequeued() will clear that stamp when appropriate.
#include <linux/rmap.h>
#include <linux/mmu_notifier.h>
#include <linux/perf_event.h>
+#include <linux/audit.h>
#include <asm/uaccess.h>
#include <asm/cacheflush.h>
unsigned long retval = -EBADF;
if (!(flags & MAP_ANONYMOUS)) {
+ audit_mmap_fd(fd, flags);
if (unlikely(flags & MAP_HUGETLB))
return -EINVAL;
file = fget(fd);
#include <linux/personality.h>
#include <linux/security.h>
#include <linux/syscalls.h>
+#include <linux/audit.h>
#include <asm/uaccess.h>
#include <asm/tlb.h>
struct file *file = NULL;
unsigned long retval = -EBADF;
+ audit_mmap_fd(fd, flags);
if (!(flags & MAP_ANONYMOUS)) {
file = fget(fd);
if (!file)
};
-static int shmem_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *shmem_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_nodev(fs_type, flags, data, shmem_fill_super, mnt);
+ return mount_nodev(fs_type, flags, data, shmem_fill_super);
}
static struct file_system_type tmpfs_fs_type = {
.owner = THIS_MODULE,
.name = "tmpfs",
- .get_sb = shmem_get_sb,
+ .mount = shmem_mount,
.kill_sb = kill_litter_super,
};
static struct file_system_type tmpfs_fs_type = {
.name = "tmpfs",
- .get_sb = ramfs_get_sb,
+ .mount = ramfs_mount,
.kill_sb = kill_litter_super,
};
compat_size_t len;
if (get_user(len, &uiov32->iov_len) ||
- get_user(buf, &uiov32->iov_base)) {
- tot_len = -EFAULT;
- break;
- }
+ get_user(buf, &uiov32->iov_base))
+ return -EFAULT;
+
+ if (len > INT_MAX - tot_len)
+ len = INT_MAX - tot_len;
+
tot_len += len;
kiov->iov_base = compat_ptr(buf);
kiov->iov_len = (__kernel_size_t) len;
* in any case.
*/
-long verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode)
+int verify_iovec(struct msghdr *m, struct iovec *iov, struct sockaddr *address, int mode)
{
- int size, ct;
- long err;
+ int size, ct, err;
if (m->msg_namelen) {
if (mode == VERIFY_READ) {
err = 0;
for (ct = 0; ct < m->msg_iovlen; ct++) {
- err += iov[ct].iov_len;
- /*
- * Goal is not to verify user data, but to prevent returning
- * negative value, which is interpreted as errno.
- * Overflow is still possible, but it is harmless.
- */
- if (err < 0)
- return -EMSGSIZE;
+ size_t len = iov[ct].iov_len;
+
+ if (len > INT_MAX - err) {
+ len = INT_MAX - err;
+ iov[ct].iov_len = len;
+ }
+ err += len;
}
return err;
i += len;
if (debug) {
- char tb[count + 1];
- if (copy_from_user(tb, user_buffer, count))
+ size_t copy = min(count, 1023);
+ char tb[copy + 1];
+ if (copy_from_user(tb, user_buffer, copy))
return -EFAULT;
- tb[count] = 0;
+ tb[copy] = 0;
printk(KERN_DEBUG "pktgen: %s,%lu buffer -:%s:-\n", name,
(unsigned long)count, tb);
}
extern void ccid_hc_rx_delete(struct ccid *ccid, struct sock *sk);
extern void ccid_hc_tx_delete(struct ccid *ccid, struct sock *sk);
+/*
+ * Congestion control of queued data packets via CCID decision.
+ *
+ * The TX CCID performs its congestion-control by indicating whether and when a
+ * queued packet may be sent, using the return code of ccid_hc_tx_send_packet().
+ * The following modes are supported via the symbolic constants below:
+ * - timer-based pacing (CCID returns a delay value in milliseconds);
+ * - autonomous dequeueing (CCID internally schedules dccps_xmitlet).
+ */
+
+enum ccid_dequeueing_decision {
+ CCID_PACKET_SEND_AT_ONCE = 0x00000, /* "green light": no delay */
+ CCID_PACKET_DELAY_MAX = 0x0FFFF, /* maximum delay in msecs */
+ CCID_PACKET_DELAY = 0x10000, /* CCID msec-delay mode */
+ CCID_PACKET_WILL_DEQUEUE_LATER = 0x20000, /* CCID autonomous mode */
+ CCID_PACKET_ERR = 0xF0000, /* error condition */
+};
+
+static inline int ccid_packet_dequeue_eval(const int return_code)
+{
+ if (return_code < 0)
+ return CCID_PACKET_ERR;
+ if (return_code == 0)
+ return CCID_PACKET_SEND_AT_ONCE;
+ if (return_code <= CCID_PACKET_DELAY_MAX)
+ return CCID_PACKET_DELAY;
+ return return_code;
+}
+
static inline int ccid_hc_tx_send_packet(struct ccid *ccid, struct sock *sk,
struct sk_buff *skb)
{
- int rc = 0;
if (ccid->ccid_ops->ccid_hc_tx_send_packet != NULL)
- rc = ccid->ccid_ops->ccid_hc_tx_send_packet(sk, skb);
- return rc;
+ return ccid->ccid_ops->ccid_hc_tx_send_packet(sk, skb);
+ return CCID_PACKET_SEND_AT_ONCE;
}
static inline void ccid_hc_tx_packet_sent(struct ccid *ccid, struct sock *sk,
static int ccid2_hc_tx_send_packet(struct sock *sk, struct sk_buff *skb)
{
- struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
-
- if (hc->tx_pipe < hc->tx_cwnd)
- return 0;
-
- return 1; /* XXX CCID should dequeue when ready instead of polling */
+ if (ccid2_cwnd_network_limited(ccid2_hc_tx_sk(sk)))
+ return CCID_PACKET_WILL_DEQUEUE_LATER;
+ return CCID_PACKET_SEND_AT_ONCE;
}
static void ccid2_change_l_ack_ratio(struct sock *sk, u32 val)
{
struct sock *sk = (struct sock *)data;
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
+ const bool sender_was_blocked = ccid2_cwnd_network_limited(hc);
bh_lock_sock(sk);
if (sock_owned_by_user(sk)) {
if (hc->tx_rto > DCCP_RTO_MAX)
hc->tx_rto = DCCP_RTO_MAX;
- sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
-
/* adjust pipe, cwnd etc */
hc->tx_ssthresh = hc->tx_cwnd / 2;
if (hc->tx_ssthresh < 2)
hc->tx_rpseq = 0;
hc->tx_rpdupack = -1;
ccid2_change_l_ack_ratio(sk, 1);
+
+ /* if we were blocked before, we may now send cwnd=1 packet */
+ if (sender_was_blocked)
+ tasklet_schedule(&dccp_sk(sk)->dccps_xmitlet);
+ /* restart backed-off timer */
+ sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
out:
bh_unlock_sock(sk);
sock_put(sk);
{
struct dccp_sock *dp = dccp_sk(sk);
struct ccid2_hc_tx_sock *hc = ccid2_hc_tx_sk(sk);
+ const bool sender_was_blocked = ccid2_cwnd_network_limited(hc);
u64 ackno, seqno;
struct ccid2_seq *seqp;
unsigned char *vector;
sk_stop_timer(sk, &hc->tx_rtotimer);
else
sk_reset_timer(sk, &hc->tx_rtotimer, jiffies + hc->tx_rto);
+
+ /* check if incoming Acks allow pending packets to be sent */
+ if (sender_was_blocked && !ccid2_cwnd_network_limited(hc))
+ tasklet_schedule(&dccp_sk(sk)->dccps_xmitlet);
}
static int ccid2_hc_tx_init(struct ccid *ccid, struct sock *sk)
u64 tx_high_ack;
};
+static inline bool ccid2_cwnd_network_limited(struct ccid2_hc_tx_sock *hc)
+{
+ return hc->tx_pipe >= hc->tx_cwnd;
+}
+
struct ccid2_hc_rx_sock {
int rx_data;
};
sock_put(sk);
}
-/*
- * returns
- * > 0: delay (in msecs) that should pass before actually sending
- * = 0: can send immediately
- * < 0: error condition; do not send packet
+/**
+ * ccid3_hc_tx_send_packet - Delay-based dequeueing of TX packets
+ * @skb: next packet candidate to send on @sk
+ * This function uses the convention of ccid_packet_dequeue_eval() and
+ * returns a millisecond-delay value between 0 and t_mbi = 64000 msec.
*/
static int ccid3_hc_tx_send_packet(struct sock *sk, struct sk_buff *skb)
{
/* set the nominal send time for the next following packet */
hc->tx_t_nom = ktime_add_us(hc->tx_t_nom, hc->tx_t_ipi);
- return 0;
+ return CCID_PACKET_SEND_AT_ONCE;
}
static void ccid3_hc_tx_packet_sent(struct sock *sk, unsigned int len)
extern void dccp_send_sync(struct sock *sk, const u64 seq,
const enum dccp_pkt_type pkt_type);
-extern void dccp_write_xmit(struct sock *sk, int block);
-extern void dccp_write_space(struct sock *sk);
+extern void dccp_write_xmit(struct sock *sk);
+extern void dccp_write_space(struct sock *sk);
+extern void dccp_flush_write_queue(struct sock *sk, long *time_budget);
extern void dccp_init_xmit_timers(struct sock *sk);
static inline void dccp_clear_xmit_timers(struct sock *sk)
}
/**
- * dccp_wait_for_ccid - Wait for ccid to tell us we can send a packet
+ * dccp_wait_for_ccid - Await CCID send permission
* @sk: socket to wait for
- * @skb: current skb to pass on for waiting
- * @delay: sleep timeout in milliseconds (> 0)
- * This function is called by default when the socket is closed, and
- * when a non-zero linger time is set on the socket. For consistency
+ * @delay: timeout in jiffies
+ * This is used by CCIDs which need to delay the send time in process context.
*/
-static int dccp_wait_for_ccid(struct sock *sk, struct sk_buff *skb, int delay)
+static int dccp_wait_for_ccid(struct sock *sk, unsigned long delay)
{
- struct dccp_sock *dp = dccp_sk(sk);
DEFINE_WAIT(wait);
- unsigned long jiffdelay;
- int rc;
+ long remaining;
+
+ prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
+ sk->sk_write_pending++;
+ release_sock(sk);
+
+ remaining = schedule_timeout(delay);
+
+ lock_sock(sk);
+ sk->sk_write_pending--;
+ finish_wait(sk_sleep(sk), &wait);
+
+ if (signal_pending(current) || sk->sk_err)
+ return -1;
+ return remaining;
+}
+
+/**
+ * dccp_xmit_packet - Send data packet under control of CCID
+ * Transmits next-queued payload and informs CCID to account for the packet.
+ */
+static void dccp_xmit_packet(struct sock *sk)
+{
+ int err, len;
+ struct dccp_sock *dp = dccp_sk(sk);
+ struct sk_buff *skb = skb_dequeue(&sk->sk_write_queue);
- do {
- dccp_pr_debug("delayed send by %d msec\n", delay);
- jiffdelay = msecs_to_jiffies(delay);
+ if (unlikely(skb == NULL))
+ return;
+ len = skb->len;
- prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE);
+ if (sk->sk_state == DCCP_PARTOPEN) {
+ const u32 cur_mps = dp->dccps_mss_cache - DCCP_FEATNEG_OVERHEAD;
+ /*
+ * See 8.1.5 - Handshake Completion.
+ *
+ * For robustness we resend Confirm options until the client has
+ * entered OPEN. During the initial feature negotiation, the MPS
+ * is smaller than usual, reduced by the Change/Confirm options.
+ */
+ if (!list_empty(&dp->dccps_featneg) && len > cur_mps) {
+ DCCP_WARN("Payload too large (%d) for featneg.\n", len);
+ dccp_send_ack(sk);
+ dccp_feat_list_purge(&dp->dccps_featneg);
+ }
- sk->sk_write_pending++;
- release_sock(sk);
- schedule_timeout(jiffdelay);
- lock_sock(sk);
- sk->sk_write_pending--;
+ inet_csk_schedule_ack(sk);
+ inet_csk_reset_xmit_timer(sk, ICSK_TIME_DACK,
+ inet_csk(sk)->icsk_rto,
+ DCCP_RTO_MAX);
+ DCCP_SKB_CB(skb)->dccpd_type = DCCP_PKT_DATAACK;
+ } else if (dccp_ack_pending(sk)) {
+ DCCP_SKB_CB(skb)->dccpd_type = DCCP_PKT_DATAACK;
+ } else {
+ DCCP_SKB_CB(skb)->dccpd_type = DCCP_PKT_DATA;
+ }
+
+ err = dccp_transmit_skb(sk, skb);
+ if (err)
+ dccp_pr_debug("transmit_skb() returned err=%d\n", err);
+ /*
+ * Register this one as sent even if an error occurred. To the remote
+ * end a local packet drop is indistinguishable from network loss, i.e.
+ * any local drop will eventually be reported via receiver feedback.
+ */
+ ccid_hc_tx_packet_sent(dp->dccps_hc_tx_ccid, sk, len);
+}
- if (sk->sk_err)
- goto do_error;
- if (signal_pending(current))
- goto do_interrupted;
+/**
+ * dccp_flush_write_queue - Drain queue at end of connection
+ * Since dccp_sendmsg queues packets without waiting for them to be sent, it may
+ * happen that the TX queue is not empty at the end of a connection. We give the
+ * HC-sender CCID a grace period of up to @time_budget jiffies. If this function
+ * returns with a non-empty write queue, it will be purged later.
+ */
+void dccp_flush_write_queue(struct sock *sk, long *time_budget)
+{
+ struct dccp_sock *dp = dccp_sk(sk);
+ struct sk_buff *skb;
+ long delay, rc;
+ while (*time_budget > 0 && (skb = skb_peek(&sk->sk_write_queue))) {
rc = ccid_hc_tx_send_packet(dp->dccps_hc_tx_ccid, sk, skb);
- } while ((delay = rc) > 0);
-out:
- finish_wait(sk_sleep(sk), &wait);
- return rc;
-
-do_error:
- rc = -EPIPE;
- goto out;
-do_interrupted:
- rc = -EINTR;
- goto out;
+
+ switch (ccid_packet_dequeue_eval(rc)) {
+ case CCID_PACKET_WILL_DEQUEUE_LATER:
+ /*
+ * If the CCID determines when to send, the next sending
+ * time is unknown or the CCID may not even send again
+ * (e.g. remote host crashes or lost Ack packets).
+ */
+ DCCP_WARN("CCID did not manage to send all packets\n");
+ return;
+ case CCID_PACKET_DELAY:
+ delay = msecs_to_jiffies(rc);
+ if (delay > *time_budget)
+ return;
+ rc = dccp_wait_for_ccid(sk, delay);
+ if (rc < 0)
+ return;
+ *time_budget -= (delay - rc);
+ /* check again if we can send now */
+ break;
+ case CCID_PACKET_SEND_AT_ONCE:
+ dccp_xmit_packet(sk);
+ break;
+ case CCID_PACKET_ERR:
+ skb_dequeue(&sk->sk_write_queue);
+ kfree_skb(skb);
+ dccp_pr_debug("packet discarded due to err=%ld\n", rc);
+ }
+ }
}
-void dccp_write_xmit(struct sock *sk, int block)
+void dccp_write_xmit(struct sock *sk)
{
struct dccp_sock *dp = dccp_sk(sk);
struct sk_buff *skb;
while ((skb = skb_peek(&sk->sk_write_queue))) {
- int err = ccid_hc_tx_send_packet(dp->dccps_hc_tx_ccid, sk, skb);
-
- if (err > 0) {
- if (!block) {
- sk_reset_timer(sk, &dp->dccps_xmit_timer,
- msecs_to_jiffies(err)+jiffies);
- break;
- } else
- err = dccp_wait_for_ccid(sk, skb, err);
- if (err && err != -EINTR)
- DCCP_BUG("err=%d after dccp_wait_for_ccid", err);
- }
+ int rc = ccid_hc_tx_send_packet(dp->dccps_hc_tx_ccid, sk, skb);
- skb_dequeue(&sk->sk_write_queue);
- if (err == 0) {
- struct dccp_skb_cb *dcb = DCCP_SKB_CB(skb);
- const int len = skb->len;
-
- if (sk->sk_state == DCCP_PARTOPEN) {
- const u32 cur_mps = dp->dccps_mss_cache - DCCP_FEATNEG_OVERHEAD;
- /*
- * See 8.1.5 - Handshake Completion.
- *
- * For robustness we resend Confirm options until the client has
- * entered OPEN. During the initial feature negotiation, the MPS
- * is smaller than usual, reduced by the Change/Confirm options.
- */
- if (!list_empty(&dp->dccps_featneg) && len > cur_mps) {
- DCCP_WARN("Payload too large (%d) for featneg.\n", len);
- dccp_send_ack(sk);
- dccp_feat_list_purge(&dp->dccps_featneg);
- }
-
- inet_csk_schedule_ack(sk);
- inet_csk_reset_xmit_timer(sk, ICSK_TIME_DACK,
- inet_csk(sk)->icsk_rto,
- DCCP_RTO_MAX);
- dcb->dccpd_type = DCCP_PKT_DATAACK;
- } else if (dccp_ack_pending(sk))
- dcb->dccpd_type = DCCP_PKT_DATAACK;
- else
- dcb->dccpd_type = DCCP_PKT_DATA;
-
- err = dccp_transmit_skb(sk, skb);
- ccid_hc_tx_packet_sent(dp->dccps_hc_tx_ccid, sk, len);
- if (err)
- DCCP_BUG("err=%d after ccid_hc_tx_packet_sent",
- err);
- } else {
- dccp_pr_debug("packet discarded due to err=%d\n", err);
+ switch (ccid_packet_dequeue_eval(rc)) {
+ case CCID_PACKET_WILL_DEQUEUE_LATER:
+ return;
+ case CCID_PACKET_DELAY:
+ sk_reset_timer(sk, &dp->dccps_xmit_timer,
+ jiffies + msecs_to_jiffies(rc));
+ return;
+ case CCID_PACKET_SEND_AT_ONCE:
+ dccp_xmit_packet(sk);
+ break;
+ case CCID_PACKET_ERR:
+ skb_dequeue(&sk->sk_write_queue);
kfree_skb(skb);
+ dccp_pr_debug("packet discarded due to err=%d\n", rc);
}
}
}
DCCP_SKB_CB(skb)->dccpd_type = DCCP_PKT_CLOSE;
if (active) {
- dccp_write_xmit(sk, 1);
dccp_skb_entail(sk, skb);
dccp_transmit_skb(sk, skb_clone(skb, prio));
/*
goto out_discard;
skb_queue_tail(&sk->sk_write_queue, skb);
- dccp_write_xmit(sk,0);
+ /*
+ * The xmit_timer is set if the TX CCID is rate-based and will expire
+ * when congestion control permits to release further packets into the
+ * network. Window-based CCIDs do not use this timer.
+ */
+ if (!timer_pending(&dp->dccps_xmit_timer))
+ dccp_write_xmit(sk);
out_release:
release_sock(sk);
return rc ? : len;
/* Check zero linger _after_ checking for unread data. */
sk->sk_prot->disconnect(sk, 0);
} else if (sk->sk_state != DCCP_CLOSED) {
+ /*
+ * Normal connection termination. May need to wait if there are
+ * still packets in the TX queue that are delayed by the CCID.
+ */
+ dccp_flush_write_queue(sk, &timeout);
dccp_terminate_connection(sk);
}
+ /*
+ * Flush write queue. This may be necessary in several cases:
+ * - we have been closed by the peer but still have application data;
+ * - abortive termination (unread data or zero linger time),
+ * - normal termination but queue could not be flushed within time limit
+ */
+ __skb_queue_purge(&sk->sk_write_queue);
+
sk_stream_wait_close(sk, timeout);
adjudge_to_death:
sock_put(sk);
}
-/* Transmit-delay timer: used by the CCIDs to delay actual send time */
-static void dccp_write_xmit_timer(unsigned long data)
+/**
+ * dccp_write_xmitlet - Workhorse for CCID packet dequeueing interface
+ * See the comments above %ccid_dequeueing_decision for supported modes.
+ */
+static void dccp_write_xmitlet(unsigned long data)
{
struct sock *sk = (struct sock *)data;
- struct dccp_sock *dp = dccp_sk(sk);
bh_lock_sock(sk);
if (sock_owned_by_user(sk))
- sk_reset_timer(sk, &dp->dccps_xmit_timer, jiffies+1);
+ sk_reset_timer(sk, &dccp_sk(sk)->dccps_xmit_timer, jiffies + 1);
else
- dccp_write_xmit(sk, 0);
+ dccp_write_xmit(sk);
bh_unlock_sock(sk);
- sock_put(sk);
}
-static void dccp_init_write_xmit_timer(struct sock *sk)
+static void dccp_write_xmit_timer(unsigned long data)
{
- struct dccp_sock *dp = dccp_sk(sk);
-
- setup_timer(&dp->dccps_xmit_timer, dccp_write_xmit_timer,
- (unsigned long)sk);
+ dccp_write_xmitlet(data);
+ sock_put((struct sock *)data);
}
void dccp_init_xmit_timers(struct sock *sk)
{
- dccp_init_write_xmit_timer(sk);
+ struct dccp_sock *dp = dccp_sk(sk);
+
+ tasklet_init(&dp->dccps_xmitlet, dccp_write_xmitlet, (unsigned long)sk);
+ setup_timer(&dp->dccps_xmit_timer, dccp_write_xmit_timer,
+ (unsigned long)sk);
inet_csk_init_xmit_timers(sk, &dccp_write_timer, &dccp_delack_timer,
&dccp_keepalive_timer);
}
hlist_for_each_entry_safe(tb, node, tmp, head, tb_hlist) {
hlist_del(node);
fib_table_flush(tb);
- kfree(tb);
+ fib_free_table(tb);
}
}
kfree(net->ipv4.fib_table_hash);
return found;
}
+void fib_free_table(struct fib_table *tb)
+{
+ struct fn_hash *table = (struct fn_hash *) tb->tb_data;
+ struct fn_zone *fz, *next;
+
+ next = table->fn_zone_list;
+ while (next != NULL) {
+ fz = next;
+ next = fz->fz_next;
+
+ if (fz->fz_hash != fz->fz_embedded_hash)
+ fz_hash_free(fz->fz_hash, fz->fz_divisor);
+
+ kfree(fz);
+ }
+
+ kfree(tb);
+}
static inline int
fn_hash_dump_bucket(struct sk_buff *skb, struct netlink_callback *cb,
return found;
}
+void fib_free_table(struct fib_table *tb)
+{
+ kfree(tb);
+}
+
void fib_table_select_default(struct fib_table *tb,
const struct flowi *flp,
struct fib_result *res)
{
struct ip_tunnel *tunnel = netdev_priv(dev);
struct iphdr *iph = &tunnel->parms.iph;
- struct ipgre_net *ign = net_generic(dev_net(dev), ipgre_net_id);
tunnel->dev = dev;
strcpy(tunnel->parms.name, dev->name);
tunnel->hlen = sizeof(struct iphdr) + 4;
dev_hold(dev);
- rcu_assign_pointer(ign->tunnels_wc[0], tunnel);
}
if ((err = register_netdev(ign->fb_tunnel_dev)))
goto err_reg_dev;
+ rcu_assign_pointer(ign->tunnels_wc[0],
+ netdev_priv(ign->fb_tunnel_dev));
return 0;
err_reg_dev:
- free_netdev(ign->fb_tunnel_dev);
+ ipgre_dev_free(ign->fb_tunnel_dev);
err_alloc_dev:
return err;
}
SNMP_MIB_ITEM("Udp6NoPorts", UDP_MIB_NOPORTS),
SNMP_MIB_ITEM("Udp6InErrors", UDP_MIB_INERRORS),
SNMP_MIB_ITEM("Udp6OutDatagrams", UDP_MIB_OUTDATAGRAMS),
+ SNMP_MIB_ITEM("Udp6RcvbufErrors", UDP_MIB_RCVBUFERRORS),
+ SNMP_MIB_ITEM("Udp6SndbufErrors", UDP_MIB_SNDBUFERRORS),
SNMP_MIB_SENTINEL
};
SNMP_MIB_ITEM("UdpLite6NoPorts", UDP_MIB_NOPORTS),
SNMP_MIB_ITEM("UdpLite6InErrors", UDP_MIB_INERRORS),
SNMP_MIB_ITEM("UdpLite6OutDatagrams", UDP_MIB_OUTDATAGRAMS),
+ SNMP_MIB_ITEM("UdpLite6RcvbufErrors", UDP_MIB_RCVBUFERRORS),
+ SNMP_MIB_ITEM("UdpLite6SndbufErrors", UDP_MIB_SNDBUFERRORS),
SNMP_MIB_SENTINEL
};
size_t count, loff_t *ppos)
{
struct ieee80211_key *key = file->private_data;
- int i, res, bufsize = 2 * key->conf.keylen + 2;
+ int i, bufsize = 2 * key->conf.keylen + 2;
char *buf = kmalloc(bufsize, GFP_KERNEL);
char *p = buf;
+ ssize_t res;
+
+ if (!buf)
+ return -ENOMEM;
for (i = 0; i < key->conf.keylen; i++)
p += scnprintf(p, bufsize + buf - p, "%02x", key->conf.key[i]);
/*
* Calculate scan IE length -- we need this to alloc
* memory and to subtract from the driver limit. It
- * includes the (extended) supported rates and HT
+ * includes the DS Params, (extended) supported rates, and HT
* information -- SSID is the driver's responsibility.
*/
- local->scan_ies_len = 4 + max_bitrates; /* (ext) supp rates */
+ local->scan_ies_len = 4 + max_bitrates /* (ext) supp rates */ +
+ 3 /* DS Params */;
if (supp_ht)
local->scan_ies_len += 2 + sizeof(struct ieee80211_ht_cap);
static int
extract_icmp6_fields(const struct sk_buff *skb,
unsigned int outside_hdrlen,
- u8 *protocol,
+ int *protocol,
struct in6_addr **raddr,
struct in6_addr **laddr,
__be16 *rport,
struct sock *sk;
struct in6_addr *daddr, *saddr;
__be16 dport, sport;
- int thoff;
- u8 tproto;
+ int thoff, tproto;
const struct xt_socket_mtinfo1 *info = (struct xt_socket_mtinfo1 *) par->matchinfo;
tproto = ipv6_find_hdr(skb, &thoff, -1, NULL);
sk = NULL;
}
- pr_debug("proto %hhu %pI6:%hu -> %pI6:%hu "
+ pr_debug("proto %hhd %pI6:%hu -> %pI6:%hu "
"(orig %pI6:%hu) sock %p\n",
tproto, saddr, ntohs(sport),
daddr, ntohs(dport),
WARN_ON(rm->m_used_sgs + nents > rm->m_total_sgs);
WARN_ON(!nents);
+ if (rm->m_used_sgs + nents > rm->m_total_sgs)
+ return NULL;
+
sg_ret = &sg_first[rm->m_used_sgs];
sg_init_table(sg_ret, nents);
rm->m_used_sgs += nents;
rm->m_inc.i_hdr.h_len = cpu_to_be32(total_len);
rm->data.op_nents = ceil(total_len, PAGE_SIZE);
rm->data.op_sg = rds_message_alloc_sgs(rm, num_sgs);
+ if (!rm->data.op_sg)
+ return ERR_PTR(-ENOMEM);
for (i = 0; i < rm->data.op_nents; ++i) {
sg_set_page(&rm->data.op_sg[i],
/*
- * Count the number of pages needed to describe an incoming iovec.
+ * Count the number of pages needed to describe an incoming iovec array.
*/
-static int rds_rdma_pages(struct rds_rdma_args *args)
+static int rds_rdma_pages(struct rds_iovec iov[], int nr_iovecs)
+{
+ int tot_pages = 0;
+ unsigned int nr_pages;
+ unsigned int i;
+
+ /* figure out the number of pages in the vector */
+ for (i = 0; i < nr_iovecs; i++) {
+ nr_pages = rds_pages_in_vec(&iov[i]);
+ if (nr_pages == 0)
+ return -EINVAL;
+
+ tot_pages += nr_pages;
+
+ /*
+ * nr_pages for one entry is limited to (UINT_MAX>>PAGE_SHIFT)+1,
+ * so tot_pages cannot overflow without first going negative.
+ */
+ if (tot_pages < 0)
+ return -EINVAL;
+ }
+
+ return tot_pages;
+}
+
+int rds_rdma_extra_size(struct rds_rdma_args *args)
{
struct rds_iovec vec;
struct rds_iovec __user *local_vec;
- unsigned int tot_pages = 0;
+ int tot_pages = 0;
unsigned int nr_pages;
unsigned int i;
return -EINVAL;
tot_pages += nr_pages;
- }
- return tot_pages;
-}
+ /*
+ * nr_pages for one entry is limited to (UINT_MAX>>PAGE_SHIFT)+1,
+ * so tot_pages cannot overflow without first going negative.
+ */
+ if (tot_pages < 0)
+ return -EINVAL;
+ }
-int rds_rdma_extra_size(struct rds_rdma_args *args)
-{
- return rds_rdma_pages(args) * sizeof(struct scatterlist);
+ return tot_pages * sizeof(struct scatterlist);
}
/*
struct cmsghdr *cmsg)
{
struct rds_rdma_args *args;
- struct rds_iovec vec;
struct rm_rdma_op *op = &rm->rdma;
int nr_pages;
unsigned int nr_bytes;
struct page **pages = NULL;
- struct rds_iovec __user *local_vec;
- unsigned int nr;
+ struct rds_iovec iovstack[UIO_FASTIOV], *iovs = iovstack;
+ int iov_size;
unsigned int i, j;
int ret = 0;
goto out;
}
- nr_pages = rds_rdma_pages(args);
- if (nr_pages < 0)
+ /* Check whether to allocate the iovec area */
+ iov_size = args->nr_local * sizeof(struct rds_iovec);
+ if (args->nr_local > UIO_FASTIOV) {
+ iovs = sock_kmalloc(rds_rs_to_sk(rs), iov_size, GFP_KERNEL);
+ if (!iovs) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ }
+
+ if (copy_from_user(iovs, (struct rds_iovec __user *)(unsigned long) args->local_vec_addr, iov_size)) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ nr_pages = rds_rdma_pages(iovs, args->nr_local);
+ if (nr_pages < 0) {
+ ret = -EINVAL;
goto out;
+ }
pages = kcalloc(nr_pages, sizeof(struct page *), GFP_KERNEL);
if (!pages) {
op->op_recverr = rs->rs_recverr;
WARN_ON(!nr_pages);
op->op_sg = rds_message_alloc_sgs(rm, nr_pages);
+ if (!op->op_sg) {
+ ret = -ENOMEM;
+ goto out;
+ }
if (op->op_notify || op->op_recverr) {
/* We allocate an uninitialized notifier here, because
(unsigned long long)args->remote_vec.addr,
op->op_rkey);
- local_vec = (struct rds_iovec __user *)(unsigned long) args->local_vec_addr;
-
for (i = 0; i < args->nr_local; i++) {
- if (copy_from_user(&vec, &local_vec[i],
- sizeof(struct rds_iovec))) {
- ret = -EFAULT;
- goto out;
- }
-
- nr = rds_pages_in_vec(&vec);
- if (nr == 0) {
- ret = -EINVAL;
- goto out;
- }
+ struct rds_iovec *iov = &iovs[i];
+ /* don't need to check, rds_rdma_pages() verified nr will be +nonzero */
+ unsigned int nr = rds_pages_in_vec(iov);
- rs->rs_user_addr = vec.addr;
- rs->rs_user_bytes = vec.bytes;
+ rs->rs_user_addr = iov->addr;
+ rs->rs_user_bytes = iov->bytes;
/* If it's a WRITE operation, we want to pin the pages for reading.
* If it's a READ operation, we need to pin the pages for writing.
*/
- ret = rds_pin_pages(vec.addr, nr, pages, !op->op_write);
+ ret = rds_pin_pages(iov->addr, nr, pages, !op->op_write);
if (ret < 0)
goto out;
- rdsdebug("RDS: nr_bytes %u nr %u vec.bytes %llu vec.addr %llx\n",
- nr_bytes, nr, vec.bytes, vec.addr);
+ rdsdebug("RDS: nr_bytes %u nr %u iov->bytes %llu iov->addr %llx\n",
+ nr_bytes, nr, iov->bytes, iov->addr);
- nr_bytes += vec.bytes;
+ nr_bytes += iov->bytes;
for (j = 0; j < nr; j++) {
- unsigned int offset = vec.addr & ~PAGE_MASK;
+ unsigned int offset = iov->addr & ~PAGE_MASK;
struct scatterlist *sg;
sg = &op->op_sg[op->op_nents + j];
sg_set_page(sg, pages[j],
- min_t(unsigned int, vec.bytes, PAGE_SIZE - offset),
+ min_t(unsigned int, iov->bytes, PAGE_SIZE - offset),
offset);
- rdsdebug("RDS: sg->offset %x sg->len %x vec.addr %llx vec.bytes %llu\n",
- sg->offset, sg->length, vec.addr, vec.bytes);
+ rdsdebug("RDS: sg->offset %x sg->len %x iov->addr %llx iov->bytes %llu\n",
+ sg->offset, sg->length, iov->addr, iov->bytes);
- vec.addr += sg->length;
- vec.bytes -= sg->length;
+ iov->addr += sg->length;
+ iov->bytes -= sg->length;
}
op->op_nents += nr;
}
op->op_bytes = nr_bytes;
- ret = 0;
out:
+ if (iovs != iovstack)
+ sock_kfree_s(rds_rs_to_sk(rs), iovs, iov_size);
kfree(pages);
if (ret)
rds_rdma_free_op(op);
-
- rds_stats_inc(s_send_rdma);
+ else
+ rds_stats_inc(s_send_rdma);
return ret;
}
rm->atomic.op_active = 1;
rm->atomic.op_recverr = rs->rs_recverr;
rm->atomic.op_sg = rds_message_alloc_sgs(rm, 1);
+ if (!rm->atomic.op_sg) {
+ ret = -ENOMEM;
+ goto err;
+ }
/* verify 8 byte-aligned */
if (args->local_addr & 0x7) {
/* Attach data to the rm */
if (payload_len) {
rm->data.op_sg = rds_message_alloc_sgs(rm, ceil(payload_len, PAGE_SIZE));
+ if (!rm->data.op_sg) {
+ ret = -ENOMEM;
+ goto out;
+ }
ret = rds_message_copy_from_user(rm, msg->msg_iov, payload_len);
if (ret)
goto out;
.statfs = simple_statfs,
};
-static int sockfs_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *sockfs_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_pseudo(fs_type, "socket:", &sockfs_ops, SOCKFS_MAGIC,
- mnt);
+ return mount_pseudo(fs_type, "socket:", &sockfs_ops, SOCKFS_MAGIC);
}
static struct vfsmount *sock_mnt __read_mostly;
static struct file_system_type sock_fs_type = {
.name = "sockfs",
- .get_sb = sockfs_get_sb,
+ .mount = sockfs_mount,
.kill_sb = kill_anon_super,
};
struct iovec iov;
int fput_needed;
+ if (len > INT_MAX)
+ len = INT_MAX;
sock = sockfd_lookup_light(fd, &err, &fput_needed);
if (!sock)
goto out;
int err, err2;
int fput_needed;
+ if (size > INT_MAX)
+ size = INT_MAX;
sock = sockfd_lookup_light(fd, &err, &fput_needed);
if (!sock)
goto out;
#include <linux/sunrpc/rpc_pipe_fs.h>
#include <linux/sunrpc/cache.h>
-static struct vfsmount *rpc_mount __read_mostly;
+static struct vfsmount *rpc_mnt __read_mostly;
static int rpc_mount_count;
static struct file_system_type rpc_pipe_fs_type;
{
int err;
- err = simple_pin_fs(&rpc_pipe_fs_type, &rpc_mount, &rpc_mount_count);
+ err = simple_pin_fs(&rpc_pipe_fs_type, &rpc_mnt, &rpc_mount_count);
if (err != 0)
return ERR_PTR(err);
- return rpc_mount;
+ return rpc_mnt;
}
EXPORT_SYMBOL_GPL(rpc_get_mount);
void rpc_put_mount(void)
{
- simple_release_fs(&rpc_mount, &rpc_mount_count);
+ simple_release_fs(&rpc_mnt, &rpc_mount_count);
}
EXPORT_SYMBOL_GPL(rpc_put_mount);
return 0;
}
-static int
-rpc_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data, struct vfsmount *mnt)
+static struct dentry *
+rpc_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, rpc_fill_super, mnt);
+ return mount_single(fs_type, flags, data, rpc_fill_super);
}
static struct file_system_type rpc_pipe_fs_type = {
.owner = THIS_MODULE,
.name = "rpc_pipefs",
- .get_sb = rpc_get_sb,
+ .mount = rpc_mount,
.kill_sb = kill_litter_super,
};
If in doubt, say "N" here.
+config SAMPLE_KDB
+ tristate "Build kdb command exmaple -- loadable modules only"
+ depends on KGDB_KDB && m
+ help
+ Build an example of how to dynamically add the hello
+ command to the kdb shell.
+
endif # SAMPLES
# Makefile for Linux samples code
obj-$(CONFIG_SAMPLES) += kobject/ kprobes/ tracepoints/ trace_events/ \
- hw_breakpoint/ kfifo/
+ hw_breakpoint/ kfifo/ kdb/
--- /dev/null
+obj-$(CONFIG_SAMPLE_KDB) += kdb_hello.o
--- /dev/null
+/*
+ * Created by: Jason Wessel <jason.wessel@windriver.com>
+ *
+ * Copyright (c) 2010 Wind River Systems, Inc. All Rights Reserved.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kdb.h>
+
+/*
+ * All kdb shell command call backs receive argc and argv, where
+ * argv[0] is the command the end user typed
+ */
+static int kdb_hello_cmd(int argc, const char **argv)
+{
+ if (argc > 1)
+ return KDB_ARGCOUNT;
+
+ if (argc)
+ kdb_printf("Hello %s.\n", argv[1]);
+ else
+ kdb_printf("Hello world!\n");
+
+ return 0;
+}
+
+
+static int __init kdb_hello_cmd_init(void)
+{
+ /*
+ * Registration of a dynamically added kdb command is done with
+ * kdb_register() with the arguments being:
+ * 1: The name of the shell command
+ * 2: The function that processes the command
+ * 3: Description of the usage of any arguments
+ * 4: Descriptive text when you run help
+ * 5: Number of characters to complete the command
+ * 0 == type the whole command
+ * 1 == match both "g" and "go" for example
+ */
+ kdb_register("hello", kdb_hello_cmd, "[string]",
+ "Say Hello World or Hello [string]", 0);
+ return 0;
+}
+
+static void __exit kdb_hello_cmd_exit(void)
+{
+ kdb_unregister("hello");
+}
+
+module_init(kdb_hello_cmd_init);
+module_exit(kdb_hello_cmd_exit);
+
+MODULE_AUTHOR("WindRiver");
+MODULE_DESCRIPTION("KDB example to add a hello command");
+MODULE_LICENSE("GPL");
# mv config_strip .config
# make oldconfig
#
+use strict;
+
my $config = ".config";
my $uname = `uname -r`;
my %prompts;
my %objects;
my $var;
-my $cont = 0;
my $iflevel = 0;
my @ifdeps;
my $config;
my @kconfigs;
- open(KIN, "$ksource/$kconfig") || die "Can't open $kconfig";
+ my $cont = 0;
+ my $line;
+
+ my $source = "$ksource/$kconfig";
+ my $last_source = "";
+
+ # Check for any environment variables used
+ while ($source =~ /\$(\w+)/ && $last_source ne $source) {
+ my $env = $1;
+ $last_source = $source;
+ $source =~ s/\$$env/$ENV{$env}/;
+ }
+
+ open(KIN, "$source") || die "Can't open $kconfig";
while (<KIN>) {
chomp;
+ # Make sure that lines ending with \ continue
+ if ($cont) {
+ $_ = $line . " " . $_;
+ }
+
+ if (s/\\$//) {
+ $cont = 1;
+ $line = $_;
+ next;
+ }
+
+ $cont = 0;
+
# collect any Kconfig sources
if (/^source\s*"(.*)"/) {
$kconfigs[$#kconfigs+1] = $1;
}
# configs found
- if (/^\s*config\s+(\S+)\s*$/) {
+ if (/^\s*(menu)?config\s+(\S+)\s*$/) {
$state = "NEW";
- $config = $1;
+ $config = $2;
for (my $i = 0; $i < $iflevel; $i++) {
if ($i) {
# configs without prompts must be selected
} elsif ($state ne "NONE" && /^\s*tristate\s\S/) {
# note if the config has a prompt
- $prompt{$config} = 1;
+ $prompts{$config} = 1;
# Check for if statements
} elsif (/^if\s+(.*\S)\s*$/) {
# Read all Makefiles to map the configs to the objects
foreach my $makefile (@makefiles) {
+ my $cont = 0;
+
open(MIN,$makefile) || die "Can't open $makefile";
while (<MIN>) {
my $objs;
# see what modules are loaded on this system
my $lsmod;
- foreach $dir ( ("/sbin", "/bin", "/usr/sbin", "/usr/bin") ) {
+ foreach my $dir ( ("/sbin", "/bin", "/usr/sbin", "/usr/bin") ) {
if ( -x "$dir/lsmod" ) {
$lsmod = "$dir/lsmod";
last;
parse_config_dep_select $depends{$config};
}
- if (defined($prompt{$config}) || !defined($selects{$config})) {
+ if (defined($prompts{$config}) || !defined($selects{$config})) {
next;
}
#define RECORD_MCOUNT_64
#include "recordmcount.h"
+/* 64-bit EM_MIPS has weird ELF64_Rela.r_info.
+ * http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf
+ * We interpret Table 29 Relocation Operation (Elf64_Rel, Elf64_Rela) [p.40]
+ * to imply the order of the members; the spec does not say so.
+ * typedef unsigned char Elf64_Byte;
+ * fails on MIPS64 because their <elf.h> already has it!
+ */
+
+typedef uint8_t myElf64_Byte; /* Type for a 8-bit quantity. */
+
+union mips_r_info {
+ Elf64_Xword r_info;
+ struct {
+ Elf64_Word r_sym; /* Symbol index. */
+ myElf64_Byte r_ssym; /* Special symbol. */
+ myElf64_Byte r_type3; /* Third relocation. */
+ myElf64_Byte r_type2; /* Second relocation. */
+ myElf64_Byte r_type; /* First relocation. */
+ } r_mips;
+};
+
+static uint64_t MIPS64_r_sym(Elf64_Rel const *rp)
+{
+ return w(((union mips_r_info){ .r_info = rp->r_info }).r_mips.r_sym);
+}
+
+static void MIPS64_r_info(Elf64_Rel *const rp, unsigned sym, unsigned type)
+{
+ rp->r_info = ((union mips_r_info){
+ .r_mips = { .r_sym = w(sym), .r_type = type }
+ }).r_info;
+}
+
static void
do_file(char const *const fname)
{
case EM_386: reltype = R_386_32; break;
case EM_ARM: reltype = R_ARM_ABS32; break;
case EM_IA_64: reltype = R_IA64_IMM64; gpfx = '_'; break;
+ case EM_MIPS: /* reltype: e_class */ gpfx = '_'; break;
case EM_PPC: reltype = R_PPC_ADDR32; gpfx = '_'; break;
case EM_PPC64: reltype = R_PPC64_ADDR64; gpfx = '_'; break;
case EM_S390: /* reltype: e_class */ gpfx = '_'; break;
}
if (EM_S390 == w2(ehdr->e_machine))
reltype = R_390_32;
+ if (EM_MIPS == w2(ehdr->e_machine)) {
+ reltype = R_MIPS_32;
+ is_fake_mcount32 = MIPS32_is_fake_mcount;
+ }
do32(ehdr, fname, reltype);
} break;
case ELFCLASS64: {
}
if (EM_S390 == w2(ghdr->e_machine))
reltype = R_390_64;
+ if (EM_MIPS == w2(ghdr->e_machine)) {
+ reltype = R_MIPS_64;
+ Elf64_r_sym = MIPS64_r_sym;
+ Elf64_r_info = MIPS64_r_info;
+ is_fake_mcount64 = MIPS64_is_fake_mcount;
+ }
do64(ghdr, fname, reltype);
} break;
} /* end switch */
* Licensed under the GNU General Public License, version 2 (GPLv2).
*/
#undef append_func
+#undef is_fake_mcount
+#undef fn_is_fake_mcount
+#undef MIPS_is_fake_mcount
#undef sift_rel_mcount
#undef find_secsym_ndx
#undef __has_rel_mcount
#undef has_rel_mcount
#undef tot_relsize
#undef do_func
+#undef Elf_Addr
#undef Elf_Ehdr
#undef Elf_Shdr
#undef Elf_Rel
#undef Elf_Rela
#undef Elf_Sym
#undef ELF_R_SYM
+#undef Elf_r_sym
#undef ELF_R_INFO
+#undef Elf_r_info
#undef ELF_ST_BIND
+#undef fn_ELF_R_SYM
+#undef fn_ELF_R_INFO
#undef uint_t
#undef _w
#undef _align
# define has_rel_mcount has64_rel_mcount
# define tot_relsize tot64_relsize
# define do_func do64
+# define is_fake_mcount is_fake_mcount64
+# define fn_is_fake_mcount fn_is_fake_mcount64
+# define MIPS_is_fake_mcount MIPS64_is_fake_mcount
+# define Elf_Addr Elf64_Addr
# define Elf_Ehdr Elf64_Ehdr
# define Elf_Shdr Elf64_Shdr
# define Elf_Rel Elf64_Rel
# define Elf_Rela Elf64_Rela
# define Elf_Sym Elf64_Sym
# define ELF_R_SYM ELF64_R_SYM
+# define Elf_r_sym Elf64_r_sym
# define ELF_R_INFO ELF64_R_INFO
+# define Elf_r_info Elf64_r_info
# define ELF_ST_BIND ELF64_ST_BIND
+# define fn_ELF_R_SYM fn_ELF64_R_SYM
+# define fn_ELF_R_INFO fn_ELF64_R_INFO
# define uint_t uint64_t
# define _w w8
# define _align 7u
# define has_rel_mcount has32_rel_mcount
# define tot_relsize tot32_relsize
# define do_func do32
+# define is_fake_mcount is_fake_mcount32
+# define fn_is_fake_mcount fn_is_fake_mcount32
+# define MIPS_is_fake_mcount MIPS32_is_fake_mcount
+# define Elf_Addr Elf32_Addr
# define Elf_Ehdr Elf32_Ehdr
# define Elf_Shdr Elf32_Shdr
# define Elf_Rel Elf32_Rel
# define Elf_Rela Elf32_Rela
# define Elf_Sym Elf32_Sym
# define ELF_R_SYM ELF32_R_SYM
+# define Elf_r_sym Elf32_r_sym
# define ELF_R_INFO ELF32_R_INFO
+# define Elf_r_info Elf32_r_info
# define ELF_ST_BIND ELF32_ST_BIND
+# define fn_ELF_R_SYM fn_ELF32_R_SYM
+# define fn_ELF_R_INFO fn_ELF32_R_INFO
# define uint_t uint32_t
# define _w w
# define _align 3u
# define _size 4
#endif
+/* Functions and pointers that do_file() may override for specific e_machine. */
+static int fn_is_fake_mcount(Elf_Rel const *rp)
+{
+ return 0;
+}
+static int (*is_fake_mcount)(Elf_Rel const *rp) = fn_is_fake_mcount;
+
+static uint_t fn_ELF_R_SYM(Elf_Rel const *rp)
+{
+ return ELF_R_SYM(_w(rp->r_info));
+}
+static uint_t (*Elf_r_sym)(Elf_Rel const *rp) = fn_ELF_R_SYM;
+
+static void fn_ELF_R_INFO(Elf_Rel *const rp, unsigned sym, unsigned type)
+{
+ rp->r_info = ELF_R_INFO(sym, type);
+}
+static void (*Elf_r_info)(Elf_Rel *const rp, unsigned sym, unsigned type) = fn_ELF_R_INFO;
+
+/*
+ * MIPS mcount long call has 2 _mcount symbols, only the position of the 1st
+ * _mcount symbol is needed for dynamic function tracer, with it, to disable
+ * tracing(ftrace_make_nop), the instruction in the position is replaced with
+ * the "b label" instruction, to enable tracing(ftrace_make_call), replace the
+ * instruction back. So, here, we set the 2nd one as fake and filter it.
+ *
+ * c: 3c030000 lui v1,0x0 <--> b label
+ * c: R_MIPS_HI16 _mcount
+ * c: R_MIPS_NONE *ABS*
+ * c: R_MIPS_NONE *ABS*
+ * 10: 64630000 daddiu v1,v1,0
+ * 10: R_MIPS_LO16 _mcount
+ * 10: R_MIPS_NONE *ABS*
+ * 10: R_MIPS_NONE *ABS*
+ * 14: 03e0082d move at,ra
+ * 18: 0060f809 jalr v1
+ * label:
+ */
+#define MIPS_FAKEMCOUNT_OFFSET 4
+
+static int MIPS_is_fake_mcount(Elf_Rel const *rp)
+{
+ static Elf_Addr old_r_offset;
+ Elf_Addr current_r_offset = _w(rp->r_offset);
+ int is_fake;
+
+ is_fake = old_r_offset &&
+ (current_r_offset - old_r_offset == MIPS_FAKEMCOUNT_OFFSET);
+ old_r_offset = current_r_offset;
+
+ return is_fake;
+}
+
/* Append the new shstrtab, Elf_Shdr[], __mcount_loc and its relocations. */
static void append_func(Elf_Ehdr *const ehdr,
Elf_Shdr *const shstr,
uwrite(fd_map, ehdr, sizeof(*ehdr));
}
-
/*
* Look at the relocations in order to find the calls to mcount.
* Accumulate the section offsets that are found, and their relocation info,
for (t = nrel; t; --t) {
if (!mcountsym) {
Elf_Sym const *const symp =
- &sym0[ELF_R_SYM(_w(relp->r_info))];
+ &sym0[Elf_r_sym(relp)];
char const *symname = &str0[w(symp->st_name)];
if ('.' == symname[0])
++symname; /* ppc64 hack */
if (0 == strcmp((('_' == gpfx) ? "_mcount" : "mcount"),
symname))
- mcountsym = ELF_R_SYM(_w(relp->r_info));
+ mcountsym = Elf_r_sym(relp);
}
- if (mcountsym == ELF_R_SYM(_w(relp->r_info))) {
+ if (mcountsym == Elf_r_sym(relp) && !is_fake_mcount(relp)) {
uint_t const addend = _w(_w(relp->r_offset) - recval);
mrelp->r_offset = _w(offbase
+ ((void *)mlocp - (void *)mloc0));
- mrelp->r_info = _w(ELF_R_INFO(recsym, reltype));
+ Elf_r_info(mrelp, recsym, reltype);
if (sizeof(Elf_Rela) == rel_entsize) {
((Elf_Rela *)mrelp)->r_addend = addend;
*mlocp++ = 0;
return simple_fill_super(sb, SECURITYFS_MAGIC, files);
}
-static int get_sb(struct file_system_type *fs_type,
+static struct dentry *get_sb(struct file_system_type *fs_type,
int flags, const char *dev_name,
- void *data, struct vfsmount *mnt)
+ void *data)
{
- return get_sb_single(fs_type, flags, data, fill_super, mnt);
+ return mount_single(fs_type, flags, data, fill_super);
}
static struct file_system_type fs_type = {
.owner = THIS_MODULE,
.name = "securityfs",
- .get_sb = get_sb,
+ .mount = get_sb,
.kill_sb = kill_litter_super,
};
goto out;
}
-static int sel_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *sel_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, sel_fill_super, mnt);
+ return mount_single(fs_type, flags, data, sel_fill_super);
}
static struct file_system_type sel_fs_type = {
.name = "selinuxfs",
- .get_sb = sel_get_sb,
+ .mount = sel_mount,
.kill_sb = kill_litter_super,
};
}
/**
- * smk_get_sb - get the smackfs superblock
+ * smk_mount - get the smackfs superblock
* @fs_type: passed along without comment
* @flags: passed along without comment
* @dev_name: passed along without comment
* @data: passed along without comment
- * @mnt: passed along without comment
*
* Just passes everything along.
*
* Returns what the lower level code does.
*/
-static int smk_get_sb(struct file_system_type *fs_type,
- int flags, const char *dev_name, void *data,
- struct vfsmount *mnt)
+static struct dentry *smk_mount(struct file_system_type *fs_type,
+ int flags, const char *dev_name, void *data)
{
- return get_sb_single(fs_type, flags, data, smk_fill_super, mnt);
+ return mount_single(fs_type, flags, data, smk_fill_super);
}
static struct file_system_type smk_fs_type = {
.name = "smackfs",
- .get_sb = smk_get_sb,
+ .mount = smk_mount,
.kill_sb = kill_litter_super,
};
.section .init.ramfs.info,"a"
.globl __initramfs_size
__initramfs_size:
-#ifdef CONFIG_32BIT
- .long __irf_end - __irf_start
-#else
+#ifdef CONFIG_64BIT
.quad __irf_end - __irf_start
+#else
+ .long __irf_end - __irf_start
#endif
git://bbs.cooldavid.org / net-next-2.6.git / commitdiff