]> bbs.cooldavid.org Git - net-next-2.6.git/commitdiff
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()
authorKirill A. Shutemov <kirill@shutemov.name>
Fri, 25 Sep 2009 12:39:47 +0000 (13:39 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Fri, 2 Oct 2009 21:34:32 +0000 (22:34 +0100)
Instruction fault status register, IFSR, was introduced on ARMv6 to
provide status information about the last insturction fault. It
needed for proper prefetch abort handling.

Now we have three prefetch abort model:

  * legacy - for CPUs before ARMv6. They doesn't provide neither
    IFSR nor IFAR. We simulate IFSR with section translation fault
    status for them to generalize code;
  * ARMv6 - provides IFSR, but not IFAR;
  * ARMv7 - provides both IFSR and IFAR.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
33 files changed:
arch/arm/include/asm/glue.h
arch/arm/kernel/entry-armv.S
arch/arm/kernel/entry-common.S
arch/arm/mm/Kconfig
arch/arm/mm/Makefile
arch/arm/mm/fault.c
arch/arm/mm/pabort-legacy.S [new file with mode: 0644]
arch/arm/mm/pabort-v6.S [new file with mode: 0644]
arch/arm/mm/pabort-v7.S [new file with mode: 0644]
arch/arm/mm/proc-arm1020.S
arch/arm/mm/proc-arm1020e.S
arch/arm/mm/proc-arm1022.S
arch/arm/mm/proc-arm1026.S
arch/arm/mm/proc-arm6_7.S
arch/arm/mm/proc-arm720.S
arch/arm/mm/proc-arm740.S
arch/arm/mm/proc-arm7tdmi.S
arch/arm/mm/proc-arm920.S
arch/arm/mm/proc-arm922.S
arch/arm/mm/proc-arm925.S
arch/arm/mm/proc-arm926.S
arch/arm/mm/proc-arm940.S
arch/arm/mm/proc-arm946.S
arch/arm/mm/proc-arm9tdmi.S
arch/arm/mm/proc-fa526.S
arch/arm/mm/proc-feroceon.S
arch/arm/mm/proc-mohawk.S
arch/arm/mm/proc-sa110.S
arch/arm/mm/proc-sa1100.S
arch/arm/mm/proc-v6.S
arch/arm/mm/proc-v7.S
arch/arm/mm/proc-xsc3.S
arch/arm/mm/proc-xscale.S

index a0e39d5d00c936a68ac4f99ca9a9b6559b61854f..234a3fc1c78ee43357dba69b4c850aa73c819541 100644 (file)
 #endif
 
 /*
- * Prefetch abort handler.  If the CPU has an IFAR use that, otherwise
- * use the address of the aborted instruction
+ *     Prefetch Abort Model
+ *     ================
+ *
+ *     We have the following to choose from:
+ *       legacy        - no IFSR, no IFAR
+ *       v6            - ARMv6: IFSR, no IFAR
+ *       v7            - ARMv7: IFSR and IFAR
  */
+
 #undef CPU_PABORT_HANDLER
 #undef MULTI_PABORT
 
-#ifdef CONFIG_CPU_PABRT_IFAR
+#ifdef CONFIG_CPU_PABRT_LEGACY
+# ifdef CPU_PABORT_HANDLER
+#  define MULTI_PABORT 1
+# else
+#  define CPU_PABORT_HANDLER legacy_pabort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_PABRT_V6
 # ifdef CPU_PABORT_HANDLER
 #  define MULTI_PABORT 1
 # else
-#  define CPU_PABORT_HANDLER(reg, insn)        mrc p15, 0, reg, cr6, cr0, 2
+#  define CPU_PABORT_HANDLER v6_pabort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_PABRT_NOIFAR
+#ifdef CONFIG_CPU_PABRT_V7
 # ifdef CPU_PABORT_HANDLER
 #  define MULTI_PABORT 1
 # else
-#  define CPU_PABORT_HANDLER(reg, insn)        mov reg, insn
+#  define CPU_PABORT_HANDLER v7_pabort
 # endif
 #endif
 
index 0a2ba51cf35df1602db7d5a692c7c712a4bcf0d3..322410be573ca027bd8e03da67e134492423974d 100644 (file)
@@ -311,22 +311,16 @@ __pabt_svc:
        tst     r3, #PSR_I_BIT
        biceq   r9, r9, #PSR_I_BIT
 
-       @
-       @ set args, then call main handler
-       @
-       @  r0 - address of faulting instruction
-       @  r1 - pointer to registers on stack
-       @
-#ifdef MULTI_PABORT
        mov     r0, r2                  @ pass address of aborted instruction.
+#ifdef MULTI_PABORT
        ldr     r4, .LCprocfns
        mov     lr, pc
        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
 #else
-       CPU_PABORT_HANDLER(r0, r2)
+       bl      CPU_PABORT_HANDLER
 #endif
        msr     cpsr_c, r9                      @ Maybe enable interrupts
-       mov     r1, sp                          @ regs
+       mov     r2, sp                          @ regs
        bl      do_PrefetchAbort                @ call abort handler
 
        @
@@ -701,16 +695,16 @@ ENDPROC(__und_usr_unknown)
 __pabt_usr:
        usr_entry
 
-#ifdef MULTI_PABORT
        mov     r0, r2                  @ pass address of aborted instruction.
+#ifdef MULTI_PABORT
        ldr     r4, .LCprocfns
        mov     lr, pc
        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
 #else
-       CPU_PABORT_HANDLER(r0, r2)
+       bl      CPU_PABORT_HANDLER
 #endif
        enable_irq                              @ Enable interrupts
-       mov     r1, sp                          @ regs
+       mov     r2, sp                          @ regs
        bl      do_PrefetchAbort                @ call abort handler
  UNWIND(.fnend         )
        /* fall through */
index 825db52e558a03cc77a6cb945ae8bf93d1f54871..f0fe95b7085d8020682b297915ba1910af476828 100644 (file)
@@ -425,13 +425,6 @@ sys_mmap2:
 #endif
 ENDPROC(sys_mmap2)
 
-ENTRY(pabort_ifar)
-               mrc     p15, 0, r0, cr6, cr0, 2
-ENTRY(pabort_noifar)
-               mov     pc, lr
-ENDPROC(pabort_ifar)
-ENDPROC(pabort_noifar)
-
 #ifdef CONFIG_OABI_COMPAT
 
 /*
index 8d43e58f9244349601d6001ec6332d6909634017..e993140edd880e3f62be0eed4d6851f5496375ab 100644 (file)
@@ -17,7 +17,7 @@ config CPU_ARM610
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        help
          The ARM610 is the successor to the ARM3 processor
          and was produced by VLSI Technology Inc.
@@ -31,7 +31,7 @@ config CPU_ARM7TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
@@ -49,7 +49,7 @@ config CPU_ARM710
        select CPU_CP15_MMU
        select CPU_COPY_V3 if MMU
        select CPU_TLB_V3 if MMU
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        help
          A 32-bit RISC microprocessor based on the ARM7 processor core
          designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,7 +64,7 @@ config CPU_ARM720T
        bool "Support ARM720T processor" if ARCH_INTEGRATOR
        select CPU_32v4T
        select CPU_ABRT_LV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -83,7 +83,7 @@ config CPU_ARM740T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_LV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V3     # although the core is v4t
        select CPU_CP15_MPU
        help
@@ -100,7 +100,7 @@ config CPU_ARM9TDMI
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4
        help
          A 32-bit RISC microprocessor based on the ARM9 processor core
@@ -114,7 +114,7 @@ config CPU_ARM920T
        bool "Support ARM920T processor" if ARCH_INTEGRATOR
        select CPU_32v4T
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -135,7 +135,7 @@ config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR
        select CPU_32v4T
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -154,7 +154,7 @@ config CPU_ARM925T
        bool "Support ARM925T processor" if ARCH_OMAP1
        select CPU_32v4T
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -173,7 +173,7 @@ config CPU_ARM926T
        bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
        select CPU_32v5
        select CPU_ABRT_EV5TJ
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU
@@ -191,7 +191,7 @@ config CPU_FA526
        bool
        select CPU_32v4
        select CPU_ABRT_EV4
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_CACHE_FA
@@ -210,7 +210,7 @@ config CPU_ARM940T
        depends on !MMU
        select CPU_32v4T
        select CPU_ABRT_NOMMU
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
@@ -228,7 +228,7 @@ config CPU_ARM946E
        depends on !MMU
        select CPU_32v5
        select CPU_ABRT_NOMMU
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MPU
        help
@@ -244,7 +244,7 @@ config CPU_ARM1020
        bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
        select CPU_32v5
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -262,7 +262,7 @@ config CPU_ARM1020E
        bool "Support ARM1020E processor" if ARCH_INTEGRATOR
        select CPU_32v5
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WT
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -275,7 +275,7 @@ config CPU_ARM1022
        bool "Support ARM1022E processor" if ARCH_INTEGRATOR
        select CPU_32v5
        select CPU_ABRT_EV4T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,7 +293,7 @@ config CPU_ARM1026
        bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
        select CPU_32v5
        select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_V4WB if MMU # can probably do better
@@ -311,7 +311,7 @@ config CPU_SA110
        select CPU_32v3 if ARCH_RPC
        select CPU_32v4 if !ARCH_RPC
        select CPU_ABRT_EV4
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -331,7 +331,7 @@ config CPU_SA1100
        bool
        select CPU_32v4
        select CPU_ABRT_EV4
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
@@ -342,7 +342,7 @@ config CPU_XSCALE
        bool
        select CPU_32v5
        select CPU_ABRT_EV5T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
@@ -352,7 +352,7 @@ config CPU_XSC3
        bool
        select CPU_32v5
        select CPU_ABRT_EV5T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
@@ -363,7 +363,7 @@ config CPU_MOHAWK
        bool
        select CPU_32v5
        select CPU_ABRT_EV5T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_TLB_V4WBI if MMU
@@ -374,7 +374,7 @@ config CPU_FEROCEON
        bool
        select CPU_32v5
        select CPU_ABRT_EV5T
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_LEGACY
        select CPU_CACHE_VIVT
        select CPU_CP15_MMU
        select CPU_COPY_FEROCEON if MMU
@@ -394,7 +394,7 @@ config CPU_V6
        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
        select CPU_32v6
        select CPU_ABRT_EV6
-       select CPU_PABRT_NOIFAR
+       select CPU_PABRT_V6
        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
@@ -420,7 +420,7 @@ config CPU_V7
        select CPU_32v6K
        select CPU_32v7
        select CPU_ABRT_EV7
-       select CPU_PABRT_IFAR
+       select CPU_PABRT_V7
        select CPU_CACHE_V7
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
@@ -482,10 +482,13 @@ config CPU_ABRT_EV6
 config CPU_ABRT_EV7
        bool
 
-config CPU_PABRT_IFAR
+config CPU_PABRT_LEGACY
        bool
 
-config CPU_PABRT_NOIFAR
+config CPU_PABRT_V6
+       bool
+
+config CPU_PABRT_V7
        bool
 
 # The cache model
index 63e3f6dd0e2196f96eed8be436e6cc287234b72f..055cb2aa8134c63fba47cdfbc6192e3ec3ffd2f6 100644 (file)
@@ -27,6 +27,10 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ) += abort-ev5tj.o
 obj-$(CONFIG_CPU_ABRT_EV6)     += abort-ev6.o
 obj-$(CONFIG_CPU_ABRT_EV7)     += abort-ev7.o
 
+obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
+obj-$(CONFIG_CPU_PABRT_V6)     += pabort-v6.o
+obj-$(CONFIG_CPU_PABRT_V7)     += pabort-v7.o
+
 obj-$(CONFIG_CPU_CACHE_V3)     += cache-v3.o
 obj-$(CONFIG_CPU_CACHE_V4)     += cache-v4.o
 obj-$(CONFIG_CPU_CACHE_V4WT)   += cache-v4wt.o
index 379f7855605554c9ae955cf7ffe44964374f297e..fd2375f849941f7a91727e70e84ba73804d06c35 100644 (file)
@@ -520,7 +520,7 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 }
 
 asmlinkage void __exception
-do_PrefetchAbort(unsigned long addr, struct pt_regs *regs)
+do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
 {
        do_translation_fault(addr, FSR_LNX_PF, regs);
 }
diff --git a/arch/arm/mm/pabort-legacy.S b/arch/arm/mm/pabort-legacy.S
new file mode 100644 (file)
index 0000000..87970eb
--- /dev/null
@@ -0,0 +1,19 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Function: legacy_pabort
+ *
+ * Params  : r0 = address of aborted instruction
+ *
+ * Returns : r0 = address of abort
+ *        : r1 = Simulated IFSR with section translation fault status
+ *
+ * Purpose : obtain information about current prefetch abort.
+ */
+
+       .align  5
+ENTRY(legacy_pabort)
+       mov     r1, #5
+       mov     pc, lr
+ENDPROC(legacy_pabort)
diff --git a/arch/arm/mm/pabort-v6.S b/arch/arm/mm/pabort-v6.S
new file mode 100644 (file)
index 0000000..06e3d1e
--- /dev/null
@@ -0,0 +1,19 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Function: v6_pabort
+ *
+ * Params  : r0 = address of aborted instruction
+ *
+ * Returns : r0 = address of abort
+ *        : r1 = IFSR
+ *
+ * Purpose : obtain information about current prefetch abort.
+ */
+
+       .align  5
+ENTRY(v6_pabort)
+       mrc     p15, 0, r1, c5, c0, 1           @ get IFSR
+       mov     pc, lr
+ENDPROC(v6_pabort)
diff --git a/arch/arm/mm/pabort-v7.S b/arch/arm/mm/pabort-v7.S
new file mode 100644 (file)
index 0000000..a8b3b30
--- /dev/null
@@ -0,0 +1,20 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Function: v6_pabort
+ *
+ * Params  : r0 = address of aborted instruction
+ *
+ * Returns : r0 = address of abort
+ *        : r1 = IFSR
+ *
+ * Purpose : obtain information about current prefetch abort.
+ */
+
+       .align  5
+ENTRY(v7_pabort)
+       mrc     p15, 0, r0, c6, c0, 2           @ get IFAR
+       mrc     p15, 0, r1, c5, c0, 1           @ get IFSR
+       mov     pc, lr
+ENDPROC(v7_pabort)
index b5551bf010aa33668d938e09d184d3df2bc1ec5d..d9fb4b98c49ff8866a1d36288d431ce364ad1180 100644 (file)
@@ -449,7 +449,7 @@ arm1020_crval:
        .type   arm1020_processor_functions, #object
 arm1020_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm1020_proc_init
        .word   cpu_arm1020_proc_fin
        .word   cpu_arm1020_reset
index 8bc6740c29eb68d8bcfdb97111281ecca87e0f41..7453b75dcea5f1527790e940263f113a70aec417 100644 (file)
@@ -430,7 +430,7 @@ arm1020e_crval:
        .type   arm1020e_processor_functions, #object
 arm1020e_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm1020e_proc_init
        .word   cpu_arm1020e_proc_fin
        .word   cpu_arm1020e_reset
index 2cd03e66c0a318f9b28c14bdf0749571604de303..8eb72d75a8b6fe2757e0c6c8bcfa7325519c2a11 100644 (file)
@@ -413,7 +413,7 @@ arm1022_crval:
        .type   arm1022_processor_functions, #object
 arm1022_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm1022_proc_init
        .word   cpu_arm1022_proc_fin
        .word   cpu_arm1022_reset
index ad961a897f6eae5cfad3d3bee1fc6fcd0d8d865f..3b59f0d6713962d3e83222d1d05dc2c10606157c 100644 (file)
@@ -408,7 +408,7 @@ arm1026_crval:
        .type   arm1026_processor_functions, #object
 arm1026_processor_functions:
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm1026_proc_init
        .word   cpu_arm1026_proc_fin
        .word   cpu_arm1026_reset
index 80d6e1de069ada45c74cf6b665b91292d5990019..3f9cd3d8f6d508c447e46c5cf29ca078dd1b630b 100644 (file)
@@ -278,7 +278,7 @@ __arm7_setup:       mov     r0, #0
                .type   arm6_processor_functions, #object
 ENTRY(arm6_processor_functions)
                .word   cpu_arm6_data_abort
-               .word   pabort_noifar
+               .word   legacy_pabort
                .word   cpu_arm6_proc_init
                .word   cpu_arm6_proc_fin
                .word   cpu_arm6_reset
@@ -295,7 +295,7 @@ ENTRY(arm6_processor_functions)
                .type   arm7_processor_functions, #object
 ENTRY(arm7_processor_functions)
                .word   cpu_arm7_data_abort
-               .word   pabort_noifar
+               .word   legacy_pabort
                .word   cpu_arm7_proc_init
                .word   cpu_arm7_proc_fin
                .word   cpu_arm7_reset
index 85ae18695f1021a4cf2299fbcad8f382b9f7c03d..0b62de24466646d8b7e8aa65b84e8ac5191335f5 100644 (file)
@@ -181,7 +181,7 @@ arm720_crval:
                .type   arm720_processor_functions, #object
 ENTRY(arm720_processor_functions)
                .word   v4t_late_abort
-               .word   pabort_noifar
+               .word   legacy_pabort
                .word   cpu_arm720_proc_init
                .word   cpu_arm720_proc_fin
                .word   cpu_arm720_reset
index 4f95bee63e95c0454cc1fc9224a686316db37368..01860cdeb2ec3df451947f325c7d132449820717 100644 (file)
@@ -126,7 +126,7 @@ __arm740_setup:
        .type   arm740_processor_functions, #object
 ENTRY(arm740_processor_functions)
        .word   v4t_late_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm740_proc_init
        .word   cpu_arm740_proc_fin
        .word   cpu_arm740_reset
index 93e05fa7bed44933341d6d4c42db7655b6fafb15..1201b98638298087063d3ec02eefd3a7e58d9aa6 100644 (file)
@@ -64,7 +64,7 @@ __arm7tdmi_setup:
                .type   arm7tdmi_processor_functions, #object
 ENTRY(arm7tdmi_processor_functions)
                .word   v4t_late_abort
-               .word   pabort_noifar
+               .word   legacy_pabort
                .word   cpu_arm7tdmi_proc_init
                .word   cpu_arm7tdmi_proc_fin
                .word   cpu_arm7tdmi_reset
index 914d688394fc150f26c9e4987542dae74a24205a..2b7c197cc58d2ab4babcf39920220b96a973570e 100644 (file)
@@ -395,7 +395,7 @@ arm920_crval:
        .type   arm920_processor_functions, #object
 arm920_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm920_proc_init
        .word   cpu_arm920_proc_fin
        .word   cpu_arm920_reset
index 51c9c9859e58475232851e89c7fa032af52d72ad..06a1aa4e33989976465155586fe0390e19109bb9 100644 (file)
@@ -399,7 +399,7 @@ arm922_crval:
        .type   arm922_processor_functions, #object
 arm922_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm922_proc_init
        .word   cpu_arm922_proc_fin
        .word   cpu_arm922_reset
index 2724526d89c1ccb302055ebf0ef52378497189bc..cb53435a85aee2120f2e97f6b01c24561f32e860 100644 (file)
@@ -462,7 +462,7 @@ arm925_crval:
        .type   arm925_processor_functions, #object
 arm925_processor_functions:
        .word   v4t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm925_proc_init
        .word   cpu_arm925_proc_fin
        .word   cpu_arm925_reset
index 54466937bff994ea288ba5ece9c7c39ddacecbd8..1c4848704bb358c98a0e4c87141f7326e802d3fb 100644 (file)
@@ -415,7 +415,7 @@ arm926_crval:
        .type   arm926_processor_functions, #object
 arm926_processor_functions:
        .word   v5tj_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm926_proc_init
        .word   cpu_arm926_proc_fin
        .word   cpu_arm926_reset
index f595117caf55bb7db716b29e477c7c0f9f49bb95..5b0f8464c8f29f9cc908cd2bbff5a820652f7751 100644 (file)
@@ -322,7 +322,7 @@ __arm940_setup:
        .type   arm940_processor_functions, #object
 ENTRY(arm940_processor_functions)
        .word   nommu_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm940_proc_init
        .word   cpu_arm940_proc_fin
        .word   cpu_arm940_reset
index e03f6ff1fb2631284176fd5cc08c164f592a6f4d..40c0449a139b829a709525984442b36561494e13 100644 (file)
@@ -377,7 +377,7 @@ __arm946_setup:
        .type   arm946_processor_functions, #object
 ENTRY(arm946_processor_functions)
        .word   nommu_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_arm946_proc_init
        .word   cpu_arm946_proc_fin
        .word   cpu_arm946_reset
index be6c11d2b3fbf10092be644df37aba7787387004..28545c29dbcda317db178a564a7a894f3a846f96 100644 (file)
@@ -64,7 +64,7 @@ __arm9tdmi_setup:
                .type   arm9tdmi_processor_functions, #object
 ENTRY(arm9tdmi_processor_functions)
                .word   nommu_early_abort
-               .word   pabort_noifar
+               .word   legacy_pabort
                .word   cpu_arm9tdmi_proc_init
                .word   cpu_arm9tdmi_proc_fin
                .word   cpu_arm9tdmi_reset
index 08b8a955d5d7843baad616afd342707714160a0b..08f5ac237ad4e83e67b7540a9680d28c619edc41 100644 (file)
@@ -191,7 +191,7 @@ fa526_cr1_set:
        .type   fa526_processor_functions, #object
 fa526_processor_functions:
        .word   v4_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_fa526_proc_init
        .word   cpu_fa526_proc_fin
        .word   cpu_fa526_reset
index 0fe1f8fc348802777a02e42da50c58f56e2a2d9e..d0d7795200fc143a0362312c960f334deb5f1957 100644 (file)
@@ -499,7 +499,7 @@ feroceon_crval:
        .type   feroceon_processor_functions, #object
 feroceon_processor_functions:
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_feroceon_proc_init
        .word   cpu_feroceon_proc_fin
        .word   cpu_feroceon_reset
index 540f5078496ba155e2cc91c3656097ebaddd9c0e..52b5fd74fbb3fcbfe3295d570a2e121001318562 100644 (file)
@@ -359,7 +359,7 @@ mohawk_crval:
        .type   mohawk_processor_functions, #object
 mohawk_processor_functions:
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_mohawk_proc_init
        .word   cpu_mohawk_proc_fin
        .word   cpu_mohawk_reset
index 90a7e5279f296c1193cc0a389c9b9d8b1f272186..7b706b38990625c08ca3595ff19b6657fcbb0648 100644 (file)
@@ -199,7 +199,7 @@ sa110_crval:
        .type   sa110_processor_functions, #object
 ENTRY(sa110_processor_functions)
        .word   v4_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_sa110_proc_init
        .word   cpu_sa110_proc_fin
        .word   cpu_sa110_reset
index 451e2d953e2a0389ed462b253ca904053b2b24ff..ee7700242c19567b94ad256984225c66d5e57872 100644 (file)
@@ -214,7 +214,7 @@ sa1100_crval:
        .type   sa1100_processor_functions, #object
 ENTRY(sa1100_processor_functions)
        .word   v4_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_sa1100_proc_init
        .word   cpu_sa1100_proc_fin
        .word   cpu_sa1100_reset
index 524ddae92595052c19ef0e015ab9ed09b24d4026..194737d60a22691c263daf1cba31b0f7ae189e0d 100644 (file)
@@ -191,7 +191,7 @@ v6_crval:
        .type   v6_processor_functions, #object
 ENTRY(v6_processor_functions)
        .word   v6_early_abort
-       .word   pabort_noifar
+       .word   v6_pabort
        .word   cpu_v6_proc_init
        .word   cpu_v6_proc_fin
        .word   cpu_v6_reset
index f3fa1c32fe923cb93f0e73fc14f883182b55df57..23ebcf6eab9f63241e3743170c168e2e38ec0ea2 100644 (file)
@@ -295,7 +295,7 @@ __v7_setup_stack:
        .type   v7_processor_functions, #object
 ENTRY(v7_processor_functions)
        .word   v7_early_abort
-       .word   pabort_ifar
+       .word   v7_pabort
        .word   cpu_v7_proc_init
        .word   cpu_v7_proc_fin
        .word   cpu_v7_reset
index 33515c214b92d5483e7257adf076be3758332993..2028f370288113507d2d5dcfa6e5599629270df5 100644 (file)
@@ -428,7 +428,7 @@ xsc3_crval:
        .type   xsc3_processor_functions, #object
 ENTRY(xsc3_processor_functions)
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_xsc3_proc_init
        .word   cpu_xsc3_proc_fin
        .word   cpu_xsc3_reset
index 423394260bcbd17fc863deecd225bf85f617025c..f056c283682db09b37b3b282a1cded25d9683367 100644 (file)
@@ -511,7 +511,7 @@ xscale_crval:
        .type   xscale_processor_functions, #object
 ENTRY(xscale_processor_functions)
        .word   v5t_early_abort
-       .word   pabort_noifar
+       .word   legacy_pabort
        .word   cpu_xscale_proc_init
        .word   cpu_xscale_proc_fin
        .word   cpu_xscale_reset