2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/kernel.h>
21 #include <linux/string.h>
30 #define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
31 (CHIPREV(sih->chiprev) == 0) && \
32 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
37 get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
40 uint inv = 0, nom = 0;
43 ent = R_REG(si_osh(sih), *eromptr);
49 if ((ent & ER_VALID) == 0) {
54 if (ent == (ER_END | ER_VALID))
57 if ((ent & mask) == match)
63 SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
65 SI_VMSG((" after %d invalid and %d non-matching entries\n",
72 get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
73 u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
77 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
78 if (((asd & ER_TAG1) != ER_ADD) ||
79 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
80 ((asd & AD_ST_MASK) != st)) {
81 /* This is not what we want, "push" it back */
85 *addrl = asd & AD_ADDR_MASK;
87 *addrh = get_erom_ent(sih, eromptr, 0, 0);
91 sz = asd & AD_SZ_MASK;
92 if (sz == AD_SZ_SZD) {
93 szd = get_erom_ent(sih, eromptr, 0, 0);
94 *sizel = szd & SD_SZ_MASK;
96 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
98 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
100 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
101 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
106 static void ai_hwfixup(si_info_t *sii)
110 /* parse the enumeration rom to identify all cores */
111 void ai_scan(si_t *sih, void *regs, uint devid)
113 si_info_t *sii = SI_INFO(sih);
114 chipcregs_t *cc = (chipcregs_t *) regs;
115 u32 erombase, *eromptr, *eromlim;
117 erombase = R_REG(sii->osh, &cc->eromptr);
119 switch (BUSTYPE(sih->bustype)) {
121 eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
125 /* Set wrappers address */
126 sii->curwrap = (void *)((uintptr) regs + SI_CORE_SIZE);
128 /* Now point the window at the erom */
129 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
137 eromptr = (u32 *) (uintptr) erombase;
141 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
146 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
148 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
149 while (eromptr < eromlim) {
150 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
151 u32 mpd, asd, addrl, addrh, sizel, sizeh;
158 /* Grok a component */
159 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
160 if (cia == (ER_END | ER_VALID)) {
161 SI_VMSG(("Found END of erom after %d cores\n",
167 cib = get_erom_ent(sih, &eromptr, 0, 0);
169 if ((cib & ER_TAG) != ER_CI) {
170 SI_ERROR(("CIA not followed by CIB\n"));
174 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
175 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
176 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
177 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
178 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
179 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
180 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
182 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
184 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
186 if ((nmw + nsw == 0)) {
187 /* A component which is not a core */
188 if (cid == OOB_ROUTER_CORE_ID) {
189 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
190 &addrl, &addrh, &sizel, &sizeh);
192 sii->oob_router = addrl;
199 /* sii->eromptr[idx] = base; */
202 sii->coreid[idx] = cid;
204 for (i = 0; i < nmp; i++) {
205 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
206 if ((mpd & ER_TAG) != ER_MP) {
207 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
210 SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
211 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
212 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
215 /* First Slave Address Descriptor should be port 0:
216 * the main register space for the core
219 get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
222 /* Try again to see if it is a bridge */
224 get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
225 &addrh, &sizel, &sizeh);
228 else if ((addrh != 0) || (sizeh != 0)
229 || (sizel != SI_CORE_SIZE)) {
230 SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
234 sii->coresba[idx] = addrl;
235 sii->coresba_size[idx] = sizel;
236 /* Get any more ASDs in port 0 */
240 get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
241 &addrh, &sizel, &sizeh);
242 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
243 sii->coresba2[idx] = addrl;
244 sii->coresba2_size[idx] = sizel;
249 /* Go through the ASDs for other slave ports */
250 for (i = 1; i < nsp; i++) {
254 get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
255 &addrl, &addrh, &sizel, &sizeh);
258 SI_ERROR((" SP %d has no address descriptors\n",
264 /* Now get master wrappers */
265 for (i = 0; i < nmw; i++) {
267 get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
268 &addrh, &sizel, &sizeh);
270 SI_ERROR(("Missing descriptor for MW %d\n", i));
273 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
274 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
278 sii->wrapba[idx] = addrl;
281 /* And finally slave wrappers */
282 for (i = 0; i < nsw; i++) {
283 uint fwp = (nsp == 1) ? 0 : 1;
285 get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
286 &addrl, &addrh, &sizel, &sizeh);
288 SI_ERROR(("Missing descriptor for SW %d\n", i));
291 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
292 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
295 if ((nmw == 0) && (i == 0))
296 sii->wrapba[idx] = addrl;
299 /* Don't record bridges */
307 SI_ERROR(("Reached end of erom without finding END"));
314 /* This function changes the logical "focus" to the indicated core.
315 * Return the current core's virtual address.
317 void *ai_setcoreidx(si_t *sih, uint coreidx)
319 si_info_t *sii = SI_INFO(sih);
320 u32 addr = sii->coresba[coreidx];
321 u32 wrap = sii->wrapba[coreidx];
324 if (coreidx >= sii->numcores)
328 * If the user has provided an interrupt mask enabled function,
329 * then assert interrupts are disabled before switching the core.
331 ASSERT((sii->intrsenabled_fn == NULL)
332 || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
334 switch (BUSTYPE(sih->bustype)) {
337 if (!sii->regs[coreidx]) {
338 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
339 ASSERT(GOODREGS(sii->regs[coreidx]));
341 sii->curmap = regs = sii->regs[coreidx];
342 if (!sii->wrappers[coreidx]) {
343 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
344 ASSERT(GOODREGS(sii->wrappers[coreidx]));
346 sii->curwrap = sii->wrappers[coreidx];
350 /* point bar0 window */
351 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
353 /* point bar0 2nd 4KB window */
354 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
361 sii->curmap = regs = (void *)((uintptr) addr);
362 sii->curwrap = (void *)((uintptr) wrap);
372 sii->curidx = coreidx;
377 /* Return the number of address spaces in current core */
378 int ai_numaddrspaces(si_t *sih)
383 /* Return the address of the nth address space in the current core */
384 u32 ai_addrspace(si_t *sih, uint asidx)
393 return sii->coresba[cidx];
395 return sii->coresba2[cidx];
397 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
402 /* Return the size of the nth address space in the current core */
403 u32 ai_addrspacesize(si_t *sih, uint asidx)
412 return sii->coresba_size[cidx];
414 return sii->coresba2_size[cidx];
416 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
421 uint ai_flag(si_t *sih)
427 if (BCM47162_DMP()) {
428 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
433 return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
436 void ai_setint(si_t *sih, int siflag)
440 void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
442 si_info_t *sii = SI_INFO(sih);
443 u32 *w = (u32 *) sii->curwrap;
444 W_REG(sii->osh, w + (offset / 4), val);
448 uint ai_corevendor(si_t *sih)
454 cia = sii->cia[sii->curidx];
455 return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
458 uint ai_corerev(si_t *sih)
464 cib = sii->cib[sii->curidx];
465 return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
468 bool ai_iscoreup(si_t *sih)
476 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
478 && ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
482 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
483 * switch back to the original core, and return the new value.
485 * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
487 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
488 * and (on newer pci cores) chipcommon registers.
490 uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
501 ASSERT(GOODIDX(coreidx));
502 ASSERT(regoff < SI_CORE_SIZE);
503 ASSERT((val & ~mask) == 0);
505 if (coreidx >= SI_MAXCORES)
508 if (BUSTYPE(sih->bustype) == SI_BUS) {
509 /* If internal bus, we can always get at everything */
511 /* map if does not exist */
512 if (!sii->regs[coreidx]) {
513 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
515 ASSERT(GOODREGS(sii->regs[coreidx]));
517 r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
518 } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
519 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
521 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
522 /* Chipc registers are mapped at 12KB */
525 r = (u32 *) ((char *)sii->curmap +
526 PCI_16KB0_CCREGS_OFFSET + regoff);
527 } else if (sii->pub.buscoreidx == coreidx) {
528 /* pci registers are at either in the last 2KB of an 8KB window
529 * or, in pcie and pci rev 13 at 8KB
533 r = (u32 *) ((char *)sii->curmap +
534 PCI_16KB0_PCIREGS_OFFSET +
537 r = (u32 *) ((char *)sii->curmap +
538 ((regoff >= SBCONFIGOFF) ?
539 PCI_BAR0_PCISBR_OFFSET :
540 PCI_BAR0_PCIREGS_OFFSET) +
546 INTR_OFF(sii, intr_val);
548 /* save current core index */
549 origidx = si_coreidx(&sii->pub);
552 r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
559 w = (R_REG(sii->osh, r) & ~mask) | val;
560 W_REG(sii->osh, r, w);
564 w = R_REG(sii->osh, r);
567 /* restore core index */
568 if (origidx != coreidx)
569 ai_setcoreidx(&sii->pub, origidx);
571 INTR_RESTORE(sii, intr_val);
577 void ai_core_disable(si_t *sih, u32 bits)
585 ASSERT(GOODREGS(sii->curwrap));
588 /* if core is already in reset, just return */
589 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
592 W_REG(sii->osh, &ai->ioctrl, bits);
593 dummy = R_REG(sii->osh, &ai->ioctrl);
596 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
600 /* reset and re-enable a core
602 * bits - core specific bits that are set during and after reset sequence
603 * resetbits - core specific bits that are set only during reset sequence
605 void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
612 ASSERT(GOODREGS(sii->curwrap));
616 * Must do the disable sequence first to work for arbitrary current core state.
618 ai_core_disable(sih, (bits | resetbits));
621 * Now do the initialization sequence.
623 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
624 dummy = R_REG(sii->osh, &ai->ioctrl);
625 W_REG(sii->osh, &ai->resetctrl, 0);
628 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
629 dummy = R_REG(sii->osh, &ai->ioctrl);
633 void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
641 if (BCM47162_DMP()) {
642 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
647 ASSERT(GOODREGS(sii->curwrap));
650 ASSERT((val & ~mask) == 0);
653 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
654 W_REG(sii->osh, &ai->ioctrl, w);
658 u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
665 if (BCM47162_DMP()) {
666 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
671 ASSERT(GOODREGS(sii->curwrap));
674 ASSERT((val & ~mask) == 0);
677 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
678 W_REG(sii->osh, &ai->ioctrl, w);
681 return R_REG(sii->osh, &ai->ioctrl);
684 u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
691 if (BCM47162_DMP()) {
692 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
696 ASSERT(GOODREGS(sii->curwrap));
699 ASSERT((val & ~mask) == 0);
700 ASSERT((mask & ~SISF_CORE_BITS) == 0);
703 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
704 W_REG(sii->osh, &ai->iostatus, w);
707 return R_REG(sii->osh, &ai->iostatus);