drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     115
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "October 14, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          RX_STD_MAX_SIZE_5717 : 512)
 108 #define TG3_DEF_RX_RING_PENDING         200
 109 #define TG3_RX_JMB_RING_SIZE(tp) \
 110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 112          1024 : 256)
 113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 114 #define TG3_RSS_INDIR_TBL_SIZE          128
 115
 116 /* Do not place this n-ring entries value into the tp struct itself,
 117  * we really want to expose these constants to GCC so that modulo et
 118  * al.  operations are done with shifts and masks instead of with
 119  * hw multiply/modulo instructions.  Another solution would be to
 120  * replace things like '% foo' with '& (foo - 1)'.
 121  */
 122
 123 #define TG3_TX_RING_SIZE                512
 124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 125
 126 #define TG3_RX_STD_RING_BYTES(tp) \
 127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 128 #define TG3_RX_JMB_RING_BYTES(tp) \
 129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 130 #define TG3_RX_RCB_RING_BYTES(tp) \
 131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 133                                  TG3_TX_RING_SIZE)
 134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 135
 136 #define TG3_RX_DMA_ALIGN                16
 137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 138
 139 #define TG3_DMA_BYTE_ENAB               64
 140
 141 #define TG3_RX_STD_DMA_SZ               1536
 142 #define TG3_RX_JMB_DMA_SZ               9046
 143
 144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 145
 146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 148
 149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 151
 152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 154
 155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 156  * that are at least dword aligned when used in PCIX mode.  The driver
 157  * works around this bug by double copying the packet.  This workaround
 158  * is built into the normal double copy length check for efficiency.
 159  *
 160  * However, the double copy is only necessary on those architectures
 161  * where unaligned memory accesses are inefficient.  For those architectures
 162  * where unaligned memory accesses incur little penalty, we can reintegrate
 163  * the 5701 in the normal rx path.  Doing so saves a device structure
 164  * dereference by hardcoding the double copy threshold in place.
 165  */
 166 #define TG3_RX_COPY_THRESHOLD           256
 167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 169 #else
 170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 171 #endif
 172
 173 /* minimum number of free TX descriptors required to wake up TX process */
 174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 175
 176 #define TG3_RAW_IP_ALIGN 2
 177
 178 /* number of ETHTOOL_GSTATS u64's */
 179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 180
 181 #define TG3_NUM_TEST            6
 182
 183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 184
 185 #define FIRMWARE_TG3            "tigon/tg3.bin"
 186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 188
 189 static char version[] __devinitdata =
 190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 191
 192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 194 MODULE_LICENSE("GPL");
 195 MODULE_VERSION(DRV_MODULE_VERSION);
 196 MODULE_FIRMWARE(FIRMWARE_TG3);
 197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 199
 200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 201 module_param(tg3_debug, int, 0);
 202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 203
 204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 284         {}
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 288
 289 static const struct {
 290         const char string[ETH_GSTRING_LEN];
 291 } ethtool_stats_keys[TG3_NUM_STATS] = {
 292         { "rx_octets" },
 293         { "rx_fragments" },
 294         { "rx_ucast_packets" },
 295         { "rx_mcast_packets" },
 296         { "rx_bcast_packets" },
 297         { "rx_fcs_errors" },
 298         { "rx_align_errors" },
 299         { "rx_xon_pause_rcvd" },
 300         { "rx_xoff_pause_rcvd" },
 301         { "rx_mac_ctrl_rcvd" },
 302         { "rx_xoff_entered" },
 303         { "rx_frame_too_long_errors" },
 304         { "rx_jabbers" },
 305         { "rx_undersize_packets" },
 306         { "rx_in_length_errors" },
 307         { "rx_out_length_errors" },
 308         { "rx_64_or_less_octet_packets" },
 309         { "rx_65_to_127_octet_packets" },
 310         { "rx_128_to_255_octet_packets" },
 311         { "rx_256_to_511_octet_packets" },
 312         { "rx_512_to_1023_octet_packets" },
 313         { "rx_1024_to_1522_octet_packets" },
 314         { "rx_1523_to_2047_octet_packets" },
 315         { "rx_2048_to_4095_octet_packets" },
 316         { "rx_4096_to_8191_octet_packets" },
 317         { "rx_8192_to_9022_octet_packets" },
 318
 319         { "tx_octets" },
 320         { "tx_collisions" },
 321
 322         { "tx_xon_sent" },
 323         { "tx_xoff_sent" },
 324         { "tx_flow_control" },
 325         { "tx_mac_errors" },
 326         { "tx_single_collisions" },
 327         { "tx_mult_collisions" },
 328         { "tx_deferred" },
 329         { "tx_excessive_collisions" },
 330         { "tx_late_collisions" },
 331         { "tx_collide_2times" },
 332         { "tx_collide_3times" },
 333         { "tx_collide_4times" },
 334         { "tx_collide_5times" },
 335         { "tx_collide_6times" },
 336         { "tx_collide_7times" },
 337         { "tx_collide_8times" },
 338         { "tx_collide_9times" },
 339         { "tx_collide_10times" },
 340         { "tx_collide_11times" },
 341         { "tx_collide_12times" },
 342         { "tx_collide_13times" },
 343         { "tx_collide_14times" },
 344         { "tx_collide_15times" },
 345         { "tx_ucast_packets" },
 346         { "tx_mcast_packets" },
 347         { "tx_bcast_packets" },
 348         { "tx_carrier_sense_errors" },
 349         { "tx_discards" },
 350         { "tx_errors" },
 351
 352         { "dma_writeq_full" },
 353         { "dma_write_prioq_full" },
 354         { "rxbds_empty" },
 355         { "rx_discards" },
 356         { "rx_errors" },
 357         { "rx_threshold_hit" },
 358
 359         { "dma_readq_full" },
 360         { "dma_read_prioq_full" },
 361         { "tx_comp_queue_full" },
 362
 363         { "ring_set_send_prod_index" },
 364         { "ring_status_update" },
 365         { "nic_irqs" },
 366         { "nic_avoided_irqs" },
 367         { "nic_tx_threshold_hit" }
 368 };
 369
 370 static const struct {
 371         const char string[ETH_GSTRING_LEN];
 372 } ethtool_test_keys[TG3_NUM_TEST] = {
 373         { "nvram test     (online) " },
 374         { "link test      (online) " },
 375         { "register test  (offline)" },
 376         { "memory test    (offline)" },
 377         { "loopback test  (offline)" },
 378         { "interrupt test (offline)" },
 379 };
 380
 381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384 }
 385
 386 static u32 tg3_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->regs + off);
 389 }
 390
 391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         writel(val, tp->aperegs + off);
 394 }
 395
 396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 397 {
 398         return readl(tp->aperegs + off);
 399 }
 400
 401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409 }
 410
 411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         writel(val, tp->regs + off);
 414         readl(tp->regs + off);
 415 }
 416
 417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 430 {
 431         unsigned long flags;
 432
 433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 435                                        TG3_64BIT_REG_LOW, val);
 436                 return;
 437         }
 438         if (off == TG3_RX_STD_PROD_IDX_REG) {
 439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 440                                        TG3_64BIT_REG_LOW, val);
 441                 return;
 442         }
 443
 444         spin_lock_irqsave(&tp->indirect_lock, flags);
 445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 448
 449         /* In indirect mode when disabling interrupts, we also need
 450          * to clear the interrupt bit in the GRC local ctrl register.
 451          */
 452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 453             (val == 0x1)) {
 454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 456         }
 457 }
 458
 459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 460 {
 461         unsigned long flags;
 462         u32 val;
 463
 464         spin_lock_irqsave(&tp->indirect_lock, flags);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 468         return val;
 469 }
 470
 471 /* usec_wait specifies the wait time in usec when writing to certain registers
 472  * where it is unsafe to read back the register without some delay.
 473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 475  */
 476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 477 {
 478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 480                 /* Non-posted methods */
 481                 tp->write32(tp, off, val);
 482         else {
 483                 /* Posted method */
 484                 tg3_write32(tp, off, val);
 485                 if (usec_wait)
 486                         udelay(usec_wait);
 487                 tp->read32(tp, off);
 488         }
 489         /* Wait again after the read for the posted method to guarantee that
 490          * the wait time is met.
 491          */
 492         if (usec_wait)
 493                 udelay(usec_wait);
 494 }
 495
 496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         tp->write32_mbox(tp, off, val);
 499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 501                 tp->read32_mbox(tp, off);
 502 }
 503
 504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         void __iomem *mbox = tp->regs + off;
 507         writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 509                 writel(val, mbox);
 510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 511                 readl(mbox);
 512 }
 513
 514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 515 {
 516         return readl(tp->regs + off + GRCMBOX_BASE);
 517 }
 518
 519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 520 {
 521         writel(val, tp->regs + off + GRCMBOX_BASE);
 522 }
 523
 524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 529
 530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 533 #define tr32(reg)                       tp->read32(tp, reg)
 534
 535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 541                 return;
 542
 543         spin_lock_irqsave(&tp->indirect_lock, flags);
 544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 547
 548                 /* Always leave this as zero. */
 549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         } else {
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 553
 554                 /* Always leave this as zero. */
 555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 556         }
 557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 558 }
 559
 560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 561 {
 562         unsigned long flags;
 563
 564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 566                 *val = 0;
 567                 return;
 568         }
 569
 570         spin_lock_irqsave(&tp->indirect_lock, flags);
 571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 574
 575                 /* Always leave this as zero. */
 576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 577         } else {
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 580
 581                 /* Always leave this as zero. */
 582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 583         }
 584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 585 }
 586
 587 static void tg3_ape_lock_init(struct tg3 *tp)
 588 {
 589         int i;
 590         u32 regbase;
 591
 592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 593                 regbase = TG3_APE_LOCK_GRANT;
 594         else
 595                 regbase = TG3_APE_PER_LOCK_GRANT;
 596
 597         /* Make sure the driver hasn't any stale locks. */
 598         for (i = 0; i < 8; i++)
 599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 600 }
 601
 602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 603 {
 604         int i, off;
 605         int ret = 0;
 606         u32 status, req, gnt;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return 0;
 610
 611         switch (locknum) {
 612         case TG3_APE_LOCK_GRC:
 613         case TG3_APE_LOCK_MEM:
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 620                 req = TG3_APE_LOCK_REQ;
 621                 gnt = TG3_APE_LOCK_GRANT;
 622         } else {
 623                 req = TG3_APE_PER_LOCK_REQ;
 624                 gnt = TG3_APE_PER_LOCK_GRANT;
 625         }
 626
 627         off = 4 * locknum;
 628
 629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 630
 631         /* Wait for up to 1 millisecond to acquire lock. */
 632         for (i = 0; i < 100; i++) {
 633                 status = tg3_ape_read32(tp, gnt + off);
 634                 if (status == APE_LOCK_GRANT_DRIVER)
 635                         break;
 636                 udelay(10);
 637         }
 638
 639         if (status != APE_LOCK_GRANT_DRIVER) {
 640                 /* Revoke the lock request. */
 641                 tg3_ape_write32(tp, gnt + off,
 642                                 APE_LOCK_GRANT_DRIVER);
 643
 644                 ret = -EBUSY;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 651 {
 652         u32 gnt;
 653
 654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 655                 return;
 656
 657         switch (locknum) {
 658         case TG3_APE_LOCK_GRC:
 659         case TG3_APE_LOCK_MEM:
 660                 break;
 661         default:
 662                 return;
 663         }
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 gnt = TG3_APE_LOCK_GRANT;
 667         else
 668                 gnt = TG3_APE_PER_LOCK_GRANT;
 669
 670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 671 }
 672
 673 static void tg3_disable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tw32(TG3PCI_MISC_HOST_CTRL,
 678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 679         for (i = 0; i < tp->irq_max; i++)
 680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 681 }
 682
 683 static void tg3_enable_ints(struct tg3 *tp)
 684 {
 685         int i;
 686
 687         tp->irq_sync = 0;
 688         wmb();
 689
 690         tw32(TG3PCI_MISC_HOST_CTRL,
 691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 692
 693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 694         for (i = 0; i < tp->irq_cnt; i++) {
 695                 struct tg3_napi *tnapi = &tp->napi[i];
 696
 697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 700
 701                 tp->coal_now |= tnapi->coal_now;
 702         }
 703
 704         /* Force an initial interrupt */
 705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 708         else
 709                 tw32(HOSTCC_MODE, tp->coal_now);
 710
 711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 712 }
 713
 714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 715 {
 716         struct tg3 *tp = tnapi->tp;
 717         struct tg3_hw_status *sblk = tnapi->hw_status;
 718         unsigned int work_exists = 0;
 719
 720         /* check for phy events */
 721         if (!(tp->tg3_flags &
 722               (TG3_FLAG_USE_LINKCHG_REG |
 723                TG3_FLAG_POLL_SERDES))) {
 724                 if (sblk->status & SD_STATUS_LINK_CHG)
 725                         work_exists = 1;
 726         }
 727         /* check for RX/TX work to do */
 728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 730                 work_exists = 1;
 731
 732         return work_exists;
 733 }
 734
 735 /* tg3_int_reenable
 736  *  similar to tg3_enable_ints, but it accurately determines whether there
 737  *  is new work pending and can return without flushing the PIO write
 738  *  which reenables interrupts
 739  */
 740 static void tg3_int_reenable(struct tg3_napi *tnapi)
 741 {
 742         struct tg3 *tp = tnapi->tp;
 743
 744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 745         mmiowb();
 746
 747         /* When doing tagged status, this work check is unnecessary.
 748          * The last_tag we write above tells the chip which piece of
 749          * work we've completed.
 750          */
 751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 752             tg3_has_work(tnapi))
 753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 755 }
 756
 757 static void tg3_switch_clocks(struct tg3 *tp)
 758 {
 759         u32 clock_ctrl;
 760         u32 orig_clock_ctrl;
 761
 762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 764                 return;
 765
 766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 767
 768         orig_clock_ctrl = clock_ctrl;
 769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 770                        CLOCK_CTRL_CLKRUN_OENABLE |
 771                        0x1f);
 772         tp->pci_clock_ctrl = clock_ctrl;
 773
 774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 778                 }
 779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 781                             clock_ctrl |
 782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 783                             40);
 784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 786                             40);
 787         }
 788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 789 }
 790
 791 #define PHY_BUSY_LOOPS  5000
 792
 793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 794 {
 795         u32 frame_val;
 796         unsigned int loops;
 797         int ret;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         *val = 0x0;
 806
 807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 808                       MI_COM_PHY_ADDR_MASK);
 809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 810                       MI_COM_REG_ADDR_MASK);
 811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 812
 813         tw32_f(MAC_MI_COM, frame_val);
 814
 815         loops = PHY_BUSY_LOOPS;
 816         while (loops != 0) {
 817                 udelay(10);
 818                 frame_val = tr32(MAC_MI_COM);
 819
 820                 if ((frame_val & MI_COM_BUSY) == 0) {
 821                         udelay(5);
 822                         frame_val = tr32(MAC_MI_COM);
 823                         break;
 824                 }
 825                 loops -= 1;
 826         }
 827
 828         ret = -EBUSY;
 829         if (loops != 0) {
 830                 *val = frame_val & MI_COM_DATA_MASK;
 831                 ret = 0;
 832         }
 833
 834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 836                 udelay(80);
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 843 {
 844         u32 frame_val;
 845         unsigned int loops;
 846         int ret;
 847
 848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 850                 return 0;
 851
 852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 853                 tw32_f(MAC_MI_MODE,
 854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 855                 udelay(80);
 856         }
 857
 858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 859                       MI_COM_PHY_ADDR_MASK);
 860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 861                       MI_COM_REG_ADDR_MASK);
 862         frame_val |= (val & MI_COM_DATA_MASK);
 863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 864
 865         tw32_f(MAC_MI_COM, frame_val);
 866
 867         loops = PHY_BUSY_LOOPS;
 868         while (loops != 0) {
 869                 udelay(10);
 870                 frame_val = tr32(MAC_MI_COM);
 871                 if ((frame_val & MI_COM_BUSY) == 0) {
 872                         udelay(5);
 873                         frame_val = tr32(MAC_MI_COM);
 874                         break;
 875                 }
 876                 loops -= 1;
 877         }
 878
 879         ret = -EBUSY;
 880         if (loops != 0)
 881                 ret = 0;
 882
 883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 885                 udelay(80);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static int tg3_bmcr_reset(struct tg3 *tp)
 892 {
 893         u32 phy_control;
 894         int limit, err;
 895
 896         /* OK, reset it, and poll the BMCR_RESET bit until it
 897          * clears or we time out.
 898          */
 899         phy_control = BMCR_RESET;
 900         err = tg3_writephy(tp, MII_BMCR, phy_control);
 901         if (err != 0)
 902                 return -EBUSY;
 903
 904         limit = 5000;
 905         while (limit--) {
 906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 907                 if (err != 0)
 908                         return -EBUSY;
 909
 910                 if ((phy_control & BMCR_RESET) == 0) {
 911                         udelay(40);
 912                         break;
 913                 }
 914                 udelay(10);
 915         }
 916         if (limit < 0)
 917                 return -EBUSY;
 918
 919         return 0;
 920 }
 921
 922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 923 {
 924         struct tg3 *tp = bp->priv;
 925         u32 val;
 926
 927         spin_lock_bh(&tp->lock);
 928
 929         if (tg3_readphy(tp, reg, &val))
 930                 val = -EIO;
 931
 932         spin_unlock_bh(&tp->lock);
 933
 934         return val;
 935 }
 936
 937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 938 {
 939         struct tg3 *tp = bp->priv;
 940         u32 ret = 0;
 941
 942         spin_lock_bh(&tp->lock);
 943
 944         if (tg3_writephy(tp, reg, val))
 945                 ret = -EIO;
 946
 947         spin_unlock_bh(&tp->lock);
 948
 949         return ret;
 950 }
 951
 952 static int tg3_mdio_reset(struct mii_bus *bp)
 953 {
 954         return 0;
 955 }
 956
 957 static void tg3_mdio_config_5785(struct tg3 *tp)
 958 {
 959         u32 val;
 960         struct phy_device *phydev;
 961
 962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 964         case PHY_ID_BCM50610:
 965         case PHY_ID_BCM50610M:
 966                 val = MAC_PHYCFG2_50610_LED_MODES;
 967                 break;
 968         case PHY_ID_BCMAC131:
 969                 val = MAC_PHYCFG2_AC131_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8211C:
 972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 973                 break;
 974         case PHY_ID_RTL8201E:
 975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 982                 tw32(MAC_PHYCFG2, val);
 983
 984                 val = tr32(MAC_PHYCFG1);
 985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 988                 tw32(MAC_PHYCFG1, val);
 989
 990                 return;
 991         }
 992
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 995                        MAC_PHYCFG2_FMODE_MASK_MASK |
 996                        MAC_PHYCFG2_GMODE_MASK_MASK |
 997                        MAC_PHYCFG2_ACT_MASK_MASK   |
 998                        MAC_PHYCFG2_QUAL_MASK_MASK |
 999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2732                         mac_mode |= MAC_MODE_APE_TX_EN |
2733                                     MAC_MODE_APE_RX_EN |
2734                                     MAC_MODE_TDE_ENABLE;
2735
2736                 tw32_f(MAC_MODE, mac_mode);
2737                 udelay(100);
2738
2739                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2740                 udelay(10);
2741         }
2742
2743         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2744             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2745              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2746                 u32 base_val;
2747
2748                 base_val = tp->pci_clock_ctrl;
2749                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2750                              CLOCK_CTRL_TXCLK_DISABLE);
2751
2752                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2753                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2754         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2755                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2756                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2757                 /* do nothing */
2758         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2759                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2760                 u32 newbits1, newbits2;
2761
2762                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2763                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2764                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2765                                     CLOCK_CTRL_TXCLK_DISABLE |
2766                                     CLOCK_CTRL_ALTCLK);
2767                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2768                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2769                         newbits1 = CLOCK_CTRL_625_CORE;
2770                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2771                 } else {
2772                         newbits1 = CLOCK_CTRL_ALTCLK;
2773                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2774                 }
2775
2776                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2777                             40);
2778
2779                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2780                             40);
2781
2782                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2783                         u32 newbits3;
2784
2785                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2786                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2787                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2788                                             CLOCK_CTRL_TXCLK_DISABLE |
2789                                             CLOCK_CTRL_44MHZ_CORE);
2790                         } else {
2791                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2792                         }
2793
2794                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2795                                     tp->pci_clock_ctrl | newbits3, 40);
2796                 }
2797         }
2798
2799         if (!(device_should_wake) &&
2800             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2801                 tg3_power_down_phy(tp, do_low_power);
2802
2803         tg3_frob_aux_power(tp);
2804
2805         /* Workaround for unstable PLL clock */
2806         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2807             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2808                 u32 val = tr32(0x7d00);
2809
2810                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2811                 tw32(0x7d00, val);
2812                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2813                         int err;
2814
2815                         err = tg3_nvram_lock(tp);
2816                         tg3_halt_cpu(tp, RX_CPU_BASE);
2817                         if (!err)
2818                                 tg3_nvram_unlock(tp);
2819                 }
2820         }
2821
2822         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2823
2824         if (device_should_wake)
2825                 pci_enable_wake(tp->pdev, state, true);
2826
2827         /* Finally, set the new power state. */
2828         pci_set_power_state(tp->pdev, state);
2829
2830         return 0;
2831 }
2832
2833 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2834 {
2835         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2836         case MII_TG3_AUX_STAT_10HALF:
2837                 *speed = SPEED_10;
2838                 *duplex = DUPLEX_HALF;
2839                 break;
2840
2841         case MII_TG3_AUX_STAT_10FULL:
2842                 *speed = SPEED_10;
2843                 *duplex = DUPLEX_FULL;
2844                 break;
2845
2846         case MII_TG3_AUX_STAT_100HALF:
2847                 *speed = SPEED_100;
2848                 *duplex = DUPLEX_HALF;
2849                 break;
2850
2851         case MII_TG3_AUX_STAT_100FULL:
2852                 *speed = SPEED_100;
2853                 *duplex = DUPLEX_FULL;
2854                 break;
2855
2856         case MII_TG3_AUX_STAT_1000HALF:
2857                 *speed = SPEED_1000;
2858                 *duplex = DUPLEX_HALF;
2859                 break;
2860
2861         case MII_TG3_AUX_STAT_1000FULL:
2862                 *speed = SPEED_1000;
2863                 *duplex = DUPLEX_FULL;
2864                 break;
2865
2866         default:
2867                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2868                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2869                                  SPEED_10;
2870                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2871                                   DUPLEX_HALF;
2872                         break;
2873                 }
2874                 *speed = SPEED_INVALID;
2875                 *duplex = DUPLEX_INVALID;
2876                 break;
2877         }
2878 }
2879
2880 static void tg3_phy_copper_begin(struct tg3 *tp)
2881 {
2882         u32 new_adv;
2883         int i;
2884
2885         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2886                 /* Entering low power mode.  Disable gigabit and
2887                  * 100baseT advertisements.
2888                  */
2889                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2890
2891                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2892                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2893                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2894                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2895
2896                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2897         } else if (tp->link_config.speed == SPEED_INVALID) {
2898                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2899                         tp->link_config.advertising &=
2900                                 ~(ADVERTISED_1000baseT_Half |
2901                                   ADVERTISED_1000baseT_Full);
2902
2903                 new_adv = ADVERTISE_CSMA;
2904                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2905                         new_adv |= ADVERTISE_10HALF;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2907                         new_adv |= ADVERTISE_10FULL;
2908                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2909                         new_adv |= ADVERTISE_100HALF;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2911                         new_adv |= ADVERTISE_100FULL;
2912
2913                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2914
2915                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                 if (tp->link_config.advertising &
2918                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2919                         new_adv = 0;
2920                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2921                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2924                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2925                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2926                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2927                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2928                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2929                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2930                 } else {
2931                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2932                 }
2933         } else {
2934                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2935                 new_adv |= ADVERTISE_CSMA;
2936
2937                 /* Asking for a specific link mode. */
2938                 if (tp->link_config.speed == SPEED_1000) {
2939                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2940
2941                         if (tp->link_config.duplex == DUPLEX_FULL)
2942                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2943                         else
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2945                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2946                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2947                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2948                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2949                 } else {
2950                         if (tp->link_config.speed == SPEED_100) {
2951                                 if (tp->link_config.duplex == DUPLEX_FULL)
2952                                         new_adv |= ADVERTISE_100FULL;
2953                                 else
2954                                         new_adv |= ADVERTISE_100HALF;
2955                         } else {
2956                                 if (tp->link_config.duplex == DUPLEX_FULL)
2957                                         new_adv |= ADVERTISE_10FULL;
2958                                 else
2959                                         new_adv |= ADVERTISE_10HALF;
2960                         }
2961                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2962
2963                         new_adv = 0;
2964                 }
2965
2966                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2967         }
2968
2969         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2970                 u32 val = 0;
2971
2972                 tw32(TG3_CPMU_EEE_MODE,
2973                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2974
2975                 /* Enable SM_DSP clock and tx 6dB coding. */
2976                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2977                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2978                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2980
2981                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2982                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2983                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2984                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2985                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2986
2987                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2988                         /* Advertise 100-BaseTX EEE ability */
2989                         if (tp->link_config.advertising &
2990                             (ADVERTISED_100baseT_Half |
2991                              ADVERTISED_100baseT_Full))
2992                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2993                         /* Advertise 1000-BaseT EEE ability */
2994                         if (tp->link_config.advertising &
2995                             (ADVERTISED_1000baseT_Half |
2996                              ADVERTISED_1000baseT_Full))
2997                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
2998                 }
2999                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3000
3001                 /* Turn off SM_DSP clock. */
3002                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3003                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3005         }
3006
3007         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3008             tp->link_config.speed != SPEED_INVALID) {
3009                 u32 bmcr, orig_bmcr;
3010
3011                 tp->link_config.active_speed = tp->link_config.speed;
3012                 tp->link_config.active_duplex = tp->link_config.duplex;
3013
3014                 bmcr = 0;
3015                 switch (tp->link_config.speed) {
3016                 default:
3017                 case SPEED_10:
3018                         break;
3019
3020                 case SPEED_100:
3021                         bmcr |= BMCR_SPEED100;
3022                         break;
3023
3024                 case SPEED_1000:
3025                         bmcr |= TG3_BMCR_SPEED1000;
3026                         break;
3027                 }
3028
3029                 if (tp->link_config.duplex == DUPLEX_FULL)
3030                         bmcr |= BMCR_FULLDPLX;
3031
3032                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3033                     (bmcr != orig_bmcr)) {
3034                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3035                         for (i = 0; i < 1500; i++) {
3036                                 u32 tmp;
3037
3038                                 udelay(10);
3039                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3040                                     tg3_readphy(tp, MII_BMSR, &tmp))
3041                                         continue;
3042                                 if (!(tmp & BMSR_LSTATUS)) {
3043                                         udelay(40);
3044                                         break;
3045                                 }
3046                         }
3047                         tg3_writephy(tp, MII_BMCR, bmcr);
3048                         udelay(40);
3049                 }
3050         } else {
3051                 tg3_writephy(tp, MII_BMCR,
3052                              BMCR_ANENABLE | BMCR_ANRESTART);
3053         }
3054 }
3055
3056 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3057 {
3058         int err;
3059
3060         /* Turn off tap power management. */
3061         /* Set Extended packet length bit */
3062         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3063
3064         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3065         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3066         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3067         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3068         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3069
3070         udelay(40);
3071
3072         return err;
3073 }
3074
3075 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3076 {
3077         u32 adv_reg, all_mask = 0;
3078
3079         if (mask & ADVERTISED_10baseT_Half)
3080                 all_mask |= ADVERTISE_10HALF;
3081         if (mask & ADVERTISED_10baseT_Full)
3082                 all_mask |= ADVERTISE_10FULL;
3083         if (mask & ADVERTISED_100baseT_Half)
3084                 all_mask |= ADVERTISE_100HALF;
3085         if (mask & ADVERTISED_100baseT_Full)
3086                 all_mask |= ADVERTISE_100FULL;
3087
3088         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3089                 return 0;
3090
3091         if ((adv_reg & all_mask) != all_mask)
3092                 return 0;
3093         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3094                 u32 tg3_ctrl;
3095
3096                 all_mask = 0;
3097                 if (mask & ADVERTISED_1000baseT_Half)
3098                         all_mask |= ADVERTISE_1000HALF;
3099                 if (mask & ADVERTISED_1000baseT_Full)
3100                         all_mask |= ADVERTISE_1000FULL;
3101
3102                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3103                         return 0;
3104
3105                 if ((tg3_ctrl & all_mask) != all_mask)
3106                         return 0;
3107         }
3108         return 1;
3109 }
3110
3111 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3112 {
3113         u32 curadv, reqadv;
3114
3115         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3116                 return 1;
3117
3118         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3119         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3120
3121         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3122                 if (curadv != reqadv)
3123                         return 0;
3124
3125                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3126                         tg3_readphy(tp, MII_LPA, rmtadv);
3127         } else {
3128                 /* Reprogram the advertisement register, even if it
3129                  * does not affect the current link.  If the link
3130                  * gets renegotiated in the future, we can save an
3131                  * additional renegotiation cycle by advertising
3132                  * it correctly in the first place.
3133                  */
3134                 if (curadv != reqadv) {
3135                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3136                                      ADVERTISE_PAUSE_ASYM);
3137                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3138                 }
3139         }
3140
3141         return 1;
3142 }
3143
3144 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3145 {
3146         int current_link_up;
3147         u32 bmsr, val;
3148         u32 lcl_adv, rmt_adv;
3149         u16 current_speed;
3150         u8 current_duplex;
3151         int i, err;
3152
3153         tw32(MAC_EVENT, 0);
3154
3155         tw32_f(MAC_STATUS,
3156              (MAC_STATUS_SYNC_CHANGED |
3157               MAC_STATUS_CFG_CHANGED |
3158               MAC_STATUS_MI_COMPLETION |
3159               MAC_STATUS_LNKSTATE_CHANGED));
3160         udelay(40);
3161
3162         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3163                 tw32_f(MAC_MI_MODE,
3164                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3165                 udelay(80);
3166         }
3167
3168         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3169
3170         /* Some third-party PHYs need to be reset on link going
3171          * down.
3172          */
3173         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3174              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3175              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3176             netif_carrier_ok(tp->dev)) {
3177                 tg3_readphy(tp, MII_BMSR, &bmsr);
3178                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3179                     !(bmsr & BMSR_LSTATUS))
3180                         force_reset = 1;
3181         }
3182         if (force_reset)
3183                 tg3_phy_reset(tp);
3184
3185         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3186                 tg3_readphy(tp, MII_BMSR, &bmsr);
3187                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3188                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3189                         bmsr = 0;
3190
3191                 if (!(bmsr & BMSR_LSTATUS)) {
3192                         err = tg3_init_5401phy_dsp(tp);
3193                         if (err)
3194                                 return err;
3195
3196                         tg3_readphy(tp, MII_BMSR, &bmsr);
3197                         for (i = 0; i < 1000; i++) {
3198                                 udelay(10);
3199                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3200                                     (bmsr & BMSR_LSTATUS)) {
3201                                         udelay(40);
3202                                         break;
3203                                 }
3204                         }
3205
3206                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3207                             TG3_PHY_REV_BCM5401_B0 &&
3208                             !(bmsr & BMSR_LSTATUS) &&
3209                             tp->link_config.active_speed == SPEED_1000) {
3210                                 err = tg3_phy_reset(tp);
3211                                 if (!err)
3212                                         err = tg3_init_5401phy_dsp(tp);
3213                                 if (err)
3214                                         return err;
3215                         }
3216                 }
3217         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3218                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3219                 /* 5701 {A0,B0} CRC bug workaround */
3220                 tg3_writephy(tp, 0x15, 0x0a75);
3221                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3222                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224         }
3225
3226         /* Clear pending interrupts... */
3227         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3228         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3229
3230         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3231                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3232         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3234
3235         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3236             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3237                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3238                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3239                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3240                 else
3241                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3242         }
3243
3244         current_link_up = 0;
3245         current_speed = SPEED_INVALID;
3246         current_duplex = DUPLEX_INVALID;
3247
3248         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3249                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3250                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3251                 if (!(val & (1 << 10))) {
3252                         val |= (1 << 10);
3253                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3254                         goto relink;
3255                 }
3256         }
3257
3258         bmsr = 0;
3259         for (i = 0; i < 100; i++) {
3260                 tg3_readphy(tp, MII_BMSR, &bmsr);
3261                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3262                     (bmsr & BMSR_LSTATUS))
3263                         break;
3264                 udelay(40);
3265         }
3266
3267         if (bmsr & BMSR_LSTATUS) {
3268                 u32 aux_stat, bmcr;
3269
3270                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3271                 for (i = 0; i < 2000; i++) {
3272                         udelay(10);
3273                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3274                             aux_stat)
3275                                 break;
3276                 }
3277
3278                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3279                                              &current_speed,
3280                                              &current_duplex);
3281
3282                 bmcr = 0;
3283                 for (i = 0; i < 200; i++) {
3284                         tg3_readphy(tp, MII_BMCR, &bmcr);
3285                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3286                                 continue;
3287                         if (bmcr && bmcr != 0x7fff)
3288                                 break;
3289                         udelay(10);
3290                 }
3291
3292                 lcl_adv = 0;
3293                 rmt_adv = 0;
3294
3295                 tp->link_config.active_speed = current_speed;
3296                 tp->link_config.active_duplex = current_duplex;
3297
3298                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3299                         if ((bmcr & BMCR_ANENABLE) &&
3300                             tg3_copper_is_advertising_all(tp,
3301                                                 tp->link_config.advertising)) {
3302                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3303                                                                   &rmt_adv))
3304                                         current_link_up = 1;
3305                         }
3306                 } else {
3307                         if (!(bmcr & BMCR_ANENABLE) &&
3308                             tp->link_config.speed == current_speed &&
3309                             tp->link_config.duplex == current_duplex &&
3310                             tp->link_config.flowctrl ==
3311                             tp->link_config.active_flowctrl) {
3312                                 current_link_up = 1;
3313                         }
3314                 }
3315
3316                 if (current_link_up == 1 &&
3317                     tp->link_config.active_duplex == DUPLEX_FULL)
3318                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3319         }
3320
3321 relink:
3322         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3323                 tg3_phy_copper_begin(tp);
3324
3325                 tg3_readphy(tp, MII_BMSR, &bmsr);
3326                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3327                     (bmsr & BMSR_LSTATUS))
3328                         current_link_up = 1;
3329         }
3330
3331         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3332         if (current_link_up == 1) {
3333                 if (tp->link_config.active_speed == SPEED_100 ||
3334                     tp->link_config.active_speed == SPEED_10)
3335                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3336                 else
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3338         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3339                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3340         else
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3342
3343         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3344         if (tp->link_config.active_duplex == DUPLEX_HALF)
3345                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3346
3347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3348                 if (current_link_up == 1 &&
3349                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3350                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3351                 else
3352                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3353         }
3354
3355         /* ??? Without this setting Netgear GA302T PHY does not
3356          * ??? send/receive packets...
3357          */
3358         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3359             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3360                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3361                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3362                 udelay(80);
3363         }
3364
3365         tw32_f(MAC_MODE, tp->mac_mode);
3366         udelay(40);
3367
3368         tg3_phy_eee_adjust(tp, current_link_up);
3369
3370         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3371                 /* Polled via timer. */
3372                 tw32_f(MAC_EVENT, 0);
3373         } else {
3374                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3375         }
3376         udelay(40);
3377
3378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3379             current_link_up == 1 &&
3380             tp->link_config.active_speed == SPEED_1000 &&
3381             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3382              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3383                 udelay(120);
3384                 tw32_f(MAC_STATUS,
3385                      (MAC_STATUS_SYNC_CHANGED |
3386                       MAC_STATUS_CFG_CHANGED));
3387                 udelay(40);
3388                 tg3_write_mem(tp,
3389                               NIC_SRAM_FIRMWARE_MBOX,
3390                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3391         }
3392
3393         /* Prevent send BD corruption. */
3394         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3395                 u16 oldlnkctl, newlnkctl;
3396
3397                 pci_read_config_word(tp->pdev,
3398                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3399                                      &oldlnkctl);
3400                 if (tp->link_config.active_speed == SPEED_100 ||
3401                     tp->link_config.active_speed == SPEED_10)
3402                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3403                 else
3404                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 if (newlnkctl != oldlnkctl)
3406                         pci_write_config_word(tp->pdev,
3407                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3408                                               newlnkctl);
3409         }
3410
3411         if (current_link_up != netif_carrier_ok(tp->dev)) {
3412                 if (current_link_up)
3413                         netif_carrier_on(tp->dev);
3414                 else
3415                         netif_carrier_off(tp->dev);
3416                 tg3_link_report(tp);
3417         }
3418
3419         return 0;
3420 }
3421
3422 struct tg3_fiber_aneginfo {
3423         int state;
3424 #define ANEG_STATE_UNKNOWN              0
3425 #define ANEG_STATE_AN_ENABLE            1
3426 #define ANEG_STATE_RESTART_INIT         2
3427 #define ANEG_STATE_RESTART              3
3428 #define ANEG_STATE_DISABLE_LINK_OK      4
3429 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3430 #define ANEG_STATE_ABILITY_DETECT       6
3431 #define ANEG_STATE_ACK_DETECT_INIT      7
3432 #define ANEG_STATE_ACK_DETECT           8
3433 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3434 #define ANEG_STATE_COMPLETE_ACK         10
3435 #define ANEG_STATE_IDLE_DETECT_INIT     11
3436 #define ANEG_STATE_IDLE_DETECT          12
3437 #define ANEG_STATE_LINK_OK              13
3438 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3439 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3440
3441         u32 flags;
3442 #define MR_AN_ENABLE            0x00000001
3443 #define MR_RESTART_AN           0x00000002
3444 #define MR_AN_COMPLETE          0x00000004
3445 #define MR_PAGE_RX              0x00000008
3446 #define MR_NP_LOADED            0x00000010
3447 #define MR_TOGGLE_TX            0x00000020
3448 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3449 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3450 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3451 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3452 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3453 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3454 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3455 #define MR_TOGGLE_RX            0x00002000
3456 #define MR_NP_RX                0x00004000
3457
3458 #define MR_LINK_OK              0x80000000
3459
3460         unsigned long link_time, cur_time;
3461
3462         u32 ability_match_cfg;
3463         int ability_match_count;
3464
3465         char ability_match, idle_match, ack_match;
3466
3467         u32 txconfig, rxconfig;
3468 #define ANEG_CFG_NP             0x00000080
3469 #define ANEG_CFG_ACK            0x00000040
3470 #define ANEG_CFG_RF2            0x00000020
3471 #define ANEG_CFG_RF1            0x00000010
3472 #define ANEG_CFG_PS2            0x00000001
3473 #define ANEG_CFG_PS1            0x00008000
3474 #define ANEG_CFG_HD             0x00004000
3475 #define ANEG_CFG_FD             0x00002000
3476 #define ANEG_CFG_INVAL          0x00001f06
3477
3478 };
3479 #define ANEG_OK         0
3480 #define ANEG_DONE       1
3481 #define ANEG_TIMER_ENAB 2
3482 #define ANEG_FAILED     -1
3483
3484 #define ANEG_STATE_SETTLE_TIME  10000
3485
3486 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3487                                    struct tg3_fiber_aneginfo *ap)
3488 {
3489         u16 flowctrl;
3490         unsigned long delta;
3491         u32 rx_cfg_reg;
3492         int ret;
3493
3494         if (ap->state == ANEG_STATE_UNKNOWN) {
3495                 ap->rxconfig = 0;
3496                 ap->link_time = 0;
3497                 ap->cur_time = 0;
3498                 ap->ability_match_cfg = 0;
3499                 ap->ability_match_count = 0;
3500                 ap->ability_match = 0;
3501                 ap->idle_match = 0;
3502                 ap->ack_match = 0;
3503         }
3504         ap->cur_time++;
3505
3506         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3507                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3508
3509                 if (rx_cfg_reg != ap->ability_match_cfg) {
3510                         ap->ability_match_cfg = rx_cfg_reg;
3511                         ap->ability_match = 0;
3512                         ap->ability_match_count = 0;
3513                 } else {
3514                         if (++ap->ability_match_count > 1) {
3515                                 ap->ability_match = 1;
3516                                 ap->ability_match_cfg = rx_cfg_reg;
3517                         }
3518                 }
3519                 if (rx_cfg_reg & ANEG_CFG_ACK)
3520                         ap->ack_match = 1;
3521                 else
3522                         ap->ack_match = 0;
3523
3524                 ap->idle_match = 0;
3525         } else {
3526                 ap->idle_match = 1;
3527                 ap->ability_match_cfg = 0;
3528                 ap->ability_match_count = 0;
3529                 ap->ability_match = 0;
3530                 ap->ack_match = 0;
3531
3532                 rx_cfg_reg = 0;
3533         }
3534
3535         ap->rxconfig = rx_cfg_reg;
3536         ret = ANEG_OK;
3537
3538         switch (ap->state) {
3539         case ANEG_STATE_UNKNOWN:
3540                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3541                         ap->state = ANEG_STATE_AN_ENABLE;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_AN_ENABLE:
3545                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3546                 if (ap->flags & MR_AN_ENABLE) {
3547                         ap->link_time = 0;
3548                         ap->cur_time = 0;
3549                         ap->ability_match_cfg = 0;
3550                         ap->ability_match_count = 0;
3551                         ap->ability_match = 0;
3552                         ap->idle_match = 0;
3553                         ap->ack_match = 0;
3554
3555                         ap->state = ANEG_STATE_RESTART_INIT;
3556                 } else {
3557                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3558                 }
3559                 break;
3560
3561         case ANEG_STATE_RESTART_INIT:
3562                 ap->link_time = ap->cur_time;
3563                 ap->flags &= ~(MR_NP_LOADED);
3564                 ap->txconfig = 0;
3565                 tw32(MAC_TX_AUTO_NEG, 0);
3566                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ret = ANEG_TIMER_ENAB;
3571                 ap->state = ANEG_STATE_RESTART;
3572
3573                 /* fallthru */
3574         case ANEG_STATE_RESTART:
3575                 delta = ap->cur_time - ap->link_time;
3576                 if (delta > ANEG_STATE_SETTLE_TIME)
3577                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3578                 else
3579                         ret = ANEG_TIMER_ENAB;
3580                 break;
3581
3582         case ANEG_STATE_DISABLE_LINK_OK:
3583                 ret = ANEG_DONE;
3584                 break;
3585
3586         case ANEG_STATE_ABILITY_DETECT_INIT:
3587                 ap->flags &= ~(MR_TOGGLE_TX);
3588                 ap->txconfig = ANEG_CFG_FD;
3589                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3590                 if (flowctrl & ADVERTISE_1000XPAUSE)
3591                         ap->txconfig |= ANEG_CFG_PS1;
3592                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3593                         ap->txconfig |= ANEG_CFG_PS2;
3594                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3595                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3596                 tw32_f(MAC_MODE, tp->mac_mode);
3597                 udelay(40);
3598
3599                 ap->state = ANEG_STATE_ABILITY_DETECT;
3600                 break;
3601
3602         case ANEG_STATE_ABILITY_DETECT:
3603                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3604                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3605                 break;
3606
3607         case ANEG_STATE_ACK_DETECT_INIT:
3608                 ap->txconfig |= ANEG_CFG_ACK;
3609                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611                 tw32_f(MAC_MODE, tp->mac_mode);
3612                 udelay(40);
3613
3614                 ap->state = ANEG_STATE_ACK_DETECT;
3615
3616                 /* fallthru */
3617         case ANEG_STATE_ACK_DETECT:
3618                 if (ap->ack_match != 0) {
3619                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3620                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3621                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3622                         } else {
3623                                 ap->state = ANEG_STATE_AN_ENABLE;
3624                         }
3625                 } else if (ap->ability_match != 0 &&
3626                            ap->rxconfig == 0) {
3627                         ap->state = ANEG_STATE_AN_ENABLE;
3628                 }
3629                 break;
3630
3631         case ANEG_STATE_COMPLETE_ACK_INIT:
3632                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3633                         ret = ANEG_FAILED;
3634                         break;
3635                 }
3636                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3637                                MR_LP_ADV_HALF_DUPLEX |
3638                                MR_LP_ADV_SYM_PAUSE |
3639                                MR_LP_ADV_ASYM_PAUSE |
3640                                MR_LP_ADV_REMOTE_FAULT1 |
3641                                MR_LP_ADV_REMOTE_FAULT2 |
3642                                MR_LP_ADV_NEXT_PAGE |
3643                                MR_TOGGLE_RX |
3644                                MR_NP_RX);
3645                 if (ap->rxconfig & ANEG_CFG_FD)
3646                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3647                 if (ap->rxconfig & ANEG_CFG_HD)
3648                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_PS1)
3650                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3651                 if (ap->rxconfig & ANEG_CFG_PS2)
3652                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_RF1)
3654                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3655                 if (ap->rxconfig & ANEG_CFG_RF2)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3657                 if (ap->rxconfig & ANEG_CFG_NP)
3658                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3659
3660                 ap->link_time = ap->cur_time;
3661
3662                 ap->flags ^= (MR_TOGGLE_TX);
3663                 if (ap->rxconfig & 0x0008)
3664                         ap->flags |= MR_TOGGLE_RX;
3665                 if (ap->rxconfig & ANEG_CFG_NP)
3666                         ap->flags |= MR_NP_RX;
3667                 ap->flags |= MR_PAGE_RX;
3668
3669                 ap->state = ANEG_STATE_COMPLETE_ACK;
3670                 ret = ANEG_TIMER_ENAB;
3671                 break;
3672
3673         case ANEG_STATE_COMPLETE_ACK:
3674                 if (ap->ability_match != 0 &&
3675                     ap->rxconfig == 0) {
3676                         ap->state = ANEG_STATE_AN_ENABLE;
3677                         break;
3678                 }
3679                 delta = ap->cur_time - ap->link_time;
3680                 if (delta > ANEG_STATE_SETTLE_TIME) {
3681                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3682                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3683                         } else {
3684                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3685                                     !(ap->flags & MR_NP_RX)) {
3686                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3687                                 } else {
3688                                         ret = ANEG_FAILED;
3689                                 }
3690                         }
3691                 }
3692                 break;
3693
3694         case ANEG_STATE_IDLE_DETECT_INIT:
3695                 ap->link_time = ap->cur_time;
3696                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3697                 tw32_f(MAC_MODE, tp->mac_mode);
3698                 udelay(40);
3699
3700                 ap->state = ANEG_STATE_IDLE_DETECT;
3701                 ret = ANEG_TIMER_ENAB;
3702                 break;
3703
3704         case ANEG_STATE_IDLE_DETECT:
3705                 if (ap->ability_match != 0 &&
3706                     ap->rxconfig == 0) {
3707                         ap->state = ANEG_STATE_AN_ENABLE;
3708                         break;
3709                 }
3710                 delta = ap->cur_time - ap->link_time;
3711                 if (delta > ANEG_STATE_SETTLE_TIME) {
3712                         /* XXX another gem from the Broadcom driver :( */
3713                         ap->state = ANEG_STATE_LINK_OK;
3714                 }
3715                 break;
3716
3717         case ANEG_STATE_LINK_OK:
3718                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3719                 ret = ANEG_DONE;
3720                 break;
3721
3722         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3723                 /* ??? unimplemented */
3724                 break;
3725
3726         case ANEG_STATE_NEXT_PAGE_WAIT:
3727                 /* ??? unimplemented */
3728                 break;
3729
3730         default:
3731                 ret = ANEG_FAILED;
3732                 break;
3733         }
3734
3735         return ret;
3736 }
3737
3738 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3739 {
3740         int res = 0;
3741         struct tg3_fiber_aneginfo aninfo;
3742         int status = ANEG_FAILED;
3743         unsigned int tick;
3744         u32 tmp;
3745
3746         tw32_f(MAC_TX_AUTO_NEG, 0);
3747
3748         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3749         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3750         udelay(40);
3751
3752         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3753         udelay(40);
3754
3755         memset(&aninfo, 0, sizeof(aninfo));
3756         aninfo.flags |= MR_AN_ENABLE;
3757         aninfo.state = ANEG_STATE_UNKNOWN;
3758         aninfo.cur_time = 0;
3759         tick = 0;
3760         while (++tick < 195000) {
3761                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3762                 if (status == ANEG_DONE || status == ANEG_FAILED)
3763                         break;
3764
3765                 udelay(1);
3766         }
3767
3768         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3769         tw32_f(MAC_MODE, tp->mac_mode);
3770         udelay(40);
3771
3772         *txflags = aninfo.txconfig;
3773         *rxflags = aninfo.flags;
3774
3775         if (status == ANEG_DONE &&
3776             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3777                              MR_LP_ADV_FULL_DUPLEX)))
3778                 res = 1;
3779
3780         return res;
3781 }
3782
3783 static void tg3_init_bcm8002(struct tg3 *tp)
3784 {
3785         u32 mac_status = tr32(MAC_STATUS);
3786         int i;
3787
3788         /* Reset when initting first time or we have a link. */
3789         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3790             !(mac_status & MAC_STATUS_PCS_SYNCED))
3791                 return;
3792
3793         /* Set PLL lock range. */
3794         tg3_writephy(tp, 0x16, 0x8007);
3795
3796         /* SW reset */
3797         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3798
3799         /* Wait for reset to complete. */
3800         /* XXX schedule_timeout() ... */
3801         for (i = 0; i < 500; i++)
3802                 udelay(10);
3803
3804         /* Config mode; select PMA/Ch 1 regs. */
3805         tg3_writephy(tp, 0x10, 0x8411);
3806
3807         /* Enable auto-lock and comdet, select txclk for tx. */
3808         tg3_writephy(tp, 0x11, 0x0a10);
3809
3810         tg3_writephy(tp, 0x18, 0x00a0);
3811         tg3_writephy(tp, 0x16, 0x41ff);
3812
3813         /* Assert and deassert POR. */
3814         tg3_writephy(tp, 0x13, 0x0400);
3815         udelay(40);
3816         tg3_writephy(tp, 0x13, 0x0000);
3817
3818         tg3_writephy(tp, 0x11, 0x0a50);
3819         udelay(40);
3820         tg3_writephy(tp, 0x11, 0x0a10);
3821
3822         /* Wait for signal to stabilize */
3823         /* XXX schedule_timeout() ... */
3824         for (i = 0; i < 15000; i++)
3825                 udelay(10);
3826
3827         /* Deselect the channel register so we can read the PHYID
3828          * later.
3829          */
3830         tg3_writephy(tp, 0x10, 0x8011);
3831 }
3832
3833 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3834 {
3835         u16 flowctrl;
3836         u32 sg_dig_ctrl, sg_dig_status;
3837         u32 serdes_cfg, expected_sg_dig_ctrl;
3838         int workaround, port_a;
3839         int current_link_up;
3840
3841         serdes_cfg = 0;
3842         expected_sg_dig_ctrl = 0;
3843         workaround = 0;
3844         port_a = 1;
3845         current_link_up = 0;
3846
3847         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3848             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3849                 workaround = 1;
3850                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3851                         port_a = 0;
3852
3853                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3854                 /* preserve bits 20-23 for voltage regulator */
3855                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3856         }
3857
3858         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3859
3860         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3861                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3862                         if (workaround) {
3863                                 u32 val = serdes_cfg;
3864
3865                                 if (port_a)
3866                                         val |= 0xc010000;
3867                                 else
3868                                         val |= 0x4010000;
3869                                 tw32_f(MAC_SERDES_CFG, val);
3870                         }
3871
3872                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3873                 }
3874                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3875                         tg3_setup_flow_control(tp, 0, 0);
3876                         current_link_up = 1;
3877                 }
3878                 goto out;
3879         }
3880
3881         /* Want auto-negotiation.  */
3882         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3883
3884         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3885         if (flowctrl & ADVERTISE_1000XPAUSE)
3886                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3887         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3888                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3889
3890         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3891                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3892                     tp->serdes_counter &&
3893                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3894                                     MAC_STATUS_RCVD_CFG)) ==
3895                      MAC_STATUS_PCS_SYNCED)) {
3896                         tp->serdes_counter--;
3897                         current_link_up = 1;
3898                         goto out;
3899                 }
3900 restart_autoneg:
3901                 if (workaround)
3902                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3903                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3904                 udelay(5);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3906
3907                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3908                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3909         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3910                                  MAC_STATUS_SIGNAL_DET)) {
3911                 sg_dig_status = tr32(SG_DIG_STATUS);
3912                 mac_status = tr32(MAC_STATUS);
3913
3914                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3915                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3916                         u32 local_adv = 0, remote_adv = 0;
3917
3918                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3919                                 local_adv |= ADVERTISE_1000XPAUSE;
3920                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3921                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3922
3923                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3924                                 remote_adv |= LPA_1000XPAUSE;
3925                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3926                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3927
3928                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3929                         current_link_up = 1;
3930                         tp->serdes_counter = 0;
3931                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3932                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3933                         if (tp->serdes_counter)
3934                                 tp->serdes_counter--;
3935                         else {
3936                                 if (workaround) {
3937                                         u32 val = serdes_cfg;
3938
3939                                         if (port_a)
3940                                                 val |= 0xc010000;
3941                                         else
3942                                                 val |= 0x4010000;
3943
3944                                         tw32_f(MAC_SERDES_CFG, val);
3945                                 }
3946
3947                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3948                                 udelay(40);
3949
3950                                 /* Link parallel detection - link is up */
3951                                 /* only if we have PCS_SYNC and not */
3952                                 /* receiving config code words */
3953                                 mac_status = tr32(MAC_STATUS);
3954                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3955                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3956                                         tg3_setup_flow_control(tp, 0, 0);
3957                                         current_link_up = 1;
3958                                         tp->phy_flags |=
3959                                                 TG3_PHYFLG_PARALLEL_DETECT;
3960                                         tp->serdes_counter =
3961                                                 SERDES_PARALLEL_DET_TIMEOUT;
3962                                 } else
3963                                         goto restart_autoneg;
3964                         }
3965                 }
3966         } else {
3967                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3968                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3969         }
3970
3971 out:
3972         return current_link_up;
3973 }
3974
3975 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3976 {
3977         int current_link_up = 0;
3978
3979         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3980                 goto out;
3981
3982         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3983                 u32 txflags, rxflags;
3984                 int i;
3985
3986                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3987                         u32 local_adv = 0, remote_adv = 0;
3988
3989                         if (txflags & ANEG_CFG_PS1)
3990                                 local_adv |= ADVERTISE_1000XPAUSE;
3991                         if (txflags & ANEG_CFG_PS2)
3992                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3993
3994                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3995                                 remote_adv |= LPA_1000XPAUSE;
3996                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3998
3999                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4000
4001                         current_link_up = 1;
4002                 }
4003                 for (i = 0; i < 30; i++) {
4004                         udelay(20);
4005                         tw32_f(MAC_STATUS,
4006                                (MAC_STATUS_SYNC_CHANGED |
4007                                 MAC_STATUS_CFG_CHANGED));
4008                         udelay(40);
4009                         if ((tr32(MAC_STATUS) &
4010                              (MAC_STATUS_SYNC_CHANGED |
4011                               MAC_STATUS_CFG_CHANGED)) == 0)
4012                                 break;
4013                 }
4014
4015                 mac_status = tr32(MAC_STATUS);
4016                 if (current_link_up == 0 &&
4017                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4018                     !(mac_status & MAC_STATUS_RCVD_CFG))
4019                         current_link_up = 1;
4020         } else {
4021                 tg3_setup_flow_control(tp, 0, 0);
4022
4023                 /* Forcing 1000FD link up. */
4024                 current_link_up = 1;
4025
4026                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4027                 udelay(40);
4028
4029                 tw32_f(MAC_MODE, tp->mac_mode);
4030                 udelay(40);
4031         }
4032
4033 out:
4034         return current_link_up;
4035 }
4036
4037 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4038 {
4039         u32 orig_pause_cfg;
4040         u16 orig_active_speed;
4041         u8 orig_active_duplex;
4042         u32 mac_status;
4043         int current_link_up;
4044         int i;
4045
4046         orig_pause_cfg = tp->link_config.active_flowctrl;
4047         orig_active_speed = tp->link_config.active_speed;
4048         orig_active_duplex = tp->link_config.active_duplex;
4049
4050         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4051             netif_carrier_ok(tp->dev) &&
4052             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4053                 mac_status = tr32(MAC_STATUS);
4054                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4055                                MAC_STATUS_SIGNAL_DET |
4056                                MAC_STATUS_CFG_CHANGED |
4057                                MAC_STATUS_RCVD_CFG);
4058                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4059                                    MAC_STATUS_SIGNAL_DET)) {
4060                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4061                                             MAC_STATUS_CFG_CHANGED));
4062                         return 0;
4063                 }
4064         }
4065
4066         tw32_f(MAC_TX_AUTO_NEG, 0);
4067
4068         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4069         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4070         tw32_f(MAC_MODE, tp->mac_mode);
4071         udelay(40);
4072
4073         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4074                 tg3_init_bcm8002(tp);
4075
4076         /* Enable link change event even when serdes polling.  */
4077         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4078         udelay(40);
4079
4080         current_link_up = 0;
4081         mac_status = tr32(MAC_STATUS);
4082
4083         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4084                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4085         else
4086                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4087
4088         tp->napi[0].hw_status->status =
4089                 (SD_STATUS_UPDATED |
4090                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4091
4092         for (i = 0; i < 100; i++) {
4093                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4094                                     MAC_STATUS_CFG_CHANGED));
4095                 udelay(5);
4096                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4097                                          MAC_STATUS_CFG_CHANGED |
4098                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4099                         break;
4100         }
4101
4102         mac_status = tr32(MAC_STATUS);
4103         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4104                 current_link_up = 0;
4105                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4106                     tp->serdes_counter == 0) {
4107                         tw32_f(MAC_MODE, (tp->mac_mode |
4108                                           MAC_MODE_SEND_CONFIGS));
4109                         udelay(1);
4110                         tw32_f(MAC_MODE, tp->mac_mode);
4111                 }
4112         }
4113
4114         if (current_link_up == 1) {
4115                 tp->link_config.active_speed = SPEED_1000;
4116                 tp->link_config.active_duplex = DUPLEX_FULL;
4117                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4118                                     LED_CTRL_LNKLED_OVERRIDE |
4119                                     LED_CTRL_1000MBPS_ON));
4120         } else {
4121                 tp->link_config.active_speed = SPEED_INVALID;
4122                 tp->link_config.active_duplex = DUPLEX_INVALID;
4123                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4124                                     LED_CTRL_LNKLED_OVERRIDE |
4125                                     LED_CTRL_TRAFFIC_OVERRIDE));
4126         }
4127
4128         if (current_link_up != netif_carrier_ok(tp->dev)) {
4129                 if (current_link_up)
4130                         netif_carrier_on(tp->dev);
4131                 else
4132                         netif_carrier_off(tp->dev);
4133                 tg3_link_report(tp);
4134         } else {
4135                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4136                 if (orig_pause_cfg != now_pause_cfg ||
4137                     orig_active_speed != tp->link_config.active_speed ||
4138                     orig_active_duplex != tp->link_config.active_duplex)
4139                         tg3_link_report(tp);
4140         }
4141
4142         return 0;
4143 }
4144
4145 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4146 {
4147         int current_link_up, err = 0;
4148         u32 bmsr, bmcr;
4149         u16 current_speed;
4150         u8 current_duplex;
4151         u32 local_adv, remote_adv;
4152
4153         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4154         tw32_f(MAC_MODE, tp->mac_mode);
4155         udelay(40);
4156
4157         tw32(MAC_EVENT, 0);
4158
4159         tw32_f(MAC_STATUS,
4160              (MAC_STATUS_SYNC_CHANGED |
4161               MAC_STATUS_CFG_CHANGED |
4162               MAC_STATUS_MI_COMPLETION |
4163               MAC_STATUS_LNKSTATE_CHANGED));
4164         udelay(40);
4165
4166         if (force_reset)
4167                 tg3_phy_reset(tp);
4168
4169         current_link_up = 0;
4170         current_speed = SPEED_INVALID;
4171         current_duplex = DUPLEX_INVALID;
4172
4173         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4176                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4177                         bmsr |= BMSR_LSTATUS;
4178                 else
4179                         bmsr &= ~BMSR_LSTATUS;
4180         }
4181
4182         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4183
4184         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4185             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4186                 /* do nothing, just check for link up at the end */
4187         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4188                 u32 adv, new_adv;
4189
4190                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4191                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4192                                   ADVERTISE_1000XPAUSE |
4193                                   ADVERTISE_1000XPSE_ASYM |
4194                                   ADVERTISE_SLCT);
4195
4196                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4197
4198                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4199                         new_adv |= ADVERTISE_1000XHALF;
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4201                         new_adv |= ADVERTISE_1000XFULL;
4202
4203                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4204                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4205                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4206                         tg3_writephy(tp, MII_BMCR, bmcr);
4207
4208                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4209                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4210                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4211
4212                         return err;
4213                 }
4214         } else {
4215                 u32 new_bmcr;
4216
4217                 bmcr &= ~BMCR_SPEED1000;
4218                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4219
4220                 if (tp->link_config.duplex == DUPLEX_FULL)
4221                         new_bmcr |= BMCR_FULLDPLX;
4222
4223                 if (new_bmcr != bmcr) {
4224                         /* BMCR_SPEED1000 is a reserved bit that needs
4225                          * to be set on write.
4226                          */
4227                         new_bmcr |= BMCR_SPEED1000;
4228
4229                         /* Force a linkdown */
4230                         if (netif_carrier_ok(tp->dev)) {
4231                                 u32 adv;
4232
4233                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4234                                 adv &= ~(ADVERTISE_1000XFULL |
4235                                          ADVERTISE_1000XHALF |
4236                                          ADVERTISE_SLCT);
4237                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4238                                 tg3_writephy(tp, MII_BMCR, bmcr |
4239                                                            BMCR_ANRESTART |
4240                                                            BMCR_ANENABLE);
4241                                 udelay(10);
4242                                 netif_carrier_off(tp->dev);
4243                         }
4244                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4245                         bmcr = new_bmcr;
4246                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4247                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4248                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4249                             ASIC_REV_5714) {
4250                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4251                                         bmsr |= BMSR_LSTATUS;
4252                                 else
4253                                         bmsr &= ~BMSR_LSTATUS;
4254                         }
4255                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4256                 }
4257         }
4258
4259         if (bmsr & BMSR_LSTATUS) {
4260                 current_speed = SPEED_1000;
4261                 current_link_up = 1;
4262                 if (bmcr & BMCR_FULLDPLX)
4263                         current_duplex = DUPLEX_FULL;
4264                 else
4265                         current_duplex = DUPLEX_HALF;
4266
4267                 local_adv = 0;
4268                 remote_adv = 0;
4269
4270                 if (bmcr & BMCR_ANENABLE) {
4271                         u32 common;
4272
4273                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4274                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4275                         common = local_adv & remote_adv;
4276                         if (common & (ADVERTISE_1000XHALF |
4277                                       ADVERTISE_1000XFULL)) {
4278                                 if (common & ADVERTISE_1000XFULL)
4279                                         current_duplex = DUPLEX_FULL;
4280                                 else
4281                                         current_duplex = DUPLEX_HALF;
4282                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4283                                 /* Link is up via parallel detect */
4284                         } else {
4285                                 current_link_up = 0;
4286                         }
4287                 }
4288         }
4289
4290         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4291                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4292
4293         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4294         if (tp->link_config.active_duplex == DUPLEX_HALF)
4295                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4296
4297         tw32_f(MAC_MODE, tp->mac_mode);
4298         udelay(40);
4299
4300         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4301
4302         tp->link_config.active_speed = current_speed;
4303         tp->link_config.active_duplex = current_duplex;
4304
4305         if (current_link_up != netif_carrier_ok(tp->dev)) {
4306                 if (current_link_up)
4307                         netif_carrier_on(tp->dev);
4308                 else {
4309                         netif_carrier_off(tp->dev);
4310                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4311                 }
4312                 tg3_link_report(tp);
4313         }
4314         return err;
4315 }
4316
4317 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4318 {
4319         if (tp->serdes_counter) {
4320                 /* Give autoneg time to complete. */
4321                 tp->serdes_counter--;
4322                 return;
4323         }
4324
4325         if (!netif_carrier_ok(tp->dev) &&
4326             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4327                 u32 bmcr;
4328
4329                 tg3_readphy(tp, MII_BMCR, &bmcr);
4330                 if (bmcr & BMCR_ANENABLE) {
4331                         u32 phy1, phy2;
4332
4333                         /* Select shadow register 0x1f */
4334                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4335                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4336
4337                         /* Select expansion interrupt status register */
4338                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4339                                          MII_TG3_DSP_EXP1_INT_STAT);
4340                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4341                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4342
4343                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4344                                 /* We have signal detect and not receiving
4345                                  * config code words, link is up by parallel
4346                                  * detection.
4347                                  */
4348
4349                                 bmcr &= ~BMCR_ANENABLE;
4350                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4351                                 tg3_writephy(tp, MII_BMCR, bmcr);
4352                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4353                         }
4354                 }
4355         } else if (netif_carrier_ok(tp->dev) &&
4356                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4357                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4358                 u32 phy2;
4359
4360                 /* Select expansion interrupt status register */
4361                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4362                                  MII_TG3_DSP_EXP1_INT_STAT);
4363                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4364                 if (phy2 & 0x20) {
4365                         u32 bmcr;
4366
4367                         /* Config code words received, turn on autoneg. */
4368                         tg3_readphy(tp, MII_BMCR, &bmcr);
4369                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4370
4371                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4372
4373                 }
4374         }
4375 }
4376
4377 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4378 {
4379         int err;
4380
4381         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4382                 err = tg3_setup_fiber_phy(tp, force_reset);
4383         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4384                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4385         else
4386                 err = tg3_setup_copper_phy(tp, force_reset);
4387
4388         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4389                 u32 val, scale;
4390
4391                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4392                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4393                         scale = 65;
4394                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4395                         scale = 6;
4396                 else
4397                         scale = 12;
4398
4399                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4400                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4401                 tw32(GRC_MISC_CFG, val);
4402         }
4403
4404         if (tp->link_config.active_speed == SPEED_1000 &&
4405             tp->link_config.active_duplex == DUPLEX_HALF)
4406                 tw32(MAC_TX_LENGTHS,
4407                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4408                       (6 << TX_LENGTHS_IPG_SHIFT) |
4409                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4410         else
4411                 tw32(MAC_TX_LENGTHS,
4412                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4413                       (6 << TX_LENGTHS_IPG_SHIFT) |
4414                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4415
4416         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4417                 if (netif_carrier_ok(tp->dev)) {
4418                         tw32(HOSTCC_STAT_COAL_TICKS,
4419                              tp->coal.stats_block_coalesce_usecs);
4420                 } else {
4421                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4422                 }
4423         }
4424
4425         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4426                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4427                 if (!netif_carrier_ok(tp->dev))
4428                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4429                               tp->pwrmgmt_thresh;
4430                 else
4431                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4432                 tw32(PCIE_PWR_MGMT_THRESH, val);
4433         }
4434
4435         return err;
4436 }
4437
4438 static inline int tg3_irq_sync(struct tg3 *tp)
4439 {
4440         return tp->irq_sync;
4441 }
4442
4443 /* This is called whenever we suspect that the system chipset is re-
4444  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4445  * is bogus tx completions. We try to recover by setting the
4446  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4447  * in the workqueue.
4448  */
4449 static void tg3_tx_recover(struct tg3 *tp)
4450 {
4451         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4452                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4453
4454         netdev_warn(tp->dev,
4455                     "The system may be re-ordering memory-mapped I/O "
4456                     "cycles to the network device, attempting to recover. "
4457                     "Please report the problem to the driver maintainer "
4458                     "and include system chipset information.\n");
4459
4460         spin_lock(&tp->lock);
4461         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4462         spin_unlock(&tp->lock);
4463 }
4464
4465 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4466 {
4467         /* Tell compiler to fetch tx indices from memory. */
4468         barrier();
4469         return tnapi->tx_pending -
4470                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4471 }
4472
4473 /* Tigon3 never reports partial packet sends.  So we do not
4474  * need special logic to handle SKBs that have not had all
4475  * of their frags sent yet, like SunGEM does.
4476  */
4477 static void tg3_tx(struct tg3_napi *tnapi)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4481         u32 sw_idx = tnapi->tx_cons;
4482         struct netdev_queue *txq;
4483         int index = tnapi - tp->napi;
4484
4485         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4486                 index--;
4487
4488         txq = netdev_get_tx_queue(tp->dev, index);
4489
4490         while (sw_idx != hw_idx) {
4491                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4492                 struct sk_buff *skb = ri->skb;
4493                 int i, tx_bug = 0;
4494
4495                 if (unlikely(skb == NULL)) {
4496                         tg3_tx_recover(tp);
4497                         return;
4498                 }
4499
4500                 pci_unmap_single(tp->pdev,
4501                                  dma_unmap_addr(ri, mapping),
4502                                  skb_headlen(skb),
4503                                  PCI_DMA_TODEVICE);
4504
4505                 ri->skb = NULL;
4506
4507                 sw_idx = NEXT_TX(sw_idx);
4508
4509                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4510                         ri = &tnapi->tx_buffers[sw_idx];
4511                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4512                                 tx_bug = 1;
4513
4514                         pci_unmap_page(tp->pdev,
4515                                        dma_unmap_addr(ri, mapping),
4516                                        skb_shinfo(skb)->frags[i].size,
4517                                        PCI_DMA_TODEVICE);
4518                         sw_idx = NEXT_TX(sw_idx);
4519                 }
4520
4521                 dev_kfree_skb(skb);
4522
4523                 if (unlikely(tx_bug)) {
4524                         tg3_tx_recover(tp);
4525                         return;
4526                 }
4527         }
4528
4529         tnapi->tx_cons = sw_idx;
4530
4531         /* Need to make the tx_cons update visible to tg3_start_xmit()
4532          * before checking for netif_queue_stopped().  Without the
4533          * memory barrier, there is a small possibility that tg3_start_xmit()
4534          * will miss it and cause the queue to be stopped forever.
4535          */
4536         smp_mb();
4537
4538         if (unlikely(netif_tx_queue_stopped(txq) &&
4539                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4540                 __netif_tx_lock(txq, smp_processor_id());
4541                 if (netif_tx_queue_stopped(txq) &&
4542                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4543                         netif_tx_wake_queue(txq);
4544                 __netif_tx_unlock(txq);
4545         }
4546 }
4547
4548 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4549 {
4550         if (!ri->skb)
4551                 return;
4552
4553         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4554                          map_sz, PCI_DMA_FROMDEVICE);
4555         dev_kfree_skb_any(ri->skb);
4556         ri->skb = NULL;
4557 }
4558
4559 /* Returns size of skb allocated or < 0 on error.
4560  *
4561  * We only need to fill in the address because the other members
4562  * of the RX descriptor are invariant, see tg3_init_rings.
4563  *
4564  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4565  * posting buffers we only dirty the first cache line of the RX
4566  * descriptor (containing the address).  Whereas for the RX status
4567  * buffers the cpu only reads the last cacheline of the RX descriptor
4568  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4569  */
4570 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4571                             u32 opaque_key, u32 dest_idx_unmasked)
4572 {
4573         struct tg3_rx_buffer_desc *desc;
4574         struct ring_info *map;
4575         struct sk_buff *skb;
4576         dma_addr_t mapping;
4577         int skb_size, dest_idx;
4578
4579         switch (opaque_key) {
4580         case RXD_OPAQUE_RING_STD:
4581                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4582                 desc = &tpr->rx_std[dest_idx];
4583                 map = &tpr->rx_std_buffers[dest_idx];
4584                 skb_size = tp->rx_pkt_map_sz;
4585                 break;
4586
4587         case RXD_OPAQUE_RING_JUMBO:
4588                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4589                 desc = &tpr->rx_jmb[dest_idx].std;
4590                 map = &tpr->rx_jmb_buffers[dest_idx];
4591                 skb_size = TG3_RX_JMB_MAP_SZ;
4592                 break;
4593
4594         default:
4595                 return -EINVAL;
4596         }
4597
4598         /* Do not overwrite any of the map or rp information
4599          * until we are sure we can commit to a new buffer.
4600          *
4601          * Callers depend upon this behavior and assume that
4602          * we leave everything unchanged if we fail.
4603          */
4604         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4605         if (skb == NULL)
4606                 return -ENOMEM;
4607
4608         skb_reserve(skb, tp->rx_offset);
4609
4610         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4611                                  PCI_DMA_FROMDEVICE);
4612         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4613                 dev_kfree_skb(skb);
4614                 return -EIO;
4615         }
4616
4617         map->skb = skb;
4618         dma_unmap_addr_set(map, mapping, mapping);
4619
4620         desc->addr_hi = ((u64)mapping >> 32);
4621         desc->addr_lo = ((u64)mapping & 0xffffffff);
4622
4623         return skb_size;
4624 }
4625
4626 /* We only need to move over in the address because the other
4627  * members of the RX descriptor are invariant.  See notes above
4628  * tg3_alloc_rx_skb for full details.
4629  */
4630 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4631                            struct tg3_rx_prodring_set *dpr,
4632                            u32 opaque_key, int src_idx,
4633                            u32 dest_idx_unmasked)
4634 {
4635         struct tg3 *tp = tnapi->tp;
4636         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4637         struct ring_info *src_map, *dest_map;
4638         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4639         int dest_idx;
4640
4641         switch (opaque_key) {
4642         case RXD_OPAQUE_RING_STD:
4643                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4644                 dest_desc = &dpr->rx_std[dest_idx];
4645                 dest_map = &dpr->rx_std_buffers[dest_idx];
4646                 src_desc = &spr->rx_std[src_idx];
4647                 src_map = &spr->rx_std_buffers[src_idx];
4648                 break;
4649
4650         case RXD_OPAQUE_RING_JUMBO:
4651                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4652                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4653                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4654                 src_desc = &spr->rx_jmb[src_idx].std;
4655                 src_map = &spr->rx_jmb_buffers[src_idx];
4656                 break;
4657
4658         default:
4659                 return;
4660         }
4661
4662         dest_map->skb = src_map->skb;
4663         dma_unmap_addr_set(dest_map, mapping,
4664                            dma_unmap_addr(src_map, mapping));
4665         dest_desc->addr_hi = src_desc->addr_hi;
4666         dest_desc->addr_lo = src_desc->addr_lo;
4667
4668         /* Ensure that the update to the skb happens after the physical
4669          * addresses have been transferred to the new BD location.
4670          */
4671         smp_wmb();
4672
4673         src_map->skb = NULL;
4674 }
4675
4676 /* The RX ring scheme is composed of multiple rings which post fresh
4677  * buffers to the chip, and one special ring the chip uses to report
4678  * status back to the host.
4679  *
4680  * The special ring reports the status of received packets to the
4681  * host.  The chip does not write into the original descriptor the
4682  * RX buffer was obtained from.  The chip simply takes the original
4683  * descriptor as provided by the host, updates the status and length
4684  * field, then writes this into the next status ring entry.
4685  *
4686  * Each ring the host uses to post buffers to the chip is described
4687  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4688  * it is first placed into the on-chip ram.  When the packet's length
4689  * is known, it walks down the TG3_BDINFO entries to select the ring.
4690  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4691  * which is within the range of the new packet's length is chosen.
4692  *
4693  * The "separate ring for rx status" scheme may sound queer, but it makes
4694  * sense from a cache coherency perspective.  If only the host writes
4695  * to the buffer post rings, and only the chip writes to the rx status
4696  * rings, then cache lines never move beyond shared-modified state.
4697  * If both the host and chip were to write into the same ring, cache line
4698  * eviction could occur since both entities want it in an exclusive state.
4699  */
4700 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4701 {
4702         struct tg3 *tp = tnapi->tp;
4703         u32 work_mask, rx_std_posted = 0;
4704         u32 std_prod_idx, jmb_prod_idx;
4705         u32 sw_idx = tnapi->rx_rcb_ptr;
4706         u16 hw_idx;
4707         int received;
4708         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4709
4710         hw_idx = *(tnapi->rx_rcb_prod_idx);
4711         /*
4712          * We need to order the read of hw_idx and the read of
4713          * the opaque cookie.
4714          */
4715         rmb();
4716         work_mask = 0;
4717         received = 0;
4718         std_prod_idx = tpr->rx_std_prod_idx;
4719         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4720         while (sw_idx != hw_idx && budget > 0) {
4721                 struct ring_info *ri;
4722                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4723                 unsigned int len;
4724                 struct sk_buff *skb;
4725                 dma_addr_t dma_addr;
4726                 u32 opaque_key, desc_idx, *post_ptr;
4727                 bool hw_vlan __maybe_unused = false;
4728                 u16 vtag __maybe_unused = 0;
4729
4730                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4731                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4732                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4733                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4734                         dma_addr = dma_unmap_addr(ri, mapping);
4735                         skb = ri->skb;
4736                         post_ptr = &std_prod_idx;
4737                         rx_std_posted++;
4738                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4739                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4740                         dma_addr = dma_unmap_addr(ri, mapping);
4741                         skb = ri->skb;
4742                         post_ptr = &jmb_prod_idx;
4743                 } else
4744                         goto next_pkt_nopost;
4745
4746                 work_mask |= opaque_key;
4747
4748                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4749                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4750                 drop_it:
4751                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4752                                        desc_idx, *post_ptr);
4753                 drop_it_no_recycle:
4754                         /* Other statistics kept track of by card. */
4755                         tp->rx_dropped++;
4756                         goto next_pkt;
4757                 }
4758
4759                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4760                       ETH_FCS_LEN;
4761
4762                 if (len > TG3_RX_COPY_THRESH(tp)) {
4763                         int skb_size;
4764
4765                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4766                                                     *post_ptr);
4767                         if (skb_size < 0)
4768                                 goto drop_it;
4769
4770                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4771                                          PCI_DMA_FROMDEVICE);
4772
4773                         /* Ensure that the update to the skb happens
4774                          * after the usage of the old DMA mapping.
4775                          */
4776                         smp_wmb();
4777
4778                         ri->skb = NULL;
4779
4780                         skb_put(skb, len);
4781                 } else {
4782                         struct sk_buff *copy_skb;
4783
4784                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4785                                        desc_idx, *post_ptr);
4786
4787                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4788                                                     TG3_RAW_IP_ALIGN);
4789                         if (copy_skb == NULL)
4790                                 goto drop_it_no_recycle;
4791
4792                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4793                         skb_put(copy_skb, len);
4794                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4795                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4796                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797
4798                         /* We'll reuse the original ring buffer. */
4799                         skb = copy_skb;
4800                 }
4801
4802                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4803                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4804                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4805                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4806                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4807                 else
4808                         skb_checksum_none_assert(skb);
4809
4810                 skb->protocol = eth_type_trans(skb, tp->dev);
4811
4812                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4813                     skb->protocol != htons(ETH_P_8021Q)) {
4814                         dev_kfree_skb(skb);
4815                         goto drop_it_no_recycle;
4816                 }
4817
4818                 if (desc->type_flags & RXD_FLAG_VLAN &&
4819                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4820                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4821 #if TG3_VLAN_TAG_USED
4822                         if (tp->vlgrp)
4823                                 hw_vlan = true;
4824                         else
4825 #endif
4826                         {
4827                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4828                                                     __skb_push(skb, VLAN_HLEN);
4829
4830                                 memmove(ve, skb->data + VLAN_HLEN,
4831                                         ETH_ALEN * 2);
4832                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4833                                 ve->h_vlan_TCI = htons(vtag);
4834                         }
4835                 }
4836
4837 #if TG3_VLAN_TAG_USED
4838                 if (hw_vlan)
4839                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4840                 else
4841 #endif
4842                         napi_gro_receive(&tnapi->napi, skb);
4843
4844                 received++;
4845                 budget--;
4846
4847 next_pkt:
4848                 (*post_ptr)++;
4849
4850                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4851                         tpr->rx_std_prod_idx = std_prod_idx &
4852                                                tp->rx_std_ring_mask;
4853                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4854                                      tpr->rx_std_prod_idx);
4855                         work_mask &= ~RXD_OPAQUE_RING_STD;
4856                         rx_std_posted = 0;
4857                 }
4858 next_pkt_nopost:
4859                 sw_idx++;
4860                 sw_idx &= tp->rx_ret_ring_mask;
4861
4862                 /* Refresh hw_idx to see if there is new work */
4863                 if (sw_idx == hw_idx) {
4864                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4865                         rmb();
4866                 }
4867         }
4868
4869         /* ACK the status ring. */
4870         tnapi->rx_rcb_ptr = sw_idx;
4871         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4872
4873         /* Refill RX ring(s). */
4874         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4875                 if (work_mask & RXD_OPAQUE_RING_STD) {
4876                         tpr->rx_std_prod_idx = std_prod_idx &
4877                                                tp->rx_std_ring_mask;
4878                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4879                                      tpr->rx_std_prod_idx);
4880                 }
4881                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4882                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4883                                                tp->rx_jmb_ring_mask;
4884                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4885                                      tpr->rx_jmb_prod_idx);
4886                 }
4887                 mmiowb();
4888         } else if (work_mask) {
4889                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4890                  * updated before the producer indices can be updated.
4891                  */
4892                 smp_wmb();
4893
4894                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4895                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4896
4897                 if (tnapi != &tp->napi[1])
4898                         napi_schedule(&tp->napi[1].napi);
4899         }
4900
4901         return received;
4902 }
4903
4904 static void tg3_poll_link(struct tg3 *tp)
4905 {
4906         /* handle link change and other phy events */
4907         if (!(tp->tg3_flags &
4908               (TG3_FLAG_USE_LINKCHG_REG |
4909                TG3_FLAG_POLL_SERDES))) {
4910                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4911
4912                 if (sblk->status & SD_STATUS_LINK_CHG) {
4913                         sblk->status = SD_STATUS_UPDATED |
4914                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4915                         spin_lock(&tp->lock);
4916                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4917                                 tw32_f(MAC_STATUS,
4918                                      (MAC_STATUS_SYNC_CHANGED |
4919                                       MAC_STATUS_CFG_CHANGED |
4920                                       MAC_STATUS_MI_COMPLETION |
4921                                       MAC_STATUS_LNKSTATE_CHANGED));
4922                                 udelay(40);
4923                         } else
4924                                 tg3_setup_phy(tp, 0);
4925                         spin_unlock(&tp->lock);
4926                 }
4927         }
4928 }
4929
4930 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4931                                 struct tg3_rx_prodring_set *dpr,
4932                                 struct tg3_rx_prodring_set *spr)
4933 {
4934         u32 si, di, cpycnt, src_prod_idx;
4935         int i, err = 0;
4936
4937         while (1) {
4938                 src_prod_idx = spr->rx_std_prod_idx;
4939
4940                 /* Make sure updates to the rx_std_buffers[] entries and the
4941                  * standard producer index are seen in the correct order.
4942                  */
4943                 smp_rmb();
4944
4945                 if (spr->rx_std_cons_idx == src_prod_idx)
4946                         break;
4947
4948                 if (spr->rx_std_cons_idx < src_prod_idx)
4949                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4950                 else
4951                         cpycnt = tp->rx_std_ring_mask + 1 -
4952                                  spr->rx_std_cons_idx;
4953
4954                 cpycnt = min(cpycnt,
4955                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4956
4957                 si = spr->rx_std_cons_idx;
4958                 di = dpr->rx_std_prod_idx;
4959
4960                 for (i = di; i < di + cpycnt; i++) {
4961                         if (dpr->rx_std_buffers[i].skb) {
4962                                 cpycnt = i - di;
4963                                 err = -ENOSPC;
4964                                 break;
4965                         }
4966                 }
4967
4968                 if (!cpycnt)
4969                         break;
4970
4971                 /* Ensure that updates to the rx_std_buffers ring and the
4972                  * shadowed hardware producer ring from tg3_recycle_skb() are
4973                  * ordered correctly WRT the skb check above.
4974                  */
4975                 smp_rmb();
4976
4977                 memcpy(&dpr->rx_std_buffers[di],
4978                        &spr->rx_std_buffers[si],
4979                        cpycnt * sizeof(struct ring_info));
4980
4981                 for (i = 0; i < cpycnt; i++, di++, si++) {
4982                         struct tg3_rx_buffer_desc *sbd, *dbd;
4983                         sbd = &spr->rx_std[si];
4984                         dbd = &dpr->rx_std[di];
4985                         dbd->addr_hi = sbd->addr_hi;
4986                         dbd->addr_lo = sbd->addr_lo;
4987                 }
4988
4989                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4990                                        tp->rx_std_ring_mask;
4991                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993         }
4994
4995         while (1) {
4996                 src_prod_idx = spr->rx_jmb_prod_idx;
4997
4998                 /* Make sure updates to the rx_jmb_buffers[] entries and
4999                  * the jumbo producer index are seen in the correct order.
5000                  */
5001                 smp_rmb();
5002
5003                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5004                         break;
5005
5006                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5007                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5008                 else
5009                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5010                                  spr->rx_jmb_cons_idx;
5011
5012                 cpycnt = min(cpycnt,
5013                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5014
5015                 si = spr->rx_jmb_cons_idx;
5016                 di = dpr->rx_jmb_prod_idx;
5017
5018                 for (i = di; i < di + cpycnt; i++) {
5019                         if (dpr->rx_jmb_buffers[i].skb) {
5020                                 cpycnt = i - di;
5021                                 err = -ENOSPC;
5022                                 break;
5023                         }
5024                 }
5025
5026                 if (!cpycnt)
5027                         break;
5028
5029                 /* Ensure that updates to the rx_jmb_buffers ring and the
5030                  * shadowed hardware producer ring from tg3_recycle_skb() are
5031                  * ordered correctly WRT the skb check above.
5032                  */
5033                 smp_rmb();
5034
5035                 memcpy(&dpr->rx_jmb_buffers[di],
5036                        &spr->rx_jmb_buffers[si],
5037                        cpycnt * sizeof(struct ring_info));
5038
5039                 for (i = 0; i < cpycnt; i++, di++, si++) {
5040                         struct tg3_rx_buffer_desc *sbd, *dbd;
5041                         sbd = &spr->rx_jmb[si].std;
5042                         dbd = &dpr->rx_jmb[di].std;
5043                         dbd->addr_hi = sbd->addr_hi;
5044                         dbd->addr_lo = sbd->addr_lo;
5045                 }
5046
5047                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5048                                        tp->rx_jmb_ring_mask;
5049                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051         }
5052
5053         return err;
5054 }
5055
5056 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5057 {
5058         struct tg3 *tp = tnapi->tp;
5059
5060         /* run TX completion thread */
5061         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5062                 tg3_tx(tnapi);
5063                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5064                         return work_done;
5065         }
5066
5067         /* run RX thread, within the bounds set by NAPI.
5068          * All RX "locking" is done by ensuring outside
5069          * code synchronizes with tg3->napi.poll()
5070          */
5071         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5072                 work_done += tg3_rx(tnapi, budget - work_done);
5073
5074         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5075                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5076                 int i, err = 0;
5077                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5078                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5079
5080                 for (i = 1; i < tp->irq_cnt; i++)
5081                         err |= tg3_rx_prodring_xfer(tp, dpr,
5082                                                     &tp->napi[i].prodring);
5083
5084                 wmb();
5085
5086                 if (std_prod_idx != dpr->rx_std_prod_idx)
5087                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5088                                      dpr->rx_std_prod_idx);
5089
5090                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5091                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5092                                      dpr->rx_jmb_prod_idx);
5093
5094                 mmiowb();
5095
5096                 if (err)
5097                         tw32_f(HOSTCC_MODE, tp->coal_now);
5098         }
5099
5100         return work_done;
5101 }
5102
5103 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5104 {
5105         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5106         struct tg3 *tp = tnapi->tp;
5107         int work_done = 0;
5108         struct tg3_hw_status *sblk = tnapi->hw_status;
5109
5110         while (1) {
5111                 work_done = tg3_poll_work(tnapi, work_done, budget);
5112
5113                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5114                         goto tx_recovery;
5115
5116                 if (unlikely(work_done >= budget))
5117                         break;
5118
5119                 /* tp->last_tag is used in tg3_int_reenable() below
5120                  * to tell the hw how much work has been processed,
5121                  * so we must read it before checking for more work.
5122                  */
5123                 tnapi->last_tag = sblk->status_tag;
5124                 tnapi->last_irq_tag = tnapi->last_tag;
5125                 rmb();
5126
5127                 /* check for RX/TX work to do */
5128                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5129                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5130                         napi_complete(napi);
5131                         /* Reenable interrupts. */
5132                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5133                         mmiowb();
5134                         break;
5135                 }
5136         }
5137
5138         return work_done;
5139
5140 tx_recovery:
5141         /* work_done is guaranteed to be less than budget. */
5142         napi_complete(napi);
5143         schedule_work(&tp->reset_task);
5144         return work_done;
5145 }
5146
5147 static int tg3_poll(struct napi_struct *napi, int budget)
5148 {
5149         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5150         struct tg3 *tp = tnapi->tp;
5151         int work_done = 0;
5152         struct tg3_hw_status *sblk = tnapi->hw_status;
5153
5154         while (1) {
5155                 tg3_poll_link(tp);
5156
5157                 work_done = tg3_poll_work(tnapi, work_done, budget);
5158
5159                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5160                         goto tx_recovery;
5161
5162                 if (unlikely(work_done >= budget))
5163                         break;
5164
5165                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5166                         /* tp->last_tag is used in tg3_int_reenable() below
5167                          * to tell the hw how much work has been processed,
5168                          * so we must read it before checking for more work.
5169                          */
5170                         tnapi->last_tag = sblk->status_tag;
5171                         tnapi->last_irq_tag = tnapi->last_tag;
5172                         rmb();
5173                 } else
5174                         sblk->status &= ~SD_STATUS_UPDATED;
5175
5176                 if (likely(!tg3_has_work(tnapi))) {
5177                         napi_complete(napi);
5178                         tg3_int_reenable(tnapi);
5179                         break;
5180                 }
5181         }
5182
5183         return work_done;
5184
5185 tx_recovery:
5186         /* work_done is guaranteed to be less than budget. */
5187         napi_complete(napi);
5188         schedule_work(&tp->reset_task);
5189         return work_done;
5190 }
5191
5192 static void tg3_napi_disable(struct tg3 *tp)
5193 {
5194         int i;
5195
5196         for (i = tp->irq_cnt - 1; i >= 0; i--)
5197                 napi_disable(&tp->napi[i].napi);
5198 }
5199
5200 static void tg3_napi_enable(struct tg3 *tp)
5201 {
5202         int i;
5203
5204         for (i = 0; i < tp->irq_cnt; i++)
5205                 napi_enable(&tp->napi[i].napi);
5206 }
5207
5208 static void tg3_napi_init(struct tg3 *tp)
5209 {
5210         int i;
5211
5212         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5213         for (i = 1; i < tp->irq_cnt; i++)
5214                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5215 }
5216
5217 static void tg3_napi_fini(struct tg3 *tp)
5218 {
5219         int i;
5220
5221         for (i = 0; i < tp->irq_cnt; i++)
5222                 netif_napi_del(&tp->napi[i].napi);
5223 }
5224
5225 static inline void tg3_netif_stop(struct tg3 *tp)
5226 {
5227         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5228         tg3_napi_disable(tp);
5229         netif_tx_disable(tp->dev);
5230 }
5231
5232 static inline void tg3_netif_start(struct tg3 *tp)
5233 {
5234         /* NOTE: unconditional netif_tx_wake_all_queues is only
5235          * appropriate so long as all callers are assured to
5236          * have free tx slots (such as after tg3_init_hw)
5237          */
5238         netif_tx_wake_all_queues(tp->dev);
5239
5240         tg3_napi_enable(tp);
5241         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5242         tg3_enable_ints(tp);
5243 }
5244
5245 static void tg3_irq_quiesce(struct tg3 *tp)
5246 {
5247         int i;
5248
5249         BUG_ON(tp->irq_sync);
5250
5251         tp->irq_sync = 1;
5252         smp_mb();
5253
5254         for (i = 0; i < tp->irq_cnt; i++)
5255                 synchronize_irq(tp->napi[i].irq_vec);
5256 }
5257
5258 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5259  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5260  * with as well.  Most of the time, this is not necessary except when
5261  * shutting down the device.
5262  */
5263 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5264 {
5265         spin_lock_bh(&tp->lock);
5266         if (irq_sync)
5267                 tg3_irq_quiesce(tp);
5268 }
5269
5270 static inline void tg3_full_unlock(struct tg3 *tp)
5271 {
5272         spin_unlock_bh(&tp->lock);
5273 }
5274
5275 /* One-shot MSI handler - Chip automatically disables interrupt
5276  * after sending MSI so driver doesn't have to do it.
5277  */
5278 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5279 {
5280         struct tg3_napi *tnapi = dev_id;
5281         struct tg3 *tp = tnapi->tp;
5282
5283         prefetch(tnapi->hw_status);
5284         if (tnapi->rx_rcb)
5285                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5286
5287         if (likely(!tg3_irq_sync(tp)))
5288                 napi_schedule(&tnapi->napi);
5289
5290         return IRQ_HANDLED;
5291 }
5292
5293 /* MSI ISR - No need to check for interrupt sharing and no need to
5294  * flush status block and interrupt mailbox. PCI ordering rules
5295  * guarantee that MSI will arrive after the status block.
5296  */
5297 static irqreturn_t tg3_msi(int irq, void *dev_id)
5298 {
5299         struct tg3_napi *tnapi = dev_id;
5300         struct tg3 *tp = tnapi->tp;
5301
5302         prefetch(tnapi->hw_status);
5303         if (tnapi->rx_rcb)
5304                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5305         /*
5306          * Writing any value to intr-mbox-0 clears PCI INTA# and
5307          * chip-internal interrupt pending events.
5308          * Writing non-zero to intr-mbox-0 additional tells the
5309          * NIC to stop sending us irqs, engaging "in-intr-handler"
5310          * event coalescing.
5311          */
5312         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5313         if (likely(!tg3_irq_sync(tp)))
5314                 napi_schedule(&tnapi->napi);
5315
5316         return IRQ_RETVAL(1);
5317 }
5318
5319 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5320 {
5321         struct tg3_napi *tnapi = dev_id;
5322         struct tg3 *tp = tnapi->tp;
5323         struct tg3_hw_status *sblk = tnapi->hw_status;
5324         unsigned int handled = 1;
5325
5326         /* In INTx mode, it is possible for the interrupt to arrive at
5327          * the CPU before the status block posted prior to the interrupt.
5328          * Reading the PCI State register will confirm whether the
5329          * interrupt is ours and will flush the status block.
5330          */
5331         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5332                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5333                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5334                         handled = 0;
5335                         goto out;
5336                 }
5337         }
5338
5339         /*
5340          * Writing any value to intr-mbox-0 clears PCI INTA# and
5341          * chip-internal interrupt pending events.
5342          * Writing non-zero to intr-mbox-0 additional tells the
5343          * NIC to stop sending us irqs, engaging "in-intr-handler"
5344          * event coalescing.
5345          *
5346          * Flush the mailbox to de-assert the IRQ immediately to prevent
5347          * spurious interrupts.  The flush impacts performance but
5348          * excessive spurious interrupts can be worse in some cases.
5349          */
5350         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5351         if (tg3_irq_sync(tp))
5352                 goto out;
5353         sblk->status &= ~SD_STATUS_UPDATED;
5354         if (likely(tg3_has_work(tnapi))) {
5355                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5356                 napi_schedule(&tnapi->napi);
5357         } else {
5358                 /* No work, shared interrupt perhaps?  re-enable
5359                  * interrupts, and flush that PCI write
5360                  */
5361                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5362                                0x00000000);
5363         }
5364 out:
5365         return IRQ_RETVAL(handled);
5366 }
5367
5368 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5369 {
5370         struct tg3_napi *tnapi = dev_id;
5371         struct tg3 *tp = tnapi->tp;
5372         struct tg3_hw_status *sblk = tnapi->hw_status;
5373         unsigned int handled = 1;
5374
5375         /* In INTx mode, it is possible for the interrupt to arrive at
5376          * the CPU before the status block posted prior to the interrupt.
5377          * Reading the PCI State register will confirm whether the
5378          * interrupt is ours and will flush the status block.
5379          */
5380         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5381                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5382                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5383                         handled = 0;
5384                         goto out;
5385                 }
5386         }
5387
5388         /*
5389          * writing any value to intr-mbox-0 clears PCI INTA# and
5390          * chip-internal interrupt pending events.
5391          * writing non-zero to intr-mbox-0 additional tells the
5392          * NIC to stop sending us irqs, engaging "in-intr-handler"
5393          * event coalescing.
5394          *
5395          * Flush the mailbox to de-assert the IRQ immediately to prevent
5396          * spurious interrupts.  The flush impacts performance but
5397          * excessive spurious interrupts can be worse in some cases.
5398          */
5399         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5400
5401         /*
5402          * In a shared interrupt configuration, sometimes other devices'
5403          * interrupts will scream.  We record the current status tag here
5404          * so that the above check can report that the screaming interrupts
5405          * are unhandled.  Eventually they will be silenced.
5406          */
5407         tnapi->last_irq_tag = sblk->status_tag;
5408
5409         if (tg3_irq_sync(tp))
5410                 goto out;
5411
5412         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5413
5414         napi_schedule(&tnapi->napi);
5415
5416 out:
5417         return IRQ_RETVAL(handled);
5418 }
5419
5420 /* ISR for interrupt test */
5421 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5422 {
5423         struct tg3_napi *tnapi = dev_id;
5424         struct tg3 *tp = tnapi->tp;
5425         struct tg3_hw_status *sblk = tnapi->hw_status;
5426
5427         if ((sblk->status & SD_STATUS_UPDATED) ||
5428             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5429                 tg3_disable_ints(tp);
5430                 return IRQ_RETVAL(1);
5431         }
5432         return IRQ_RETVAL(0);
5433 }
5434
5435 static int tg3_init_hw(struct tg3 *, int);
5436 static int tg3_halt(struct tg3 *, int, int);
5437
5438 /* Restart hardware after configuration changes, self-test, etc.
5439  * Invoked with tp->lock held.
5440  */
5441 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5442         __releases(tp->lock)
5443         __acquires(tp->lock)
5444 {
5445         int err;
5446
5447         err = tg3_init_hw(tp, reset_phy);
5448         if (err) {
5449                 netdev_err(tp->dev,
5450                            "Failed to re-initialize device, aborting\n");
5451                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5452                 tg3_full_unlock(tp);
5453                 del_timer_sync(&tp->timer);
5454                 tp->irq_sync = 0;
5455                 tg3_napi_enable(tp);
5456                 dev_close(tp->dev);
5457                 tg3_full_lock(tp, 0);
5458         }
5459         return err;
5460 }
5461
5462 #ifdef CONFIG_NET_POLL_CONTROLLER
5463 static void tg3_poll_controller(struct net_device *dev)
5464 {
5465         int i;
5466         struct tg3 *tp = netdev_priv(dev);
5467
5468         for (i = 0; i < tp->irq_cnt; i++)
5469                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5470 }
5471 #endif
5472
5473 static void tg3_reset_task(struct work_struct *work)
5474 {
5475         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5476         int err;
5477         unsigned int restart_timer;
5478
5479         tg3_full_lock(tp, 0);
5480
5481         if (!netif_running(tp->dev)) {
5482                 tg3_full_unlock(tp);
5483                 return;
5484         }
5485
5486         tg3_full_unlock(tp);
5487
5488         tg3_phy_stop(tp);
5489
5490         tg3_netif_stop(tp);
5491
5492         tg3_full_lock(tp, 1);
5493
5494         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5495         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5496
5497         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5498                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5499                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5500                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5501                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5502         }
5503
5504         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5505         err = tg3_init_hw(tp, 1);
5506         if (err)
5507                 goto out;
5508
5509         tg3_netif_start(tp);
5510
5511         if (restart_timer)
5512                 mod_timer(&tp->timer, jiffies + 1);
5513
5514 out:
5515         tg3_full_unlock(tp);
5516
5517         if (!err)
5518                 tg3_phy_start(tp);
5519 }
5520
5521 static void tg3_dump_short_state(struct tg3 *tp)
5522 {
5523         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5524                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5525         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5526                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5527 }
5528
5529 static void tg3_tx_timeout(struct net_device *dev)
5530 {
5531         struct tg3 *tp = netdev_priv(dev);
5532
5533         if (netif_msg_tx_err(tp)) {
5534                 netdev_err(dev, "transmit timed out, resetting\n");
5535                 tg3_dump_short_state(tp);
5536         }
5537
5538         schedule_work(&tp->reset_task);
5539 }
5540
5541 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5542 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5543 {
5544         u32 base = (u32) mapping & 0xffffffff;
5545
5546         return (base > 0xffffdcc0) && (base + len + 8 < base);
5547 }
5548
5549 /* Test for DMA addresses > 40-bit */
5550 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5551                                           int len)
5552 {
5553 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5554         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5555                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5556         return 0;
5557 #else
5558         return 0;
5559 #endif
5560 }
5561
5562 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5563
5564 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5565 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5566                                        struct sk_buff *skb, u32 last_plus_one,
5567                                        u32 *start, u32 base_flags, u32 mss)
5568 {
5569         struct tg3 *tp = tnapi->tp;
5570         struct sk_buff *new_skb;
5571         dma_addr_t new_addr = 0;
5572         u32 entry = *start;
5573         int i, ret = 0;
5574
5575         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5576                 new_skb = skb_copy(skb, GFP_ATOMIC);
5577         else {
5578                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5579
5580                 new_skb = skb_copy_expand(skb,
5581                                           skb_headroom(skb) + more_headroom,
5582                                           skb_tailroom(skb), GFP_ATOMIC);
5583         }
5584
5585         if (!new_skb) {
5586                 ret = -1;
5587         } else {
5588                 /* New SKB is guaranteed to be linear. */
5589                 entry = *start;
5590                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5591                                           PCI_DMA_TODEVICE);
5592                 /* Make sure the mapping succeeded */
5593                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5594                         ret = -1;
5595                         dev_kfree_skb(new_skb);
5596                         new_skb = NULL;
5597
5598                 /* Make sure new skb does not cross any 4G boundaries.
5599                  * Drop the packet if it does.
5600                  */
5601                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5602                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5603                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5604                                          PCI_DMA_TODEVICE);
5605                         ret = -1;
5606                         dev_kfree_skb(new_skb);
5607                         new_skb = NULL;
5608                 } else {
5609                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5610                                     base_flags, 1 | (mss << 1));
5611                         *start = NEXT_TX(entry);
5612                 }
5613         }
5614
5615         /* Now clean up the sw ring entries. */
5616         i = 0;
5617         while (entry != last_plus_one) {
5618                 int len;
5619
5620                 if (i == 0)
5621                         len = skb_headlen(skb);
5622                 else
5623                         len = skb_shinfo(skb)->frags[i-1].size;
5624
5625                 pci_unmap_single(tp->pdev,
5626                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5627                                                 mapping),
5628                                  len, PCI_DMA_TODEVICE);
5629                 if (i == 0) {
5630                         tnapi->tx_buffers[entry].skb = new_skb;
5631                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5632                                            new_addr);
5633                 } else {
5634                         tnapi->tx_buffers[entry].skb = NULL;
5635                 }
5636                 entry = NEXT_TX(entry);
5637                 i++;
5638         }
5639
5640         dev_kfree_skb(skb);
5641
5642         return ret;
5643 }
5644
5645 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5646                         dma_addr_t mapping, int len, u32 flags,
5647                         u32 mss_and_is_end)
5648 {
5649         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5650         int is_end = (mss_and_is_end & 0x1);
5651         u32 mss = (mss_and_is_end >> 1);
5652         u32 vlan_tag = 0;
5653
5654         if (is_end)
5655                 flags |= TXD_FLAG_END;
5656         if (flags & TXD_FLAG_VLAN) {
5657                 vlan_tag = flags >> 16;
5658                 flags &= 0xffff;
5659         }
5660         vlan_tag |= (mss << TXD_MSS_SHIFT);
5661
5662         txd->addr_hi = ((u64) mapping >> 32);
5663         txd->addr_lo = ((u64) mapping & 0xffffffff);
5664         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5665         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5666 }
5667
5668 /* hard_start_xmit for devices that don't have any bugs and
5669  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5670  */
5671 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5672                                   struct net_device *dev)
5673 {
5674         struct tg3 *tp = netdev_priv(dev);
5675         u32 len, entry, base_flags, mss;
5676         dma_addr_t mapping;
5677         struct tg3_napi *tnapi;
5678         struct netdev_queue *txq;
5679         unsigned int i, last;
5680
5681         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5682         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5683         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5684                 tnapi++;
5685
5686         /* We are running in BH disabled context with netif_tx_lock
5687          * and TX reclaim runs via tp->napi.poll inside of a software
5688          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5689          * no IRQ context deadlocks to worry about either.  Rejoice!
5690          */
5691         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5692                 if (!netif_tx_queue_stopped(txq)) {
5693                         netif_tx_stop_queue(txq);
5694
5695                         /* This is a hard error, log it. */
5696                         netdev_err(dev,
5697                                    "BUG! Tx Ring full when queue awake!\n");
5698                 }
5699                 return NETDEV_TX_BUSY;
5700         }
5701
5702         entry = tnapi->tx_prod;
5703         base_flags = 0;
5704         mss = skb_shinfo(skb)->gso_size;
5705         if (mss) {
5706                 int tcp_opt_len, ip_tcp_len;
5707                 u32 hdrlen;
5708
5709                 if (skb_header_cloned(skb) &&
5710                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5711                         dev_kfree_skb(skb);
5712                         goto out_unlock;
5713                 }
5714
5715                 if (skb_is_gso_v6(skb)) {
5716                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5717                 } else {
5718                         struct iphdr *iph = ip_hdr(skb);
5719
5720                         tcp_opt_len = tcp_optlen(skb);
5721                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5722
5723                         iph->check = 0;
5724                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5725                         hdrlen = ip_tcp_len + tcp_opt_len;
5726                 }
5727
5728                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5729                         mss |= (hdrlen & 0xc) << 12;
5730                         if (hdrlen & 0x10)
5731                                 base_flags |= 0x00000010;
5732                         base_flags |= (hdrlen & 0x3e0) << 5;
5733                 } else
5734                         mss |= hdrlen << 9;
5735
5736                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5737                                TXD_FLAG_CPU_POST_DMA);
5738
5739                 tcp_hdr(skb)->check = 0;
5740
5741         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5742                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5743         }
5744
5745 #if TG3_VLAN_TAG_USED
5746         if (vlan_tx_tag_present(skb))
5747                 base_flags |= (TXD_FLAG_VLAN |
5748                                (vlan_tx_tag_get(skb) << 16));
5749 #endif
5750
5751         len = skb_headlen(skb);
5752
5753         /* Queue skb data, a.k.a. the main skb fragment. */
5754         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5755         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5756                 dev_kfree_skb(skb);
5757                 goto out_unlock;
5758         }
5759
5760         tnapi->tx_buffers[entry].skb = skb;
5761         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5762
5763         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5764             !mss && skb->len > ETH_DATA_LEN)
5765                 base_flags |= TXD_FLAG_JMB_PKT;
5766
5767         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5768                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5769
5770         entry = NEXT_TX(entry);
5771
5772         /* Now loop through additional data fragments, and queue them. */
5773         if (skb_shinfo(skb)->nr_frags > 0) {
5774                 last = skb_shinfo(skb)->nr_frags - 1;
5775                 for (i = 0; i <= last; i++) {
5776                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5777
5778                         len = frag->size;
5779                         mapping = pci_map_page(tp->pdev,
5780                                                frag->page,
5781                                                frag->page_offset,
5782                                                len, PCI_DMA_TODEVICE);
5783                         if (pci_dma_mapping_error(tp->pdev, mapping))
5784                                 goto dma_error;
5785
5786                         tnapi->tx_buffers[entry].skb = NULL;
5787                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5788                                            mapping);
5789
5790                         tg3_set_txd(tnapi, entry, mapping, len,
5791                                     base_flags, (i == last) | (mss << 1));
5792
5793                         entry = NEXT_TX(entry);
5794                 }
5795         }
5796
5797         /* Packets are ready, update Tx producer idx local and on card. */
5798         tw32_tx_mbox(tnapi->prodmbox, entry);
5799
5800         tnapi->tx_prod = entry;
5801         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5802                 netif_tx_stop_queue(txq);
5803
5804                 /* netif_tx_stop_queue() must be done before checking
5805                  * checking tx index in tg3_tx_avail() below, because in
5806                  * tg3_tx(), we update tx index before checking for
5807                  * netif_tx_queue_stopped().
5808                  */
5809                 smp_mb();
5810                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5811                         netif_tx_wake_queue(txq);
5812         }
5813
5814 out_unlock:
5815         mmiowb();
5816
5817         return NETDEV_TX_OK;
5818
5819 dma_error:
5820         last = i;
5821         entry = tnapi->tx_prod;
5822         tnapi->tx_buffers[entry].skb = NULL;
5823         pci_unmap_single(tp->pdev,
5824                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5825                          skb_headlen(skb),
5826                          PCI_DMA_TODEVICE);
5827         for (i = 0; i <= last; i++) {
5828                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5829                 entry = NEXT_TX(entry);
5830
5831                 pci_unmap_page(tp->pdev,
5832                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5833                                               mapping),
5834                                frag->size, PCI_DMA_TODEVICE);
5835         }
5836
5837         dev_kfree_skb(skb);
5838         return NETDEV_TX_OK;
5839 }
5840
5841 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5842                                           struct net_device *);
5843
5844 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5845  * TSO header is greater than 80 bytes.
5846  */
5847 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5848 {
5849         struct sk_buff *segs, *nskb;
5850         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5851
5852         /* Estimate the number of fragments in the worst case */
5853         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5854                 netif_stop_queue(tp->dev);
5855
5856                 /* netif_tx_stop_queue() must be done before checking
5857                  * checking tx index in tg3_tx_avail() below, because in
5858                  * tg3_tx(), we update tx index before checking for
5859                  * netif_tx_queue_stopped().
5860                  */
5861                 smp_mb();
5862                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5863                         return NETDEV_TX_BUSY;
5864
5865                 netif_wake_queue(tp->dev);
5866         }
5867
5868         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5869         if (IS_ERR(segs))
5870                 goto tg3_tso_bug_end;
5871
5872         do {
5873                 nskb = segs;
5874                 segs = segs->next;
5875                 nskb->next = NULL;
5876                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5877         } while (segs);
5878
5879 tg3_tso_bug_end:
5880         dev_kfree_skb(skb);
5881
5882         return NETDEV_TX_OK;
5883 }
5884
5885 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5886  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5887  */
5888 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5889                                           struct net_device *dev)
5890 {
5891         struct tg3 *tp = netdev_priv(dev);
5892         u32 len, entry, base_flags, mss;
5893         int would_hit_hwbug;
5894         dma_addr_t mapping;
5895         struct tg3_napi *tnapi;
5896         struct netdev_queue *txq;
5897         unsigned int i, last;
5898
5899         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5900         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5901         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5902                 tnapi++;
5903
5904         /* We are running in BH disabled context with netif_tx_lock
5905          * and TX reclaim runs via tp->napi.poll inside of a software
5906          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5907          * no IRQ context deadlocks to worry about either.  Rejoice!
5908          */
5909         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5910                 if (!netif_tx_queue_stopped(txq)) {
5911                         netif_tx_stop_queue(txq);
5912
5913                         /* This is a hard error, log it. */
5914                         netdev_err(dev,
5915                                    "BUG! Tx Ring full when queue awake!\n");
5916                 }
5917                 return NETDEV_TX_BUSY;
5918         }
5919
5920         entry = tnapi->tx_prod;
5921         base_flags = 0;
5922         if (skb->ip_summed == CHECKSUM_PARTIAL)
5923                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5924
5925         mss = skb_shinfo(skb)->gso_size;
5926         if (mss) {
5927                 struct iphdr *iph;
5928                 u32 tcp_opt_len, hdr_len;
5929
5930                 if (skb_header_cloned(skb) &&
5931                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5932                         dev_kfree_skb(skb);
5933                         goto out_unlock;
5934                 }
5935
5936                 iph = ip_hdr(skb);
5937                 tcp_opt_len = tcp_optlen(skb);
5938
5939                 if (skb_is_gso_v6(skb)) {
5940                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5941                 } else {
5942                         u32 ip_tcp_len;
5943
5944                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5945                         hdr_len = ip_tcp_len + tcp_opt_len;
5946
5947                         iph->check = 0;
5948                         iph->tot_len = htons(mss + hdr_len);
5949                 }
5950
5951                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5952                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5953                         return tg3_tso_bug(tp, skb);
5954
5955                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5956                                TXD_FLAG_CPU_POST_DMA);
5957
5958                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5959                         tcp_hdr(skb)->check = 0;
5960                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5961                 } else
5962                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5963                                                                  iph->daddr, 0,
5964                                                                  IPPROTO_TCP,
5965                                                                  0);
5966
5967                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5968                         mss |= (hdr_len & 0xc) << 12;
5969                         if (hdr_len & 0x10)
5970                                 base_flags |= 0x00000010;
5971                         base_flags |= (hdr_len & 0x3e0) << 5;
5972                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5973                         mss |= hdr_len << 9;
5974                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5975                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5976                         if (tcp_opt_len || iph->ihl > 5) {
5977                                 int tsflags;
5978
5979                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5980                                 mss |= (tsflags << 11);
5981                         }
5982                 } else {
5983                         if (tcp_opt_len || iph->ihl > 5) {
5984                                 int tsflags;
5985
5986                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5987                                 base_flags |= tsflags << 12;
5988                         }
5989                 }
5990         }
5991 #if TG3_VLAN_TAG_USED
5992         if (vlan_tx_tag_present(skb))
5993                 base_flags |= (TXD_FLAG_VLAN |
5994                                (vlan_tx_tag_get(skb) << 16));
5995 #endif
5996
5997         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5998             !mss && skb->len > ETH_DATA_LEN)
5999                 base_flags |= TXD_FLAG_JMB_PKT;
6000
6001         len = skb_headlen(skb);
6002
6003         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6004         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6005                 dev_kfree_skb(skb);
6006                 goto out_unlock;
6007         }
6008
6009         tnapi->tx_buffers[entry].skb = skb;
6010         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6011
6012         would_hit_hwbug = 0;
6013
6014         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6015                 would_hit_hwbug = 1;
6016
6017         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6018             tg3_4g_overflow_test(mapping, len))
6019                 would_hit_hwbug = 1;
6020
6021         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6022             tg3_40bit_overflow_test(tp, mapping, len))
6023                 would_hit_hwbug = 1;
6024
6025         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6026                 would_hit_hwbug = 1;
6027
6028         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6029                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6030
6031         entry = NEXT_TX(entry);
6032
6033         /* Now loop through additional data fragments, and queue them. */
6034         if (skb_shinfo(skb)->nr_frags > 0) {
6035                 last = skb_shinfo(skb)->nr_frags - 1;
6036                 for (i = 0; i <= last; i++) {
6037                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6038
6039                         len = frag->size;
6040                         mapping = pci_map_page(tp->pdev,
6041                                                frag->page,
6042                                                frag->page_offset,
6043                                                len, PCI_DMA_TODEVICE);
6044
6045                         tnapi->tx_buffers[entry].skb = NULL;
6046                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6047                                            mapping);
6048                         if (pci_dma_mapping_error(tp->pdev, mapping))
6049                                 goto dma_error;
6050
6051                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6052                             len <= 8)
6053                                 would_hit_hwbug = 1;
6054
6055                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6056                             tg3_4g_overflow_test(mapping, len))
6057                                 would_hit_hwbug = 1;
6058
6059                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6060                             tg3_40bit_overflow_test(tp, mapping, len))
6061                                 would_hit_hwbug = 1;
6062
6063                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6064                                 tg3_set_txd(tnapi, entry, mapping, len,
6065                                             base_flags, (i == last)|(mss << 1));
6066                         else
6067                                 tg3_set_txd(tnapi, entry, mapping, len,
6068                                             base_flags, (i == last));
6069
6070                         entry = NEXT_TX(entry);
6071                 }
6072         }
6073
6074         if (would_hit_hwbug) {
6075                 u32 last_plus_one = entry;
6076                 u32 start;
6077
6078                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6079                 start &= (TG3_TX_RING_SIZE - 1);
6080
6081                 /* If the workaround fails due to memory/mapping
6082                  * failure, silently drop this packet.
6083                  */
6084                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6085                                                 &start, base_flags, mss))
6086                         goto out_unlock;
6087
6088                 entry = start;
6089         }
6090
6091         /* Packets are ready, update Tx producer idx local and on card. */
6092         tw32_tx_mbox(tnapi->prodmbox, entry);
6093
6094         tnapi->tx_prod = entry;
6095         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6096                 netif_tx_stop_queue(txq);
6097
6098                 /* netif_tx_stop_queue() must be done before checking
6099                  * checking tx index in tg3_tx_avail() below, because in
6100                  * tg3_tx(), we update tx index before checking for
6101                  * netif_tx_queue_stopped().
6102                  */
6103                 smp_mb();
6104                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6105                         netif_tx_wake_queue(txq);
6106         }
6107
6108 out_unlock:
6109         mmiowb();
6110
6111         return NETDEV_TX_OK;
6112
6113 dma_error:
6114         last = i;
6115         entry = tnapi->tx_prod;
6116         tnapi->tx_buffers[entry].skb = NULL;
6117         pci_unmap_single(tp->pdev,
6118                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6119                          skb_headlen(skb),
6120                          PCI_DMA_TODEVICE);
6121         for (i = 0; i <= last; i++) {
6122                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6123                 entry = NEXT_TX(entry);
6124
6125                 pci_unmap_page(tp->pdev,
6126                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6127                                               mapping),
6128                                frag->size, PCI_DMA_TODEVICE);
6129         }
6130
6131         dev_kfree_skb(skb);
6132         return NETDEV_TX_OK;
6133 }
6134
6135 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6136                                int new_mtu)
6137 {
6138         dev->mtu = new_mtu;
6139
6140         if (new_mtu > ETH_DATA_LEN) {
6141                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6142                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6143                         ethtool_op_set_tso(dev, 0);
6144                 } else {
6145                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6146                 }
6147         } else {
6148                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6149                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6150                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6151         }
6152 }
6153
6154 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6155 {
6156         struct tg3 *tp = netdev_priv(dev);
6157         int err;
6158
6159         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6160                 return -EINVAL;
6161
6162         if (!netif_running(dev)) {
6163                 /* We'll just catch it later when the
6164                  * device is up'd.
6165                  */
6166                 tg3_set_mtu(dev, tp, new_mtu);
6167                 return 0;
6168         }
6169
6170         tg3_phy_stop(tp);
6171
6172         tg3_netif_stop(tp);
6173
6174         tg3_full_lock(tp, 1);
6175
6176         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6177
6178         tg3_set_mtu(dev, tp, new_mtu);
6179
6180         err = tg3_restart_hw(tp, 0);
6181
6182         if (!err)
6183                 tg3_netif_start(tp);
6184
6185         tg3_full_unlock(tp);
6186
6187         if (!err)
6188                 tg3_phy_start(tp);
6189
6190         return err;
6191 }
6192
6193 static void tg3_rx_prodring_free(struct tg3 *tp,
6194                                  struct tg3_rx_prodring_set *tpr)
6195 {
6196         int i;
6197
6198         if (tpr != &tp->napi[0].prodring) {
6199                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6200                      i = (i + 1) & tp->rx_std_ring_mask)
6201                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6202                                         tp->rx_pkt_map_sz);
6203
6204                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6205                         for (i = tpr->rx_jmb_cons_idx;
6206                              i != tpr->rx_jmb_prod_idx;
6207                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6208                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6209                                                 TG3_RX_JMB_MAP_SZ);
6210                         }
6211                 }
6212
6213                 return;
6214         }
6215
6216         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6217                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6218                                 tp->rx_pkt_map_sz);
6219
6220         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6221             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6222                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6223                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6224                                         TG3_RX_JMB_MAP_SZ);
6225         }
6226 }
6227
6228 /* Initialize rx rings for packet processing.
6229  *
6230  * The chip has been shut down and the driver detached from
6231  * the networking, so no interrupts or new tx packets will
6232  * end up in the driver.  tp->{tx,}lock are held and thus
6233  * we may not sleep.
6234  */
6235 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6236                                  struct tg3_rx_prodring_set *tpr)
6237 {
6238         u32 i, rx_pkt_dma_sz;
6239
6240         tpr->rx_std_cons_idx = 0;
6241         tpr->rx_std_prod_idx = 0;
6242         tpr->rx_jmb_cons_idx = 0;
6243         tpr->rx_jmb_prod_idx = 0;
6244
6245         if (tpr != &tp->napi[0].prodring) {
6246                 memset(&tpr->rx_std_buffers[0], 0,
6247                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6248                 if (tpr->rx_jmb_buffers)
6249                         memset(&tpr->rx_jmb_buffers[0], 0,
6250                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6251                 goto done;
6252         }
6253
6254         /* Zero out all descriptors. */
6255         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6256
6257         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6258         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6259             tp->dev->mtu > ETH_DATA_LEN)
6260                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6261         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6262
6263         /* Initialize invariants of the rings, we only set this
6264          * stuff once.  This works because the card does not
6265          * write into the rx buffer posting rings.
6266          */
6267         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6268                 struct tg3_rx_buffer_desc *rxd;
6269
6270                 rxd = &tpr->rx_std[i];
6271                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6272                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6273                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6274                                (i << RXD_OPAQUE_INDEX_SHIFT));
6275         }
6276
6277         /* Now allocate fresh SKBs for each rx ring. */
6278         for (i = 0; i < tp->rx_pending; i++) {
6279                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6280                         netdev_warn(tp->dev,
6281                                     "Using a smaller RX standard ring. Only "
6282                                     "%d out of %d buffers were allocated "
6283                                     "successfully\n", i, tp->rx_pending);
6284                         if (i == 0)
6285                                 goto initfail;
6286                         tp->rx_pending = i;
6287                         break;
6288                 }
6289         }
6290
6291         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6292             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6293                 goto done;
6294
6295         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6296
6297         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6298                 goto done;
6299
6300         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6301                 struct tg3_rx_buffer_desc *rxd;
6302
6303                 rxd = &tpr->rx_jmb[i].std;
6304                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6305                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6306                                   RXD_FLAG_JUMBO;
6307                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6308                        (i << RXD_OPAQUE_INDEX_SHIFT));
6309         }
6310
6311         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6312                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6313                         netdev_warn(tp->dev,
6314                                     "Using a smaller RX jumbo ring. Only %d "
6315                                     "out of %d buffers were allocated "
6316                                     "successfully\n", i, tp->rx_jumbo_pending);
6317                         if (i == 0)
6318                                 goto initfail;
6319                         tp->rx_jumbo_pending = i;
6320                         break;
6321                 }
6322         }
6323
6324 done:
6325         return 0;
6326
6327 initfail:
6328         tg3_rx_prodring_free(tp, tpr);
6329         return -ENOMEM;
6330 }
6331
6332 static void tg3_rx_prodring_fini(struct tg3 *tp,
6333                                  struct tg3_rx_prodring_set *tpr)
6334 {
6335         kfree(tpr->rx_std_buffers);
6336         tpr->rx_std_buffers = NULL;
6337         kfree(tpr->rx_jmb_buffers);
6338         tpr->rx_jmb_buffers = NULL;
6339         if (tpr->rx_std) {
6340                 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6341                                     tpr->rx_std, tpr->rx_std_mapping);
6342                 tpr->rx_std = NULL;
6343         }
6344         if (tpr->rx_jmb) {
6345                 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6346                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6347                 tpr->rx_jmb = NULL;
6348         }
6349 }
6350
6351 static int tg3_rx_prodring_init(struct tg3 *tp,
6352                                 struct tg3_rx_prodring_set *tpr)
6353 {
6354         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6355                                       GFP_KERNEL);
6356         if (!tpr->rx_std_buffers)
6357                 return -ENOMEM;
6358
6359         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6360                                            &tpr->rx_std_mapping);
6361         if (!tpr->rx_std)
6362                 goto err_out;
6363
6364         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6365             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6366                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6367                                               GFP_KERNEL);
6368                 if (!tpr->rx_jmb_buffers)
6369                         goto err_out;
6370
6371                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6372                                                    TG3_RX_JMB_RING_BYTES(tp),
6373                                                    &tpr->rx_jmb_mapping);
6374                 if (!tpr->rx_jmb)
6375                         goto err_out;
6376         }
6377
6378         return 0;
6379
6380 err_out:
6381         tg3_rx_prodring_fini(tp, tpr);
6382         return -ENOMEM;
6383 }
6384
6385 /* Free up pending packets in all rx/tx rings.
6386  *
6387  * The chip has been shut down and the driver detached from
6388  * the networking, so no interrupts or new tx packets will
6389  * end up in the driver.  tp->{tx,}lock is not held and we are not
6390  * in an interrupt context and thus may sleep.
6391  */
6392 static void tg3_free_rings(struct tg3 *tp)
6393 {
6394         int i, j;
6395
6396         for (j = 0; j < tp->irq_cnt; j++) {
6397                 struct tg3_napi *tnapi = &tp->napi[j];
6398
6399                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6400
6401                 if (!tnapi->tx_buffers)
6402                         continue;
6403
6404                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6405                         struct ring_info *txp;
6406                         struct sk_buff *skb;
6407                         unsigned int k;
6408
6409                         txp = &tnapi->tx_buffers[i];
6410                         skb = txp->skb;
6411
6412                         if (skb == NULL) {
6413                                 i++;
6414                                 continue;
6415                         }
6416
6417                         pci_unmap_single(tp->pdev,
6418                                          dma_unmap_addr(txp, mapping),
6419                                          skb_headlen(skb),
6420                                          PCI_DMA_TODEVICE);
6421                         txp->skb = NULL;
6422
6423                         i++;
6424
6425                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6426                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6427                                 pci_unmap_page(tp->pdev,
6428                                                dma_unmap_addr(txp, mapping),
6429                                                skb_shinfo(skb)->frags[k].size,
6430                                                PCI_DMA_TODEVICE);
6431                                 i++;
6432                         }
6433
6434                         dev_kfree_skb_any(skb);
6435                 }
6436         }
6437 }
6438
6439 /* Initialize tx/rx rings for packet processing.
6440  *
6441  * The chip has been shut down and the driver detached from
6442  * the networking, so no interrupts or new tx packets will
6443  * end up in the driver.  tp->{tx,}lock are held and thus
6444  * we may not sleep.
6445  */
6446 static int tg3_init_rings(struct tg3 *tp)
6447 {
6448         int i;
6449
6450         /* Free up all the SKBs. */
6451         tg3_free_rings(tp);
6452
6453         for (i = 0; i < tp->irq_cnt; i++) {
6454                 struct tg3_napi *tnapi = &tp->napi[i];
6455
6456                 tnapi->last_tag = 0;
6457                 tnapi->last_irq_tag = 0;
6458                 tnapi->hw_status->status = 0;
6459                 tnapi->hw_status->status_tag = 0;
6460                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6461
6462                 tnapi->tx_prod = 0;
6463                 tnapi->tx_cons = 0;
6464                 if (tnapi->tx_ring)
6465                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6466
6467                 tnapi->rx_rcb_ptr = 0;
6468                 if (tnapi->rx_rcb)
6469                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6470
6471                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6472                         tg3_free_rings(tp);
6473                         return -ENOMEM;
6474                 }
6475         }
6476
6477         return 0;
6478 }
6479
6480 /*
6481  * Must not be invoked with interrupt sources disabled and
6482  * the hardware shutdown down.
6483  */
6484 static void tg3_free_consistent(struct tg3 *tp)
6485 {
6486         int i;
6487
6488         for (i = 0; i < tp->irq_cnt; i++) {
6489                 struct tg3_napi *tnapi = &tp->napi[i];
6490
6491                 if (tnapi->tx_ring) {
6492                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6493                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6494                         tnapi->tx_ring = NULL;
6495                 }
6496
6497                 kfree(tnapi->tx_buffers);
6498                 tnapi->tx_buffers = NULL;
6499
6500                 if (tnapi->rx_rcb) {
6501                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6502                                             tnapi->rx_rcb,
6503                                             tnapi->rx_rcb_mapping);
6504                         tnapi->rx_rcb = NULL;
6505                 }
6506
6507                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6508
6509                 if (tnapi->hw_status) {
6510                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6511                                             tnapi->hw_status,
6512                                             tnapi->status_mapping);
6513                         tnapi->hw_status = NULL;
6514                 }
6515         }
6516
6517         if (tp->hw_stats) {
6518                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6519                                     tp->hw_stats, tp->stats_mapping);
6520                 tp->hw_stats = NULL;
6521         }
6522 }
6523
6524 /*
6525  * Must not be invoked with interrupt sources disabled and
6526  * the hardware shutdown down.  Can sleep.
6527  */
6528 static int tg3_alloc_consistent(struct tg3 *tp)
6529 {
6530         int i;
6531
6532         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6533                                             sizeof(struct tg3_hw_stats),
6534                                             &tp->stats_mapping);
6535         if (!tp->hw_stats)
6536                 goto err_out;
6537
6538         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6539
6540         for (i = 0; i < tp->irq_cnt; i++) {
6541                 struct tg3_napi *tnapi = &tp->napi[i];
6542                 struct tg3_hw_status *sblk;
6543
6544                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6545                                                         TG3_HW_STATUS_SIZE,
6546                                                         &tnapi->status_mapping);
6547                 if (!tnapi->hw_status)
6548                         goto err_out;
6549
6550                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6551                 sblk = tnapi->hw_status;
6552
6553                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6554                         goto err_out;
6555
6556                 /* If multivector TSS is enabled, vector 0 does not handle
6557                  * tx interrupts.  Don't allocate any resources for it.
6558                  */
6559                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6560                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6561                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6562                                                     TG3_TX_RING_SIZE,
6563                                                     GFP_KERNEL);
6564                         if (!tnapi->tx_buffers)
6565                                 goto err_out;
6566
6567                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6568                                                               TG3_TX_RING_BYTES,
6569                                                        &tnapi->tx_desc_mapping);
6570                         if (!tnapi->tx_ring)
6571                                 goto err_out;
6572                 }
6573
6574                 /*
6575                  * When RSS is enabled, the status block format changes
6576                  * slightly.  The "rx_jumbo_consumer", "reserved",
6577                  * and "rx_mini_consumer" members get mapped to the
6578                  * other three rx return ring producer indexes.
6579                  */
6580                 switch (i) {
6581                 default:
6582                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6583                         break;
6584                 case 2:
6585                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6586                         break;
6587                 case 3:
6588                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6589                         break;
6590                 case 4:
6591                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6592                         break;
6593                 }
6594
6595                 /*
6596                  * If multivector RSS is enabled, vector 0 does not handle
6597                  * rx or tx interrupts.  Don't allocate any resources for it.
6598                  */
6599                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6600                         continue;
6601
6602                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6603                                                      TG3_RX_RCB_RING_BYTES(tp),
6604                                                      &tnapi->rx_rcb_mapping);
6605                 if (!tnapi->rx_rcb)
6606                         goto err_out;
6607
6608                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6609         }
6610
6611         return 0;
6612
6613 err_out:
6614         tg3_free_consistent(tp);
6615         return -ENOMEM;
6616 }
6617
6618 #define MAX_WAIT_CNT 1000
6619
6620 /* To stop a block, clear the enable bit and poll till it
6621  * clears.  tp->lock is held.
6622  */
6623 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6624 {
6625         unsigned int i;
6626         u32 val;
6627
6628         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6629                 switch (ofs) {
6630                 case RCVLSC_MODE:
6631                 case DMAC_MODE:
6632                 case MBFREE_MODE:
6633                 case BUFMGR_MODE:
6634                 case MEMARB_MODE:
6635                         /* We can't enable/disable these bits of the
6636                          * 5705/5750, just say success.
6637                          */
6638                         return 0;
6639
6640                 default:
6641                         break;
6642                 }
6643         }
6644
6645         val = tr32(ofs);
6646         val &= ~enable_bit;
6647         tw32_f(ofs, val);
6648
6649         for (i = 0; i < MAX_WAIT_CNT; i++) {
6650                 udelay(100);
6651                 val = tr32(ofs);
6652                 if ((val & enable_bit) == 0)
6653                         break;
6654         }
6655
6656         if (i == MAX_WAIT_CNT && !silent) {
6657                 dev_err(&tp->pdev->dev,
6658                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6659                         ofs, enable_bit);
6660                 return -ENODEV;
6661         }
6662
6663         return 0;
6664 }
6665
6666 /* tp->lock is held. */
6667 static int tg3_abort_hw(struct tg3 *tp, int silent)
6668 {
6669         int i, err;
6670
6671         tg3_disable_ints(tp);
6672
6673         tp->rx_mode &= ~RX_MODE_ENABLE;
6674         tw32_f(MAC_RX_MODE, tp->rx_mode);
6675         udelay(10);
6676
6677         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6678         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6679         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6680         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6681         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6682         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6683
6684         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6685         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6686         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6687         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6688         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6689         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6690         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6691
6692         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6693         tw32_f(MAC_MODE, tp->mac_mode);
6694         udelay(40);
6695
6696         tp->tx_mode &= ~TX_MODE_ENABLE;
6697         tw32_f(MAC_TX_MODE, tp->tx_mode);
6698
6699         for (i = 0; i < MAX_WAIT_CNT; i++) {
6700                 udelay(100);
6701                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6702                         break;
6703         }
6704         if (i >= MAX_WAIT_CNT) {
6705                 dev_err(&tp->pdev->dev,
6706                         "%s timed out, TX_MODE_ENABLE will not clear "
6707                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6708                 err |= -ENODEV;
6709         }
6710
6711         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6712         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6713         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6714
6715         tw32(FTQ_RESET, 0xffffffff);
6716         tw32(FTQ_RESET, 0x00000000);
6717
6718         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6719         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6720
6721         for (i = 0; i < tp->irq_cnt; i++) {
6722                 struct tg3_napi *tnapi = &tp->napi[i];
6723                 if (tnapi->hw_status)
6724                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6725         }
6726         if (tp->hw_stats)
6727                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6728
6729         return err;
6730 }
6731
6732 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6733 {
6734         int i;
6735         u32 apedata;
6736
6737         /* NCSI does not support APE events */
6738         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6739                 return;
6740
6741         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6742         if (apedata != APE_SEG_SIG_MAGIC)
6743                 return;
6744
6745         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6746         if (!(apedata & APE_FW_STATUS_READY))
6747                 return;
6748
6749         /* Wait for up to 1 millisecond for APE to service previous event. */
6750         for (i = 0; i < 10; i++) {
6751                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6752                         return;
6753
6754                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6755
6756                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6757                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6758                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6759
6760                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6761
6762                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6763                         break;
6764
6765                 udelay(100);
6766         }
6767
6768         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6769                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6770 }
6771
6772 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6773 {
6774         u32 event;
6775         u32 apedata;
6776
6777         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6778                 return;
6779
6780         switch (kind) {
6781         case RESET_KIND_INIT:
6782                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6783                                 APE_HOST_SEG_SIG_MAGIC);
6784                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6785                                 APE_HOST_SEG_LEN_MAGIC);
6786                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6787                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6788                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6789                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6790                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6791                                 APE_HOST_BEHAV_NO_PHYLOCK);
6792                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6793                                     TG3_APE_HOST_DRVR_STATE_START);
6794
6795                 event = APE_EVENT_STATUS_STATE_START;
6796                 break;
6797         case RESET_KIND_SHUTDOWN:
6798                 /* With the interface we are currently using,
6799                  * APE does not track driver state.  Wiping
6800                  * out the HOST SEGMENT SIGNATURE forces
6801                  * the APE to assume OS absent status.
6802                  */
6803                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6804
6805                 if (device_may_wakeup(&tp->pdev->dev) &&
6806                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6807                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6808                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6809                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6810                 } else
6811                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6812
6813                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6814
6815                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6816                 break;
6817         case RESET_KIND_SUSPEND:
6818                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6819                 break;
6820         default:
6821                 return;
6822         }
6823
6824         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6825
6826         tg3_ape_send_event(tp, event);
6827 }
6828
6829 /* tp->lock is held. */
6830 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6831 {
6832         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6833                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6834
6835         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6836                 switch (kind) {
6837                 case RESET_KIND_INIT:
6838                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6839                                       DRV_STATE_START);
6840                         break;
6841
6842                 case RESET_KIND_SHUTDOWN:
6843                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6844                                       DRV_STATE_UNLOAD);
6845                         break;
6846
6847                 case RESET_KIND_SUSPEND:
6848                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6849                                       DRV_STATE_SUSPEND);
6850                         break;
6851
6852                 default:
6853                         break;
6854                 }
6855         }
6856
6857         if (kind == RESET_KIND_INIT ||
6858             kind == RESET_KIND_SUSPEND)
6859                 tg3_ape_driver_state_change(tp, kind);
6860 }
6861
6862 /* tp->lock is held. */
6863 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6864 {
6865         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6866                 switch (kind) {
6867                 case RESET_KIND_INIT:
6868                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6869                                       DRV_STATE_START_DONE);
6870                         break;
6871
6872                 case RESET_KIND_SHUTDOWN:
6873                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6874                                       DRV_STATE_UNLOAD_DONE);
6875                         break;
6876
6877                 default:
6878                         break;
6879                 }
6880         }
6881
6882         if (kind == RESET_KIND_SHUTDOWN)
6883                 tg3_ape_driver_state_change(tp, kind);
6884 }
6885
6886 /* tp->lock is held. */
6887 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6888 {
6889         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6890                 switch (kind) {
6891                 case RESET_KIND_INIT:
6892                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6893                                       DRV_STATE_START);
6894                         break;
6895
6896                 case RESET_KIND_SHUTDOWN:
6897                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6898                                       DRV_STATE_UNLOAD);
6899                         break;
6900
6901                 case RESET_KIND_SUSPEND:
6902                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6903                                       DRV_STATE_SUSPEND);
6904                         break;
6905
6906                 default:
6907                         break;
6908                 }
6909         }
6910 }
6911
6912 static int tg3_poll_fw(struct tg3 *tp)
6913 {
6914         int i;
6915         u32 val;
6916
6917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6918                 /* Wait up to 20ms for init done. */
6919                 for (i = 0; i < 200; i++) {
6920                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6921                                 return 0;
6922                         udelay(100);
6923                 }
6924                 return -ENODEV;
6925         }
6926
6927         /* Wait for firmware initialization to complete. */
6928         for (i = 0; i < 100000; i++) {
6929                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6930                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6931                         break;
6932                 udelay(10);
6933         }
6934
6935         /* Chip might not be fitted with firmware.  Some Sun onboard
6936          * parts are configured like that.  So don't signal the timeout
6937          * of the above loop as an error, but do report the lack of
6938          * running firmware once.
6939          */
6940         if (i >= 100000 &&
6941             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6942                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6943
6944                 netdev_info(tp->dev, "No firmware running\n");
6945         }
6946
6947         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6948                 /* The 57765 A0 needs a little more
6949                  * time to do some important work.
6950                  */
6951                 mdelay(10);
6952         }
6953
6954         return 0;
6955 }
6956
6957 /* Save PCI command register before chip reset */
6958 static void tg3_save_pci_state(struct tg3 *tp)
6959 {
6960         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6961 }
6962
6963 /* Restore PCI state after chip reset */
6964 static void tg3_restore_pci_state(struct tg3 *tp)
6965 {
6966         u32 val;
6967
6968         /* Re-enable indirect register accesses. */
6969         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6970                                tp->misc_host_ctrl);
6971
6972         /* Set MAX PCI retry to zero. */
6973         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6974         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6975             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6976                 val |= PCISTATE_RETRY_SAME_DMA;
6977         /* Allow reads and writes to the APE register and memory space. */
6978         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6979                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6980                        PCISTATE_ALLOW_APE_SHMEM_WR |
6981                        PCISTATE_ALLOW_APE_PSPACE_WR;
6982         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6983
6984         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6985
6986         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6987                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6988                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6989                 else {
6990                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6991                                               tp->pci_cacheline_sz);
6992                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6993                                               tp->pci_lat_timer);
6994                 }
6995         }
6996
6997         /* Make sure PCI-X relaxed ordering bit is clear. */
6998         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6999                 u16 pcix_cmd;
7000
7001                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7002                                      &pcix_cmd);
7003                 pcix_cmd &= ~PCI_X_CMD_ERO;
7004                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7005                                       pcix_cmd);
7006         }
7007
7008         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7009
7010                 /* Chip reset on 5780 will reset MSI enable bit,
7011                  * so need to restore it.
7012                  */
7013                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7014                         u16 ctrl;
7015
7016                         pci_read_config_word(tp->pdev,
7017                                              tp->msi_cap + PCI_MSI_FLAGS,
7018                                              &ctrl);
7019                         pci_write_config_word(tp->pdev,
7020                                               tp->msi_cap + PCI_MSI_FLAGS,
7021                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7022                         val = tr32(MSGINT_MODE);
7023                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7024                 }
7025         }
7026 }
7027
7028 static void tg3_stop_fw(struct tg3 *);
7029
7030 /* tp->lock is held. */
7031 static int tg3_chip_reset(struct tg3 *tp)
7032 {
7033         u32 val;
7034         void (*write_op)(struct tg3 *, u32, u32);
7035         int i, err;
7036
7037         tg3_nvram_lock(tp);
7038
7039         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7040
7041         /* No matching tg3_nvram_unlock() after this because
7042          * chip reset below will undo the nvram lock.
7043          */
7044         tp->nvram_lock_cnt = 0;
7045
7046         /* GRC_MISC_CFG core clock reset will clear the memory
7047          * enable bit in PCI register 4 and the MSI enable bit
7048          * on some chips, so we save relevant registers here.
7049          */
7050         tg3_save_pci_state(tp);
7051
7052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7053             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7054                 tw32(GRC_FASTBOOT_PC, 0);
7055
7056         /*
7057          * We must avoid the readl() that normally takes place.
7058          * It locks machines, causes machine checks, and other
7059          * fun things.  So, temporarily disable the 5701
7060          * hardware workaround, while we do the reset.
7061          */
7062         write_op = tp->write32;
7063         if (write_op == tg3_write_flush_reg32)
7064                 tp->write32 = tg3_write32;
7065
7066         /* Prevent the irq handler from reading or writing PCI registers
7067          * during chip reset when the memory enable bit in the PCI command
7068          * register may be cleared.  The chip does not generate interrupt
7069          * at this time, but the irq handler may still be called due to irq
7070          * sharing or irqpoll.
7071          */
7072         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7073         for (i = 0; i < tp->irq_cnt; i++) {
7074                 struct tg3_napi *tnapi = &tp->napi[i];
7075                 if (tnapi->hw_status) {
7076                         tnapi->hw_status->status = 0;
7077                         tnapi->hw_status->status_tag = 0;
7078                 }
7079                 tnapi->last_tag = 0;
7080                 tnapi->last_irq_tag = 0;
7081         }
7082         smp_mb();
7083
7084         for (i = 0; i < tp->irq_cnt; i++)
7085                 synchronize_irq(tp->napi[i].irq_vec);
7086
7087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7088                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7089                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7090         }
7091
7092         /* do the reset */
7093         val = GRC_MISC_CFG_CORECLK_RESET;
7094
7095         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7096                 /* Force PCIe 1.0a mode */
7097                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7098                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7099                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7100                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7101                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7102
7103                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7104                         tw32(GRC_MISC_CFG, (1 << 29));
7105                         val |= (1 << 29);
7106                 }
7107         }
7108
7109         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7110                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7111                 tw32(GRC_VCPU_EXT_CTRL,
7112                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7113         }
7114
7115         /* Manage gphy power for all CPMU absent PCIe devices. */
7116         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7117             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7118                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7119
7120         tw32(GRC_MISC_CFG, val);
7121
7122         /* restore 5701 hardware bug workaround write method */
7123         tp->write32 = write_op;
7124
7125         /* Unfortunately, we have to delay before the PCI read back.
7126          * Some 575X chips even will not respond to a PCI cfg access
7127          * when the reset command is given to the chip.
7128          *
7129          * How do these hardware designers expect things to work
7130          * properly if the PCI write is posted for a long period
7131          * of time?  It is always necessary to have some method by
7132          * which a register read back can occur to push the write
7133          * out which does the reset.
7134          *
7135          * For most tg3 variants the trick below was working.
7136          * Ho hum...
7137          */
7138         udelay(120);
7139
7140         /* Flush PCI posted writes.  The normal MMIO registers
7141          * are inaccessible at this time so this is the only
7142          * way to make this reliably (actually, this is no longer
7143          * the case, see above).  I tried to use indirect
7144          * register read/write but this upset some 5701 variants.
7145          */
7146         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7147
7148         udelay(120);
7149
7150         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7151                 u16 val16;
7152
7153                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7154                         int i;
7155                         u32 cfg_val;
7156
7157                         /* Wait for link training to complete.  */
7158                         for (i = 0; i < 5000; i++)
7159                                 udelay(100);
7160
7161                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7162                         pci_write_config_dword(tp->pdev, 0xc4,
7163                                                cfg_val | (1 << 15));
7164                 }
7165
7166                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7167                 pci_read_config_word(tp->pdev,
7168                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7169                                      &val16);
7170                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7171                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7172                 /*
7173                  * Older PCIe devices only support the 128 byte
7174                  * MPS setting.  Enforce the restriction.
7175                  */
7176                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7177                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7178                 pci_write_config_word(tp->pdev,
7179                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7180                                       val16);
7181
7182                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7183
7184                 /* Clear error status */
7185                 pci_write_config_word(tp->pdev,
7186                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7187                                       PCI_EXP_DEVSTA_CED |
7188                                       PCI_EXP_DEVSTA_NFED |
7189                                       PCI_EXP_DEVSTA_FED |
7190                                       PCI_EXP_DEVSTA_URD);
7191         }
7192
7193         tg3_restore_pci_state(tp);
7194
7195         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7196
7197         val = 0;
7198         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7199                 val = tr32(MEMARB_MODE);
7200         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7201
7202         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7203                 tg3_stop_fw(tp);
7204                 tw32(0x5000, 0x400);
7205         }
7206
7207         tw32(GRC_MODE, tp->grc_mode);
7208
7209         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7210                 val = tr32(0xc4);
7211
7212                 tw32(0xc4, val | (1 << 15));
7213         }
7214
7215         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7217                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7218                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7219                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7220                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7221         }
7222
7223         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7224                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7225                                MAC_MODE_APE_RX_EN |
7226                                MAC_MODE_TDE_ENABLE;
7227
7228         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7229                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7230                 val = tp->mac_mode;
7231         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7232                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7233                 val = tp->mac_mode;
7234         } else
7235                 val = 0;
7236
7237         tw32_f(MAC_MODE, val);
7238         udelay(40);
7239
7240         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7241
7242         err = tg3_poll_fw(tp);
7243         if (err)
7244                 return err;
7245
7246         tg3_mdio_start(tp);
7247
7248         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7249             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7250             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7251             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7252                 val = tr32(0x7c00);
7253
7254                 tw32(0x7c00, val | (1 << 25));
7255         }
7256
7257         /* Reprobe ASF enable state.  */
7258         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7259         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7260         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7261         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7262                 u32 nic_cfg;
7263
7264                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7265                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7266                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7267                         tp->last_event_jiffies = jiffies;
7268                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7269                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7270                 }
7271         }
7272
7273         return 0;
7274 }
7275
7276 /* tp->lock is held. */
7277 static void tg3_stop_fw(struct tg3 *tp)
7278 {
7279         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7280            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7281                 /* Wait for RX cpu to ACK the previous event. */
7282                 tg3_wait_for_event_ack(tp);
7283
7284                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7285
7286                 tg3_generate_fw_event(tp);
7287
7288                 /* Wait for RX cpu to ACK this event. */
7289                 tg3_wait_for_event_ack(tp);
7290         }
7291 }
7292
7293 /* tp->lock is held. */
7294 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7295 {
7296         int err;
7297
7298         tg3_stop_fw(tp);
7299
7300         tg3_write_sig_pre_reset(tp, kind);
7301
7302         tg3_abort_hw(tp, silent);
7303         err = tg3_chip_reset(tp);
7304
7305         __tg3_set_mac_addr(tp, 0);
7306
7307         tg3_write_sig_legacy(tp, kind);
7308         tg3_write_sig_post_reset(tp, kind);
7309
7310         if (err)
7311                 return err;
7312
7313         return 0;
7314 }
7315
7316 #define RX_CPU_SCRATCH_BASE     0x30000
7317 #define RX_CPU_SCRATCH_SIZE     0x04000
7318 #define TX_CPU_SCRATCH_BASE     0x34000
7319 #define TX_CPU_SCRATCH_SIZE     0x04000
7320
7321 /* tp->lock is held. */
7322 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7323 {
7324         int i;
7325
7326         BUG_ON(offset == TX_CPU_BASE &&
7327             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7328
7329         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7330                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7331
7332                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7333                 return 0;
7334         }
7335         if (offset == RX_CPU_BASE) {
7336                 for (i = 0; i < 10000; i++) {
7337                         tw32(offset + CPU_STATE, 0xffffffff);
7338                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7339                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7340                                 break;
7341                 }
7342
7343                 tw32(offset + CPU_STATE, 0xffffffff);
7344                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7345                 udelay(10);
7346         } else {
7347                 for (i = 0; i < 10000; i++) {
7348                         tw32(offset + CPU_STATE, 0xffffffff);
7349                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7350                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7351                                 break;
7352                 }
7353         }
7354
7355         if (i >= 10000) {
7356                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7357                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7358                 return -ENODEV;
7359         }
7360
7361         /* Clear firmware's nvram arbitration. */
7362         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7363                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7364         return 0;
7365 }
7366
7367 struct fw_info {
7368         unsigned int fw_base;
7369         unsigned int fw_len;
7370         const __be32 *fw_data;
7371 };
7372
7373 /* tp->lock is held. */
7374 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7375                                  int cpu_scratch_size, struct fw_info *info)
7376 {
7377         int err, lock_err, i;
7378         void (*write_op)(struct tg3 *, u32, u32);
7379
7380         if (cpu_base == TX_CPU_BASE &&
7381             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7382                 netdev_err(tp->dev,
7383                            "%s: Trying to load TX cpu firmware which is 5705\n",
7384                            __func__);
7385                 return -EINVAL;
7386         }
7387
7388         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7389                 write_op = tg3_write_mem;
7390         else
7391                 write_op = tg3_write_indirect_reg32;
7392
7393         /* It is possible that bootcode is still loading at this point.
7394          * Get the nvram lock first before halting the cpu.
7395          */
7396         lock_err = tg3_nvram_lock(tp);
7397         err = tg3_halt_cpu(tp, cpu_base);
7398         if (!lock_err)
7399                 tg3_nvram_unlock(tp);
7400         if (err)
7401                 goto out;
7402
7403         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7404                 write_op(tp, cpu_scratch_base + i, 0);
7405         tw32(cpu_base + CPU_STATE, 0xffffffff);
7406         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7407         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7408                 write_op(tp, (cpu_scratch_base +
7409                               (info->fw_base & 0xffff) +
7410                               (i * sizeof(u32))),
7411                               be32_to_cpu(info->fw_data[i]));
7412
7413         err = 0;
7414
7415 out:
7416         return err;
7417 }
7418
7419 /* tp->lock is held. */
7420 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7421 {
7422         struct fw_info info;
7423         const __be32 *fw_data;
7424         int err, i;
7425
7426         fw_data = (void *)tp->fw->data;
7427
7428         /* Firmware blob starts with version numbers, followed by
7429            start address and length. We are setting complete length.
7430            length = end_address_of_bss - start_address_of_text.
7431            Remainder is the blob to be loaded contiguously
7432            from start address. */
7433
7434         info.fw_base = be32_to_cpu(fw_data[1]);
7435         info.fw_len = tp->fw->size - 12;
7436         info.fw_data = &fw_data[3];
7437
7438         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7439                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7440                                     &info);
7441         if (err)
7442                 return err;
7443
7444         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7445                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7446                                     &info);
7447         if (err)
7448                 return err;
7449
7450         /* Now startup only the RX cpu. */
7451         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7452         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7453
7454         for (i = 0; i < 5; i++) {
7455                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7456                         break;
7457                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7458                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7459                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7460                 udelay(1000);
7461         }
7462         if (i >= 5) {
7463                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7464                            "should be %08x\n", __func__,
7465                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7466                 return -ENODEV;
7467         }
7468         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7469         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7470
7471         return 0;
7472 }
7473
7474 /* 5705 needs a special version of the TSO firmware.  */
7475
7476 /* tp->lock is held. */
7477 static int tg3_load_tso_firmware(struct tg3 *tp)
7478 {
7479         struct fw_info info;
7480         const __be32 *fw_data;
7481         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7482         int err, i;
7483
7484         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7485                 return 0;
7486
7487         fw_data = (void *)tp->fw->data;
7488
7489         /* Firmware blob starts with version numbers, followed by
7490            start address and length. We are setting complete length.
7491            length = end_address_of_bss - start_address_of_text.
7492            Remainder is the blob to be loaded contiguously
7493            from start address. */
7494
7495         info.fw_base = be32_to_cpu(fw_data[1]);
7496         cpu_scratch_size = tp->fw_len;
7497         info.fw_len = tp->fw->size - 12;
7498         info.fw_data = &fw_data[3];
7499
7500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7501                 cpu_base = RX_CPU_BASE;
7502                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7503         } else {
7504                 cpu_base = TX_CPU_BASE;
7505                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7506                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7507         }
7508
7509         err = tg3_load_firmware_cpu(tp, cpu_base,
7510                                     cpu_scratch_base, cpu_scratch_size,
7511                                     &info);
7512         if (err)
7513                 return err;
7514
7515         /* Now startup the cpu. */
7516         tw32(cpu_base + CPU_STATE, 0xffffffff);
7517         tw32_f(cpu_base + CPU_PC, info.fw_base);
7518
7519         for (i = 0; i < 5; i++) {
7520                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7521                         break;
7522                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7523                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7524                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7525                 udelay(1000);
7526         }
7527         if (i >= 5) {
7528                 netdev_err(tp->dev,
7529                            "%s fails to set CPU PC, is %08x should be %08x\n",
7530                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7531                 return -ENODEV;
7532         }
7533         tw32(cpu_base + CPU_STATE, 0xffffffff);
7534         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7535         return 0;
7536 }
7537
7538
7539 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7540 {
7541         struct tg3 *tp = netdev_priv(dev);
7542         struct sockaddr *addr = p;
7543         int err = 0, skip_mac_1 = 0;
7544
7545         if (!is_valid_ether_addr(addr->sa_data))
7546                 return -EINVAL;
7547
7548         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7549
7550         if (!netif_running(dev))
7551                 return 0;
7552
7553         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7554                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7555
7556                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7557                 addr0_low = tr32(MAC_ADDR_0_LOW);
7558                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7559                 addr1_low = tr32(MAC_ADDR_1_LOW);
7560
7561                 /* Skip MAC addr 1 if ASF is using it. */
7562                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7563                     !(addr1_high == 0 && addr1_low == 0))
7564                         skip_mac_1 = 1;
7565         }
7566         spin_lock_bh(&tp->lock);
7567         __tg3_set_mac_addr(tp, skip_mac_1);
7568         spin_unlock_bh(&tp->lock);
7569
7570         return err;
7571 }
7572
7573 /* tp->lock is held. */
7574 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7575                            dma_addr_t mapping, u32 maxlen_flags,
7576                            u32 nic_addr)
7577 {
7578         tg3_write_mem(tp,
7579                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7580                       ((u64) mapping >> 32));
7581         tg3_write_mem(tp,
7582                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7583                       ((u64) mapping & 0xffffffff));
7584         tg3_write_mem(tp,
7585                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7586                        maxlen_flags);
7587
7588         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7589                 tg3_write_mem(tp,
7590                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7591                               nic_addr);
7592 }
7593
7594 static void __tg3_set_rx_mode(struct net_device *);
7595 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7596 {
7597         int i;
7598
7599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7600                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7601                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7602                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7603         } else {
7604                 tw32(HOSTCC_TXCOL_TICKS, 0);
7605                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7606                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7607         }
7608
7609         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7610                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7611                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7612                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7613         } else {
7614                 tw32(HOSTCC_RXCOL_TICKS, 0);
7615                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7616                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7617         }
7618
7619         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7620                 u32 val = ec->stats_block_coalesce_usecs;
7621
7622                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7623                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7624
7625                 if (!netif_carrier_ok(tp->dev))
7626                         val = 0;
7627
7628                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7629         }
7630
7631         for (i = 0; i < tp->irq_cnt - 1; i++) {
7632                 u32 reg;
7633
7634                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7635                 tw32(reg, ec->rx_coalesce_usecs);
7636                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7637                 tw32(reg, ec->rx_max_coalesced_frames);
7638                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7639                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7640
7641                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7642                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7643                         tw32(reg, ec->tx_coalesce_usecs);
7644                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7645                         tw32(reg, ec->tx_max_coalesced_frames);
7646                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7647                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7648                 }
7649         }
7650
7651         for (; i < tp->irq_max - 1; i++) {
7652                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7653                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7654                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7655
7656                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7657                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7658                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7659                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7660                 }
7661         }
7662 }
7663
7664 /* tp->lock is held. */
7665 static void tg3_rings_reset(struct tg3 *tp)
7666 {
7667         int i;
7668         u32 stblk, txrcb, rxrcb, limit;
7669         struct tg3_napi *tnapi = &tp->napi[0];
7670
7671         /* Disable all transmit rings but the first. */
7672         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7673                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7674         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7675                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7676                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7677         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7678                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7679         else
7680                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7681
7682         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7683              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7684                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7685                               BDINFO_FLAGS_DISABLED);
7686
7687
7688         /* Disable all receive return rings but the first. */
7689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7690             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7691                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7692         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7694         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7695                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7696                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7697         else
7698                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7699
7700         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7701              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7702                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7703                               BDINFO_FLAGS_DISABLED);
7704
7705         /* Disable interrupts */
7706         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7707
7708         /* Zero mailbox registers. */
7709         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7710                 for (i = 1; i < tp->irq_max; i++) {
7711                         tp->napi[i].tx_prod = 0;
7712                         tp->napi[i].tx_cons = 0;
7713                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7714                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7715                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7716                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7717                 }
7718                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7719                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7720         } else {
7721                 tp->napi[0].tx_prod = 0;
7722                 tp->napi[0].tx_cons = 0;
7723                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7724                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7725         }
7726
7727         /* Make sure the NIC-based send BD rings are disabled. */
7728         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7729                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7730                 for (i = 0; i < 16; i++)
7731                         tw32_tx_mbox(mbox + i * 8, 0);
7732         }
7733
7734         txrcb = NIC_SRAM_SEND_RCB;
7735         rxrcb = NIC_SRAM_RCV_RET_RCB;
7736
7737         /* Clear status block in ram. */
7738         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7739
7740         /* Set status block DMA address */
7741         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7742              ((u64) tnapi->status_mapping >> 32));
7743         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7744              ((u64) tnapi->status_mapping & 0xffffffff));
7745
7746         if (tnapi->tx_ring) {
7747                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7748                                (TG3_TX_RING_SIZE <<
7749                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7750                                NIC_SRAM_TX_BUFFER_DESC);
7751                 txrcb += TG3_BDINFO_SIZE;
7752         }
7753
7754         if (tnapi->rx_rcb) {
7755                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7756                                (tp->rx_ret_ring_mask + 1) <<
7757                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7758                 rxrcb += TG3_BDINFO_SIZE;
7759         }
7760
7761         stblk = HOSTCC_STATBLCK_RING1;
7762
7763         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7764                 u64 mapping = (u64)tnapi->status_mapping;
7765                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7766                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7767
7768                 /* Clear status block in ram. */
7769                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7770
7771                 if (tnapi->tx_ring) {
7772                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7773                                        (TG3_TX_RING_SIZE <<
7774                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7775                                        NIC_SRAM_TX_BUFFER_DESC);
7776                         txrcb += TG3_BDINFO_SIZE;
7777                 }
7778
7779                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7780                                ((tp->rx_ret_ring_mask + 1) <<
7781                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7782
7783                 stblk += 8;
7784                 rxrcb += TG3_BDINFO_SIZE;
7785         }
7786 }
7787
7788 /* tp->lock is held. */
7789 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7790 {
7791         u32 val, rdmac_mode;
7792         int i, err, limit;
7793         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7794
7795         tg3_disable_ints(tp);
7796
7797         tg3_stop_fw(tp);
7798
7799         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7800
7801         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7802                 tg3_abort_hw(tp, 1);
7803
7804         if (reset_phy)
7805                 tg3_phy_reset(tp);
7806
7807         err = tg3_chip_reset(tp);
7808         if (err)
7809                 return err;
7810
7811         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7812
7813         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7814                 val = tr32(TG3_CPMU_CTRL);
7815                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7816                 tw32(TG3_CPMU_CTRL, val);
7817
7818                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7819                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7820                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7821                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7822
7823                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7824                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7825                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7826                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7827
7828                 val = tr32(TG3_CPMU_HST_ACC);
7829                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7830                 val |= CPMU_HST_ACC_MACCLK_6_25;
7831                 tw32(TG3_CPMU_HST_ACC, val);
7832         }
7833
7834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7835                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7836                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7837                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7838                 tw32(PCIE_PWR_MGMT_THRESH, val);
7839
7840                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7841                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7842
7843                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7844
7845                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7846                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7847         }
7848
7849         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7850                 u32 grc_mode = tr32(GRC_MODE);
7851
7852                 /* Access the lower 1K of PL PCIE block registers. */
7853                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7854                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7855
7856                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7857                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7858                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7859
7860                 tw32(GRC_MODE, grc_mode);
7861         }
7862
7863         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7864                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7865                         u32 grc_mode = tr32(GRC_MODE);
7866
7867                         /* Access the lower 1K of PL PCIE block registers. */
7868                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7869                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7870
7871                         val = tr32(TG3_PCIE_TLDLPL_PORT +
7872                                    TG3_PCIE_PL_LO_PHYCTL5);
7873                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7874                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7875
7876                         tw32(GRC_MODE, grc_mode);
7877                 }
7878
7879                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7880                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7881                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7882                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7883         }
7884
7885         /* Enable MAC control of LPI */
7886         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7887                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7888                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7889                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7890
7891                 tw32_f(TG3_CPMU_EEE_CTRL,
7892                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7893
7894                 tw32_f(TG3_CPMU_EEE_MODE,
7895                        TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7896                        TG3_CPMU_EEEMD_LPI_IN_TX |
7897                        TG3_CPMU_EEEMD_LPI_IN_RX |
7898                        TG3_CPMU_EEEMD_EEE_ENABLE);
7899         }
7900
7901         /* This works around an issue with Athlon chipsets on
7902          * B3 tigon3 silicon.  This bit has no effect on any
7903          * other revision.  But do not set this on PCI Express
7904          * chips and don't even touch the clocks if the CPMU is present.
7905          */
7906         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7907                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7908                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7909                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7910         }
7911
7912         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7913             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7914                 val = tr32(TG3PCI_PCISTATE);
7915                 val |= PCISTATE_RETRY_SAME_DMA;
7916                 tw32(TG3PCI_PCISTATE, val);
7917         }
7918
7919         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7920                 /* Allow reads and writes to the
7921                  * APE register and memory space.
7922                  */
7923                 val = tr32(TG3PCI_PCISTATE);
7924                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7925                        PCISTATE_ALLOW_APE_SHMEM_WR |
7926                        PCISTATE_ALLOW_APE_PSPACE_WR;
7927                 tw32(TG3PCI_PCISTATE, val);
7928         }
7929
7930         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7931                 /* Enable some hw fixes.  */
7932                 val = tr32(TG3PCI_MSI_DATA);
7933                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7934                 tw32(TG3PCI_MSI_DATA, val);
7935         }
7936
7937         /* Descriptor ring init may make accesses to the
7938          * NIC SRAM area to setup the TX descriptors, so we
7939          * can only do this after the hardware has been
7940          * successfully reset.
7941          */
7942         err = tg3_init_rings(tp);
7943         if (err)
7944                 return err;
7945
7946         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7947                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7948                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7949                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7950                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7951                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7952         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7953                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7954                 /* This value is determined during the probe time DMA
7955                  * engine test, tg3_test_dma.
7956                  */
7957                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7958         }
7959
7960         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7961                           GRC_MODE_4X_NIC_SEND_RINGS |
7962                           GRC_MODE_NO_TX_PHDR_CSUM |
7963                           GRC_MODE_NO_RX_PHDR_CSUM);
7964         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7965
7966         /* Pseudo-header checksum is done by hardware logic and not
7967          * the offload processers, so make the chip do the pseudo-
7968          * header checksums on receive.  For transmit it is more
7969          * convenient to do the pseudo-header checksum in software
7970          * as Linux does that on transmit for us in all cases.
7971          */
7972         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7973
7974         tw32(GRC_MODE,
7975              tp->grc_mode |
7976              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7977
7978         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7979         val = tr32(GRC_MISC_CFG);
7980         val &= ~0xff;
7981         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7982         tw32(GRC_MISC_CFG, val);
7983
7984         /* Initialize MBUF/DESC pool. */
7985         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7986                 /* Do nothing.  */
7987         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7988                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7989                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7990                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7991                 else
7992                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7993                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7994                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7995         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7996                 int fw_len;
7997
7998                 fw_len = tp->fw_len;
7999                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8000                 tw32(BUFMGR_MB_POOL_ADDR,
8001                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8002                 tw32(BUFMGR_MB_POOL_SIZE,
8003                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8004         }
8005
8006         if (tp->dev->mtu <= ETH_DATA_LEN) {
8007                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8008                      tp->bufmgr_config.mbuf_read_dma_low_water);
8009                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8010                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8011                 tw32(BUFMGR_MB_HIGH_WATER,
8012                      tp->bufmgr_config.mbuf_high_water);
8013         } else {
8014                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8015                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8016                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8017                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8018                 tw32(BUFMGR_MB_HIGH_WATER,
8019                      tp->bufmgr_config.mbuf_high_water_jumbo);
8020         }
8021         tw32(BUFMGR_DMA_LOW_WATER,
8022              tp->bufmgr_config.dma_low_water);
8023         tw32(BUFMGR_DMA_HIGH_WATER,
8024              tp->bufmgr_config.dma_high_water);
8025
8026         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8028                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8029         tw32(BUFMGR_MODE, val);
8030         for (i = 0; i < 2000; i++) {
8031                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8032                         break;
8033                 udelay(10);
8034         }
8035         if (i >= 2000) {
8036                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8037                 return -ENODEV;
8038         }
8039
8040         /* Setup replenish threshold. */
8041         val = tp->rx_pending / 8;
8042         if (val == 0)
8043                 val = 1;
8044         else if (val > tp->rx_std_max_post)
8045                 val = tp->rx_std_max_post;
8046         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8047                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8048                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8049
8050                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8051                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8052         }
8053
8054         tw32(RCVBDI_STD_THRESH, val);
8055
8056         /* Initialize TG3_BDINFO's at:
8057          *  RCVDBDI_STD_BD:     standard eth size rx ring
8058          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8059          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8060          *
8061          * like so:
8062          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8063          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8064          *                              ring attribute flags
8065          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8066          *
8067          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8068          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8069          *
8070          * The size of each ring is fixed in the firmware, but the location is
8071          * configurable.
8072          */
8073         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8074              ((u64) tpr->rx_std_mapping >> 32));
8075         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8076              ((u64) tpr->rx_std_mapping & 0xffffffff));
8077         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8078             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8079                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8080                      NIC_SRAM_RX_BUFFER_DESC);
8081
8082         /* Disable the mini ring */
8083         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8084                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8085                      BDINFO_FLAGS_DISABLED);
8086
8087         /* Program the jumbo buffer descriptor ring control
8088          * blocks on those devices that have them.
8089          */
8090         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8091             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8092                 /* Setup replenish threshold. */
8093                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8094
8095                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8096                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8097                              ((u64) tpr->rx_jmb_mapping >> 32));
8098                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8099                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8100                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8101                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8102                              BDINFO_FLAGS_USE_EXT_RECV);
8103                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8104                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8105                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8106                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8107                 } else {
8108                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8109                              BDINFO_FLAGS_DISABLED);
8110                 }
8111
8112                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8113                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8114                                 val = RX_STD_MAX_SIZE_5705;
8115                         else
8116                                 val = RX_STD_MAX_SIZE_5717;
8117                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8118                         val |= (TG3_RX_STD_DMA_SZ << 2);
8119                 } else
8120                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8121         } else
8122                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8123
8124         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8125
8126         tpr->rx_std_prod_idx = tp->rx_pending;
8127         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8128
8129         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8130                           tp->rx_jumbo_pending : 0;
8131         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8132
8133         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8134                 tw32(STD_REPLENISH_LWM, 32);
8135                 tw32(JMB_REPLENISH_LWM, 16);
8136         }
8137
8138         tg3_rings_reset(tp);
8139
8140         /* Initialize MAC address and backoff seed. */
8141         __tg3_set_mac_addr(tp, 0);
8142
8143         /* MTU + ethernet header + FCS + optional VLAN tag */
8144         tw32(MAC_RX_MTU_SIZE,
8145              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8146
8147         /* The slot time is changed by tg3_setup_phy if we
8148          * run at gigabit with half duplex.
8149          */
8150         tw32(MAC_TX_LENGTHS,
8151              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8152              (6 << TX_LENGTHS_IPG_SHIFT) |
8153              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8154
8155         /* Receive rules. */
8156         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8157         tw32(RCVLPC_CONFIG, 0x0181);
8158
8159         /* Calculate RDMAC_MODE setting early, we need it to determine
8160          * the RCVLPC_STATE_ENABLE mask.
8161          */
8162         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8163                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8164                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8165                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8166                       RDMAC_MODE_LNGREAD_ENAB);
8167
8168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8169                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8170
8171         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8172             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8173             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8174                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8175                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8176                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8177
8178         /* If statement applies to 5705 and 5750 PCI devices only */
8179         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8180              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8181             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8182                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8183                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8184                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8185                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8186                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8187                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8188                 }
8189         }
8190
8191         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8192                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8193
8194         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8195                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8196
8197         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8199             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8200                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8201
8202         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8203             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8204             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8205             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8206             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8207                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8208                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8209                         val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
8210                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
8211                 }
8212                 tw32(TG3_RDMA_RSRVCTRL_REG,
8213                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8214         }
8215
8216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8217                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8218                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8219                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8220                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8221         }
8222
8223         /* Receive/send statistics. */
8224         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8225                 val = tr32(RCVLPC_STATS_ENABLE);
8226                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8227                 tw32(RCVLPC_STATS_ENABLE, val);
8228         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8229                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8230                 val = tr32(RCVLPC_STATS_ENABLE);
8231                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8232                 tw32(RCVLPC_STATS_ENABLE, val);
8233         } else {
8234                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8235         }
8236         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8237         tw32(SNDDATAI_STATSENAB, 0xffffff);
8238         tw32(SNDDATAI_STATSCTRL,
8239              (SNDDATAI_SCTRL_ENABLE |
8240               SNDDATAI_SCTRL_FASTUPD));
8241
8242         /* Setup host coalescing engine. */
8243         tw32(HOSTCC_MODE, 0);
8244         for (i = 0; i < 2000; i++) {
8245                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8246                         break;
8247                 udelay(10);
8248         }
8249
8250         __tg3_set_coalesce(tp, &tp->coal);
8251
8252         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8253                 /* Status/statistics block address.  See tg3_timer,
8254                  * the tg3_periodic_fetch_stats call there, and
8255                  * tg3_get_stats to see how this works for 5705/5750 chips.
8256                  */
8257                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8258                      ((u64) tp->stats_mapping >> 32));
8259                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8260                      ((u64) tp->stats_mapping & 0xffffffff));
8261                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8262
8263                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8264
8265                 /* Clear statistics and status block memory areas */
8266                 for (i = NIC_SRAM_STATS_BLK;
8267                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8268                      i += sizeof(u32)) {
8269                         tg3_write_mem(tp, i, 0);
8270                         udelay(40);
8271                 }
8272         }
8273
8274         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8275
8276         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8277         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8278         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8279                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8280
8281         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8282                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8283                 /* reset to prevent losing 1st rx packet intermittently */
8284                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8285                 udelay(10);
8286         }
8287
8288         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8289                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8290         else
8291                 tp->mac_mode = 0;
8292         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8293                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8294         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8295             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8296             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8297                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8298         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8299         udelay(40);
8300
8301         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8302          * If TG3_FLG2_IS_NIC is zero, we should read the
8303          * register to preserve the GPIO settings for LOMs. The GPIOs,
8304          * whether used as inputs or outputs, are set by boot code after
8305          * reset.
8306          */
8307         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8308                 u32 gpio_mask;
8309
8310                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8311                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8312                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8313
8314                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8315                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8316                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8317
8318                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8319                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8320
8321                 tp->grc_local_ctrl &= ~gpio_mask;
8322                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8323
8324                 /* GPIO1 must be driven high for eeprom write protect */
8325                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8326                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8327                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8328         }
8329         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8330         udelay(100);
8331
8332         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8333                 val = tr32(MSGINT_MODE);
8334                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8335                 tw32(MSGINT_MODE, val);
8336         }
8337
8338         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8339                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8340                 udelay(40);
8341         }
8342
8343         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8344                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8345                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8346                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8347                WDMAC_MODE_LNGREAD_ENAB);
8348
8349         /* If statement applies to 5705 and 5750 PCI devices only */
8350         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8351              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8352             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8353                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8354                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8355                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8356                         /* nothing */
8357                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8358                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8359                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8360                         val |= WDMAC_MODE_RX_ACCEL;
8361                 }
8362         }
8363
8364         /* Enable host coalescing bug fix */
8365         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8366                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8367
8368         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8369                 val |= WDMAC_MODE_BURST_ALL_DATA;
8370
8371         tw32_f(WDMAC_MODE, val);
8372         udelay(40);
8373
8374         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8375                 u16 pcix_cmd;
8376
8377                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8378                                      &pcix_cmd);
8379                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8380                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8381                         pcix_cmd |= PCI_X_CMD_READ_2K;
8382                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8383                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8384                         pcix_cmd |= PCI_X_CMD_READ_2K;
8385                 }
8386                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8387                                       pcix_cmd);
8388         }
8389
8390         tw32_f(RDMAC_MODE, rdmac_mode);
8391         udelay(40);
8392
8393         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8394         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8395                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8396
8397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8398                 tw32(SNDDATAC_MODE,
8399                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8400         else
8401                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8402
8403         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8404         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8405         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8406         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8407             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8408                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8409         tw32(RCVDBDI_MODE, val);
8410         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8411         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8412                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8413         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8414         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8415                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8416         tw32(SNDBDI_MODE, val);
8417         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8418
8419         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8420                 err = tg3_load_5701_a0_firmware_fix(tp);
8421                 if (err)
8422                         return err;
8423         }
8424
8425         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8426                 err = tg3_load_tso_firmware(tp);
8427                 if (err)
8428                         return err;
8429         }
8430
8431         tp->tx_mode = TX_MODE_ENABLE;
8432         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8433             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8434                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8435         tw32_f(MAC_TX_MODE, tp->tx_mode);
8436         udelay(100);
8437
8438         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8439                 u32 reg = MAC_RSS_INDIR_TBL_0;
8440                 u8 *ent = (u8 *)&val;
8441
8442                 /* Setup the indirection table */
8443                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8444                         int idx = i % sizeof(val);
8445
8446                         ent[idx] = i % (tp->irq_cnt - 1);
8447                         if (idx == sizeof(val) - 1) {
8448                                 tw32(reg, val);
8449                                 reg += 4;
8450                         }
8451                 }
8452
8453                 /* Setup the "secret" hash key. */
8454                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8455                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8456                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8457                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8458                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8459                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8460                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8461                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8462                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8463                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8464         }
8465
8466         tp->rx_mode = RX_MODE_ENABLE;
8467         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8468                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8469
8470         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8471                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8472                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8473                                RX_MODE_RSS_IPV6_HASH_EN |
8474                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8475                                RX_MODE_RSS_IPV4_HASH_EN |
8476                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8477
8478         tw32_f(MAC_RX_MODE, tp->rx_mode);
8479         udelay(10);
8480
8481         tw32(MAC_LED_CTRL, tp->led_ctrl);
8482
8483         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8484         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8485                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8486                 udelay(10);
8487         }
8488         tw32_f(MAC_RX_MODE, tp->rx_mode);
8489         udelay(10);
8490
8491         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8492                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8493                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8494                         /* Set drive transmission level to 1.2V  */
8495                         /* only if the signal pre-emphasis bit is not set  */
8496                         val = tr32(MAC_SERDES_CFG);
8497                         val &= 0xfffff000;
8498                         val |= 0x880;
8499                         tw32(MAC_SERDES_CFG, val);
8500                 }
8501                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8502                         tw32(MAC_SERDES_CFG, 0x616000);
8503         }
8504
8505         /* Prevent chip from dropping frames when flow control
8506          * is enabled.
8507          */
8508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8509                 val = 1;
8510         else
8511                 val = 2;
8512         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8513
8514         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8515             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8516                 /* Use hardware link auto-negotiation */
8517                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8518         }
8519
8520         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8521             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8522                 u32 tmp;
8523
8524                 tmp = tr32(SERDES_RX_CTRL);
8525                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8526                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8527                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8528                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8529         }
8530
8531         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8532                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8533                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8534                         tp->link_config.speed = tp->link_config.orig_speed;
8535                         tp->link_config.duplex = tp->link_config.orig_duplex;
8536                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8537                 }
8538
8539                 err = tg3_setup_phy(tp, 0);
8540                 if (err)
8541                         return err;
8542
8543                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8544                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8545                         u32 tmp;
8546
8547                         /* Clear CRC stats. */
8548                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8549                                 tg3_writephy(tp, MII_TG3_TEST1,
8550                                              tmp | MII_TG3_TEST1_CRC_EN);
8551                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8552                         }
8553                 }
8554         }
8555
8556         __tg3_set_rx_mode(tp->dev);
8557
8558         /* Initialize receive rules. */
8559         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8560         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8561         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8562         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8563
8564         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8565             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8566                 limit = 8;
8567         else
8568                 limit = 16;
8569         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8570                 limit -= 4;
8571         switch (limit) {
8572         case 16:
8573                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8574         case 15:
8575                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8576         case 14:
8577                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8578         case 13:
8579                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8580         case 12:
8581                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8582         case 11:
8583                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8584         case 10:
8585                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8586         case 9:
8587                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8588         case 8:
8589                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8590         case 7:
8591                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8592         case 6:
8593                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8594         case 5:
8595                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8596         case 4:
8597                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8598         case 3:
8599                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8600         case 2:
8601         case 1:
8602
8603         default:
8604                 break;
8605         }
8606
8607         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8608                 /* Write our heartbeat update interval to APE. */
8609                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8610                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8611
8612         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8613
8614         return 0;
8615 }
8616
8617 /* Called at device open time to get the chip ready for
8618  * packet processing.  Invoked with tp->lock held.
8619  */
8620 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8621 {
8622         tg3_switch_clocks(tp);
8623
8624         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8625
8626         return tg3_reset_hw(tp, reset_phy);
8627 }
8628
8629 #define TG3_STAT_ADD32(PSTAT, REG) \
8630 do {    u32 __val = tr32(REG); \
8631         (PSTAT)->low += __val; \
8632         if ((PSTAT)->low < __val) \
8633                 (PSTAT)->high += 1; \
8634 } while (0)
8635
8636 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8637 {
8638         struct tg3_hw_stats *sp = tp->hw_stats;
8639
8640         if (!netif_carrier_ok(tp->dev))
8641                 return;
8642
8643         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8644         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8645         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8646         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8647         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8648         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8649         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8650         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8651         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8652         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8653         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8654         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8655         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8656
8657         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8658         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8659         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8660         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8661         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8662         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8663         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8664         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8665         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8666         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8667         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8668         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8669         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8670         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8671
8672         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8673         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8674         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8675 }
8676
8677 static void tg3_timer(unsigned long __opaque)
8678 {
8679         struct tg3 *tp = (struct tg3 *) __opaque;
8680
8681         if (tp->irq_sync)
8682                 goto restart_timer;
8683
8684         spin_lock(&tp->lock);
8685
8686         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8687                 /* All of this garbage is because when using non-tagged
8688                  * IRQ status the mailbox/status_block protocol the chip
8689                  * uses with the cpu is race prone.
8690                  */
8691                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8692                         tw32(GRC_LOCAL_CTRL,
8693                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8694                 } else {
8695                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8696                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8697                 }
8698
8699                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8700                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8701                         spin_unlock(&tp->lock);
8702                         schedule_work(&tp->reset_task);
8703                         return;
8704                 }
8705         }
8706
8707         /* This part only runs once per second. */
8708         if (!--tp->timer_counter) {
8709                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8710                         tg3_periodic_fetch_stats(tp);
8711
8712                 if (tp->setlpicnt && !--tp->setlpicnt) {
8713                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8714                         tw32(TG3_CPMU_EEE_MODE,
8715                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8716                 }
8717
8718                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8719                         u32 mac_stat;
8720                         int phy_event;
8721
8722                         mac_stat = tr32(MAC_STATUS);
8723
8724                         phy_event = 0;
8725                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8726                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8727                                         phy_event = 1;
8728                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8729                                 phy_event = 1;
8730
8731                         if (phy_event)
8732                                 tg3_setup_phy(tp, 0);
8733                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8734                         u32 mac_stat = tr32(MAC_STATUS);
8735                         int need_setup = 0;
8736
8737                         if (netif_carrier_ok(tp->dev) &&
8738                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8739                                 need_setup = 1;
8740                         }
8741                         if (!netif_carrier_ok(tp->dev) &&
8742                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8743                                          MAC_STATUS_SIGNAL_DET))) {
8744                                 need_setup = 1;
8745                         }
8746                         if (need_setup) {
8747                                 if (!tp->serdes_counter) {
8748                                         tw32_f(MAC_MODE,
8749                                              (tp->mac_mode &
8750                                               ~MAC_MODE_PORT_MODE_MASK));
8751                                         udelay(40);
8752                                         tw32_f(MAC_MODE, tp->mac_mode);
8753                                         udelay(40);
8754                                 }
8755                                 tg3_setup_phy(tp, 0);
8756                         }
8757                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8758                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8759                         tg3_serdes_parallel_detect(tp);
8760                 }
8761
8762                 tp->timer_counter = tp->timer_multiplier;
8763         }
8764
8765         /* Heartbeat is only sent once every 2 seconds.
8766          *
8767          * The heartbeat is to tell the ASF firmware that the host
8768          * driver is still alive.  In the event that the OS crashes,
8769          * ASF needs to reset the hardware to free up the FIFO space
8770          * that may be filled with rx packets destined for the host.
8771          * If the FIFO is full, ASF will no longer function properly.
8772          *
8773          * Unintended resets have been reported on real time kernels
8774          * where the timer doesn't run on time.  Netpoll will also have
8775          * same problem.
8776          *
8777          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8778          * to check the ring condition when the heartbeat is expiring
8779          * before doing the reset.  This will prevent most unintended
8780          * resets.
8781          */
8782         if (!--tp->asf_counter) {
8783                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8784                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8785                         tg3_wait_for_event_ack(tp);
8786
8787                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8788                                       FWCMD_NICDRV_ALIVE3);
8789                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8790                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8791                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8792
8793                         tg3_generate_fw_event(tp);
8794                 }
8795                 tp->asf_counter = tp->asf_multiplier;
8796         }
8797
8798         spin_unlock(&tp->lock);
8799
8800 restart_timer:
8801         tp->timer.expires = jiffies + tp->timer_offset;
8802         add_timer(&tp->timer);
8803 }
8804
8805 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8806 {
8807         irq_handler_t fn;
8808         unsigned long flags;
8809         char *name;
8810         struct tg3_napi *tnapi = &tp->napi[irq_num];
8811
8812         if (tp->irq_cnt == 1)
8813                 name = tp->dev->name;
8814         else {
8815                 name = &tnapi->irq_lbl[0];
8816                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8817                 name[IFNAMSIZ-1] = 0;
8818         }
8819
8820         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8821                 fn = tg3_msi;
8822                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8823                         fn = tg3_msi_1shot;
8824                 flags = IRQF_SAMPLE_RANDOM;
8825         } else {
8826                 fn = tg3_interrupt;
8827                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8828                         fn = tg3_interrupt_tagged;
8829                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8830         }
8831
8832         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8833 }
8834
8835 static int tg3_test_interrupt(struct tg3 *tp)
8836 {
8837         struct tg3_napi *tnapi = &tp->napi[0];
8838         struct net_device *dev = tp->dev;
8839         int err, i, intr_ok = 0;
8840         u32 val;
8841
8842         if (!netif_running(dev))
8843                 return -ENODEV;
8844
8845         tg3_disable_ints(tp);
8846
8847         free_irq(tnapi->irq_vec, tnapi);
8848
8849         /*
8850          * Turn off MSI one shot mode.  Otherwise this test has no
8851          * observable way to know whether the interrupt was delivered.
8852          */
8853         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8854             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8855                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8856                 tw32(MSGINT_MODE, val);
8857         }
8858
8859         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8860                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8861         if (err)
8862                 return err;
8863
8864         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8865         tg3_enable_ints(tp);
8866
8867         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8868                tnapi->coal_now);
8869
8870         for (i = 0; i < 5; i++) {
8871                 u32 int_mbox, misc_host_ctrl;
8872
8873                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8874                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8875
8876                 if ((int_mbox != 0) ||
8877                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8878                         intr_ok = 1;
8879                         break;
8880                 }
8881
8882                 msleep(10);
8883         }
8884
8885         tg3_disable_ints(tp);
8886
8887         free_irq(tnapi->irq_vec, tnapi);
8888
8889         err = tg3_request_irq(tp, 0);
8890
8891         if (err)
8892                 return err;
8893
8894         if (intr_ok) {
8895                 /* Reenable MSI one shot mode. */
8896                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8897                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8898                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8899                         tw32(MSGINT_MODE, val);
8900                 }
8901                 return 0;
8902         }
8903
8904         return -EIO;
8905 }
8906
8907 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8908  * successfully restored
8909  */
8910 static int tg3_test_msi(struct tg3 *tp)
8911 {
8912         int err;
8913         u16 pci_cmd;
8914
8915         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8916                 return 0;
8917
8918         /* Turn off SERR reporting in case MSI terminates with Master
8919          * Abort.
8920          */
8921         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8922         pci_write_config_word(tp->pdev, PCI_COMMAND,
8923                               pci_cmd & ~PCI_COMMAND_SERR);
8924
8925         err = tg3_test_interrupt(tp);
8926
8927         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8928
8929         if (!err)
8930                 return 0;
8931
8932         /* other failures */
8933         if (err != -EIO)
8934                 return err;
8935
8936         /* MSI test failed, go back to INTx mode */
8937         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8938                     "to INTx mode. Please report this failure to the PCI "
8939                     "maintainer and include system chipset information\n");
8940
8941         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8942
8943         pci_disable_msi(tp->pdev);
8944
8945         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8946         tp->napi[0].irq_vec = tp->pdev->irq;
8947
8948         err = tg3_request_irq(tp, 0);
8949         if (err)
8950                 return err;
8951
8952         /* Need to reset the chip because the MSI cycle may have terminated
8953          * with Master Abort.
8954          */
8955         tg3_full_lock(tp, 1);
8956
8957         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8958         err = tg3_init_hw(tp, 1);
8959
8960         tg3_full_unlock(tp);
8961
8962         if (err)
8963                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8964
8965         return err;
8966 }
8967
8968 static int tg3_request_firmware(struct tg3 *tp)
8969 {
8970         const __be32 *fw_data;
8971
8972         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8973                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8974                            tp->fw_needed);
8975                 return -ENOENT;
8976         }
8977
8978         fw_data = (void *)tp->fw->data;
8979
8980         /* Firmware blob starts with version numbers, followed by
8981          * start address and _full_ length including BSS sections
8982          * (which must be longer than the actual data, of course
8983          */
8984
8985         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8986         if (tp->fw_len < (tp->fw->size - 12)) {
8987                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8988                            tp->fw_len, tp->fw_needed);
8989                 release_firmware(tp->fw);
8990                 tp->fw = NULL;
8991                 return -EINVAL;
8992         }
8993
8994         /* We no longer need firmware; we have it. */
8995         tp->fw_needed = NULL;
8996         return 0;
8997 }
8998
8999 static bool tg3_enable_msix(struct tg3 *tp)
9000 {
9001         int i, rc, cpus = num_online_cpus();
9002         struct msix_entry msix_ent[tp->irq_max];
9003
9004         if (cpus == 1)
9005                 /* Just fallback to the simpler MSI mode. */
9006                 return false;
9007
9008         /*
9009          * We want as many rx rings enabled as there are cpus.
9010          * The first MSIX vector only deals with link interrupts, etc,
9011          * so we add one to the number of vectors we are requesting.
9012          */
9013         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9014
9015         for (i = 0; i < tp->irq_max; i++) {
9016                 msix_ent[i].entry  = i;
9017                 msix_ent[i].vector = 0;
9018         }
9019
9020         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9021         if (rc < 0) {
9022                 return false;
9023         } else if (rc != 0) {
9024                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9025                         return false;
9026                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9027                               tp->irq_cnt, rc);
9028                 tp->irq_cnt = rc;
9029         }
9030
9031         for (i = 0; i < tp->irq_max; i++)
9032                 tp->napi[i].irq_vec = msix_ent[i].vector;
9033
9034         netif_set_real_num_tx_queues(tp->dev, 1);
9035         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9036         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9037                 pci_disable_msix(tp->pdev);
9038                 return false;
9039         }
9040         if (tp->irq_cnt > 1)
9041                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9042
9043         return true;
9044 }
9045
9046 static void tg3_ints_init(struct tg3 *tp)
9047 {
9048         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9049             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9050                 /* All MSI supporting chips should support tagged
9051                  * status.  Assert that this is the case.
9052                  */
9053                 netdev_warn(tp->dev,
9054                             "MSI without TAGGED_STATUS? Not using MSI\n");
9055                 goto defcfg;
9056         }
9057
9058         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9059                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9060         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9061                  pci_enable_msi(tp->pdev) == 0)
9062                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9063
9064         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9065                 u32 msi_mode = tr32(MSGINT_MODE);
9066                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9067                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9068                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9069         }
9070 defcfg:
9071         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9072                 tp->irq_cnt = 1;
9073                 tp->napi[0].irq_vec = tp->pdev->irq;
9074                 netif_set_real_num_tx_queues(tp->dev, 1);
9075                 netif_set_real_num_rx_queues(tp->dev, 1);
9076         }
9077 }
9078
9079 static void tg3_ints_fini(struct tg3 *tp)
9080 {
9081         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9082                 pci_disable_msix(tp->pdev);
9083         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9084                 pci_disable_msi(tp->pdev);
9085         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9086         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9087 }
9088
9089 static int tg3_open(struct net_device *dev)
9090 {
9091         struct tg3 *tp = netdev_priv(dev);
9092         int i, err;
9093
9094         if (tp->fw_needed) {
9095                 err = tg3_request_firmware(tp);
9096                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9097                         if (err)
9098                                 return err;
9099                 } else if (err) {
9100                         netdev_warn(tp->dev, "TSO capability disabled\n");
9101                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9102                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9103                         netdev_notice(tp->dev, "TSO capability restored\n");
9104                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9105                 }
9106         }
9107
9108         netif_carrier_off(tp->dev);
9109
9110         err = tg3_set_power_state(tp, PCI_D0);
9111         if (err)
9112                 return err;
9113
9114         tg3_full_lock(tp, 0);
9115
9116         tg3_disable_ints(tp);
9117         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9118
9119         tg3_full_unlock(tp);
9120
9121         /*
9122          * Setup interrupts first so we know how
9123          * many NAPI resources to allocate
9124          */
9125         tg3_ints_init(tp);
9126
9127         /* The placement of this call is tied
9128          * to the setup and use of Host TX descriptors.
9129          */
9130         err = tg3_alloc_consistent(tp);
9131         if (err)
9132                 goto err_out1;
9133
9134         tg3_napi_init(tp);
9135
9136         tg3_napi_enable(tp);
9137
9138         for (i = 0; i < tp->irq_cnt; i++) {
9139                 struct tg3_napi *tnapi = &tp->napi[i];
9140                 err = tg3_request_irq(tp, i);
9141                 if (err) {
9142                         for (i--; i >= 0; i--)
9143                                 free_irq(tnapi->irq_vec, tnapi);
9144                         break;
9145                 }
9146         }
9147
9148         if (err)
9149                 goto err_out2;
9150
9151         tg3_full_lock(tp, 0);
9152
9153         err = tg3_init_hw(tp, 1);
9154         if (err) {
9155                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9156                 tg3_free_rings(tp);
9157         } else {
9158                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9159                         tp->timer_offset = HZ;
9160                 else
9161                         tp->timer_offset = HZ / 10;
9162
9163                 BUG_ON(tp->timer_offset > HZ);
9164                 tp->timer_counter = tp->timer_multiplier =
9165                         (HZ / tp->timer_offset);
9166                 tp->asf_counter = tp->asf_multiplier =
9167                         ((HZ / tp->timer_offset) * 2);
9168
9169                 init_timer(&tp->timer);
9170                 tp->timer.expires = jiffies + tp->timer_offset;
9171                 tp->timer.data = (unsigned long) tp;
9172                 tp->timer.function = tg3_timer;
9173         }
9174
9175         tg3_full_unlock(tp);
9176
9177         if (err)
9178                 goto err_out3;
9179
9180         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9181                 err = tg3_test_msi(tp);
9182
9183                 if (err) {
9184                         tg3_full_lock(tp, 0);
9185                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9186                         tg3_free_rings(tp);
9187                         tg3_full_unlock(tp);
9188
9189                         goto err_out2;
9190                 }
9191
9192                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9193                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9194                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9195
9196                         tw32(PCIE_TRANSACTION_CFG,
9197                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9198                 }
9199         }
9200
9201         tg3_phy_start(tp);
9202
9203         tg3_full_lock(tp, 0);
9204
9205         add_timer(&tp->timer);
9206         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9207         tg3_enable_ints(tp);
9208
9209         tg3_full_unlock(tp);
9210
9211         netif_tx_start_all_queues(dev);
9212
9213         return 0;
9214
9215 err_out3:
9216         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9217                 struct tg3_napi *tnapi = &tp->napi[i];
9218                 free_irq(tnapi->irq_vec, tnapi);
9219         }
9220
9221 err_out2:
9222         tg3_napi_disable(tp);
9223         tg3_napi_fini(tp);
9224         tg3_free_consistent(tp);
9225
9226 err_out1:
9227         tg3_ints_fini(tp);
9228         return err;
9229 }
9230
9231 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9232                                                  struct rtnl_link_stats64 *);
9233 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9234
9235 static int tg3_close(struct net_device *dev)
9236 {
9237         int i;
9238         struct tg3 *tp = netdev_priv(dev);
9239
9240         tg3_napi_disable(tp);
9241         cancel_work_sync(&tp->reset_task);
9242
9243         netif_tx_stop_all_queues(dev);
9244
9245         del_timer_sync(&tp->timer);
9246
9247         tg3_phy_stop(tp);
9248
9249         tg3_full_lock(tp, 1);
9250
9251         tg3_disable_ints(tp);
9252
9253         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9254         tg3_free_rings(tp);
9255         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9256
9257         tg3_full_unlock(tp);
9258
9259         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9260                 struct tg3_napi *tnapi = &tp->napi[i];
9261                 free_irq(tnapi->irq_vec, tnapi);
9262         }
9263
9264         tg3_ints_fini(tp);
9265
9266         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9267
9268         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9269                sizeof(tp->estats_prev));
9270
9271         tg3_napi_fini(tp);
9272
9273         tg3_free_consistent(tp);
9274
9275         tg3_set_power_state(tp, PCI_D3hot);
9276
9277         netif_carrier_off(tp->dev);
9278
9279         return 0;
9280 }
9281
9282 static inline u64 get_stat64(tg3_stat64_t *val)
9283 {
9284        return ((u64)val->high << 32) | ((u64)val->low);
9285 }
9286
9287 static u64 calc_crc_errors(struct tg3 *tp)
9288 {
9289         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9290
9291         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9292             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9293              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9294                 u32 val;
9295
9296                 spin_lock_bh(&tp->lock);
9297                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9298                         tg3_writephy(tp, MII_TG3_TEST1,
9299                                      val | MII_TG3_TEST1_CRC_EN);
9300                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9301                 } else
9302                         val = 0;
9303                 spin_unlock_bh(&tp->lock);
9304
9305                 tp->phy_crc_errors += val;
9306
9307                 return tp->phy_crc_errors;
9308         }
9309
9310         return get_stat64(&hw_stats->rx_fcs_errors);
9311 }
9312
9313 #define ESTAT_ADD(member) \
9314         estats->member =        old_estats->member + \
9315                                 get_stat64(&hw_stats->member)
9316
9317 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9318 {
9319         struct tg3_ethtool_stats *estats = &tp->estats;
9320         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9321         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9322
9323         if (!hw_stats)
9324                 return old_estats;
9325
9326         ESTAT_ADD(rx_octets);
9327         ESTAT_ADD(rx_fragments);
9328         ESTAT_ADD(rx_ucast_packets);
9329         ESTAT_ADD(rx_mcast_packets);
9330         ESTAT_ADD(rx_bcast_packets);
9331         ESTAT_ADD(rx_fcs_errors);
9332         ESTAT_ADD(rx_align_errors);
9333         ESTAT_ADD(rx_xon_pause_rcvd);
9334         ESTAT_ADD(rx_xoff_pause_rcvd);
9335         ESTAT_ADD(rx_mac_ctrl_rcvd);
9336         ESTAT_ADD(rx_xoff_entered);
9337         ESTAT_ADD(rx_frame_too_long_errors);
9338         ESTAT_ADD(rx_jabbers);
9339         ESTAT_ADD(rx_undersize_packets);
9340         ESTAT_ADD(rx_in_length_errors);
9341         ESTAT_ADD(rx_out_length_errors);
9342         ESTAT_ADD(rx_64_or_less_octet_packets);
9343         ESTAT_ADD(rx_65_to_127_octet_packets);
9344         ESTAT_ADD(rx_128_to_255_octet_packets);
9345         ESTAT_ADD(rx_256_to_511_octet_packets);
9346         ESTAT_ADD(rx_512_to_1023_octet_packets);
9347         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9348         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9349         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9350         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9351         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9352
9353         ESTAT_ADD(tx_octets);
9354         ESTAT_ADD(tx_collisions);
9355         ESTAT_ADD(tx_xon_sent);
9356         ESTAT_ADD(tx_xoff_sent);
9357         ESTAT_ADD(tx_flow_control);
9358         ESTAT_ADD(tx_mac_errors);
9359         ESTAT_ADD(tx_single_collisions);
9360         ESTAT_ADD(tx_mult_collisions);
9361         ESTAT_ADD(tx_deferred);
9362         ESTAT_ADD(tx_excessive_collisions);
9363         ESTAT_ADD(tx_late_collisions);
9364         ESTAT_ADD(tx_collide_2times);
9365         ESTAT_ADD(tx_collide_3times);
9366         ESTAT_ADD(tx_collide_4times);
9367         ESTAT_ADD(tx_collide_5times);
9368         ESTAT_ADD(tx_collide_6times);
9369         ESTAT_ADD(tx_collide_7times);
9370         ESTAT_ADD(tx_collide_8times);
9371         ESTAT_ADD(tx_collide_9times);
9372         ESTAT_ADD(tx_collide_10times);
9373         ESTAT_ADD(tx_collide_11times);
9374         ESTAT_ADD(tx_collide_12times);
9375         ESTAT_ADD(tx_collide_13times);
9376         ESTAT_ADD(tx_collide_14times);
9377         ESTAT_ADD(tx_collide_15times);
9378         ESTAT_ADD(tx_ucast_packets);
9379         ESTAT_ADD(tx_mcast_packets);
9380         ESTAT_ADD(tx_bcast_packets);
9381         ESTAT_ADD(tx_carrier_sense_errors);
9382         ESTAT_ADD(tx_discards);
9383         ESTAT_ADD(tx_errors);
9384
9385         ESTAT_ADD(dma_writeq_full);
9386         ESTAT_ADD(dma_write_prioq_full);
9387         ESTAT_ADD(rxbds_empty);
9388         ESTAT_ADD(rx_discards);
9389         ESTAT_ADD(rx_errors);
9390         ESTAT_ADD(rx_threshold_hit);
9391
9392         ESTAT_ADD(dma_readq_full);
9393         ESTAT_ADD(dma_read_prioq_full);
9394         ESTAT_ADD(tx_comp_queue_full);
9395
9396         ESTAT_ADD(ring_set_send_prod_index);
9397         ESTAT_ADD(ring_status_update);
9398         ESTAT_ADD(nic_irqs);
9399         ESTAT_ADD(nic_avoided_irqs);
9400         ESTAT_ADD(nic_tx_threshold_hit);
9401
9402         return estats;
9403 }
9404
9405 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9406                                                  struct rtnl_link_stats64 *stats)
9407 {
9408         struct tg3 *tp = netdev_priv(dev);
9409         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9410         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9411
9412         if (!hw_stats)
9413                 return old_stats;
9414
9415         stats->rx_packets = old_stats->rx_packets +
9416                 get_stat64(&hw_stats->rx_ucast_packets) +
9417                 get_stat64(&hw_stats->rx_mcast_packets) +
9418                 get_stat64(&hw_stats->rx_bcast_packets);
9419
9420         stats->tx_packets = old_stats->tx_packets +
9421                 get_stat64(&hw_stats->tx_ucast_packets) +
9422                 get_stat64(&hw_stats->tx_mcast_packets) +
9423                 get_stat64(&hw_stats->tx_bcast_packets);
9424
9425         stats->rx_bytes = old_stats->rx_bytes +
9426                 get_stat64(&hw_stats->rx_octets);
9427         stats->tx_bytes = old_stats->tx_bytes +
9428                 get_stat64(&hw_stats->tx_octets);
9429
9430         stats->rx_errors = old_stats->rx_errors +
9431                 get_stat64(&hw_stats->rx_errors);
9432         stats->tx_errors = old_stats->tx_errors +
9433                 get_stat64(&hw_stats->tx_errors) +
9434                 get_stat64(&hw_stats->tx_mac_errors) +
9435                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9436                 get_stat64(&hw_stats->tx_discards);
9437
9438         stats->multicast = old_stats->multicast +
9439                 get_stat64(&hw_stats->rx_mcast_packets);
9440         stats->collisions = old_stats->collisions +
9441                 get_stat64(&hw_stats->tx_collisions);
9442
9443         stats->rx_length_errors = old_stats->rx_length_errors +
9444                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9445                 get_stat64(&hw_stats->rx_undersize_packets);
9446
9447         stats->rx_over_errors = old_stats->rx_over_errors +
9448                 get_stat64(&hw_stats->rxbds_empty);
9449         stats->rx_frame_errors = old_stats->rx_frame_errors +
9450                 get_stat64(&hw_stats->rx_align_errors);
9451         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9452                 get_stat64(&hw_stats->tx_discards);
9453         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9454                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9455
9456         stats->rx_crc_errors = old_stats->rx_crc_errors +
9457                 calc_crc_errors(tp);
9458
9459         stats->rx_missed_errors = old_stats->rx_missed_errors +
9460                 get_stat64(&hw_stats->rx_discards);
9461
9462         stats->rx_dropped = tp->rx_dropped;
9463
9464         return stats;
9465 }
9466
9467 static inline u32 calc_crc(unsigned char *buf, int len)
9468 {
9469         u32 reg;
9470         u32 tmp;
9471         int j, k;
9472
9473         reg = 0xffffffff;
9474
9475         for (j = 0; j < len; j++) {
9476                 reg ^= buf[j];
9477
9478                 for (k = 0; k < 8; k++) {
9479                         tmp = reg & 0x01;
9480
9481                         reg >>= 1;
9482
9483                         if (tmp)
9484                                 reg ^= 0xedb88320;
9485                 }
9486         }
9487
9488         return ~reg;
9489 }
9490
9491 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9492 {
9493         /* accept or reject all multicast frames */
9494         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9495         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9496         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9497         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9498 }
9499
9500 static void __tg3_set_rx_mode(struct net_device *dev)
9501 {
9502         struct tg3 *tp = netdev_priv(dev);
9503         u32 rx_mode;
9504
9505         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9506                                   RX_MODE_KEEP_VLAN_TAG);
9507
9508         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9509          * flag clear.
9510          */
9511 #if TG3_VLAN_TAG_USED
9512         if (!tp->vlgrp &&
9513             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9514                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9515 #else
9516         /* By definition, VLAN is disabled always in this
9517          * case.
9518          */
9519         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9520                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9521 #endif
9522
9523         if (dev->flags & IFF_PROMISC) {
9524                 /* Promiscuous mode. */
9525                 rx_mode |= RX_MODE_PROMISC;
9526         } else if (dev->flags & IFF_ALLMULTI) {
9527                 /* Accept all multicast. */
9528                 tg3_set_multi(tp, 1);
9529         } else if (netdev_mc_empty(dev)) {
9530                 /* Reject all multicast. */
9531                 tg3_set_multi(tp, 0);
9532         } else {
9533                 /* Accept one or more multicast(s). */
9534                 struct netdev_hw_addr *ha;
9535                 u32 mc_filter[4] = { 0, };
9536                 u32 regidx;
9537                 u32 bit;
9538                 u32 crc;
9539
9540                 netdev_for_each_mc_addr(ha, dev) {
9541                         crc = calc_crc(ha->addr, ETH_ALEN);
9542                         bit = ~crc & 0x7f;
9543                         regidx = (bit & 0x60) >> 5;
9544                         bit &= 0x1f;
9545                         mc_filter[regidx] |= (1 << bit);
9546                 }
9547
9548                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9549                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9550                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9551                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9552         }
9553
9554         if (rx_mode != tp->rx_mode) {
9555                 tp->rx_mode = rx_mode;
9556                 tw32_f(MAC_RX_MODE, rx_mode);
9557                 udelay(10);
9558         }
9559 }
9560
9561 static void tg3_set_rx_mode(struct net_device *dev)
9562 {
9563         struct tg3 *tp = netdev_priv(dev);
9564
9565         if (!netif_running(dev))
9566                 return;
9567
9568         tg3_full_lock(tp, 0);
9569         __tg3_set_rx_mode(dev);
9570         tg3_full_unlock(tp);
9571 }
9572
9573 #define TG3_REGDUMP_LEN         (32 * 1024)
9574
9575 static int tg3_get_regs_len(struct net_device *dev)
9576 {
9577         return TG3_REGDUMP_LEN;
9578 }
9579
9580 static void tg3_get_regs(struct net_device *dev,
9581                 struct ethtool_regs *regs, void *_p)
9582 {
9583         u32 *p = _p;
9584         struct tg3 *tp = netdev_priv(dev);
9585         u8 *orig_p = _p;
9586         int i;
9587
9588         regs->version = 0;
9589
9590         memset(p, 0, TG3_REGDUMP_LEN);
9591
9592         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9593                 return;
9594
9595         tg3_full_lock(tp, 0);
9596
9597 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9598 #define GET_REG32_LOOP(base, len)               \
9599 do {    p = (u32 *)(orig_p + (base));           \
9600         for (i = 0; i < len; i += 4)            \
9601                 __GET_REG32((base) + i);        \
9602 } while (0)
9603 #define GET_REG32_1(reg)                        \
9604 do {    p = (u32 *)(orig_p + (reg));            \
9605         __GET_REG32((reg));                     \
9606 } while (0)
9607
9608         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9609         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9610         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9611         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9612         GET_REG32_1(SNDDATAC_MODE);
9613         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9614         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9615         GET_REG32_1(SNDBDC_MODE);
9616         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9617         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9618         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9619         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9620         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9621         GET_REG32_1(RCVDCC_MODE);
9622         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9623         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9624         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9625         GET_REG32_1(MBFREE_MODE);
9626         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9627         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9628         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9629         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9630         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9631         GET_REG32_1(RX_CPU_MODE);
9632         GET_REG32_1(RX_CPU_STATE);
9633         GET_REG32_1(RX_CPU_PGMCTR);
9634         GET_REG32_1(RX_CPU_HWBKPT);
9635         GET_REG32_1(TX_CPU_MODE);
9636         GET_REG32_1(TX_CPU_STATE);
9637         GET_REG32_1(TX_CPU_PGMCTR);
9638         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9639         GET_REG32_LOOP(FTQ_RESET, 0x120);
9640         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9641         GET_REG32_1(DMAC_MODE);
9642         GET_REG32_LOOP(GRC_MODE, 0x4c);
9643         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9644                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9645
9646 #undef __GET_REG32
9647 #undef GET_REG32_LOOP
9648 #undef GET_REG32_1
9649
9650         tg3_full_unlock(tp);
9651 }
9652
9653 static int tg3_get_eeprom_len(struct net_device *dev)
9654 {
9655         struct tg3 *tp = netdev_priv(dev);
9656
9657         return tp->nvram_size;
9658 }
9659
9660 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9661 {
9662         struct tg3 *tp = netdev_priv(dev);
9663         int ret;
9664         u8  *pd;
9665         u32 i, offset, len, b_offset, b_count;
9666         __be32 val;
9667
9668         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9669                 return -EINVAL;
9670
9671         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9672                 return -EAGAIN;
9673
9674         offset = eeprom->offset;
9675         len = eeprom->len;
9676         eeprom->len = 0;
9677
9678         eeprom->magic = TG3_EEPROM_MAGIC;
9679
9680         if (offset & 3) {
9681                 /* adjustments to start on required 4 byte boundary */
9682                 b_offset = offset & 3;
9683                 b_count = 4 - b_offset;
9684                 if (b_count > len) {
9685                         /* i.e. offset=1 len=2 */
9686                         b_count = len;
9687                 }
9688                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9689                 if (ret)
9690                         return ret;
9691                 memcpy(data, ((char *)&val) + b_offset, b_count);
9692                 len -= b_count;
9693                 offset += b_count;
9694                 eeprom->len += b_count;
9695         }
9696
9697         /* read bytes upto the last 4 byte boundary */
9698         pd = &data[eeprom->len];
9699         for (i = 0; i < (len - (len & 3)); i += 4) {
9700                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9701                 if (ret) {
9702                         eeprom->len += i;
9703                         return ret;
9704                 }
9705                 memcpy(pd + i, &val, 4);
9706         }
9707         eeprom->len += i;
9708
9709         if (len & 3) {
9710                 /* read last bytes not ending on 4 byte boundary */
9711                 pd = &data[eeprom->len];
9712                 b_count = len & 3;
9713                 b_offset = offset + len - b_count;
9714                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9715                 if (ret)
9716                         return ret;
9717                 memcpy(pd, &val, b_count);
9718                 eeprom->len += b_count;
9719         }
9720         return 0;
9721 }
9722
9723 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9724
9725 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9726 {
9727         struct tg3 *tp = netdev_priv(dev);
9728         int ret;
9729         u32 offset, len, b_offset, odd_len;
9730         u8 *buf;
9731         __be32 start, end;
9732
9733         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9734                 return -EAGAIN;
9735
9736         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9737             eeprom->magic != TG3_EEPROM_MAGIC)
9738                 return -EINVAL;
9739
9740         offset = eeprom->offset;
9741         len = eeprom->len;
9742
9743         if ((b_offset = (offset & 3))) {
9744                 /* adjustments to start on required 4 byte boundary */
9745                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9746                 if (ret)
9747                         return ret;
9748                 len += b_offset;
9749                 offset &= ~3;
9750                 if (len < 4)
9751                         len = 4;
9752         }
9753
9754         odd_len = 0;
9755         if (len & 3) {
9756                 /* adjustments to end on required 4 byte boundary */
9757                 odd_len = 1;
9758                 len = (len + 3) & ~3;
9759                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9760                 if (ret)
9761                         return ret;
9762         }
9763
9764         buf = data;
9765         if (b_offset || odd_len) {
9766                 buf = kmalloc(len, GFP_KERNEL);
9767                 if (!buf)
9768                         return -ENOMEM;
9769                 if (b_offset)
9770                         memcpy(buf, &start, 4);
9771                 if (odd_len)
9772                         memcpy(buf+len-4, &end, 4);
9773                 memcpy(buf + b_offset, data, eeprom->len);
9774         }
9775
9776         ret = tg3_nvram_write_block(tp, offset, len, buf);
9777
9778         if (buf != data)
9779                 kfree(buf);
9780
9781         return ret;
9782 }
9783
9784 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9785 {
9786         struct tg3 *tp = netdev_priv(dev);
9787
9788         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9789                 struct phy_device *phydev;
9790                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9791                         return -EAGAIN;
9792                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9793                 return phy_ethtool_gset(phydev, cmd);
9794         }
9795
9796         cmd->supported = (SUPPORTED_Autoneg);
9797
9798         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9799                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9800                                    SUPPORTED_1000baseT_Full);
9801
9802         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9803                 cmd->supported |= (SUPPORTED_100baseT_Half |
9804                                   SUPPORTED_100baseT_Full |
9805                                   SUPPORTED_10baseT_Half |
9806                                   SUPPORTED_10baseT_Full |
9807                                   SUPPORTED_TP);
9808                 cmd->port = PORT_TP;
9809         } else {
9810                 cmd->supported |= SUPPORTED_FIBRE;
9811                 cmd->port = PORT_FIBRE;
9812         }
9813
9814         cmd->advertising = tp->link_config.advertising;
9815         if (netif_running(dev)) {
9816                 cmd->speed = tp->link_config.active_speed;
9817                 cmd->duplex = tp->link_config.active_duplex;
9818         } else {
9819                 cmd->speed = SPEED_INVALID;
9820                 cmd->duplex = DUPLEX_INVALID;
9821         }
9822         cmd->phy_address = tp->phy_addr;
9823         cmd->transceiver = XCVR_INTERNAL;
9824         cmd->autoneg = tp->link_config.autoneg;
9825         cmd->maxtxpkt = 0;
9826         cmd->maxrxpkt = 0;
9827         return 0;
9828 }
9829
9830 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9831 {
9832         struct tg3 *tp = netdev_priv(dev);
9833
9834         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9835                 struct phy_device *phydev;
9836                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9837                         return -EAGAIN;
9838                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9839                 return phy_ethtool_sset(phydev, cmd);
9840         }
9841
9842         if (cmd->autoneg != AUTONEG_ENABLE &&
9843             cmd->autoneg != AUTONEG_DISABLE)
9844                 return -EINVAL;
9845
9846         if (cmd->autoneg == AUTONEG_DISABLE &&
9847             cmd->duplex != DUPLEX_FULL &&
9848             cmd->duplex != DUPLEX_HALF)
9849                 return -EINVAL;
9850
9851         if (cmd->autoneg == AUTONEG_ENABLE) {
9852                 u32 mask = ADVERTISED_Autoneg |
9853                            ADVERTISED_Pause |
9854                            ADVERTISED_Asym_Pause;
9855
9856                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9857                         mask |= ADVERTISED_1000baseT_Half |
9858                                 ADVERTISED_1000baseT_Full;
9859
9860                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9861                         mask |= ADVERTISED_100baseT_Half |
9862                                 ADVERTISED_100baseT_Full |
9863                                 ADVERTISED_10baseT_Half |
9864                                 ADVERTISED_10baseT_Full |
9865                                 ADVERTISED_TP;
9866                 else
9867                         mask |= ADVERTISED_FIBRE;
9868
9869                 if (cmd->advertising & ~mask)
9870                         return -EINVAL;
9871
9872                 mask &= (ADVERTISED_1000baseT_Half |
9873                          ADVERTISED_1000baseT_Full |
9874                          ADVERTISED_100baseT_Half |
9875                          ADVERTISED_100baseT_Full |
9876                          ADVERTISED_10baseT_Half |
9877                          ADVERTISED_10baseT_Full);
9878
9879                 cmd->advertising &= mask;
9880         } else {
9881                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9882                         if (cmd->speed != SPEED_1000)
9883                                 return -EINVAL;
9884
9885                         if (cmd->duplex != DUPLEX_FULL)
9886                                 return -EINVAL;
9887                 } else {
9888                         if (cmd->speed != SPEED_100 &&
9889                             cmd->speed != SPEED_10)
9890                                 return -EINVAL;
9891                 }
9892         }
9893
9894         tg3_full_lock(tp, 0);
9895
9896         tp->link_config.autoneg = cmd->autoneg;
9897         if (cmd->autoneg == AUTONEG_ENABLE) {
9898                 tp->link_config.advertising = (cmd->advertising |
9899                                               ADVERTISED_Autoneg);
9900                 tp->link_config.speed = SPEED_INVALID;
9901                 tp->link_config.duplex = DUPLEX_INVALID;
9902         } else {
9903                 tp->link_config.advertising = 0;
9904                 tp->link_config.speed = cmd->speed;
9905                 tp->link_config.duplex = cmd->duplex;
9906         }
9907
9908         tp->link_config.orig_speed = tp->link_config.speed;
9909         tp->link_config.orig_duplex = tp->link_config.duplex;
9910         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9911
9912         if (netif_running(dev))
9913                 tg3_setup_phy(tp, 1);
9914
9915         tg3_full_unlock(tp);
9916
9917         return 0;
9918 }
9919
9920 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9921 {
9922         struct tg3 *tp = netdev_priv(dev);
9923
9924         strcpy(info->driver, DRV_MODULE_NAME);
9925         strcpy(info->version, DRV_MODULE_VERSION);
9926         strcpy(info->fw_version, tp->fw_ver);
9927         strcpy(info->bus_info, pci_name(tp->pdev));
9928 }
9929
9930 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9931 {
9932         struct tg3 *tp = netdev_priv(dev);
9933
9934         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9935             device_can_wakeup(&tp->pdev->dev))
9936                 wol->supported = WAKE_MAGIC;
9937         else
9938                 wol->supported = 0;
9939         wol->wolopts = 0;
9940         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9941             device_can_wakeup(&tp->pdev->dev))
9942                 wol->wolopts = WAKE_MAGIC;
9943         memset(&wol->sopass, 0, sizeof(wol->sopass));
9944 }
9945
9946 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9947 {
9948         struct tg3 *tp = netdev_priv(dev);
9949         struct device *dp = &tp->pdev->dev;
9950
9951         if (wol->wolopts & ~WAKE_MAGIC)
9952                 return -EINVAL;
9953         if ((wol->wolopts & WAKE_MAGIC) &&
9954             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9955                 return -EINVAL;
9956
9957         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9958
9959         spin_lock_bh(&tp->lock);
9960         if (device_may_wakeup(dp))
9961                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9962         else
9963                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9964         spin_unlock_bh(&tp->lock);
9965
9966
9967         return 0;
9968 }
9969
9970 static u32 tg3_get_msglevel(struct net_device *dev)
9971 {
9972         struct tg3 *tp = netdev_priv(dev);
9973         return tp->msg_enable;
9974 }
9975
9976 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9977 {
9978         struct tg3 *tp = netdev_priv(dev);
9979         tp->msg_enable = value;
9980 }
9981
9982 static int tg3_set_tso(struct net_device *dev, u32 value)
9983 {
9984         struct tg3 *tp = netdev_priv(dev);
9985
9986         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9987                 if (value)
9988                         return -EINVAL;
9989                 return 0;
9990         }
9991         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9992             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9993              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9994                 if (value) {
9995                         dev->features |= NETIF_F_TSO6;
9996                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9997                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9998                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9999                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10000                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10001                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10002                                 dev->features |= NETIF_F_TSO_ECN;
10003                 } else
10004                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10005         }
10006         return ethtool_op_set_tso(dev, value);
10007 }
10008
10009 static int tg3_nway_reset(struct net_device *dev)
10010 {
10011         struct tg3 *tp = netdev_priv(dev);
10012         int r;
10013
10014         if (!netif_running(dev))
10015                 return -EAGAIN;
10016
10017         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10018                 return -EINVAL;
10019
10020         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10021                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10022                         return -EAGAIN;
10023                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10024         } else {
10025                 u32 bmcr;
10026
10027                 spin_lock_bh(&tp->lock);
10028                 r = -EINVAL;
10029                 tg3_readphy(tp, MII_BMCR, &bmcr);
10030                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10031                     ((bmcr & BMCR_ANENABLE) ||
10032                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10033                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10034                                                    BMCR_ANENABLE);
10035                         r = 0;
10036                 }
10037                 spin_unlock_bh(&tp->lock);
10038         }
10039
10040         return r;
10041 }
10042
10043 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10044 {
10045         struct tg3 *tp = netdev_priv(dev);
10046
10047         ering->rx_max_pending = tp->rx_std_ring_mask;
10048         ering->rx_mini_max_pending = 0;
10049         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10050                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10051         else
10052                 ering->rx_jumbo_max_pending = 0;
10053
10054         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10055
10056         ering->rx_pending = tp->rx_pending;
10057         ering->rx_mini_pending = 0;
10058         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10059                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10060         else
10061                 ering->rx_jumbo_pending = 0;
10062
10063         ering->tx_pending = tp->napi[0].tx_pending;
10064 }
10065
10066 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10067 {
10068         struct tg3 *tp = netdev_priv(dev);
10069         int i, irq_sync = 0, err = 0;
10070
10071         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10072             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10073             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10074             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10075             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10076              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10077                 return -EINVAL;
10078
10079         if (netif_running(dev)) {
10080                 tg3_phy_stop(tp);
10081                 tg3_netif_stop(tp);
10082                 irq_sync = 1;
10083         }
10084
10085         tg3_full_lock(tp, irq_sync);
10086
10087         tp->rx_pending = ering->rx_pending;
10088
10089         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10090             tp->rx_pending > 63)
10091                 tp->rx_pending = 63;
10092         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10093
10094         for (i = 0; i < tp->irq_max; i++)
10095                 tp->napi[i].tx_pending = ering->tx_pending;
10096
10097         if (netif_running(dev)) {
10098                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10099                 err = tg3_restart_hw(tp, 1);
10100                 if (!err)
10101                         tg3_netif_start(tp);
10102         }
10103
10104         tg3_full_unlock(tp);
10105
10106         if (irq_sync && !err)
10107                 tg3_phy_start(tp);
10108
10109         return err;
10110 }
10111
10112 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10113 {
10114         struct tg3 *tp = netdev_priv(dev);
10115
10116         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10117
10118         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10119                 epause->rx_pause = 1;
10120         else
10121                 epause->rx_pause = 0;
10122
10123         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10124                 epause->tx_pause = 1;
10125         else
10126                 epause->tx_pause = 0;
10127 }
10128
10129 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10130 {
10131         struct tg3 *tp = netdev_priv(dev);
10132         int err = 0;
10133
10134         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10135                 u32 newadv;
10136                 struct phy_device *phydev;
10137
10138                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10139
10140                 if (!(phydev->supported & SUPPORTED_Pause) ||
10141                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10142                      (epause->rx_pause != epause->tx_pause)))
10143                         return -EINVAL;
10144
10145                 tp->link_config.flowctrl = 0;
10146                 if (epause->rx_pause) {
10147                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10148
10149                         if (epause->tx_pause) {
10150                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10151                                 newadv = ADVERTISED_Pause;
10152                         } else
10153                                 newadv = ADVERTISED_Pause |
10154                                          ADVERTISED_Asym_Pause;
10155                 } else if (epause->tx_pause) {
10156                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10157                         newadv = ADVERTISED_Asym_Pause;
10158                 } else
10159                         newadv = 0;
10160
10161                 if (epause->autoneg)
10162                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10163                 else
10164                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10165
10166                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10167                         u32 oldadv = phydev->advertising &
10168                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10169                         if (oldadv != newadv) {
10170                                 phydev->advertising &=
10171                                         ~(ADVERTISED_Pause |
10172                                           ADVERTISED_Asym_Pause);
10173                                 phydev->advertising |= newadv;
10174                                 if (phydev->autoneg) {
10175                                         /*
10176                                          * Always renegotiate the link to
10177                                          * inform our link partner of our
10178                                          * flow control settings, even if the
10179                                          * flow control is forced.  Let
10180                                          * tg3_adjust_link() do the final
10181                                          * flow control setup.
10182                                          */
10183                                         return phy_start_aneg(phydev);
10184                                 }
10185                         }
10186
10187                         if (!epause->autoneg)
10188                                 tg3_setup_flow_control(tp, 0, 0);
10189                 } else {
10190                         tp->link_config.orig_advertising &=
10191                                         ~(ADVERTISED_Pause |
10192                                           ADVERTISED_Asym_Pause);
10193                         tp->link_config.orig_advertising |= newadv;
10194                 }
10195         } else {
10196                 int irq_sync = 0;
10197
10198                 if (netif_running(dev)) {
10199                         tg3_netif_stop(tp);
10200                         irq_sync = 1;
10201                 }
10202
10203                 tg3_full_lock(tp, irq_sync);
10204
10205                 if (epause->autoneg)
10206                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10207                 else
10208                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10209                 if (epause->rx_pause)
10210                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10211                 else
10212                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10213                 if (epause->tx_pause)
10214                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10215                 else
10216                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10217
10218                 if (netif_running(dev)) {
10219                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10220                         err = tg3_restart_hw(tp, 1);
10221                         if (!err)
10222                                 tg3_netif_start(tp);
10223                 }
10224
10225                 tg3_full_unlock(tp);
10226         }
10227
10228         return err;
10229 }
10230
10231 static u32 tg3_get_rx_csum(struct net_device *dev)
10232 {
10233         struct tg3 *tp = netdev_priv(dev);
10234         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10235 }
10236
10237 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10238 {
10239         struct tg3 *tp = netdev_priv(dev);
10240
10241         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10242                 if (data != 0)
10243                         return -EINVAL;
10244                 return 0;
10245         }
10246
10247         spin_lock_bh(&tp->lock);
10248         if (data)
10249                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10250         else
10251                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10252         spin_unlock_bh(&tp->lock);
10253
10254         return 0;
10255 }
10256
10257 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10258 {
10259         struct tg3 *tp = netdev_priv(dev);
10260
10261         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10262                 if (data != 0)
10263                         return -EINVAL;
10264                 return 0;
10265         }
10266
10267         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10268                 ethtool_op_set_tx_ipv6_csum(dev, data);
10269         else
10270                 ethtool_op_set_tx_csum(dev, data);
10271
10272         return 0;
10273 }
10274
10275 static int tg3_get_sset_count(struct net_device *dev, int sset)
10276 {
10277         switch (sset) {
10278         case ETH_SS_TEST:
10279                 return TG3_NUM_TEST;
10280         case ETH_SS_STATS:
10281                 return TG3_NUM_STATS;
10282         default:
10283                 return -EOPNOTSUPP;
10284         }
10285 }
10286
10287 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10288 {
10289         switch (stringset) {
10290         case ETH_SS_STATS:
10291                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10292                 break;
10293         case ETH_SS_TEST:
10294                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10295                 break;
10296         default:
10297                 WARN_ON(1);     /* we need a WARN() */
10298                 break;
10299         }
10300 }
10301
10302 static int tg3_phys_id(struct net_device *dev, u32 data)
10303 {
10304         struct tg3 *tp = netdev_priv(dev);
10305         int i;
10306
10307         if (!netif_running(tp->dev))
10308                 return -EAGAIN;
10309
10310         if (data == 0)
10311                 data = UINT_MAX / 2;
10312
10313         for (i = 0; i < (data * 2); i++) {
10314                 if ((i % 2) == 0)
10315                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10316                                            LED_CTRL_1000MBPS_ON |
10317                                            LED_CTRL_100MBPS_ON |
10318                                            LED_CTRL_10MBPS_ON |
10319                                            LED_CTRL_TRAFFIC_OVERRIDE |
10320                                            LED_CTRL_TRAFFIC_BLINK |
10321                                            LED_CTRL_TRAFFIC_LED);
10322
10323                 else
10324                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10325                                            LED_CTRL_TRAFFIC_OVERRIDE);
10326
10327                 if (msleep_interruptible(500))
10328                         break;
10329         }
10330         tw32(MAC_LED_CTRL, tp->led_ctrl);
10331         return 0;
10332 }
10333
10334 static void tg3_get_ethtool_stats(struct net_device *dev,
10335                                    struct ethtool_stats *estats, u64 *tmp_stats)
10336 {
10337         struct tg3 *tp = netdev_priv(dev);
10338         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10339 }
10340
10341 #define NVRAM_TEST_SIZE 0x100
10342 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10343 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10344 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10345 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10346 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10347
10348 static int tg3_test_nvram(struct tg3 *tp)
10349 {
10350         u32 csum, magic;
10351         __be32 *buf;
10352         int i, j, k, err = 0, size;
10353
10354         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10355                 return 0;
10356
10357         if (tg3_nvram_read(tp, 0, &magic) != 0)
10358                 return -EIO;
10359
10360         if (magic == TG3_EEPROM_MAGIC)
10361                 size = NVRAM_TEST_SIZE;
10362         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10363                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10364                     TG3_EEPROM_SB_FORMAT_1) {
10365                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10366                         case TG3_EEPROM_SB_REVISION_0:
10367                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10368                                 break;
10369                         case TG3_EEPROM_SB_REVISION_2:
10370                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10371                                 break;
10372                         case TG3_EEPROM_SB_REVISION_3:
10373                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10374                                 break;
10375                         default:
10376                                 return 0;
10377                         }
10378                 } else
10379                         return 0;
10380         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10381                 size = NVRAM_SELFBOOT_HW_SIZE;
10382         else
10383                 return -EIO;
10384
10385         buf = kmalloc(size, GFP_KERNEL);
10386         if (buf == NULL)
10387                 return -ENOMEM;
10388
10389         err = -EIO;
10390         for (i = 0, j = 0; i < size; i += 4, j++) {
10391                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10392                 if (err)
10393                         break;
10394         }
10395         if (i < size)
10396                 goto out;
10397
10398         /* Selfboot format */
10399         magic = be32_to_cpu(buf[0]);
10400         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10401             TG3_EEPROM_MAGIC_FW) {
10402                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10403
10404                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10405                     TG3_EEPROM_SB_REVISION_2) {
10406                         /* For rev 2, the csum doesn't include the MBA. */
10407                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10408                                 csum8 += buf8[i];
10409                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10410                                 csum8 += buf8[i];
10411                 } else {
10412                         for (i = 0; i < size; i++)
10413                                 csum8 += buf8[i];
10414                 }
10415
10416                 if (csum8 == 0) {
10417                         err = 0;
10418                         goto out;
10419                 }
10420
10421                 err = -EIO;
10422                 goto out;
10423         }
10424
10425         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10426             TG3_EEPROM_MAGIC_HW) {
10427                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10428                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10429                 u8 *buf8 = (u8 *) buf;
10430
10431                 /* Separate the parity bits and the data bytes.  */
10432                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10433                         if ((i == 0) || (i == 8)) {
10434                                 int l;
10435                                 u8 msk;
10436
10437                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10438                                         parity[k++] = buf8[i] & msk;
10439                                 i++;
10440                         } else if (i == 16) {
10441                                 int l;
10442                                 u8 msk;
10443
10444                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10445                                         parity[k++] = buf8[i] & msk;
10446                                 i++;
10447
10448                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10449                                         parity[k++] = buf8[i] & msk;
10450                                 i++;
10451                         }
10452                         data[j++] = buf8[i];
10453                 }
10454
10455                 err = -EIO;
10456                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10457                         u8 hw8 = hweight8(data[i]);
10458
10459                         if ((hw8 & 0x1) && parity[i])
10460                                 goto out;
10461                         else if (!(hw8 & 0x1) && !parity[i])
10462                                 goto out;
10463                 }
10464                 err = 0;
10465                 goto out;
10466         }
10467
10468         /* Bootstrap checksum at offset 0x10 */
10469         csum = calc_crc((unsigned char *) buf, 0x10);
10470         if (csum != be32_to_cpu(buf[0x10/4]))
10471                 goto out;
10472
10473         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10474         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10475         if (csum != be32_to_cpu(buf[0xfc/4]))
10476                 goto out;
10477
10478         err = 0;
10479
10480 out:
10481         kfree(buf);
10482         return err;
10483 }
10484
10485 #define TG3_SERDES_TIMEOUT_SEC  2
10486 #define TG3_COPPER_TIMEOUT_SEC  6
10487
10488 static int tg3_test_link(struct tg3 *tp)
10489 {
10490         int i, max;
10491
10492         if (!netif_running(tp->dev))
10493                 return -ENODEV;
10494
10495         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10496                 max = TG3_SERDES_TIMEOUT_SEC;
10497         else
10498                 max = TG3_COPPER_TIMEOUT_SEC;
10499
10500         for (i = 0; i < max; i++) {
10501                 if (netif_carrier_ok(tp->dev))
10502                         return 0;
10503
10504                 if (msleep_interruptible(1000))
10505                         break;
10506         }
10507
10508         return -EIO;
10509 }
10510
10511 /* Only test the commonly used registers */
10512 static int tg3_test_registers(struct tg3 *tp)
10513 {
10514         int i, is_5705, is_5750;
10515         u32 offset, read_mask, write_mask, val, save_val, read_val;
10516         static struct {
10517                 u16 offset;
10518                 u16 flags;
10519 #define TG3_FL_5705     0x1
10520 #define TG3_FL_NOT_5705 0x2
10521 #define TG3_FL_NOT_5788 0x4
10522 #define TG3_FL_NOT_5750 0x8
10523                 u32 read_mask;
10524                 u32 write_mask;
10525         } reg_tbl[] = {
10526                 /* MAC Control Registers */
10527                 { MAC_MODE, TG3_FL_NOT_5705,
10528                         0x00000000, 0x00ef6f8c },
10529                 { MAC_MODE, TG3_FL_5705,
10530                         0x00000000, 0x01ef6b8c },
10531                 { MAC_STATUS, TG3_FL_NOT_5705,
10532                         0x03800107, 0x00000000 },
10533                 { MAC_STATUS, TG3_FL_5705,
10534                         0x03800100, 0x00000000 },
10535                 { MAC_ADDR_0_HIGH, 0x0000,
10536                         0x00000000, 0x0000ffff },
10537                 { MAC_ADDR_0_LOW, 0x0000,
10538                         0x00000000, 0xffffffff },
10539                 { MAC_RX_MTU_SIZE, 0x0000,
10540                         0x00000000, 0x0000ffff },
10541                 { MAC_TX_MODE, 0x0000,
10542                         0x00000000, 0x00000070 },
10543                 { MAC_TX_LENGTHS, 0x0000,
10544                         0x00000000, 0x00003fff },
10545                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10546                         0x00000000, 0x000007fc },
10547                 { MAC_RX_MODE, TG3_FL_5705,
10548                         0x00000000, 0x000007dc },
10549                 { MAC_HASH_REG_0, 0x0000,
10550                         0x00000000, 0xffffffff },
10551                 { MAC_HASH_REG_1, 0x0000,
10552                         0x00000000, 0xffffffff },
10553                 { MAC_HASH_REG_2, 0x0000,
10554                         0x00000000, 0xffffffff },
10555                 { MAC_HASH_REG_3, 0x0000,
10556                         0x00000000, 0xffffffff },
10557
10558                 /* Receive Data and Receive BD Initiator Control Registers. */
10559                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10560                         0x00000000, 0xffffffff },
10561                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10562                         0x00000000, 0xffffffff },
10563                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10564                         0x00000000, 0x00000003 },
10565                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10566                         0x00000000, 0xffffffff },
10567                 { RCVDBDI_STD_BD+0, 0x0000,
10568                         0x00000000, 0xffffffff },
10569                 { RCVDBDI_STD_BD+4, 0x0000,
10570                         0x00000000, 0xffffffff },
10571                 { RCVDBDI_STD_BD+8, 0x0000,
10572                         0x00000000, 0xffff0002 },
10573                 { RCVDBDI_STD_BD+0xc, 0x0000,
10574                         0x00000000, 0xffffffff },
10575
10576                 /* Receive BD Initiator Control Registers. */
10577                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10578                         0x00000000, 0xffffffff },
10579                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10580                         0x00000000, 0x000003ff },
10581                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10582                         0x00000000, 0xffffffff },
10583
10584                 /* Host Coalescing Control Registers. */
10585                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10586                         0x00000000, 0x00000004 },
10587                 { HOSTCC_MODE, TG3_FL_5705,
10588                         0x00000000, 0x000000f6 },
10589                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10590                         0x00000000, 0xffffffff },
10591                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10592                         0x00000000, 0x000003ff },
10593                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10594                         0x00000000, 0xffffffff },
10595                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10596                         0x00000000, 0x000003ff },
10597                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10598                         0x00000000, 0xffffffff },
10599                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10600                         0x00000000, 0x000000ff },
10601                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10602                         0x00000000, 0xffffffff },
10603                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10604                         0x00000000, 0x000000ff },
10605                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10606                         0x00000000, 0xffffffff },
10607                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10608                         0x00000000, 0xffffffff },
10609                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10610                         0x00000000, 0xffffffff },
10611                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10612                         0x00000000, 0x000000ff },
10613                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10614                         0x00000000, 0xffffffff },
10615                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10616                         0x00000000, 0x000000ff },
10617                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10618                         0x00000000, 0xffffffff },
10619                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10620                         0x00000000, 0xffffffff },
10621                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10622                         0x00000000, 0xffffffff },
10623                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10624                         0x00000000, 0xffffffff },
10625                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10626                         0x00000000, 0xffffffff },
10627                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10628                         0xffffffff, 0x00000000 },
10629                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10630                         0xffffffff, 0x00000000 },
10631
10632                 /* Buffer Manager Control Registers. */
10633                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10634                         0x00000000, 0x007fff80 },
10635                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10636                         0x00000000, 0x007fffff },
10637                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10638                         0x00000000, 0x0000003f },
10639                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10640                         0x00000000, 0x000001ff },
10641                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10642                         0x00000000, 0x000001ff },
10643                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10644                         0xffffffff, 0x00000000 },
10645                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10646                         0xffffffff, 0x00000000 },
10647
10648                 /* Mailbox Registers */
10649                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10650                         0x00000000, 0x000001ff },
10651                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10652                         0x00000000, 0x000001ff },
10653                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10654                         0x00000000, 0x000007ff },
10655                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10656                         0x00000000, 0x000001ff },
10657
10658                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10659         };
10660
10661         is_5705 = is_5750 = 0;
10662         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10663                 is_5705 = 1;
10664                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10665                         is_5750 = 1;
10666         }
10667
10668         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10669                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10670                         continue;
10671
10672                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10673                         continue;
10674
10675                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10676                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10677                         continue;
10678
10679                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10680                         continue;
10681
10682                 offset = (u32) reg_tbl[i].offset;
10683                 read_mask = reg_tbl[i].read_mask;
10684                 write_mask = reg_tbl[i].write_mask;
10685
10686                 /* Save the original register content */
10687                 save_val = tr32(offset);
10688
10689                 /* Determine the read-only value. */
10690                 read_val = save_val & read_mask;
10691
10692                 /* Write zero to the register, then make sure the read-only bits
10693                  * are not changed and the read/write bits are all zeros.
10694                  */
10695                 tw32(offset, 0);
10696
10697                 val = tr32(offset);
10698
10699                 /* Test the read-only and read/write bits. */
10700                 if (((val & read_mask) != read_val) || (val & write_mask))
10701                         goto out;
10702
10703                 /* Write ones to all the bits defined by RdMask and WrMask, then
10704                  * make sure the read-only bits are not changed and the
10705                  * read/write bits are all ones.
10706                  */
10707                 tw32(offset, read_mask | write_mask);
10708
10709                 val = tr32(offset);
10710
10711                 /* Test the read-only bits. */
10712                 if ((val & read_mask) != read_val)
10713                         goto out;
10714
10715                 /* Test the read/write bits. */
10716                 if ((val & write_mask) != write_mask)
10717                         goto out;
10718
10719                 tw32(offset, save_val);
10720         }
10721
10722         return 0;
10723
10724 out:
10725         if (netif_msg_hw(tp))
10726                 netdev_err(tp->dev,
10727                            "Register test failed at offset %x\n", offset);
10728         tw32(offset, save_val);
10729         return -EIO;
10730 }
10731
10732 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10733 {
10734         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10735         int i;
10736         u32 j;
10737
10738         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10739                 for (j = 0; j < len; j += 4) {
10740                         u32 val;
10741
10742                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10743                         tg3_read_mem(tp, offset + j, &val);
10744                         if (val != test_pattern[i])
10745                                 return -EIO;
10746                 }
10747         }
10748         return 0;
10749 }
10750
10751 static int tg3_test_memory(struct tg3 *tp)
10752 {
10753         static struct mem_entry {
10754                 u32 offset;
10755                 u32 len;
10756         } mem_tbl_570x[] = {
10757                 { 0x00000000, 0x00b50},
10758                 { 0x00002000, 0x1c000},
10759                 { 0xffffffff, 0x00000}
10760         }, mem_tbl_5705[] = {
10761                 { 0x00000100, 0x0000c},
10762                 { 0x00000200, 0x00008},
10763                 { 0x00004000, 0x00800},
10764                 { 0x00006000, 0x01000},
10765                 { 0x00008000, 0x02000},
10766                 { 0x00010000, 0x0e000},
10767                 { 0xffffffff, 0x00000}
10768         }, mem_tbl_5755[] = {
10769                 { 0x00000200, 0x00008},
10770                 { 0x00004000, 0x00800},
10771                 { 0x00006000, 0x00800},
10772                 { 0x00008000, 0x02000},
10773                 { 0x00010000, 0x0c000},
10774                 { 0xffffffff, 0x00000}
10775         }, mem_tbl_5906[] = {
10776                 { 0x00000200, 0x00008},
10777                 { 0x00004000, 0x00400},
10778                 { 0x00006000, 0x00400},
10779                 { 0x00008000, 0x01000},
10780                 { 0x00010000, 0x01000},
10781                 { 0xffffffff, 0x00000}
10782         }, mem_tbl_5717[] = {
10783                 { 0x00000200, 0x00008},
10784                 { 0x00010000, 0x0a000},
10785                 { 0x00020000, 0x13c00},
10786                 { 0xffffffff, 0x00000}
10787         }, mem_tbl_57765[] = {
10788                 { 0x00000200, 0x00008},
10789                 { 0x00004000, 0x00800},
10790                 { 0x00006000, 0x09800},
10791                 { 0x00010000, 0x0a000},
10792                 { 0xffffffff, 0x00000}
10793         };
10794         struct mem_entry *mem_tbl;
10795         int err = 0;
10796         int i;
10797
10798         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10799             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10800                 mem_tbl = mem_tbl_5717;
10801         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10802                 mem_tbl = mem_tbl_57765;
10803         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10804                 mem_tbl = mem_tbl_5755;
10805         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10806                 mem_tbl = mem_tbl_5906;
10807         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10808                 mem_tbl = mem_tbl_5705;
10809         else
10810                 mem_tbl = mem_tbl_570x;
10811
10812         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10813                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10814                 if (err)
10815                         break;
10816         }
10817
10818         return err;
10819 }
10820
10821 #define TG3_MAC_LOOPBACK        0
10822 #define TG3_PHY_LOOPBACK        1
10823
10824 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10825 {
10826         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10827         u32 desc_idx, coal_now;
10828         struct sk_buff *skb, *rx_skb;
10829         u8 *tx_data;
10830         dma_addr_t map;
10831         int num_pkts, tx_len, rx_len, i, err;
10832         struct tg3_rx_buffer_desc *desc;
10833         struct tg3_napi *tnapi, *rnapi;
10834         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10835
10836         tnapi = &tp->napi[0];
10837         rnapi = &tp->napi[0];
10838         if (tp->irq_cnt > 1) {
10839                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10840                         rnapi = &tp->napi[1];
10841                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10842                         tnapi = &tp->napi[1];
10843         }
10844         coal_now = tnapi->coal_now | rnapi->coal_now;
10845
10846         if (loopback_mode == TG3_MAC_LOOPBACK) {
10847                 /* HW errata - mac loopback fails in some cases on 5780.
10848                  * Normal traffic and PHY loopback are not affected by
10849                  * errata.
10850                  */
10851                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10852                         return 0;
10853
10854                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10855                            MAC_MODE_PORT_INT_LPBACK;
10856                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10857                         mac_mode |= MAC_MODE_LINK_POLARITY;
10858                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10859                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10860                 else
10861                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10862                 tw32(MAC_MODE, mac_mode);
10863         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10864                 u32 val;
10865
10866                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10867                         tg3_phy_fet_toggle_apd(tp, false);
10868                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10869                 } else
10870                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10871
10872                 tg3_phy_toggle_automdix(tp, 0);
10873
10874                 tg3_writephy(tp, MII_BMCR, val);
10875                 udelay(40);
10876
10877                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10878                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10879                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10880                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10881                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10882                         /* The write needs to be flushed for the AC131 */
10883                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10884                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10885                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10886                 } else
10887                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10888
10889                 /* reset to prevent losing 1st rx packet intermittently */
10890                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10891                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10892                         udelay(10);
10893                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10894                 }
10895                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10896                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10897                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10898                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10899                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10900                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10901                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10902                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10903                 }
10904                 tw32(MAC_MODE, mac_mode);
10905         } else {
10906                 return -EINVAL;
10907         }
10908
10909         err = -EIO;
10910
10911         tx_len = 1514;
10912         skb = netdev_alloc_skb(tp->dev, tx_len);
10913         if (!skb)
10914                 return -ENOMEM;
10915
10916         tx_data = skb_put(skb, tx_len);
10917         memcpy(tx_data, tp->dev->dev_addr, 6);
10918         memset(tx_data + 6, 0x0, 8);
10919
10920         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10921
10922         for (i = 14; i < tx_len; i++)
10923                 tx_data[i] = (u8) (i & 0xff);
10924
10925         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10926         if (pci_dma_mapping_error(tp->pdev, map)) {
10927                 dev_kfree_skb(skb);
10928                 return -EIO;
10929         }
10930
10931         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10932                rnapi->coal_now);
10933
10934         udelay(10);
10935
10936         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10937
10938         num_pkts = 0;
10939
10940         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10941
10942         tnapi->tx_prod++;
10943         num_pkts++;
10944
10945         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10946         tr32_mailbox(tnapi->prodmbox);
10947
10948         udelay(10);
10949
10950         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10951         for (i = 0; i < 35; i++) {
10952                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10953                        coal_now);
10954
10955                 udelay(10);
10956
10957                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10958                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10959                 if ((tx_idx == tnapi->tx_prod) &&
10960                     (rx_idx == (rx_start_idx + num_pkts)))
10961                         break;
10962         }
10963
10964         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10965         dev_kfree_skb(skb);
10966
10967         if (tx_idx != tnapi->tx_prod)
10968                 goto out;
10969
10970         if (rx_idx != rx_start_idx + num_pkts)
10971                 goto out;
10972
10973         desc = &rnapi->rx_rcb[rx_start_idx];
10974         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10975         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10976         if (opaque_key != RXD_OPAQUE_RING_STD)
10977                 goto out;
10978
10979         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10980             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10981                 goto out;
10982
10983         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10984         if (rx_len != tx_len)
10985                 goto out;
10986
10987         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10988
10989         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10990         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10991
10992         for (i = 14; i < tx_len; i++) {
10993                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10994                         goto out;
10995         }
10996         err = 0;
10997
10998         /* tg3_free_rings will unmap and free the rx_skb */
10999 out:
11000         return err;
11001 }
11002
11003 #define TG3_MAC_LOOPBACK_FAILED         1
11004 #define TG3_PHY_LOOPBACK_FAILED         2
11005 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11006                                          TG3_PHY_LOOPBACK_FAILED)
11007
11008 static int tg3_test_loopback(struct tg3 *tp)
11009 {
11010         int err = 0;
11011         u32 cpmuctrl = 0;
11012
11013         if (!netif_running(tp->dev))
11014                 return TG3_LOOPBACK_FAILED;
11015
11016         err = tg3_reset_hw(tp, 1);
11017         if (err)
11018                 return TG3_LOOPBACK_FAILED;
11019
11020         /* Turn off gphy autopowerdown. */
11021         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11022                 tg3_phy_toggle_apd(tp, false);
11023
11024         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11025                 int i;
11026                 u32 status;
11027
11028                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11029
11030                 /* Wait for up to 40 microseconds to acquire lock. */
11031                 for (i = 0; i < 4; i++) {
11032                         status = tr32(TG3_CPMU_MUTEX_GNT);
11033                         if (status == CPMU_MUTEX_GNT_DRIVER)
11034                                 break;
11035                         udelay(10);
11036                 }
11037
11038                 if (status != CPMU_MUTEX_GNT_DRIVER)
11039                         return TG3_LOOPBACK_FAILED;
11040
11041                 /* Turn off link-based power management. */
11042                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11043                 tw32(TG3_CPMU_CTRL,
11044                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11045                                   CPMU_CTRL_LINK_AWARE_MODE));
11046         }
11047
11048         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11049                 err |= TG3_MAC_LOOPBACK_FAILED;
11050
11051         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11052                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11053
11054                 /* Release the mutex */
11055                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11056         }
11057
11058         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11059             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11060                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11061                         err |= TG3_PHY_LOOPBACK_FAILED;
11062         }
11063
11064         /* Re-enable gphy autopowerdown. */
11065         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11066                 tg3_phy_toggle_apd(tp, true);
11067
11068         return err;
11069 }
11070
11071 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11072                           u64 *data)
11073 {
11074         struct tg3 *tp = netdev_priv(dev);
11075
11076         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11077                 tg3_set_power_state(tp, PCI_D0);
11078
11079         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11080
11081         if (tg3_test_nvram(tp) != 0) {
11082                 etest->flags |= ETH_TEST_FL_FAILED;
11083                 data[0] = 1;
11084         }
11085         if (tg3_test_link(tp) != 0) {
11086                 etest->flags |= ETH_TEST_FL_FAILED;
11087                 data[1] = 1;
11088         }
11089         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11090                 int err, err2 = 0, irq_sync = 0;
11091
11092                 if (netif_running(dev)) {
11093                         tg3_phy_stop(tp);
11094                         tg3_netif_stop(tp);
11095                         irq_sync = 1;
11096                 }
11097
11098                 tg3_full_lock(tp, irq_sync);
11099
11100                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11101                 err = tg3_nvram_lock(tp);
11102                 tg3_halt_cpu(tp, RX_CPU_BASE);
11103                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11104                         tg3_halt_cpu(tp, TX_CPU_BASE);
11105                 if (!err)
11106                         tg3_nvram_unlock(tp);
11107
11108                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11109                         tg3_phy_reset(tp);
11110
11111                 if (tg3_test_registers(tp) != 0) {
11112                         etest->flags |= ETH_TEST_FL_FAILED;
11113                         data[2] = 1;
11114                 }
11115                 if (tg3_test_memory(tp) != 0) {
11116                         etest->flags |= ETH_TEST_FL_FAILED;
11117                         data[3] = 1;
11118                 }
11119                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11120                         etest->flags |= ETH_TEST_FL_FAILED;
11121
11122                 tg3_full_unlock(tp);
11123
11124                 if (tg3_test_interrupt(tp) != 0) {
11125                         etest->flags |= ETH_TEST_FL_FAILED;
11126                         data[5] = 1;
11127                 }
11128
11129                 tg3_full_lock(tp, 0);
11130
11131                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11132                 if (netif_running(dev)) {
11133                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11134                         err2 = tg3_restart_hw(tp, 1);
11135                         if (!err2)
11136                                 tg3_netif_start(tp);
11137                 }
11138
11139                 tg3_full_unlock(tp);
11140
11141                 if (irq_sync && !err2)
11142                         tg3_phy_start(tp);
11143         }
11144         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11145                 tg3_set_power_state(tp, PCI_D3hot);
11146
11147 }
11148
11149 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11150 {
11151         struct mii_ioctl_data *data = if_mii(ifr);
11152         struct tg3 *tp = netdev_priv(dev);
11153         int err;
11154
11155         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11156                 struct phy_device *phydev;
11157                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11158                         return -EAGAIN;
11159                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11160                 return phy_mii_ioctl(phydev, ifr, cmd);
11161         }
11162
11163         switch (cmd) {
11164         case SIOCGMIIPHY:
11165                 data->phy_id = tp->phy_addr;
11166
11167                 /* fallthru */
11168         case SIOCGMIIREG: {
11169                 u32 mii_regval;
11170
11171                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11172                         break;                  /* We have no PHY */
11173
11174                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11175                         return -EAGAIN;
11176
11177                 spin_lock_bh(&tp->lock);
11178                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11179                 spin_unlock_bh(&tp->lock);
11180
11181                 data->val_out = mii_regval;
11182
11183                 return err;
11184         }
11185
11186         case SIOCSMIIREG:
11187                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11188                         break;                  /* We have no PHY */
11189
11190                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11191                         return -EAGAIN;
11192
11193                 spin_lock_bh(&tp->lock);
11194                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11195                 spin_unlock_bh(&tp->lock);
11196
11197                 return err;
11198
11199         default:
11200                 /* do nothing */
11201                 break;
11202         }
11203         return -EOPNOTSUPP;
11204 }
11205
11206 #if TG3_VLAN_TAG_USED
11207 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11208 {
11209         struct tg3 *tp = netdev_priv(dev);
11210
11211         if (!netif_running(dev)) {
11212                 tp->vlgrp = grp;
11213                 return;
11214         }
11215
11216         tg3_netif_stop(tp);
11217
11218         tg3_full_lock(tp, 0);
11219
11220         tp->vlgrp = grp;
11221
11222         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11223         __tg3_set_rx_mode(dev);
11224
11225         tg3_netif_start(tp);
11226
11227         tg3_full_unlock(tp);
11228 }
11229 #endif
11230
11231 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11232 {
11233         struct tg3 *tp = netdev_priv(dev);
11234
11235         memcpy(ec, &tp->coal, sizeof(*ec));
11236         return 0;
11237 }
11238
11239 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11240 {
11241         struct tg3 *tp = netdev_priv(dev);
11242         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11243         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11244
11245         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11246                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11247                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11248                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11249                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11250         }
11251
11252         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11253             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11254             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11255             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11256             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11257             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11258             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11259             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11260             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11261             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11262                 return -EINVAL;
11263
11264         /* No rx interrupts will be generated if both are zero */
11265         if ((ec->rx_coalesce_usecs == 0) &&
11266             (ec->rx_max_coalesced_frames == 0))
11267                 return -EINVAL;
11268
11269         /* No tx interrupts will be generated if both are zero */
11270         if ((ec->tx_coalesce_usecs == 0) &&
11271             (ec->tx_max_coalesced_frames == 0))
11272                 return -EINVAL;
11273
11274         /* Only copy relevant parameters, ignore all others. */
11275         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11276         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11277         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11278         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11279         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11280         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11281         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11282         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11283         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11284
11285         if (netif_running(dev)) {
11286                 tg3_full_lock(tp, 0);
11287                 __tg3_set_coalesce(tp, &tp->coal);
11288                 tg3_full_unlock(tp);
11289         }
11290         return 0;
11291 }
11292
11293 static const struct ethtool_ops tg3_ethtool_ops = {
11294         .get_settings           = tg3_get_settings,
11295         .set_settings           = tg3_set_settings,
11296         .get_drvinfo            = tg3_get_drvinfo,
11297         .get_regs_len           = tg3_get_regs_len,
11298         .get_regs               = tg3_get_regs,
11299         .get_wol                = tg3_get_wol,
11300         .set_wol                = tg3_set_wol,
11301         .get_msglevel           = tg3_get_msglevel,
11302         .set_msglevel           = tg3_set_msglevel,
11303         .nway_reset             = tg3_nway_reset,
11304         .get_link               = ethtool_op_get_link,
11305         .get_eeprom_len         = tg3_get_eeprom_len,
11306         .get_eeprom             = tg3_get_eeprom,
11307         .set_eeprom             = tg3_set_eeprom,
11308         .get_ringparam          = tg3_get_ringparam,
11309         .set_ringparam          = tg3_set_ringparam,
11310         .get_pauseparam         = tg3_get_pauseparam,
11311         .set_pauseparam         = tg3_set_pauseparam,
11312         .get_rx_csum            = tg3_get_rx_csum,
11313         .set_rx_csum            = tg3_set_rx_csum,
11314         .set_tx_csum            = tg3_set_tx_csum,
11315         .set_sg                 = ethtool_op_set_sg,
11316         .set_tso                = tg3_set_tso,
11317         .self_test              = tg3_self_test,
11318         .get_strings            = tg3_get_strings,
11319         .phys_id                = tg3_phys_id,
11320         .get_ethtool_stats      = tg3_get_ethtool_stats,
11321         .get_coalesce           = tg3_get_coalesce,
11322         .set_coalesce           = tg3_set_coalesce,
11323         .get_sset_count         = tg3_get_sset_count,
11324 };
11325
11326 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11327 {
11328         u32 cursize, val, magic;
11329
11330         tp->nvram_size = EEPROM_CHIP_SIZE;
11331
11332         if (tg3_nvram_read(tp, 0, &magic) != 0)
11333                 return;
11334
11335         if ((magic != TG3_EEPROM_MAGIC) &&
11336             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11337             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11338                 return;
11339
11340         /*
11341          * Size the chip by reading offsets at increasing powers of two.
11342          * When we encounter our validation signature, we know the addressing
11343          * has wrapped around, and thus have our chip size.
11344          */
11345         cursize = 0x10;
11346
11347         while (cursize < tp->nvram_size) {
11348                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11349                         return;
11350
11351                 if (val == magic)
11352                         break;
11353
11354                 cursize <<= 1;
11355         }
11356
11357         tp->nvram_size = cursize;
11358 }
11359
11360 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11361 {
11362         u32 val;
11363
11364         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11365             tg3_nvram_read(tp, 0, &val) != 0)
11366                 return;
11367
11368         /* Selfboot format */
11369         if (val != TG3_EEPROM_MAGIC) {
11370                 tg3_get_eeprom_size(tp);
11371                 return;
11372         }
11373
11374         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11375                 if (val != 0) {
11376                         /* This is confusing.  We want to operate on the
11377                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11378                          * call will read from NVRAM and byteswap the data
11379                          * according to the byteswapping settings for all
11380                          * other register accesses.  This ensures the data we
11381                          * want will always reside in the lower 16-bits.
11382                          * However, the data in NVRAM is in LE format, which
11383                          * means the data from the NVRAM read will always be
11384                          * opposite the endianness of the CPU.  The 16-bit
11385                          * byteswap then brings the data to CPU endianness.
11386                          */
11387                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11388                         return;
11389                 }
11390         }
11391         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11392 }
11393
11394 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11395 {
11396         u32 nvcfg1;
11397
11398         nvcfg1 = tr32(NVRAM_CFG1);
11399         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11400                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11401         } else {
11402                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11403                 tw32(NVRAM_CFG1, nvcfg1);
11404         }
11405
11406         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11407             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11408                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11409                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11410                         tp->nvram_jedecnum = JEDEC_ATMEL;
11411                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11412                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11413                         break;
11414                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11415                         tp->nvram_jedecnum = JEDEC_ATMEL;
11416                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11417                         break;
11418                 case FLASH_VENDOR_ATMEL_EEPROM:
11419                         tp->nvram_jedecnum = JEDEC_ATMEL;
11420                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11421                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11422                         break;
11423                 case FLASH_VENDOR_ST:
11424                         tp->nvram_jedecnum = JEDEC_ST;
11425                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11426                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427                         break;
11428                 case FLASH_VENDOR_SAIFUN:
11429                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11430                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11431                         break;
11432                 case FLASH_VENDOR_SST_SMALL:
11433                 case FLASH_VENDOR_SST_LARGE:
11434                         tp->nvram_jedecnum = JEDEC_SST;
11435                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11436                         break;
11437                 }
11438         } else {
11439                 tp->nvram_jedecnum = JEDEC_ATMEL;
11440                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11441                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11442         }
11443 }
11444
11445 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11446 {
11447         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11448         case FLASH_5752PAGE_SIZE_256:
11449                 tp->nvram_pagesize = 256;
11450                 break;
11451         case FLASH_5752PAGE_SIZE_512:
11452                 tp->nvram_pagesize = 512;
11453                 break;
11454         case FLASH_5752PAGE_SIZE_1K:
11455                 tp->nvram_pagesize = 1024;
11456                 break;
11457         case FLASH_5752PAGE_SIZE_2K:
11458                 tp->nvram_pagesize = 2048;
11459                 break;
11460         case FLASH_5752PAGE_SIZE_4K:
11461                 tp->nvram_pagesize = 4096;
11462                 break;
11463         case FLASH_5752PAGE_SIZE_264:
11464                 tp->nvram_pagesize = 264;
11465                 break;
11466         case FLASH_5752PAGE_SIZE_528:
11467                 tp->nvram_pagesize = 528;
11468                 break;
11469         }
11470 }
11471
11472 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11473 {
11474         u32 nvcfg1;
11475
11476         nvcfg1 = tr32(NVRAM_CFG1);
11477
11478         /* NVRAM protection for TPM */
11479         if (nvcfg1 & (1 << 27))
11480                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11481
11482         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11483         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11484         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11485                 tp->nvram_jedecnum = JEDEC_ATMEL;
11486                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11487                 break;
11488         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11489                 tp->nvram_jedecnum = JEDEC_ATMEL;
11490                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11491                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11492                 break;
11493         case FLASH_5752VENDOR_ST_M45PE10:
11494         case FLASH_5752VENDOR_ST_M45PE20:
11495         case FLASH_5752VENDOR_ST_M45PE40:
11496                 tp->nvram_jedecnum = JEDEC_ST;
11497                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11498                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11499                 break;
11500         }
11501
11502         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11503                 tg3_nvram_get_pagesize(tp, nvcfg1);
11504         } else {
11505                 /* For eeprom, set pagesize to maximum eeprom size */
11506                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11507
11508                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11509                 tw32(NVRAM_CFG1, nvcfg1);
11510         }
11511 }
11512
11513 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11514 {
11515         u32 nvcfg1, protect = 0;
11516
11517         nvcfg1 = tr32(NVRAM_CFG1);
11518
11519         /* NVRAM protection for TPM */
11520         if (nvcfg1 & (1 << 27)) {
11521                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11522                 protect = 1;
11523         }
11524
11525         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11526         switch (nvcfg1) {
11527         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11528         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11529         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11530         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11531                 tp->nvram_jedecnum = JEDEC_ATMEL;
11532                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11533                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11534                 tp->nvram_pagesize = 264;
11535                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11536                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11537                         tp->nvram_size = (protect ? 0x3e200 :
11538                                           TG3_NVRAM_SIZE_512KB);
11539                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11540                         tp->nvram_size = (protect ? 0x1f200 :
11541                                           TG3_NVRAM_SIZE_256KB);
11542                 else
11543                         tp->nvram_size = (protect ? 0x1f200 :
11544                                           TG3_NVRAM_SIZE_128KB);
11545                 break;
11546         case FLASH_5752VENDOR_ST_M45PE10:
11547         case FLASH_5752VENDOR_ST_M45PE20:
11548         case FLASH_5752VENDOR_ST_M45PE40:
11549                 tp->nvram_jedecnum = JEDEC_ST;
11550                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11551                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11552                 tp->nvram_pagesize = 256;
11553                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11554                         tp->nvram_size = (protect ?
11555                                           TG3_NVRAM_SIZE_64KB :
11556                                           TG3_NVRAM_SIZE_128KB);
11557                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11558                         tp->nvram_size = (protect ?
11559                                           TG3_NVRAM_SIZE_64KB :
11560                                           TG3_NVRAM_SIZE_256KB);
11561                 else
11562                         tp->nvram_size = (protect ?
11563                                           TG3_NVRAM_SIZE_128KB :
11564                                           TG3_NVRAM_SIZE_512KB);
11565                 break;
11566         }
11567 }
11568
11569 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11570 {
11571         u32 nvcfg1;
11572
11573         nvcfg1 = tr32(NVRAM_CFG1);
11574
11575         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11576         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11577         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11578         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11579         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11580                 tp->nvram_jedecnum = JEDEC_ATMEL;
11581                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11582                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11583
11584                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11585                 tw32(NVRAM_CFG1, nvcfg1);
11586                 break;
11587         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11588         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11589         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11590         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11591                 tp->nvram_jedecnum = JEDEC_ATMEL;
11592                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11593                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11594                 tp->nvram_pagesize = 264;
11595                 break;
11596         case FLASH_5752VENDOR_ST_M45PE10:
11597         case FLASH_5752VENDOR_ST_M45PE20:
11598         case FLASH_5752VENDOR_ST_M45PE40:
11599                 tp->nvram_jedecnum = JEDEC_ST;
11600                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11601                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11602                 tp->nvram_pagesize = 256;
11603                 break;
11604         }
11605 }
11606
11607 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11608 {
11609         u32 nvcfg1, protect = 0;
11610
11611         nvcfg1 = tr32(NVRAM_CFG1);
11612
11613         /* NVRAM protection for TPM */
11614         if (nvcfg1 & (1 << 27)) {
11615                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11616                 protect = 1;
11617         }
11618
11619         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11620         switch (nvcfg1) {
11621         case FLASH_5761VENDOR_ATMEL_ADB021D:
11622         case FLASH_5761VENDOR_ATMEL_ADB041D:
11623         case FLASH_5761VENDOR_ATMEL_ADB081D:
11624         case FLASH_5761VENDOR_ATMEL_ADB161D:
11625         case FLASH_5761VENDOR_ATMEL_MDB021D:
11626         case FLASH_5761VENDOR_ATMEL_MDB041D:
11627         case FLASH_5761VENDOR_ATMEL_MDB081D:
11628         case FLASH_5761VENDOR_ATMEL_MDB161D:
11629                 tp->nvram_jedecnum = JEDEC_ATMEL;
11630                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11631                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11632                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11633                 tp->nvram_pagesize = 256;
11634                 break;
11635         case FLASH_5761VENDOR_ST_A_M45PE20:
11636         case FLASH_5761VENDOR_ST_A_M45PE40:
11637         case FLASH_5761VENDOR_ST_A_M45PE80:
11638         case FLASH_5761VENDOR_ST_A_M45PE16:
11639         case FLASH_5761VENDOR_ST_M_M45PE20:
11640         case FLASH_5761VENDOR_ST_M_M45PE40:
11641         case FLASH_5761VENDOR_ST_M_M45PE80:
11642         case FLASH_5761VENDOR_ST_M_M45PE16:
11643                 tp->nvram_jedecnum = JEDEC_ST;
11644                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11645                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11646                 tp->nvram_pagesize = 256;
11647                 break;
11648         }
11649
11650         if (protect) {
11651                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11652         } else {
11653                 switch (nvcfg1) {
11654                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11655                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11656                 case FLASH_5761VENDOR_ST_A_M45PE16:
11657                 case FLASH_5761VENDOR_ST_M_M45PE16:
11658                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11659                         break;
11660                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11661                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11662                 case FLASH_5761VENDOR_ST_A_M45PE80:
11663                 case FLASH_5761VENDOR_ST_M_M45PE80:
11664                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11665                         break;
11666                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11667                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11668                 case FLASH_5761VENDOR_ST_A_M45PE40:
11669                 case FLASH_5761VENDOR_ST_M_M45PE40:
11670                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11671                         break;
11672                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11673                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11674                 case FLASH_5761VENDOR_ST_A_M45PE20:
11675                 case FLASH_5761VENDOR_ST_M_M45PE20:
11676                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11677                         break;
11678                 }
11679         }
11680 }
11681
11682 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11683 {
11684         tp->nvram_jedecnum = JEDEC_ATMEL;
11685         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11686         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11687 }
11688
11689 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11690 {
11691         u32 nvcfg1;
11692
11693         nvcfg1 = tr32(NVRAM_CFG1);
11694
11695         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11696         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11697         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11698                 tp->nvram_jedecnum = JEDEC_ATMEL;
11699                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11700                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11701
11702                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11703                 tw32(NVRAM_CFG1, nvcfg1);
11704                 return;
11705         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11706         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11707         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11708         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11709         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11710         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11711         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11712                 tp->nvram_jedecnum = JEDEC_ATMEL;
11713                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11714                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11715
11716                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11717                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11718                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11719                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11720                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11721                         break;
11722                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11723                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11724                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11725                         break;
11726                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11727                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11728                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11729                         break;
11730                 }
11731                 break;
11732         case FLASH_5752VENDOR_ST_M45PE10:
11733         case FLASH_5752VENDOR_ST_M45PE20:
11734         case FLASH_5752VENDOR_ST_M45PE40:
11735                 tp->nvram_jedecnum = JEDEC_ST;
11736                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11737                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11738
11739                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11740                 case FLASH_5752VENDOR_ST_M45PE10:
11741                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11742                         break;
11743                 case FLASH_5752VENDOR_ST_M45PE20:
11744                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11745                         break;
11746                 case FLASH_5752VENDOR_ST_M45PE40:
11747                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11748                         break;
11749                 }
11750                 break;
11751         default:
11752                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11753                 return;
11754         }
11755
11756         tg3_nvram_get_pagesize(tp, nvcfg1);
11757         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11758                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11759 }
11760
11761
11762 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11763 {
11764         u32 nvcfg1;
11765
11766         nvcfg1 = tr32(NVRAM_CFG1);
11767
11768         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11769         case FLASH_5717VENDOR_ATMEL_EEPROM:
11770         case FLASH_5717VENDOR_MICRO_EEPROM:
11771                 tp->nvram_jedecnum = JEDEC_ATMEL;
11772                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11773                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11774
11775                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11776                 tw32(NVRAM_CFG1, nvcfg1);
11777                 return;
11778         case FLASH_5717VENDOR_ATMEL_MDB011D:
11779         case FLASH_5717VENDOR_ATMEL_ADB011B:
11780         case FLASH_5717VENDOR_ATMEL_ADB011D:
11781         case FLASH_5717VENDOR_ATMEL_MDB021D:
11782         case FLASH_5717VENDOR_ATMEL_ADB021B:
11783         case FLASH_5717VENDOR_ATMEL_ADB021D:
11784         case FLASH_5717VENDOR_ATMEL_45USPT:
11785                 tp->nvram_jedecnum = JEDEC_ATMEL;
11786                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11787                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11788
11789                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11790                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11791                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11792                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11793                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11794                         break;
11795                 default:
11796                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11797                         break;
11798                 }
11799                 break;
11800         case FLASH_5717VENDOR_ST_M_M25PE10:
11801         case FLASH_5717VENDOR_ST_A_M25PE10:
11802         case FLASH_5717VENDOR_ST_M_M45PE10:
11803         case FLASH_5717VENDOR_ST_A_M45PE10:
11804         case FLASH_5717VENDOR_ST_M_M25PE20:
11805         case FLASH_5717VENDOR_ST_A_M25PE20:
11806         case FLASH_5717VENDOR_ST_M_M45PE20:
11807         case FLASH_5717VENDOR_ST_A_M45PE20:
11808         case FLASH_5717VENDOR_ST_25USPT:
11809         case FLASH_5717VENDOR_ST_45USPT:
11810                 tp->nvram_jedecnum = JEDEC_ST;
11811                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11812                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11813
11814                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11815                 case FLASH_5717VENDOR_ST_M_M25PE20:
11816                 case FLASH_5717VENDOR_ST_A_M25PE20:
11817                 case FLASH_5717VENDOR_ST_M_M45PE20:
11818                 case FLASH_5717VENDOR_ST_A_M45PE20:
11819                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11820                         break;
11821                 default:
11822                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11823                         break;
11824                 }
11825                 break;
11826         default:
11827                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11828                 return;
11829         }
11830
11831         tg3_nvram_get_pagesize(tp, nvcfg1);
11832         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11833                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11834 }
11835
11836 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11837 static void __devinit tg3_nvram_init(struct tg3 *tp)
11838 {
11839         tw32_f(GRC_EEPROM_ADDR,
11840              (EEPROM_ADDR_FSM_RESET |
11841               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11842                EEPROM_ADDR_CLKPERD_SHIFT)));
11843
11844         msleep(1);
11845
11846         /* Enable seeprom accesses. */
11847         tw32_f(GRC_LOCAL_CTRL,
11848              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11849         udelay(100);
11850
11851         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11852             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11853                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11854
11855                 if (tg3_nvram_lock(tp)) {
11856                         netdev_warn(tp->dev,
11857                                     "Cannot get nvram lock, %s failed\n",
11858                                     __func__);
11859                         return;
11860                 }
11861                 tg3_enable_nvram_access(tp);
11862
11863                 tp->nvram_size = 0;
11864
11865                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11866                         tg3_get_5752_nvram_info(tp);
11867                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11868                         tg3_get_5755_nvram_info(tp);
11869                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11870                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11871                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11872                         tg3_get_5787_nvram_info(tp);
11873                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11874                         tg3_get_5761_nvram_info(tp);
11875                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11876                         tg3_get_5906_nvram_info(tp);
11877                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11878                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11879                         tg3_get_57780_nvram_info(tp);
11880                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11881                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11882                         tg3_get_5717_nvram_info(tp);
11883                 else
11884                         tg3_get_nvram_info(tp);
11885
11886                 if (tp->nvram_size == 0)
11887                         tg3_get_nvram_size(tp);
11888
11889                 tg3_disable_nvram_access(tp);
11890                 tg3_nvram_unlock(tp);
11891
11892         } else {
11893                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11894
11895                 tg3_get_eeprom_size(tp);
11896         }
11897 }
11898
11899 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11900                                     u32 offset, u32 len, u8 *buf)
11901 {
11902         int i, j, rc = 0;
11903         u32 val;
11904
11905         for (i = 0; i < len; i += 4) {
11906                 u32 addr;
11907                 __be32 data;
11908
11909                 addr = offset + i;
11910
11911                 memcpy(&data, buf + i, 4);
11912
11913                 /*
11914                  * The SEEPROM interface expects the data to always be opposite
11915                  * the native endian format.  We accomplish this by reversing
11916                  * all the operations that would have been performed on the
11917                  * data from a call to tg3_nvram_read_be32().
11918                  */
11919                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11920
11921                 val = tr32(GRC_EEPROM_ADDR);
11922                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11923
11924                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11925                         EEPROM_ADDR_READ);
11926                 tw32(GRC_EEPROM_ADDR, val |
11927                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11928                         (addr & EEPROM_ADDR_ADDR_MASK) |
11929                         EEPROM_ADDR_START |
11930                         EEPROM_ADDR_WRITE);
11931
11932                 for (j = 0; j < 1000; j++) {
11933                         val = tr32(GRC_EEPROM_ADDR);
11934
11935                         if (val & EEPROM_ADDR_COMPLETE)
11936                                 break;
11937                         msleep(1);
11938                 }
11939                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11940                         rc = -EBUSY;
11941                         break;
11942                 }
11943         }
11944
11945         return rc;
11946 }
11947
11948 /* offset and length are dword aligned */
11949 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11950                 u8 *buf)
11951 {
11952         int ret = 0;
11953         u32 pagesize = tp->nvram_pagesize;
11954         u32 pagemask = pagesize - 1;
11955         u32 nvram_cmd;
11956         u8 *tmp;
11957
11958         tmp = kmalloc(pagesize, GFP_KERNEL);
11959         if (tmp == NULL)
11960                 return -ENOMEM;
11961
11962         while (len) {
11963                 int j;
11964                 u32 phy_addr, page_off, size;
11965
11966                 phy_addr = offset & ~pagemask;
11967
11968                 for (j = 0; j < pagesize; j += 4) {
11969                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11970                                                   (__be32 *) (tmp + j));
11971                         if (ret)
11972                                 break;
11973                 }
11974                 if (ret)
11975                         break;
11976
11977                 page_off = offset & pagemask;
11978                 size = pagesize;
11979                 if (len < size)
11980                         size = len;
11981
11982                 len -= size;
11983
11984                 memcpy(tmp + page_off, buf, size);
11985
11986                 offset = offset + (pagesize - page_off);
11987
11988                 tg3_enable_nvram_access(tp);
11989
11990                 /*
11991                  * Before we can erase the flash page, we need
11992                  * to issue a special "write enable" command.
11993                  */
11994                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11995
11996                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11997                         break;
11998
11999                 /* Erase the target page */
12000                 tw32(NVRAM_ADDR, phy_addr);
12001
12002                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12003                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12004
12005                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12006                         break;
12007
12008                 /* Issue another write enable to start the write. */
12009                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12010
12011                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12012                         break;
12013
12014                 for (j = 0; j < pagesize; j += 4) {
12015                         __be32 data;
12016
12017                         data = *((__be32 *) (tmp + j));
12018
12019                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12020
12021                         tw32(NVRAM_ADDR, phy_addr + j);
12022
12023                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12024                                 NVRAM_CMD_WR;
12025
12026                         if (j == 0)
12027                                 nvram_cmd |= NVRAM_CMD_FIRST;
12028                         else if (j == (pagesize - 4))
12029                                 nvram_cmd |= NVRAM_CMD_LAST;
12030
12031                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12032                                 break;
12033                 }
12034                 if (ret)
12035                         break;
12036         }
12037
12038         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12039         tg3_nvram_exec_cmd(tp, nvram_cmd);
12040
12041         kfree(tmp);
12042
12043         return ret;
12044 }
12045
12046 /* offset and length are dword aligned */
12047 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12048                 u8 *buf)
12049 {
12050         int i, ret = 0;
12051
12052         for (i = 0; i < len; i += 4, offset += 4) {
12053                 u32 page_off, phy_addr, nvram_cmd;
12054                 __be32 data;
12055
12056                 memcpy(&data, buf + i, 4);
12057                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12058
12059                 page_off = offset % tp->nvram_pagesize;
12060
12061                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12062
12063                 tw32(NVRAM_ADDR, phy_addr);
12064
12065                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12066
12067                 if (page_off == 0 || i == 0)
12068                         nvram_cmd |= NVRAM_CMD_FIRST;
12069                 if (page_off == (tp->nvram_pagesize - 4))
12070                         nvram_cmd |= NVRAM_CMD_LAST;
12071
12072                 if (i == (len - 4))
12073                         nvram_cmd |= NVRAM_CMD_LAST;
12074
12075                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12076                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12077                     (tp->nvram_jedecnum == JEDEC_ST) &&
12078                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12079
12080                         if ((ret = tg3_nvram_exec_cmd(tp,
12081                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12082                                 NVRAM_CMD_DONE)))
12083
12084                                 break;
12085                 }
12086                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12087                         /* We always do complete word writes to eeprom. */
12088                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12089                 }
12090
12091                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12092                         break;
12093         }
12094         return ret;
12095 }
12096
12097 /* offset and length are dword aligned */
12098 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12099 {
12100         int ret;
12101
12102         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12103                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12104                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12105                 udelay(40);
12106         }
12107
12108         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12109                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12110         } else {
12111                 u32 grc_mode;
12112
12113                 ret = tg3_nvram_lock(tp);
12114                 if (ret)
12115                         return ret;
12116
12117                 tg3_enable_nvram_access(tp);
12118                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12119                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12120                         tw32(NVRAM_WRITE1, 0x406);
12121
12122                 grc_mode = tr32(GRC_MODE);
12123                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12124
12125                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12126                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12127
12128                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12129                                 buf);
12130                 } else {
12131                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12132                                 buf);
12133                 }
12134
12135                 grc_mode = tr32(GRC_MODE);
12136                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12137
12138                 tg3_disable_nvram_access(tp);
12139                 tg3_nvram_unlock(tp);
12140         }
12141
12142         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12143                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12144                 udelay(40);
12145         }
12146
12147         return ret;
12148 }
12149
12150 struct subsys_tbl_ent {
12151         u16 subsys_vendor, subsys_devid;
12152         u32 phy_id;
12153 };
12154
12155 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12156         /* Broadcom boards. */
12157         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12158           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12159         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12160           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12161         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12162           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12163         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12164           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12165         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12166           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12167         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12168           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12169         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12170           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12171         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12172           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12173         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12174           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12175         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12176           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12177         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12178           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12179
12180         /* 3com boards. */
12181         { TG3PCI_SUBVENDOR_ID_3COM,
12182           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12183         { TG3PCI_SUBVENDOR_ID_3COM,
12184           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12185         { TG3PCI_SUBVENDOR_ID_3COM,
12186           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12187         { TG3PCI_SUBVENDOR_ID_3COM,
12188           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12189         { TG3PCI_SUBVENDOR_ID_3COM,
12190           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12191
12192         /* DELL boards. */
12193         { TG3PCI_SUBVENDOR_ID_DELL,
12194           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12195         { TG3PCI_SUBVENDOR_ID_DELL,
12196           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12197         { TG3PCI_SUBVENDOR_ID_DELL,
12198           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12199         { TG3PCI_SUBVENDOR_ID_DELL,
12200           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12201
12202         /* Compaq boards. */
12203         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12204           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12205         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12206           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12207         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12208           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12209         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12210           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12211         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12212           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12213
12214         /* IBM boards. */
12215         { TG3PCI_SUBVENDOR_ID_IBM,
12216           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12217 };
12218
12219 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12220 {
12221         int i;
12222
12223         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12224                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12225                      tp->pdev->subsystem_vendor) &&
12226                     (subsys_id_to_phy_id[i].subsys_devid ==
12227                      tp->pdev->subsystem_device))
12228                         return &subsys_id_to_phy_id[i];
12229         }
12230         return NULL;
12231 }
12232
12233 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12234 {
12235         u32 val;
12236         u16 pmcsr;
12237
12238         /* On some early chips the SRAM cannot be accessed in D3hot state,
12239          * so need make sure we're in D0.
12240          */
12241         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12242         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12243         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12244         msleep(1);
12245
12246         /* Make sure register accesses (indirect or otherwise)
12247          * will function correctly.
12248          */
12249         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12250                                tp->misc_host_ctrl);
12251
12252         /* The memory arbiter has to be enabled in order for SRAM accesses
12253          * to succeed.  Normally on powerup the tg3 chip firmware will make
12254          * sure it is enabled, but other entities such as system netboot
12255          * code might disable it.
12256          */
12257         val = tr32(MEMARB_MODE);
12258         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12259
12260         tp->phy_id = TG3_PHY_ID_INVALID;
12261         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12262
12263         /* Assume an onboard device and WOL capable by default.  */
12264         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12265
12266         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12267                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12268                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12269                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12270                 }
12271                 val = tr32(VCPU_CFGSHDW);
12272                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12273                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12274                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12275                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12276                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12277                 goto done;
12278         }
12279
12280         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12281         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12282                 u32 nic_cfg, led_cfg;
12283                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12284                 int eeprom_phy_serdes = 0;
12285
12286                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12287                 tp->nic_sram_data_cfg = nic_cfg;
12288
12289                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12290                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12291                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12292                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12293                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12294                     (ver > 0) && (ver < 0x100))
12295                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12296
12297                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12298                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12299
12300                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12301                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12302                         eeprom_phy_serdes = 1;
12303
12304                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12305                 if (nic_phy_id != 0) {
12306                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12307                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12308
12309                         eeprom_phy_id  = (id1 >> 16) << 10;
12310                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12311                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12312                 } else
12313                         eeprom_phy_id = 0;
12314
12315                 tp->phy_id = eeprom_phy_id;
12316                 if (eeprom_phy_serdes) {
12317                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12318                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12319                         else
12320                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12321                 }
12322
12323                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12324                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12325                                     SHASTA_EXT_LED_MODE_MASK);
12326                 else
12327                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12328
12329                 switch (led_cfg) {
12330                 default:
12331                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12332                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12333                         break;
12334
12335                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12336                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12337                         break;
12338
12339                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12340                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12341
12342                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12343                          * read on some older 5700/5701 bootcode.
12344                          */
12345                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12346                             ASIC_REV_5700 ||
12347                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12348                             ASIC_REV_5701)
12349                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12350
12351                         break;
12352
12353                 case SHASTA_EXT_LED_SHARED:
12354                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12355                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12356                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12357                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12358                                                  LED_CTRL_MODE_PHY_2);
12359                         break;
12360
12361                 case SHASTA_EXT_LED_MAC:
12362                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12363                         break;
12364
12365                 case SHASTA_EXT_LED_COMBO:
12366                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12367                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12368                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12369                                                  LED_CTRL_MODE_PHY_2);
12370                         break;
12371
12372                 }
12373
12374                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12375                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12376                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12377                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12378
12379                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12380                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12381
12382                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12383                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12384                         if ((tp->pdev->subsystem_vendor ==
12385                              PCI_VENDOR_ID_ARIMA) &&
12386                             (tp->pdev->subsystem_device == 0x205a ||
12387                              tp->pdev->subsystem_device == 0x2063))
12388                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12389                 } else {
12390                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12391                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12392                 }
12393
12394                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12395                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12396                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12397                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12398                 }
12399
12400                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12401                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12402                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12403
12404                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12405                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12406                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12407
12408                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12409                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12410                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12411
12412                 if (cfg2 & (1 << 17))
12413                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12414
12415                 /* serdes signal pre-emphasis in register 0x590 set by */
12416                 /* bootcode if bit 18 is set */
12417                 if (cfg2 & (1 << 18))
12418                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12419
12420                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12421                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12422                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12423                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12424
12425                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12426                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12427                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12428                         u32 cfg3;
12429
12430                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12431                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12432                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12433                 }
12434
12435                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12436                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12437                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12438                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12439                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12440                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12441         }
12442 done:
12443         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12444         device_set_wakeup_enable(&tp->pdev->dev,
12445                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12446 }
12447
12448 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12449 {
12450         int i;
12451         u32 val;
12452
12453         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12454         tw32(OTP_CTRL, cmd);
12455
12456         /* Wait for up to 1 ms for command to execute. */
12457         for (i = 0; i < 100; i++) {
12458                 val = tr32(OTP_STATUS);
12459                 if (val & OTP_STATUS_CMD_DONE)
12460                         break;
12461                 udelay(10);
12462         }
12463
12464         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12465 }
12466
12467 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12468  * configuration is a 32-bit value that straddles the alignment boundary.
12469  * We do two 32-bit reads and then shift and merge the results.
12470  */
12471 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12472 {
12473         u32 bhalf_otp, thalf_otp;
12474
12475         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12476
12477         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12478                 return 0;
12479
12480         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12481
12482         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12483                 return 0;
12484
12485         thalf_otp = tr32(OTP_READ_DATA);
12486
12487         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12488
12489         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12490                 return 0;
12491
12492         bhalf_otp = tr32(OTP_READ_DATA);
12493
12494         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12495 }
12496
12497 static int __devinit tg3_phy_probe(struct tg3 *tp)
12498 {
12499         u32 hw_phy_id_1, hw_phy_id_2;
12500         u32 hw_phy_id, hw_phy_id_masked;
12501         int err;
12502
12503         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12504                 return tg3_phy_init(tp);
12505
12506         /* Reading the PHY ID register can conflict with ASF
12507          * firmware access to the PHY hardware.
12508          */
12509         err = 0;
12510         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12511             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12512                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12513         } else {
12514                 /* Now read the physical PHY_ID from the chip and verify
12515                  * that it is sane.  If it doesn't look good, we fall back
12516                  * to either the hard-coded table based PHY_ID and failing
12517                  * that the value found in the eeprom area.
12518                  */
12519                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12520                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12521
12522                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12523                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12524                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12525
12526                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12527         }
12528
12529         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12530                 tp->phy_id = hw_phy_id;
12531                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12532                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12533                 else
12534                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12535         } else {
12536                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12537                         /* Do nothing, phy ID already set up in
12538                          * tg3_get_eeprom_hw_cfg().
12539                          */
12540                 } else {
12541                         struct subsys_tbl_ent *p;
12542
12543                         /* No eeprom signature?  Try the hardcoded
12544                          * subsys device table.
12545                          */
12546                         p = tg3_lookup_by_subsys(tp);
12547                         if (!p)
12548                                 return -ENODEV;
12549
12550                         tp->phy_id = p->phy_id;
12551                         if (!tp->phy_id ||
12552                             tp->phy_id == TG3_PHY_ID_BCM8002)
12553                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12554                 }
12555         }
12556
12557         if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12558             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12559              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12560                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12561
12562         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12563             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12564             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12565                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12566
12567                 tg3_readphy(tp, MII_BMSR, &bmsr);
12568                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12569                     (bmsr & BMSR_LSTATUS))
12570                         goto skip_phy_reset;
12571
12572                 err = tg3_phy_reset(tp);
12573                 if (err)
12574                         return err;
12575
12576                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12577                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12578                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12579                 tg3_ctrl = 0;
12580                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12581                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12582                                     MII_TG3_CTRL_ADV_1000_FULL);
12583                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12584                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12585                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12586                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12587                 }
12588
12589                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12590                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12591                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12592                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12593                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12594
12595                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12596                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12597
12598                         tg3_writephy(tp, MII_BMCR,
12599                                      BMCR_ANENABLE | BMCR_ANRESTART);
12600                 }
12601                 tg3_phy_set_wirespeed(tp);
12602
12603                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12604                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12605                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12606         }
12607
12608 skip_phy_reset:
12609         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12610                 err = tg3_init_5401phy_dsp(tp);
12611                 if (err)
12612                         return err;
12613
12614                 err = tg3_init_5401phy_dsp(tp);
12615         }
12616
12617         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12618                 tp->link_config.advertising =
12619                         (ADVERTISED_1000baseT_Half |
12620                          ADVERTISED_1000baseT_Full |
12621                          ADVERTISED_Autoneg |
12622                          ADVERTISED_FIBRE);
12623         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12624                 tp->link_config.advertising &=
12625                         ~(ADVERTISED_1000baseT_Half |
12626                           ADVERTISED_1000baseT_Full);
12627
12628         return err;
12629 }
12630
12631 static void __devinit tg3_read_vpd(struct tg3 *tp)
12632 {
12633         u8 *vpd_data;
12634         unsigned int block_end, rosize, len;
12635         int j, i = 0;
12636         u32 magic;
12637
12638         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12639             tg3_nvram_read(tp, 0x0, &magic))
12640                 goto out_no_vpd;
12641
12642         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12643         if (!vpd_data)
12644                 goto out_no_vpd;
12645
12646         if (magic == TG3_EEPROM_MAGIC) {
12647                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12648                         u32 tmp;
12649
12650                         /* The data is in little-endian format in NVRAM.
12651                          * Use the big-endian read routines to preserve
12652                          * the byte order as it exists in NVRAM.
12653                          */
12654                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12655                                 goto out_not_found;
12656
12657                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12658                 }
12659         } else {
12660                 ssize_t cnt;
12661                 unsigned int pos = 0;
12662
12663                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12664                         cnt = pci_read_vpd(tp->pdev, pos,
12665                                            TG3_NVM_VPD_LEN - pos,
12666                                            &vpd_data[pos]);
12667                         if (cnt == -ETIMEDOUT || -EINTR)
12668                                 cnt = 0;
12669                         else if (cnt < 0)
12670                                 goto out_not_found;
12671                 }
12672                 if (pos != TG3_NVM_VPD_LEN)
12673                         goto out_not_found;
12674         }
12675
12676         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12677                              PCI_VPD_LRDT_RO_DATA);
12678         if (i < 0)
12679                 goto out_not_found;
12680
12681         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12682         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12683         i += PCI_VPD_LRDT_TAG_SIZE;
12684
12685         if (block_end > TG3_NVM_VPD_LEN)
12686                 goto out_not_found;
12687
12688         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12689                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12690         if (j > 0) {
12691                 len = pci_vpd_info_field_size(&vpd_data[j]);
12692
12693                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12694                 if (j + len > block_end || len != 4 ||
12695                     memcmp(&vpd_data[j], "1028", 4))
12696                         goto partno;
12697
12698                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12699                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12700                 if (j < 0)
12701                         goto partno;
12702
12703                 len = pci_vpd_info_field_size(&vpd_data[j]);
12704
12705                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12706                 if (j + len > block_end)
12707                         goto partno;
12708
12709                 memcpy(tp->fw_ver, &vpd_data[j], len);
12710                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12711         }
12712
12713 partno:
12714         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12715                                       PCI_VPD_RO_KEYWORD_PARTNO);
12716         if (i < 0)
12717                 goto out_not_found;
12718
12719         len = pci_vpd_info_field_size(&vpd_data[i]);
12720
12721         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12722         if (len > TG3_BPN_SIZE ||
12723             (len + i) > TG3_NVM_VPD_LEN)
12724                 goto out_not_found;
12725
12726         memcpy(tp->board_part_number, &vpd_data[i], len);
12727
12728 out_not_found:
12729         kfree(vpd_data);
12730         if (tp->board_part_number[0])
12731                 return;
12732
12733 out_no_vpd:
12734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12735                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12736                         strcpy(tp->board_part_number, "BCM5717");
12737                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12738                         strcpy(tp->board_part_number, "BCM5718");
12739                 else
12740                         goto nomatch;
12741         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12742                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12743                         strcpy(tp->board_part_number, "BCM57780");
12744                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12745                         strcpy(tp->board_part_number, "BCM57760");
12746                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12747                         strcpy(tp->board_part_number, "BCM57790");
12748                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12749                         strcpy(tp->board_part_number, "BCM57788");
12750                 else
12751                         goto nomatch;
12752         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12753                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12754                         strcpy(tp->board_part_number, "BCM57761");
12755                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12756                         strcpy(tp->board_part_number, "BCM57765");
12757                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12758                         strcpy(tp->board_part_number, "BCM57781");
12759                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12760                         strcpy(tp->board_part_number, "BCM57785");
12761                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12762                         strcpy(tp->board_part_number, "BCM57791");
12763                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12764                         strcpy(tp->board_part_number, "BCM57795");
12765                 else
12766                         goto nomatch;
12767         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12768                 strcpy(tp->board_part_number, "BCM95906");
12769         } else {
12770 nomatch:
12771                 strcpy(tp->board_part_number, "none");
12772         }
12773 }
12774
12775 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12776 {
12777         u32 val;
12778
12779         if (tg3_nvram_read(tp, offset, &val) ||
12780             (val & 0xfc000000) != 0x0c000000 ||
12781             tg3_nvram_read(tp, offset + 4, &val) ||
12782             val != 0)
12783                 return 0;
12784
12785         return 1;
12786 }
12787
12788 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12789 {
12790         u32 val, offset, start, ver_offset;
12791         int i, dst_off;
12792         bool newver = false;
12793
12794         if (tg3_nvram_read(tp, 0xc, &offset) ||
12795             tg3_nvram_read(tp, 0x4, &start))
12796                 return;
12797
12798         offset = tg3_nvram_logical_addr(tp, offset);
12799
12800         if (tg3_nvram_read(tp, offset, &val))
12801                 return;
12802
12803         if ((val & 0xfc000000) == 0x0c000000) {
12804                 if (tg3_nvram_read(tp, offset + 4, &val))
12805                         return;
12806
12807                 if (val == 0)
12808                         newver = true;
12809         }
12810
12811         dst_off = strlen(tp->fw_ver);
12812
12813         if (newver) {
12814                 if (TG3_VER_SIZE - dst_off < 16 ||
12815                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12816                         return;
12817
12818                 offset = offset + ver_offset - start;
12819                 for (i = 0; i < 16; i += 4) {
12820                         __be32 v;
12821                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12822                                 return;
12823
12824                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12825                 }
12826         } else {
12827                 u32 major, minor;
12828
12829                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12830                         return;
12831
12832                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12833                         TG3_NVM_BCVER_MAJSFT;
12834                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12835                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12836                          "v%d.%02d", major, minor);
12837         }
12838 }
12839
12840 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12841 {
12842         u32 val, major, minor;
12843
12844         /* Use native endian representation */
12845         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12846                 return;
12847
12848         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12849                 TG3_NVM_HWSB_CFG1_MAJSFT;
12850         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12851                 TG3_NVM_HWSB_CFG1_MINSFT;
12852
12853         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12854 }
12855
12856 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12857 {
12858         u32 offset, major, minor, build;
12859
12860         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12861
12862         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12863                 return;
12864
12865         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12866         case TG3_EEPROM_SB_REVISION_0:
12867                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12868                 break;
12869         case TG3_EEPROM_SB_REVISION_2:
12870                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12871                 break;
12872         case TG3_EEPROM_SB_REVISION_3:
12873                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12874                 break;
12875         case TG3_EEPROM_SB_REVISION_4:
12876                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12877                 break;
12878         case TG3_EEPROM_SB_REVISION_5:
12879                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12880                 break;
12881         case TG3_EEPROM_SB_REVISION_6:
12882                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12883                 break;
12884         default:
12885                 return;
12886         }
12887
12888         if (tg3_nvram_read(tp, offset, &val))
12889                 return;
12890
12891         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12892                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12893         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12894                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12895         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12896
12897         if (minor > 99 || build > 26)
12898                 return;
12899
12900         offset = strlen(tp->fw_ver);
12901         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12902                  " v%d.%02d", major, minor);
12903
12904         if (build > 0) {
12905                 offset = strlen(tp->fw_ver);
12906                 if (offset < TG3_VER_SIZE - 1)
12907                         tp->fw_ver[offset] = 'a' + build - 1;
12908         }
12909 }
12910
12911 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12912 {
12913         u32 val, offset, start;
12914         int i, vlen;
12915
12916         for (offset = TG3_NVM_DIR_START;
12917              offset < TG3_NVM_DIR_END;
12918              offset += TG3_NVM_DIRENT_SIZE) {
12919                 if (tg3_nvram_read(tp, offset, &val))
12920                         return;
12921
12922                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12923                         break;
12924         }
12925
12926         if (offset == TG3_NVM_DIR_END)
12927                 return;
12928
12929         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12930                 start = 0x08000000;
12931         else if (tg3_nvram_read(tp, offset - 4, &start))
12932                 return;
12933
12934         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12935             !tg3_fw_img_is_valid(tp, offset) ||
12936             tg3_nvram_read(tp, offset + 8, &val))
12937                 return;
12938
12939         offset += val - start;
12940
12941         vlen = strlen(tp->fw_ver);
12942
12943         tp->fw_ver[vlen++] = ',';
12944         tp->fw_ver[vlen++] = ' ';
12945
12946         for (i = 0; i < 4; i++) {
12947                 __be32 v;
12948                 if (tg3_nvram_read_be32(tp, offset, &v))
12949                         return;
12950
12951                 offset += sizeof(v);
12952
12953                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12954                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12955                         break;
12956                 }
12957
12958                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12959                 vlen += sizeof(v);
12960         }
12961 }
12962
12963 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12964 {
12965         int vlen;
12966         u32 apedata;
12967         char *fwtype;
12968
12969         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12970             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12971                 return;
12972
12973         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12974         if (apedata != APE_SEG_SIG_MAGIC)
12975                 return;
12976
12977         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12978         if (!(apedata & APE_FW_STATUS_READY))
12979                 return;
12980
12981         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12982
12983         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12984                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12985                 fwtype = "NCSI";
12986         } else {
12987                 fwtype = "DASH";
12988         }
12989
12990         vlen = strlen(tp->fw_ver);
12991
12992         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12993                  fwtype,
12994                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12995                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12996                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12997                  (apedata & APE_FW_VERSION_BLDMSK));
12998 }
12999
13000 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13001 {
13002         u32 val;
13003         bool vpd_vers = false;
13004
13005         if (tp->fw_ver[0] != 0)
13006                 vpd_vers = true;
13007
13008         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13009                 strcat(tp->fw_ver, "sb");
13010                 return;
13011         }
13012
13013         if (tg3_nvram_read(tp, 0, &val))
13014                 return;
13015
13016         if (val == TG3_EEPROM_MAGIC)
13017                 tg3_read_bc_ver(tp);
13018         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13019                 tg3_read_sb_ver(tp, val);
13020         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13021                 tg3_read_hwsb_ver(tp);
13022         else
13023                 return;
13024
13025         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13026              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13027                 goto done;
13028
13029         tg3_read_mgmtfw_ver(tp);
13030
13031 done:
13032         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13033 }
13034
13035 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13036
13037 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13038 {
13039 #if TG3_VLAN_TAG_USED
13040         dev->vlan_features |= flags;
13041 #endif
13042 }
13043
13044 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13045 {
13046         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13048                 return 4096;
13049         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13050                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13051                 return 1024;
13052         else
13053                 return 512;
13054 }
13055
13056 static int __devinit tg3_get_invariants(struct tg3 *tp)
13057 {
13058         static struct pci_device_id write_reorder_chipsets[] = {
13059                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13060                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13061                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13062                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13063                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13064                              PCI_DEVICE_ID_VIA_8385_0) },
13065                 { },
13066         };
13067         u32 misc_ctrl_reg;
13068         u32 pci_state_reg, grc_misc_cfg;
13069         u32 val;
13070         u16 pci_cmd;
13071         int err;
13072
13073         /* Force memory write invalidate off.  If we leave it on,
13074          * then on 5700_BX chips we have to enable a workaround.
13075          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13076          * to match the cacheline size.  The Broadcom driver have this
13077          * workaround but turns MWI off all the times so never uses
13078          * it.  This seems to suggest that the workaround is insufficient.
13079          */
13080         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13081         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13082         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13083
13084         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13085          * has the register indirect write enable bit set before
13086          * we try to access any of the MMIO registers.  It is also
13087          * critical that the PCI-X hw workaround situation is decided
13088          * before that as well.
13089          */
13090         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13091                               &misc_ctrl_reg);
13092
13093         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13094                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13095         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13096                 u32 prod_id_asic_rev;
13097
13098                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13099                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13100                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13101                         pci_read_config_dword(tp->pdev,
13102                                               TG3PCI_GEN2_PRODID_ASICREV,
13103                                               &prod_id_asic_rev);
13104                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13105                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13106                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13107                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13108                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13109                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13110                         pci_read_config_dword(tp->pdev,
13111                                               TG3PCI_GEN15_PRODID_ASICREV,
13112                                               &prod_id_asic_rev);
13113                 else
13114                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13115                                               &prod_id_asic_rev);
13116
13117                 tp->pci_chip_rev_id = prod_id_asic_rev;
13118         }
13119
13120         /* Wrong chip ID in 5752 A0. This code can be removed later
13121          * as A0 is not in production.
13122          */
13123         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13124                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13125
13126         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13127          * we need to disable memory and use config. cycles
13128          * only to access all registers. The 5702/03 chips
13129          * can mistakenly decode the special cycles from the
13130          * ICH chipsets as memory write cycles, causing corruption
13131          * of register and memory space. Only certain ICH bridges
13132          * will drive special cycles with non-zero data during the
13133          * address phase which can fall within the 5703's address
13134          * range. This is not an ICH bug as the PCI spec allows
13135          * non-zero address during special cycles. However, only
13136          * these ICH bridges are known to drive non-zero addresses
13137          * during special cycles.
13138          *
13139          * Since special cycles do not cross PCI bridges, we only
13140          * enable this workaround if the 5703 is on the secondary
13141          * bus of these ICH bridges.
13142          */
13143         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13144             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13145                 static struct tg3_dev_id {
13146                         u32     vendor;
13147                         u32     device;
13148                         u32     rev;
13149                 } ich_chipsets[] = {
13150                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13151                           PCI_ANY_ID },
13152                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13153                           PCI_ANY_ID },
13154                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13155                           0xa },
13156                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13157                           PCI_ANY_ID },
13158                         { },
13159                 };
13160                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13161                 struct pci_dev *bridge = NULL;
13162
13163                 while (pci_id->vendor != 0) {
13164                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13165                                                 bridge);
13166                         if (!bridge) {
13167                                 pci_id++;
13168                                 continue;
13169                         }
13170                         if (pci_id->rev != PCI_ANY_ID) {
13171                                 if (bridge->revision > pci_id->rev)
13172                                         continue;
13173                         }
13174                         if (bridge->subordinate &&
13175                             (bridge->subordinate->number ==
13176                              tp->pdev->bus->number)) {
13177
13178                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13179                                 pci_dev_put(bridge);
13180                                 break;
13181                         }
13182                 }
13183         }
13184
13185         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13186                 static struct tg3_dev_id {
13187                         u32     vendor;
13188                         u32     device;
13189                 } bridge_chipsets[] = {
13190                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13191                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13192                         { },
13193                 };
13194                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13195                 struct pci_dev *bridge = NULL;
13196
13197                 while (pci_id->vendor != 0) {
13198                         bridge = pci_get_device(pci_id->vendor,
13199                                                 pci_id->device,
13200                                                 bridge);
13201                         if (!bridge) {
13202                                 pci_id++;
13203                                 continue;
13204                         }
13205                         if (bridge->subordinate &&
13206                             (bridge->subordinate->number <=
13207                              tp->pdev->bus->number) &&
13208                             (bridge->subordinate->subordinate >=
13209                              tp->pdev->bus->number)) {
13210                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13211                                 pci_dev_put(bridge);
13212                                 break;
13213                         }
13214                 }
13215         }
13216
13217         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13218          * DMA addresses > 40-bit. This bridge may have other additional
13219          * 57xx devices behind it in some 4-port NIC designs for example.
13220          * Any tg3 device found behind the bridge will also need the 40-bit
13221          * DMA workaround.
13222          */
13223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13224             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13225                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13226                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13227                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13228         } else {
13229                 struct pci_dev *bridge = NULL;
13230
13231                 do {
13232                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13233                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13234                                                 bridge);
13235                         if (bridge && bridge->subordinate &&
13236                             (bridge->subordinate->number <=
13237                              tp->pdev->bus->number) &&
13238                             (bridge->subordinate->subordinate >=
13239                              tp->pdev->bus->number)) {
13240                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13241                                 pci_dev_put(bridge);
13242                                 break;
13243                         }
13244                 } while (bridge);
13245         }
13246
13247         /* Initialize misc host control in PCI block. */
13248         tp->misc_host_ctrl |= (misc_ctrl_reg &
13249                                MISC_HOST_CTRL_CHIPREV);
13250         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13251                                tp->misc_host_ctrl);
13252
13253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13254             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13255             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13256                 tp->pdev_peer = tg3_find_peer(tp);
13257
13258         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13259             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13260             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13261                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13262
13263         /* Intentionally exclude ASIC_REV_5906 */
13264         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13265             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13266             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13267             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13268             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13269             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13270             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13271                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13272
13273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13274             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13275             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13276             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13277             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13278                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13279
13280         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13281             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13282                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13283
13284         /* 5700 B0 chips do not support checksumming correctly due
13285          * to hardware bugs.
13286          */
13287         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13288                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13289         else {
13290                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13291
13292                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13293                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13294                         features |= NETIF_F_IPV6_CSUM;
13295                 tp->dev->features |= features;
13296                 vlan_features_add(tp->dev, features);
13297         }
13298
13299         /* Determine TSO capabilities */
13300         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13301                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13302         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13303                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13304                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13305         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13306                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13307                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13308                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13309                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13310         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13311                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13312                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13313                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13314                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13315                         tp->fw_needed = FIRMWARE_TG3TSO5;
13316                 else
13317                         tp->fw_needed = FIRMWARE_TG3TSO;
13318         }
13319
13320         tp->irq_max = 1;
13321
13322         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13323                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13324                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13325                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13326                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13327                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13328                      tp->pdev_peer == tp->pdev))
13329                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13330
13331                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13332                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13333                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13334                 }
13335
13336                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13337                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13338                         tp->irq_max = TG3_IRQ_MAX_VECS;
13339                 }
13340         }
13341
13342         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13343             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13344             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13345                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13346         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13347                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13348                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13349         }
13350
13351         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13352                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13353
13354         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13355             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13356             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13357                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13358
13359         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13360                               &pci_state_reg);
13361
13362         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13363         if (tp->pcie_cap != 0) {
13364                 u16 lnkctl;
13365
13366                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13367
13368                 tp->pcie_readrq = 4096;
13369                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13370                         u16 word;
13371
13372                         pci_read_config_word(tp->pdev,
13373                                              tp->pcie_cap + PCI_EXP_LNKSTA,
13374                                              &word);
13375                         switch (word & PCI_EXP_LNKSTA_CLS) {
13376                         case PCI_EXP_LNKSTA_CLS_2_5GB:
13377                                 word &= PCI_EXP_LNKSTA_NLW;
13378                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13379                                 switch (word) {
13380                                 case 2:
13381                                         tp->pcie_readrq = 2048;
13382                                         break;
13383                                 case 4:
13384                                         tp->pcie_readrq = 1024;
13385                                         break;
13386                                 }
13387                                 break;
13388
13389                         case PCI_EXP_LNKSTA_CLS_5_0GB:
13390                                 word &= PCI_EXP_LNKSTA_NLW;
13391                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13392                                 switch (word) {
13393                                 case 1:
13394                                         tp->pcie_readrq = 2048;
13395                                         break;
13396                                 case 2:
13397                                         tp->pcie_readrq = 1024;
13398                                         break;
13399                                 case 4:
13400                                         tp->pcie_readrq = 512;
13401                                         break;
13402                                 }
13403                         }
13404                 }
13405
13406                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13407
13408                 pci_read_config_word(tp->pdev,
13409                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13410                                      &lnkctl);
13411                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13412                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13413                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13414                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13415                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13416                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13417                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13418                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13419                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13420                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13421                 }
13422         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13423                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13424         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13425                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13426                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13427                 if (!tp->pcix_cap) {
13428                         dev_err(&tp->pdev->dev,
13429                                 "Cannot find PCI-X capability, aborting\n");
13430                         return -EIO;
13431                 }
13432
13433                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13434                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13435         }
13436
13437         /* If we have an AMD 762 or VIA K8T800 chipset, write
13438          * reordering to the mailbox registers done by the host
13439          * controller can cause major troubles.  We read back from
13440          * every mailbox register write to force the writes to be
13441          * posted to the chip in order.
13442          */
13443         if (pci_dev_present(write_reorder_chipsets) &&
13444             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13445                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13446
13447         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13448                              &tp->pci_cacheline_sz);
13449         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13450                              &tp->pci_lat_timer);
13451         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13452             tp->pci_lat_timer < 64) {
13453                 tp->pci_lat_timer = 64;
13454                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13455                                       tp->pci_lat_timer);
13456         }
13457
13458         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13459                 /* 5700 BX chips need to have their TX producer index
13460                  * mailboxes written twice to workaround a bug.
13461                  */
13462                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13463
13464                 /* If we are in PCI-X mode, enable register write workaround.
13465                  *
13466                  * The workaround is to use indirect register accesses
13467                  * for all chip writes not to mailbox registers.
13468                  */
13469                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13470                         u32 pm_reg;
13471
13472                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13473
13474                         /* The chip can have it's power management PCI config
13475                          * space registers clobbered due to this bug.
13476                          * So explicitly force the chip into D0 here.
13477                          */
13478                         pci_read_config_dword(tp->pdev,
13479                                               tp->pm_cap + PCI_PM_CTRL,
13480                                               &pm_reg);
13481                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13482                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13483                         pci_write_config_dword(tp->pdev,
13484                                                tp->pm_cap + PCI_PM_CTRL,
13485                                                pm_reg);
13486
13487                         /* Also, force SERR#/PERR# in PCI command. */
13488                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13489                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13490                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13491                 }
13492         }
13493
13494         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13495                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13496         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13497                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13498
13499         /* Chip-specific fixup from Broadcom driver */
13500         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13501             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13502                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13503                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13504         }
13505
13506         /* Default fast path register access methods */
13507         tp->read32 = tg3_read32;
13508         tp->write32 = tg3_write32;
13509         tp->read32_mbox = tg3_read32;
13510         tp->write32_mbox = tg3_write32;
13511         tp->write32_tx_mbox = tg3_write32;
13512         tp->write32_rx_mbox = tg3_write32;
13513
13514         /* Various workaround register access methods */
13515         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13516                 tp->write32 = tg3_write_indirect_reg32;
13517         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13518                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13519                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13520                 /*
13521                  * Back to back register writes can cause problems on these
13522                  * chips, the workaround is to read back all reg writes
13523                  * except those to mailbox regs.
13524                  *
13525                  * See tg3_write_indirect_reg32().
13526                  */
13527                 tp->write32 = tg3_write_flush_reg32;
13528         }
13529
13530         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13531             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13532                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13533                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13534                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13535         }
13536
13537         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13538                 tp->read32 = tg3_read_indirect_reg32;
13539                 tp->write32 = tg3_write_indirect_reg32;
13540                 tp->read32_mbox = tg3_read_indirect_mbox;
13541                 tp->write32_mbox = tg3_write_indirect_mbox;
13542                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13543                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13544
13545                 iounmap(tp->regs);
13546                 tp->regs = NULL;
13547
13548                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13549                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13550                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13551         }
13552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13553                 tp->read32_mbox = tg3_read32_mbox_5906;
13554                 tp->write32_mbox = tg3_write32_mbox_5906;
13555                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13556                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13557         }
13558
13559         if (tp->write32 == tg3_write_indirect_reg32 ||
13560             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13561              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13562               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13563                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13564
13565         /* Get eeprom hw config before calling tg3_set_power_state().
13566          * In particular, the TG3_FLG2_IS_NIC flag must be
13567          * determined before calling tg3_set_power_state() so that
13568          * we know whether or not to switch out of Vaux power.
13569          * When the flag is set, it means that GPIO1 is used for eeprom
13570          * write protect and also implies that it is a LOM where GPIOs
13571          * are not used to switch power.
13572          */
13573         tg3_get_eeprom_hw_cfg(tp);
13574
13575         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13576                 /* Allow reads and writes to the
13577                  * APE register and memory space.
13578                  */
13579                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13580                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13581                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13582                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13583                                        pci_state_reg);
13584         }
13585
13586         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13587             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13588             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13589             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13590             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13591                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13592
13593         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13594          * GPIO1 driven high will bring 5700's external PHY out of reset.
13595          * It is also used as eeprom write protect on LOMs.
13596          */
13597         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13598         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13599             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13600                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13601                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13602         /* Unused GPIO3 must be driven as output on 5752 because there
13603          * are no pull-up resistors on unused GPIO pins.
13604          */
13605         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13606                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13607
13608         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13609             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13610             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13611                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13612
13613         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13614             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13615                 /* Turn off the debug UART. */
13616                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13617                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13618                         /* Keep VMain power. */
13619                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13620                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13621         }
13622
13623         /* Force the chip into D0. */
13624         err = tg3_set_power_state(tp, PCI_D0);
13625         if (err) {
13626                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13627                 return err;
13628         }
13629
13630         /* Derive initial jumbo mode from MTU assigned in
13631          * ether_setup() via the alloc_etherdev() call
13632          */
13633         if (tp->dev->mtu > ETH_DATA_LEN &&
13634             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13635                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13636
13637         /* Determine WakeOnLan speed to use. */
13638         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13639             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13640             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13641             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13642                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13643         } else {
13644                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13645         }
13646
13647         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13648                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13649
13650         /* A few boards don't want Ethernet@WireSpeed phy feature */
13651         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13652             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13653              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13654              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13655             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13656             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13657                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13658
13659         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13660             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13661                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13662         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13663                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13664
13665         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13666             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13667             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13668             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13669             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13670                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13671                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13672                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13673                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13674                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13675                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13676                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13677                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13678                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13679                 } else
13680                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13681         }
13682
13683         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13684             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13685                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13686                 if (tp->phy_otp == 0)
13687                         tp->phy_otp = TG3_OTP_DEFAULT;
13688         }
13689
13690         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13691                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13692         else
13693                 tp->mi_mode = MAC_MI_MODE_BASE;
13694
13695         tp->coalesce_mode = 0;
13696         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13697             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13698                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13699
13700         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13701             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13702                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13703
13704         err = tg3_mdio_init(tp);
13705         if (err)
13706                 return err;
13707
13708         /* Initialize data/descriptor byte/word swapping. */
13709         val = tr32(GRC_MODE);
13710         val &= GRC_MODE_HOST_STACKUP;
13711         tw32(GRC_MODE, val | tp->grc_mode);
13712
13713         tg3_switch_clocks(tp);
13714
13715         /* Clear this out for sanity. */
13716         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13717
13718         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13719                               &pci_state_reg);
13720         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13721             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13722                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13723
13724                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13725                     chiprevid == CHIPREV_ID_5701_B0 ||
13726                     chiprevid == CHIPREV_ID_5701_B2 ||
13727                     chiprevid == CHIPREV_ID_5701_B5) {
13728                         void __iomem *sram_base;
13729
13730                         /* Write some dummy words into the SRAM status block
13731                          * area, see if it reads back correctly.  If the return
13732                          * value is bad, force enable the PCIX workaround.
13733                          */
13734                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13735
13736                         writel(0x00000000, sram_base);
13737                         writel(0x00000000, sram_base + 4);
13738                         writel(0xffffffff, sram_base + 4);
13739                         if (readl(sram_base) != 0x00000000)
13740                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13741                 }
13742         }
13743
13744         udelay(50);
13745         tg3_nvram_init(tp);
13746
13747         grc_misc_cfg = tr32(GRC_MISC_CFG);
13748         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13749
13750         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13751             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13752              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13753                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13754
13755         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13756             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13757                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13758         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13759                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13760                                       HOSTCC_MODE_CLRTICK_TXBD);
13761
13762                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13763                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13764                                        tp->misc_host_ctrl);
13765         }
13766
13767         /* Preserve the APE MAC_MODE bits */
13768         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13769                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13770         else
13771                 tp->mac_mode = TG3_DEF_MAC_MODE;
13772
13773         /* these are limited to 10/100 only */
13774         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13775              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13776             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13777              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13778              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13779               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13780               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13781             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13782              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13783               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13784               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13785             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13786             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13787             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13788             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13789                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13790
13791         err = tg3_phy_probe(tp);
13792         if (err) {
13793                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13794                 /* ... but do not return immediately ... */
13795                 tg3_mdio_fini(tp);
13796         }
13797
13798         tg3_read_vpd(tp);
13799         tg3_read_fw_ver(tp);
13800
13801         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13802                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13803         } else {
13804                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13805                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13806                 else
13807                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13808         }
13809
13810         /* 5700 {AX,BX} chips have a broken status block link
13811          * change bit implementation, so we must use the
13812          * status register in those cases.
13813          */
13814         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13815                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13816         else
13817                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13818
13819         /* The led_ctrl is set during tg3_phy_probe, here we might
13820          * have to force the link status polling mechanism based
13821          * upon subsystem IDs.
13822          */
13823         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13824             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13825             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13826                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13827                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13828         }
13829
13830         /* For all SERDES we poll the MAC status register. */
13831         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13832                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13833         else
13834                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13835
13836         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13837         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13839             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13840                 tp->rx_offset -= NET_IP_ALIGN;
13841 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13842                 tp->rx_copy_thresh = ~(u16)0;
13843 #endif
13844         }
13845
13846         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13847         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13848         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13849
13850         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13851
13852         /* Increment the rx prod index on the rx std ring by at most
13853          * 8 for these chips to workaround hw errata.
13854          */
13855         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13856             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13858                 tp->rx_std_max_post = 8;
13859
13860         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13861                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13862                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13863
13864         return err;
13865 }
13866
13867 #ifdef CONFIG_SPARC
13868 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13869 {
13870         struct net_device *dev = tp->dev;
13871         struct pci_dev *pdev = tp->pdev;
13872         struct device_node *dp = pci_device_to_OF_node(pdev);
13873         const unsigned char *addr;
13874         int len;
13875
13876         addr = of_get_property(dp, "local-mac-address", &len);
13877         if (addr && len == 6) {
13878                 memcpy(dev->dev_addr, addr, 6);
13879                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13880                 return 0;
13881         }
13882         return -ENODEV;
13883 }
13884
13885 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13886 {
13887         struct net_device *dev = tp->dev;
13888
13889         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13890         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13891         return 0;
13892 }
13893 #endif
13894
13895 static int __devinit tg3_get_device_address(struct tg3 *tp)
13896 {
13897         struct net_device *dev = tp->dev;
13898         u32 hi, lo, mac_offset;
13899         int addr_ok = 0;
13900
13901 #ifdef CONFIG_SPARC
13902         if (!tg3_get_macaddr_sparc(tp))
13903                 return 0;
13904 #endif
13905
13906         mac_offset = 0x7c;
13907         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13908             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13909                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13910                         mac_offset = 0xcc;
13911                 if (tg3_nvram_lock(tp))
13912                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13913                 else
13914                         tg3_nvram_unlock(tp);
13915         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13916                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13917                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13918                         mac_offset = 0xcc;
13919                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13920                         mac_offset += 0x18c;
13921         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13922                 mac_offset = 0x10;
13923
13924         /* First try to get it from MAC address mailbox. */
13925         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13926         if ((hi >> 16) == 0x484b) {
13927                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13928                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13929
13930                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13931                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13932                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13933                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13934                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13935
13936                 /* Some old bootcode may report a 0 MAC address in SRAM */
13937                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13938         }
13939         if (!addr_ok) {
13940                 /* Next, try NVRAM. */
13941                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13942                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13943                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13944                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13945                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13946                 }
13947                 /* Finally just fetch it out of the MAC control regs. */
13948                 else {
13949                         hi = tr32(MAC_ADDR_0_HIGH);
13950                         lo = tr32(MAC_ADDR_0_LOW);
13951
13952                         dev->dev_addr[5] = lo & 0xff;
13953                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13954                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13955                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13956                         dev->dev_addr[1] = hi & 0xff;
13957                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13958                 }
13959         }
13960
13961         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13962 #ifdef CONFIG_SPARC
13963                 if (!tg3_get_default_macaddr_sparc(tp))
13964                         return 0;
13965 #endif
13966                 return -EINVAL;
13967         }
13968         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13969         return 0;
13970 }
13971
13972 #define BOUNDARY_SINGLE_CACHELINE       1
13973 #define BOUNDARY_MULTI_CACHELINE        2
13974
13975 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13976 {
13977         int cacheline_size;
13978         u8 byte;
13979         int goal;
13980
13981         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13982         if (byte == 0)
13983                 cacheline_size = 1024;
13984         else
13985                 cacheline_size = (int) byte * 4;
13986
13987         /* On 5703 and later chips, the boundary bits have no
13988          * effect.
13989          */
13990         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13991             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13992             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13993                 goto out;
13994
13995 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13996         goal = BOUNDARY_MULTI_CACHELINE;
13997 #else
13998 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13999         goal = BOUNDARY_SINGLE_CACHELINE;
14000 #else
14001         goal = 0;
14002 #endif
14003 #endif
14004
14005         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14006                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14007                 goto out;
14008         }
14009
14010         if (!goal)
14011                 goto out;
14012
14013         /* PCI controllers on most RISC systems tend to disconnect
14014          * when a device tries to burst across a cache-line boundary.
14015          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14016          *
14017          * Unfortunately, for PCI-E there are only limited
14018          * write-side controls for this, and thus for reads
14019          * we will still get the disconnects.  We'll also waste
14020          * these PCI cycles for both read and write for chips
14021          * other than 5700 and 5701 which do not implement the
14022          * boundary bits.
14023          */
14024         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14025             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14026                 switch (cacheline_size) {
14027                 case 16:
14028                 case 32:
14029                 case 64:
14030                 case 128:
14031                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14032                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14033                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14034                         } else {
14035                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14036                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14037                         }
14038                         break;
14039
14040                 case 256:
14041                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14042                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14043                         break;
14044
14045                 default:
14046                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14047                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14048                         break;
14049                 }
14050         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14051                 switch (cacheline_size) {
14052                 case 16:
14053                 case 32:
14054                 case 64:
14055                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14056                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14057                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14058                                 break;
14059                         }
14060                         /* fallthrough */
14061                 case 128:
14062                 default:
14063                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14064                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14065                         break;
14066                 }
14067         } else {
14068                 switch (cacheline_size) {
14069                 case 16:
14070                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14071                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14072                                         DMA_RWCTRL_WRITE_BNDRY_16);
14073                                 break;
14074                         }
14075                         /* fallthrough */
14076                 case 32:
14077                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14078                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14079                                         DMA_RWCTRL_WRITE_BNDRY_32);
14080                                 break;
14081                         }
14082                         /* fallthrough */
14083                 case 64:
14084                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14085                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14086                                         DMA_RWCTRL_WRITE_BNDRY_64);
14087                                 break;
14088                         }
14089                         /* fallthrough */
14090                 case 128:
14091                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14092                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14093                                         DMA_RWCTRL_WRITE_BNDRY_128);
14094                                 break;
14095                         }
14096                         /* fallthrough */
14097                 case 256:
14098                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14099                                 DMA_RWCTRL_WRITE_BNDRY_256);
14100                         break;
14101                 case 512:
14102                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14103                                 DMA_RWCTRL_WRITE_BNDRY_512);
14104                         break;
14105                 case 1024:
14106                 default:
14107                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14108                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14109                         break;
14110                 }
14111         }
14112
14113 out:
14114         return val;
14115 }
14116
14117 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14118 {
14119         struct tg3_internal_buffer_desc test_desc;
14120         u32 sram_dma_descs;
14121         int i, ret;
14122
14123         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14124
14125         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14126         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14127         tw32(RDMAC_STATUS, 0);
14128         tw32(WDMAC_STATUS, 0);
14129
14130         tw32(BUFMGR_MODE, 0);
14131         tw32(FTQ_RESET, 0);
14132
14133         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14134         test_desc.addr_lo = buf_dma & 0xffffffff;
14135         test_desc.nic_mbuf = 0x00002100;
14136         test_desc.len = size;
14137
14138         /*
14139          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14140          * the *second* time the tg3 driver was getting loaded after an
14141          * initial scan.
14142          *
14143          * Broadcom tells me:
14144          *   ...the DMA engine is connected to the GRC block and a DMA
14145          *   reset may affect the GRC block in some unpredictable way...
14146          *   The behavior of resets to individual blocks has not been tested.
14147          *
14148          * Broadcom noted the GRC reset will also reset all sub-components.
14149          */
14150         if (to_device) {
14151                 test_desc.cqid_sqid = (13 << 8) | 2;
14152
14153                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14154                 udelay(40);
14155         } else {
14156                 test_desc.cqid_sqid = (16 << 8) | 7;
14157
14158                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14159                 udelay(40);
14160         }
14161         test_desc.flags = 0x00000005;
14162
14163         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14164                 u32 val;
14165
14166                 val = *(((u32 *)&test_desc) + i);
14167                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14168                                        sram_dma_descs + (i * sizeof(u32)));
14169                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14170         }
14171         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14172
14173         if (to_device)
14174                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14175         else
14176                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14177
14178         ret = -ENODEV;
14179         for (i = 0; i < 40; i++) {
14180                 u32 val;
14181
14182                 if (to_device)
14183                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14184                 else
14185                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14186                 if ((val & 0xffff) == sram_dma_descs) {
14187                         ret = 0;
14188                         break;
14189                 }
14190
14191                 udelay(100);
14192         }
14193
14194         return ret;
14195 }
14196
14197 #define TEST_BUFFER_SIZE        0x2000
14198
14199 static int __devinit tg3_test_dma(struct tg3 *tp)
14200 {
14201         dma_addr_t buf_dma;
14202         u32 *buf, saved_dma_rwctrl;
14203         int ret = 0;
14204
14205         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14206         if (!buf) {
14207                 ret = -ENOMEM;
14208                 goto out_nofree;
14209         }
14210
14211         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14212                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14213
14214         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14215
14216         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14217                 goto out;
14218
14219         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14220                 /* DMA read watermark not used on PCIE */
14221                 tp->dma_rwctrl |= 0x00180000;
14222         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14223                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14224                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14225                         tp->dma_rwctrl |= 0x003f0000;
14226                 else
14227                         tp->dma_rwctrl |= 0x003f000f;
14228         } else {
14229                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14230                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14231                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14232                         u32 read_water = 0x7;
14233
14234                         /* If the 5704 is behind the EPB bridge, we can
14235                          * do the less restrictive ONE_DMA workaround for
14236                          * better performance.
14237                          */
14238                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14239                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14240                                 tp->dma_rwctrl |= 0x8000;
14241                         else if (ccval == 0x6 || ccval == 0x7)
14242                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14243
14244                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14245                                 read_water = 4;
14246                         /* Set bit 23 to enable PCIX hw bug fix */
14247                         tp->dma_rwctrl |=
14248                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14249                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14250                                 (1 << 23);
14251                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14252                         /* 5780 always in PCIX mode */
14253                         tp->dma_rwctrl |= 0x00144000;
14254                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14255                         /* 5714 always in PCIX mode */
14256                         tp->dma_rwctrl |= 0x00148000;
14257                 } else {
14258                         tp->dma_rwctrl |= 0x001b000f;
14259                 }
14260         }
14261
14262         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14263             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14264                 tp->dma_rwctrl &= 0xfffffff0;
14265
14266         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14267             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14268                 /* Remove this if it causes problems for some boards. */
14269                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14270
14271                 /* On 5700/5701 chips, we need to set this bit.
14272                  * Otherwise the chip will issue cacheline transactions
14273                  * to streamable DMA memory with not all the byte
14274                  * enables turned on.  This is an error on several
14275                  * RISC PCI controllers, in particular sparc64.
14276                  *
14277                  * On 5703/5704 chips, this bit has been reassigned
14278                  * a different meaning.  In particular, it is used
14279                  * on those chips to enable a PCI-X workaround.
14280                  */
14281                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14282         }
14283
14284         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14285
14286 #if 0
14287         /* Unneeded, already done by tg3_get_invariants.  */
14288         tg3_switch_clocks(tp);
14289 #endif
14290
14291         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14292             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14293                 goto out;
14294
14295         /* It is best to perform DMA test with maximum write burst size
14296          * to expose the 5700/5701 write DMA bug.
14297          */
14298         saved_dma_rwctrl = tp->dma_rwctrl;
14299         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14300         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14301
14302         while (1) {
14303                 u32 *p = buf, i;
14304
14305                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14306                         p[i] = i;
14307
14308                 /* Send the buffer to the chip. */
14309                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14310                 if (ret) {
14311                         dev_err(&tp->pdev->dev,
14312                                 "%s: Buffer write failed. err = %d\n",
14313                                 __func__, ret);
14314                         break;
14315                 }
14316
14317 #if 0
14318                 /* validate data reached card RAM correctly. */
14319                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14320                         u32 val;
14321                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14322                         if (le32_to_cpu(val) != p[i]) {
14323                                 dev_err(&tp->pdev->dev,
14324                                         "%s: Buffer corrupted on device! "
14325                                         "(%d != %d)\n", __func__, val, i);
14326                                 /* ret = -ENODEV here? */
14327                         }
14328                         p[i] = 0;
14329                 }
14330 #endif
14331                 /* Now read it back. */
14332                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14333                 if (ret) {
14334                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14335                                 "err = %d\n", __func__, ret);
14336                         break;
14337                 }
14338
14339                 /* Verify it. */
14340                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14341                         if (p[i] == i)
14342                                 continue;
14343
14344                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14345                             DMA_RWCTRL_WRITE_BNDRY_16) {
14346                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14347                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14348                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14349                                 break;
14350                         } else {
14351                                 dev_err(&tp->pdev->dev,
14352                                         "%s: Buffer corrupted on read back! "
14353                                         "(%d != %d)\n", __func__, p[i], i);
14354                                 ret = -ENODEV;
14355                                 goto out;
14356                         }
14357                 }
14358
14359                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14360                         /* Success. */
14361                         ret = 0;
14362                         break;
14363                 }
14364         }
14365         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14366             DMA_RWCTRL_WRITE_BNDRY_16) {
14367                 static struct pci_device_id dma_wait_state_chipsets[] = {
14368                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14369                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14370                         { },
14371                 };
14372
14373                 /* DMA test passed without adjusting DMA boundary,
14374                  * now look for chipsets that are known to expose the
14375                  * DMA bug without failing the test.
14376                  */
14377                 if (pci_dev_present(dma_wait_state_chipsets)) {
14378                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14379                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14380                 } else {
14381                         /* Safe to use the calculated DMA boundary. */
14382                         tp->dma_rwctrl = saved_dma_rwctrl;
14383                 }
14384
14385                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14386         }
14387
14388 out:
14389         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14390 out_nofree:
14391         return ret;
14392 }
14393
14394 static void __devinit tg3_init_link_config(struct tg3 *tp)
14395 {
14396         tp->link_config.advertising =
14397                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14398                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14399                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14400                  ADVERTISED_Autoneg | ADVERTISED_MII);
14401         tp->link_config.speed = SPEED_INVALID;
14402         tp->link_config.duplex = DUPLEX_INVALID;
14403         tp->link_config.autoneg = AUTONEG_ENABLE;
14404         tp->link_config.active_speed = SPEED_INVALID;
14405         tp->link_config.active_duplex = DUPLEX_INVALID;
14406         tp->link_config.orig_speed = SPEED_INVALID;
14407         tp->link_config.orig_duplex = DUPLEX_INVALID;
14408         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14409 }
14410
14411 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14412 {
14413         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14414                 tp->bufmgr_config.mbuf_read_dma_low_water =
14415                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14416                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14417                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14418                 tp->bufmgr_config.mbuf_high_water =
14419                         DEFAULT_MB_HIGH_WATER_57765;
14420
14421                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14422                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14423                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14424                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14425                 tp->bufmgr_config.mbuf_high_water_jumbo =
14426                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14427         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14428                 tp->bufmgr_config.mbuf_read_dma_low_water =
14429                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14430                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14431                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14432                 tp->bufmgr_config.mbuf_high_water =
14433                         DEFAULT_MB_HIGH_WATER_5705;
14434                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14435                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14436                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14437                         tp->bufmgr_config.mbuf_high_water =
14438                                 DEFAULT_MB_HIGH_WATER_5906;
14439                 }
14440
14441                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14442                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14443                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14444                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14445                 tp->bufmgr_config.mbuf_high_water_jumbo =
14446                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14447         } else {
14448                 tp->bufmgr_config.mbuf_read_dma_low_water =
14449                         DEFAULT_MB_RDMA_LOW_WATER;
14450                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14451                         DEFAULT_MB_MACRX_LOW_WATER;
14452                 tp->bufmgr_config.mbuf_high_water =
14453                         DEFAULT_MB_HIGH_WATER;
14454
14455                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14456                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14457                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14458                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14459                 tp->bufmgr_config.mbuf_high_water_jumbo =
14460                         DEFAULT_MB_HIGH_WATER_JUMBO;
14461         }
14462
14463         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14464         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14465 }
14466
14467 static char * __devinit tg3_phy_string(struct tg3 *tp)
14468 {
14469         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14470         case TG3_PHY_ID_BCM5400:        return "5400";
14471         case TG3_PHY_ID_BCM5401:        return "5401";
14472         case TG3_PHY_ID_BCM5411:        return "5411";
14473         case TG3_PHY_ID_BCM5701:        return "5701";
14474         case TG3_PHY_ID_BCM5703:        return "5703";
14475         case TG3_PHY_ID_BCM5704:        return "5704";
14476         case TG3_PHY_ID_BCM5705:        return "5705";
14477         case TG3_PHY_ID_BCM5750:        return "5750";
14478         case TG3_PHY_ID_BCM5752:        return "5752";
14479         case TG3_PHY_ID_BCM5714:        return "5714";
14480         case TG3_PHY_ID_BCM5780:        return "5780";
14481         case TG3_PHY_ID_BCM5755:        return "5755";
14482         case TG3_PHY_ID_BCM5787:        return "5787";
14483         case TG3_PHY_ID_BCM5784:        return "5784";
14484         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14485         case TG3_PHY_ID_BCM5906:        return "5906";
14486         case TG3_PHY_ID_BCM5761:        return "5761";
14487         case TG3_PHY_ID_BCM5718C:       return "5718C";
14488         case TG3_PHY_ID_BCM5718S:       return "5718S";
14489         case TG3_PHY_ID_BCM57765:       return "57765";
14490         case TG3_PHY_ID_BCM5719C:       return "5719C";
14491         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14492         case 0:                 return "serdes";
14493         default:                return "unknown";
14494         }
14495 }
14496
14497 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14498 {
14499         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14500                 strcpy(str, "PCI Express");
14501                 return str;
14502         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14503                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14504
14505                 strcpy(str, "PCIX:");
14506
14507                 if ((clock_ctrl == 7) ||
14508                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14509                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14510                         strcat(str, "133MHz");
14511                 else if (clock_ctrl == 0)
14512                         strcat(str, "33MHz");
14513                 else if (clock_ctrl == 2)
14514                         strcat(str, "50MHz");
14515                 else if (clock_ctrl == 4)
14516                         strcat(str, "66MHz");
14517                 else if (clock_ctrl == 6)
14518                         strcat(str, "100MHz");
14519         } else {
14520                 strcpy(str, "PCI:");
14521                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14522                         strcat(str, "66MHz");
14523                 else
14524                         strcat(str, "33MHz");
14525         }
14526         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14527                 strcat(str, ":32-bit");
14528         else
14529                 strcat(str, ":64-bit");
14530         return str;
14531 }
14532
14533 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14534 {
14535         struct pci_dev *peer;
14536         unsigned int func, devnr = tp->pdev->devfn & ~7;
14537
14538         for (func = 0; func < 8; func++) {
14539                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14540                 if (peer && peer != tp->pdev)
14541                         break;
14542                 pci_dev_put(peer);
14543         }
14544         /* 5704 can be configured in single-port mode, set peer to
14545          * tp->pdev in that case.
14546          */
14547         if (!peer) {
14548                 peer = tp->pdev;
14549                 return peer;
14550         }
14551
14552         /*
14553          * We don't need to keep the refcount elevated; there's no way
14554          * to remove one half of this device without removing the other
14555          */
14556         pci_dev_put(peer);
14557
14558         return peer;
14559 }
14560
14561 static void __devinit tg3_init_coal(struct tg3 *tp)
14562 {
14563         struct ethtool_coalesce *ec = &tp->coal;
14564
14565         memset(ec, 0, sizeof(*ec));
14566         ec->cmd = ETHTOOL_GCOALESCE;
14567         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14568         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14569         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14570         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14571         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14572         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14573         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14574         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14575         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14576
14577         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14578                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14579                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14580                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14581                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14582                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14583         }
14584
14585         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14586                 ec->rx_coalesce_usecs_irq = 0;
14587                 ec->tx_coalesce_usecs_irq = 0;
14588                 ec->stats_block_coalesce_usecs = 0;
14589         }
14590 }
14591
14592 static const struct net_device_ops tg3_netdev_ops = {
14593         .ndo_open               = tg3_open,
14594         .ndo_stop               = tg3_close,
14595         .ndo_start_xmit         = tg3_start_xmit,
14596         .ndo_get_stats64        = tg3_get_stats64,
14597         .ndo_validate_addr      = eth_validate_addr,
14598         .ndo_set_multicast_list = tg3_set_rx_mode,
14599         .ndo_set_mac_address    = tg3_set_mac_addr,
14600         .ndo_do_ioctl           = tg3_ioctl,
14601         .ndo_tx_timeout         = tg3_tx_timeout,
14602         .ndo_change_mtu         = tg3_change_mtu,
14603 #if TG3_VLAN_TAG_USED
14604         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14605 #endif
14606 #ifdef CONFIG_NET_POLL_CONTROLLER
14607         .ndo_poll_controller    = tg3_poll_controller,
14608 #endif
14609 };
14610
14611 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14612         .ndo_open               = tg3_open,
14613         .ndo_stop               = tg3_close,
14614         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14615         .ndo_get_stats64        = tg3_get_stats64,
14616         .ndo_validate_addr      = eth_validate_addr,
14617         .ndo_set_multicast_list = tg3_set_rx_mode,
14618         .ndo_set_mac_address    = tg3_set_mac_addr,
14619         .ndo_do_ioctl           = tg3_ioctl,
14620         .ndo_tx_timeout         = tg3_tx_timeout,
14621         .ndo_change_mtu         = tg3_change_mtu,
14622 #if TG3_VLAN_TAG_USED
14623         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14624 #endif
14625 #ifdef CONFIG_NET_POLL_CONTROLLER
14626         .ndo_poll_controller    = tg3_poll_controller,
14627 #endif
14628 };
14629
14630 static int __devinit tg3_init_one(struct pci_dev *pdev,
14631                                   const struct pci_device_id *ent)
14632 {
14633         struct net_device *dev;
14634         struct tg3 *tp;
14635         int i, err, pm_cap;
14636         u32 sndmbx, rcvmbx, intmbx;
14637         char str[40];
14638         u64 dma_mask, persist_dma_mask;
14639
14640         printk_once(KERN_INFO "%s\n", version);
14641
14642         err = pci_enable_device(pdev);
14643         if (err) {
14644                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14645                 return err;
14646         }
14647
14648         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14649         if (err) {
14650                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14651                 goto err_out_disable_pdev;
14652         }
14653
14654         pci_set_master(pdev);
14655
14656         /* Find power-management capability. */
14657         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14658         if (pm_cap == 0) {
14659                 dev_err(&pdev->dev,
14660                         "Cannot find Power Management capability, aborting\n");
14661                 err = -EIO;
14662                 goto err_out_free_res;
14663         }
14664
14665         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14666         if (!dev) {
14667                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14668                 err = -ENOMEM;
14669                 goto err_out_free_res;
14670         }
14671
14672         SET_NETDEV_DEV(dev, &pdev->dev);
14673
14674 #if TG3_VLAN_TAG_USED
14675         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14676 #endif
14677
14678         tp = netdev_priv(dev);
14679         tp->pdev = pdev;
14680         tp->dev = dev;
14681         tp->pm_cap = pm_cap;
14682         tp->rx_mode = TG3_DEF_RX_MODE;
14683         tp->tx_mode = TG3_DEF_TX_MODE;
14684
14685         if (tg3_debug > 0)
14686                 tp->msg_enable = tg3_debug;
14687         else
14688                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14689
14690         /* The word/byte swap controls here control register access byte
14691          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14692          * setting below.
14693          */
14694         tp->misc_host_ctrl =
14695                 MISC_HOST_CTRL_MASK_PCI_INT |
14696                 MISC_HOST_CTRL_WORD_SWAP |
14697                 MISC_HOST_CTRL_INDIR_ACCESS |
14698                 MISC_HOST_CTRL_PCISTATE_RW;
14699
14700         /* The NONFRM (non-frame) byte/word swap controls take effect
14701          * on descriptor entries, anything which isn't packet data.
14702          *
14703          * The StrongARM chips on the board (one for tx, one for rx)
14704          * are running in big-endian mode.
14705          */
14706         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14707                         GRC_MODE_WSWAP_NONFRM_DATA);
14708 #ifdef __BIG_ENDIAN
14709         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14710 #endif
14711         spin_lock_init(&tp->lock);
14712         spin_lock_init(&tp->indirect_lock);
14713         INIT_WORK(&tp->reset_task, tg3_reset_task);
14714
14715         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14716         if (!tp->regs) {
14717                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14718                 err = -ENOMEM;
14719                 goto err_out_free_dev;
14720         }
14721
14722         tg3_init_link_config(tp);
14723
14724         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14725         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14726
14727         dev->ethtool_ops = &tg3_ethtool_ops;
14728         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14729         dev->irq = pdev->irq;
14730
14731         err = tg3_get_invariants(tp);
14732         if (err) {
14733                 dev_err(&pdev->dev,
14734                         "Problem fetching invariants of chip, aborting\n");
14735                 goto err_out_iounmap;
14736         }
14737
14738         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14739             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14740             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14741                 dev->netdev_ops = &tg3_netdev_ops;
14742         else
14743                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14744
14745
14746         /* The EPB bridge inside 5714, 5715, and 5780 and any
14747          * device behind the EPB cannot support DMA addresses > 40-bit.
14748          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14749          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14750          * do DMA address check in tg3_start_xmit().
14751          */
14752         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14753                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14754         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14755                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14756 #ifdef CONFIG_HIGHMEM
14757                 dma_mask = DMA_BIT_MASK(64);
14758 #endif
14759         } else
14760                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14761
14762         /* Configure DMA attributes. */
14763         if (dma_mask > DMA_BIT_MASK(32)) {
14764                 err = pci_set_dma_mask(pdev, dma_mask);
14765                 if (!err) {
14766                         dev->features |= NETIF_F_HIGHDMA;
14767                         err = pci_set_consistent_dma_mask(pdev,
14768                                                           persist_dma_mask);
14769                         if (err < 0) {
14770                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14771                                         "DMA for consistent allocations\n");
14772                                 goto err_out_iounmap;
14773                         }
14774                 }
14775         }
14776         if (err || dma_mask == DMA_BIT_MASK(32)) {
14777                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14778                 if (err) {
14779                         dev_err(&pdev->dev,
14780                                 "No usable DMA configuration, aborting\n");
14781                         goto err_out_iounmap;
14782                 }
14783         }
14784
14785         tg3_init_bufmgr_config(tp);
14786
14787         /* Selectively allow TSO based on operating conditions */
14788         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14789             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14790                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14791         else {
14792                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14793                 tp->fw_needed = NULL;
14794         }
14795
14796         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14797                 tp->fw_needed = FIRMWARE_TG3;
14798
14799         /* TSO is on by default on chips that support hardware TSO.
14800          * Firmware TSO on older chips gives lower performance, so it
14801          * is off by default, but can be enabled using ethtool.
14802          */
14803         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14804             (dev->features & NETIF_F_IP_CSUM)) {
14805                 dev->features |= NETIF_F_TSO;
14806                 vlan_features_add(dev, NETIF_F_TSO);
14807         }
14808         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14809             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14810                 if (dev->features & NETIF_F_IPV6_CSUM) {
14811                         dev->features |= NETIF_F_TSO6;
14812                         vlan_features_add(dev, NETIF_F_TSO6);
14813                 }
14814                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14815                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14816                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14817                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14818                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14819                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14820                         dev->features |= NETIF_F_TSO_ECN;
14821                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14822                 }
14823         }
14824
14825         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14826             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14827             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14828                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14829                 tp->rx_pending = 63;
14830         }
14831
14832         err = tg3_get_device_address(tp);
14833         if (err) {
14834                 dev_err(&pdev->dev,
14835                         "Could not obtain valid ethernet address, aborting\n");
14836                 goto err_out_iounmap;
14837         }
14838
14839         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14840                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14841                 if (!tp->aperegs) {
14842                         dev_err(&pdev->dev,
14843                                 "Cannot map APE registers, aborting\n");
14844                         err = -ENOMEM;
14845                         goto err_out_iounmap;
14846                 }
14847
14848                 tg3_ape_lock_init(tp);
14849
14850                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14851                         tg3_read_dash_ver(tp);
14852         }
14853
14854         /*
14855          * Reset chip in case UNDI or EFI driver did not shutdown
14856          * DMA self test will enable WDMAC and we'll see (spurious)
14857          * pending DMA on the PCI bus at that point.
14858          */
14859         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14860             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14861                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14862                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14863         }
14864
14865         err = tg3_test_dma(tp);
14866         if (err) {
14867                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14868                 goto err_out_apeunmap;
14869         }
14870
14871         /* flow control autonegotiation is default behavior */
14872         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14873         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14874
14875         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14876         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14877         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14878         for (i = 0; i < tp->irq_max; i++) {
14879                 struct tg3_napi *tnapi = &tp->napi[i];
14880
14881                 tnapi->tp = tp;
14882                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14883
14884                 tnapi->int_mbox = intmbx;
14885                 if (i < 4)
14886                         intmbx += 0x8;
14887                 else
14888                         intmbx += 0x4;
14889
14890                 tnapi->consmbox = rcvmbx;
14891                 tnapi->prodmbox = sndmbx;
14892
14893                 if (i)
14894                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14895                 else
14896                         tnapi->coal_now = HOSTCC_MODE_NOW;
14897
14898                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14899                         break;
14900
14901                 /*
14902                  * If we support MSIX, we'll be using RSS.  If we're using
14903                  * RSS, the first vector only handles link interrupts and the
14904                  * remaining vectors handle rx and tx interrupts.  Reuse the
14905                  * mailbox values for the next iteration.  The values we setup
14906                  * above are still useful for the single vectored mode.
14907                  */
14908                 if (!i)
14909                         continue;
14910
14911                 rcvmbx += 0x8;
14912
14913                 if (sndmbx & 0x4)
14914                         sndmbx -= 0x4;
14915                 else
14916                         sndmbx += 0xc;
14917         }
14918
14919         tg3_init_coal(tp);
14920
14921         pci_set_drvdata(pdev, dev);
14922
14923         err = register_netdev(dev);
14924         if (err) {
14925                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14926                 goto err_out_apeunmap;
14927         }
14928
14929         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14930                     tp->board_part_number,
14931                     tp->pci_chip_rev_id,
14932                     tg3_bus_string(tp, str),
14933                     dev->dev_addr);
14934
14935         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14936                 struct phy_device *phydev;
14937                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14938                 netdev_info(dev,
14939                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14940                             phydev->drv->name, dev_name(&phydev->dev));
14941         } else {
14942                 char *ethtype;
14943
14944                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14945                         ethtype = "10/100Base-TX";
14946                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14947                         ethtype = "1000Base-SX";
14948                 else
14949                         ethtype = "10/100/1000Base-T";
14950
14951                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14952                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14953                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14954         }
14955
14956         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14957                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14958                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14959                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14960                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14961                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14962         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14963                     tp->dma_rwctrl,
14964                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14965                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14966
14967         return 0;
14968
14969 err_out_apeunmap:
14970         if (tp->aperegs) {
14971                 iounmap(tp->aperegs);
14972                 tp->aperegs = NULL;
14973         }
14974
14975 err_out_iounmap:
14976         if (tp->regs) {
14977                 iounmap(tp->regs);
14978                 tp->regs = NULL;
14979         }
14980
14981 err_out_free_dev:
14982         free_netdev(dev);
14983
14984 err_out_free_res:
14985         pci_release_regions(pdev);
14986
14987 err_out_disable_pdev:
14988         pci_disable_device(pdev);
14989         pci_set_drvdata(pdev, NULL);
14990         return err;
14991 }
14992
14993 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14994 {
14995         struct net_device *dev = pci_get_drvdata(pdev);
14996
14997         if (dev) {
14998                 struct tg3 *tp = netdev_priv(dev);
14999
15000                 if (tp->fw)
15001                         release_firmware(tp->fw);
15002
15003                 flush_scheduled_work();
15004
15005                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15006                         tg3_phy_fini(tp);
15007                         tg3_mdio_fini(tp);
15008                 }
15009
15010                 unregister_netdev(dev);
15011                 if (tp->aperegs) {
15012                         iounmap(tp->aperegs);
15013                         tp->aperegs = NULL;
15014                 }
15015                 if (tp->regs) {
15016                         iounmap(tp->regs);
15017                         tp->regs = NULL;
15018                 }
15019                 free_netdev(dev);
15020                 pci_release_regions(pdev);
15021                 pci_disable_device(pdev);
15022                 pci_set_drvdata(pdev, NULL);
15023         }
15024 }
15025
15026 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
15027 {
15028         struct net_device *dev = pci_get_drvdata(pdev);
15029         struct tg3 *tp = netdev_priv(dev);
15030         pci_power_t target_state;
15031         int err;
15032
15033         /* PCI register 4 needs to be saved whether netif_running() or not.
15034          * MSI address and data need to be saved if using MSI and
15035          * netif_running().
15036          */
15037         pci_save_state(pdev);
15038
15039         if (!netif_running(dev))
15040                 return 0;
15041
15042         flush_scheduled_work();
15043         tg3_phy_stop(tp);
15044         tg3_netif_stop(tp);
15045
15046         del_timer_sync(&tp->timer);
15047
15048         tg3_full_lock(tp, 1);
15049         tg3_disable_ints(tp);
15050         tg3_full_unlock(tp);
15051
15052         netif_device_detach(dev);
15053
15054         tg3_full_lock(tp, 0);
15055         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15056         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15057         tg3_full_unlock(tp);
15058
15059         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15060
15061         err = tg3_set_power_state(tp, target_state);
15062         if (err) {
15063                 int err2;
15064
15065                 tg3_full_lock(tp, 0);
15066
15067                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15068                 err2 = tg3_restart_hw(tp, 1);
15069                 if (err2)
15070                         goto out;
15071
15072                 tp->timer.expires = jiffies + tp->timer_offset;
15073                 add_timer(&tp->timer);
15074
15075                 netif_device_attach(dev);
15076                 tg3_netif_start(tp);
15077
15078 out:
15079                 tg3_full_unlock(tp);
15080
15081                 if (!err2)
15082                         tg3_phy_start(tp);
15083         }
15084
15085         return err;
15086 }
15087
15088 static int tg3_resume(struct pci_dev *pdev)
15089 {
15090         struct net_device *dev = pci_get_drvdata(pdev);
15091         struct tg3 *tp = netdev_priv(dev);
15092         int err;
15093
15094         pci_restore_state(tp->pdev);
15095
15096         if (!netif_running(dev))
15097                 return 0;
15098
15099         err = tg3_set_power_state(tp, PCI_D0);
15100         if (err)
15101                 return err;
15102
15103         netif_device_attach(dev);
15104
15105         tg3_full_lock(tp, 0);
15106
15107         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15108         err = tg3_restart_hw(tp, 1);
15109         if (err)
15110                 goto out;
15111
15112         tp->timer.expires = jiffies + tp->timer_offset;
15113         add_timer(&tp->timer);
15114
15115         tg3_netif_start(tp);
15116
15117 out:
15118         tg3_full_unlock(tp);
15119
15120         if (!err)
15121                 tg3_phy_start(tp);
15122
15123         return err;
15124 }
15125
15126 static struct pci_driver tg3_driver = {
15127         .name           = DRV_MODULE_NAME,
15128         .id_table       = tg3_pci_tbl,
15129         .probe          = tg3_init_one,
15130         .remove         = __devexit_p(tg3_remove_one),
15131         .suspend        = tg3_suspend,
15132         .resume         = tg3_resume
15133 };
15134
15135 static int __init tg3_init(void)
15136 {
15137         return pci_register_driver(&tg3_driver);
15138 }
15139
15140 static void __exit tg3_cleanup(void)
15141 {
15142         pci_unregister_driver(&tg3_driver);
15143 }
15144
15145 module_init(tg3_init);
15146 module_exit(tg3_cleanup);