drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   Cougar Point (PCH)    0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49
  50   Features supported by this driver:
  51   Software PEC                     no
  52   Hardware PEC                     yes
  53   Block buffer                     yes
  54   Block process call transaction   no
  55   I2C block read transaction       yes  (doesn't use the block buffer)
  56
  57   See the file Documentation/i2c/busses/i2c-i801 for details.
  58 */
  59
  60 #include <linux/module.h>
  61 #include <linux/pci.h>
  62 #include <linux/kernel.h>
  63 #include <linux/stddef.h>
  64 #include <linux/delay.h>
  65 #include <linux/ioport.h>
  66 #include <linux/init.h>
  67 #include <linux/i2c.h>
  68 #include <linux/acpi.h>
  69 #include <linux/io.h>
  70 #include <linux/dmi.h>
  71
  72 /* I801 SMBus address offsets */
  73 #define SMBHSTSTS(p)    (0 + (p)->smba)
  74 #define SMBHSTCNT(p)    (2 + (p)->smba)
  75 #define SMBHSTCMD(p)    (3 + (p)->smba)
  76 #define SMBHSTADD(p)    (4 + (p)->smba)
  77 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  78 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  79 #define SMBBLKDAT(p)    (7 + (p)->smba)
  80 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  81 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  82 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
  83
  84 /* PCI Address Constants */
  85 #define SMBBAR          4
  86 #define SMBHSTCFG       0x040
  87
  88 /* Host configuration bits for SMBHSTCFG */
  89 #define SMBHSTCFG_HST_EN        1
  90 #define SMBHSTCFG_SMB_SMI_EN    2
  91 #define SMBHSTCFG_I2C_EN        4
  92
  93 /* Auxillary control register bits, ICH4+ only */
  94 #define SMBAUXCTL_CRC           1
  95 #define SMBAUXCTL_E32B          2
  96
  97 /* kill bit for SMBHSTCNT */
  98 #define SMBHSTCNT_KILL          2
  99
 100 /* Other settings */
 101 #define MAX_TIMEOUT             100
 102 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 103
 104 /* I801 command constants */
 105 #define I801_QUICK              0x00
 106 #define I801_BYTE               0x04
 107 #define I801_BYTE_DATA          0x08
 108 #define I801_WORD_DATA          0x0C
 109 #define I801_PROC_CALL          0x10    /* unimplemented */
 110 #define I801_BLOCK_DATA         0x14
 111 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 112 #define I801_BLOCK_LAST         0x34
 113 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 114 #define I801_START              0x40
 115 #define I801_PEC_EN             0x80    /* ICH3 and later */
 116
 117 /* I801 Hosts Status register bits */
 118 #define SMBHSTSTS_BYTE_DONE     0x80
 119 #define SMBHSTSTS_INUSE_STS     0x40
 120 #define SMBHSTSTS_SMBALERT_STS  0x20
 121 #define SMBHSTSTS_FAILED        0x10
 122 #define SMBHSTSTS_BUS_ERR       0x08
 123 #define SMBHSTSTS_DEV_ERR       0x04
 124 #define SMBHSTSTS_INTR          0x02
 125 #define SMBHSTSTS_HOST_BUSY     0x01
 126
 127 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 128                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 129                                  SMBHSTSTS_INTR)
 130
 131 struct i801_priv {
 132         struct i2c_adapter adapter;
 133         unsigned long smba;
 134         unsigned char original_hstcfg;
 135         struct pci_dev *pci_dev;
 136         unsigned int features;
 137 };
 138
 139 static struct pci_driver i801_driver;
 140
 141 #define FEATURE_SMBUS_PEC       (1 << 0)
 142 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 143 #define FEATURE_BLOCK_PROC      (1 << 2)
 144 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 145
 146 static const char *i801_feature_names[] = {
 147         "SMBus PEC",
 148         "Block buffer",
 149         "Block process call",
 150         "I2C block read",
 151 };
 152
 153 static unsigned int disable_features;
 154 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 155 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 156
 157 /* Make sure the SMBus host is ready to start transmitting.
 158    Return 0 if it is, -EBUSY if it is not. */
 159 static int i801_check_pre(struct i801_priv *priv)
 160 {
 161         int status;
 162
 163         status = inb_p(SMBHSTSTS(priv));
 164         if (status & SMBHSTSTS_HOST_BUSY) {
 165                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 166                 return -EBUSY;
 167         }
 168
 169         status &= STATUS_FLAGS;
 170         if (status) {
 171                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 172                         status);
 173                 outb_p(status, SMBHSTSTS(priv));
 174                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 175                 if (status) {
 176                         dev_err(&priv->pci_dev->dev,
 177                                 "Failed clearing status flags (%02x)\n",
 178                                 status);
 179                         return -EBUSY;
 180                 }
 181         }
 182
 183         return 0;
 184 }
 185
 186 /* Convert the status register to an error code, and clear it. */
 187 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 188 {
 189         int result = 0;
 190
 191         /* If the SMBus is still busy, we give up */
 192         if (timeout) {
 193                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 194                 /* try to stop the current command */
 195                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 196                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 197                        SMBHSTCNT(priv));
 198                 msleep(1);
 199                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 200                        SMBHSTCNT(priv));
 201
 202                 /* Check if it worked */
 203                 status = inb_p(SMBHSTSTS(priv));
 204                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 205                     !(status & SMBHSTSTS_FAILED))
 206                         dev_err(&priv->pci_dev->dev,
 207                                 "Failed terminating the transaction\n");
 208                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 209                 return -ETIMEDOUT;
 210         }
 211
 212         if (status & SMBHSTSTS_FAILED) {
 213                 result = -EIO;
 214                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 215         }
 216         if (status & SMBHSTSTS_DEV_ERR) {
 217                 result = -ENXIO;
 218                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 219         }
 220         if (status & SMBHSTSTS_BUS_ERR) {
 221                 result = -EAGAIN;
 222                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 223         }
 224
 225         if (result) {
 226                 /* Clear error flags */
 227                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 228                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 229                 if (status) {
 230                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 231                                  "flags at end of transaction (%02x)\n",
 232                                  status);
 233                 }
 234         }
 235
 236         return result;
 237 }
 238
 239 static int i801_transaction(struct i801_priv *priv, int xact)
 240 {
 241         int status;
 242         int result;
 243         int timeout = 0;
 244
 245         result = i801_check_pre(priv);
 246         if (result < 0)
 247                 return result;
 248
 249         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 250          * INTREN, SMBSCMD are passed in xact */
 251         outb_p(xact | I801_START, SMBHSTCNT(priv));
 252
 253         /* We will always wait for a fraction of a second! */
 254         do {
 255                 msleep(1);
 256                 status = inb_p(SMBHSTSTS(priv));
 257         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 258
 259         result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 260         if (result < 0)
 261                 return result;
 262
 263         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 264         return 0;
 265 }
 266
 267 /* wait for INTR bit as advised by Intel */
 268 static void i801_wait_hwpec(struct i801_priv *priv)
 269 {
 270         int timeout = 0;
 271         int status;
 272
 273         do {
 274                 msleep(1);
 275                 status = inb_p(SMBHSTSTS(priv));
 276         } while ((!(status & SMBHSTSTS_INTR))
 277                  && (timeout++ < MAX_TIMEOUT));
 278
 279         if (timeout > MAX_TIMEOUT)
 280                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 281
 282         outb_p(status, SMBHSTSTS(priv));
 283 }
 284
 285 static int i801_block_transaction_by_block(struct i801_priv *priv,
 286                                            union i2c_smbus_data *data,
 287                                            char read_write, int hwpec)
 288 {
 289         int i, len;
 290         int status;
 291
 292         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 293
 294         /* Use 32-byte buffer to process this transaction */
 295         if (read_write == I2C_SMBUS_WRITE) {
 296                 len = data->block[0];
 297                 outb_p(len, SMBHSTDAT0(priv));
 298                 for (i = 0; i < len; i++)
 299                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 300         }
 301
 302         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 303                                   I801_PEC_EN * hwpec);
 304         if (status)
 305                 return status;
 306
 307         if (read_write == I2C_SMBUS_READ) {
 308                 len = inb_p(SMBHSTDAT0(priv));
 309                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 310                         return -EPROTO;
 311
 312                 data->block[0] = len;
 313                 for (i = 0; i < len; i++)
 314                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 315         }
 316         return 0;
 317 }
 318
 319 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 320                                                union i2c_smbus_data *data,
 321                                                char read_write, int command,
 322                                                int hwpec)
 323 {
 324         int i, len;
 325         int smbcmd;
 326         int status;
 327         int result;
 328         int timeout;
 329
 330         result = i801_check_pre(priv);
 331         if (result < 0)
 332                 return result;
 333
 334         len = data->block[0];
 335
 336         if (read_write == I2C_SMBUS_WRITE) {
 337                 outb_p(len, SMBHSTDAT0(priv));
 338                 outb_p(data->block[1], SMBBLKDAT(priv));
 339         }
 340
 341         for (i = 1; i <= len; i++) {
 342                 if (i == len && read_write == I2C_SMBUS_READ) {
 343                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 344                                 smbcmd = I801_I2C_BLOCK_LAST;
 345                         else
 346                                 smbcmd = I801_BLOCK_LAST;
 347                 } else {
 348                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 349                          && read_write == I2C_SMBUS_READ)
 350                                 smbcmd = I801_I2C_BLOCK_DATA;
 351                         else
 352                                 smbcmd = I801_BLOCK_DATA;
 353                 }
 354                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 355
 356                 if (i == 1)
 357                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 358                                SMBHSTCNT(priv));
 359
 360                 /* We will always wait for a fraction of a second! */
 361                 timeout = 0;
 362                 do {
 363                         msleep(1);
 364                         status = inb_p(SMBHSTSTS(priv));
 365                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 366                          && (timeout++ < MAX_TIMEOUT));
 367
 368                 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
 369                 if (result < 0)
 370                         return result;
 371
 372                 if (i == 1 && read_write == I2C_SMBUS_READ
 373                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 374                         len = inb_p(SMBHSTDAT0(priv));
 375                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 376                                 dev_err(&priv->pci_dev->dev,
 377                                         "Illegal SMBus block read size %d\n",
 378                                         len);
 379                                 /* Recover */
 380                                 while (inb_p(SMBHSTSTS(priv)) &
 381                                        SMBHSTSTS_HOST_BUSY)
 382                                         outb_p(SMBHSTSTS_BYTE_DONE,
 383                                                SMBHSTSTS(priv));
 384                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 385                                 return -EPROTO;
 386                         }
 387                         data->block[0] = len;
 388                 }
 389
 390                 /* Retrieve/store value in SMBBLKDAT */
 391                 if (read_write == I2C_SMBUS_READ)
 392                         data->block[i] = inb_p(SMBBLKDAT(priv));
 393                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 394                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 395
 396                 /* signals SMBBLKDAT ready */
 397                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 404 {
 405         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 406         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 407                 return -EIO;
 408         return 0;
 409 }
 410
 411 /* Block transaction function */
 412 static int i801_block_transaction(struct i801_priv *priv,
 413                                   union i2c_smbus_data *data, char read_write,
 414                                   int command, int hwpec)
 415 {
 416         int result = 0;
 417         unsigned char hostc;
 418
 419         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 420                 if (read_write == I2C_SMBUS_WRITE) {
 421                         /* set I2C_EN bit in configuration register */
 422                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 423                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 424                                               hostc | SMBHSTCFG_I2C_EN);
 425                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 426                         dev_err(&priv->pci_dev->dev,
 427                                 "I2C block read is unsupported!\n");
 428                         return -EOPNOTSUPP;
 429                 }
 430         }
 431
 432         if (read_write == I2C_SMBUS_WRITE
 433          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 434                 if (data->block[0] < 1)
 435                         data->block[0] = 1;
 436                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 437                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 438         } else {
 439                 data->block[0] = 32;    /* max for SMBus block reads */
 440         }
 441
 442         /* Experience has shown that the block buffer can only be used for
 443            SMBus (not I2C) block transactions, even though the datasheet
 444            doesn't mention this limitation. */
 445         if ((priv->features & FEATURE_BLOCK_BUFFER)
 446          && command != I2C_SMBUS_I2C_BLOCK_DATA
 447          && i801_set_block_buffer_mode(priv) == 0)
 448                 result = i801_block_transaction_by_block(priv, data,
 449                                                          read_write, hwpec);
 450         else
 451                 result = i801_block_transaction_byte_by_byte(priv, data,
 452                                                              read_write,
 453                                                              command, hwpec);
 454
 455         if (result == 0 && hwpec)
 456                 i801_wait_hwpec(priv);
 457
 458         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 459          && read_write == I2C_SMBUS_WRITE) {
 460                 /* restore saved configuration register value */
 461                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 462         }
 463         return result;
 464 }
 465
 466 /* Return negative errno on error. */
 467 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 468                        unsigned short flags, char read_write, u8 command,
 469                        int size, union i2c_smbus_data *data)
 470 {
 471         int hwpec;
 472         int block = 0;
 473         int ret, xact = 0;
 474         struct i801_priv *priv = i2c_get_adapdata(adap);
 475
 476         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 477                 && size != I2C_SMBUS_QUICK
 478                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 479
 480         switch (size) {
 481         case I2C_SMBUS_QUICK:
 482                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 483                        SMBHSTADD(priv));
 484                 xact = I801_QUICK;
 485                 break;
 486         case I2C_SMBUS_BYTE:
 487                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 488                        SMBHSTADD(priv));
 489                 if (read_write == I2C_SMBUS_WRITE)
 490                         outb_p(command, SMBHSTCMD(priv));
 491                 xact = I801_BYTE;
 492                 break;
 493         case I2C_SMBUS_BYTE_DATA:
 494                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 495                        SMBHSTADD(priv));
 496                 outb_p(command, SMBHSTCMD(priv));
 497                 if (read_write == I2C_SMBUS_WRITE)
 498                         outb_p(data->byte, SMBHSTDAT0(priv));
 499                 xact = I801_BYTE_DATA;
 500                 break;
 501         case I2C_SMBUS_WORD_DATA:
 502                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 503                        SMBHSTADD(priv));
 504                 outb_p(command, SMBHSTCMD(priv));
 505                 if (read_write == I2C_SMBUS_WRITE) {
 506                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 507                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 508                 }
 509                 xact = I801_WORD_DATA;
 510                 break;
 511         case I2C_SMBUS_BLOCK_DATA:
 512                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 513                        SMBHSTADD(priv));
 514                 outb_p(command, SMBHSTCMD(priv));
 515                 block = 1;
 516                 break;
 517         case I2C_SMBUS_I2C_BLOCK_DATA:
 518                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 519                  * bit should be cleared here, even when reading */
 520                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 521                 if (read_write == I2C_SMBUS_READ) {
 522                         /* NB: page 240 of ICH5 datasheet also shows
 523                          * that DATA1 is the cmd field when reading */
 524                         outb_p(command, SMBHSTDAT1(priv));
 525                 } else
 526                         outb_p(command, SMBHSTCMD(priv));
 527                 block = 1;
 528                 break;
 529         default:
 530                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 531                         size);
 532                 return -EOPNOTSUPP;
 533         }
 534
 535         if (hwpec)      /* enable/disable hardware PEC */
 536                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 537         else
 538                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 539                        SMBAUXCTL(priv));
 540
 541         if (block)
 542                 ret = i801_block_transaction(priv, data, read_write, size,
 543                                              hwpec);
 544         else
 545                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 546
 547         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 548            time, so we forcibly disable it after every transaction. Turn off
 549            E32B for the same reason. */
 550         if (hwpec || block)
 551                 outb_p(inb_p(SMBAUXCTL(priv)) &
 552                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 553
 554         if (block)
 555                 return ret;
 556         if (ret)
 557                 return ret;
 558         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 559                 return 0;
 560
 561         switch (xact & 0x7f) {
 562         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 563         case I801_BYTE_DATA:
 564                 data->byte = inb_p(SMBHSTDAT0(priv));
 565                 break;
 566         case I801_WORD_DATA:
 567                 data->word = inb_p(SMBHSTDAT0(priv)) +
 568                              (inb_p(SMBHSTDAT1(priv)) << 8);
 569                 break;
 570         }
 571         return 0;
 572 }
 573
 574
 575 static u32 i801_func(struct i2c_adapter *adapter)
 576 {
 577         struct i801_priv *priv = i2c_get_adapdata(adapter);
 578
 579         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 580                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 581                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 582                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 583                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 584                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 585 }
 586
 587 static const struct i2c_algorithm smbus_algorithm = {
 588         .smbus_xfer     = i801_access,
 589         .functionality  = i801_func,
 590 };
 591
 592 static const struct pci_device_id i801_ids[] = {
 593         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 594         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 595         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 596         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 597         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 598         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 599         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 600         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 601         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 602         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 603         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 604         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 605         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 606         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 607         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 608         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 609         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 610         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 611         { 0, }
 612 };
 613
 614 MODULE_DEVICE_TABLE(pci, i801_ids);
 615
 616 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
 617 static unsigned char apanel_addr;
 618
 619 /* Scan the system ROM for the signature "FJKEYINF" */
 620 static __init const void __iomem *bios_signature(const void __iomem *bios)
 621 {
 622         ssize_t offset;
 623         const unsigned char signature[] = "FJKEYINF";
 624
 625         for (offset = 0; offset < 0x10000; offset += 0x10) {
 626                 if (check_signature(bios + offset, signature,
 627                                     sizeof(signature)-1))
 628                         return bios + offset;
 629         }
 630         return NULL;
 631 }
 632
 633 static void __init input_apanel_init(void)
 634 {
 635         void __iomem *bios;
 636         const void __iomem *p;
 637
 638         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 639         p = bios_signature(bios);
 640         if (p) {
 641                 /* just use the first address */
 642                 apanel_addr = readb(p + 8 + 3) >> 1;
 643         }
 644         iounmap(bios);
 645 }
 646 #else
 647 static void __init input_apanel_init(void) {}
 648 #endif
 649
 650 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
 651 struct dmi_onboard_device_info {
 652         const char *name;
 653         u8 type;
 654         unsigned short i2c_addr;
 655         const char *i2c_type;
 656 };
 657
 658 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 659         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 660         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 661         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 662 };
 663
 664 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 665                                                struct i2c_adapter *adap)
 666 {
 667         int i;
 668         struct i2c_board_info info;
 669
 670         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 671                 /* & ~0x80, ignore enabled/disabled bit */
 672                 if ((type & ~0x80) != dmi_devices[i].type)
 673                         continue;
 674                 if (strcasecmp(name, dmi_devices[i].name))
 675                         continue;
 676
 677                 memset(&info, 0, sizeof(struct i2c_board_info));
 678                 info.addr = dmi_devices[i].i2c_addr;
 679                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 680                 i2c_new_device(adap, &info);
 681                 break;
 682         }
 683 }
 684
 685 /* We use our own function to check for onboard devices instead of
 686    dmi_find_device() as some buggy BIOS's have the devices we are interested
 687    in marked as disabled */
 688 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 689                                                 void *adap)
 690 {
 691         int i, count;
 692
 693         if (dm->type != 10)
 694                 return;
 695
 696         count = (dm->length - sizeof(struct dmi_header)) / 2;
 697         for (i = 0; i < count; i++) {
 698                 const u8 *d = (char *)(dm + 1) + (i * 2);
 699                 const char *name = ((char *) dm) + dm->length;
 700                 u8 type = d[0];
 701                 u8 s = d[1];
 702
 703                 if (!s)
 704                         continue;
 705                 s--;
 706                 while (s > 0 && name[0]) {
 707                         name += strlen(name) + 1;
 708                         s--;
 709                 }
 710                 if (name[0] == 0) /* Bogus string reference */
 711                         continue;
 712
 713                 dmi_check_onboard_device(type, name, adap);
 714         }
 715 }
 716 #endif
 717
 718 static int __devinit i801_probe(struct pci_dev *dev,
 719                                 const struct pci_device_id *id)
 720 {
 721         unsigned char temp;
 722         int err, i;
 723         struct i801_priv *priv;
 724
 725         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 726         if (!priv)
 727                 return -ENOMEM;
 728
 729         i2c_set_adapdata(&priv->adapter, priv);
 730         priv->adapter.owner = THIS_MODULE;
 731         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 732         priv->adapter.algo = &smbus_algorithm;
 733
 734         priv->pci_dev = dev;
 735         switch (dev->device) {
 736         default:
 737                 priv->features |= FEATURE_I2C_BLOCK_READ;
 738                 /* fall through */
 739         case PCI_DEVICE_ID_INTEL_82801DB_3:
 740                 priv->features |= FEATURE_SMBUS_PEC;
 741                 priv->features |= FEATURE_BLOCK_BUFFER;
 742                 /* fall through */
 743         case PCI_DEVICE_ID_INTEL_82801CA_3:
 744         case PCI_DEVICE_ID_INTEL_82801BA_2:
 745         case PCI_DEVICE_ID_INTEL_82801AB_3:
 746         case PCI_DEVICE_ID_INTEL_82801AA_3:
 747                 break;
 748         }
 749
 750         /* Disable features on user request */
 751         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 752                 if (priv->features & disable_features & (1 << i))
 753                         dev_notice(&dev->dev, "%s disabled by user\n",
 754                                    i801_feature_names[i]);
 755         }
 756         priv->features &= ~disable_features;
 757
 758         err = pci_enable_device(dev);
 759         if (err) {
 760                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 761                         err);
 762                 goto exit;
 763         }
 764
 765         /* Determine the address of the SMBus area */
 766         priv->smba = pci_resource_start(dev, SMBBAR);
 767         if (!priv->smba) {
 768                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 769                         "upgrade BIOS\n");
 770                 err = -ENODEV;
 771                 goto exit;
 772         }
 773
 774         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 775         if (err) {
 776                 err = -ENODEV;
 777                 goto exit;
 778         }
 779
 780         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 781         if (err) {
 782                 dev_err(&dev->dev, "Failed to request SMBus region "
 783                         "0x%lx-0x%Lx\n", priv->smba,
 784                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 785                 goto exit;
 786         }
 787
 788         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 789         priv->original_hstcfg = temp;
 790         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 791         if (!(temp & SMBHSTCFG_HST_EN)) {
 792                 dev_info(&dev->dev, "Enabling SMBus device\n");
 793                 temp |= SMBHSTCFG_HST_EN;
 794         }
 795         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 796
 797         if (temp & SMBHSTCFG_SMB_SMI_EN)
 798                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 799         else
 800                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 801
 802         /* Clear special mode bits */
 803         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 804                 outb_p(inb_p(SMBAUXCTL(priv)) &
 805                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 806
 807         /* set up the sysfs linkage to our parent device */
 808         priv->adapter.dev.parent = &dev->dev;
 809
 810         /* Retry up to 3 times on lost arbitration */
 811         priv->adapter.retries = 3;
 812
 813         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 814                 "SMBus I801 adapter at %04lx", priv->smba);
 815         err = i2c_add_adapter(&priv->adapter);
 816         if (err) {
 817                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 818                 goto exit_release;
 819         }
 820
 821         /* Register optional slaves */
 822 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
 823         if (apanel_addr) {
 824                 struct i2c_board_info info;
 825
 826                 memset(&info, 0, sizeof(struct i2c_board_info));
 827                 info.addr = apanel_addr;
 828                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 829                 i2c_new_device(&priv->adapter, &info);
 830         }
 831 #endif
 832 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
 833         if (dmi_name_in_vendors("FUJITSU"))
 834                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 835 #endif
 836
 837         pci_set_drvdata(dev, priv);
 838         return 0;
 839
 840 exit_release:
 841         pci_release_region(dev, SMBBAR);
 842 exit:
 843         kfree(priv);
 844         return err;
 845 }
 846
 847 static void __devexit i801_remove(struct pci_dev *dev)
 848 {
 849         struct i801_priv *priv = pci_get_drvdata(dev);
 850
 851         i2c_del_adapter(&priv->adapter);
 852         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 853         pci_release_region(dev, SMBBAR);
 854         pci_set_drvdata(dev, NULL);
 855         kfree(priv);
 856         /*
 857          * do not call pci_disable_device(dev) since it can cause hard hangs on
 858          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 859          */
 860 }
 861
 862 #ifdef CONFIG_PM
 863 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 864 {
 865         struct i801_priv *priv = pci_get_drvdata(dev);
 866
 867         pci_save_state(dev);
 868         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 869         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 870         return 0;
 871 }
 872
 873 static int i801_resume(struct pci_dev *dev)
 874 {
 875         pci_set_power_state(dev, PCI_D0);
 876         pci_restore_state(dev);
 877         return pci_enable_device(dev);
 878 }
 879 #else
 880 #define i801_suspend NULL
 881 #define i801_resume NULL
 882 #endif
 883
 884 static struct pci_driver i801_driver = {
 885         .name           = "i801_smbus",
 886         .id_table       = i801_ids,
 887         .probe          = i801_probe,
 888         .remove         = __devexit_p(i801_remove),
 889         .suspend        = i801_suspend,
 890         .resume         = i801_resume,
 891 };
 892
 893 static int __init i2c_i801_init(void)
 894 {
 895         input_apanel_init();
 896         return pci_register_driver(&i801_driver);
 897 }
 898
 899 static void __exit i2c_i801_exit(void)
 900 {
 901         pci_unregister_driver(&i801_driver);
 902 }
 903
 904 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 905               "Jean Delvare <khali@linux-fr.org>");
 906 MODULE_DESCRIPTION("I801 SMBus driver");
 907 MODULE_LICENSE("GPL");
 908
 909 module_init(i2c_i801_init);
 910 module_exit(i2c_i801_exit);