drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  46
  47 struct intel_dp_priv {
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int dpms_mode;
  53         uint8_t link_bw;
  54         uint8_t lane_count;
  55         uint8_t dpcd[4];
  56         struct intel_encoder *intel_encoder;
  57         struct i2c_adapter adapter;
  58         struct i2c_algo_dp_aux_data algo;
  59 };
  60
  61 static void
  62 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  63                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  64
  65 static void
  66 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  67
  68 void
  69 intel_edp_link_config (struct intel_encoder *intel_encoder,
  70                 int *lane_num, int *link_bw)
  71 {
  72         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  73
  74         *lane_num = dp_priv->lane_count;
  75         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  76                 *link_bw = 162000;
  77         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  78                 *link_bw = 270000;
  79 }
  80
  81 static int
  82 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  83 {
  84         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  85         int max_lane_count = 4;
  86
  87         if (dp_priv->dpcd[0] >= 0x11) {
  88                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  89                 switch (max_lane_count) {
  90                 case 1: case 2: case 4:
  91                         break;
  92                 default:
  93                         max_lane_count = 4;
  94                 }
  95         }
  96         return max_lane_count;
  97 }
  98
  99 static int
 100 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 101 {
 102         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 103         int max_link_bw = dp_priv->dpcd[1];
 104
 105         switch (max_link_bw) {
 106         case DP_LINK_BW_1_62:
 107         case DP_LINK_BW_2_7:
 108                 break;
 109         default:
 110                 max_link_bw = DP_LINK_BW_1_62;
 111                 break;
 112         }
 113         return max_link_bw;
 114 }
 115
 116 static int
 117 intel_dp_link_clock(uint8_t link_bw)
 118 {
 119         if (link_bw == DP_LINK_BW_2_7)
 120                 return 270000;
 121         else
 122                 return 162000;
 123 }
 124
 125 /* I think this is a fiction */
 126 static int
 127 intel_dp_link_required(struct drm_device *dev,
 128                        struct intel_encoder *intel_encoder, int pixel_clock)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131
 132         if (IS_eDP(intel_encoder))
 133                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 134         else
 135                 return pixel_clock * 3;
 136 }
 137
 138 static int
 139 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 140 {
 141         return (max_link_clock * max_lanes * 8) / 10;
 142 }
 143
 144 static int
 145 intel_dp_mode_valid(struct drm_connector *connector,
 146                     struct drm_display_mode *mode)
 147 {
 148         struct drm_encoder *encoder = intel_attached_encoder(connector);
 149         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 150         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 151         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 152
 153         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 154            which are outside spec tolerances but somehow work by magic */
 155         if (!IS_eDP(intel_encoder) &&
 156             (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 157              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 158                 return MODE_CLOCK_HIGH;
 159
 160         if (mode->clock < 10000)
 161                 return MODE_CLOCK_LOW;
 162
 163         return MODE_OK;
 164 }
 165
 166 static uint32_t
 167 pack_aux(uint8_t *src, int src_bytes)
 168 {
 169         int     i;
 170         uint32_t v = 0;
 171
 172         if (src_bytes > 4)
 173                 src_bytes = 4;
 174         for (i = 0; i < src_bytes; i++)
 175                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 176         return v;
 177 }
 178
 179 static void
 180 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 181 {
 182         int i;
 183         if (dst_bytes > 4)
 184                 dst_bytes = 4;
 185         for (i = 0; i < dst_bytes; i++)
 186                 dst[i] = src >> ((3-i) * 8);
 187 }
 188
 189 /* hrawclock is 1/4 the FSB frequency */
 190 static int
 191 intel_hrawclk(struct drm_device *dev)
 192 {
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         uint32_t clkcfg;
 195
 196         clkcfg = I915_READ(CLKCFG);
 197         switch (clkcfg & CLKCFG_FSB_MASK) {
 198         case CLKCFG_FSB_400:
 199                 return 100;
 200         case CLKCFG_FSB_533:
 201                 return 133;
 202         case CLKCFG_FSB_667:
 203                 return 166;
 204         case CLKCFG_FSB_800:
 205                 return 200;
 206         case CLKCFG_FSB_1067:
 207                 return 266;
 208         case CLKCFG_FSB_1333:
 209                 return 333;
 210         /* these two are just a guess; one of them might be right */
 211         case CLKCFG_FSB_1600:
 212         case CLKCFG_FSB_1600_ALT:
 213                 return 400;
 214         default:
 215                 return 133;
 216         }
 217 }
 218
 219 static int
 220 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 221                 uint8_t *send, int send_bytes,
 222                 uint8_t *recv, int recv_size)
 223 {
 224         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 225         uint32_t output_reg = dp_priv->output_reg;
 226         struct drm_device *dev = intel_encoder->enc.dev;
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         uint32_t ch_ctl = output_reg + 0x10;
 229         uint32_t ch_data = ch_ctl + 4;
 230         int i;
 231         int recv_bytes;
 232         uint32_t ctl;
 233         uint32_t status;
 234         uint32_t aux_clock_divider;
 235         int try, precharge;
 236
 237         /* The clock divider is based off the hrawclk,
 238          * and would like to run at 2MHz. So, take the
 239          * hrawclk value and divide by 2 and use that
 240          */
 241         if (IS_eDP(intel_encoder)) {
 242                 if (IS_GEN6(dev))
 243                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 244                 else
 245                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 246         } else if (HAS_PCH_SPLIT(dev))
 247                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 248         else
 249                 aux_clock_divider = intel_hrawclk(dev) / 2;
 250
 251         if (IS_GEN6(dev))
 252                 precharge = 3;
 253         else
 254                 precharge = 5;
 255
 256         /* Must try at least 3 times according to DP spec */
 257         for (try = 0; try < 5; try++) {
 258                 /* Load the send data into the aux channel data registers */
 259                 for (i = 0; i < send_bytes; i += 4) {
 260                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 261
 262                         I915_WRITE(ch_data + i, d);
 263                 }
 264
 265                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 266                        DP_AUX_CH_CTL_TIME_OUT_400us |
 267                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 268                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 269                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 270                        DP_AUX_CH_CTL_DONE |
 271                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 272                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 273
 274                 /* Send the command and wait for it to complete */
 275                 I915_WRITE(ch_ctl, ctl);
 276                 (void) I915_READ(ch_ctl);
 277                 for (;;) {
 278                         udelay(100);
 279                         status = I915_READ(ch_ctl);
 280                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 281                                 break;
 282                 }
 283
 284                 /* Clear done status and any errors */
 285                 I915_WRITE(ch_ctl, (status |
 286                                 DP_AUX_CH_CTL_DONE |
 287                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 288                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 289                 (void) I915_READ(ch_ctl);
 290                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 291                         break;
 292         }
 293
 294         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 295                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 296                 return -EBUSY;
 297         }
 298
 299         /* Check for timeout or receive error.
 300          * Timeouts occur when the sink is not connected
 301          */
 302         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 303                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 304                 return -EIO;
 305         }
 306
 307         /* Timeouts occur when the device isn't connected, so they're
 308          * "normal" -- don't fill the kernel log with these */
 309         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 310                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 311                 return -ETIMEDOUT;
 312         }
 313
 314         /* Unload any bytes sent back from the other side */
 315         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 316                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 317
 318         if (recv_bytes > recv_size)
 319                 recv_bytes = recv_size;
 320
 321         for (i = 0; i < recv_bytes; i += 4) {
 322                 uint32_t    d = I915_READ(ch_data + i);
 323
 324                 unpack_aux(d, recv + i, recv_bytes - i);
 325         }
 326
 327         return recv_bytes;
 328 }
 329
 330 /* Write data to the aux channel in native mode */
 331 static int
 332 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 333                           uint16_t address, uint8_t *send, int send_bytes)
 334 {
 335         int ret;
 336         uint8_t msg[20];
 337         int msg_bytes;
 338         uint8_t ack;
 339
 340         if (send_bytes > 16)
 341                 return -1;
 342         msg[0] = AUX_NATIVE_WRITE << 4;
 343         msg[1] = address >> 8;
 344         msg[2] = address & 0xff;
 345         msg[3] = send_bytes - 1;
 346         memcpy(&msg[4], send, send_bytes);
 347         msg_bytes = send_bytes + 4;
 348         for (;;) {
 349                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 350                 if (ret < 0)
 351                         return ret;
 352                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 353                         break;
 354                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 355                         udelay(100);
 356                 else
 357                         return -EIO;
 358         }
 359         return send_bytes;
 360 }
 361
 362 /* Write a single byte to the aux channel in native mode */
 363 static int
 364 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 365                             uint16_t address, uint8_t byte)
 366 {
 367         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 368 }
 369
 370 /* read bytes from a native aux channel */
 371 static int
 372 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 373                          uint16_t address, uint8_t *recv, int recv_bytes)
 374 {
 375         uint8_t msg[4];
 376         int msg_bytes;
 377         uint8_t reply[20];
 378         int reply_bytes;
 379         uint8_t ack;
 380         int ret;
 381
 382         msg[0] = AUX_NATIVE_READ << 4;
 383         msg[1] = address >> 8;
 384         msg[2] = address & 0xff;
 385         msg[3] = recv_bytes - 1;
 386
 387         msg_bytes = 4;
 388         reply_bytes = recv_bytes + 1;
 389
 390         for (;;) {
 391                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 392                                       reply, reply_bytes);
 393                 if (ret == 0)
 394                         return -EPROTO;
 395                 if (ret < 0)
 396                         return ret;
 397                 ack = reply[0];
 398                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 399                         memcpy(recv, reply + 1, ret - 1);
 400                         return ret - 1;
 401                 }
 402                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 403                         udelay(100);
 404                 else
 405                         return -EIO;
 406         }
 407 }
 408
 409 static int
 410 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 411                     uint8_t write_byte, uint8_t *read_byte)
 412 {
 413         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 414         struct intel_dp_priv *dp_priv = container_of(adapter,
 415                                                      struct intel_dp_priv,
 416                                                      adapter);
 417         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 418         uint16_t address = algo_data->address;
 419         uint8_t msg[5];
 420         uint8_t reply[2];
 421         int msg_bytes;
 422         int reply_bytes;
 423         int ret;
 424
 425         /* Set up the command byte */
 426         if (mode & MODE_I2C_READ)
 427                 msg[0] = AUX_I2C_READ << 4;
 428         else
 429                 msg[0] = AUX_I2C_WRITE << 4;
 430
 431         if (!(mode & MODE_I2C_STOP))
 432                 msg[0] |= AUX_I2C_MOT << 4;
 433
 434         msg[1] = address >> 8;
 435         msg[2] = address;
 436
 437         switch (mode) {
 438         case MODE_I2C_WRITE:
 439                 msg[3] = 0;
 440                 msg[4] = write_byte;
 441                 msg_bytes = 5;
 442                 reply_bytes = 1;
 443                 break;
 444         case MODE_I2C_READ:
 445                 msg[3] = 0;
 446                 msg_bytes = 4;
 447                 reply_bytes = 2;
 448                 break;
 449         default:
 450                 msg_bytes = 3;
 451                 reply_bytes = 1;
 452                 break;
 453         }
 454
 455         for (;;) {
 456           ret = intel_dp_aux_ch(intel_encoder,
 457                                 msg, msg_bytes,
 458                                 reply, reply_bytes);
 459                 if (ret < 0) {
 460                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 461                         return ret;
 462                 }
 463                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 464                 case AUX_I2C_REPLY_ACK:
 465                         if (mode == MODE_I2C_READ) {
 466                                 *read_byte = reply[1];
 467                         }
 468                         return reply_bytes - 1;
 469                 case AUX_I2C_REPLY_NACK:
 470                         DRM_DEBUG_KMS("aux_ch nack\n");
 471                         return -EREMOTEIO;
 472                 case AUX_I2C_REPLY_DEFER:
 473                         DRM_DEBUG_KMS("aux_ch defer\n");
 474                         udelay(100);
 475                         break;
 476                 default:
 477                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 478                         return -EREMOTEIO;
 479                 }
 480         }
 481 }
 482
 483 static int
 484 intel_dp_i2c_init(struct intel_encoder *intel_encoder,
 485                   struct intel_connector *intel_connector, const char *name)
 486 {
 487         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 488
 489         DRM_DEBUG_KMS("i2c_init %s\n", name);
 490         dp_priv->algo.running = false;
 491         dp_priv->algo.address = 0;
 492         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 493
 494         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 495         dp_priv->adapter.owner = THIS_MODULE;
 496         dp_priv->adapter.class = I2C_CLASS_DDC;
 497         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 498         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 499         dp_priv->adapter.algo_data = &dp_priv->algo;
 500         dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
 501
 502         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 503 }
 504
 505 static bool
 506 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 507                     struct drm_display_mode *adjusted_mode)
 508 {
 509         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 510         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 511         int lane_count, clock;
 512         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 513         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 514         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 515
 516         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 517                 for (clock = 0; clock <= max_clock; clock++) {
 518                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 519
 520                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 521                                         <= link_avail) {
 522                                 dp_priv->link_bw = bws[clock];
 523                                 dp_priv->lane_count = lane_count;
 524                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 525                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 526                                                 "count %d clock %d\n",
 527                                        dp_priv->link_bw, dp_priv->lane_count,
 528                                        adjusted_mode->clock);
 529                                 return true;
 530                         }
 531                 }
 532         }
 533
 534         if (IS_eDP(intel_encoder)) {
 535                 /* okay we failed just pick the highest */
 536                 dp_priv->lane_count = max_lane_count;
 537                 dp_priv->link_bw = bws[max_clock];
 538                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 539                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 540                               "count %d clock %d\n",
 541                               dp_priv->link_bw, dp_priv->lane_count,
 542                               adjusted_mode->clock);
 543                 return true;
 544         }
 545         return false;
 546 }
 547
 548 struct intel_dp_m_n {
 549         uint32_t        tu;
 550         uint32_t        gmch_m;
 551         uint32_t        gmch_n;
 552         uint32_t        link_m;
 553         uint32_t        link_n;
 554 };
 555
 556 static void
 557 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 558 {
 559         while (*num > 0xffffff || *den > 0xffffff) {
 560                 *num >>= 1;
 561                 *den >>= 1;
 562         }
 563 }
 564
 565 static void
 566 intel_dp_compute_m_n(int bytes_per_pixel,
 567                      int nlanes,
 568                      int pixel_clock,
 569                      int link_clock,
 570                      struct intel_dp_m_n *m_n)
 571 {
 572         m_n->tu = 64;
 573         m_n->gmch_m = pixel_clock * bytes_per_pixel;
 574         m_n->gmch_n = link_clock * nlanes;
 575         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 576         m_n->link_m = pixel_clock;
 577         m_n->link_n = link_clock;
 578         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 579 }
 580
 581 void
 582 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 583                  struct drm_display_mode *adjusted_mode)
 584 {
 585         struct drm_device *dev = crtc->dev;
 586         struct drm_mode_config *mode_config = &dev->mode_config;
 587         struct drm_encoder *encoder;
 588         struct drm_i915_private *dev_priv = dev->dev_private;
 589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 590         int lane_count = 4;
 591         struct intel_dp_m_n m_n;
 592
 593         /*
 594          * Find the lane count in the intel_encoder private
 595          */
 596         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 597                 struct intel_encoder *intel_encoder;
 598                 struct intel_dp_priv *dp_priv;
 599
 600                 if (encoder->crtc != crtc)
 601                         continue;
 602
 603                 intel_encoder = enc_to_intel_encoder(encoder);
 604                 dp_priv = intel_encoder->dev_priv;
 605
 606                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 607                         lane_count = dp_priv->lane_count;
 608                         break;
 609                 }
 610         }
 611
 612         /*
 613          * Compute the GMCH and Link ratios. The '3' here is
 614          * the number of bytes_per_pixel post-LUT, which we always
 615          * set up for 8-bits of R/G/B, or 3 bytes total.
 616          */
 617         intel_dp_compute_m_n(3, lane_count,
 618                              mode->clock, adjusted_mode->clock, &m_n);
 619
 620         if (HAS_PCH_SPLIT(dev)) {
 621                 if (intel_crtc->pipe == 0) {
 622                         I915_WRITE(TRANSA_DATA_M1,
 623                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 624                                    m_n.gmch_m);
 625                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 626                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 627                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 628                 } else {
 629                         I915_WRITE(TRANSB_DATA_M1,
 630                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 631                                    m_n.gmch_m);
 632                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 633                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 634                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 635                 }
 636         } else {
 637                 if (intel_crtc->pipe == 0) {
 638                         I915_WRITE(PIPEA_GMCH_DATA_M,
 639                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 640                                    m_n.gmch_m);
 641                         I915_WRITE(PIPEA_GMCH_DATA_N,
 642                                    m_n.gmch_n);
 643                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 644                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 645                 } else {
 646                         I915_WRITE(PIPEB_GMCH_DATA_M,
 647                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 648                                    m_n.gmch_m);
 649                         I915_WRITE(PIPEB_GMCH_DATA_N,
 650                                         m_n.gmch_n);
 651                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 652                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 653                 }
 654         }
 655 }
 656
 657 static void
 658 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 659                   struct drm_display_mode *adjusted_mode)
 660 {
 661         struct drm_device *dev = encoder->dev;
 662         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 663         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 664         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 666
 667         dp_priv->DP = (DP_VOLTAGE_0_4 |
 668                        DP_PRE_EMPHASIS_0);
 669
 670         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 671                 dp_priv->DP |= DP_SYNC_HS_HIGH;
 672         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 673                 dp_priv->DP |= DP_SYNC_VS_HIGH;
 674
 675         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
 676                 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
 677         else
 678                 dp_priv->DP |= DP_LINK_TRAIN_OFF;
 679
 680         switch (dp_priv->lane_count) {
 681         case 1:
 682                 dp_priv->DP |= DP_PORT_WIDTH_1;
 683                 break;
 684         case 2:
 685                 dp_priv->DP |= DP_PORT_WIDTH_2;
 686                 break;
 687         case 4:
 688                 dp_priv->DP |= DP_PORT_WIDTH_4;
 689                 break;
 690         }
 691         if (dp_priv->has_audio)
 692                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 693
 694         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 695         dp_priv->link_configuration[0] = dp_priv->link_bw;
 696         dp_priv->link_configuration[1] = dp_priv->lane_count;
 697
 698         /*
 699          * Check for DPCD version > 1.1 and enhanced framing support
 700          */
 701         if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 702                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 703                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 704         }
 705
 706         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 707         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 708                 dp_priv->DP |= DP_PIPEB_SELECT;
 709
 710         if (IS_eDP(intel_encoder)) {
 711                 /* don't miss out required setting for eDP */
 712                 dp_priv->DP |= DP_PLL_ENABLE;
 713                 if (adjusted_mode->clock < 200000)
 714                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 715                 else
 716                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 717         }
 718 }
 719
 720 static void ironlake_edp_panel_on (struct drm_device *dev)
 721 {
 722         struct drm_i915_private *dev_priv = dev->dev_private;
 723         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 724         u32 pp, pp_status;
 725
 726         pp_status = I915_READ(PCH_PP_STATUS);
 727         if (pp_status & PP_ON)
 728                 return;
 729
 730         pp = I915_READ(PCH_PP_CONTROL);
 731         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 732         I915_WRITE(PCH_PP_CONTROL, pp);
 733         do {
 734                 pp_status = I915_READ(PCH_PP_STATUS);
 735         } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
 736
 737         if (time_after(jiffies, timeout))
 738                 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
 739
 740         pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
 741         I915_WRITE(PCH_PP_CONTROL, pp);
 742 }
 743
 744 static void ironlake_edp_panel_off (struct drm_device *dev)
 745 {
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 748         u32 pp, pp_status;
 749
 750         pp = I915_READ(PCH_PP_CONTROL);
 751         pp &= ~POWER_TARGET_ON;
 752         I915_WRITE(PCH_PP_CONTROL, pp);
 753         do {
 754                 pp_status = I915_READ(PCH_PP_STATUS);
 755         } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
 756
 757         if (time_after(jiffies, timeout))
 758                 DRM_DEBUG_KMS("panel off wait timed out\n");
 759
 760         /* Make sure VDD is enabled so DP AUX will work */
 761         pp |= EDP_FORCE_VDD;
 762         I915_WRITE(PCH_PP_CONTROL, pp);
 763 }
 764
 765 static void ironlake_edp_backlight_on (struct drm_device *dev)
 766 {
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         u32 pp;
 769
 770         DRM_DEBUG_KMS("\n");
 771         pp = I915_READ(PCH_PP_CONTROL);
 772         pp |= EDP_BLC_ENABLE;
 773         I915_WRITE(PCH_PP_CONTROL, pp);
 774 }
 775
 776 static void ironlake_edp_backlight_off (struct drm_device *dev)
 777 {
 778         struct drm_i915_private *dev_priv = dev->dev_private;
 779         u32 pp;
 780
 781         DRM_DEBUG_KMS("\n");
 782         pp = I915_READ(PCH_PP_CONTROL);
 783         pp &= ~EDP_BLC_ENABLE;
 784         I915_WRITE(PCH_PP_CONTROL, pp);
 785 }
 786
 787 static void
 788 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 789 {
 790         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 791         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 792         struct drm_device *dev = encoder->dev;
 793         struct drm_i915_private *dev_priv = dev->dev_private;
 794         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 795
 796         if (mode != DRM_MODE_DPMS_ON) {
 797                 if (dp_reg & DP_PORT_EN) {
 798                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 799                         if (IS_eDP(intel_encoder)) {
 800                                 ironlake_edp_backlight_off(dev);
 801                                 ironlake_edp_backlight_off(dev);
 802                         }
 803                 }
 804         } else {
 805                 if (!(dp_reg & DP_PORT_EN)) {
 806                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 807                         if (IS_eDP(intel_encoder)) {
 808                                 ironlake_edp_panel_on(dev);
 809                                 ironlake_edp_backlight_on(dev);
 810                         }
 811                 }
 812         }
 813         dp_priv->dpms_mode = mode;
 814 }
 815
 816 /*
 817  * Fetch AUX CH registers 0x202 - 0x207 which contain
 818  * link status information
 819  */
 820 static bool
 821 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 822                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 823 {
 824         int ret;
 825
 826         ret = intel_dp_aux_native_read(intel_encoder,
 827                                        DP_LANE0_1_STATUS,
 828                                        link_status, DP_LINK_STATUS_SIZE);
 829         if (ret != DP_LINK_STATUS_SIZE)
 830                 return false;
 831         return true;
 832 }
 833
 834 static uint8_t
 835 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 836                      int r)
 837 {
 838         return link_status[r - DP_LANE0_1_STATUS];
 839 }
 840
 841 static uint8_t
 842 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 843                                  int lane)
 844 {
 845         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 846         int         s = ((lane & 1) ?
 847                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 848                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 849         uint8_t l = intel_dp_link_status(link_status, i);
 850
 851         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 852 }
 853
 854 static uint8_t
 855 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 856                                       int lane)
 857 {
 858         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 859         int         s = ((lane & 1) ?
 860                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 861                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 862         uint8_t l = intel_dp_link_status(link_status, i);
 863
 864         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 865 }
 866
 867
 868 #if 0
 869 static char     *voltage_names[] = {
 870         "0.4V", "0.6V", "0.8V", "1.2V"
 871 };
 872 static char     *pre_emph_names[] = {
 873         "0dB", "3.5dB", "6dB", "9.5dB"
 874 };
 875 static char     *link_train_names[] = {
 876         "pattern 1", "pattern 2", "idle", "off"
 877 };
 878 #endif
 879
 880 /*
 881  * These are source-specific values; current Intel hardware supports
 882  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 883  */
 884 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 885
 886 static uint8_t
 887 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 888 {
 889         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 890         case DP_TRAIN_VOLTAGE_SWING_400:
 891                 return DP_TRAIN_PRE_EMPHASIS_6;
 892         case DP_TRAIN_VOLTAGE_SWING_600:
 893                 return DP_TRAIN_PRE_EMPHASIS_6;
 894         case DP_TRAIN_VOLTAGE_SWING_800:
 895                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 896         case DP_TRAIN_VOLTAGE_SWING_1200:
 897         default:
 898                 return DP_TRAIN_PRE_EMPHASIS_0;
 899         }
 900 }
 901
 902 static void
 903 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 904                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 905                        int lane_count,
 906                        uint8_t train_set[4])
 907 {
 908         uint8_t v = 0;
 909         uint8_t p = 0;
 910         int lane;
 911
 912         for (lane = 0; lane < lane_count; lane++) {
 913                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 914                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 915
 916                 if (this_v > v)
 917                         v = this_v;
 918                 if (this_p > p)
 919                         p = this_p;
 920         }
 921
 922         if (v >= I830_DP_VOLTAGE_MAX)
 923                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 924
 925         if (p >= intel_dp_pre_emphasis_max(v))
 926                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 927
 928         for (lane = 0; lane < 4; lane++)
 929                 train_set[lane] = v | p;
 930 }
 931
 932 static uint32_t
 933 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 934 {
 935         uint32_t        signal_levels = 0;
 936
 937         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 938         case DP_TRAIN_VOLTAGE_SWING_400:
 939         default:
 940                 signal_levels |= DP_VOLTAGE_0_4;
 941                 break;
 942         case DP_TRAIN_VOLTAGE_SWING_600:
 943                 signal_levels |= DP_VOLTAGE_0_6;
 944                 break;
 945         case DP_TRAIN_VOLTAGE_SWING_800:
 946                 signal_levels |= DP_VOLTAGE_0_8;
 947                 break;
 948         case DP_TRAIN_VOLTAGE_SWING_1200:
 949                 signal_levels |= DP_VOLTAGE_1_2;
 950                 break;
 951         }
 952         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 953         case DP_TRAIN_PRE_EMPHASIS_0:
 954         default:
 955                 signal_levels |= DP_PRE_EMPHASIS_0;
 956                 break;
 957         case DP_TRAIN_PRE_EMPHASIS_3_5:
 958                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 959                 break;
 960         case DP_TRAIN_PRE_EMPHASIS_6:
 961                 signal_levels |= DP_PRE_EMPHASIS_6;
 962                 break;
 963         case DP_TRAIN_PRE_EMPHASIS_9_5:
 964                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 965                 break;
 966         }
 967         return signal_levels;
 968 }
 969
 970 /* Gen6's DP voltage swing and pre-emphasis control */
 971 static uint32_t
 972 intel_gen6_edp_signal_levels(uint8_t train_set)
 973 {
 974         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
 975         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
 976                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 977         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
 978                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
 979         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
 980                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
 981         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
 982                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
 983         default:
 984                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
 985                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
 986         }
 987 }
 988
 989 static uint8_t
 990 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 991                       int lane)
 992 {
 993         int i = DP_LANE0_1_STATUS + (lane >> 1);
 994         int s = (lane & 1) * 4;
 995         uint8_t l = intel_dp_link_status(link_status, i);
 996
 997         return (l >> s) & 0xf;
 998 }
 999
1000 /* Check for clock recovery is done on all channels */
1001 static bool
1002 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1003 {
1004         int lane;
1005         uint8_t lane_status;
1006
1007         for (lane = 0; lane < lane_count; lane++) {
1008                 lane_status = intel_get_lane_status(link_status, lane);
1009                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1010                         return false;
1011         }
1012         return true;
1013 }
1014
1015 /* Check to see if channel eq is done on all channels */
1016 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1017                          DP_LANE_CHANNEL_EQ_DONE|\
1018                          DP_LANE_SYMBOL_LOCKED)
1019 static bool
1020 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1021 {
1022         uint8_t lane_align;
1023         uint8_t lane_status;
1024         int lane;
1025
1026         lane_align = intel_dp_link_status(link_status,
1027                                           DP_LANE_ALIGN_STATUS_UPDATED);
1028         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1029                 return false;
1030         for (lane = 0; lane < lane_count; lane++) {
1031                 lane_status = intel_get_lane_status(link_status, lane);
1032                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1033                         return false;
1034         }
1035         return true;
1036 }
1037
1038 static bool
1039 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
1040                         uint32_t dp_reg_value,
1041                         uint8_t dp_train_pat,
1042                         uint8_t train_set[4],
1043                         bool first)
1044 {
1045         struct drm_device *dev = intel_encoder->enc.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1048         int ret;
1049
1050         I915_WRITE(dp_priv->output_reg, dp_reg_value);
1051         POSTING_READ(dp_priv->output_reg);
1052         if (first)
1053                 intel_wait_for_vblank(dev);
1054
1055         intel_dp_aux_native_write_1(intel_encoder,
1056                                     DP_TRAINING_PATTERN_SET,
1057                                     dp_train_pat);
1058
1059         ret = intel_dp_aux_native_write(intel_encoder,
1060                                         DP_TRAINING_LANE0_SET, train_set, 4);
1061         if (ret != 4)
1062                 return false;
1063
1064         return true;
1065 }
1066
1067 static void
1068 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1069                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1070 {
1071         struct drm_device *dev = intel_encoder->enc.dev;
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1074         uint8_t train_set[4];
1075         uint8_t link_status[DP_LINK_STATUS_SIZE];
1076         int i;
1077         uint8_t voltage;
1078         bool clock_recovery = false;
1079         bool channel_eq = false;
1080         bool first = true;
1081         int tries;
1082         u32 reg;
1083
1084         /* Write the link configuration data */
1085         intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
1086                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
1087
1088         DP |= DP_PORT_EN;
1089         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1090                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1091         else
1092                 DP &= ~DP_LINK_TRAIN_MASK;
1093         memset(train_set, 0, 4);
1094         voltage = 0xff;
1095         tries = 0;
1096         clock_recovery = false;
1097         for (;;) {
1098                 /* Use train_set[0] to set the voltage and pre emphasis values */
1099                 uint32_t    signal_levels;
1100                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1101                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1102                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1103                 } else {
1104                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1105                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1106                 }
1107
1108                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1109                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1110                 else
1111                         reg = DP | DP_LINK_TRAIN_PAT_1;
1112
1113                 if (!intel_dp_set_link_train(intel_encoder, reg,
1114                                              DP_TRAINING_PATTERN_1, train_set, first))
1115                         break;
1116                 first = false;
1117                 /* Set training pattern 1 */
1118
1119                 udelay(100);
1120                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1121                         break;
1122
1123                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1124                         clock_recovery = true;
1125                         break;
1126                 }
1127
1128                 /* Check to see if we've tried the max voltage */
1129                 for (i = 0; i < dp_priv->lane_count; i++)
1130                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1131                                 break;
1132                 if (i == dp_priv->lane_count)
1133                         break;
1134
1135                 /* Check to see if we've tried the same voltage 5 times */
1136                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1137                         ++tries;
1138                         if (tries == 5)
1139                                 break;
1140                 } else
1141                         tries = 0;
1142                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1143
1144                 /* Compute new train_set as requested by target */
1145                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1146         }
1147
1148         /* channel equalization */
1149         tries = 0;
1150         channel_eq = false;
1151         for (;;) {
1152                 /* Use train_set[0] to set the voltage and pre emphasis values */
1153                 uint32_t    signal_levels;
1154
1155                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1156                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1157                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1158                 } else {
1159                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1160                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1161                 }
1162
1163                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1164                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1165                 else
1166                         reg = DP | DP_LINK_TRAIN_PAT_2;
1167
1168                 /* channel eq pattern */
1169                 if (!intel_dp_set_link_train(intel_encoder, reg,
1170                                              DP_TRAINING_PATTERN_2, train_set,
1171                                              false))
1172                         break;
1173
1174                 udelay(400);
1175                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1176                         break;
1177
1178                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1179                         channel_eq = true;
1180                         break;
1181                 }
1182
1183                 /* Try 5 times */
1184                 if (tries > 5)
1185                         break;
1186
1187                 /* Compute new train_set as requested by target */
1188                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1189                 ++tries;
1190         }
1191
1192         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1193                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1194         else
1195                 reg = DP | DP_LINK_TRAIN_OFF;
1196
1197         I915_WRITE(dp_priv->output_reg, reg);
1198         POSTING_READ(dp_priv->output_reg);
1199         intel_dp_aux_native_write_1(intel_encoder,
1200                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1201 }
1202
1203 static void
1204 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1205 {
1206         struct drm_device *dev = intel_encoder->enc.dev;
1207         struct drm_i915_private *dev_priv = dev->dev_private;
1208         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1209
1210         DRM_DEBUG_KMS("\n");
1211
1212         if (IS_eDP(intel_encoder)) {
1213                 DP &= ~DP_PLL_ENABLE;
1214                 I915_WRITE(dp_priv->output_reg, DP);
1215                 POSTING_READ(dp_priv->output_reg);
1216                 udelay(100);
1217         }
1218
1219         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1220                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1221                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1222                 POSTING_READ(dp_priv->output_reg);
1223         } else {
1224                 DP &= ~DP_LINK_TRAIN_MASK;
1225                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1226                 POSTING_READ(dp_priv->output_reg);
1227         }
1228
1229         udelay(17000);
1230
1231         if (IS_eDP(intel_encoder))
1232                 DP |= DP_LINK_TRAIN_OFF;
1233         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1234         POSTING_READ(dp_priv->output_reg);
1235 }
1236
1237 /*
1238  * According to DP spec
1239  * 5.1.2:
1240  *  1. Read DPCD
1241  *  2. Configure link according to Receiver Capabilities
1242  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1243  *  4. Check link status on receipt of hot-plug interrupt
1244  */
1245
1246 static void
1247 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1248 {
1249         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1250         uint8_t link_status[DP_LINK_STATUS_SIZE];
1251
1252         if (!intel_encoder->enc.crtc)
1253                 return;
1254
1255         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1256                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1257                 return;
1258         }
1259
1260         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1261                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1262 }
1263
1264 static enum drm_connector_status
1265 ironlake_dp_detect(struct drm_connector *connector)
1266 {
1267         struct drm_encoder *encoder = intel_attached_encoder(connector);
1268         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1269         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1270         enum drm_connector_status status;
1271
1272         status = connector_status_disconnected;
1273         if (intel_dp_aux_native_read(intel_encoder,
1274                                      0x000, dp_priv->dpcd,
1275                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1276         {
1277                 if (dp_priv->dpcd[0] != 0)
1278                         status = connector_status_connected;
1279         }
1280         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1281                       dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
1282         return status;
1283 }
1284
1285 /**
1286  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1287  *
1288  * \return true if DP port is connected.
1289  * \return false if DP port is disconnected.
1290  */
1291 static enum drm_connector_status
1292 intel_dp_detect(struct drm_connector *connector)
1293 {
1294         struct drm_encoder *encoder = intel_attached_encoder(connector);
1295         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1296         struct drm_device *dev = intel_encoder->enc.dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1299         uint32_t temp, bit;
1300         enum drm_connector_status status;
1301
1302         dp_priv->has_audio = false;
1303
1304         if (HAS_PCH_SPLIT(dev))
1305                 return ironlake_dp_detect(connector);
1306
1307         switch (dp_priv->output_reg) {
1308         case DP_B:
1309                 bit = DPB_HOTPLUG_INT_STATUS;
1310                 break;
1311         case DP_C:
1312                 bit = DPC_HOTPLUG_INT_STATUS;
1313                 break;
1314         case DP_D:
1315                 bit = DPD_HOTPLUG_INT_STATUS;
1316                 break;
1317         default:
1318                 return connector_status_unknown;
1319         }
1320
1321         temp = I915_READ(PORT_HOTPLUG_STAT);
1322
1323         if ((temp & bit) == 0)
1324                 return connector_status_disconnected;
1325
1326         status = connector_status_disconnected;
1327         if (intel_dp_aux_native_read(intel_encoder,
1328                                      0x000, dp_priv->dpcd,
1329                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1330         {
1331                 if (dp_priv->dpcd[0] != 0)
1332                         status = connector_status_connected;
1333         }
1334         return status;
1335 }
1336
1337 static int intel_dp_get_modes(struct drm_connector *connector)
1338 {
1339         struct drm_encoder *encoder = intel_attached_encoder(connector);
1340         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1341         struct drm_device *dev = intel_encoder->enc.dev;
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         int ret;
1344
1345         /* We should parse the EDID data and find out if it has an audio sink
1346          */
1347
1348         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1349         if (ret)
1350                 return ret;
1351
1352         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1353         if (IS_eDP(intel_encoder)) {
1354                 if (dev_priv->panel_fixed_mode != NULL) {
1355                         struct drm_display_mode *mode;
1356                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1357                         drm_mode_probed_add(connector, mode);
1358                         return 1;
1359                 }
1360         }
1361         return 0;
1362 }
1363
1364 static void
1365 intel_dp_destroy (struct drm_connector *connector)
1366 {
1367         drm_sysfs_connector_remove(connector);
1368         drm_connector_cleanup(connector);
1369         kfree(connector);
1370 }
1371
1372 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1373         .dpms = intel_dp_dpms,
1374         .mode_fixup = intel_dp_mode_fixup,
1375         .prepare = intel_encoder_prepare,
1376         .mode_set = intel_dp_mode_set,
1377         .commit = intel_encoder_commit,
1378 };
1379
1380 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1381         .dpms = drm_helper_connector_dpms,
1382         .detect = intel_dp_detect,
1383         .fill_modes = drm_helper_probe_single_connector_modes,
1384         .destroy = intel_dp_destroy,
1385 };
1386
1387 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1388         .get_modes = intel_dp_get_modes,
1389         .mode_valid = intel_dp_mode_valid,
1390         .best_encoder = intel_attached_encoder,
1391 };
1392
1393 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1394 {
1395         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1396
1397         if (intel_encoder->i2c_bus)
1398                 intel_i2c_destroy(intel_encoder->i2c_bus);
1399         drm_encoder_cleanup(encoder);
1400         kfree(intel_encoder);
1401 }
1402
1403 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1404         .destroy = intel_dp_enc_destroy,
1405 };
1406
1407 void
1408 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1409 {
1410         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1411
1412         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1413                 intel_dp_check_link_status(intel_encoder);
1414 }
1415
1416 /* Return which DP Port should be selected for Transcoder DP control */
1417 int
1418 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1419 {
1420         struct drm_device *dev = crtc->dev;
1421         struct drm_mode_config *mode_config = &dev->mode_config;
1422         struct drm_encoder *encoder;
1423         struct intel_encoder *intel_encoder = NULL;
1424
1425         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1426                 if (encoder->crtc != crtc)
1427                         continue;
1428
1429                 intel_encoder = enc_to_intel_encoder(encoder);
1430                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1431                         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1432                         return dp_priv->output_reg;
1433                 }
1434         }
1435         return -1;
1436 }
1437
1438 void
1439 intel_dp_init(struct drm_device *dev, int output_reg)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         struct drm_connector *connector;
1443         struct intel_encoder *intel_encoder;
1444         struct intel_connector *intel_connector;
1445         struct intel_dp_priv *dp_priv;
1446         const char *name = NULL;
1447
1448         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1449                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1450         if (!intel_encoder)
1451                 return;
1452
1453         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1454         if (!intel_connector) {
1455                 kfree(intel_encoder);
1456                 return;
1457         }
1458
1459         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1460
1461         connector = &intel_connector->base;
1462         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1463                            DRM_MODE_CONNECTOR_DisplayPort);
1464         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1465
1466         connector->polled = DRM_CONNECTOR_POLL_HPD;
1467
1468         if (output_reg == DP_A)
1469                 intel_encoder->type = INTEL_OUTPUT_EDP;
1470         else
1471                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1472
1473         if (output_reg == DP_B || output_reg == PCH_DP_B)
1474                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1475         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1476                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1477         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1478                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1479
1480         if (IS_eDP(intel_encoder))
1481                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1482
1483         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1484         connector->interlace_allowed = true;
1485         connector->doublescan_allowed = 0;
1486
1487         dp_priv->intel_encoder = intel_encoder;
1488         dp_priv->output_reg = output_reg;
1489         dp_priv->has_audio = false;
1490         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1491         intel_encoder->dev_priv = dp_priv;
1492
1493         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1494                          DRM_MODE_ENCODER_TMDS);
1495         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1496
1497         drm_mode_connector_attach_encoder(&intel_connector->base,
1498                                           &intel_encoder->enc);
1499         drm_sysfs_connector_add(connector);
1500
1501         /* Set up the DDC bus. */
1502         switch (output_reg) {
1503                 case DP_A:
1504                         name = "DPDDC-A";
1505                         break;
1506                 case DP_B:
1507                 case PCH_DP_B:
1508                         dev_priv->hotplug_supported_mask |=
1509                                 HDMIB_HOTPLUG_INT_STATUS;
1510                         name = "DPDDC-B";
1511                         break;
1512                 case DP_C:
1513                 case PCH_DP_C:
1514                         dev_priv->hotplug_supported_mask |=
1515                                 HDMIC_HOTPLUG_INT_STATUS;
1516                         name = "DPDDC-C";
1517                         break;
1518                 case DP_D:
1519                 case PCH_DP_D:
1520                         dev_priv->hotplug_supported_mask |=
1521                                 HDMID_HOTPLUG_INT_STATUS;
1522                         name = "DPDDC-D";
1523                         break;
1524         }
1525
1526         intel_dp_i2c_init(intel_encoder, intel_connector, name);
1527
1528         intel_encoder->ddc_bus = &dp_priv->adapter;
1529         intel_encoder->hot_plug = intel_dp_hot_plug;
1530
1531         if (output_reg == DP_A) {
1532                 /* initialize panel mode from VBT if available for eDP */
1533                 if (dev_priv->lfp_lvds_vbt_mode) {
1534                         dev_priv->panel_fixed_mode =
1535                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1536                         if (dev_priv->panel_fixed_mode) {
1537                                 dev_priv->panel_fixed_mode->type |=
1538                                         DRM_MODE_TYPE_PREFERRED;
1539                         }
1540                 }
1541         }
1542
1543         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1544          * 0xd.  Failure to do so will result in spurious interrupts being
1545          * generated on the port when a cable is not attached.
1546          */
1547         if (IS_G4X(dev) && !IS_GM45(dev)) {
1548                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1549                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1550         }
1551 }