drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static const intel_limit_t intel_limits_i8xx_dvo = {
 346         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 347         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 348         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 349         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 350         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 351         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 352         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 353         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 354         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 355                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 356         .find_pll = intel_find_best_PLL,
 357 };
 358
 359 static const intel_limit_t intel_limits_i8xx_lvds = {
 360         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 361         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 362         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 363         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 364         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 365         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 366         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 367         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 368         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 369                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 370         .find_pll = intel_find_best_PLL,
 371 };
 372
 373 static const intel_limit_t intel_limits_i9xx_sdvo = {
 374         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 375         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 376         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 377         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 378         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 379         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 380         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 381         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 382         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 384         .find_pll = intel_find_best_PLL,
 385 };
 386
 387 static const intel_limit_t intel_limits_i9xx_lvds = {
 388         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 389         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 390         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 391         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 392         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 393         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 394         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 395         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 396         /* The single-channel range is 25-112Mhz, and dual-channel
 397          * is 80-224Mhz.  Prefer single channel as much as possible.
 398          */
 399         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 400                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 401         .find_pll = intel_find_best_PLL,
 402 };
 403
 404     /* below parameter and function is for G4X Chipset Family*/
 405 static const intel_limit_t intel_limits_g4x_sdvo = {
 406         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 407         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 408         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 409         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 410         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 411         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 412         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 413         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 414         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 415                  .p2_slow = G4X_P2_SDVO_SLOW,
 416                  .p2_fast = G4X_P2_SDVO_FAST
 417         },
 418         .find_pll = intel_g4x_find_best_PLL,
 419 };
 420
 421 static const intel_limit_t intel_limits_g4x_hdmi = {
 422         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 423         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 424         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 425         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 426         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 427         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 428         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 429         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 430         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 431                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 432                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 433         },
 434         .find_pll = intel_g4x_find_best_PLL,
 435 };
 436
 437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 438         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 440         .vco = { .min = G4X_VCO_MIN,
 441                  .max = G4X_VCO_MAX },
 442         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 444         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 446         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 448         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 450         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 452         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 454         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 455                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 456                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 457         },
 458         .find_pll = intel_g4x_find_best_PLL,
 459 };
 460
 461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 462         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 464         .vco = { .min = G4X_VCO_MIN,
 465                  .max = G4X_VCO_MAX },
 466         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 468         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 470         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 472         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 474         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 476         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 478         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 479                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 480                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 481         },
 482         .find_pll = intel_g4x_find_best_PLL,
 483 };
 484
 485 static const intel_limit_t intel_limits_g4x_display_port = {
 486         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 487                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 488         .vco = { .min = G4X_VCO_MIN,
 489                  .max = G4X_VCO_MAX},
 490         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 491                  .max = G4X_N_DISPLAY_PORT_MAX },
 492         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 493                  .max = G4X_M_DISPLAY_PORT_MAX },
 494         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 495                  .max = G4X_M1_DISPLAY_PORT_MAX },
 496         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 497                  .max = G4X_M2_DISPLAY_PORT_MAX },
 498         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 499                  .max = G4X_P_DISPLAY_PORT_MAX },
 500         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 501                  .max = G4X_P1_DISPLAY_PORT_MAX},
 502         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 503                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 504                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 505         .find_pll = intel_find_pll_g4x_dp,
 506 };
 507
 508 static const intel_limit_t intel_limits_pineview_sdvo = {
 509         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 510         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 511         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 512         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 513         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 514         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 515         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 516         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 517         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 518                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 519         .find_pll = intel_find_best_PLL,
 520 };
 521
 522 static const intel_limit_t intel_limits_pineview_lvds = {
 523         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 524         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 525         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 526         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 527         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 528         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 529         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 530         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 531         /* Pineview only supports single-channel mode. */
 532         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 533                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 534         .find_pll = intel_find_best_PLL,
 535 };
 536
 537 static const intel_limit_t intel_limits_ironlake_dac = {
 538         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 539         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 540         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 541         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 542         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 543         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 544         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 545         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 546         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 547                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 548                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 549         .find_pll = intel_g4x_find_best_PLL,
 550 };
 551
 552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 553         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 554         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 555         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 556         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 557         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 558         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 559         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 560         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 561         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 562                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 563                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 564         .find_pll = intel_g4x_find_best_PLL,
 565 };
 566
 567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 568         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 569         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 570         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 571         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 572         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 573         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 574         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 575         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 576         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 577                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 578                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 579         .find_pll = intel_g4x_find_best_PLL,
 580 };
 581
 582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 583         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 584         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 585         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 586         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 587         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 588         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 589         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 590         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 591         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 592                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 593                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 594         .find_pll = intel_g4x_find_best_PLL,
 595 };
 596
 597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 598         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 599         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 600         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 601         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 602         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 603         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 604         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 605         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 606         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 607                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 608                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 609         .find_pll = intel_g4x_find_best_PLL,
 610 };
 611
 612 static const intel_limit_t intel_limits_ironlake_display_port = {
 613         .dot = { .min = IRONLAKE_DOT_MIN,
 614                  .max = IRONLAKE_DOT_MAX },
 615         .vco = { .min = IRONLAKE_VCO_MIN,
 616                  .max = IRONLAKE_VCO_MAX},
 617         .n   = { .min = IRONLAKE_DP_N_MIN,
 618                  .max = IRONLAKE_DP_N_MAX },
 619         .m   = { .min = IRONLAKE_DP_M_MIN,
 620                  .max = IRONLAKE_DP_M_MAX },
 621         .m1  = { .min = IRONLAKE_M1_MIN,
 622                  .max = IRONLAKE_M1_MAX },
 623         .m2  = { .min = IRONLAKE_M2_MIN,
 624                  .max = IRONLAKE_M2_MAX },
 625         .p   = { .min = IRONLAKE_DP_P_MIN,
 626                  .max = IRONLAKE_DP_P_MAX },
 627         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 628                  .max = IRONLAKE_DP_P1_MAX},
 629         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 630                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 631                  .p2_fast = IRONLAKE_DP_P2_FAST },
 632         .find_pll = intel_find_pll_ironlake_dp,
 633 };
 634
 635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         const intel_limit_t *limit;
 640         int refclk = 120;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 644                         refclk = 100;
 645
 646                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 647                     LVDS_CLKB_POWER_UP) {
 648                         /* LVDS dual channel */
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_dual_lvds;
 653                 } else {
 654                         if (refclk == 100)
 655                                 limit = &intel_limits_ironlake_single_lvds_100m;
 656                         else
 657                                 limit = &intel_limits_ironlake_single_lvds;
 658                 }
 659         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 660                         HAS_eDP)
 661                 limit = &intel_limits_ironlake_display_port;
 662         else
 663                 limit = &intel_limits_ironlake_dac;
 664
 665         return limit;
 666 }
 667
 668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         const intel_limit_t *limit;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 676                     LVDS_CLKB_POWER_UP)
 677                         /* LVDS with dual channel */
 678                         limit = &intel_limits_g4x_dual_channel_lvds;
 679                 else
 680                         /* LVDS with dual channel */
 681                         limit = &intel_limits_g4x_single_channel_lvds;
 682         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 683                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 684                 limit = &intel_limits_g4x_hdmi;
 685         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 686                 limit = &intel_limits_g4x_sdvo;
 687         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 688                 limit = &intel_limits_g4x_display_port;
 689         } else /* The option is for other outputs */
 690                 limit = &intel_limits_i9xx_sdvo;
 691
 692         return limit;
 693 }
 694
 695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 696 {
 697         struct drm_device *dev = crtc->dev;
 698         const intel_limit_t *limit;
 699
 700         if (HAS_PCH_SPLIT(dev))
 701                 limit = intel_ironlake_limit(crtc);
 702         else if (IS_G4X(dev)) {
 703                 limit = intel_g4x_limit(crtc);
 704         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_i9xx_lvds;
 707                 else
 708                         limit = &intel_limits_i9xx_sdvo;
 709         } else if (IS_PINEVIEW(dev)) {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_pineview_lvds;
 712                 else
 713                         limit = &intel_limits_pineview_sdvo;
 714         } else {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_i8xx_lvds;
 717                 else
 718                         limit = &intel_limits_i8xx_dvo;
 719         }
 720         return limit;
 721 }
 722
 723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 724 static void pineview_clock(int refclk, intel_clock_t *clock)
 725 {
 726         clock->m = clock->m2 + 2;
 727         clock->p = clock->p1 * clock->p2;
 728         clock->vco = refclk * clock->m / clock->n;
 729         clock->dot = clock->vco / clock->p;
 730 }
 731
 732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 733 {
 734         if (IS_PINEVIEW(dev)) {
 735                 pineview_clock(refclk, clock);
 736                 return;
 737         }
 738         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 739         clock->p = clock->p1 * clock->p2;
 740         clock->vco = refclk * clock->m / (clock->n + 2);
 741         clock->dot = clock->vco / clock->p;
 742 }
 743
 744 /**
 745  * Returns whether any output on the specified pipe is of the specified type
 746  */
 747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 748 {
 749     struct drm_device *dev = crtc->dev;
 750     struct drm_mode_config *mode_config = &dev->mode_config;
 751     struct drm_encoder *l_entry;
 752
 753     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 754             if (l_entry && l_entry->crtc == crtc) {
 755                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 756                     if (intel_encoder->type == type)
 757                             return true;
 758             }
 759     }
 760     return false;
 761 }
 762
 763 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 764 /**
 765  * Returns whether the given set of divisors are valid for a given refclk with
 766  * the given connectors.
 767  */
 768
 769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 770 {
 771         const intel_limit_t *limit = intel_limit (crtc);
 772         struct drm_device *dev = crtc->dev;
 773
 774         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 775                 INTELPllInvalid ("p1 out of range\n");
 776         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 777                 INTELPllInvalid ("p out of range\n");
 778         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 779                 INTELPllInvalid ("m2 out of range\n");
 780         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 781                 INTELPllInvalid ("m1 out of range\n");
 782         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 783                 INTELPllInvalid ("m1 <= m2\n");
 784         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 785                 INTELPllInvalid ("m out of range\n");
 786         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 787                 INTELPllInvalid ("n out of range\n");
 788         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 789                 INTELPllInvalid ("vco out of range\n");
 790         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 791          * connector, etc., rather than just a single range.
 792          */
 793         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 794                 INTELPllInvalid ("dot out of range\n");
 795
 796         return true;
 797 }
 798
 799 static bool
 800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 801                     int target, int refclk, intel_clock_t *best_clock)
 802
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         intel_clock_t clock;
 807         int err = target;
 808
 809         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 810             (I915_READ(LVDS)) != 0) {
 811                 /*
 812                  * For LVDS, if the panel is on, just rely on its current
 813                  * settings for dual-channel.  We haven't figured out how to
 814                  * reliably set up different single/dual channel state, if we
 815                  * even can.
 816                  */
 817                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 818                     LVDS_CLKB_POWER_UP)
 819                         clock.p2 = limit->p2.p2_fast;
 820                 else
 821                         clock.p2 = limit->p2.p2_slow;
 822         } else {
 823                 if (target < limit->p2.dot_limit)
 824                         clock.p2 = limit->p2.p2_slow;
 825                 else
 826                         clock.p2 = limit->p2.p2_fast;
 827         }
 828
 829         memset (best_clock, 0, sizeof (*best_clock));
 830
 831         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 832              clock.m1++) {
 833                 for (clock.m2 = limit->m2.min;
 834                      clock.m2 <= limit->m2.max; clock.m2++) {
 835                         /* m1 is always 0 in Pineview */
 836                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 837                                 break;
 838                         for (clock.n = limit->n.min;
 839                              clock.n <= limit->n.max; clock.n++) {
 840                                 for (clock.p1 = limit->p1.min;
 841                                         clock.p1 <= limit->p1.max; clock.p1++) {
 842                                         int this_err;
 843
 844                                         intel_clock(dev, refclk, &clock);
 845
 846                                         if (!intel_PLL_is_valid(crtc, &clock))
 847                                                 continue;
 848
 849                                         this_err = abs(clock.dot - target);
 850                                         if (this_err < err) {
 851                                                 *best_clock = clock;
 852                                                 err = this_err;
 853                                         }
 854                                 }
 855                         }
 856                 }
 857         }
 858
 859         return (err != target);
 860 }
 861
 862 static bool
 863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 864                         int target, int refclk, intel_clock_t *best_clock)
 865 {
 866         struct drm_device *dev = crtc->dev;
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         intel_clock_t clock;
 869         int max_n;
 870         bool found;
 871         /* approximately equals target * 0.00585 */
 872         int err_most = (target >> 8) + (target >> 9);
 873         found = false;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 876                 int lvds_reg;
 877
 878                 if (HAS_PCH_SPLIT(dev))
 879                         lvds_reg = PCH_LVDS;
 880                 else
 881                         lvds_reg = LVDS;
 882                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 883                     LVDS_CLKB_POWER_UP)
 884                         clock.p2 = limit->p2.p2_fast;
 885                 else
 886                         clock.p2 = limit->p2.p2_slow;
 887         } else {
 888                 if (target < limit->p2.dot_limit)
 889                         clock.p2 = limit->p2.p2_slow;
 890                 else
 891                         clock.p2 = limit->p2.p2_fast;
 892         }
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895         max_n = limit->n.max;
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 /* based on hardware requirement, prefere larger m1,m2 */
 899                 for (clock.m1 = limit->m1.max;
 900                      clock.m1 >= limit->m1.min; clock.m1--) {
 901                         for (clock.m2 = limit->m2.max;
 902                              clock.m2 >= limit->m2.min; clock.m2--) {
 903                                 for (clock.p1 = limit->p1.max;
 904                                      clock.p1 >= limit->p1.min; clock.p1--) {
 905                                         int this_err;
 906
 907                                         intel_clock(dev, refclk, &clock);
 908                                         if (!intel_PLL_is_valid(crtc, &clock))
 909                                                 continue;
 910                                         this_err = abs(clock.dot - target) ;
 911                                         if (this_err < err_most) {
 912                                                 *best_clock = clock;
 913                                                 err_most = this_err;
 914                                                 max_n = clock.n;
 915                                                 found = true;
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         return found;
 922 }
 923
 924 static bool
 925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 926                            int target, int refclk, intel_clock_t *best_clock)
 927 {
 928         struct drm_device *dev = crtc->dev;
 929         intel_clock_t clock;
 930
 931         /* return directly when it is eDP */
 932         if (HAS_eDP)
 933                 return true;
 934
 935         if (target < 200000) {
 936                 clock.n = 1;
 937                 clock.p1 = 2;
 938                 clock.p2 = 10;
 939                 clock.m1 = 12;
 940                 clock.m2 = 9;
 941         } else {
 942                 clock.n = 2;
 943                 clock.p1 = 1;
 944                 clock.p2 = 10;
 945                 clock.m1 = 14;
 946                 clock.m2 = 8;
 947         }
 948         intel_clock(dev, refclk, &clock);
 949         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 950         return true;
 951 }
 952
 953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 954 static bool
 955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 956                       int target, int refclk, intel_clock_t *best_clock)
 957 {
 958     intel_clock_t clock;
 959     if (target < 200000) {
 960         clock.p1 = 2;
 961         clock.p2 = 10;
 962         clock.n = 2;
 963         clock.m1 = 23;
 964         clock.m2 = 8;
 965     } else {
 966         clock.p1 = 1;
 967         clock.p2 = 10;
 968         clock.n = 1;
 969         clock.m1 = 14;
 970         clock.m2 = 2;
 971     }
 972     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 973     clock.p = (clock.p1 * clock.p2);
 974     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 975     clock.vco = 0;
 976     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 977     return true;
 978 }
 979
 980 /**
 981  * intel_wait_for_vblank - wait for vblank on a given pipe
 982  * @dev: drm device
 983  * @pipe: pipe to wait for
 984  *
 985  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 986  * mode setting code.
 987  */
 988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 992
 993         /* Wait for vblank interrupt bit to set */
 994         if (wait_for((I915_READ(pipestat_reg) &
 995                       PIPE_VBLANK_INTERRUPT_STATUS) == 0,
 996                      50, 0))
 997                 DRM_DEBUG_KMS("vblank wait timed out\n");
 998 }
 999
1000 /**
1001  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1002  * @dev: drm device
1003  * @pipe: pipe to wait for
1004  *
1005  * After disabling a pipe, we can't wait for vblank in the usual way,
1006  * spinning on the vblank interrupt status bit, since we won't actually
1007  * see an interrupt when the pipe is disabled.
1008  *
1009  * So this function waits for the display line value to settle (it
1010  * usually ends up stopping at the start of the next frame).
1011  */
1012 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1013 {
1014         struct drm_i915_private *dev_priv = dev->dev_private;
1015         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1016         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1017         u32 last_line;
1018
1019         /* Wait for the display line to settle */
1020         do {
1021                 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1022                 mdelay(5);
1023         } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1024                  time_after(timeout, jiffies));
1025
1026         if (time_after(jiffies, timeout))
1027                 DRM_DEBUG_KMS("vblank wait timed out\n");
1028 }
1029
1030 /* Parameters have changed, update FBC info */
1031 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1032 {
1033         struct drm_device *dev = crtc->dev;
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         struct drm_framebuffer *fb = crtc->fb;
1036         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039         int plane, i;
1040         u32 fbc_ctl, fbc_ctl2;
1041
1042         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1043
1044         if (fb->pitch < dev_priv->cfb_pitch)
1045                 dev_priv->cfb_pitch = fb->pitch;
1046
1047         /* FBC_CTL wants 64B units */
1048         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1049         dev_priv->cfb_fence = obj_priv->fence_reg;
1050         dev_priv->cfb_plane = intel_crtc->plane;
1051         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1052
1053         /* Clear old tags */
1054         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1055                 I915_WRITE(FBC_TAG + (i * 4), 0);
1056
1057         /* Set it up... */
1058         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1059         if (obj_priv->tiling_mode != I915_TILING_NONE)
1060                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1061         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1062         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1063
1064         /* enable it... */
1065         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1066         if (IS_I945GM(dev))
1067                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1068         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1069         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1070         if (obj_priv->tiling_mode != I915_TILING_NONE)
1071                 fbc_ctl |= dev_priv->cfb_fence;
1072         I915_WRITE(FBC_CONTROL, fbc_ctl);
1073
1074         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1075                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1076 }
1077
1078 void i8xx_disable_fbc(struct drm_device *dev)
1079 {
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         u32 fbc_ctl;
1082
1083         if (!I915_HAS_FBC(dev))
1084                 return;
1085
1086         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1087                 return; /* Already off, just return */
1088
1089         /* Disable compression */
1090         fbc_ctl = I915_READ(FBC_CONTROL);
1091         fbc_ctl &= ~FBC_CTL_EN;
1092         I915_WRITE(FBC_CONTROL, fbc_ctl);
1093
1094         /* Wait for compressing bit to clear */
1095         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1096                 DRM_DEBUG_KMS("FBC idle timed out\n");
1097                 return;
1098         }
1099
1100         DRM_DEBUG_KMS("disabled FBC\n");
1101 }
1102
1103 static bool i8xx_fbc_enabled(struct drm_device *dev)
1104 {
1105         struct drm_i915_private *dev_priv = dev->dev_private;
1106
1107         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1108 }
1109
1110 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1111 {
1112         struct drm_device *dev = crtc->dev;
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         struct drm_framebuffer *fb = crtc->fb;
1115         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1116         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1118         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1119                      DPFC_CTL_PLANEB);
1120         unsigned long stall_watermark = 200;
1121         u32 dpfc_ctl;
1122
1123         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1124         dev_priv->cfb_fence = obj_priv->fence_reg;
1125         dev_priv->cfb_plane = intel_crtc->plane;
1126
1127         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1128         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1129                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1130                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1131         } else {
1132                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1133         }
1134
1135         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1136         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1137                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1138                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1139         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1140
1141         /* enable it... */
1142         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1143
1144         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1145 }
1146
1147 void g4x_disable_fbc(struct drm_device *dev)
1148 {
1149         struct drm_i915_private *dev_priv = dev->dev_private;
1150         u32 dpfc_ctl;
1151
1152         /* Disable compression */
1153         dpfc_ctl = I915_READ(DPFC_CONTROL);
1154         dpfc_ctl &= ~DPFC_CTL_EN;
1155         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1156
1157         DRM_DEBUG_KMS("disabled FBC\n");
1158 }
1159
1160 static bool g4x_fbc_enabled(struct drm_device *dev)
1161 {
1162         struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1165 }
1166
1167 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1168 {
1169         struct drm_device *dev = crtc->dev;
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         struct drm_framebuffer *fb = crtc->fb;
1172         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1173         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1175         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1176                                                DPFC_CTL_PLANEB;
1177         unsigned long stall_watermark = 200;
1178         u32 dpfc_ctl;
1179
1180         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1181         dev_priv->cfb_fence = obj_priv->fence_reg;
1182         dev_priv->cfb_plane = intel_crtc->plane;
1183
1184         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1185         dpfc_ctl &= DPFC_RESERVED;
1186         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1187         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1188                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1189                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1190         } else {
1191                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1192         }
1193
1194         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1195         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1196                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1197                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1198         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1199         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1200         /* enable it... */
1201         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1202                    DPFC_CTL_EN);
1203
1204         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1205 }
1206
1207 void ironlake_disable_fbc(struct drm_device *dev)
1208 {
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210         u32 dpfc_ctl;
1211
1212         /* Disable compression */
1213         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1214         dpfc_ctl &= ~DPFC_CTL_EN;
1215         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1216
1217         DRM_DEBUG_KMS("disabled FBC\n");
1218 }
1219
1220 static bool ironlake_fbc_enabled(struct drm_device *dev)
1221 {
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223
1224         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1225 }
1226
1227 bool intel_fbc_enabled(struct drm_device *dev)
1228 {
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230
1231         if (!dev_priv->display.fbc_enabled)
1232                 return false;
1233
1234         return dev_priv->display.fbc_enabled(dev);
1235 }
1236
1237 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1238 {
1239         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1240
1241         if (!dev_priv->display.enable_fbc)
1242                 return;
1243
1244         dev_priv->display.enable_fbc(crtc, interval);
1245 }
1246
1247 void intel_disable_fbc(struct drm_device *dev)
1248 {
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250
1251         if (!dev_priv->display.disable_fbc)
1252                 return;
1253
1254         dev_priv->display.disable_fbc(dev);
1255 }
1256
1257 /**
1258  * intel_update_fbc - enable/disable FBC as needed
1259  * @crtc: CRTC to point the compressor at
1260  * @mode: mode in use
1261  *
1262  * Set up the framebuffer compression hardware at mode set time.  We
1263  * enable it if possible:
1264  *   - plane A only (on pre-965)
1265  *   - no pixel mulitply/line duplication
1266  *   - no alpha buffer discard
1267  *   - no dual wide
1268  *   - framebuffer <= 2048 in width, 1536 in height
1269  *
1270  * We can't assume that any compression will take place (worst case),
1271  * so the compressed buffer has to be the same size as the uncompressed
1272  * one.  It also must reside (along with the line length buffer) in
1273  * stolen memory.
1274  *
1275  * We need to enable/disable FBC on a global basis.
1276  */
1277 static void intel_update_fbc(struct drm_crtc *crtc,
1278                              struct drm_display_mode *mode)
1279 {
1280         struct drm_device *dev = crtc->dev;
1281         struct drm_i915_private *dev_priv = dev->dev_private;
1282         struct drm_framebuffer *fb = crtc->fb;
1283         struct intel_framebuffer *intel_fb;
1284         struct drm_i915_gem_object *obj_priv;
1285         struct drm_crtc *tmp_crtc;
1286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1287         int plane = intel_crtc->plane;
1288         int crtcs_enabled = 0;
1289
1290         DRM_DEBUG_KMS("\n");
1291
1292         if (!i915_powersave)
1293                 return;
1294
1295         if (!I915_HAS_FBC(dev))
1296                 return;
1297
1298         if (!crtc->fb)
1299                 return;
1300
1301         intel_fb = to_intel_framebuffer(fb);
1302         obj_priv = to_intel_bo(intel_fb->obj);
1303
1304         /*
1305          * If FBC is already on, we just have to verify that we can
1306          * keep it that way...
1307          * Need to disable if:
1308          *   - more than one pipe is active
1309          *   - changing FBC params (stride, fence, mode)
1310          *   - new fb is too large to fit in compressed buffer
1311          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1312          */
1313         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1314                 if (tmp_crtc->enabled)
1315                         crtcs_enabled++;
1316         }
1317         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1318         if (crtcs_enabled > 1) {
1319                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1320                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1321                 goto out_disable;
1322         }
1323         if (intel_fb->obj->size > dev_priv->cfb_size) {
1324                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1325                                 "compression\n");
1326                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1327                 goto out_disable;
1328         }
1329         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1330             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1331                 DRM_DEBUG_KMS("mode incompatible with compression, "
1332                                 "disabling\n");
1333                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1334                 goto out_disable;
1335         }
1336         if ((mode->hdisplay > 2048) ||
1337             (mode->vdisplay > 1536)) {
1338                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1339                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1340                 goto out_disable;
1341         }
1342         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1343                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1344                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1345                 goto out_disable;
1346         }
1347         if (obj_priv->tiling_mode != I915_TILING_X) {
1348                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1349                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1350                 goto out_disable;
1351         }
1352
1353         /* If the kernel debugger is active, always disable compression */
1354         if (in_dbg_master())
1355                 goto out_disable;
1356
1357         if (intel_fbc_enabled(dev)) {
1358                 /* We can re-enable it in this case, but need to update pitch */
1359                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1360                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1361                     (plane != dev_priv->cfb_plane))
1362                         intel_disable_fbc(dev);
1363         }
1364
1365         /* Now try to turn it back on if possible */
1366         if (!intel_fbc_enabled(dev))
1367                 intel_enable_fbc(crtc, 500);
1368
1369         return;
1370
1371 out_disable:
1372         /* Multiple disables should be harmless */
1373         if (intel_fbc_enabled(dev)) {
1374                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1375                 intel_disable_fbc(dev);
1376         }
1377 }
1378
1379 int
1380 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1381 {
1382         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1383         u32 alignment;
1384         int ret;
1385
1386         switch (obj_priv->tiling_mode) {
1387         case I915_TILING_NONE:
1388                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1389                         alignment = 128 * 1024;
1390                 else if (IS_I965G(dev))
1391                         alignment = 4 * 1024;
1392                 else
1393                         alignment = 64 * 1024;
1394                 break;
1395         case I915_TILING_X:
1396                 /* pin() will align the object as required by fence */
1397                 alignment = 0;
1398                 break;
1399         case I915_TILING_Y:
1400                 /* FIXME: Is this true? */
1401                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1402                 return -EINVAL;
1403         default:
1404                 BUG();
1405         }
1406
1407         ret = i915_gem_object_pin(obj, alignment);
1408         if (ret != 0)
1409                 return ret;
1410
1411         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1412          * fence, whereas 965+ only requires a fence if using
1413          * framebuffer compression.  For simplicity, we always install
1414          * a fence as the cost is not that onerous.
1415          */
1416         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1417             obj_priv->tiling_mode != I915_TILING_NONE) {
1418                 ret = i915_gem_object_get_fence_reg(obj);
1419                 if (ret != 0) {
1420                         i915_gem_object_unpin(obj);
1421                         return ret;
1422                 }
1423         }
1424
1425         return 0;
1426 }
1427
1428 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1429 static int
1430 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1431                            int x, int y)
1432 {
1433         struct drm_device *dev = crtc->dev;
1434         struct drm_i915_private *dev_priv = dev->dev_private;
1435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1436         struct intel_framebuffer *intel_fb;
1437         struct drm_i915_gem_object *obj_priv;
1438         struct drm_gem_object *obj;
1439         int plane = intel_crtc->plane;
1440         unsigned long Start, Offset;
1441         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1442         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1443         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1444         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1445         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1446         u32 dspcntr;
1447
1448         switch (plane) {
1449         case 0:
1450         case 1:
1451                 break;
1452         default:
1453                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1454                 return -EINVAL;
1455         }
1456
1457         intel_fb = to_intel_framebuffer(fb);
1458         obj = intel_fb->obj;
1459         obj_priv = to_intel_bo(obj);
1460
1461         dspcntr = I915_READ(dspcntr_reg);
1462         /* Mask out pixel format bits in case we change it */
1463         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1464         switch (fb->bits_per_pixel) {
1465         case 8:
1466                 dspcntr |= DISPPLANE_8BPP;
1467                 break;
1468         case 16:
1469                 if (fb->depth == 15)
1470                         dspcntr |= DISPPLANE_15_16BPP;
1471                 else
1472                         dspcntr |= DISPPLANE_16BPP;
1473                 break;
1474         case 24:
1475         case 32:
1476                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1477                 break;
1478         default:
1479                 DRM_ERROR("Unknown color depth\n");
1480                 return -EINVAL;
1481         }
1482         if (IS_I965G(dev)) {
1483                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1484                         dspcntr |= DISPPLANE_TILED;
1485                 else
1486                         dspcntr &= ~DISPPLANE_TILED;
1487         }
1488
1489         if (IS_IRONLAKE(dev))
1490                 /* must disable */
1491                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1492
1493         I915_WRITE(dspcntr_reg, dspcntr);
1494
1495         Start = obj_priv->gtt_offset;
1496         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1497
1498         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1499         I915_WRITE(dspstride, fb->pitch);
1500         if (IS_I965G(dev)) {
1501                 I915_WRITE(dspbase, Offset);
1502                 I915_READ(dspbase);
1503                 I915_WRITE(dspsurf, Start);
1504                 I915_READ(dspsurf);
1505                 I915_WRITE(dsptileoff, (y << 16) | x);
1506         } else {
1507                 I915_WRITE(dspbase, Start + Offset);
1508                 I915_READ(dspbase);
1509         }
1510
1511         if ((IS_I965G(dev) || plane == 0))
1512                 intel_update_fbc(crtc, &crtc->mode);
1513
1514         intel_wait_for_vblank(dev, intel_crtc->pipe);
1515         intel_increase_pllclock(crtc, true);
1516
1517         return 0;
1518 }
1519
1520 static int
1521 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1522                     struct drm_framebuffer *old_fb)
1523 {
1524         struct drm_device *dev = crtc->dev;
1525         struct drm_i915_private *dev_priv = dev->dev_private;
1526         struct drm_i915_master_private *master_priv;
1527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1528         struct intel_framebuffer *intel_fb;
1529         struct drm_i915_gem_object *obj_priv;
1530         struct drm_gem_object *obj;
1531         int pipe = intel_crtc->pipe;
1532         int plane = intel_crtc->plane;
1533         unsigned long Start, Offset;
1534         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1535         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1536         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1537         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1538         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1539         u32 dspcntr;
1540         int ret;
1541
1542         /* no fb bound */
1543         if (!crtc->fb) {
1544                 DRM_DEBUG_KMS("No FB bound\n");
1545                 return 0;
1546         }
1547
1548         switch (plane) {
1549         case 0:
1550         case 1:
1551                 break;
1552         default:
1553                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1554                 return -EINVAL;
1555         }
1556
1557         intel_fb = to_intel_framebuffer(crtc->fb);
1558         obj = intel_fb->obj;
1559         obj_priv = to_intel_bo(obj);
1560
1561         mutex_lock(&dev->struct_mutex);
1562         ret = intel_pin_and_fence_fb_obj(dev, obj);
1563         if (ret != 0) {
1564                 mutex_unlock(&dev->struct_mutex);
1565                 return ret;
1566         }
1567
1568         ret = i915_gem_object_set_to_display_plane(obj);
1569         if (ret != 0) {
1570                 i915_gem_object_unpin(obj);
1571                 mutex_unlock(&dev->struct_mutex);
1572                 return ret;
1573         }
1574
1575         dspcntr = I915_READ(dspcntr_reg);
1576         /* Mask out pixel format bits in case we change it */
1577         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1578         switch (crtc->fb->bits_per_pixel) {
1579         case 8:
1580                 dspcntr |= DISPPLANE_8BPP;
1581                 break;
1582         case 16:
1583                 if (crtc->fb->depth == 15)
1584                         dspcntr |= DISPPLANE_15_16BPP;
1585                 else
1586                         dspcntr |= DISPPLANE_16BPP;
1587                 break;
1588         case 24:
1589         case 32:
1590                 if (crtc->fb->depth == 30)
1591                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1592                 else
1593                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1594                 break;
1595         default:
1596                 DRM_ERROR("Unknown color depth\n");
1597                 i915_gem_object_unpin(obj);
1598                 mutex_unlock(&dev->struct_mutex);
1599                 return -EINVAL;
1600         }
1601         if (IS_I965G(dev)) {
1602                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1603                         dspcntr |= DISPPLANE_TILED;
1604                 else
1605                         dspcntr &= ~DISPPLANE_TILED;
1606         }
1607
1608         if (HAS_PCH_SPLIT(dev))
1609                 /* must disable */
1610                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1611
1612         I915_WRITE(dspcntr_reg, dspcntr);
1613
1614         Start = obj_priv->gtt_offset;
1615         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1616
1617         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1618                       Start, Offset, x, y, crtc->fb->pitch);
1619         I915_WRITE(dspstride, crtc->fb->pitch);
1620         if (IS_I965G(dev)) {
1621                 I915_WRITE(dspsurf, Start);
1622                 I915_WRITE(dsptileoff, (y << 16) | x);
1623                 I915_WRITE(dspbase, Offset);
1624         } else {
1625                 I915_WRITE(dspbase, Start + Offset);
1626         }
1627         POSTING_READ(dspbase);
1628
1629         if ((IS_I965G(dev) || plane == 0))
1630                 intel_update_fbc(crtc, &crtc->mode);
1631
1632         intel_wait_for_vblank(dev, pipe);
1633
1634         if (old_fb) {
1635                 intel_fb = to_intel_framebuffer(old_fb);
1636                 obj_priv = to_intel_bo(intel_fb->obj);
1637                 i915_gem_object_unpin(intel_fb->obj);
1638         }
1639         intel_increase_pllclock(crtc, true);
1640
1641         mutex_unlock(&dev->struct_mutex);
1642
1643         if (!dev->primary->master)
1644                 return 0;
1645
1646         master_priv = dev->primary->master->driver_priv;
1647         if (!master_priv->sarea_priv)
1648                 return 0;
1649
1650         if (pipe) {
1651                 master_priv->sarea_priv->pipeB_x = x;
1652                 master_priv->sarea_priv->pipeB_y = y;
1653         } else {
1654                 master_priv->sarea_priv->pipeA_x = x;
1655                 master_priv->sarea_priv->pipeA_y = y;
1656         }
1657
1658         return 0;
1659 }
1660
1661 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1662 {
1663         struct drm_device *dev = crtc->dev;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         u32 dpa_ctl;
1666
1667         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1668         dpa_ctl = I915_READ(DP_A);
1669         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1670
1671         if (clock < 200000) {
1672                 u32 temp;
1673                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1674                 /* workaround for 160Mhz:
1675                    1) program 0x4600c bits 15:0 = 0x8124
1676                    2) program 0x46010 bit 0 = 1
1677                    3) program 0x46034 bit 24 = 1
1678                    4) program 0x64000 bit 14 = 1
1679                    */
1680                 temp = I915_READ(0x4600c);
1681                 temp &= 0xffff0000;
1682                 I915_WRITE(0x4600c, temp | 0x8124);
1683
1684                 temp = I915_READ(0x46010);
1685                 I915_WRITE(0x46010, temp | 1);
1686
1687                 temp = I915_READ(0x46034);
1688                 I915_WRITE(0x46034, temp | (1 << 24));
1689         } else {
1690                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1691         }
1692         I915_WRITE(DP_A, dpa_ctl);
1693
1694         udelay(500);
1695 }
1696
1697 /* The FDI link training functions for ILK/Ibexpeak. */
1698 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1699 {
1700         struct drm_device *dev = crtc->dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1703         int pipe = intel_crtc->pipe;
1704         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1705         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1706         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1707         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1708         u32 temp, tries = 0;
1709
1710         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1711            for train result */
1712         temp = I915_READ(fdi_rx_imr_reg);
1713         temp &= ~FDI_RX_SYMBOL_LOCK;
1714         temp &= ~FDI_RX_BIT_LOCK;
1715         I915_WRITE(fdi_rx_imr_reg, temp);
1716         I915_READ(fdi_rx_imr_reg);
1717         udelay(150);
1718
1719         /* enable CPU FDI TX and PCH FDI RX */
1720         temp = I915_READ(fdi_tx_reg);
1721         temp |= FDI_TX_ENABLE;
1722         temp &= ~(7 << 19);
1723         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1724         temp &= ~FDI_LINK_TRAIN_NONE;
1725         temp |= FDI_LINK_TRAIN_PATTERN_1;
1726         I915_WRITE(fdi_tx_reg, temp);
1727         I915_READ(fdi_tx_reg);
1728
1729         temp = I915_READ(fdi_rx_reg);
1730         temp &= ~FDI_LINK_TRAIN_NONE;
1731         temp |= FDI_LINK_TRAIN_PATTERN_1;
1732         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1733         I915_READ(fdi_rx_reg);
1734         udelay(150);
1735
1736         for (tries = 0; tries < 5; tries++) {
1737                 temp = I915_READ(fdi_rx_iir_reg);
1738                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1739
1740                 if ((temp & FDI_RX_BIT_LOCK)) {
1741                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1742                         I915_WRITE(fdi_rx_iir_reg,
1743                                    temp | FDI_RX_BIT_LOCK);
1744                         break;
1745                 }
1746         }
1747         if (tries == 5)
1748                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1749
1750         /* Train 2 */
1751         temp = I915_READ(fdi_tx_reg);
1752         temp &= ~FDI_LINK_TRAIN_NONE;
1753         temp |= FDI_LINK_TRAIN_PATTERN_2;
1754         I915_WRITE(fdi_tx_reg, temp);
1755
1756         temp = I915_READ(fdi_rx_reg);
1757         temp &= ~FDI_LINK_TRAIN_NONE;
1758         temp |= FDI_LINK_TRAIN_PATTERN_2;
1759         I915_WRITE(fdi_rx_reg, temp);
1760         udelay(150);
1761
1762         tries = 0;
1763
1764         for (tries = 0; tries < 5; tries++) {
1765                 temp = I915_READ(fdi_rx_iir_reg);
1766                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1767
1768                 if (temp & FDI_RX_SYMBOL_LOCK) {
1769                         I915_WRITE(fdi_rx_iir_reg,
1770                                    temp | FDI_RX_SYMBOL_LOCK);
1771                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1772                         break;
1773                 }
1774         }
1775         if (tries == 5)
1776                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1777
1778         DRM_DEBUG_KMS("FDI train done\n");
1779 }
1780
1781 static int snb_b_fdi_train_param [] = {
1782         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1783         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1784         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1785         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1786 };
1787
1788 /* The FDI link training functions for SNB/Cougarpoint. */
1789 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1790 {
1791         struct drm_device *dev = crtc->dev;
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1794         int pipe = intel_crtc->pipe;
1795         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1796         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1797         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1798         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1799         u32 temp, i;
1800
1801         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1802            for train result */
1803         temp = I915_READ(fdi_rx_imr_reg);
1804         temp &= ~FDI_RX_SYMBOL_LOCK;
1805         temp &= ~FDI_RX_BIT_LOCK;
1806         I915_WRITE(fdi_rx_imr_reg, temp);
1807         I915_READ(fdi_rx_imr_reg);
1808         udelay(150);
1809
1810         /* enable CPU FDI TX and PCH FDI RX */
1811         temp = I915_READ(fdi_tx_reg);
1812         temp |= FDI_TX_ENABLE;
1813         temp &= ~(7 << 19);
1814         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1815         temp &= ~FDI_LINK_TRAIN_NONE;
1816         temp |= FDI_LINK_TRAIN_PATTERN_1;
1817         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1818         /* SNB-B */
1819         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1820         I915_WRITE(fdi_tx_reg, temp);
1821         I915_READ(fdi_tx_reg);
1822
1823         temp = I915_READ(fdi_rx_reg);
1824         if (HAS_PCH_CPT(dev)) {
1825                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1826                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1827         } else {
1828                 temp &= ~FDI_LINK_TRAIN_NONE;
1829                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1830         }
1831         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1832         I915_READ(fdi_rx_reg);
1833         udelay(150);
1834
1835         for (i = 0; i < 4; i++ ) {
1836                 temp = I915_READ(fdi_tx_reg);
1837                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838                 temp |= snb_b_fdi_train_param[i];
1839                 I915_WRITE(fdi_tx_reg, temp);
1840                 udelay(500);
1841
1842                 temp = I915_READ(fdi_rx_iir_reg);
1843                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1844
1845                 if (temp & FDI_RX_BIT_LOCK) {
1846                         I915_WRITE(fdi_rx_iir_reg,
1847                                    temp | FDI_RX_BIT_LOCK);
1848                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1849                         break;
1850                 }
1851         }
1852         if (i == 4)
1853                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1854
1855         /* Train 2 */
1856         temp = I915_READ(fdi_tx_reg);
1857         temp &= ~FDI_LINK_TRAIN_NONE;
1858         temp |= FDI_LINK_TRAIN_PATTERN_2;
1859         if (IS_GEN6(dev)) {
1860                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1861                 /* SNB-B */
1862                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1863         }
1864         I915_WRITE(fdi_tx_reg, temp);
1865
1866         temp = I915_READ(fdi_rx_reg);
1867         if (HAS_PCH_CPT(dev)) {
1868                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1869                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1870         } else {
1871                 temp &= ~FDI_LINK_TRAIN_NONE;
1872                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1873         }
1874         I915_WRITE(fdi_rx_reg, temp);
1875         udelay(150);
1876
1877         for (i = 0; i < 4; i++ ) {
1878                 temp = I915_READ(fdi_tx_reg);
1879                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1880                 temp |= snb_b_fdi_train_param[i];
1881                 I915_WRITE(fdi_tx_reg, temp);
1882                 udelay(500);
1883
1884                 temp = I915_READ(fdi_rx_iir_reg);
1885                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1886
1887                 if (temp & FDI_RX_SYMBOL_LOCK) {
1888                         I915_WRITE(fdi_rx_iir_reg,
1889                                    temp | FDI_RX_SYMBOL_LOCK);
1890                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1891                         break;
1892                 }
1893         }
1894         if (i == 4)
1895                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1896
1897         DRM_DEBUG_KMS("FDI train done.\n");
1898 }
1899
1900 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1901 {
1902         struct drm_device *dev = crtc->dev;
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905         int pipe = intel_crtc->pipe;
1906         int plane = intel_crtc->plane;
1907         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1908         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1909         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1910         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1911         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1912         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1913         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1914         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1915         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1916         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1917         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1918         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1919         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1920         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1921         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1922         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1923         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1924         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1925         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1926         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1927         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1928         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1929         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1930         u32 temp;
1931         u32 pipe_bpc;
1932
1933         temp = I915_READ(pipeconf_reg);
1934         pipe_bpc = temp & PIPE_BPC_MASK;
1935
1936         /* XXX: When our outputs are all unaware of DPMS modes other than off
1937          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1938          */
1939         switch (mode) {
1940         case DRM_MODE_DPMS_ON:
1941         case DRM_MODE_DPMS_STANDBY:
1942         case DRM_MODE_DPMS_SUSPEND:
1943                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1944
1945                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1946                         temp = I915_READ(PCH_LVDS);
1947                         if ((temp & LVDS_PORT_EN) == 0) {
1948                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1949                                 POSTING_READ(PCH_LVDS);
1950                         }
1951                 }
1952
1953                 if (!HAS_eDP) {
1954
1955                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1956                         temp = I915_READ(fdi_rx_reg);
1957                         /*
1958                          * make the BPC in FDI Rx be consistent with that in
1959                          * pipeconf reg.
1960                          */
1961                         temp &= ~(0x7 << 16);
1962                         temp |= (pipe_bpc << 11);
1963                         temp &= ~(7 << 19);
1964                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1965                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1966                         I915_READ(fdi_rx_reg);
1967                         udelay(200);
1968
1969                         /* Switch from Rawclk to PCDclk */
1970                         temp = I915_READ(fdi_rx_reg);
1971                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1972                         I915_READ(fdi_rx_reg);
1973                         udelay(200);
1974
1975                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1976                         temp = I915_READ(fdi_tx_reg);
1977                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1978                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1979                                 I915_READ(fdi_tx_reg);
1980                                 udelay(100);
1981                         }
1982                 }
1983
1984                 /* Enable panel fitting for LVDS */
1985                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1986                     || HAS_eDP || intel_pch_has_edp(crtc)) {
1987                         if (dev_priv->pch_pf_size) {
1988                                 temp = I915_READ(pf_ctl_reg);
1989                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1990                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
1991                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
1992                         } else
1993                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1994                 }
1995
1996                 /* Enable CPU pipe */
1997                 temp = I915_READ(pipeconf_reg);
1998                 if ((temp & PIPEACONF_ENABLE) == 0) {
1999                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2000                         I915_READ(pipeconf_reg);
2001                         udelay(100);
2002                 }
2003
2004                 /* configure and enable CPU plane */
2005                 temp = I915_READ(dspcntr_reg);
2006                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2007                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2008                         /* Flush the plane changes */
2009                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2010                 }
2011
2012                 if (!HAS_eDP) {
2013                         /* For PCH output, training FDI link */
2014                         if (IS_GEN6(dev))
2015                                 gen6_fdi_link_train(crtc);
2016                         else
2017                                 ironlake_fdi_link_train(crtc);
2018
2019                         /* enable PCH DPLL */
2020                         temp = I915_READ(pch_dpll_reg);
2021                         if ((temp & DPLL_VCO_ENABLE) == 0) {
2022                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2023                                 I915_READ(pch_dpll_reg);
2024                         }
2025                         udelay(200);
2026
2027                         if (HAS_PCH_CPT(dev)) {
2028                                 /* Be sure PCH DPLL SEL is set */
2029                                 temp = I915_READ(PCH_DPLL_SEL);
2030                                 if (trans_dpll_sel == 0 &&
2031                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2032                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2033                                 else if (trans_dpll_sel == 1 &&
2034                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2035                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2036                                 I915_WRITE(PCH_DPLL_SEL, temp);
2037                                 I915_READ(PCH_DPLL_SEL);
2038                         }
2039
2040                         /* set transcoder timing */
2041                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2042                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2043                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2044
2045                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2046                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2047                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2048
2049                         /* enable normal train */
2050                         temp = I915_READ(fdi_tx_reg);
2051                         temp &= ~FDI_LINK_TRAIN_NONE;
2052                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2053                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2054                         I915_READ(fdi_tx_reg);
2055
2056                         temp = I915_READ(fdi_rx_reg);
2057                         if (HAS_PCH_CPT(dev)) {
2058                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2059                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2060                         } else {
2061                                 temp &= ~FDI_LINK_TRAIN_NONE;
2062                                 temp |= FDI_LINK_TRAIN_NONE;
2063                         }
2064                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2065                         I915_READ(fdi_rx_reg);
2066
2067                         /* wait one idle pattern time */
2068                         udelay(100);
2069
2070                         /* For PCH DP, enable TRANS_DP_CTL */
2071                         if (HAS_PCH_CPT(dev) &&
2072                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2073                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2074                                 int reg;
2075
2076                                 reg = I915_READ(trans_dp_ctl);
2077                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2078                                          TRANS_DP_SYNC_MASK);
2079                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2080                                         TRANS_DP_ENH_FRAMING);
2081
2082                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2083                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2084                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2085                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2086
2087                                 switch (intel_trans_dp_port_sel(crtc)) {
2088                                 case PCH_DP_B:
2089                                         reg |= TRANS_DP_PORT_SEL_B;
2090                                         break;
2091                                 case PCH_DP_C:
2092                                         reg |= TRANS_DP_PORT_SEL_C;
2093                                         break;
2094                                 case PCH_DP_D:
2095                                         reg |= TRANS_DP_PORT_SEL_D;
2096                                         break;
2097                                 default:
2098                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2099                                         reg |= TRANS_DP_PORT_SEL_B;
2100                                         break;
2101                                 }
2102
2103                                 I915_WRITE(trans_dp_ctl, reg);
2104                                 POSTING_READ(trans_dp_ctl);
2105                         }
2106
2107                         /* enable PCH transcoder */
2108                         temp = I915_READ(transconf_reg);
2109                         /*
2110                          * make the BPC in transcoder be consistent with
2111                          * that in pipeconf reg.
2112                          */
2113                         temp &= ~PIPE_BPC_MASK;
2114                         temp |= pipe_bpc;
2115                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2116                         I915_READ(transconf_reg);
2117
2118                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2119                                 DRM_ERROR("failed to enable transcoder\n");
2120                 }
2121
2122                 intel_crtc_load_lut(crtc);
2123
2124                 intel_update_fbc(crtc, &crtc->mode);
2125                 break;
2126
2127         case DRM_MODE_DPMS_OFF:
2128                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2129
2130                 drm_vblank_off(dev, pipe);
2131                 /* Disable display plane */
2132                 temp = I915_READ(dspcntr_reg);
2133                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2134                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2135                         /* Flush the plane changes */
2136                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2137                         I915_READ(dspbase_reg);
2138                 }
2139
2140                 if (dev_priv->cfb_plane == plane &&
2141                     dev_priv->display.disable_fbc)
2142                         dev_priv->display.disable_fbc(dev);
2143
2144                 /* disable cpu pipe, disable after all planes disabled */
2145                 temp = I915_READ(pipeconf_reg);
2146                 if ((temp & PIPEACONF_ENABLE) != 0) {
2147                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2148
2149                         /* wait for cpu pipe off, pipe state */
2150                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2151                                 DRM_ERROR("failed to turn off cpu pipe\n");
2152                 } else
2153                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2154
2155                 udelay(100);
2156
2157                 /* Disable PF */
2158                 temp = I915_READ(pf_ctl_reg);
2159                 if ((temp & PF_ENABLE) != 0) {
2160                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2161                         I915_READ(pf_ctl_reg);
2162                 }
2163                 I915_WRITE(pf_win_size, 0);
2164                 POSTING_READ(pf_win_size);
2165
2166
2167                 /* disable CPU FDI tx and PCH FDI rx */
2168                 temp = I915_READ(fdi_tx_reg);
2169                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2170                 I915_READ(fdi_tx_reg);
2171
2172                 temp = I915_READ(fdi_rx_reg);
2173                 /* BPC in FDI rx is consistent with that in pipeconf */
2174                 temp &= ~(0x07 << 16);
2175                 temp |= (pipe_bpc << 11);
2176                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2177                 I915_READ(fdi_rx_reg);
2178
2179                 udelay(100);
2180
2181                 /* still set train pattern 1 */
2182                 temp = I915_READ(fdi_tx_reg);
2183                 temp &= ~FDI_LINK_TRAIN_NONE;
2184                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2185                 I915_WRITE(fdi_tx_reg, temp);
2186                 POSTING_READ(fdi_tx_reg);
2187
2188                 temp = I915_READ(fdi_rx_reg);
2189                 if (HAS_PCH_CPT(dev)) {
2190                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2191                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2192                 } else {
2193                         temp &= ~FDI_LINK_TRAIN_NONE;
2194                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2195                 }
2196                 I915_WRITE(fdi_rx_reg, temp);
2197                 POSTING_READ(fdi_rx_reg);
2198
2199                 udelay(100);
2200
2201                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2202                         temp = I915_READ(PCH_LVDS);
2203                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2204                         I915_READ(PCH_LVDS);
2205                         udelay(100);
2206                 }
2207
2208                 /* disable PCH transcoder */
2209                 temp = I915_READ(transconf_reg);
2210                 if ((temp & TRANS_ENABLE) != 0) {
2211                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2212
2213                         /* wait for PCH transcoder off, transcoder state */
2214                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2215                                 DRM_ERROR("failed to disable transcoder\n");
2216                 }
2217
2218                 temp = I915_READ(transconf_reg);
2219                 /* BPC in transcoder is consistent with that in pipeconf */
2220                 temp &= ~PIPE_BPC_MASK;
2221                 temp |= pipe_bpc;
2222                 I915_WRITE(transconf_reg, temp);
2223                 I915_READ(transconf_reg);
2224                 udelay(100);
2225
2226                 if (HAS_PCH_CPT(dev)) {
2227                         /* disable TRANS_DP_CTL */
2228                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2229                         int reg;
2230
2231                         reg = I915_READ(trans_dp_ctl);
2232                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2233                         I915_WRITE(trans_dp_ctl, reg);
2234                         POSTING_READ(trans_dp_ctl);
2235
2236                         /* disable DPLL_SEL */
2237                         temp = I915_READ(PCH_DPLL_SEL);
2238                         if (trans_dpll_sel == 0)
2239                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2240                         else
2241                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2242                         I915_WRITE(PCH_DPLL_SEL, temp);
2243                         I915_READ(PCH_DPLL_SEL);
2244
2245                 }
2246
2247                 /* disable PCH DPLL */
2248                 temp = I915_READ(pch_dpll_reg);
2249                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2250                 I915_READ(pch_dpll_reg);
2251
2252                 /* Switch from PCDclk to Rawclk */
2253                 temp = I915_READ(fdi_rx_reg);
2254                 temp &= ~FDI_SEL_PCDCLK;
2255                 I915_WRITE(fdi_rx_reg, temp);
2256                 I915_READ(fdi_rx_reg);
2257
2258                 /* Disable CPU FDI TX PLL */
2259                 temp = I915_READ(fdi_tx_reg);
2260                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2261                 I915_READ(fdi_tx_reg);
2262                 udelay(100);
2263
2264                 temp = I915_READ(fdi_rx_reg);
2265                 temp &= ~FDI_RX_PLL_ENABLE;
2266                 I915_WRITE(fdi_rx_reg, temp);
2267                 I915_READ(fdi_rx_reg);
2268
2269                 /* Wait for the clocks to turn off. */
2270                 udelay(100);
2271                 break;
2272         }
2273 }
2274
2275 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2276 {
2277         struct intel_overlay *overlay;
2278         int ret;
2279
2280         if (!enable && intel_crtc->overlay) {
2281                 overlay = intel_crtc->overlay;
2282                 mutex_lock(&overlay->dev->struct_mutex);
2283                 for (;;) {
2284                         ret = intel_overlay_switch_off(overlay);
2285                         if (ret == 0)
2286                                 break;
2287
2288                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2289                         if (ret != 0) {
2290                                 /* overlay doesn't react anymore. Usually
2291                                  * results in a black screen and an unkillable
2292                                  * X server. */
2293                                 BUG();
2294                                 overlay->hw_wedged = HW_WEDGED;
2295                                 break;
2296                         }
2297                 }
2298                 mutex_unlock(&overlay->dev->struct_mutex);
2299         }
2300         /* Let userspace switch the overlay on again. In most cases userspace
2301          * has to recompute where to put it anyway. */
2302
2303         return;
2304 }
2305
2306 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2307 {
2308         struct drm_device *dev = crtc->dev;
2309         struct drm_i915_private *dev_priv = dev->dev_private;
2310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311         int pipe = intel_crtc->pipe;
2312         int plane = intel_crtc->plane;
2313         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2314         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2315         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2316         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2317         u32 temp;
2318
2319         /* XXX: When our outputs are all unaware of DPMS modes other than off
2320          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2321          */
2322         switch (mode) {
2323         case DRM_MODE_DPMS_ON:
2324         case DRM_MODE_DPMS_STANDBY:
2325         case DRM_MODE_DPMS_SUSPEND:
2326                 /* Enable the DPLL */
2327                 temp = I915_READ(dpll_reg);
2328                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2329                         I915_WRITE(dpll_reg, temp);
2330                         I915_READ(dpll_reg);
2331                         /* Wait for the clocks to stabilize. */
2332                         udelay(150);
2333                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2334                         I915_READ(dpll_reg);
2335                         /* Wait for the clocks to stabilize. */
2336                         udelay(150);
2337                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2338                         I915_READ(dpll_reg);
2339                         /* Wait for the clocks to stabilize. */
2340                         udelay(150);
2341                 }
2342
2343                 /* Enable the pipe */
2344                 temp = I915_READ(pipeconf_reg);
2345                 if ((temp & PIPEACONF_ENABLE) == 0)
2346                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2347
2348                 /* Enable the plane */
2349                 temp = I915_READ(dspcntr_reg);
2350                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2351                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2352                         /* Flush the plane changes */
2353                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2354                 }
2355
2356                 intel_crtc_load_lut(crtc);
2357
2358                 if ((IS_I965G(dev) || plane == 0))
2359                         intel_update_fbc(crtc, &crtc->mode);
2360
2361                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2362                 intel_crtc_dpms_overlay(intel_crtc, true);
2363         break;
2364         case DRM_MODE_DPMS_OFF:
2365                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2366                 intel_crtc_dpms_overlay(intel_crtc, false);
2367                 drm_vblank_off(dev, pipe);
2368
2369                 if (dev_priv->cfb_plane == plane &&
2370                     dev_priv->display.disable_fbc)
2371                         dev_priv->display.disable_fbc(dev);
2372
2373                 /* Disable display plane */
2374                 temp = I915_READ(dspcntr_reg);
2375                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2376                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2377                         /* Flush the plane changes */
2378                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2379                         I915_READ(dspbase_reg);
2380                 }
2381
2382                 /* Wait for vblank for the disable to take effect */
2383                 intel_wait_for_vblank_off(dev, pipe);
2384
2385                 /* Don't disable pipe A or pipe A PLLs if needed */
2386                 if (pipeconf_reg == PIPEACONF &&
2387                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2388                         goto skip_pipe_off;
2389
2390                 /* Next, disable display pipes */
2391                 temp = I915_READ(pipeconf_reg);
2392                 if ((temp & PIPEACONF_ENABLE) != 0) {
2393                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2394                         I915_READ(pipeconf_reg);
2395                 }
2396
2397                 /* Wait for vblank for the disable to take effect. */
2398                 intel_wait_for_vblank_off(dev, pipe);
2399
2400                 temp = I915_READ(dpll_reg);
2401                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2402                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2403                         I915_READ(dpll_reg);
2404                 }
2405         skip_pipe_off:
2406                 /* Wait for the clocks to turn off. */
2407                 udelay(150);
2408                 break;
2409         }
2410 }
2411
2412 /**
2413  * Sets the power management mode of the pipe and plane.
2414  */
2415 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2416 {
2417         struct drm_device *dev = crtc->dev;
2418         struct drm_i915_private *dev_priv = dev->dev_private;
2419         struct drm_i915_master_private *master_priv;
2420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2421         int pipe = intel_crtc->pipe;
2422         bool enabled;
2423
2424         intel_crtc->dpms_mode = mode;
2425         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2426
2427         /* When switching on the display, ensure that SR is disabled
2428          * with multiple pipes prior to enabling to new pipe.
2429          *
2430          * When switching off the display, make sure the cursor is
2431          * properly hidden prior to disabling the pipe.
2432          */
2433         if (mode == DRM_MODE_DPMS_ON)
2434                 intel_update_watermarks(dev);
2435         else
2436                 intel_crtc_update_cursor(crtc);
2437
2438         dev_priv->display.dpms(crtc, mode);
2439
2440         if (mode == DRM_MODE_DPMS_ON)
2441                 intel_crtc_update_cursor(crtc);
2442         else
2443                 intel_update_watermarks(dev);
2444
2445         if (!dev->primary->master)
2446                 return;
2447
2448         master_priv = dev->primary->master->driver_priv;
2449         if (!master_priv->sarea_priv)
2450                 return;
2451
2452         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2453
2454         switch (pipe) {
2455         case 0:
2456                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2457                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2458                 break;
2459         case 1:
2460                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2461                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2462                 break;
2463         default:
2464                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2465                 break;
2466         }
2467 }
2468
2469 static void intel_crtc_prepare (struct drm_crtc *crtc)
2470 {
2471         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2472         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2473 }
2474
2475 static void intel_crtc_commit (struct drm_crtc *crtc)
2476 {
2477         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2478         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2479 }
2480
2481 void intel_encoder_prepare (struct drm_encoder *encoder)
2482 {
2483         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2484         /* lvds has its own version of prepare see intel_lvds_prepare */
2485         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2486 }
2487
2488 void intel_encoder_commit (struct drm_encoder *encoder)
2489 {
2490         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2491         /* lvds has its own version of commit see intel_lvds_commit */
2492         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2493 }
2494
2495 void intel_encoder_destroy(struct drm_encoder *encoder)
2496 {
2497         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2498
2499         if (intel_encoder->ddc_bus)
2500                 intel_i2c_destroy(intel_encoder->ddc_bus);
2501
2502         if (intel_encoder->i2c_bus)
2503                 intel_i2c_destroy(intel_encoder->i2c_bus);
2504
2505         drm_encoder_cleanup(encoder);
2506         kfree(intel_encoder);
2507 }
2508
2509 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2510                                   struct drm_display_mode *mode,
2511                                   struct drm_display_mode *adjusted_mode)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         if (HAS_PCH_SPLIT(dev)) {
2515                 /* FDI link clock is fixed at 2.7G */
2516                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2517                         return false;
2518         }
2519         return true;
2520 }
2521
2522 static int i945_get_display_clock_speed(struct drm_device *dev)
2523 {
2524         return 400000;
2525 }
2526
2527 static int i915_get_display_clock_speed(struct drm_device *dev)
2528 {
2529         return 333000;
2530 }
2531
2532 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2533 {
2534         return 200000;
2535 }
2536
2537 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2538 {
2539         u16 gcfgc = 0;
2540
2541         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2542
2543         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2544                 return 133000;
2545         else {
2546                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2547                 case GC_DISPLAY_CLOCK_333_MHZ:
2548                         return 333000;
2549                 default:
2550                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2551                         return 190000;
2552                 }
2553         }
2554 }
2555
2556 static int i865_get_display_clock_speed(struct drm_device *dev)
2557 {
2558         return 266000;
2559 }
2560
2561 static int i855_get_display_clock_speed(struct drm_device *dev)
2562 {
2563         u16 hpllcc = 0;
2564         /* Assume that the hardware is in the high speed state.  This
2565          * should be the default.
2566          */
2567         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2568         case GC_CLOCK_133_200:
2569         case GC_CLOCK_100_200:
2570                 return 200000;
2571         case GC_CLOCK_166_250:
2572                 return 250000;
2573         case GC_CLOCK_100_133:
2574                 return 133000;
2575         }
2576
2577         /* Shouldn't happen */
2578         return 0;
2579 }
2580
2581 static int i830_get_display_clock_speed(struct drm_device *dev)
2582 {
2583         return 133000;
2584 }
2585
2586 /**
2587  * Return the pipe currently connected to the panel fitter,
2588  * or -1 if the panel fitter is not present or not in use
2589  */
2590 int intel_panel_fitter_pipe (struct drm_device *dev)
2591 {
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593         u32  pfit_control;
2594
2595         /* i830 doesn't have a panel fitter */
2596         if (IS_I830(dev))
2597                 return -1;
2598
2599         pfit_control = I915_READ(PFIT_CONTROL);
2600
2601         /* See if the panel fitter is in use */
2602         if ((pfit_control & PFIT_ENABLE) == 0)
2603                 return -1;
2604
2605         /* 965 can place panel fitter on either pipe */
2606         if (IS_I965G(dev))
2607                 return (pfit_control >> 29) & 0x3;
2608
2609         /* older chips can only use pipe 1 */
2610         return 1;
2611 }
2612
2613 struct fdi_m_n {
2614         u32        tu;
2615         u32        gmch_m;
2616         u32        gmch_n;
2617         u32        link_m;
2618         u32        link_n;
2619 };
2620
2621 static void
2622 fdi_reduce_ratio(u32 *num, u32 *den)
2623 {
2624         while (*num > 0xffffff || *den > 0xffffff) {
2625                 *num >>= 1;
2626                 *den >>= 1;
2627         }
2628 }
2629
2630 #define DATA_N 0x800000
2631 #define LINK_N 0x80000
2632
2633 static void
2634 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2635                      int link_clock, struct fdi_m_n *m_n)
2636 {
2637         u64 temp;
2638
2639         m_n->tu = 64; /* default size */
2640
2641         temp = (u64) DATA_N * pixel_clock;
2642         temp = div_u64(temp, link_clock);
2643         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2644         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2645         m_n->gmch_n = DATA_N;
2646         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2647
2648         temp = (u64) LINK_N * pixel_clock;
2649         m_n->link_m = div_u64(temp, link_clock);
2650         m_n->link_n = LINK_N;
2651         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2652 }
2653
2654
2655 struct intel_watermark_params {
2656         unsigned long fifo_size;
2657         unsigned long max_wm;
2658         unsigned long default_wm;
2659         unsigned long guard_size;
2660         unsigned long cacheline_size;
2661 };
2662
2663 /* Pineview has different values for various configs */
2664 static struct intel_watermark_params pineview_display_wm = {
2665         PINEVIEW_DISPLAY_FIFO,
2666         PINEVIEW_MAX_WM,
2667         PINEVIEW_DFT_WM,
2668         PINEVIEW_GUARD_WM,
2669         PINEVIEW_FIFO_LINE_SIZE
2670 };
2671 static struct intel_watermark_params pineview_display_hplloff_wm = {
2672         PINEVIEW_DISPLAY_FIFO,
2673         PINEVIEW_MAX_WM,
2674         PINEVIEW_DFT_HPLLOFF_WM,
2675         PINEVIEW_GUARD_WM,
2676         PINEVIEW_FIFO_LINE_SIZE
2677 };
2678 static struct intel_watermark_params pineview_cursor_wm = {
2679         PINEVIEW_CURSOR_FIFO,
2680         PINEVIEW_CURSOR_MAX_WM,
2681         PINEVIEW_CURSOR_DFT_WM,
2682         PINEVIEW_CURSOR_GUARD_WM,
2683         PINEVIEW_FIFO_LINE_SIZE,
2684 };
2685 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2686         PINEVIEW_CURSOR_FIFO,
2687         PINEVIEW_CURSOR_MAX_WM,
2688         PINEVIEW_CURSOR_DFT_WM,
2689         PINEVIEW_CURSOR_GUARD_WM,
2690         PINEVIEW_FIFO_LINE_SIZE
2691 };
2692 static struct intel_watermark_params g4x_wm_info = {
2693         G4X_FIFO_SIZE,
2694         G4X_MAX_WM,
2695         G4X_MAX_WM,
2696         2,
2697         G4X_FIFO_LINE_SIZE,
2698 };
2699 static struct intel_watermark_params g4x_cursor_wm_info = {
2700         I965_CURSOR_FIFO,
2701         I965_CURSOR_MAX_WM,
2702         I965_CURSOR_DFT_WM,
2703         2,
2704         G4X_FIFO_LINE_SIZE,
2705 };
2706 static struct intel_watermark_params i965_cursor_wm_info = {
2707         I965_CURSOR_FIFO,
2708         I965_CURSOR_MAX_WM,
2709         I965_CURSOR_DFT_WM,
2710         2,
2711         I915_FIFO_LINE_SIZE,
2712 };
2713 static struct intel_watermark_params i945_wm_info = {
2714         I945_FIFO_SIZE,
2715         I915_MAX_WM,
2716         1,
2717         2,
2718         I915_FIFO_LINE_SIZE
2719 };
2720 static struct intel_watermark_params i915_wm_info = {
2721         I915_FIFO_SIZE,
2722         I915_MAX_WM,
2723         1,
2724         2,
2725         I915_FIFO_LINE_SIZE
2726 };
2727 static struct intel_watermark_params i855_wm_info = {
2728         I855GM_FIFO_SIZE,
2729         I915_MAX_WM,
2730         1,
2731         2,
2732         I830_FIFO_LINE_SIZE
2733 };
2734 static struct intel_watermark_params i830_wm_info = {
2735         I830_FIFO_SIZE,
2736         I915_MAX_WM,
2737         1,
2738         2,
2739         I830_FIFO_LINE_SIZE
2740 };
2741
2742 static struct intel_watermark_params ironlake_display_wm_info = {
2743         ILK_DISPLAY_FIFO,
2744         ILK_DISPLAY_MAXWM,
2745         ILK_DISPLAY_DFTWM,
2746         2,
2747         ILK_FIFO_LINE_SIZE
2748 };
2749
2750 static struct intel_watermark_params ironlake_cursor_wm_info = {
2751         ILK_CURSOR_FIFO,
2752         ILK_CURSOR_MAXWM,
2753         ILK_CURSOR_DFTWM,
2754         2,
2755         ILK_FIFO_LINE_SIZE
2756 };
2757
2758 static struct intel_watermark_params ironlake_display_srwm_info = {
2759         ILK_DISPLAY_SR_FIFO,
2760         ILK_DISPLAY_MAX_SRWM,
2761         ILK_DISPLAY_DFT_SRWM,
2762         2,
2763         ILK_FIFO_LINE_SIZE
2764 };
2765
2766 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2767         ILK_CURSOR_SR_FIFO,
2768         ILK_CURSOR_MAX_SRWM,
2769         ILK_CURSOR_DFT_SRWM,
2770         2,
2771         ILK_FIFO_LINE_SIZE
2772 };
2773
2774 /**
2775  * intel_calculate_wm - calculate watermark level
2776  * @clock_in_khz: pixel clock
2777  * @wm: chip FIFO params
2778  * @pixel_size: display pixel size
2779  * @latency_ns: memory latency for the platform
2780  *
2781  * Calculate the watermark level (the level at which the display plane will
2782  * start fetching from memory again).  Each chip has a different display
2783  * FIFO size and allocation, so the caller needs to figure that out and pass
2784  * in the correct intel_watermark_params structure.
2785  *
2786  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2787  * on the pixel size.  When it reaches the watermark level, it'll start
2788  * fetching FIFO line sized based chunks from memory until the FIFO fills
2789  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2790  * will occur, and a display engine hang could result.
2791  */
2792 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2793                                         struct intel_watermark_params *wm,
2794                                         int pixel_size,
2795                                         unsigned long latency_ns)
2796 {
2797         long entries_required, wm_size;
2798
2799         /*
2800          * Note: we need to make sure we don't overflow for various clock &
2801          * latency values.
2802          * clocks go from a few thousand to several hundred thousand.
2803          * latency is usually a few thousand
2804          */
2805         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2806                 1000;
2807         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2808
2809         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2810
2811         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2812
2813         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2814
2815         /* Don't promote wm_size to unsigned... */
2816         if (wm_size > (long)wm->max_wm)
2817                 wm_size = wm->max_wm;
2818         if (wm_size <= 0) {
2819                 wm_size = wm->default_wm;
2820                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2821                           " entries required = %ld, available = %lu.\n",
2822                           entries_required + wm->guard_size,
2823                           wm->fifo_size);
2824         }
2825
2826         return wm_size;
2827 }
2828
2829 struct cxsr_latency {
2830         int is_desktop;
2831         int is_ddr3;
2832         unsigned long fsb_freq;
2833         unsigned long mem_freq;
2834         unsigned long display_sr;
2835         unsigned long display_hpll_disable;
2836         unsigned long cursor_sr;
2837         unsigned long cursor_hpll_disable;
2838 };
2839
2840 static const struct cxsr_latency cxsr_latency_table[] = {
2841         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2842         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2843         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2844         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2845         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2846
2847         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2848         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2849         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2850         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2851         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2852
2853         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2854         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2855         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2856         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2857         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2858
2859         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2860         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2861         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2862         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2863         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2864
2865         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2866         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2867         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2868         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2869         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2870
2871         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2872         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2873         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2874         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2875         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2876 };
2877
2878 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2879                                                          int is_ddr3,
2880                                                          int fsb,
2881                                                          int mem)
2882 {
2883         const struct cxsr_latency *latency;
2884         int i;
2885
2886         if (fsb == 0 || mem == 0)
2887                 return NULL;
2888
2889         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2890                 latency = &cxsr_latency_table[i];
2891                 if (is_desktop == latency->is_desktop &&
2892                     is_ddr3 == latency->is_ddr3 &&
2893                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2894                         return latency;
2895         }
2896
2897         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2898
2899         return NULL;
2900 }
2901
2902 static void pineview_disable_cxsr(struct drm_device *dev)
2903 {
2904         struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906         /* deactivate cxsr */
2907         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2908 }
2909
2910 /*
2911  * Latency for FIFO fetches is dependent on several factors:
2912  *   - memory configuration (speed, channels)
2913  *   - chipset
2914  *   - current MCH state
2915  * It can be fairly high in some situations, so here we assume a fairly
2916  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2917  * set this value too high, the FIFO will fetch frequently to stay full)
2918  * and power consumption (set it too low to save power and we might see
2919  * FIFO underruns and display "flicker").
2920  *
2921  * A value of 5us seems to be a good balance; safe for very low end
2922  * platforms but not overly aggressive on lower latency configs.
2923  */
2924 static const int latency_ns = 5000;
2925
2926 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2927 {
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         uint32_t dsparb = I915_READ(DSPARB);
2930         int size;
2931
2932         size = dsparb & 0x7f;
2933         if (plane)
2934                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2935
2936         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2937                         plane ? "B" : "A", size);
2938
2939         return size;
2940 }
2941
2942 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2943 {
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         uint32_t dsparb = I915_READ(DSPARB);
2946         int size;
2947
2948         size = dsparb & 0x1ff;
2949         if (plane)
2950                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2951         size >>= 1; /* Convert to cachelines */
2952
2953         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2954                         plane ? "B" : "A", size);
2955
2956         return size;
2957 }
2958
2959 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2960 {
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         uint32_t dsparb = I915_READ(DSPARB);
2963         int size;
2964
2965         size = dsparb & 0x7f;
2966         size >>= 2; /* Convert to cachelines */
2967
2968         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2969                         plane ? "B" : "A",
2970                   size);
2971
2972         return size;
2973 }
2974
2975 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         uint32_t dsparb = I915_READ(DSPARB);
2979         int size;
2980
2981         size = dsparb & 0x7f;
2982         size >>= 1; /* Convert to cachelines */
2983
2984         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2985                         plane ? "B" : "A", size);
2986
2987         return size;
2988 }
2989
2990 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2991                           int planeb_clock, int sr_hdisplay, int unused,
2992                           int pixel_size)
2993 {
2994         struct drm_i915_private *dev_priv = dev->dev_private;
2995         const struct cxsr_latency *latency;
2996         u32 reg;
2997         unsigned long wm;
2998         int sr_clock;
2999
3000         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3001                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3002         if (!latency) {
3003                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3004                 pineview_disable_cxsr(dev);
3005                 return;
3006         }
3007
3008         if (!planea_clock || !planeb_clock) {
3009                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3010
3011                 /* Display SR */
3012                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3013                                         pixel_size, latency->display_sr);
3014                 reg = I915_READ(DSPFW1);
3015                 reg &= ~DSPFW_SR_MASK;
3016                 reg |= wm << DSPFW_SR_SHIFT;
3017                 I915_WRITE(DSPFW1, reg);
3018                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3019
3020                 /* cursor SR */
3021                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3022                                         pixel_size, latency->cursor_sr);
3023                 reg = I915_READ(DSPFW3);
3024                 reg &= ~DSPFW_CURSOR_SR_MASK;
3025                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3026                 I915_WRITE(DSPFW3, reg);
3027
3028                 /* Display HPLL off SR */
3029                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3030                                         pixel_size, latency->display_hpll_disable);
3031                 reg = I915_READ(DSPFW3);
3032                 reg &= ~DSPFW_HPLL_SR_MASK;
3033                 reg |= wm & DSPFW_HPLL_SR_MASK;
3034                 I915_WRITE(DSPFW3, reg);
3035
3036                 /* cursor HPLL off SR */
3037                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3038                                         pixel_size, latency->cursor_hpll_disable);
3039                 reg = I915_READ(DSPFW3);
3040                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3041                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3042                 I915_WRITE(DSPFW3, reg);
3043                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3044
3045                 /* activate cxsr */
3046                 I915_WRITE(DSPFW3,
3047                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3048                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3049         } else {
3050                 pineview_disable_cxsr(dev);
3051                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3052         }
3053 }
3054
3055 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3056                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3057                           int pixel_size)
3058 {
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         int total_size, cacheline_size;
3061         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3062         struct intel_watermark_params planea_params, planeb_params;
3063         unsigned long line_time_us;
3064         int sr_clock, sr_entries = 0, entries_required;
3065
3066         /* Create copies of the base settings for each pipe */
3067         planea_params = planeb_params = g4x_wm_info;
3068
3069         /* Grab a couple of global values before we overwrite them */
3070         total_size = planea_params.fifo_size;
3071         cacheline_size = planea_params.cacheline_size;
3072
3073         /*
3074          * Note: we need to make sure we don't overflow for various clock &
3075          * latency values.
3076          * clocks go from a few thousand to several hundred thousand.
3077          * latency is usually a few thousand
3078          */
3079         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3080                 1000;
3081         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3082         planea_wm = entries_required + planea_params.guard_size;
3083
3084         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3085                 1000;
3086         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3087         planeb_wm = entries_required + planeb_params.guard_size;
3088
3089         cursora_wm = cursorb_wm = 16;
3090         cursor_sr = 32;
3091
3092         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3093
3094         /* Calc sr entries for one plane configs */
3095         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3096                 /* self-refresh has much higher latency */
3097                 static const int sr_latency_ns = 12000;
3098
3099                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3100                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3101
3102                 /* Use ns/us then divide to preserve precision */
3103                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3104                               pixel_size * sr_hdisplay;
3105                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3106
3107                 entries_required = (((sr_latency_ns / line_time_us) +
3108                                      1000) / 1000) * pixel_size * 64;
3109                 entries_required = DIV_ROUND_UP(entries_required,
3110                                            g4x_cursor_wm_info.cacheline_size);
3111                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3112
3113                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3114                         cursor_sr = g4x_cursor_wm_info.max_wm;
3115                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3116                               "cursor %d\n", sr_entries, cursor_sr);
3117
3118                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3119         } else {
3120                 /* Turn off self refresh if both pipes are enabled */
3121                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3122                                         & ~FW_BLC_SELF_EN);
3123         }
3124
3125         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3126                   planea_wm, planeb_wm, sr_entries);
3127
3128         planea_wm &= 0x3f;
3129         planeb_wm &= 0x3f;
3130
3131         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3132                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3133                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3134         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3135                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3136         /* HPLL off in SR has some issues on G4x... disable it */
3137         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3138                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3139 }
3140
3141 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3142                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3143                            int pixel_size)
3144 {
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         unsigned long line_time_us;
3147         int sr_clock, sr_entries, srwm = 1;
3148         int cursor_sr = 16;
3149
3150         /* Calc sr entries for one plane configs */
3151         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3152                 /* self-refresh has much higher latency */
3153                 static const int sr_latency_ns = 12000;
3154
3155                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3156                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3157
3158                 /* Use ns/us then divide to preserve precision */
3159                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3160                               pixel_size * sr_hdisplay;
3161                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3162                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3163                 srwm = I965_FIFO_SIZE - sr_entries;
3164                 if (srwm < 0)
3165                         srwm = 1;
3166                 srwm &= 0x1ff;
3167
3168                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3169                              pixel_size * 64;
3170                 sr_entries = DIV_ROUND_UP(sr_entries,
3171                                           i965_cursor_wm_info.cacheline_size);
3172                 cursor_sr = i965_cursor_wm_info.fifo_size -
3173                             (sr_entries + i965_cursor_wm_info.guard_size);
3174
3175                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3176                         cursor_sr = i965_cursor_wm_info.max_wm;
3177
3178                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3179                               "cursor %d\n", srwm, cursor_sr);
3180
3181                 if (IS_I965GM(dev))
3182                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3183         } else {
3184                 /* Turn off self refresh if both pipes are enabled */
3185                 if (IS_I965GM(dev))
3186                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3187                                    & ~FW_BLC_SELF_EN);
3188         }
3189
3190         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3191                       srwm);
3192
3193         /* 965 has limitations... */
3194         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3195                    (8 << 0));
3196         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3197         /* update cursor SR watermark */
3198         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3199 }
3200
3201 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3202                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3203                            int pixel_size)
3204 {
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         uint32_t fwater_lo;
3207         uint32_t fwater_hi;
3208         int total_size, cacheline_size, cwm, srwm = 1;
3209         int planea_wm, planeb_wm;
3210         struct intel_watermark_params planea_params, planeb_params;
3211         unsigned long line_time_us;
3212         int sr_clock, sr_entries = 0;
3213
3214         /* Create copies of the base settings for each pipe */
3215         if (IS_I965GM(dev) || IS_I945GM(dev))
3216                 planea_params = planeb_params = i945_wm_info;
3217         else if (IS_I9XX(dev))
3218                 planea_params = planeb_params = i915_wm_info;
3219         else
3220                 planea_params = planeb_params = i855_wm_info;
3221
3222         /* Grab a couple of global values before we overwrite them */
3223         total_size = planea_params.fifo_size;
3224         cacheline_size = planea_params.cacheline_size;
3225
3226         /* Update per-plane FIFO sizes */
3227         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3228         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3229
3230         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3231                                        pixel_size, latency_ns);
3232         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3233                                        pixel_size, latency_ns);
3234         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3235
3236         /*
3237          * Overlay gets an aggressive default since video jitter is bad.
3238          */
3239         cwm = 2;
3240
3241         /* Calc sr entries for one plane configs */
3242         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3243             (!planea_clock || !planeb_clock)) {
3244                 /* self-refresh has much higher latency */
3245                 static const int sr_latency_ns = 6000;
3246
3247                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3248                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3249
3250                 /* Use ns/us then divide to preserve precision */
3251                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3252                               pixel_size * sr_hdisplay;
3253                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3254                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3255                 srwm = total_size - sr_entries;
3256                 if (srwm < 0)
3257                         srwm = 1;
3258
3259                 if (IS_I945G(dev) || IS_I945GM(dev))
3260                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3261                 else if (IS_I915GM(dev)) {
3262                         /* 915M has a smaller SRWM field */
3263                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3264                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3265                 }
3266         } else {
3267                 /* Turn off self refresh if both pipes are enabled */
3268                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3269                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3270                                    & ~FW_BLC_SELF_EN);
3271                 } else if (IS_I915GM(dev)) {
3272                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3273                 }
3274         }
3275
3276         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3277                   planea_wm, planeb_wm, cwm, srwm);
3278
3279         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3280         fwater_hi = (cwm & 0x1f);
3281
3282         /* Set request length to 8 cachelines per fetch */
3283         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3284         fwater_hi = fwater_hi | (1 << 8);
3285
3286         I915_WRITE(FW_BLC, fwater_lo);
3287         I915_WRITE(FW_BLC2, fwater_hi);
3288 }
3289
3290 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3291                            int unused2, int unused3, int pixel_size)
3292 {
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3295         int planea_wm;
3296
3297         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3298
3299         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3300                                        pixel_size, latency_ns);
3301         fwater_lo |= (3<<8) | planea_wm;
3302
3303         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3304
3305         I915_WRITE(FW_BLC, fwater_lo);
3306 }
3307
3308 #define ILK_LP0_PLANE_LATENCY           700
3309 #define ILK_LP0_CURSOR_LATENCY          1300
3310
3311 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3312                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3313                        int pixel_size)
3314 {
3315         struct drm_i915_private *dev_priv = dev->dev_private;
3316         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3317         int sr_wm, cursor_wm;
3318         unsigned long line_time_us;
3319         int sr_clock, entries_required;
3320         u32 reg_value;
3321         int line_count;
3322         int planea_htotal = 0, planeb_htotal = 0;
3323         struct drm_crtc *crtc;
3324
3325         /* Need htotal for all active display plane */
3326         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3327                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3328                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3329                         if (intel_crtc->plane == 0)
3330                                 planea_htotal = crtc->mode.htotal;
3331                         else
3332                                 planeb_htotal = crtc->mode.htotal;
3333                 }
3334         }
3335
3336         /* Calculate and update the watermark for plane A */
3337         if (planea_clock) {
3338                 entries_required = ((planea_clock / 1000) * pixel_size *
3339                                      ILK_LP0_PLANE_LATENCY) / 1000;
3340                 entries_required = DIV_ROUND_UP(entries_required,
3341                                                 ironlake_display_wm_info.cacheline_size);
3342                 planea_wm = entries_required +
3343                             ironlake_display_wm_info.guard_size;
3344
3345                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3346                         planea_wm = ironlake_display_wm_info.max_wm;
3347
3348                 /* Use the large buffer method to calculate cursor watermark */
3349                 line_time_us = (planea_htotal * 1000) / planea_clock;
3350
3351                 /* Use ns/us then divide to preserve precision */
3352                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3353
3354                 /* calculate the cursor watermark for cursor A */
3355                 entries_required = line_count * 64 * pixel_size;
3356                 entries_required = DIV_ROUND_UP(entries_required,
3357                                                 ironlake_cursor_wm_info.cacheline_size);
3358                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3359                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3360                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3361
3362                 reg_value = I915_READ(WM0_PIPEA_ILK);
3363                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3364                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3365                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3366                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3367                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3368                                 "cursor: %d\n", planea_wm, cursora_wm);
3369         }
3370         /* Calculate and update the watermark for plane B */
3371         if (planeb_clock) {
3372                 entries_required = ((planeb_clock / 1000) * pixel_size *
3373                                      ILK_LP0_PLANE_LATENCY) / 1000;
3374                 entries_required = DIV_ROUND_UP(entries_required,
3375                                                 ironlake_display_wm_info.cacheline_size);
3376                 planeb_wm = entries_required +
3377                             ironlake_display_wm_info.guard_size;
3378
3379                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3380                         planeb_wm = ironlake_display_wm_info.max_wm;
3381
3382                 /* Use the large buffer method to calculate cursor watermark */
3383                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3384
3385                 /* Use ns/us then divide to preserve precision */
3386                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3387
3388                 /* calculate the cursor watermark for cursor B */
3389                 entries_required = line_count * 64 * pixel_size;
3390                 entries_required = DIV_ROUND_UP(entries_required,
3391                                                 ironlake_cursor_wm_info.cacheline_size);
3392                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3393                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3394                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3395
3396                 reg_value = I915_READ(WM0_PIPEB_ILK);
3397                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3398                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3399                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3400                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3401                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3402                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3403         }
3404
3405         /*
3406          * Calculate and update the self-refresh watermark only when one
3407          * display plane is used.
3408          */
3409         if (!planea_clock || !planeb_clock) {
3410
3411                 /* Read the self-refresh latency. The unit is 0.5us */
3412                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3413
3414                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3415                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3416
3417                 /* Use ns/us then divide to preserve precision */
3418                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3419                                / 1000;
3420
3421                 /* calculate the self-refresh watermark for display plane */
3422                 entries_required = line_count * sr_hdisplay * pixel_size;
3423                 entries_required = DIV_ROUND_UP(entries_required,
3424                                                 ironlake_display_srwm_info.cacheline_size);
3425                 sr_wm = entries_required +
3426                         ironlake_display_srwm_info.guard_size;
3427
3428                 /* calculate the self-refresh watermark for display cursor */
3429                 entries_required = line_count * pixel_size * 64;
3430                 entries_required = DIV_ROUND_UP(entries_required,
3431                                                 ironlake_cursor_srwm_info.cacheline_size);
3432                 cursor_wm = entries_required +
3433                             ironlake_cursor_srwm_info.guard_size;
3434
3435                 /* configure watermark and enable self-refresh */
3436                 reg_value = I915_READ(WM1_LP_ILK);
3437                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3438                                WM1_LP_CURSOR_MASK);
3439                 reg_value |= WM1_LP_SR_EN |
3440                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3441                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3442
3443                 I915_WRITE(WM1_LP_ILK, reg_value);
3444                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3445                                 "cursor %d\n", sr_wm, cursor_wm);
3446
3447         } else {
3448                 /* Turn off self refresh if both pipes are enabled */
3449                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3450         }
3451 }
3452 /**
3453  * intel_update_watermarks - update FIFO watermark values based on current modes
3454  *
3455  * Calculate watermark values for the various WM regs based on current mode
3456  * and plane configuration.
3457  *
3458  * There are several cases to deal with here:
3459  *   - normal (i.e. non-self-refresh)
3460  *   - self-refresh (SR) mode
3461  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3462  *   - lines are small relative to FIFO size (buffer can hold more than 2
3463  *     lines), so need to account for TLB latency
3464  *
3465  *   The normal calculation is:
3466  *     watermark = dotclock * bytes per pixel * latency
3467  *   where latency is platform & configuration dependent (we assume pessimal
3468  *   values here).
3469  *
3470  *   The SR calculation is:
3471  *     watermark = (trunc(latency/line time)+1) * surface width *
3472  *       bytes per pixel
3473  *   where
3474  *     line time = htotal / dotclock
3475  *     surface width = hdisplay for normal plane and 64 for cursor
3476  *   and latency is assumed to be high, as above.
3477  *
3478  * The final value programmed to the register should always be rounded up,
3479  * and include an extra 2 entries to account for clock crossings.
3480  *
3481  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3482  * to set the non-SR watermarks to 8.
3483   */
3484 static void intel_update_watermarks(struct drm_device *dev)
3485 {
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         struct drm_crtc *crtc;
3488         int sr_hdisplay = 0;
3489         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3490         int enabled = 0, pixel_size = 0;
3491         int sr_htotal = 0;
3492
3493         if (!dev_priv->display.update_wm)
3494                 return;
3495
3496         /* Get the clock config from both planes */
3497         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3498                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3500                         enabled++;
3501                         if (intel_crtc->plane == 0) {
3502                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3503                                           intel_crtc->pipe, crtc->mode.clock);
3504                                 planea_clock = crtc->mode.clock;
3505                         } else {
3506                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3507                                           intel_crtc->pipe, crtc->mode.clock);
3508                                 planeb_clock = crtc->mode.clock;
3509                         }
3510                         sr_hdisplay = crtc->mode.hdisplay;
3511                         sr_clock = crtc->mode.clock;
3512                         sr_htotal = crtc->mode.htotal;
3513                         if (crtc->fb)
3514                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3515                         else
3516                                 pixel_size = 4; /* by default */
3517                 }
3518         }
3519
3520         if (enabled <= 0)
3521                 return;
3522
3523         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3524                                     sr_hdisplay, sr_htotal, pixel_size);
3525 }
3526
3527 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3528                                struct drm_display_mode *mode,
3529                                struct drm_display_mode *adjusted_mode,
3530                                int x, int y,
3531                                struct drm_framebuffer *old_fb)
3532 {
3533         struct drm_device *dev = crtc->dev;
3534         struct drm_i915_private *dev_priv = dev->dev_private;
3535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3536         int pipe = intel_crtc->pipe;
3537         int plane = intel_crtc->plane;
3538         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3539         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3540         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3541         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3542         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3543         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3544         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3545         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3546         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3547         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3548         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3549         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3550         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3551         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3552         int refclk, num_connectors = 0;
3553         intel_clock_t clock, reduced_clock;
3554         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3555         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3556         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3557         bool is_edp = false;
3558         struct drm_mode_config *mode_config = &dev->mode_config;
3559         struct drm_encoder *encoder;
3560         struct intel_encoder *intel_encoder = NULL;
3561         const intel_limit_t *limit;
3562         int ret;
3563         struct fdi_m_n m_n = {0};
3564         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3565         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3566         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3567         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3568         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3569         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3570         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3571         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3572         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3573         int lvds_reg = LVDS;
3574         u32 temp;
3575         int sdvo_pixel_multiply;
3576         int target_clock;
3577
3578         drm_vblank_pre_modeset(dev, pipe);
3579
3580         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3581
3582                 if (!encoder || encoder->crtc != crtc)
3583                         continue;
3584
3585                 intel_encoder = enc_to_intel_encoder(encoder);
3586
3587                 switch (intel_encoder->type) {
3588                 case INTEL_OUTPUT_LVDS:
3589                         is_lvds = true;
3590                         break;
3591                 case INTEL_OUTPUT_SDVO:
3592                 case INTEL_OUTPUT_HDMI:
3593                         is_sdvo = true;
3594                         if (intel_encoder->needs_tv_clock)
3595                                 is_tv = true;
3596                         break;
3597                 case INTEL_OUTPUT_DVO:
3598                         is_dvo = true;
3599                         break;
3600                 case INTEL_OUTPUT_TVOUT:
3601                         is_tv = true;
3602                         break;
3603                 case INTEL_OUTPUT_ANALOG:
3604                         is_crt = true;
3605                         break;
3606                 case INTEL_OUTPUT_DISPLAYPORT:
3607                         is_dp = true;
3608                         break;
3609                 case INTEL_OUTPUT_EDP:
3610                         is_edp = true;
3611                         break;
3612                 }
3613
3614                 num_connectors++;
3615         }
3616
3617         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3618                 refclk = dev_priv->lvds_ssc_freq * 1000;
3619                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3620                                         refclk / 1000);
3621         } else if (IS_I9XX(dev)) {
3622                 refclk = 96000;
3623                 if (HAS_PCH_SPLIT(dev))
3624                         refclk = 120000; /* 120Mhz refclk */
3625         } else {
3626                 refclk = 48000;
3627         }
3628
3629
3630         /*
3631          * Returns a set of divisors for the desired target clock with the given
3632          * refclk, or FALSE.  The returned values represent the clock equation:
3633          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3634          */
3635         limit = intel_limit(crtc);
3636         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3637         if (!ok) {
3638                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3639                 drm_vblank_post_modeset(dev, pipe);
3640                 return -EINVAL;
3641         }
3642
3643         /* Ensure that the cursor is valid for the new mode before changing... */
3644         intel_crtc_update_cursor(crtc);
3645
3646         if (is_lvds && dev_priv->lvds_downclock_avail) {
3647                 has_reduced_clock = limit->find_pll(limit, crtc,
3648                                                             dev_priv->lvds_downclock,
3649                                                             refclk,
3650                                                             &reduced_clock);
3651                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3652                         /*
3653                          * If the different P is found, it means that we can't
3654                          * switch the display clock by using the FP0/FP1.
3655                          * In such case we will disable the LVDS downclock
3656                          * feature.
3657                          */
3658                         DRM_DEBUG_KMS("Different P is found for "
3659                                                 "LVDS clock/downclock\n");
3660                         has_reduced_clock = 0;
3661                 }
3662         }
3663         /* SDVO TV has fixed PLL values depend on its clock range,
3664            this mirrors vbios setting. */
3665         if (is_sdvo && is_tv) {
3666                 if (adjusted_mode->clock >= 100000
3667                                 && adjusted_mode->clock < 140500) {
3668                         clock.p1 = 2;
3669                         clock.p2 = 10;
3670                         clock.n = 3;
3671                         clock.m1 = 16;
3672                         clock.m2 = 8;
3673                 } else if (adjusted_mode->clock >= 140500
3674                                 && adjusted_mode->clock <= 200000) {
3675                         clock.p1 = 1;
3676                         clock.p2 = 10;
3677                         clock.n = 6;
3678                         clock.m1 = 12;
3679                         clock.m2 = 8;
3680                 }
3681         }
3682
3683         /* FDI link */
3684         if (HAS_PCH_SPLIT(dev)) {
3685                 int lane = 0, link_bw, bpp;
3686                 /* eDP doesn't require FDI link, so just set DP M/N
3687                    according to current link config */
3688                 if (is_edp) {
3689                         target_clock = mode->clock;
3690                         intel_edp_link_config(intel_encoder,
3691                                         &lane, &link_bw);
3692                 } else {
3693                         /* DP over FDI requires target mode clock
3694                            instead of link clock */
3695                         if (is_dp)
3696                                 target_clock = mode->clock;
3697                         else
3698                                 target_clock = adjusted_mode->clock;
3699                         link_bw = 270000;
3700                 }
3701
3702                 /* determine panel color depth */
3703                 temp = I915_READ(pipeconf_reg);
3704                 temp &= ~PIPE_BPC_MASK;
3705                 if (is_lvds) {
3706                         int lvds_reg = I915_READ(PCH_LVDS);
3707                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3708                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3709                                 temp |= PIPE_8BPC;
3710                         else
3711                                 temp |= PIPE_6BPC;
3712                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3713                         switch (dev_priv->edp_bpp/3) {
3714                         case 8:
3715                                 temp |= PIPE_8BPC;
3716                                 break;
3717                         case 10:
3718                                 temp |= PIPE_10BPC;
3719                                 break;
3720                         case 6:
3721                                 temp |= PIPE_6BPC;
3722                                 break;
3723                         case 12:
3724                                 temp |= PIPE_12BPC;
3725                                 break;
3726                         }
3727                 } else
3728                         temp |= PIPE_8BPC;
3729                 I915_WRITE(pipeconf_reg, temp);
3730                 I915_READ(pipeconf_reg);
3731
3732                 switch (temp & PIPE_BPC_MASK) {
3733                 case PIPE_8BPC:
3734                         bpp = 24;
3735                         break;
3736                 case PIPE_10BPC:
3737                         bpp = 30;
3738                         break;
3739                 case PIPE_6BPC:
3740                         bpp = 18;
3741                         break;
3742                 case PIPE_12BPC:
3743                         bpp = 36;
3744                         break;
3745                 default:
3746                         DRM_ERROR("unknown pipe bpc value\n");
3747                         bpp = 24;
3748                 }
3749
3750                 if (!lane) {
3751                         /*
3752                          * Account for spread spectrum to avoid
3753                          * oversubscribing the link. Max center spread
3754                          * is 2.5%; use 5% for safety's sake.
3755                          */
3756                         u32 bps = target_clock * bpp * 21 / 20;
3757                         lane = bps / (link_bw * 8) + 1;
3758                 }
3759
3760                 intel_crtc->fdi_lanes = lane;
3761
3762                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3763         }
3764
3765         /* Ironlake: try to setup display ref clock before DPLL
3766          * enabling. This is only under driver's control after
3767          * PCH B stepping, previous chipset stepping should be
3768          * ignoring this setting.
3769          */
3770         if (HAS_PCH_SPLIT(dev)) {
3771                 temp = I915_READ(PCH_DREF_CONTROL);
3772                 /* Always enable nonspread source */
3773                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3774                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3775                 I915_WRITE(PCH_DREF_CONTROL, temp);
3776                 POSTING_READ(PCH_DREF_CONTROL);
3777
3778                 temp &= ~DREF_SSC_SOURCE_MASK;
3779                 temp |= DREF_SSC_SOURCE_ENABLE;
3780                 I915_WRITE(PCH_DREF_CONTROL, temp);
3781                 POSTING_READ(PCH_DREF_CONTROL);
3782
3783                 udelay(200);
3784
3785                 if (is_edp) {
3786                         if (dev_priv->lvds_use_ssc) {
3787                                 temp |= DREF_SSC1_ENABLE;
3788                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3789                                 POSTING_READ(PCH_DREF_CONTROL);
3790
3791                                 udelay(200);
3792
3793                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3794                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3795                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3796                                 POSTING_READ(PCH_DREF_CONTROL);
3797                         } else {
3798                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3799                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3800                                 POSTING_READ(PCH_DREF_CONTROL);
3801                         }
3802                 }
3803         }
3804
3805         if (IS_PINEVIEW(dev)) {
3806                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3807                 if (has_reduced_clock)
3808                         fp2 = (1 << reduced_clock.n) << 16 |
3809                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3810         } else {
3811                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3812                 if (has_reduced_clock)
3813                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3814                                 reduced_clock.m2;
3815         }
3816
3817         if (!HAS_PCH_SPLIT(dev))
3818                 dpll = DPLL_VGA_MODE_DIS;
3819
3820         if (IS_I9XX(dev)) {
3821                 if (is_lvds)
3822                         dpll |= DPLLB_MODE_LVDS;
3823                 else
3824                         dpll |= DPLLB_MODE_DAC_SERIAL;
3825                 if (is_sdvo) {
3826                         dpll |= DPLL_DVO_HIGH_SPEED;
3827                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3828                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3829                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3830                         else if (HAS_PCH_SPLIT(dev))
3831                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3832                 }
3833                 if (is_dp)
3834                         dpll |= DPLL_DVO_HIGH_SPEED;
3835
3836                 /* compute bitmask from p1 value */
3837                 if (IS_PINEVIEW(dev))
3838                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3839                 else {
3840                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3841                         /* also FPA1 */
3842                         if (HAS_PCH_SPLIT(dev))
3843                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3844                         if (IS_G4X(dev) && has_reduced_clock)
3845                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3846                 }
3847                 switch (clock.p2) {
3848                 case 5:
3849                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3850                         break;
3851                 case 7:
3852                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3853                         break;
3854                 case 10:
3855                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3856                         break;
3857                 case 14:
3858                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3859                         break;
3860                 }
3861                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3862                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3863         } else {
3864                 if (is_lvds) {
3865                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3866                 } else {
3867                         if (clock.p1 == 2)
3868                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3869                         else
3870                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3871                         if (clock.p2 == 4)
3872                                 dpll |= PLL_P2_DIVIDE_BY_4;
3873                 }
3874         }
3875
3876         if (is_sdvo && is_tv)
3877                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3878         else if (is_tv)
3879                 /* XXX: just matching BIOS for now */
3880                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3881                 dpll |= 3;
3882         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3883                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3884         else
3885                 dpll |= PLL_REF_INPUT_DREFCLK;
3886
3887         /* setup pipeconf */
3888         pipeconf = I915_READ(pipeconf_reg);
3889
3890         /* Set up the display plane register */
3891         dspcntr = DISPPLANE_GAMMA_ENABLE;
3892
3893         /* Ironlake's plane is forced to pipe, bit 24 is to
3894            enable color space conversion */
3895         if (!HAS_PCH_SPLIT(dev)) {
3896                 if (pipe == 0)
3897                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3898                 else
3899                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3900         }
3901
3902         if (pipe == 0 && !IS_I965G(dev)) {
3903                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3904                  * core speed.
3905                  *
3906                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3907                  * pipe == 0 check?
3908                  */
3909                 if (mode->clock >
3910                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3911                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3912                 else
3913                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3914         }
3915
3916         dspcntr |= DISPLAY_PLANE_ENABLE;
3917         pipeconf |= PIPEACONF_ENABLE;
3918         dpll |= DPLL_VCO_ENABLE;
3919
3920
3921         /* Disable the panel fitter if it was on our pipe */
3922         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3923                 I915_WRITE(PFIT_CONTROL, 0);
3924
3925         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3926         drm_mode_debug_printmodeline(mode);
3927
3928         /* assign to Ironlake registers */
3929         if (HAS_PCH_SPLIT(dev)) {
3930                 fp_reg = pch_fp_reg;
3931                 dpll_reg = pch_dpll_reg;
3932         }
3933
3934         if (!is_edp) {
3935                 I915_WRITE(fp_reg, fp);
3936                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3937                 I915_READ(dpll_reg);
3938                 udelay(150);
3939         }
3940
3941         /* enable transcoder DPLL */
3942         if (HAS_PCH_CPT(dev)) {
3943                 temp = I915_READ(PCH_DPLL_SEL);
3944                 if (trans_dpll_sel == 0)
3945                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3946                 else
3947                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3948                 I915_WRITE(PCH_DPLL_SEL, temp);
3949                 I915_READ(PCH_DPLL_SEL);
3950                 udelay(150);
3951         }
3952
3953         if (HAS_PCH_SPLIT(dev)) {
3954                 pipeconf &= ~PIPE_ENABLE_DITHER;
3955                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3956         }
3957
3958         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3959          * This is an exception to the general rule that mode_set doesn't turn
3960          * things on.
3961          */
3962         if (is_lvds) {
3963                 u32 lvds;
3964
3965                 if (HAS_PCH_SPLIT(dev))
3966                         lvds_reg = PCH_LVDS;
3967
3968                 lvds = I915_READ(lvds_reg);
3969                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3970                 if (pipe == 1) {
3971                         if (HAS_PCH_CPT(dev))
3972                                 lvds |= PORT_TRANS_B_SEL_CPT;
3973                         else
3974                                 lvds |= LVDS_PIPEB_SELECT;
3975                 } else {
3976                         if (HAS_PCH_CPT(dev))
3977                                 lvds &= ~PORT_TRANS_SEL_MASK;
3978                         else
3979                                 lvds &= ~LVDS_PIPEB_SELECT;
3980                 }
3981                 /* set the corresponsding LVDS_BORDER bit */
3982                 lvds |= dev_priv->lvds_border_bits;
3983                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3984                  * set the DPLLs for dual-channel mode or not.
3985                  */
3986                 if (clock.p2 == 7)
3987                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3988                 else
3989                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3990
3991                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3992                  * appropriately here, but we need to look more thoroughly into how
3993                  * panels behave in the two modes.
3994                  */
3995                 /* set the dithering flag */
3996                 if (IS_I965G(dev)) {
3997                         if (dev_priv->lvds_dither) {
3998                                 if (HAS_PCH_SPLIT(dev)) {
3999                                         pipeconf |= PIPE_ENABLE_DITHER;
4000                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
4001                                 } else
4002                                         lvds |= LVDS_ENABLE_DITHER;
4003                         } else {
4004                                 if (!HAS_PCH_SPLIT(dev)) {
4005                                         lvds &= ~LVDS_ENABLE_DITHER;
4006                                 }
4007                         }
4008                 }
4009                 I915_WRITE(lvds_reg, lvds);
4010                 I915_READ(lvds_reg);
4011         }
4012         if (is_dp)
4013                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4014         else if (HAS_PCH_SPLIT(dev)) {
4015                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4016                 if (pipe == 0) {
4017                         I915_WRITE(TRANSA_DATA_M1, 0);
4018                         I915_WRITE(TRANSA_DATA_N1, 0);
4019                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4020                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4021                 } else {
4022                         I915_WRITE(TRANSB_DATA_M1, 0);
4023                         I915_WRITE(TRANSB_DATA_N1, 0);
4024                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4025                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4026                 }
4027         }
4028
4029         if (!is_edp) {
4030                 I915_WRITE(fp_reg, fp);
4031                 I915_WRITE(dpll_reg, dpll);
4032                 I915_READ(dpll_reg);
4033                 /* Wait for the clocks to stabilize. */
4034                 udelay(150);
4035
4036                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4037                         if (is_sdvo) {
4038                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4039                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4040                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4041                         } else
4042                                 I915_WRITE(dpll_md_reg, 0);
4043                 } else {
4044                         /* write it again -- the BIOS does, after all */
4045                         I915_WRITE(dpll_reg, dpll);
4046                 }
4047                 I915_READ(dpll_reg);
4048                 /* Wait for the clocks to stabilize. */
4049                 udelay(150);
4050         }
4051
4052         if (is_lvds && has_reduced_clock && i915_powersave) {
4053                 I915_WRITE(fp_reg + 4, fp2);
4054                 intel_crtc->lowfreq_avail = true;
4055                 if (HAS_PIPE_CXSR(dev)) {
4056                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4057                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4058                 }
4059         } else {
4060                 I915_WRITE(fp_reg + 4, fp);
4061                 intel_crtc->lowfreq_avail = false;
4062                 if (HAS_PIPE_CXSR(dev)) {
4063                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4064                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4065                 }
4066         }
4067
4068         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4069                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4070                 /* the chip adds 2 halflines automatically */
4071                 adjusted_mode->crtc_vdisplay -= 1;
4072                 adjusted_mode->crtc_vtotal -= 1;
4073                 adjusted_mode->crtc_vblank_start -= 1;
4074                 adjusted_mode->crtc_vblank_end -= 1;
4075                 adjusted_mode->crtc_vsync_end -= 1;
4076                 adjusted_mode->crtc_vsync_start -= 1;
4077         } else
4078                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4079
4080         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4081                    ((adjusted_mode->crtc_htotal - 1) << 16));
4082         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4083                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4084         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4085                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4086         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4087                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4088         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4089                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4090         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4091                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4092         /* pipesrc and dspsize control the size that is scaled from, which should
4093          * always be the user's requested size.
4094          */
4095         if (!HAS_PCH_SPLIT(dev)) {
4096                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4097                                 (mode->hdisplay - 1));
4098                 I915_WRITE(dsppos_reg, 0);
4099         }
4100         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4101
4102         if (HAS_PCH_SPLIT(dev)) {
4103                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4104                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4105                 I915_WRITE(link_m1_reg, m_n.link_m);
4106                 I915_WRITE(link_n1_reg, m_n.link_n);
4107
4108                 if (is_edp) {
4109                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4110                 } else {
4111                         /* enable FDI RX PLL too */
4112                         temp = I915_READ(fdi_rx_reg);
4113                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4114                         I915_READ(fdi_rx_reg);
4115                         udelay(200);
4116
4117                         /* enable FDI TX PLL too */
4118                         temp = I915_READ(fdi_tx_reg);
4119                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4120                         I915_READ(fdi_tx_reg);
4121
4122                         /* enable FDI RX PCDCLK */
4123                         temp = I915_READ(fdi_rx_reg);
4124                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4125                         I915_READ(fdi_rx_reg);
4126                         udelay(200);
4127                 }
4128         }
4129
4130         I915_WRITE(pipeconf_reg, pipeconf);
4131         I915_READ(pipeconf_reg);
4132
4133         intel_wait_for_vblank(dev, pipe);
4134
4135         if (IS_IRONLAKE(dev)) {
4136                 /* enable address swizzle for tiling buffer */
4137                 temp = I915_READ(DISP_ARB_CTL);
4138                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4139         }
4140
4141         I915_WRITE(dspcntr_reg, dspcntr);
4142
4143         /* Flush the plane changes */
4144         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4145
4146         intel_update_watermarks(dev);
4147
4148         drm_vblank_post_modeset(dev, pipe);
4149
4150         return ret;
4151 }
4152
4153 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4154 void intel_crtc_load_lut(struct drm_crtc *crtc)
4155 {
4156         struct drm_device *dev = crtc->dev;
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4160         int i;
4161
4162         /* The clocks have to be on to load the palette. */
4163         if (!crtc->enabled)
4164                 return;
4165
4166         /* use legacy palette for Ironlake */
4167         if (HAS_PCH_SPLIT(dev))
4168                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4169                                                    LGC_PALETTE_B;
4170
4171         for (i = 0; i < 256; i++) {
4172                 I915_WRITE(palreg + 4 * i,
4173                            (intel_crtc->lut_r[i] << 16) |
4174                            (intel_crtc->lut_g[i] << 8) |
4175                            intel_crtc->lut_b[i]);
4176         }
4177 }
4178
4179 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4180 {
4181         struct drm_device *dev = crtc->dev;
4182         struct drm_i915_private *dev_priv = dev->dev_private;
4183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184         bool visible = base != 0;
4185         u32 cntl;
4186
4187         if (intel_crtc->cursor_visible == visible)
4188                 return;
4189
4190         cntl = I915_READ(CURACNTR);
4191         if (visible) {
4192                 /* On these chipsets we can only modify the base whilst
4193                  * the cursor is disabled.
4194                  */
4195                 I915_WRITE(CURABASE, base);
4196
4197                 cntl &= ~(CURSOR_FORMAT_MASK);
4198                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4199                 cntl |= CURSOR_ENABLE |
4200                         CURSOR_GAMMA_ENABLE |
4201                         CURSOR_FORMAT_ARGB;
4202         } else
4203                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4204         I915_WRITE(CURACNTR, cntl);
4205
4206         intel_crtc->cursor_visible = visible;
4207 }
4208
4209 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4210 {
4211         struct drm_device *dev = crtc->dev;
4212         struct drm_i915_private *dev_priv = dev->dev_private;
4213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214         int pipe = intel_crtc->pipe;
4215         bool visible = base != 0;
4216
4217         if (intel_crtc->cursor_visible != visible) {
4218                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4219                 if (base) {
4220                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4221                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4222                         cntl |= pipe << 28; /* Connect to correct pipe */
4223                 } else {
4224                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4225                         cntl |= CURSOR_MODE_DISABLE;
4226                 }
4227                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4228
4229                 intel_crtc->cursor_visible = visible;
4230         }
4231         /* and commit changes on next vblank */
4232         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4233 }
4234
4235 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4236 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4237 {
4238         struct drm_device *dev = crtc->dev;
4239         struct drm_i915_private *dev_priv = dev->dev_private;
4240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241         int pipe = intel_crtc->pipe;
4242         int x = intel_crtc->cursor_x;
4243         int y = intel_crtc->cursor_y;
4244         u32 base, pos;
4245         bool visible;
4246
4247         pos = 0;
4248
4249         if (intel_crtc->cursor_on && crtc->fb) {
4250                 base = intel_crtc->cursor_addr;
4251                 if (x > (int) crtc->fb->width)
4252                         base = 0;
4253
4254                 if (y > (int) crtc->fb->height)
4255                         base = 0;
4256         } else
4257                 base = 0;
4258
4259         if (x < 0) {
4260                 if (x + intel_crtc->cursor_width < 0)
4261                         base = 0;
4262
4263                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4264                 x = -x;
4265         }
4266         pos |= x << CURSOR_X_SHIFT;
4267
4268         if (y < 0) {
4269                 if (y + intel_crtc->cursor_height < 0)
4270                         base = 0;
4271
4272                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4273                 y = -y;
4274         }
4275         pos |= y << CURSOR_Y_SHIFT;
4276
4277         visible = base != 0;
4278         if (!visible && !intel_crtc->cursor_visible)
4279                 return;
4280
4281         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4282         if (IS_845G(dev) || IS_I865G(dev))
4283                 i845_update_cursor(crtc, base);
4284         else
4285                 i9xx_update_cursor(crtc, base);
4286
4287         if (visible)
4288                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4289 }
4290
4291 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4292                                  struct drm_file *file_priv,
4293                                  uint32_t handle,
4294                                  uint32_t width, uint32_t height)
4295 {
4296         struct drm_device *dev = crtc->dev;
4297         struct drm_i915_private *dev_priv = dev->dev_private;
4298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299         struct drm_gem_object *bo;
4300         struct drm_i915_gem_object *obj_priv;
4301         uint32_t addr;
4302         int ret;
4303
4304         DRM_DEBUG_KMS("\n");
4305
4306         /* if we want to turn off the cursor ignore width and height */
4307         if (!handle) {
4308                 DRM_DEBUG_KMS("cursor off\n");
4309                 addr = 0;
4310                 bo = NULL;
4311                 mutex_lock(&dev->struct_mutex);
4312                 goto finish;
4313         }
4314
4315         /* Currently we only support 64x64 cursors */
4316         if (width != 64 || height != 64) {
4317                 DRM_ERROR("we currently only support 64x64 cursors\n");
4318                 return -EINVAL;
4319         }
4320
4321         bo = drm_gem_object_lookup(dev, file_priv, handle);
4322         if (!bo)
4323                 return -ENOENT;
4324
4325         obj_priv = to_intel_bo(bo);
4326
4327         if (bo->size < width * height * 4) {
4328                 DRM_ERROR("buffer is to small\n");
4329                 ret = -ENOMEM;
4330                 goto fail;
4331         }
4332
4333         /* we only need to pin inside GTT if cursor is non-phy */
4334         mutex_lock(&dev->struct_mutex);
4335         if (!dev_priv->info->cursor_needs_physical) {
4336                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4337                 if (ret) {
4338                         DRM_ERROR("failed to pin cursor bo\n");
4339                         goto fail_locked;
4340                 }
4341
4342                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4343                 if (ret) {
4344                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4345                         goto fail_unpin;
4346                 }
4347
4348                 addr = obj_priv->gtt_offset;
4349         } else {
4350                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4351                 ret = i915_gem_attach_phys_object(dev, bo,
4352                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4353                                                   align);
4354                 if (ret) {
4355                         DRM_ERROR("failed to attach phys object\n");
4356                         goto fail_locked;
4357                 }
4358                 addr = obj_priv->phys_obj->handle->busaddr;
4359         }
4360
4361         if (!IS_I9XX(dev))
4362                 I915_WRITE(CURSIZE, (height << 12) | width);
4363
4364  finish:
4365         if (intel_crtc->cursor_bo) {
4366                 if (dev_priv->info->cursor_needs_physical) {
4367                         if (intel_crtc->cursor_bo != bo)
4368                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4369                 } else
4370                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4371                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4372         }
4373
4374         mutex_unlock(&dev->struct_mutex);
4375
4376         intel_crtc->cursor_addr = addr;
4377         intel_crtc->cursor_bo = bo;
4378         intel_crtc->cursor_width = width;
4379         intel_crtc->cursor_height = height;
4380
4381         intel_crtc_update_cursor(crtc);
4382
4383         return 0;
4384 fail_unpin:
4385         i915_gem_object_unpin(bo);
4386 fail_locked:
4387         mutex_unlock(&dev->struct_mutex);
4388 fail:
4389         drm_gem_object_unreference_unlocked(bo);
4390         return ret;
4391 }
4392
4393 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4394 {
4395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396
4397         intel_crtc->cursor_x = x;
4398         intel_crtc->cursor_y = y;
4399
4400         intel_crtc_update_cursor(crtc);
4401
4402         return 0;
4403 }
4404
4405 /** Sets the color ramps on behalf of RandR */
4406 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4407                                  u16 blue, int regno)
4408 {
4409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4410
4411         intel_crtc->lut_r[regno] = red >> 8;
4412         intel_crtc->lut_g[regno] = green >> 8;
4413         intel_crtc->lut_b[regno] = blue >> 8;
4414 }
4415
4416 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4417                              u16 *blue, int regno)
4418 {
4419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4420
4421         *red = intel_crtc->lut_r[regno] << 8;
4422         *green = intel_crtc->lut_g[regno] << 8;
4423         *blue = intel_crtc->lut_b[regno] << 8;
4424 }
4425
4426 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4427                                  u16 *blue, uint32_t size)
4428 {
4429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4430         int i;
4431
4432         if (size != 256)
4433                 return;
4434
4435         for (i = 0; i < 256; i++) {
4436                 intel_crtc->lut_r[i] = red[i] >> 8;
4437                 intel_crtc->lut_g[i] = green[i] >> 8;
4438                 intel_crtc->lut_b[i] = blue[i] >> 8;
4439         }
4440
4441         intel_crtc_load_lut(crtc);
4442 }
4443
4444 /**
4445  * Get a pipe with a simple mode set on it for doing load-based monitor
4446  * detection.
4447  *
4448  * It will be up to the load-detect code to adjust the pipe as appropriate for
4449  * its requirements.  The pipe will be connected to no other encoders.
4450  *
4451  * Currently this code will only succeed if there is a pipe with no encoders
4452  * configured for it.  In the future, it could choose to temporarily disable
4453  * some outputs to free up a pipe for its use.
4454  *
4455  * \return crtc, or NULL if no pipes are available.
4456  */
4457
4458 /* VESA 640x480x72Hz mode to set on the pipe */
4459 static struct drm_display_mode load_detect_mode = {
4460         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4461                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4462 };
4463
4464 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4465                                             struct drm_connector *connector,
4466                                             struct drm_display_mode *mode,
4467                                             int *dpms_mode)
4468 {
4469         struct intel_crtc *intel_crtc;
4470         struct drm_crtc *possible_crtc;
4471         struct drm_crtc *supported_crtc =NULL;
4472         struct drm_encoder *encoder = &intel_encoder->enc;
4473         struct drm_crtc *crtc = NULL;
4474         struct drm_device *dev = encoder->dev;
4475         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4476         struct drm_crtc_helper_funcs *crtc_funcs;
4477         int i = -1;
4478
4479         /*
4480          * Algorithm gets a little messy:
4481          *   - if the connector already has an assigned crtc, use it (but make
4482          *     sure it's on first)
4483          *   - try to find the first unused crtc that can drive this connector,
4484          *     and use that if we find one
4485          *   - if there are no unused crtcs available, try to use the first
4486          *     one we found that supports the connector
4487          */
4488
4489         /* See if we already have a CRTC for this connector */
4490         if (encoder->crtc) {
4491                 crtc = encoder->crtc;
4492                 /* Make sure the crtc and connector are running */
4493                 intel_crtc = to_intel_crtc(crtc);
4494                 *dpms_mode = intel_crtc->dpms_mode;
4495                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4496                         crtc_funcs = crtc->helper_private;
4497                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4498                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4499                 }
4500                 return crtc;
4501         }
4502
4503         /* Find an unused one (if possible) */
4504         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4505                 i++;
4506                 if (!(encoder->possible_crtcs & (1 << i)))
4507                         continue;
4508                 if (!possible_crtc->enabled) {
4509                         crtc = possible_crtc;
4510                         break;
4511                 }
4512                 if (!supported_crtc)
4513                         supported_crtc = possible_crtc;
4514         }
4515
4516         /*
4517          * If we didn't find an unused CRTC, don't use any.
4518          */
4519         if (!crtc) {
4520                 return NULL;
4521         }
4522
4523         encoder->crtc = crtc;
4524         connector->encoder = encoder;
4525         intel_encoder->load_detect_temp = true;
4526
4527         intel_crtc = to_intel_crtc(crtc);
4528         *dpms_mode = intel_crtc->dpms_mode;
4529
4530         if (!crtc->enabled) {
4531                 if (!mode)
4532                         mode = &load_detect_mode;
4533                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4534         } else {
4535                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4536                         crtc_funcs = crtc->helper_private;
4537                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4538                 }
4539
4540                 /* Add this connector to the crtc */
4541                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4542                 encoder_funcs->commit(encoder);
4543         }
4544         /* let the connector get through one full cycle before testing */
4545         intel_wait_for_vblank(dev, intel_crtc->pipe);
4546
4547         return crtc;
4548 }
4549
4550 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4551                                     struct drm_connector *connector, int dpms_mode)
4552 {
4553         struct drm_encoder *encoder = &intel_encoder->enc;
4554         struct drm_device *dev = encoder->dev;
4555         struct drm_crtc *crtc = encoder->crtc;
4556         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4557         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4558
4559         if (intel_encoder->load_detect_temp) {
4560                 encoder->crtc = NULL;
4561                 connector->encoder = NULL;
4562                 intel_encoder->load_detect_temp = false;
4563                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4564                 drm_helper_disable_unused_functions(dev);
4565         }
4566
4567         /* Switch crtc and encoder back off if necessary */
4568         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4569                 if (encoder->crtc == crtc)
4570                         encoder_funcs->dpms(encoder, dpms_mode);
4571                 crtc_funcs->dpms(crtc, dpms_mode);
4572         }
4573 }
4574
4575 /* Returns the clock of the currently programmed mode of the given pipe. */
4576 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4577 {
4578         struct drm_i915_private *dev_priv = dev->dev_private;
4579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580         int pipe = intel_crtc->pipe;
4581         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4582         u32 fp;
4583         intel_clock_t clock;
4584
4585         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4586                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4587         else
4588                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4589
4590         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4591         if (IS_PINEVIEW(dev)) {
4592                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4593                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4594         } else {
4595                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4596                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4597         }
4598
4599         if (IS_I9XX(dev)) {
4600                 if (IS_PINEVIEW(dev))
4601                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4602                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4603                 else
4604                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4605                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4606
4607                 switch (dpll & DPLL_MODE_MASK) {
4608                 case DPLLB_MODE_DAC_SERIAL:
4609                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4610                                 5 : 10;
4611                         break;
4612                 case DPLLB_MODE_LVDS:
4613                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4614                                 7 : 14;
4615                         break;
4616                 default:
4617                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4618                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4619                         return 0;
4620                 }
4621
4622                 /* XXX: Handle the 100Mhz refclk */
4623                 intel_clock(dev, 96000, &clock);
4624         } else {
4625                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4626
4627                 if (is_lvds) {
4628                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4629                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4630                         clock.p2 = 14;
4631
4632                         if ((dpll & PLL_REF_INPUT_MASK) ==
4633                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4634                                 /* XXX: might not be 66MHz */
4635                                 intel_clock(dev, 66000, &clock);
4636                         } else
4637                                 intel_clock(dev, 48000, &clock);
4638                 } else {
4639                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4640                                 clock.p1 = 2;
4641                         else {
4642                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4643                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4644                         }
4645                         if (dpll & PLL_P2_DIVIDE_BY_4)
4646                                 clock.p2 = 4;
4647                         else
4648                                 clock.p2 = 2;
4649
4650                         intel_clock(dev, 48000, &clock);
4651                 }
4652         }
4653
4654         /* XXX: It would be nice to validate the clocks, but we can't reuse
4655          * i830PllIsValid() because it relies on the xf86_config connector
4656          * configuration being accurate, which it isn't necessarily.
4657          */
4658
4659         return clock.dot;
4660 }
4661
4662 /** Returns the currently programmed mode of the given pipe. */
4663 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4664                                              struct drm_crtc *crtc)
4665 {
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668         int pipe = intel_crtc->pipe;
4669         struct drm_display_mode *mode;
4670         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4671         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4672         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4673         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4674
4675         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4676         if (!mode)
4677                 return NULL;
4678
4679         mode->clock = intel_crtc_clock_get(dev, crtc);
4680         mode->hdisplay = (htot & 0xffff) + 1;
4681         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4682         mode->hsync_start = (hsync & 0xffff) + 1;
4683         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4684         mode->vdisplay = (vtot & 0xffff) + 1;
4685         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4686         mode->vsync_start = (vsync & 0xffff) + 1;
4687         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4688
4689         drm_mode_set_name(mode);
4690         drm_mode_set_crtcinfo(mode, 0);
4691
4692         return mode;
4693 }
4694
4695 #define GPU_IDLE_TIMEOUT 500 /* ms */
4696
4697 /* When this timer fires, we've been idle for awhile */
4698 static void intel_gpu_idle_timer(unsigned long arg)
4699 {
4700         struct drm_device *dev = (struct drm_device *)arg;
4701         drm_i915_private_t *dev_priv = dev->dev_private;
4702
4703         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4704
4705         dev_priv->busy = false;
4706
4707         queue_work(dev_priv->wq, &dev_priv->idle_work);
4708 }
4709
4710 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4711
4712 static void intel_crtc_idle_timer(unsigned long arg)
4713 {
4714         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4715         struct drm_crtc *crtc = &intel_crtc->base;
4716         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4717
4718         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4719
4720         intel_crtc->busy = false;
4721
4722         queue_work(dev_priv->wq, &dev_priv->idle_work);
4723 }
4724
4725 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4726 {
4727         struct drm_device *dev = crtc->dev;
4728         drm_i915_private_t *dev_priv = dev->dev_private;
4729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730         int pipe = intel_crtc->pipe;
4731         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4732         int dpll = I915_READ(dpll_reg);
4733
4734         if (HAS_PCH_SPLIT(dev))
4735                 return;
4736
4737         if (!dev_priv->lvds_downclock_avail)
4738                 return;
4739
4740         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4741                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4742
4743                 /* Unlock panel regs */
4744                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4745                            PANEL_UNLOCK_REGS);
4746
4747                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4748                 I915_WRITE(dpll_reg, dpll);
4749                 dpll = I915_READ(dpll_reg);
4750                 intel_wait_for_vblank(dev, pipe);
4751                 dpll = I915_READ(dpll_reg);
4752                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4753                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4754
4755                 /* ...and lock them again */
4756                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4757         }
4758
4759         /* Schedule downclock */
4760         if (schedule)
4761                 mod_timer(&intel_crtc->idle_timer, jiffies +
4762                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4763 }
4764
4765 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4766 {
4767         struct drm_device *dev = crtc->dev;
4768         drm_i915_private_t *dev_priv = dev->dev_private;
4769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4770         int pipe = intel_crtc->pipe;
4771         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4772         int dpll = I915_READ(dpll_reg);
4773
4774         if (HAS_PCH_SPLIT(dev))
4775                 return;
4776
4777         if (!dev_priv->lvds_downclock_avail)
4778                 return;
4779
4780         /*
4781          * Since this is called by a timer, we should never get here in
4782          * the manual case.
4783          */
4784         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4785                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4786
4787                 /* Unlock panel regs */
4788                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4789                            PANEL_UNLOCK_REGS);
4790
4791                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4792                 I915_WRITE(dpll_reg, dpll);
4793                 dpll = I915_READ(dpll_reg);
4794                 intel_wait_for_vblank(dev, pipe);
4795                 dpll = I915_READ(dpll_reg);
4796                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4797                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4798
4799                 /* ...and lock them again */
4800                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4801         }
4802
4803 }
4804
4805 /**
4806  * intel_idle_update - adjust clocks for idleness
4807  * @work: work struct
4808  *
4809  * Either the GPU or display (or both) went idle.  Check the busy status
4810  * here and adjust the CRTC and GPU clocks as necessary.
4811  */
4812 static void intel_idle_update(struct work_struct *work)
4813 {
4814         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4815                                                     idle_work);
4816         struct drm_device *dev = dev_priv->dev;
4817         struct drm_crtc *crtc;
4818         struct intel_crtc *intel_crtc;
4819         int enabled = 0;
4820
4821         if (!i915_powersave)
4822                 return;
4823
4824         mutex_lock(&dev->struct_mutex);
4825
4826         i915_update_gfx_val(dev_priv);
4827
4828         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4829                 /* Skip inactive CRTCs */
4830                 if (!crtc->fb)
4831                         continue;
4832
4833                 enabled++;
4834                 intel_crtc = to_intel_crtc(crtc);
4835                 if (!intel_crtc->busy)
4836                         intel_decrease_pllclock(crtc);
4837         }
4838
4839         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4840                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4841                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4842         }
4843
4844         mutex_unlock(&dev->struct_mutex);
4845 }
4846
4847 /**
4848  * intel_mark_busy - mark the GPU and possibly the display busy
4849  * @dev: drm device
4850  * @obj: object we're operating on
4851  *
4852  * Callers can use this function to indicate that the GPU is busy processing
4853  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4854  * buffer), we'll also mark the display as busy, so we know to increase its
4855  * clock frequency.
4856  */
4857 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4858 {
4859         drm_i915_private_t *dev_priv = dev->dev_private;
4860         struct drm_crtc *crtc = NULL;
4861         struct intel_framebuffer *intel_fb;
4862         struct intel_crtc *intel_crtc;
4863
4864         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4865                 return;
4866
4867         if (!dev_priv->busy) {
4868                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4869                         u32 fw_blc_self;
4870
4871                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4872                         fw_blc_self = I915_READ(FW_BLC_SELF);
4873                         fw_blc_self &= ~FW_BLC_SELF_EN;
4874                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4875                 }
4876                 dev_priv->busy = true;
4877         } else
4878                 mod_timer(&dev_priv->idle_timer, jiffies +
4879                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4880
4881         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4882                 if (!crtc->fb)
4883                         continue;
4884
4885                 intel_crtc = to_intel_crtc(crtc);
4886                 intel_fb = to_intel_framebuffer(crtc->fb);
4887                 if (intel_fb->obj == obj) {
4888                         if (!intel_crtc->busy) {
4889                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4890                                         u32 fw_blc_self;
4891
4892                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4893                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4894                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4895                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4896                                 }
4897                                 /* Non-busy -> busy, upclock */
4898                                 intel_increase_pllclock(crtc, true);
4899                                 intel_crtc->busy = true;
4900                         } else {
4901                                 /* Busy -> busy, put off timer */
4902                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4903                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4904                         }
4905                 }
4906         }
4907 }
4908
4909 static void intel_crtc_destroy(struct drm_crtc *crtc)
4910 {
4911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4912
4913         drm_crtc_cleanup(crtc);
4914         kfree(intel_crtc);
4915 }
4916
4917 struct intel_unpin_work {
4918         struct work_struct work;
4919         struct drm_device *dev;
4920         struct drm_gem_object *old_fb_obj;
4921         struct drm_gem_object *pending_flip_obj;
4922         struct drm_pending_vblank_event *event;
4923         int pending;
4924 };
4925
4926 static void intel_unpin_work_fn(struct work_struct *__work)
4927 {
4928         struct intel_unpin_work *work =
4929                 container_of(__work, struct intel_unpin_work, work);
4930
4931         mutex_lock(&work->dev->struct_mutex);
4932         i915_gem_object_unpin(work->old_fb_obj);
4933         drm_gem_object_unreference(work->pending_flip_obj);
4934         drm_gem_object_unreference(work->old_fb_obj);
4935         mutex_unlock(&work->dev->struct_mutex);
4936         kfree(work);
4937 }
4938
4939 static void do_intel_finish_page_flip(struct drm_device *dev,
4940                                       struct drm_crtc *crtc)
4941 {
4942         drm_i915_private_t *dev_priv = dev->dev_private;
4943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4944         struct intel_unpin_work *work;
4945         struct drm_i915_gem_object *obj_priv;
4946         struct drm_pending_vblank_event *e;
4947         struct timeval now;
4948         unsigned long flags;
4949
4950         /* Ignore early vblank irqs */
4951         if (intel_crtc == NULL)
4952                 return;
4953
4954         spin_lock_irqsave(&dev->event_lock, flags);
4955         work = intel_crtc->unpin_work;
4956         if (work == NULL || !work->pending) {
4957                 spin_unlock_irqrestore(&dev->event_lock, flags);
4958                 return;
4959         }
4960
4961         intel_crtc->unpin_work = NULL;
4962         drm_vblank_put(dev, intel_crtc->pipe);
4963
4964         if (work->event) {
4965                 e = work->event;
4966                 do_gettimeofday(&now);
4967                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4968                 e->event.tv_sec = now.tv_sec;
4969                 e->event.tv_usec = now.tv_usec;
4970                 list_add_tail(&e->base.link,
4971                               &e->base.file_priv->event_list);
4972                 wake_up_interruptible(&e->base.file_priv->event_wait);
4973         }
4974
4975         spin_unlock_irqrestore(&dev->event_lock, flags);
4976
4977         obj_priv = to_intel_bo(work->pending_flip_obj);
4978
4979         /* Initial scanout buffer will have a 0 pending flip count */
4980         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4981             atomic_dec_and_test(&obj_priv->pending_flip))
4982                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4983         schedule_work(&work->work);
4984
4985         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4986 }
4987
4988 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4989 {
4990         drm_i915_private_t *dev_priv = dev->dev_private;
4991         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4992
4993         do_intel_finish_page_flip(dev, crtc);
4994 }
4995
4996 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4997 {
4998         drm_i915_private_t *dev_priv = dev->dev_private;
4999         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5000
5001         do_intel_finish_page_flip(dev, crtc);
5002 }
5003
5004 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5005 {
5006         drm_i915_private_t *dev_priv = dev->dev_private;
5007         struct intel_crtc *intel_crtc =
5008                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5009         unsigned long flags;
5010
5011         spin_lock_irqsave(&dev->event_lock, flags);
5012         if (intel_crtc->unpin_work) {
5013                 intel_crtc->unpin_work->pending = 1;
5014         } else {
5015                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5016         }
5017         spin_unlock_irqrestore(&dev->event_lock, flags);
5018 }
5019
5020 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5021                                 struct drm_framebuffer *fb,
5022                                 struct drm_pending_vblank_event *event)
5023 {
5024         struct drm_device *dev = crtc->dev;
5025         struct drm_i915_private *dev_priv = dev->dev_private;
5026         struct intel_framebuffer *intel_fb;
5027         struct drm_i915_gem_object *obj_priv;
5028         struct drm_gem_object *obj;
5029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030         struct intel_unpin_work *work;
5031         unsigned long flags, offset;
5032         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5033         int ret, pipesrc;
5034         u32 flip_mask;
5035
5036         work = kzalloc(sizeof *work, GFP_KERNEL);
5037         if (work == NULL)
5038                 return -ENOMEM;
5039
5040         work->event = event;
5041         work->dev = crtc->dev;
5042         intel_fb = to_intel_framebuffer(crtc->fb);
5043         work->old_fb_obj = intel_fb->obj;
5044         INIT_WORK(&work->work, intel_unpin_work_fn);
5045
5046         /* We borrow the event spin lock for protecting unpin_work */
5047         spin_lock_irqsave(&dev->event_lock, flags);
5048         if (intel_crtc->unpin_work) {
5049                 spin_unlock_irqrestore(&dev->event_lock, flags);
5050                 kfree(work);
5051
5052                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5053                 return -EBUSY;
5054         }
5055         intel_crtc->unpin_work = work;
5056         spin_unlock_irqrestore(&dev->event_lock, flags);
5057
5058         intel_fb = to_intel_framebuffer(fb);
5059         obj = intel_fb->obj;
5060
5061         mutex_lock(&dev->struct_mutex);
5062         ret = intel_pin_and_fence_fb_obj(dev, obj);
5063         if (ret)
5064                 goto cleanup_work;
5065
5066         /* Reference the objects for the scheduled work. */
5067         drm_gem_object_reference(work->old_fb_obj);
5068         drm_gem_object_reference(obj);
5069
5070         crtc->fb = fb;
5071         ret = i915_gem_object_flush_write_domain(obj);
5072         if (ret)
5073                 goto cleanup_objs;
5074
5075         ret = drm_vblank_get(dev, intel_crtc->pipe);
5076         if (ret)
5077                 goto cleanup_objs;
5078
5079         obj_priv = to_intel_bo(obj);
5080         atomic_inc(&obj_priv->pending_flip);
5081         work->pending_flip_obj = obj;
5082
5083         if (intel_crtc->plane)
5084                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5085         else
5086                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5087
5088         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5089                 BEGIN_LP_RING(2);
5090                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5091                 OUT_RING(0);
5092                 ADVANCE_LP_RING();
5093         }
5094
5095         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5096         offset = obj_priv->gtt_offset;
5097         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5098
5099         BEGIN_LP_RING(4);
5100         if (IS_I965G(dev)) {
5101                 OUT_RING(MI_DISPLAY_FLIP |
5102                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5103                 OUT_RING(fb->pitch);
5104                 OUT_RING(offset | obj_priv->tiling_mode);
5105                 pipesrc = I915_READ(pipesrc_reg);
5106                 OUT_RING(pipesrc & 0x0fff0fff);
5107         } else if (IS_GEN3(dev)) {
5108                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5109                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5110                 OUT_RING(fb->pitch);
5111                 OUT_RING(offset);
5112                 OUT_RING(MI_NOOP);
5113         } else {
5114                 OUT_RING(MI_DISPLAY_FLIP |
5115                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5116                 OUT_RING(fb->pitch);
5117                 OUT_RING(offset);
5118                 OUT_RING(MI_NOOP);
5119         }
5120         ADVANCE_LP_RING();
5121
5122         mutex_unlock(&dev->struct_mutex);
5123
5124         trace_i915_flip_request(intel_crtc->plane, obj);
5125
5126         return 0;
5127
5128 cleanup_objs:
5129         drm_gem_object_unreference(work->old_fb_obj);
5130         drm_gem_object_unreference(obj);
5131 cleanup_work:
5132         mutex_unlock(&dev->struct_mutex);
5133
5134         spin_lock_irqsave(&dev->event_lock, flags);
5135         intel_crtc->unpin_work = NULL;
5136         spin_unlock_irqrestore(&dev->event_lock, flags);
5137
5138         kfree(work);
5139
5140         return ret;
5141 }
5142
5143 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5144         .dpms = intel_crtc_dpms,
5145         .mode_fixup = intel_crtc_mode_fixup,
5146         .mode_set = intel_crtc_mode_set,
5147         .mode_set_base = intel_pipe_set_base,
5148         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5149         .prepare = intel_crtc_prepare,
5150         .commit = intel_crtc_commit,
5151         .load_lut = intel_crtc_load_lut,
5152 };
5153
5154 static const struct drm_crtc_funcs intel_crtc_funcs = {
5155         .cursor_set = intel_crtc_cursor_set,
5156         .cursor_move = intel_crtc_cursor_move,
5157         .gamma_set = intel_crtc_gamma_set,
5158         .set_config = drm_crtc_helper_set_config,
5159         .destroy = intel_crtc_destroy,
5160         .page_flip = intel_crtc_page_flip,
5161 };
5162
5163
5164 static void intel_crtc_init(struct drm_device *dev, int pipe)
5165 {
5166         drm_i915_private_t *dev_priv = dev->dev_private;
5167         struct intel_crtc *intel_crtc;
5168         int i;
5169
5170         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5171         if (intel_crtc == NULL)
5172                 return;
5173
5174         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5175
5176         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5177         intel_crtc->pipe = pipe;
5178         intel_crtc->plane = pipe;
5179         for (i = 0; i < 256; i++) {
5180                 intel_crtc->lut_r[i] = i;
5181                 intel_crtc->lut_g[i] = i;
5182                 intel_crtc->lut_b[i] = i;
5183         }
5184
5185         /* Swap pipes & planes for FBC on pre-965 */
5186         intel_crtc->pipe = pipe;
5187         intel_crtc->plane = pipe;
5188         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5189                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5190                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5191         }
5192
5193         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5194                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5195         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5196         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5197
5198         intel_crtc->cursor_addr = 0;
5199         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5200         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5201
5202         intel_crtc->busy = false;
5203
5204         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5205                     (unsigned long)intel_crtc);
5206 }
5207
5208 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5209                                 struct drm_file *file_priv)
5210 {
5211         drm_i915_private_t *dev_priv = dev->dev_private;
5212         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5213         struct drm_mode_object *drmmode_obj;
5214         struct intel_crtc *crtc;
5215
5216         if (!dev_priv) {
5217                 DRM_ERROR("called with no initialization\n");
5218                 return -EINVAL;
5219         }
5220
5221         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5222                         DRM_MODE_OBJECT_CRTC);
5223
5224         if (!drmmode_obj) {
5225                 DRM_ERROR("no such CRTC id\n");
5226                 return -EINVAL;
5227         }
5228
5229         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5230         pipe_from_crtc_id->pipe = crtc->pipe;
5231
5232         return 0;
5233 }
5234
5235 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5236 {
5237         struct drm_crtc *crtc = NULL;
5238
5239         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5240                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5241                 if (intel_crtc->pipe == pipe)
5242                         break;
5243         }
5244         return crtc;
5245 }
5246
5247 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5248 {
5249         int index_mask = 0;
5250         struct drm_encoder *encoder;
5251         int entry = 0;
5252
5253         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5254                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5255                 if (type_mask & intel_encoder->clone_mask)
5256                         index_mask |= (1 << entry);
5257                 entry++;
5258         }
5259         return index_mask;
5260 }
5261
5262
5263 static void intel_setup_outputs(struct drm_device *dev)
5264 {
5265         struct drm_i915_private *dev_priv = dev->dev_private;
5266         struct drm_encoder *encoder;
5267         bool dpd_is_edp = false;
5268
5269         if (IS_MOBILE(dev) && !IS_I830(dev))
5270                 intel_lvds_init(dev);
5271
5272         if (HAS_PCH_SPLIT(dev)) {
5273                 dpd_is_edp = intel_dpd_is_edp(dev);
5274
5275                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5276                         intel_dp_init(dev, DP_A);
5277
5278                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5279                         intel_dp_init(dev, PCH_DP_D);
5280         }
5281
5282         intel_crt_init(dev);
5283
5284         if (HAS_PCH_SPLIT(dev)) {
5285                 int found;
5286
5287                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5288                         /* PCH SDVOB multiplex with HDMIB */
5289                         found = intel_sdvo_init(dev, PCH_SDVOB);
5290                         if (!found)
5291                                 intel_hdmi_init(dev, HDMIB);
5292                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5293                                 intel_dp_init(dev, PCH_DP_B);
5294                 }
5295
5296                 if (I915_READ(HDMIC) & PORT_DETECTED)
5297                         intel_hdmi_init(dev, HDMIC);
5298
5299                 if (I915_READ(HDMID) & PORT_DETECTED)
5300                         intel_hdmi_init(dev, HDMID);
5301
5302                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5303                         intel_dp_init(dev, PCH_DP_C);
5304
5305                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5306                         intel_dp_init(dev, PCH_DP_D);
5307
5308         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5309                 bool found = false;
5310
5311                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5312                         DRM_DEBUG_KMS("probing SDVOB\n");
5313                         found = intel_sdvo_init(dev, SDVOB);
5314                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5315                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5316                                 intel_hdmi_init(dev, SDVOB);
5317                         }
5318
5319                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5320                                 DRM_DEBUG_KMS("probing DP_B\n");
5321                                 intel_dp_init(dev, DP_B);
5322                         }
5323                 }
5324
5325                 /* Before G4X SDVOC doesn't have its own detect register */
5326
5327                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5328                         DRM_DEBUG_KMS("probing SDVOC\n");
5329                         found = intel_sdvo_init(dev, SDVOC);
5330                 }
5331
5332                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5333
5334                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5335                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5336                                 intel_hdmi_init(dev, SDVOC);
5337                         }
5338                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5339                                 DRM_DEBUG_KMS("probing DP_C\n");
5340                                 intel_dp_init(dev, DP_C);
5341                         }
5342                 }
5343
5344                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5345                     (I915_READ(DP_D) & DP_DETECTED)) {
5346                         DRM_DEBUG_KMS("probing DP_D\n");
5347                         intel_dp_init(dev, DP_D);
5348                 }
5349         } else if (IS_GEN2(dev))
5350                 intel_dvo_init(dev);
5351
5352         if (SUPPORTS_TV(dev))
5353                 intel_tv_init(dev);
5354
5355         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5356                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5357
5358                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5359                 encoder->possible_clones = intel_encoder_clones(dev,
5360                                                 intel_encoder->clone_mask);
5361         }
5362 }
5363
5364 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5365 {
5366         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5367
5368         drm_framebuffer_cleanup(fb);
5369         drm_gem_object_unreference_unlocked(intel_fb->obj);
5370
5371         kfree(intel_fb);
5372 }
5373
5374 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5375                                                 struct drm_file *file_priv,
5376                                                 unsigned int *handle)
5377 {
5378         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5379         struct drm_gem_object *object = intel_fb->obj;
5380
5381         return drm_gem_handle_create(file_priv, object, handle);
5382 }
5383
5384 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5385         .destroy = intel_user_framebuffer_destroy,
5386         .create_handle = intel_user_framebuffer_create_handle,
5387 };
5388
5389 int intel_framebuffer_init(struct drm_device *dev,
5390                            struct intel_framebuffer *intel_fb,
5391                            struct drm_mode_fb_cmd *mode_cmd,
5392                            struct drm_gem_object *obj)
5393 {
5394         int ret;
5395
5396         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5397         if (ret) {
5398                 DRM_ERROR("framebuffer init failed %d\n", ret);
5399                 return ret;
5400         }
5401
5402         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5403         intel_fb->obj = obj;
5404         return 0;
5405 }
5406
5407 static struct drm_framebuffer *
5408 intel_user_framebuffer_create(struct drm_device *dev,
5409                               struct drm_file *filp,
5410                               struct drm_mode_fb_cmd *mode_cmd)
5411 {
5412         struct drm_gem_object *obj;
5413         struct intel_framebuffer *intel_fb;
5414         int ret;
5415
5416         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5417         if (!obj)
5418                 return NULL;
5419
5420         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5421         if (!intel_fb)
5422                 return NULL;
5423
5424         ret = intel_framebuffer_init(dev, intel_fb,
5425                                      mode_cmd, obj);
5426         if (ret) {
5427                 drm_gem_object_unreference_unlocked(obj);
5428                 kfree(intel_fb);
5429                 return NULL;
5430         }
5431
5432         return &intel_fb->base;
5433 }
5434
5435 static const struct drm_mode_config_funcs intel_mode_funcs = {
5436         .fb_create = intel_user_framebuffer_create,
5437         .output_poll_changed = intel_fb_output_poll_changed,
5438 };
5439
5440 static struct drm_gem_object *
5441 intel_alloc_context_page(struct drm_device *dev)
5442 {
5443         struct drm_gem_object *ctx;
5444         int ret;
5445
5446         ctx = i915_gem_alloc_object(dev, 4096);
5447         if (!ctx) {
5448                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5449                 return NULL;
5450         }
5451
5452         mutex_lock(&dev->struct_mutex);
5453         ret = i915_gem_object_pin(ctx, 4096);
5454         if (ret) {
5455                 DRM_ERROR("failed to pin power context: %d\n", ret);
5456                 goto err_unref;
5457         }
5458
5459         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5460         if (ret) {
5461                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5462                 goto err_unpin;
5463         }
5464         mutex_unlock(&dev->struct_mutex);
5465
5466         return ctx;
5467
5468 err_unpin:
5469         i915_gem_object_unpin(ctx);
5470 err_unref:
5471         drm_gem_object_unreference(ctx);
5472         mutex_unlock(&dev->struct_mutex);
5473         return NULL;
5474 }
5475
5476 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5477 {
5478         struct drm_i915_private *dev_priv = dev->dev_private;
5479         u16 rgvswctl;
5480
5481         rgvswctl = I915_READ16(MEMSWCTL);
5482         if (rgvswctl & MEMCTL_CMD_STS) {
5483                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5484                 return false; /* still busy with another command */
5485         }
5486
5487         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5488                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5489         I915_WRITE16(MEMSWCTL, rgvswctl);
5490         POSTING_READ16(MEMSWCTL);
5491
5492         rgvswctl |= MEMCTL_CMD_STS;
5493         I915_WRITE16(MEMSWCTL, rgvswctl);
5494
5495         return true;
5496 }
5497
5498 void ironlake_enable_drps(struct drm_device *dev)
5499 {
5500         struct drm_i915_private *dev_priv = dev->dev_private;
5501         u32 rgvmodectl = I915_READ(MEMMODECTL);
5502         u8 fmax, fmin, fstart, vstart;
5503
5504         /* 100ms RC evaluation intervals */
5505         I915_WRITE(RCUPEI, 100000);
5506         I915_WRITE(RCDNEI, 100000);
5507
5508         /* Set max/min thresholds to 90ms and 80ms respectively */
5509         I915_WRITE(RCBMAXAVG, 90000);
5510         I915_WRITE(RCBMINAVG, 80000);
5511
5512         I915_WRITE(MEMIHYST, 1);
5513
5514         /* Set up min, max, and cur for interrupt handling */
5515         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5516         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5517         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5518                 MEMMODE_FSTART_SHIFT;
5519         fstart = fmax;
5520
5521         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5522                 PXVFREQ_PX_SHIFT;
5523
5524         dev_priv->fmax = fstart; /* IPS callback will increase this */
5525         dev_priv->fstart = fstart;
5526
5527         dev_priv->max_delay = fmax;
5528         dev_priv->min_delay = fmin;
5529         dev_priv->cur_delay = fstart;
5530
5531         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5532                          fstart);
5533
5534         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5535
5536         /*
5537          * Interrupts will be enabled in ironlake_irq_postinstall
5538          */
5539
5540         I915_WRITE(VIDSTART, vstart);
5541         POSTING_READ(VIDSTART);
5542
5543         rgvmodectl |= MEMMODE_SWMODE_EN;
5544         I915_WRITE(MEMMODECTL, rgvmodectl);
5545
5546         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5547                 DRM_ERROR("stuck trying to change perf mode\n");
5548         msleep(1);
5549
5550         ironlake_set_drps(dev, fstart);
5551
5552         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5553                 I915_READ(0x112e0);
5554         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5555         dev_priv->last_count2 = I915_READ(0x112f4);
5556         getrawmonotonic(&dev_priv->last_time2);
5557 }
5558
5559 void ironlake_disable_drps(struct drm_device *dev)
5560 {
5561         struct drm_i915_private *dev_priv = dev->dev_private;
5562         u16 rgvswctl = I915_READ16(MEMSWCTL);
5563
5564         /* Ack interrupts, disable EFC interrupt */
5565         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5566         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5567         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5568         I915_WRITE(DEIIR, DE_PCU_EVENT);
5569         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5570
5571         /* Go back to the starting frequency */
5572         ironlake_set_drps(dev, dev_priv->fstart);
5573         msleep(1);
5574         rgvswctl |= MEMCTL_CMD_STS;
5575         I915_WRITE(MEMSWCTL, rgvswctl);
5576         msleep(1);
5577
5578 }
5579
5580 static unsigned long intel_pxfreq(u32 vidfreq)
5581 {
5582         unsigned long freq;
5583         int div = (vidfreq & 0x3f0000) >> 16;
5584         int post = (vidfreq & 0x3000) >> 12;
5585         int pre = (vidfreq & 0x7);
5586
5587         if (!pre)
5588                 return 0;
5589
5590         freq = ((div * 133333) / ((1<<post) * pre));
5591
5592         return freq;
5593 }
5594
5595 void intel_init_emon(struct drm_device *dev)
5596 {
5597         struct drm_i915_private *dev_priv = dev->dev_private;
5598         u32 lcfuse;
5599         u8 pxw[16];
5600         int i;
5601
5602         /* Disable to program */
5603         I915_WRITE(ECR, 0);
5604         POSTING_READ(ECR);
5605
5606         /* Program energy weights for various events */
5607         I915_WRITE(SDEW, 0x15040d00);
5608         I915_WRITE(CSIEW0, 0x007f0000);
5609         I915_WRITE(CSIEW1, 0x1e220004);
5610         I915_WRITE(CSIEW2, 0x04000004);
5611
5612         for (i = 0; i < 5; i++)
5613                 I915_WRITE(PEW + (i * 4), 0);
5614         for (i = 0; i < 3; i++)
5615                 I915_WRITE(DEW + (i * 4), 0);
5616
5617         /* Program P-state weights to account for frequency power adjustment */
5618         for (i = 0; i < 16; i++) {
5619                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5620                 unsigned long freq = intel_pxfreq(pxvidfreq);
5621                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5622                         PXVFREQ_PX_SHIFT;
5623                 unsigned long val;
5624
5625                 val = vid * vid;
5626                 val *= (freq / 1000);
5627                 val *= 255;
5628                 val /= (127*127*900);
5629                 if (val > 0xff)
5630                         DRM_ERROR("bad pxval: %ld\n", val);
5631                 pxw[i] = val;
5632         }
5633         /* Render standby states get 0 weight */
5634         pxw[14] = 0;
5635         pxw[15] = 0;
5636
5637         for (i = 0; i < 4; i++) {
5638                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5639                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5640                 I915_WRITE(PXW + (i * 4), val);
5641         }
5642
5643         /* Adjust magic regs to magic values (more experimental results) */
5644         I915_WRITE(OGW0, 0);
5645         I915_WRITE(OGW1, 0);
5646         I915_WRITE(EG0, 0x00007f00);
5647         I915_WRITE(EG1, 0x0000000e);
5648         I915_WRITE(EG2, 0x000e0000);
5649         I915_WRITE(EG3, 0x68000300);
5650         I915_WRITE(EG4, 0x42000000);
5651         I915_WRITE(EG5, 0x00140031);
5652         I915_WRITE(EG6, 0);
5653         I915_WRITE(EG7, 0);
5654
5655         for (i = 0; i < 8; i++)
5656                 I915_WRITE(PXWL + (i * 4), 0);
5657
5658         /* Enable PMON + select events */
5659         I915_WRITE(ECR, 0x80000019);
5660
5661         lcfuse = I915_READ(LCFUSE02);
5662
5663         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5664 }
5665
5666 void intel_init_clock_gating(struct drm_device *dev)
5667 {
5668         struct drm_i915_private *dev_priv = dev->dev_private;
5669
5670         /*
5671          * Disable clock gating reported to work incorrectly according to the
5672          * specs, but enable as much else as we can.
5673          */
5674         if (HAS_PCH_SPLIT(dev)) {
5675                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5676
5677                 if (IS_IRONLAKE(dev)) {
5678                         /* Required for FBC */
5679                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5680                         /* Required for CxSR */
5681                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5682
5683                         I915_WRITE(PCH_3DCGDIS0,
5684                                    MARIUNIT_CLOCK_GATE_DISABLE |
5685                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5686                 }
5687
5688                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5689
5690                 /*
5691                  * According to the spec the following bits should be set in
5692                  * order to enable memory self-refresh
5693                  * The bit 22/21 of 0x42004
5694                  * The bit 5 of 0x42020
5695                  * The bit 15 of 0x45000
5696                  */
5697                 if (IS_IRONLAKE(dev)) {
5698                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5699                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5700                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5701                         I915_WRITE(ILK_DSPCLK_GATE,
5702                                         (I915_READ(ILK_DSPCLK_GATE) |
5703                                                 ILK_DPARB_CLK_GATE));
5704                         I915_WRITE(DISP_ARB_CTL,
5705                                         (I915_READ(DISP_ARB_CTL) |
5706                                                 DISP_FBC_WM_DIS));
5707                 }
5708                 /*
5709                  * Based on the document from hardware guys the following bits
5710                  * should be set unconditionally in order to enable FBC.
5711                  * The bit 22 of 0x42000
5712                  * The bit 22 of 0x42004
5713                  * The bit 7,8,9 of 0x42020.
5714                  */
5715                 if (IS_IRONLAKE_M(dev)) {
5716                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5717                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5718                                    ILK_FBCQ_DIS);
5719                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5720                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5721                                    ILK_DPARB_GATE);
5722                         I915_WRITE(ILK_DSPCLK_GATE,
5723                                    I915_READ(ILK_DSPCLK_GATE) |
5724                                    ILK_DPFC_DIS1 |
5725                                    ILK_DPFC_DIS2 |
5726                                    ILK_CLK_FBC);
5727                 }
5728                 if (IS_GEN6(dev))
5729                         return;
5730         } else if (IS_G4X(dev)) {
5731                 uint32_t dspclk_gate;
5732                 I915_WRITE(RENCLK_GATE_D1, 0);
5733                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5734                        GS_UNIT_CLOCK_GATE_DISABLE |
5735                        CL_UNIT_CLOCK_GATE_DISABLE);
5736                 I915_WRITE(RAMCLK_GATE_D, 0);
5737                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5738                         OVRUNIT_CLOCK_GATE_DISABLE |
5739                         OVCUNIT_CLOCK_GATE_DISABLE;
5740                 if (IS_GM45(dev))
5741                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5742                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5743         } else if (IS_I965GM(dev)) {
5744                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5745                 I915_WRITE(RENCLK_GATE_D2, 0);
5746                 I915_WRITE(DSPCLK_GATE_D, 0);
5747                 I915_WRITE(RAMCLK_GATE_D, 0);
5748                 I915_WRITE16(DEUC, 0);
5749         } else if (IS_I965G(dev)) {
5750                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5751                        I965_RCC_CLOCK_GATE_DISABLE |
5752                        I965_RCPB_CLOCK_GATE_DISABLE |
5753                        I965_ISC_CLOCK_GATE_DISABLE |
5754                        I965_FBC_CLOCK_GATE_DISABLE);
5755                 I915_WRITE(RENCLK_GATE_D2, 0);
5756         } else if (IS_I9XX(dev)) {
5757                 u32 dstate = I915_READ(D_STATE);
5758
5759                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5760                         DSTATE_DOT_CLOCK_GATING;
5761                 I915_WRITE(D_STATE, dstate);
5762         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5763                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5764         } else if (IS_I830(dev)) {
5765                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5766         }
5767
5768         /*
5769          * GPU can automatically power down the render unit if given a page
5770          * to save state.
5771          */
5772         if (IS_IRONLAKE_M(dev)) {
5773                 if (dev_priv->renderctx == NULL)
5774                         dev_priv->renderctx = intel_alloc_context_page(dev);
5775                 if (dev_priv->renderctx) {
5776                         struct drm_i915_gem_object *obj_priv;
5777                         obj_priv = to_intel_bo(dev_priv->renderctx);
5778                         if (obj_priv) {
5779                                 BEGIN_LP_RING(4);
5780                                 OUT_RING(MI_SET_CONTEXT);
5781                                 OUT_RING(obj_priv->gtt_offset |
5782                                                 MI_MM_SPACE_GTT |
5783                                                 MI_SAVE_EXT_STATE_EN |
5784                                                 MI_RESTORE_EXT_STATE_EN |
5785                                                 MI_RESTORE_INHIBIT);
5786                                 OUT_RING(MI_NOOP);
5787                                 OUT_RING(MI_FLUSH);
5788                                 ADVANCE_LP_RING();
5789                         }
5790                 } else {
5791                         DRM_DEBUG_KMS("Failed to allocate render context."
5792                                       "Disable RC6\n");
5793                         return;
5794                 }
5795         }
5796
5797         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5798                 struct drm_i915_gem_object *obj_priv = NULL;
5799
5800                 if (dev_priv->pwrctx) {
5801                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5802                 } else {
5803                         struct drm_gem_object *pwrctx;
5804
5805                         pwrctx = intel_alloc_context_page(dev);
5806                         if (pwrctx) {
5807                                 dev_priv->pwrctx = pwrctx;
5808                                 obj_priv = to_intel_bo(pwrctx);
5809                         }
5810                 }
5811
5812                 if (obj_priv) {
5813                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5814                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5815                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5816                 }
5817         }
5818 }
5819
5820 /* Set up chip specific display functions */
5821 static void intel_init_display(struct drm_device *dev)
5822 {
5823         struct drm_i915_private *dev_priv = dev->dev_private;
5824
5825         /* We always want a DPMS function */
5826         if (HAS_PCH_SPLIT(dev))
5827                 dev_priv->display.dpms = ironlake_crtc_dpms;
5828         else
5829                 dev_priv->display.dpms = i9xx_crtc_dpms;
5830
5831         if (I915_HAS_FBC(dev)) {
5832                 if (IS_IRONLAKE_M(dev)) {
5833                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5834                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5835                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5836                 } else if (IS_GM45(dev)) {
5837                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5838                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5839                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5840                 } else if (IS_I965GM(dev)) {
5841                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5842                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5843                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5844                 }
5845                 /* 855GM needs testing */
5846         }
5847
5848         /* Returns the core display clock speed */
5849         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5850                 dev_priv->display.get_display_clock_speed =
5851                         i945_get_display_clock_speed;
5852         else if (IS_I915G(dev))
5853                 dev_priv->display.get_display_clock_speed =
5854                         i915_get_display_clock_speed;
5855         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5856                 dev_priv->display.get_display_clock_speed =
5857                         i9xx_misc_get_display_clock_speed;
5858         else if (IS_I915GM(dev))
5859                 dev_priv->display.get_display_clock_speed =
5860                         i915gm_get_display_clock_speed;
5861         else if (IS_I865G(dev))
5862                 dev_priv->display.get_display_clock_speed =
5863                         i865_get_display_clock_speed;
5864         else if (IS_I85X(dev))
5865                 dev_priv->display.get_display_clock_speed =
5866                         i855_get_display_clock_speed;
5867         else /* 852, 830 */
5868                 dev_priv->display.get_display_clock_speed =
5869                         i830_get_display_clock_speed;
5870
5871         /* For FIFO watermark updates */
5872         if (HAS_PCH_SPLIT(dev)) {
5873                 if (IS_IRONLAKE(dev)) {
5874                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5875                                 dev_priv->display.update_wm = ironlake_update_wm;
5876                         else {
5877                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5878                                               "Disable CxSR\n");
5879                                 dev_priv->display.update_wm = NULL;
5880                         }
5881                 } else
5882                         dev_priv->display.update_wm = NULL;
5883         } else if (IS_PINEVIEW(dev)) {
5884                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5885                                             dev_priv->is_ddr3,
5886                                             dev_priv->fsb_freq,
5887                                             dev_priv->mem_freq)) {
5888                         DRM_INFO("failed to find known CxSR latency "
5889                                  "(found ddr%s fsb freq %d, mem freq %d), "
5890                                  "disabling CxSR\n",
5891                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5892                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5893                         /* Disable CxSR and never update its watermark again */
5894                         pineview_disable_cxsr(dev);
5895                         dev_priv->display.update_wm = NULL;
5896                 } else
5897                         dev_priv->display.update_wm = pineview_update_wm;
5898         } else if (IS_G4X(dev))
5899                 dev_priv->display.update_wm = g4x_update_wm;
5900         else if (IS_I965G(dev))
5901                 dev_priv->display.update_wm = i965_update_wm;
5902         else if (IS_I9XX(dev)) {
5903                 dev_priv->display.update_wm = i9xx_update_wm;
5904                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5905         } else if (IS_I85X(dev)) {
5906                 dev_priv->display.update_wm = i9xx_update_wm;
5907                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5908         } else {
5909                 dev_priv->display.update_wm = i830_update_wm;
5910                 if (IS_845G(dev))
5911                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5912                 else
5913                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5914         }
5915 }
5916
5917 /*
5918  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5919  * resume, or other times.  This quirk makes sure that's the case for
5920  * affected systems.
5921  */
5922 static void quirk_pipea_force (struct drm_device *dev)
5923 {
5924         struct drm_i915_private *dev_priv = dev->dev_private;
5925
5926         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5927         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5928 }
5929
5930 struct intel_quirk {
5931         int device;
5932         int subsystem_vendor;
5933         int subsystem_device;
5934         void (*hook)(struct drm_device *dev);
5935 };
5936
5937 struct intel_quirk intel_quirks[] = {
5938         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5939         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5940         /* HP Mini needs pipe A force quirk (LP: #322104) */
5941         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5942
5943         /* Thinkpad R31 needs pipe A force quirk */
5944         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5945         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5946         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5947
5948         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5949         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5950         /* ThinkPad X40 needs pipe A force quirk */
5951
5952         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5953         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5954
5955         /* 855 & before need to leave pipe A & dpll A up */
5956         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5957         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5958 };
5959
5960 static void intel_init_quirks(struct drm_device *dev)
5961 {
5962         struct pci_dev *d = dev->pdev;
5963         int i;
5964
5965         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5966                 struct intel_quirk *q = &intel_quirks[i];
5967
5968                 if (d->device == q->device &&
5969                     (d->subsystem_vendor == q->subsystem_vendor ||
5970                      q->subsystem_vendor == PCI_ANY_ID) &&
5971                     (d->subsystem_device == q->subsystem_device ||
5972                      q->subsystem_device == PCI_ANY_ID))
5973                         q->hook(dev);
5974         }
5975 }
5976
5977 /* Disable the VGA plane that we never use */
5978 static void i915_disable_vga(struct drm_device *dev)
5979 {
5980         struct drm_i915_private *dev_priv = dev->dev_private;
5981         u8 sr1;
5982         u32 vga_reg;
5983
5984         if (HAS_PCH_SPLIT(dev))
5985                 vga_reg = CPU_VGACNTRL;
5986         else
5987                 vga_reg = VGACNTRL;
5988
5989         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5990         outb(1, VGA_SR_INDEX);
5991         sr1 = inb(VGA_SR_DATA);
5992         outb(sr1 | 1<<5, VGA_SR_DATA);
5993         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5994         udelay(300);
5995
5996         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5997         POSTING_READ(vga_reg);
5998 }
5999
6000 void intel_modeset_init(struct drm_device *dev)
6001 {
6002         struct drm_i915_private *dev_priv = dev->dev_private;
6003         int i;
6004
6005         drm_mode_config_init(dev);
6006
6007         dev->mode_config.min_width = 0;
6008         dev->mode_config.min_height = 0;
6009
6010         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6011
6012         intel_init_quirks(dev);
6013
6014         intel_init_display(dev);
6015
6016         if (IS_I965G(dev)) {
6017                 dev->mode_config.max_width = 8192;
6018                 dev->mode_config.max_height = 8192;
6019         } else if (IS_I9XX(dev)) {
6020                 dev->mode_config.max_width = 4096;
6021                 dev->mode_config.max_height = 4096;
6022         } else {
6023                 dev->mode_config.max_width = 2048;
6024                 dev->mode_config.max_height = 2048;
6025         }
6026
6027         /* set memory base */
6028         if (IS_I9XX(dev))
6029                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6030         else
6031                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6032
6033         if (IS_MOBILE(dev) || IS_I9XX(dev))
6034                 dev_priv->num_pipe = 2;
6035         else
6036                 dev_priv->num_pipe = 1;
6037         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6038                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6039
6040         for (i = 0; i < dev_priv->num_pipe; i++) {
6041                 intel_crtc_init(dev, i);
6042         }
6043
6044         intel_setup_outputs(dev);
6045
6046         intel_init_clock_gating(dev);
6047
6048         /* Just disable it once at startup */
6049         i915_disable_vga(dev);
6050
6051         if (IS_IRONLAKE_M(dev)) {
6052                 ironlake_enable_drps(dev);
6053                 intel_init_emon(dev);
6054         }
6055
6056         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6057         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6058                     (unsigned long)dev);
6059
6060         intel_setup_overlay(dev);
6061 }
6062
6063 void intel_modeset_cleanup(struct drm_device *dev)
6064 {
6065         struct drm_i915_private *dev_priv = dev->dev_private;
6066         struct drm_crtc *crtc;
6067         struct intel_crtc *intel_crtc;
6068
6069         mutex_lock(&dev->struct_mutex);
6070
6071         drm_kms_helper_poll_fini(dev);
6072         intel_fbdev_fini(dev);
6073
6074         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6075                 /* Skip inactive CRTCs */
6076                 if (!crtc->fb)
6077                         continue;
6078
6079                 intel_crtc = to_intel_crtc(crtc);
6080                 intel_increase_pllclock(crtc, false);
6081                 del_timer_sync(&intel_crtc->idle_timer);
6082         }
6083
6084         del_timer_sync(&dev_priv->idle_timer);
6085
6086         if (dev_priv->display.disable_fbc)
6087                 dev_priv->display.disable_fbc(dev);
6088
6089         if (dev_priv->renderctx) {
6090                 struct drm_i915_gem_object *obj_priv;
6091
6092                 obj_priv = to_intel_bo(dev_priv->renderctx);
6093                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6094                 I915_READ(CCID);
6095                 i915_gem_object_unpin(dev_priv->renderctx);
6096                 drm_gem_object_unreference(dev_priv->renderctx);
6097         }
6098
6099         if (dev_priv->pwrctx) {
6100                 struct drm_i915_gem_object *obj_priv;
6101
6102                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6103                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6104                 I915_READ(PWRCTXA);
6105                 i915_gem_object_unpin(dev_priv->pwrctx);
6106                 drm_gem_object_unreference(dev_priv->pwrctx);
6107         }
6108
6109         if (IS_IRONLAKE_M(dev))
6110                 ironlake_disable_drps(dev);
6111
6112         mutex_unlock(&dev->struct_mutex);
6113
6114         drm_mode_config_cleanup(dev);
6115 }
6116
6117
6118 /*
6119  * Return which encoder is currently attached for connector.
6120  */
6121 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6122 {
6123         struct drm_mode_object *obj;
6124         struct drm_encoder *encoder;
6125         int i;
6126
6127         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6128                 if (connector->encoder_ids[i] == 0)
6129                         break;
6130
6131                 obj = drm_mode_object_find(connector->dev,
6132                                            connector->encoder_ids[i],
6133                                            DRM_MODE_OBJECT_ENCODER);
6134                 if (!obj)
6135                         continue;
6136
6137                 encoder = obj_to_encoder(obj);
6138                 return encoder;
6139         }
6140         return NULL;
6141 }
6142
6143 /*
6144  * set vga decode state - true == enable VGA decode
6145  */
6146 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6147 {
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         u16 gmch_ctrl;
6150
6151         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6152         if (state)
6153                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6154         else
6155                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6156         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6157         return 0;
6158 }