drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  47
  48 typedef struct {
  49     /* given values */
  50     int n;
  51     int m1, m2;
  52     int p1, p2;
  53     /* derived values */
  54     int dot;
  55     int vco;
  56     int m;
  57     int p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61     int min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65     int dot_limit;
  66     int p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73     intel_p2_t      p2;
  74     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                       int, int, intel_clock_t *);
  76 };
  77
  78 #define I8XX_DOT_MIN              25000
  79 #define I8XX_DOT_MAX             350000
  80 #define I8XX_VCO_MIN             930000
  81 #define I8XX_VCO_MAX            1400000
  82 #define I8XX_N_MIN                    3
  83 #define I8XX_N_MAX                   16
  84 #define I8XX_M_MIN                   96
  85 #define I8XX_M_MAX                  140
  86 #define I8XX_M1_MIN                  18
  87 #define I8XX_M1_MAX                  26
  88 #define I8XX_M2_MIN                   6
  89 #define I8XX_M2_MAX                  16
  90 #define I8XX_P_MIN                    4
  91 #define I8XX_P_MAX                  128
  92 #define I8XX_P1_MIN                   2
  93 #define I8XX_P1_MAX                  33
  94 #define I8XX_P1_LVDS_MIN              1
  95 #define I8XX_P1_LVDS_MAX              6
  96 #define I8XX_P2_SLOW                  4
  97 #define I8XX_P2_FAST                  2
  98 #define I8XX_P2_LVDS_SLOW             14
  99 #define I8XX_P2_LVDS_FAST             7
 100 #define I8XX_P2_SLOW_LIMIT       165000
 101
 102 #define I9XX_DOT_MIN              20000
 103 #define I9XX_DOT_MAX             400000
 104 #define I9XX_VCO_MIN            1400000
 105 #define I9XX_VCO_MAX            2800000
 106 #define PINEVIEW_VCO_MIN                1700000
 107 #define PINEVIEW_VCO_MAX                3500000
 108 #define I9XX_N_MIN                    1
 109 #define I9XX_N_MAX                    6
 110 /* Pineview's Ncounter is a ring counter */
 111 #define PINEVIEW_N_MIN                3
 112 #define PINEVIEW_N_MAX                6
 113 #define I9XX_M_MIN                   70
 114 #define I9XX_M_MAX                  120
 115 #define PINEVIEW_M_MIN                2
 116 #define PINEVIEW_M_MAX              256
 117 #define I9XX_M1_MIN                  10
 118 #define I9XX_M1_MAX                  22
 119 #define I9XX_M2_MIN                   5
 120 #define I9XX_M2_MAX                   9
 121 /* Pineview M1 is reserved, and must be 0 */
 122 #define PINEVIEW_M1_MIN               0
 123 #define PINEVIEW_M1_MAX               0
 124 #define PINEVIEW_M2_MIN               0
 125 #define PINEVIEW_M2_MAX               254
 126 #define I9XX_P_SDVO_DAC_MIN           5
 127 #define I9XX_P_SDVO_DAC_MAX          80
 128 #define I9XX_P_LVDS_MIN               7
 129 #define I9XX_P_LVDS_MAX              98
 130 #define PINEVIEW_P_LVDS_MIN                   7
 131 #define PINEVIEW_P_LVDS_MAX                  112
 132 #define I9XX_P1_MIN                   1
 133 #define I9XX_P1_MAX                   8
 134 #define I9XX_P2_SDVO_DAC_SLOW                10
 135 #define I9XX_P2_SDVO_DAC_FAST                 5
 136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 137 #define I9XX_P2_LVDS_SLOW                    14
 138 #define I9XX_P2_LVDS_FAST                     7
 139 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 /*The parameter is for DISPLAY PORT on G4x platform*/
 220 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 221 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 222 #define G4X_N_DISPLAY_PORT_MIN             1
 223 #define G4X_N_DISPLAY_PORT_MAX             2
 224 #define G4X_M_DISPLAY_PORT_MIN             97
 225 #define G4X_M_DISPLAY_PORT_MAX             108
 226 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 227 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 228 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 229 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 230 #define G4X_P_DISPLAY_PORT_MIN             10
 231 #define G4X_P_DISPLAY_PORT_MAX             20
 232 #define G4X_P1_DISPLAY_PORT_MIN            1
 233 #define G4X_P1_DISPLAY_PORT_MAX            2
 234 #define G4X_P2_DISPLAY_PORT_SLOW           10
 235 #define G4X_P2_DISPLAY_PORT_FAST           10
 236 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 237
 238 /* Ironlake / Sandybridge */
 239 /* as we calculate clock using (register_value + 2) for
 240    N/M1/M2, so here the range value for them is (actual_value-2).
 241  */
 242 #define IRONLAKE_DOT_MIN         25000
 243 #define IRONLAKE_DOT_MAX         350000
 244 #define IRONLAKE_VCO_MIN         1760000
 245 #define IRONLAKE_VCO_MAX         3510000
 246 #define IRONLAKE_M1_MIN          12
 247 #define IRONLAKE_M1_MAX          22
 248 #define IRONLAKE_M2_MIN          5
 249 #define IRONLAKE_M2_MAX          9
 250 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 251
 252 /* We have parameter ranges for different type of outputs. */
 253
 254 /* DAC & HDMI Refclk 120Mhz */
 255 #define IRONLAKE_DAC_N_MIN      1
 256 #define IRONLAKE_DAC_N_MAX      5
 257 #define IRONLAKE_DAC_M_MIN      79
 258 #define IRONLAKE_DAC_M_MAX      127
 259 #define IRONLAKE_DAC_P_MIN      5
 260 #define IRONLAKE_DAC_P_MAX      80
 261 #define IRONLAKE_DAC_P1_MIN     1
 262 #define IRONLAKE_DAC_P1_MAX     8
 263 #define IRONLAKE_DAC_P2_SLOW    10
 264 #define IRONLAKE_DAC_P2_FAST    5
 265
 266 /* LVDS single-channel 120Mhz refclk */
 267 #define IRONLAKE_LVDS_S_N_MIN   1
 268 #define IRONLAKE_LVDS_S_N_MAX   3
 269 #define IRONLAKE_LVDS_S_M_MIN   79
 270 #define IRONLAKE_LVDS_S_M_MAX   118
 271 #define IRONLAKE_LVDS_S_P_MIN   28
 272 #define IRONLAKE_LVDS_S_P_MAX   112
 273 #define IRONLAKE_LVDS_S_P1_MIN  2
 274 #define IRONLAKE_LVDS_S_P1_MAX  8
 275 #define IRONLAKE_LVDS_S_P2_SLOW 14
 276 #define IRONLAKE_LVDS_S_P2_FAST 14
 277
 278 /* LVDS dual-channel 120Mhz refclk */
 279 #define IRONLAKE_LVDS_D_N_MIN   1
 280 #define IRONLAKE_LVDS_D_N_MAX   3
 281 #define IRONLAKE_LVDS_D_M_MIN   79
 282 #define IRONLAKE_LVDS_D_M_MAX   127
 283 #define IRONLAKE_LVDS_D_P_MIN   14
 284 #define IRONLAKE_LVDS_D_P_MAX   56
 285 #define IRONLAKE_LVDS_D_P1_MIN  2
 286 #define IRONLAKE_LVDS_D_P1_MAX  8
 287 #define IRONLAKE_LVDS_D_P2_SLOW 7
 288 #define IRONLAKE_LVDS_D_P2_FAST 7
 289
 290 /* LVDS single-channel 100Mhz refclk */
 291 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 292 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 293 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 294 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 295 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 296 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 297 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 298 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 300 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 301
 302 /* LVDS dual-channel 100Mhz refclk */
 303 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 304 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 305 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 306 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 307 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 308 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 309 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 310 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 312 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 313
 314 /* DisplayPort */
 315 #define IRONLAKE_DP_N_MIN               1
 316 #define IRONLAKE_DP_N_MAX               2
 317 #define IRONLAKE_DP_M_MIN               81
 318 #define IRONLAKE_DP_M_MAX               90
 319 #define IRONLAKE_DP_P_MIN               10
 320 #define IRONLAKE_DP_P_MAX               20
 321 #define IRONLAKE_DP_P2_FAST             10
 322 #define IRONLAKE_DP_P2_SLOW             10
 323 #define IRONLAKE_DP_P2_LIMIT            0
 324 #define IRONLAKE_DP_P1_MIN              1
 325 #define IRONLAKE_DP_P1_MAX              2
 326
 327 /* FDI */
 328 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 329
 330 static bool
 331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 332                     int target, int refclk, intel_clock_t *best_clock);
 333 static bool
 334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 335                         int target, int refclk, intel_clock_t *best_clock);
 336
 337 static bool
 338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 339                       int target, int refclk, intel_clock_t *best_clock);
 340 static bool
 341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 342                            int target, int refclk, intel_clock_t *best_clock);
 343
 344 static const intel_limit_t intel_limits_i8xx_dvo = {
 345         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 346         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 347         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 348         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 349         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 350         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 351         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 352         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 353         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 354                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 355         .find_pll = intel_find_best_PLL,
 356 };
 357
 358 static const intel_limit_t intel_limits_i8xx_lvds = {
 359         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 360         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 361         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 362         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 363         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 364         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 365         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 366         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 367         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 368                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 369         .find_pll = intel_find_best_PLL,
 370 };
 371
 372 static const intel_limit_t intel_limits_i9xx_sdvo = {
 373         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 374         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 375         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 376         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 377         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 378         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 379         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 380         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 381         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 382                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 383         .find_pll = intel_find_best_PLL,
 384 };
 385
 386 static const intel_limit_t intel_limits_i9xx_lvds = {
 387         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 388         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 389         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 390         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 391         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 392         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 393         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 394         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 395         /* The single-channel range is 25-112Mhz, and dual-channel
 396          * is 80-224Mhz.  Prefer single channel as much as possible.
 397          */
 398         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 399                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 400         .find_pll = intel_find_best_PLL,
 401 };
 402
 403     /* below parameter and function is for G4X Chipset Family*/
 404 static const intel_limit_t intel_limits_g4x_sdvo = {
 405         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 406         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 407         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 408         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 409         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 410         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 411         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 412         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 413         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 414                  .p2_slow = G4X_P2_SDVO_SLOW,
 415                  .p2_fast = G4X_P2_SDVO_FAST
 416         },
 417         .find_pll = intel_g4x_find_best_PLL,
 418 };
 419
 420 static const intel_limit_t intel_limits_g4x_hdmi = {
 421         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 422         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 423         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 424         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 425         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 426         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 427         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 428         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 429         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 430                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 431                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 432         },
 433         .find_pll = intel_g4x_find_best_PLL,
 434 };
 435
 436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 437         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 439         .vco = { .min = G4X_VCO_MIN,
 440                  .max = G4X_VCO_MAX },
 441         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 443         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 445         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 447         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 448                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 449         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 451         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 453         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 454                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 455                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 456         },
 457         .find_pll = intel_g4x_find_best_PLL,
 458 };
 459
 460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 461         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 463         .vco = { .min = G4X_VCO_MIN,
 464                  .max = G4X_VCO_MAX },
 465         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 467         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 469         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 471         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 472                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 473         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 475         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 477         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 478                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 479                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 480         },
 481         .find_pll = intel_g4x_find_best_PLL,
 482 };
 483
 484 static const intel_limit_t intel_limits_g4x_display_port = {
 485         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 486                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 487         .vco = { .min = G4X_VCO_MIN,
 488                  .max = G4X_VCO_MAX},
 489         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 490                  .max = G4X_N_DISPLAY_PORT_MAX },
 491         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 492                  .max = G4X_M_DISPLAY_PORT_MAX },
 493         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 494                  .max = G4X_M1_DISPLAY_PORT_MAX },
 495         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 496                  .max = G4X_M2_DISPLAY_PORT_MAX },
 497         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 498                  .max = G4X_P_DISPLAY_PORT_MAX },
 499         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 500                  .max = G4X_P1_DISPLAY_PORT_MAX},
 501         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 502                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 503                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 504         .find_pll = intel_find_pll_g4x_dp,
 505 };
 506
 507 static const intel_limit_t intel_limits_pineview_sdvo = {
 508         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 509         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 510         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 511         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 512         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 513         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 514         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 515         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 516         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 517                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 518         .find_pll = intel_find_best_PLL,
 519 };
 520
 521 static const intel_limit_t intel_limits_pineview_lvds = {
 522         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 523         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 524         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 525         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 526         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 527         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 528         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 529         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 530         /* Pineview only supports single-channel mode. */
 531         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 532                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 533         .find_pll = intel_find_best_PLL,
 534 };
 535
 536 static const intel_limit_t intel_limits_ironlake_dac = {
 537         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 538         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 539         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 540         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 541         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 542         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 543         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 544         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 545         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 546                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 547                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 548         .find_pll = intel_g4x_find_best_PLL,
 549 };
 550
 551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 552         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 553         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 554         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 555         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 556         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 557         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 558         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 559         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 560         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 561                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 562                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 563         .find_pll = intel_g4x_find_best_PLL,
 564 };
 565
 566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 567         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 568         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 569         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 570         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 571         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 572         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 573         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 574         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 575         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 576                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 577                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 578         .find_pll = intel_g4x_find_best_PLL,
 579 };
 580
 581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 582         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 583         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 584         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 585         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 586         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 587         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 588         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 589         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 590         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 591                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 592                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 593         .find_pll = intel_g4x_find_best_PLL,
 594 };
 595
 596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 597         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 598         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 599         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 600         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 601         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 602         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 603         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 604         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 605         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 606                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 607                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 608         .find_pll = intel_g4x_find_best_PLL,
 609 };
 610
 611 static const intel_limit_t intel_limits_ironlake_display_port = {
 612         .dot = { .min = IRONLAKE_DOT_MIN,
 613                  .max = IRONLAKE_DOT_MAX },
 614         .vco = { .min = IRONLAKE_VCO_MIN,
 615                  .max = IRONLAKE_VCO_MAX},
 616         .n   = { .min = IRONLAKE_DP_N_MIN,
 617                  .max = IRONLAKE_DP_N_MAX },
 618         .m   = { .min = IRONLAKE_DP_M_MIN,
 619                  .max = IRONLAKE_DP_M_MAX },
 620         .m1  = { .min = IRONLAKE_M1_MIN,
 621                  .max = IRONLAKE_M1_MAX },
 622         .m2  = { .min = IRONLAKE_M2_MIN,
 623                  .max = IRONLAKE_M2_MAX },
 624         .p   = { .min = IRONLAKE_DP_P_MIN,
 625                  .max = IRONLAKE_DP_P_MAX },
 626         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 627                  .max = IRONLAKE_DP_P1_MAX},
 628         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 629                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 630                  .p2_fast = IRONLAKE_DP_P2_FAST },
 631         .find_pll = intel_find_pll_ironlake_dp,
 632 };
 633
 634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 635 {
 636         struct drm_device *dev = crtc->dev;
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638         const intel_limit_t *limit;
 639         int refclk = 120;
 640
 641         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 642                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 643                         refclk = 100;
 644
 645                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 646                     LVDS_CLKB_POWER_UP) {
 647                         /* LVDS dual channel */
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_dual_lvds;
 652                 } else {
 653                         if (refclk == 100)
 654                                 limit = &intel_limits_ironlake_single_lvds_100m;
 655                         else
 656                                 limit = &intel_limits_ironlake_single_lvds;
 657                 }
 658         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 659                         HAS_eDP)
 660                 limit = &intel_limits_ironlake_display_port;
 661         else
 662                 limit = &intel_limits_ironlake_dac;
 663
 664         return limit;
 665 }
 666
 667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 668 {
 669         struct drm_device *dev = crtc->dev;
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         const intel_limit_t *limit;
 672
 673         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 674                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 675                     LVDS_CLKB_POWER_UP)
 676                         /* LVDS with dual channel */
 677                         limit = &intel_limits_g4x_dual_channel_lvds;
 678                 else
 679                         /* LVDS with dual channel */
 680                         limit = &intel_limits_g4x_single_channel_lvds;
 681         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 682                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 683                 limit = &intel_limits_g4x_hdmi;
 684         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 685                 limit = &intel_limits_g4x_sdvo;
 686         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 687                 limit = &intel_limits_g4x_display_port;
 688         } else /* The option is for other outputs */
 689                 limit = &intel_limits_i9xx_sdvo;
 690
 691         return limit;
 692 }
 693
 694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 695 {
 696         struct drm_device *dev = crtc->dev;
 697         const intel_limit_t *limit;
 698
 699         if (HAS_PCH_SPLIT(dev))
 700                 limit = intel_ironlake_limit(crtc);
 701         else if (IS_G4X(dev)) {
 702                 limit = intel_g4x_limit(crtc);
 703         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_i9xx_lvds;
 706                 else
 707                         limit = &intel_limits_i9xx_sdvo;
 708         } else if (IS_PINEVIEW(dev)) {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_pineview_lvds;
 711                 else
 712                         limit = &intel_limits_pineview_sdvo;
 713         } else {
 714                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 715                         limit = &intel_limits_i8xx_lvds;
 716                 else
 717                         limit = &intel_limits_i8xx_dvo;
 718         }
 719         return limit;
 720 }
 721
 722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 723 static void pineview_clock(int refclk, intel_clock_t *clock)
 724 {
 725         clock->m = clock->m2 + 2;
 726         clock->p = clock->p1 * clock->p2;
 727         clock->vco = refclk * clock->m / clock->n;
 728         clock->dot = clock->vco / clock->p;
 729 }
 730
 731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 732 {
 733         if (IS_PINEVIEW(dev)) {
 734                 pineview_clock(refclk, clock);
 735                 return;
 736         }
 737         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 738         clock->p = clock->p1 * clock->p2;
 739         clock->vco = refclk * clock->m / (clock->n + 2);
 740         clock->dot = clock->vco / clock->p;
 741 }
 742
 743 /**
 744  * Returns whether any output on the specified pipe is of the specified type
 745  */
 746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 747 {
 748     struct drm_device *dev = crtc->dev;
 749     struct drm_mode_config *mode_config = &dev->mode_config;
 750     struct drm_encoder *l_entry;
 751
 752     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 753             if (l_entry && l_entry->crtc == crtc) {
 754                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 755                     if (intel_encoder->type == type)
 756                             return true;
 757             }
 758     }
 759     return false;
 760 }
 761
 762 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 763 /**
 764  * Returns whether the given set of divisors are valid for a given refclk with
 765  * the given connectors.
 766  */
 767
 768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 769 {
 770         const intel_limit_t *limit = intel_limit (crtc);
 771         struct drm_device *dev = crtc->dev;
 772
 773         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 774                 INTELPllInvalid ("p1 out of range\n");
 775         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 776                 INTELPllInvalid ("p out of range\n");
 777         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 778                 INTELPllInvalid ("m2 out of range\n");
 779         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 780                 INTELPllInvalid ("m1 out of range\n");
 781         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 782                 INTELPllInvalid ("m1 <= m2\n");
 783         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 784                 INTELPllInvalid ("m out of range\n");
 785         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 786                 INTELPllInvalid ("n out of range\n");
 787         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 788                 INTELPllInvalid ("vco out of range\n");
 789         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 790          * connector, etc., rather than just a single range.
 791          */
 792         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 793                 INTELPllInvalid ("dot out of range\n");
 794
 795         return true;
 796 }
 797
 798 static bool
 799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 800                     int target, int refclk, intel_clock_t *best_clock)
 801
 802 {
 803         struct drm_device *dev = crtc->dev;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         intel_clock_t clock;
 806         int err = target;
 807
 808         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 809             (I915_READ(LVDS)) != 0) {
 810                 /*
 811                  * For LVDS, if the panel is on, just rely on its current
 812                  * settings for dual-channel.  We haven't figured out how to
 813                  * reliably set up different single/dual channel state, if we
 814                  * even can.
 815                  */
 816                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 817                     LVDS_CLKB_POWER_UP)
 818                         clock.p2 = limit->p2.p2_fast;
 819                 else
 820                         clock.p2 = limit->p2.p2_slow;
 821         } else {
 822                 if (target < limit->p2.dot_limit)
 823                         clock.p2 = limit->p2.p2_slow;
 824                 else
 825                         clock.p2 = limit->p2.p2_fast;
 826         }
 827
 828         memset (best_clock, 0, sizeof (*best_clock));
 829
 830         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 831              clock.m1++) {
 832                 for (clock.m2 = limit->m2.min;
 833                      clock.m2 <= limit->m2.max; clock.m2++) {
 834                         /* m1 is always 0 in Pineview */
 835                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 836                                 break;
 837                         for (clock.n = limit->n.min;
 838                              clock.n <= limit->n.max; clock.n++) {
 839                                 for (clock.p1 = limit->p1.min;
 840                                         clock.p1 <= limit->p1.max; clock.p1++) {
 841                                         int this_err;
 842
 843                                         intel_clock(dev, refclk, &clock);
 844
 845                                         if (!intel_PLL_is_valid(crtc, &clock))
 846                                                 continue;
 847
 848                                         this_err = abs(clock.dot - target);
 849                                         if (this_err < err) {
 850                                                 *best_clock = clock;
 851                                                 err = this_err;
 852                                         }
 853                                 }
 854                         }
 855                 }
 856         }
 857
 858         return (err != target);
 859 }
 860
 861 static bool
 862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *best_clock)
 864 {
 865         struct drm_device *dev = crtc->dev;
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         intel_clock_t clock;
 868         int max_n;
 869         bool found;
 870         /* approximately equals target * 0.00585 */
 871         int err_most = (target >> 8) + (target >> 9);
 872         found = false;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 875                 int lvds_reg;
 876
 877                 if (HAS_PCH_SPLIT(dev))
 878                         lvds_reg = PCH_LVDS;
 879                 else
 880                         lvds_reg = LVDS;
 881                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 882                     LVDS_CLKB_POWER_UP)
 883                         clock.p2 = limit->p2.p2_fast;
 884                 else
 885                         clock.p2 = limit->p2.p2_slow;
 886         } else {
 887                 if (target < limit->p2.dot_limit)
 888                         clock.p2 = limit->p2.p2_slow;
 889                 else
 890                         clock.p2 = limit->p2.p2_fast;
 891         }
 892
 893         memset(best_clock, 0, sizeof(*best_clock));
 894         max_n = limit->n.max;
 895         /* based on hardware requirement, prefer smaller n to precision */
 896         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                 /* based on hardware requirement, prefere larger m1,m2 */
 898                 for (clock.m1 = limit->m1.max;
 899                      clock.m1 >= limit->m1.min; clock.m1--) {
 900                         for (clock.m2 = limit->m2.max;
 901                              clock.m2 >= limit->m2.min; clock.m2--) {
 902                                 for (clock.p1 = limit->p1.max;
 903                                      clock.p1 >= limit->p1.min; clock.p1--) {
 904                                         int this_err;
 905
 906                                         intel_clock(dev, refclk, &clock);
 907                                         if (!intel_PLL_is_valid(crtc, &clock))
 908                                                 continue;
 909                                         this_err = abs(clock.dot - target) ;
 910                                         if (this_err < err_most) {
 911                                                 *best_clock = clock;
 912                                                 err_most = this_err;
 913                                                 max_n = clock.n;
 914                                                 found = true;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920         return found;
 921 }
 922
 923 static bool
 924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                            int target, int refclk, intel_clock_t *best_clock)
 926 {
 927         struct drm_device *dev = crtc->dev;
 928         intel_clock_t clock;
 929
 930         /* return directly when it is eDP */
 931         if (HAS_eDP)
 932                 return true;
 933
 934         if (target < 200000) {
 935                 clock.n = 1;
 936                 clock.p1 = 2;
 937                 clock.p2 = 10;
 938                 clock.m1 = 12;
 939                 clock.m2 = 9;
 940         } else {
 941                 clock.n = 2;
 942                 clock.p1 = 1;
 943                 clock.p2 = 10;
 944                 clock.m1 = 14;
 945                 clock.m2 = 8;
 946         }
 947         intel_clock(dev, refclk, &clock);
 948         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 949         return true;
 950 }
 951
 952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 953 static bool
 954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 955                       int target, int refclk, intel_clock_t *best_clock)
 956 {
 957     intel_clock_t clock;
 958     if (target < 200000) {
 959         clock.p1 = 2;
 960         clock.p2 = 10;
 961         clock.n = 2;
 962         clock.m1 = 23;
 963         clock.m2 = 8;
 964     } else {
 965         clock.p1 = 1;
 966         clock.p2 = 10;
 967         clock.n = 1;
 968         clock.m1 = 14;
 969         clock.m2 = 2;
 970     }
 971     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 972     clock.p = (clock.p1 * clock.p2);
 973     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 974     clock.vco = 0;
 975     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 976     return true;
 977 }
 978
 979 void
 980 intel_wait_for_vblank(struct drm_device *dev)
 981 {
 982         /* Wait for 20ms, i.e. one cycle at 50hz. */
 983         if (in_dbg_master())
 984                 mdelay(20); /* The kernel debugger cannot call msleep() */
 985         else
 986                 msleep(20);
 987 }
 988
 989 /* Parameters have changed, update FBC info */
 990 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 991 {
 992         struct drm_device *dev = crtc->dev;
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         struct drm_framebuffer *fb = crtc->fb;
 995         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 996         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 998         int plane, i;
 999         u32 fbc_ctl, fbc_ctl2;
1000
1001         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003         if (fb->pitch < dev_priv->cfb_pitch)
1004                 dev_priv->cfb_pitch = fb->pitch;
1005
1006         /* FBC_CTL wants 64B units */
1007         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008         dev_priv->cfb_fence = obj_priv->fence_reg;
1009         dev_priv->cfb_plane = intel_crtc->plane;
1010         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012         /* Clear old tags */
1013         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014                 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016         /* Set it up... */
1017         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018         if (obj_priv->tiling_mode != I915_TILING_NONE)
1019                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023         /* enable it... */
1024         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1025         if (IS_I945GM(dev))
1026                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1027         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029         if (obj_priv->tiling_mode != I915_TILING_NONE)
1030                 fbc_ctl |= dev_priv->cfb_fence;
1031         I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
1033         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035 }
1036
1037 void i8xx_disable_fbc(struct drm_device *dev)
1038 {
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040         u32 fbc_ctl;
1041
1042         if (!I915_HAS_FBC(dev))
1043                 return;
1044
1045         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1046                 return; /* Already off, just return */
1047
1048         /* Disable compression */
1049         fbc_ctl = I915_READ(FBC_CONTROL);
1050         fbc_ctl &= ~FBC_CTL_EN;
1051         I915_WRITE(FBC_CONTROL, fbc_ctl);
1052
1053         /* Wait for compressing bit to clear */
1054         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1055                 DRM_DEBUG_KMS("FBC idle timed out\n");
1056                 return;
1057         }
1058
1059         intel_wait_for_vblank(dev);
1060
1061         DRM_DEBUG_KMS("disabled FBC\n");
1062 }
1063
1064 static bool i8xx_fbc_enabled(struct drm_device *dev)
1065 {
1066         struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1069 }
1070
1071 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1072 {
1073         struct drm_device *dev = crtc->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         struct drm_framebuffer *fb = crtc->fb;
1076         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1077         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1079         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1080                      DPFC_CTL_PLANEB);
1081         unsigned long stall_watermark = 200;
1082         u32 dpfc_ctl;
1083
1084         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1085         dev_priv->cfb_fence = obj_priv->fence_reg;
1086         dev_priv->cfb_plane = intel_crtc->plane;
1087
1088         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1089         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1090                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1091                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1092         } else {
1093                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1094         }
1095
1096         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1097         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1098                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1099                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1100         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1101
1102         /* enable it... */
1103         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1104
1105         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1106 }
1107
1108 void g4x_disable_fbc(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         u32 dpfc_ctl;
1112
1113         /* Disable compression */
1114         dpfc_ctl = I915_READ(DPFC_CONTROL);
1115         dpfc_ctl &= ~DPFC_CTL_EN;
1116         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1117         intel_wait_for_vblank(dev);
1118
1119         DRM_DEBUG_KMS("disabled FBC\n");
1120 }
1121
1122 static bool g4x_fbc_enabled(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1127 }
1128
1129 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1130 {
1131         struct drm_device *dev = crtc->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         struct drm_framebuffer *fb = crtc->fb;
1134         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1135         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1137         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1138                                                DPFC_CTL_PLANEB;
1139         unsigned long stall_watermark = 200;
1140         u32 dpfc_ctl;
1141
1142         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1143         dev_priv->cfb_fence = obj_priv->fence_reg;
1144         dev_priv->cfb_plane = intel_crtc->plane;
1145
1146         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1147         dpfc_ctl &= DPFC_RESERVED;
1148         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1149         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1150                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1151                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1152         } else {
1153                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1154         }
1155
1156         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1157         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1158                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1159                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1160         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1161         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1162         /* enable it... */
1163         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1164                    DPFC_CTL_EN);
1165
1166         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1167 }
1168
1169 void ironlake_disable_fbc(struct drm_device *dev)
1170 {
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 dpfc_ctl;
1173
1174         /* Disable compression */
1175         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1176         dpfc_ctl &= ~DPFC_CTL_EN;
1177         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1178         intel_wait_for_vblank(dev);
1179
1180         DRM_DEBUG_KMS("disabled FBC\n");
1181 }
1182
1183 static bool ironlake_fbc_enabled(struct drm_device *dev)
1184 {
1185         struct drm_i915_private *dev_priv = dev->dev_private;
1186
1187         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1188 }
1189
1190 bool intel_fbc_enabled(struct drm_device *dev)
1191 {
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194         if (!dev_priv->display.fbc_enabled)
1195                 return false;
1196
1197         return dev_priv->display.fbc_enabled(dev);
1198 }
1199
1200 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1201 {
1202         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1203
1204         if (!dev_priv->display.enable_fbc)
1205                 return;
1206
1207         dev_priv->display.enable_fbc(crtc, interval);
1208 }
1209
1210 void intel_disable_fbc(struct drm_device *dev)
1211 {
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213
1214         if (!dev_priv->display.disable_fbc)
1215                 return;
1216
1217         dev_priv->display.disable_fbc(dev);
1218 }
1219
1220 /**
1221  * intel_update_fbc - enable/disable FBC as needed
1222  * @crtc: CRTC to point the compressor at
1223  * @mode: mode in use
1224  *
1225  * Set up the framebuffer compression hardware at mode set time.  We
1226  * enable it if possible:
1227  *   - plane A only (on pre-965)
1228  *   - no pixel mulitply/line duplication
1229  *   - no alpha buffer discard
1230  *   - no dual wide
1231  *   - framebuffer <= 2048 in width, 1536 in height
1232  *
1233  * We can't assume that any compression will take place (worst case),
1234  * so the compressed buffer has to be the same size as the uncompressed
1235  * one.  It also must reside (along with the line length buffer) in
1236  * stolen memory.
1237  *
1238  * We need to enable/disable FBC on a global basis.
1239  */
1240 static void intel_update_fbc(struct drm_crtc *crtc,
1241                              struct drm_display_mode *mode)
1242 {
1243         struct drm_device *dev = crtc->dev;
1244         struct drm_i915_private *dev_priv = dev->dev_private;
1245         struct drm_framebuffer *fb = crtc->fb;
1246         struct intel_framebuffer *intel_fb;
1247         struct drm_i915_gem_object *obj_priv;
1248         struct drm_crtc *tmp_crtc;
1249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1250         int plane = intel_crtc->plane;
1251         int crtcs_enabled = 0;
1252
1253         DRM_DEBUG_KMS("\n");
1254
1255         if (!i915_powersave)
1256                 return;
1257
1258         if (!I915_HAS_FBC(dev))
1259                 return;
1260
1261         if (!crtc->fb)
1262                 return;
1263
1264         intel_fb = to_intel_framebuffer(fb);
1265         obj_priv = to_intel_bo(intel_fb->obj);
1266
1267         /*
1268          * If FBC is already on, we just have to verify that we can
1269          * keep it that way...
1270          * Need to disable if:
1271          *   - more than one pipe is active
1272          *   - changing FBC params (stride, fence, mode)
1273          *   - new fb is too large to fit in compressed buffer
1274          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1275          */
1276         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1277                 if (tmp_crtc->enabled)
1278                         crtcs_enabled++;
1279         }
1280         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1281         if (crtcs_enabled > 1) {
1282                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1283                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1284                 goto out_disable;
1285         }
1286         if (intel_fb->obj->size > dev_priv->cfb_size) {
1287                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1288                                 "compression\n");
1289                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1290                 goto out_disable;
1291         }
1292         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1293             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1294                 DRM_DEBUG_KMS("mode incompatible with compression, "
1295                                 "disabling\n");
1296                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1297                 goto out_disable;
1298         }
1299         if ((mode->hdisplay > 2048) ||
1300             (mode->vdisplay > 1536)) {
1301                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1302                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1303                 goto out_disable;
1304         }
1305         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1306                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1307                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1308                 goto out_disable;
1309         }
1310         if (obj_priv->tiling_mode != I915_TILING_X) {
1311                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1312                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1313                 goto out_disable;
1314         }
1315
1316         /* If the kernel debugger is active, always disable compression */
1317         if (in_dbg_master())
1318                 goto out_disable;
1319
1320         if (intel_fbc_enabled(dev)) {
1321                 /* We can re-enable it in this case, but need to update pitch */
1322                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1323                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1324                     (plane != dev_priv->cfb_plane))
1325                         intel_disable_fbc(dev);
1326         }
1327
1328         /* Now try to turn it back on if possible */
1329         if (!intel_fbc_enabled(dev))
1330                 intel_enable_fbc(crtc, 500);
1331
1332         return;
1333
1334 out_disable:
1335         /* Multiple disables should be harmless */
1336         if (intel_fbc_enabled(dev)) {
1337                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1338                 intel_disable_fbc(dev);
1339         }
1340 }
1341
1342 int
1343 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1344 {
1345         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1346         u32 alignment;
1347         int ret;
1348
1349         switch (obj_priv->tiling_mode) {
1350         case I915_TILING_NONE:
1351                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1352                         alignment = 128 * 1024;
1353                 else if (IS_I965G(dev))
1354                         alignment = 4 * 1024;
1355                 else
1356                         alignment = 64 * 1024;
1357                 break;
1358         case I915_TILING_X:
1359                 /* pin() will align the object as required by fence */
1360                 alignment = 0;
1361                 break;
1362         case I915_TILING_Y:
1363                 /* FIXME: Is this true? */
1364                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1365                 return -EINVAL;
1366         default:
1367                 BUG();
1368         }
1369
1370         ret = i915_gem_object_pin(obj, alignment);
1371         if (ret != 0)
1372                 return ret;
1373
1374         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1375          * fence, whereas 965+ only requires a fence if using
1376          * framebuffer compression.  For simplicity, we always install
1377          * a fence as the cost is not that onerous.
1378          */
1379         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1380             obj_priv->tiling_mode != I915_TILING_NONE) {
1381                 ret = i915_gem_object_get_fence_reg(obj);
1382                 if (ret != 0) {
1383                         i915_gem_object_unpin(obj);
1384                         return ret;
1385                 }
1386         }
1387
1388         return 0;
1389 }
1390
1391 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1392 static int
1393 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1394                            int x, int y)
1395 {
1396         struct drm_device *dev = crtc->dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1399         struct intel_framebuffer *intel_fb;
1400         struct drm_i915_gem_object *obj_priv;
1401         struct drm_gem_object *obj;
1402         int plane = intel_crtc->plane;
1403         unsigned long Start, Offset;
1404         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1405         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1406         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1407         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1408         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1409         u32 dspcntr;
1410
1411         switch (plane) {
1412         case 0:
1413         case 1:
1414                 break;
1415         default:
1416                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1417                 return -EINVAL;
1418         }
1419
1420         intel_fb = to_intel_framebuffer(fb);
1421         obj = intel_fb->obj;
1422         obj_priv = to_intel_bo(obj);
1423
1424         dspcntr = I915_READ(dspcntr_reg);
1425         /* Mask out pixel format bits in case we change it */
1426         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1427         switch (fb->bits_per_pixel) {
1428         case 8:
1429                 dspcntr |= DISPPLANE_8BPP;
1430                 break;
1431         case 16:
1432                 if (fb->depth == 15)
1433                         dspcntr |= DISPPLANE_15_16BPP;
1434                 else
1435                         dspcntr |= DISPPLANE_16BPP;
1436                 break;
1437         case 24:
1438         case 32:
1439                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1440                 break;
1441         default:
1442                 DRM_ERROR("Unknown color depth\n");
1443                 return -EINVAL;
1444         }
1445         if (IS_I965G(dev)) {
1446                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1447                         dspcntr |= DISPPLANE_TILED;
1448                 else
1449                         dspcntr &= ~DISPPLANE_TILED;
1450         }
1451
1452         if (IS_IRONLAKE(dev))
1453                 /* must disable */
1454                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1455
1456         I915_WRITE(dspcntr_reg, dspcntr);
1457
1458         Start = obj_priv->gtt_offset;
1459         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1460
1461         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1462         I915_WRITE(dspstride, fb->pitch);
1463         if (IS_I965G(dev)) {
1464                 I915_WRITE(dspbase, Offset);
1465                 I915_READ(dspbase);
1466                 I915_WRITE(dspsurf, Start);
1467                 I915_READ(dspsurf);
1468                 I915_WRITE(dsptileoff, (y << 16) | x);
1469         } else {
1470                 I915_WRITE(dspbase, Start + Offset);
1471                 I915_READ(dspbase);
1472         }
1473
1474         if ((IS_I965G(dev) || plane == 0))
1475                 intel_update_fbc(crtc, &crtc->mode);
1476
1477         intel_wait_for_vblank(dev);
1478         intel_increase_pllclock(crtc, true);
1479
1480         return 0;
1481 }
1482
1483 static int
1484 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1485                     struct drm_framebuffer *old_fb)
1486 {
1487         struct drm_device *dev = crtc->dev;
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         struct drm_i915_master_private *master_priv;
1490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491         struct intel_framebuffer *intel_fb;
1492         struct drm_i915_gem_object *obj_priv;
1493         struct drm_gem_object *obj;
1494         int pipe = intel_crtc->pipe;
1495         int plane = intel_crtc->plane;
1496         unsigned long Start, Offset;
1497         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1498         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1499         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1500         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1501         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1502         u32 dspcntr;
1503         int ret;
1504
1505         /* no fb bound */
1506         if (!crtc->fb) {
1507                 DRM_DEBUG_KMS("No FB bound\n");
1508                 return 0;
1509         }
1510
1511         switch (plane) {
1512         case 0:
1513         case 1:
1514                 break;
1515         default:
1516                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1517                 return -EINVAL;
1518         }
1519
1520         intel_fb = to_intel_framebuffer(crtc->fb);
1521         obj = intel_fb->obj;
1522         obj_priv = to_intel_bo(obj);
1523
1524         mutex_lock(&dev->struct_mutex);
1525         ret = intel_pin_and_fence_fb_obj(dev, obj);
1526         if (ret != 0) {
1527                 mutex_unlock(&dev->struct_mutex);
1528                 return ret;
1529         }
1530
1531         ret = i915_gem_object_set_to_display_plane(obj);
1532         if (ret != 0) {
1533                 i915_gem_object_unpin(obj);
1534                 mutex_unlock(&dev->struct_mutex);
1535                 return ret;
1536         }
1537
1538         dspcntr = I915_READ(dspcntr_reg);
1539         /* Mask out pixel format bits in case we change it */
1540         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1541         switch (crtc->fb->bits_per_pixel) {
1542         case 8:
1543                 dspcntr |= DISPPLANE_8BPP;
1544                 break;
1545         case 16:
1546                 if (crtc->fb->depth == 15)
1547                         dspcntr |= DISPPLANE_15_16BPP;
1548                 else
1549                         dspcntr |= DISPPLANE_16BPP;
1550                 break;
1551         case 24:
1552         case 32:
1553                 if (crtc->fb->depth == 30)
1554                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1555                 else
1556                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1557                 break;
1558         default:
1559                 DRM_ERROR("Unknown color depth\n");
1560                 i915_gem_object_unpin(obj);
1561                 mutex_unlock(&dev->struct_mutex);
1562                 return -EINVAL;
1563         }
1564         if (IS_I965G(dev)) {
1565                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1566                         dspcntr |= DISPPLANE_TILED;
1567                 else
1568                         dspcntr &= ~DISPPLANE_TILED;
1569         }
1570
1571         if (HAS_PCH_SPLIT(dev))
1572                 /* must disable */
1573                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1574
1575         I915_WRITE(dspcntr_reg, dspcntr);
1576
1577         Start = obj_priv->gtt_offset;
1578         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1579
1580         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1581                       Start, Offset, x, y, crtc->fb->pitch);
1582         I915_WRITE(dspstride, crtc->fb->pitch);
1583         if (IS_I965G(dev)) {
1584                 I915_WRITE(dspsurf, Start);
1585                 I915_WRITE(dsptileoff, (y << 16) | x);
1586                 I915_WRITE(dspbase, Offset);
1587         } else {
1588                 I915_WRITE(dspbase, Start + Offset);
1589         }
1590         POSTING_READ(dspbase);
1591
1592         if ((IS_I965G(dev) || plane == 0))
1593                 intel_update_fbc(crtc, &crtc->mode);
1594
1595         intel_wait_for_vblank(dev);
1596
1597         if (old_fb) {
1598                 intel_fb = to_intel_framebuffer(old_fb);
1599                 obj_priv = to_intel_bo(intel_fb->obj);
1600                 i915_gem_object_unpin(intel_fb->obj);
1601         }
1602         intel_increase_pllclock(crtc, true);
1603
1604         mutex_unlock(&dev->struct_mutex);
1605
1606         if (!dev->primary->master)
1607                 return 0;
1608
1609         master_priv = dev->primary->master->driver_priv;
1610         if (!master_priv->sarea_priv)
1611                 return 0;
1612
1613         if (pipe) {
1614                 master_priv->sarea_priv->pipeB_x = x;
1615                 master_priv->sarea_priv->pipeB_y = y;
1616         } else {
1617                 master_priv->sarea_priv->pipeA_x = x;
1618                 master_priv->sarea_priv->pipeA_y = y;
1619         }
1620
1621         return 0;
1622 }
1623
1624 /* Disable the VGA plane that we never use */
1625 static void i915_disable_vga (struct drm_device *dev)
1626 {
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         u8 sr1;
1629         u32 vga_reg;
1630
1631         if (HAS_PCH_SPLIT(dev))
1632                 vga_reg = CPU_VGACNTRL;
1633         else
1634                 vga_reg = VGACNTRL;
1635
1636         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1637                 return;
1638
1639         I915_WRITE8(VGA_SR_INDEX, 1);
1640         sr1 = I915_READ8(VGA_SR_DATA);
1641         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1642         udelay(100);
1643
1644         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1645 }
1646
1647 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1648 {
1649         struct drm_device *dev = crtc->dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651         u32 dpa_ctl;
1652
1653         DRM_DEBUG_KMS("\n");
1654         dpa_ctl = I915_READ(DP_A);
1655         dpa_ctl &= ~DP_PLL_ENABLE;
1656         I915_WRITE(DP_A, dpa_ctl);
1657 }
1658
1659 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1660 {
1661         struct drm_device *dev = crtc->dev;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663         u32 dpa_ctl;
1664
1665         dpa_ctl = I915_READ(DP_A);
1666         dpa_ctl |= DP_PLL_ENABLE;
1667         I915_WRITE(DP_A, dpa_ctl);
1668         POSTING_READ(DP_A);
1669         udelay(200);
1670 }
1671
1672
1673 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1674 {
1675         struct drm_device *dev = crtc->dev;
1676         struct drm_i915_private *dev_priv = dev->dev_private;
1677         u32 dpa_ctl;
1678
1679         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1680         dpa_ctl = I915_READ(DP_A);
1681         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1682
1683         if (clock < 200000) {
1684                 u32 temp;
1685                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1686                 /* workaround for 160Mhz:
1687                    1) program 0x4600c bits 15:0 = 0x8124
1688                    2) program 0x46010 bit 0 = 1
1689                    3) program 0x46034 bit 24 = 1
1690                    4) program 0x64000 bit 14 = 1
1691                    */
1692                 temp = I915_READ(0x4600c);
1693                 temp &= 0xffff0000;
1694                 I915_WRITE(0x4600c, temp | 0x8124);
1695
1696                 temp = I915_READ(0x46010);
1697                 I915_WRITE(0x46010, temp | 1);
1698
1699                 temp = I915_READ(0x46034);
1700                 I915_WRITE(0x46034, temp | (1 << 24));
1701         } else {
1702                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1703         }
1704         I915_WRITE(DP_A, dpa_ctl);
1705
1706         udelay(500);
1707 }
1708
1709 /* The FDI link training functions for ILK/Ibexpeak. */
1710 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1711 {
1712         struct drm_device *dev = crtc->dev;
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1715         int pipe = intel_crtc->pipe;
1716         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1717         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1718         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1719         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1720         u32 temp, tries = 0;
1721
1722         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1723            for train result */
1724         temp = I915_READ(fdi_rx_imr_reg);
1725         temp &= ~FDI_RX_SYMBOL_LOCK;
1726         temp &= ~FDI_RX_BIT_LOCK;
1727         I915_WRITE(fdi_rx_imr_reg, temp);
1728         I915_READ(fdi_rx_imr_reg);
1729         udelay(150);
1730
1731         /* enable CPU FDI TX and PCH FDI RX */
1732         temp = I915_READ(fdi_tx_reg);
1733         temp |= FDI_TX_ENABLE;
1734         temp &= ~(7 << 19);
1735         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1736         temp &= ~FDI_LINK_TRAIN_NONE;
1737         temp |= FDI_LINK_TRAIN_PATTERN_1;
1738         I915_WRITE(fdi_tx_reg, temp);
1739         I915_READ(fdi_tx_reg);
1740
1741         temp = I915_READ(fdi_rx_reg);
1742         temp &= ~FDI_LINK_TRAIN_NONE;
1743         temp |= FDI_LINK_TRAIN_PATTERN_1;
1744         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1745         I915_READ(fdi_rx_reg);
1746         udelay(150);
1747
1748         for (tries = 0; tries < 5; tries++) {
1749                 temp = I915_READ(fdi_rx_iir_reg);
1750                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1751
1752                 if ((temp & FDI_RX_BIT_LOCK)) {
1753                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1754                         I915_WRITE(fdi_rx_iir_reg,
1755                                    temp | FDI_RX_BIT_LOCK);
1756                         break;
1757                 }
1758         }
1759         if (tries == 5)
1760                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1761
1762         /* Train 2 */
1763         temp = I915_READ(fdi_tx_reg);
1764         temp &= ~FDI_LINK_TRAIN_NONE;
1765         temp |= FDI_LINK_TRAIN_PATTERN_2;
1766         I915_WRITE(fdi_tx_reg, temp);
1767
1768         temp = I915_READ(fdi_rx_reg);
1769         temp &= ~FDI_LINK_TRAIN_NONE;
1770         temp |= FDI_LINK_TRAIN_PATTERN_2;
1771         I915_WRITE(fdi_rx_reg, temp);
1772         udelay(150);
1773
1774         tries = 0;
1775
1776         for (tries = 0; tries < 5; tries++) {
1777                 temp = I915_READ(fdi_rx_iir_reg);
1778                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1779
1780                 if (temp & FDI_RX_SYMBOL_LOCK) {
1781                         I915_WRITE(fdi_rx_iir_reg,
1782                                    temp | FDI_RX_SYMBOL_LOCK);
1783                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1784                         break;
1785                 }
1786         }
1787         if (tries == 5)
1788                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1789
1790         DRM_DEBUG_KMS("FDI train done\n");
1791 }
1792
1793 static int snb_b_fdi_train_param [] = {
1794         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1795         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1796         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1797         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1798 };
1799
1800 /* The FDI link training functions for SNB/Cougarpoint. */
1801 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1802 {
1803         struct drm_device *dev = crtc->dev;
1804         struct drm_i915_private *dev_priv = dev->dev_private;
1805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806         int pipe = intel_crtc->pipe;
1807         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1808         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1809         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1810         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1811         u32 temp, i;
1812
1813         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1814            for train result */
1815         temp = I915_READ(fdi_rx_imr_reg);
1816         temp &= ~FDI_RX_SYMBOL_LOCK;
1817         temp &= ~FDI_RX_BIT_LOCK;
1818         I915_WRITE(fdi_rx_imr_reg, temp);
1819         I915_READ(fdi_rx_imr_reg);
1820         udelay(150);
1821
1822         /* enable CPU FDI TX and PCH FDI RX */
1823         temp = I915_READ(fdi_tx_reg);
1824         temp |= FDI_TX_ENABLE;
1825         temp &= ~(7 << 19);
1826         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1827         temp &= ~FDI_LINK_TRAIN_NONE;
1828         temp |= FDI_LINK_TRAIN_PATTERN_1;
1829         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1830         /* SNB-B */
1831         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1832         I915_WRITE(fdi_tx_reg, temp);
1833         I915_READ(fdi_tx_reg);
1834
1835         temp = I915_READ(fdi_rx_reg);
1836         if (HAS_PCH_CPT(dev)) {
1837                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1838                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1839         } else {
1840                 temp &= ~FDI_LINK_TRAIN_NONE;
1841                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1842         }
1843         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1844         I915_READ(fdi_rx_reg);
1845         udelay(150);
1846
1847         for (i = 0; i < 4; i++ ) {
1848                 temp = I915_READ(fdi_tx_reg);
1849                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850                 temp |= snb_b_fdi_train_param[i];
1851                 I915_WRITE(fdi_tx_reg, temp);
1852                 udelay(500);
1853
1854                 temp = I915_READ(fdi_rx_iir_reg);
1855                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1856
1857                 if (temp & FDI_RX_BIT_LOCK) {
1858                         I915_WRITE(fdi_rx_iir_reg,
1859                                    temp | FDI_RX_BIT_LOCK);
1860                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1861                         break;
1862                 }
1863         }
1864         if (i == 4)
1865                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1866
1867         /* Train 2 */
1868         temp = I915_READ(fdi_tx_reg);
1869         temp &= ~FDI_LINK_TRAIN_NONE;
1870         temp |= FDI_LINK_TRAIN_PATTERN_2;
1871         if (IS_GEN6(dev)) {
1872                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1873                 /* SNB-B */
1874                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1875         }
1876         I915_WRITE(fdi_tx_reg, temp);
1877
1878         temp = I915_READ(fdi_rx_reg);
1879         if (HAS_PCH_CPT(dev)) {
1880                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1881                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1882         } else {
1883                 temp &= ~FDI_LINK_TRAIN_NONE;
1884                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1885         }
1886         I915_WRITE(fdi_rx_reg, temp);
1887         udelay(150);
1888
1889         for (i = 0; i < 4; i++ ) {
1890                 temp = I915_READ(fdi_tx_reg);
1891                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1892                 temp |= snb_b_fdi_train_param[i];
1893                 I915_WRITE(fdi_tx_reg, temp);
1894                 udelay(500);
1895
1896                 temp = I915_READ(fdi_rx_iir_reg);
1897                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1898
1899                 if (temp & FDI_RX_SYMBOL_LOCK) {
1900                         I915_WRITE(fdi_rx_iir_reg,
1901                                    temp | FDI_RX_SYMBOL_LOCK);
1902                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1903                         break;
1904                 }
1905         }
1906         if (i == 4)
1907                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1908
1909         DRM_DEBUG_KMS("FDI train done.\n");
1910 }
1911
1912 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1913 {
1914         struct drm_device *dev = crtc->dev;
1915         struct drm_i915_private *dev_priv = dev->dev_private;
1916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1917         int pipe = intel_crtc->pipe;
1918         int plane = intel_crtc->plane;
1919         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1920         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1921         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1922         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1923         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1924         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1925         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1926         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1927         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1928         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1929         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1930         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1931         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1932         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1933         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1934         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1935         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1936         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1937         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1938         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1939         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1940         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1941         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1942         u32 temp;
1943         u32 pipe_bpc;
1944
1945         temp = I915_READ(pipeconf_reg);
1946         pipe_bpc = temp & PIPE_BPC_MASK;
1947
1948         /* XXX: When our outputs are all unaware of DPMS modes other than off
1949          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1950          */
1951         switch (mode) {
1952         case DRM_MODE_DPMS_ON:
1953         case DRM_MODE_DPMS_STANDBY:
1954         case DRM_MODE_DPMS_SUSPEND:
1955                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1956
1957                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1958                         temp = I915_READ(PCH_LVDS);
1959                         if ((temp & LVDS_PORT_EN) == 0) {
1960                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1961                                 POSTING_READ(PCH_LVDS);
1962                         }
1963                 }
1964
1965                 if (HAS_eDP) {
1966                         /* enable eDP PLL */
1967                         ironlake_enable_pll_edp(crtc);
1968                 } else {
1969
1970                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1971                         temp = I915_READ(fdi_rx_reg);
1972                         /*
1973                          * make the BPC in FDI Rx be consistent with that in
1974                          * pipeconf reg.
1975                          */
1976                         temp &= ~(0x7 << 16);
1977                         temp |= (pipe_bpc << 11);
1978                         temp &= ~(7 << 19);
1979                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1980                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1981                         I915_READ(fdi_rx_reg);
1982                         udelay(200);
1983
1984                         /* Switch from Rawclk to PCDclk */
1985                         temp = I915_READ(fdi_rx_reg);
1986                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1987                         I915_READ(fdi_rx_reg);
1988                         udelay(200);
1989
1990                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1991                         temp = I915_READ(fdi_tx_reg);
1992                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1993                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1994                                 I915_READ(fdi_tx_reg);
1995                                 udelay(100);
1996                         }
1997                 }
1998
1999                 /* Enable panel fitting for LVDS */
2000                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2001                     || HAS_eDP || intel_pch_has_edp(crtc)) {
2002                         if (dev_priv->pch_pf_size) {
2003                                 temp = I915_READ(pf_ctl_reg);
2004                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2005                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2006                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2007                         } else
2008                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2009                 }
2010
2011                 /* Enable CPU pipe */
2012                 temp = I915_READ(pipeconf_reg);
2013                 if ((temp & PIPEACONF_ENABLE) == 0) {
2014                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2015                         I915_READ(pipeconf_reg);
2016                         udelay(100);
2017                 }
2018
2019                 /* configure and enable CPU plane */
2020                 temp = I915_READ(dspcntr_reg);
2021                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2022                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2023                         /* Flush the plane changes */
2024                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2025                 }
2026
2027                 if (!HAS_eDP) {
2028                         /* For PCH output, training FDI link */
2029                         if (IS_GEN6(dev))
2030                                 gen6_fdi_link_train(crtc);
2031                         else
2032                                 ironlake_fdi_link_train(crtc);
2033
2034                         /* enable PCH DPLL */
2035                         temp = I915_READ(pch_dpll_reg);
2036                         if ((temp & DPLL_VCO_ENABLE) == 0) {
2037                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2038                                 I915_READ(pch_dpll_reg);
2039                         }
2040                         udelay(200);
2041
2042                         if (HAS_PCH_CPT(dev)) {
2043                                 /* Be sure PCH DPLL SEL is set */
2044                                 temp = I915_READ(PCH_DPLL_SEL);
2045                                 if (trans_dpll_sel == 0 &&
2046                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2047                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2048                                 else if (trans_dpll_sel == 1 &&
2049                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2050                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2051                                 I915_WRITE(PCH_DPLL_SEL, temp);
2052                                 I915_READ(PCH_DPLL_SEL);
2053                         }
2054
2055                         /* set transcoder timing */
2056                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2057                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2058                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2059
2060                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2061                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2062                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2063
2064                         /* enable normal train */
2065                         temp = I915_READ(fdi_tx_reg);
2066                         temp &= ~FDI_LINK_TRAIN_NONE;
2067                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2068                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2069                         I915_READ(fdi_tx_reg);
2070
2071                         temp = I915_READ(fdi_rx_reg);
2072                         if (HAS_PCH_CPT(dev)) {
2073                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2074                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2075                         } else {
2076                                 temp &= ~FDI_LINK_TRAIN_NONE;
2077                                 temp |= FDI_LINK_TRAIN_NONE;
2078                         }
2079                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2080                         I915_READ(fdi_rx_reg);
2081
2082                         /* wait one idle pattern time */
2083                         udelay(100);
2084
2085                         /* For PCH DP, enable TRANS_DP_CTL */
2086                         if (HAS_PCH_CPT(dev) &&
2087                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2088                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2089                                 int reg;
2090
2091                                 reg = I915_READ(trans_dp_ctl);
2092                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2093                                          TRANS_DP_SYNC_MASK);
2094                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2095                                         TRANS_DP_ENH_FRAMING);
2096
2097                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2098                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2099                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2100                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2101
2102                                 switch (intel_trans_dp_port_sel(crtc)) {
2103                                 case PCH_DP_B:
2104                                         reg |= TRANS_DP_PORT_SEL_B;
2105                                         break;
2106                                 case PCH_DP_C:
2107                                         reg |= TRANS_DP_PORT_SEL_C;
2108                                         break;
2109                                 case PCH_DP_D:
2110                                         reg |= TRANS_DP_PORT_SEL_D;
2111                                         break;
2112                                 default:
2113                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2114                                         reg |= TRANS_DP_PORT_SEL_B;
2115                                         break;
2116                                 }
2117
2118                                 I915_WRITE(trans_dp_ctl, reg);
2119                                 POSTING_READ(trans_dp_ctl);
2120                         }
2121
2122                         /* enable PCH transcoder */
2123                         temp = I915_READ(transconf_reg);
2124                         /*
2125                          * make the BPC in transcoder be consistent with
2126                          * that in pipeconf reg.
2127                          */
2128                         temp &= ~PIPE_BPC_MASK;
2129                         temp |= pipe_bpc;
2130                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2131                         I915_READ(transconf_reg);
2132
2133                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2134                                 DRM_ERROR("failed to enable transcoder\n");
2135                 }
2136
2137                 intel_crtc_load_lut(crtc);
2138
2139                 intel_update_fbc(crtc, &crtc->mode);
2140                 break;
2141
2142         case DRM_MODE_DPMS_OFF:
2143                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2144
2145                 drm_vblank_off(dev, pipe);
2146                 /* Disable display plane */
2147                 temp = I915_READ(dspcntr_reg);
2148                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2149                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2150                         /* Flush the plane changes */
2151                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2152                         I915_READ(dspbase_reg);
2153                 }
2154
2155                 if (dev_priv->cfb_plane == plane &&
2156                     dev_priv->display.disable_fbc)
2157                         dev_priv->display.disable_fbc(dev);
2158
2159                 i915_disable_vga(dev);
2160
2161                 /* disable cpu pipe, disable after all planes disabled */
2162                 temp = I915_READ(pipeconf_reg);
2163                 if ((temp & PIPEACONF_ENABLE) != 0) {
2164                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2165
2166                         /* wait for cpu pipe off, pipe state */
2167                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2168                                 DRM_ERROR("failed to turn off cpu pipe\n");
2169                 } else
2170                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2171
2172                 udelay(100);
2173
2174                 /* Disable PF */
2175                 temp = I915_READ(pf_ctl_reg);
2176                 if ((temp & PF_ENABLE) != 0) {
2177                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2178                         I915_READ(pf_ctl_reg);
2179                 }
2180                 I915_WRITE(pf_win_size, 0);
2181                 POSTING_READ(pf_win_size);
2182
2183
2184                 /* disable CPU FDI tx and PCH FDI rx */
2185                 temp = I915_READ(fdi_tx_reg);
2186                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2187                 I915_READ(fdi_tx_reg);
2188
2189                 temp = I915_READ(fdi_rx_reg);
2190                 /* BPC in FDI rx is consistent with that in pipeconf */
2191                 temp &= ~(0x07 << 16);
2192                 temp |= (pipe_bpc << 11);
2193                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2194                 I915_READ(fdi_rx_reg);
2195
2196                 udelay(100);
2197
2198                 /* still set train pattern 1 */
2199                 temp = I915_READ(fdi_tx_reg);
2200                 temp &= ~FDI_LINK_TRAIN_NONE;
2201                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2202                 I915_WRITE(fdi_tx_reg, temp);
2203                 POSTING_READ(fdi_tx_reg);
2204
2205                 temp = I915_READ(fdi_rx_reg);
2206                 if (HAS_PCH_CPT(dev)) {
2207                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2208                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2209                 } else {
2210                         temp &= ~FDI_LINK_TRAIN_NONE;
2211                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2212                 }
2213                 I915_WRITE(fdi_rx_reg, temp);
2214                 POSTING_READ(fdi_rx_reg);
2215
2216                 udelay(100);
2217
2218                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2219                         temp = I915_READ(PCH_LVDS);
2220                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2221                         I915_READ(PCH_LVDS);
2222                         udelay(100);
2223                 }
2224
2225                 /* disable PCH transcoder */
2226                 temp = I915_READ(transconf_reg);
2227                 if ((temp & TRANS_ENABLE) != 0) {
2228                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2229
2230                         /* wait for PCH transcoder off, transcoder state */
2231                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2232                                 DRM_ERROR("failed to disable transcoder\n");
2233                 }
2234
2235                 temp = I915_READ(transconf_reg);
2236                 /* BPC in transcoder is consistent with that in pipeconf */
2237                 temp &= ~PIPE_BPC_MASK;
2238                 temp |= pipe_bpc;
2239                 I915_WRITE(transconf_reg, temp);
2240                 I915_READ(transconf_reg);
2241                 udelay(100);
2242
2243                 if (HAS_PCH_CPT(dev)) {
2244                         /* disable TRANS_DP_CTL */
2245                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2246                         int reg;
2247
2248                         reg = I915_READ(trans_dp_ctl);
2249                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2250                         I915_WRITE(trans_dp_ctl, reg);
2251                         POSTING_READ(trans_dp_ctl);
2252
2253                         /* disable DPLL_SEL */
2254                         temp = I915_READ(PCH_DPLL_SEL);
2255                         if (trans_dpll_sel == 0)
2256                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2257                         else
2258                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2259                         I915_WRITE(PCH_DPLL_SEL, temp);
2260                         I915_READ(PCH_DPLL_SEL);
2261
2262                 }
2263
2264                 /* disable PCH DPLL */
2265                 temp = I915_READ(pch_dpll_reg);
2266                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2267                 I915_READ(pch_dpll_reg);
2268
2269                 if (HAS_eDP) {
2270                         ironlake_disable_pll_edp(crtc);
2271                 }
2272
2273                 /* Switch from PCDclk to Rawclk */
2274                 temp = I915_READ(fdi_rx_reg);
2275                 temp &= ~FDI_SEL_PCDCLK;
2276                 I915_WRITE(fdi_rx_reg, temp);
2277                 I915_READ(fdi_rx_reg);
2278
2279                 /* Disable CPU FDI TX PLL */
2280                 temp = I915_READ(fdi_tx_reg);
2281                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2282                 I915_READ(fdi_tx_reg);
2283                 udelay(100);
2284
2285                 temp = I915_READ(fdi_rx_reg);
2286                 temp &= ~FDI_RX_PLL_ENABLE;
2287                 I915_WRITE(fdi_rx_reg, temp);
2288                 I915_READ(fdi_rx_reg);
2289
2290                 /* Wait for the clocks to turn off. */
2291                 udelay(100);
2292                 break;
2293         }
2294 }
2295
2296 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2297 {
2298         struct intel_overlay *overlay;
2299         int ret;
2300
2301         if (!enable && intel_crtc->overlay) {
2302                 overlay = intel_crtc->overlay;
2303                 mutex_lock(&overlay->dev->struct_mutex);
2304                 for (;;) {
2305                         ret = intel_overlay_switch_off(overlay);
2306                         if (ret == 0)
2307                                 break;
2308
2309                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2310                         if (ret != 0) {
2311                                 /* overlay doesn't react anymore. Usually
2312                                  * results in a black screen and an unkillable
2313                                  * X server. */
2314                                 BUG();
2315                                 overlay->hw_wedged = HW_WEDGED;
2316                                 break;
2317                         }
2318                 }
2319                 mutex_unlock(&overlay->dev->struct_mutex);
2320         }
2321         /* Let userspace switch the overlay on again. In most cases userspace
2322          * has to recompute where to put it anyway. */
2323
2324         return;
2325 }
2326
2327 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2328 {
2329         struct drm_device *dev = crtc->dev;
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332         int pipe = intel_crtc->pipe;
2333         int plane = intel_crtc->plane;
2334         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2335         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2336         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2337         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2338         u32 temp;
2339
2340         /* XXX: When our outputs are all unaware of DPMS modes other than off
2341          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2342          */
2343         switch (mode) {
2344         case DRM_MODE_DPMS_ON:
2345         case DRM_MODE_DPMS_STANDBY:
2346         case DRM_MODE_DPMS_SUSPEND:
2347                 /* Enable the DPLL */
2348                 temp = I915_READ(dpll_reg);
2349                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2350                         I915_WRITE(dpll_reg, temp);
2351                         I915_READ(dpll_reg);
2352                         /* Wait for the clocks to stabilize. */
2353                         udelay(150);
2354                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2355                         I915_READ(dpll_reg);
2356                         /* Wait for the clocks to stabilize. */
2357                         udelay(150);
2358                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2359                         I915_READ(dpll_reg);
2360                         /* Wait for the clocks to stabilize. */
2361                         udelay(150);
2362                 }
2363
2364                 /* Enable the pipe */
2365                 temp = I915_READ(pipeconf_reg);
2366                 if ((temp & PIPEACONF_ENABLE) == 0)
2367                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2368
2369                 /* Enable the plane */
2370                 temp = I915_READ(dspcntr_reg);
2371                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2372                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2373                         /* Flush the plane changes */
2374                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2375                 }
2376
2377                 intel_crtc_load_lut(crtc);
2378
2379                 if ((IS_I965G(dev) || plane == 0))
2380                         intel_update_fbc(crtc, &crtc->mode);
2381
2382                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2383                 intel_crtc_dpms_overlay(intel_crtc, true);
2384         break;
2385         case DRM_MODE_DPMS_OFF:
2386                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2387                 intel_crtc_dpms_overlay(intel_crtc, false);
2388                 drm_vblank_off(dev, pipe);
2389
2390                 if (dev_priv->cfb_plane == plane &&
2391                     dev_priv->display.disable_fbc)
2392                         dev_priv->display.disable_fbc(dev);
2393
2394                 /* Disable the VGA plane that we never use */
2395                 i915_disable_vga(dev);
2396
2397                 /* Disable display plane */
2398                 temp = I915_READ(dspcntr_reg);
2399                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2400                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2401                         /* Flush the plane changes */
2402                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2403                         I915_READ(dspbase_reg);
2404                 }
2405
2406                 if (!IS_I9XX(dev)) {
2407                         /* Wait for vblank for the disable to take effect */
2408                         intel_wait_for_vblank(dev);
2409                 }
2410
2411                 /* Don't disable pipe A or pipe A PLLs if needed */
2412                 if (pipeconf_reg == PIPEACONF &&
2413                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2414                         goto skip_pipe_off;
2415
2416                 /* Next, disable display pipes */
2417                 temp = I915_READ(pipeconf_reg);
2418                 if ((temp & PIPEACONF_ENABLE) != 0) {
2419                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2420                         I915_READ(pipeconf_reg);
2421                 }
2422
2423                 /* Wait for vblank for the disable to take effect. */
2424                 intel_wait_for_vblank(dev);
2425
2426                 temp = I915_READ(dpll_reg);
2427                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2428                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2429                         I915_READ(dpll_reg);
2430                 }
2431         skip_pipe_off:
2432                 /* Wait for the clocks to turn off. */
2433                 udelay(150);
2434                 break;
2435         }
2436 }
2437
2438 /**
2439  * Sets the power management mode of the pipe and plane.
2440  */
2441 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2442 {
2443         struct drm_device *dev = crtc->dev;
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         struct drm_i915_master_private *master_priv;
2446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447         int pipe = intel_crtc->pipe;
2448         bool enabled;
2449
2450         intel_crtc->dpms_mode = mode;
2451         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2452
2453         /* When switching on the display, ensure that SR is disabled
2454          * with multiple pipes prior to enabling to new pipe.
2455          *
2456          * When switching off the display, make sure the cursor is
2457          * properly hidden prior to disabling the pipe.
2458          */
2459         if (mode == DRM_MODE_DPMS_ON)
2460                 intel_update_watermarks(dev);
2461         else
2462                 intel_crtc_update_cursor(crtc);
2463
2464         dev_priv->display.dpms(crtc, mode);
2465
2466         if (mode == DRM_MODE_DPMS_ON)
2467                 intel_crtc_update_cursor(crtc);
2468         else
2469                 intel_update_watermarks(dev);
2470
2471         if (!dev->primary->master)
2472                 return;
2473
2474         master_priv = dev->primary->master->driver_priv;
2475         if (!master_priv->sarea_priv)
2476                 return;
2477
2478         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2479
2480         switch (pipe) {
2481         case 0:
2482                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2483                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2484                 break;
2485         case 1:
2486                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2487                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2488                 break;
2489         default:
2490                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2491                 break;
2492         }
2493 }
2494
2495 static void intel_crtc_prepare (struct drm_crtc *crtc)
2496 {
2497         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2498         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2499 }
2500
2501 static void intel_crtc_commit (struct drm_crtc *crtc)
2502 {
2503         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2504         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2505 }
2506
2507 void intel_encoder_prepare (struct drm_encoder *encoder)
2508 {
2509         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2510         /* lvds has its own version of prepare see intel_lvds_prepare */
2511         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2512 }
2513
2514 void intel_encoder_commit (struct drm_encoder *encoder)
2515 {
2516         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2517         /* lvds has its own version of commit see intel_lvds_commit */
2518         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2519 }
2520
2521 void intel_encoder_destroy(struct drm_encoder *encoder)
2522 {
2523         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2524
2525         if (intel_encoder->ddc_bus)
2526                 intel_i2c_destroy(intel_encoder->ddc_bus);
2527
2528         if (intel_encoder->i2c_bus)
2529                 intel_i2c_destroy(intel_encoder->i2c_bus);
2530
2531         drm_encoder_cleanup(encoder);
2532         kfree(intel_encoder);
2533 }
2534
2535 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2536                                   struct drm_display_mode *mode,
2537                                   struct drm_display_mode *adjusted_mode)
2538 {
2539         struct drm_device *dev = crtc->dev;
2540         if (HAS_PCH_SPLIT(dev)) {
2541                 /* FDI link clock is fixed at 2.7G */
2542                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2543                         return false;
2544         }
2545         return true;
2546 }
2547
2548 static int i945_get_display_clock_speed(struct drm_device *dev)
2549 {
2550         return 400000;
2551 }
2552
2553 static int i915_get_display_clock_speed(struct drm_device *dev)
2554 {
2555         return 333000;
2556 }
2557
2558 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2559 {
2560         return 200000;
2561 }
2562
2563 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2564 {
2565         u16 gcfgc = 0;
2566
2567         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2568
2569         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2570                 return 133000;
2571         else {
2572                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2573                 case GC_DISPLAY_CLOCK_333_MHZ:
2574                         return 333000;
2575                 default:
2576                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2577                         return 190000;
2578                 }
2579         }
2580 }
2581
2582 static int i865_get_display_clock_speed(struct drm_device *dev)
2583 {
2584         return 266000;
2585 }
2586
2587 static int i855_get_display_clock_speed(struct drm_device *dev)
2588 {
2589         u16 hpllcc = 0;
2590         /* Assume that the hardware is in the high speed state.  This
2591          * should be the default.
2592          */
2593         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2594         case GC_CLOCK_133_200:
2595         case GC_CLOCK_100_200:
2596                 return 200000;
2597         case GC_CLOCK_166_250:
2598                 return 250000;
2599         case GC_CLOCK_100_133:
2600                 return 133000;
2601         }
2602
2603         /* Shouldn't happen */
2604         return 0;
2605 }
2606
2607 static int i830_get_display_clock_speed(struct drm_device *dev)
2608 {
2609         return 133000;
2610 }
2611
2612 /**
2613  * Return the pipe currently connected to the panel fitter,
2614  * or -1 if the panel fitter is not present or not in use
2615  */
2616 int intel_panel_fitter_pipe (struct drm_device *dev)
2617 {
2618         struct drm_i915_private *dev_priv = dev->dev_private;
2619         u32  pfit_control;
2620
2621         /* i830 doesn't have a panel fitter */
2622         if (IS_I830(dev))
2623                 return -1;
2624
2625         pfit_control = I915_READ(PFIT_CONTROL);
2626
2627         /* See if the panel fitter is in use */
2628         if ((pfit_control & PFIT_ENABLE) == 0)
2629                 return -1;
2630
2631         /* 965 can place panel fitter on either pipe */
2632         if (IS_I965G(dev))
2633                 return (pfit_control >> 29) & 0x3;
2634
2635         /* older chips can only use pipe 1 */
2636         return 1;
2637 }
2638
2639 struct fdi_m_n {
2640         u32        tu;
2641         u32        gmch_m;
2642         u32        gmch_n;
2643         u32        link_m;
2644         u32        link_n;
2645 };
2646
2647 static void
2648 fdi_reduce_ratio(u32 *num, u32 *den)
2649 {
2650         while (*num > 0xffffff || *den > 0xffffff) {
2651                 *num >>= 1;
2652                 *den >>= 1;
2653         }
2654 }
2655
2656 #define DATA_N 0x800000
2657 #define LINK_N 0x80000
2658
2659 static void
2660 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2661                      int link_clock, struct fdi_m_n *m_n)
2662 {
2663         u64 temp;
2664
2665         m_n->tu = 64; /* default size */
2666
2667         temp = (u64) DATA_N * pixel_clock;
2668         temp = div_u64(temp, link_clock);
2669         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2670         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2671         m_n->gmch_n = DATA_N;
2672         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2673
2674         temp = (u64) LINK_N * pixel_clock;
2675         m_n->link_m = div_u64(temp, link_clock);
2676         m_n->link_n = LINK_N;
2677         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2678 }
2679
2680
2681 struct intel_watermark_params {
2682         unsigned long fifo_size;
2683         unsigned long max_wm;
2684         unsigned long default_wm;
2685         unsigned long guard_size;
2686         unsigned long cacheline_size;
2687 };
2688
2689 /* Pineview has different values for various configs */
2690 static struct intel_watermark_params pineview_display_wm = {
2691         PINEVIEW_DISPLAY_FIFO,
2692         PINEVIEW_MAX_WM,
2693         PINEVIEW_DFT_WM,
2694         PINEVIEW_GUARD_WM,
2695         PINEVIEW_FIFO_LINE_SIZE
2696 };
2697 static struct intel_watermark_params pineview_display_hplloff_wm = {
2698         PINEVIEW_DISPLAY_FIFO,
2699         PINEVIEW_MAX_WM,
2700         PINEVIEW_DFT_HPLLOFF_WM,
2701         PINEVIEW_GUARD_WM,
2702         PINEVIEW_FIFO_LINE_SIZE
2703 };
2704 static struct intel_watermark_params pineview_cursor_wm = {
2705         PINEVIEW_CURSOR_FIFO,
2706         PINEVIEW_CURSOR_MAX_WM,
2707         PINEVIEW_CURSOR_DFT_WM,
2708         PINEVIEW_CURSOR_GUARD_WM,
2709         PINEVIEW_FIFO_LINE_SIZE,
2710 };
2711 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2712         PINEVIEW_CURSOR_FIFO,
2713         PINEVIEW_CURSOR_MAX_WM,
2714         PINEVIEW_CURSOR_DFT_WM,
2715         PINEVIEW_CURSOR_GUARD_WM,
2716         PINEVIEW_FIFO_LINE_SIZE
2717 };
2718 static struct intel_watermark_params g4x_wm_info = {
2719         G4X_FIFO_SIZE,
2720         G4X_MAX_WM,
2721         G4X_MAX_WM,
2722         2,
2723         G4X_FIFO_LINE_SIZE,
2724 };
2725 static struct intel_watermark_params g4x_cursor_wm_info = {
2726         I965_CURSOR_FIFO,
2727         I965_CURSOR_MAX_WM,
2728         I965_CURSOR_DFT_WM,
2729         2,
2730         G4X_FIFO_LINE_SIZE,
2731 };
2732 static struct intel_watermark_params i965_cursor_wm_info = {
2733         I965_CURSOR_FIFO,
2734         I965_CURSOR_MAX_WM,
2735         I965_CURSOR_DFT_WM,
2736         2,
2737         I915_FIFO_LINE_SIZE,
2738 };
2739 static struct intel_watermark_params i945_wm_info = {
2740         I945_FIFO_SIZE,
2741         I915_MAX_WM,
2742         1,
2743         2,
2744         I915_FIFO_LINE_SIZE
2745 };
2746 static struct intel_watermark_params i915_wm_info = {
2747         I915_FIFO_SIZE,
2748         I915_MAX_WM,
2749         1,
2750         2,
2751         I915_FIFO_LINE_SIZE
2752 };
2753 static struct intel_watermark_params i855_wm_info = {
2754         I855GM_FIFO_SIZE,
2755         I915_MAX_WM,
2756         1,
2757         2,
2758         I830_FIFO_LINE_SIZE
2759 };
2760 static struct intel_watermark_params i830_wm_info = {
2761         I830_FIFO_SIZE,
2762         I915_MAX_WM,
2763         1,
2764         2,
2765         I830_FIFO_LINE_SIZE
2766 };
2767
2768 static struct intel_watermark_params ironlake_display_wm_info = {
2769         ILK_DISPLAY_FIFO,
2770         ILK_DISPLAY_MAXWM,
2771         ILK_DISPLAY_DFTWM,
2772         2,
2773         ILK_FIFO_LINE_SIZE
2774 };
2775
2776 static struct intel_watermark_params ironlake_cursor_wm_info = {
2777         ILK_CURSOR_FIFO,
2778         ILK_CURSOR_MAXWM,
2779         ILK_CURSOR_DFTWM,
2780         2,
2781         ILK_FIFO_LINE_SIZE
2782 };
2783
2784 static struct intel_watermark_params ironlake_display_srwm_info = {
2785         ILK_DISPLAY_SR_FIFO,
2786         ILK_DISPLAY_MAX_SRWM,
2787         ILK_DISPLAY_DFT_SRWM,
2788         2,
2789         ILK_FIFO_LINE_SIZE
2790 };
2791
2792 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2793         ILK_CURSOR_SR_FIFO,
2794         ILK_CURSOR_MAX_SRWM,
2795         ILK_CURSOR_DFT_SRWM,
2796         2,
2797         ILK_FIFO_LINE_SIZE
2798 };
2799
2800 /**
2801  * intel_calculate_wm - calculate watermark level
2802  * @clock_in_khz: pixel clock
2803  * @wm: chip FIFO params
2804  * @pixel_size: display pixel size
2805  * @latency_ns: memory latency for the platform
2806  *
2807  * Calculate the watermark level (the level at which the display plane will
2808  * start fetching from memory again).  Each chip has a different display
2809  * FIFO size and allocation, so the caller needs to figure that out and pass
2810  * in the correct intel_watermark_params structure.
2811  *
2812  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2813  * on the pixel size.  When it reaches the watermark level, it'll start
2814  * fetching FIFO line sized based chunks from memory until the FIFO fills
2815  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2816  * will occur, and a display engine hang could result.
2817  */
2818 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2819                                         struct intel_watermark_params *wm,
2820                                         int pixel_size,
2821                                         unsigned long latency_ns)
2822 {
2823         long entries_required, wm_size;
2824
2825         /*
2826          * Note: we need to make sure we don't overflow for various clock &
2827          * latency values.
2828          * clocks go from a few thousand to several hundred thousand.
2829          * latency is usually a few thousand
2830          */
2831         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2832                 1000;
2833         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2834
2835         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2836
2837         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2838
2839         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2840
2841         /* Don't promote wm_size to unsigned... */
2842         if (wm_size > (long)wm->max_wm)
2843                 wm_size = wm->max_wm;
2844         if (wm_size <= 0) {
2845                 wm_size = wm->default_wm;
2846                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2847                           " entries required = %ld, available = %lu.\n",
2848                           entries_required + wm->guard_size,
2849                           wm->fifo_size);
2850         }
2851
2852         return wm_size;
2853 }
2854
2855 struct cxsr_latency {
2856         int is_desktop;
2857         int is_ddr3;
2858         unsigned long fsb_freq;
2859         unsigned long mem_freq;
2860         unsigned long display_sr;
2861         unsigned long display_hpll_disable;
2862         unsigned long cursor_sr;
2863         unsigned long cursor_hpll_disable;
2864 };
2865
2866 static const struct cxsr_latency cxsr_latency_table[] = {
2867         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2868         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2869         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2870         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2871         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2872
2873         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2874         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2875         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2876         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2877         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2878
2879         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2880         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2881         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2882         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2883         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2884
2885         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2886         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2887         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2888         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2889         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2890
2891         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2892         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2893         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2894         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2895         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2896
2897         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2898         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2899         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2900         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2901         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2902 };
2903
2904 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2905                                                          int is_ddr3,
2906                                                          int fsb,
2907                                                          int mem)
2908 {
2909         const struct cxsr_latency *latency;
2910         int i;
2911
2912         if (fsb == 0 || mem == 0)
2913                 return NULL;
2914
2915         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2916                 latency = &cxsr_latency_table[i];
2917                 if (is_desktop == latency->is_desktop &&
2918                     is_ddr3 == latency->is_ddr3 &&
2919                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2920                         return latency;
2921         }
2922
2923         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2924
2925         return NULL;
2926 }
2927
2928 static void pineview_disable_cxsr(struct drm_device *dev)
2929 {
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931
2932         /* deactivate cxsr */
2933         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2934 }
2935
2936 /*
2937  * Latency for FIFO fetches is dependent on several factors:
2938  *   - memory configuration (speed, channels)
2939  *   - chipset
2940  *   - current MCH state
2941  * It can be fairly high in some situations, so here we assume a fairly
2942  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2943  * set this value too high, the FIFO will fetch frequently to stay full)
2944  * and power consumption (set it too low to save power and we might see
2945  * FIFO underruns and display "flicker").
2946  *
2947  * A value of 5us seems to be a good balance; safe for very low end
2948  * platforms but not overly aggressive on lower latency configs.
2949  */
2950 static const int latency_ns = 5000;
2951
2952 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2953 {
2954         struct drm_i915_private *dev_priv = dev->dev_private;
2955         uint32_t dsparb = I915_READ(DSPARB);
2956         int size;
2957
2958         size = dsparb & 0x7f;
2959         if (plane)
2960                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2961
2962         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2963                         plane ? "B" : "A", size);
2964
2965         return size;
2966 }
2967
2968 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2969 {
2970         struct drm_i915_private *dev_priv = dev->dev_private;
2971         uint32_t dsparb = I915_READ(DSPARB);
2972         int size;
2973
2974         size = dsparb & 0x1ff;
2975         if (plane)
2976                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2977         size >>= 1; /* Convert to cachelines */
2978
2979         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2980                         plane ? "B" : "A", size);
2981
2982         return size;
2983 }
2984
2985 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2986 {
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         uint32_t dsparb = I915_READ(DSPARB);
2989         int size;
2990
2991         size = dsparb & 0x7f;
2992         size >>= 2; /* Convert to cachelines */
2993
2994         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2995                         plane ? "B" : "A",
2996                   size);
2997
2998         return size;
2999 }
3000
3001 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         uint32_t dsparb = I915_READ(DSPARB);
3005         int size;
3006
3007         size = dsparb & 0x7f;
3008         size >>= 1; /* Convert to cachelines */
3009
3010         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3011                         plane ? "B" : "A", size);
3012
3013         return size;
3014 }
3015
3016 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3017                           int planeb_clock, int sr_hdisplay, int unused,
3018                           int pixel_size)
3019 {
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         const struct cxsr_latency *latency;
3022         u32 reg;
3023         unsigned long wm;
3024         int sr_clock;
3025
3026         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3027                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3028         if (!latency) {
3029                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3030                 pineview_disable_cxsr(dev);
3031                 return;
3032         }
3033
3034         if (!planea_clock || !planeb_clock) {
3035                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3036
3037                 /* Display SR */
3038                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3039                                         pixel_size, latency->display_sr);
3040                 reg = I915_READ(DSPFW1);
3041                 reg &= ~DSPFW_SR_MASK;
3042                 reg |= wm << DSPFW_SR_SHIFT;
3043                 I915_WRITE(DSPFW1, reg);
3044                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3045
3046                 /* cursor SR */
3047                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3048                                         pixel_size, latency->cursor_sr);
3049                 reg = I915_READ(DSPFW3);
3050                 reg &= ~DSPFW_CURSOR_SR_MASK;
3051                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3052                 I915_WRITE(DSPFW3, reg);
3053
3054                 /* Display HPLL off SR */
3055                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3056                                         pixel_size, latency->display_hpll_disable);
3057                 reg = I915_READ(DSPFW3);
3058                 reg &= ~DSPFW_HPLL_SR_MASK;
3059                 reg |= wm & DSPFW_HPLL_SR_MASK;
3060                 I915_WRITE(DSPFW3, reg);
3061
3062                 /* cursor HPLL off SR */
3063                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3064                                         pixel_size, latency->cursor_hpll_disable);
3065                 reg = I915_READ(DSPFW3);
3066                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3067                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3068                 I915_WRITE(DSPFW3, reg);
3069                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3070
3071                 /* activate cxsr */
3072                 I915_WRITE(DSPFW3,
3073                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3074                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3075         } else {
3076                 pineview_disable_cxsr(dev);
3077                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3078         }
3079 }
3080
3081 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3082                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3083                           int pixel_size)
3084 {
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         int total_size, cacheline_size;
3087         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3088         struct intel_watermark_params planea_params, planeb_params;
3089         unsigned long line_time_us;
3090         int sr_clock, sr_entries = 0, entries_required;
3091
3092         /* Create copies of the base settings for each pipe */
3093         planea_params = planeb_params = g4x_wm_info;
3094
3095         /* Grab a couple of global values before we overwrite them */
3096         total_size = planea_params.fifo_size;
3097         cacheline_size = planea_params.cacheline_size;
3098
3099         /*
3100          * Note: we need to make sure we don't overflow for various clock &
3101          * latency values.
3102          * clocks go from a few thousand to several hundred thousand.
3103          * latency is usually a few thousand
3104          */
3105         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3106                 1000;
3107         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3108         planea_wm = entries_required + planea_params.guard_size;
3109
3110         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3111                 1000;
3112         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3113         planeb_wm = entries_required + planeb_params.guard_size;
3114
3115         cursora_wm = cursorb_wm = 16;
3116         cursor_sr = 32;
3117
3118         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3119
3120         /* Calc sr entries for one plane configs */
3121         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3122                 /* self-refresh has much higher latency */
3123                 static const int sr_latency_ns = 12000;
3124
3125                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3126                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3127
3128                 /* Use ns/us then divide to preserve precision */
3129                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3130                               pixel_size * sr_hdisplay;
3131                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3132
3133                 entries_required = (((sr_latency_ns / line_time_us) +
3134                                      1000) / 1000) * pixel_size * 64;
3135                 entries_required = DIV_ROUND_UP(entries_required,
3136                                            g4x_cursor_wm_info.cacheline_size);
3137                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3138
3139                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3140                         cursor_sr = g4x_cursor_wm_info.max_wm;
3141                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3142                               "cursor %d\n", sr_entries, cursor_sr);
3143
3144                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3145         } else {
3146                 /* Turn off self refresh if both pipes are enabled */
3147                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3148                                         & ~FW_BLC_SELF_EN);
3149         }
3150
3151         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3152                   planea_wm, planeb_wm, sr_entries);
3153
3154         planea_wm &= 0x3f;
3155         planeb_wm &= 0x3f;
3156
3157         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3158                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3159                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3160         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3161                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3162         /* HPLL off in SR has some issues on G4x... disable it */
3163         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3164                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3165 }
3166
3167 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3168                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3169                            int pixel_size)
3170 {
3171         struct drm_i915_private *dev_priv = dev->dev_private;
3172         unsigned long line_time_us;
3173         int sr_clock, sr_entries, srwm = 1;
3174         int cursor_sr = 16;
3175
3176         /* Calc sr entries for one plane configs */
3177         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3178                 /* self-refresh has much higher latency */
3179                 static const int sr_latency_ns = 12000;
3180
3181                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3182                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3183
3184                 /* Use ns/us then divide to preserve precision */
3185                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3186                               pixel_size * sr_hdisplay;
3187                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3188                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3189                 srwm = I965_FIFO_SIZE - sr_entries;
3190                 if (srwm < 0)
3191                         srwm = 1;
3192                 srwm &= 0x1ff;
3193
3194                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3195                              pixel_size * 64;
3196                 sr_entries = DIV_ROUND_UP(sr_entries,
3197                                           i965_cursor_wm_info.cacheline_size);
3198                 cursor_sr = i965_cursor_wm_info.fifo_size -
3199                             (sr_entries + i965_cursor_wm_info.guard_size);
3200
3201                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3202                         cursor_sr = i965_cursor_wm_info.max_wm;
3203
3204                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3205                               "cursor %d\n", srwm, cursor_sr);
3206
3207                 if (IS_I965GM(dev))
3208                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3209         } else {
3210                 /* Turn off self refresh if both pipes are enabled */
3211                 if (IS_I965GM(dev))
3212                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3213                                    & ~FW_BLC_SELF_EN);
3214         }
3215
3216         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3217                       srwm);
3218
3219         /* 965 has limitations... */
3220         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3221                    (8 << 0));
3222         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3223         /* update cursor SR watermark */
3224         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3225 }
3226
3227 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3228                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3229                            int pixel_size)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         uint32_t fwater_lo;
3233         uint32_t fwater_hi;
3234         int total_size, cacheline_size, cwm, srwm = 1;
3235         int planea_wm, planeb_wm;
3236         struct intel_watermark_params planea_params, planeb_params;
3237         unsigned long line_time_us;
3238         int sr_clock, sr_entries = 0;
3239
3240         /* Create copies of the base settings for each pipe */
3241         if (IS_I965GM(dev) || IS_I945GM(dev))
3242                 planea_params = planeb_params = i945_wm_info;
3243         else if (IS_I9XX(dev))
3244                 planea_params = planeb_params = i915_wm_info;
3245         else
3246                 planea_params = planeb_params = i855_wm_info;
3247
3248         /* Grab a couple of global values before we overwrite them */
3249         total_size = planea_params.fifo_size;
3250         cacheline_size = planea_params.cacheline_size;
3251
3252         /* Update per-plane FIFO sizes */
3253         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3254         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3255
3256         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3257                                        pixel_size, latency_ns);
3258         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3259                                        pixel_size, latency_ns);
3260         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3261
3262         /*
3263          * Overlay gets an aggressive default since video jitter is bad.
3264          */
3265         cwm = 2;
3266
3267         /* Calc sr entries for one plane configs */
3268         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3269             (!planea_clock || !planeb_clock)) {
3270                 /* self-refresh has much higher latency */
3271                 static const int sr_latency_ns = 6000;
3272
3273                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3274                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3275
3276                 /* Use ns/us then divide to preserve precision */
3277                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3278                               pixel_size * sr_hdisplay;
3279                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3280                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3281                 srwm = total_size - sr_entries;
3282                 if (srwm < 0)
3283                         srwm = 1;
3284
3285                 if (IS_I945G(dev) || IS_I945GM(dev))
3286                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3287                 else if (IS_I915GM(dev)) {
3288                         /* 915M has a smaller SRWM field */
3289                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3290                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3291                 }
3292         } else {
3293                 /* Turn off self refresh if both pipes are enabled */
3294                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3295                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3296                                    & ~FW_BLC_SELF_EN);
3297                 } else if (IS_I915GM(dev)) {
3298                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3299                 }
3300         }
3301
3302         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3303                   planea_wm, planeb_wm, cwm, srwm);
3304
3305         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3306         fwater_hi = (cwm & 0x1f);
3307
3308         /* Set request length to 8 cachelines per fetch */
3309         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3310         fwater_hi = fwater_hi | (1 << 8);
3311
3312         I915_WRITE(FW_BLC, fwater_lo);
3313         I915_WRITE(FW_BLC2, fwater_hi);
3314 }
3315
3316 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3317                            int unused2, int unused3, int pixel_size)
3318 {
3319         struct drm_i915_private *dev_priv = dev->dev_private;
3320         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3321         int planea_wm;
3322
3323         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3324
3325         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3326                                        pixel_size, latency_ns);
3327         fwater_lo |= (3<<8) | planea_wm;
3328
3329         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3330
3331         I915_WRITE(FW_BLC, fwater_lo);
3332 }
3333
3334 #define ILK_LP0_PLANE_LATENCY           700
3335 #define ILK_LP0_CURSOR_LATENCY          1300
3336
3337 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3338                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3339                        int pixel_size)
3340 {
3341         struct drm_i915_private *dev_priv = dev->dev_private;
3342         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3343         int sr_wm, cursor_wm;
3344         unsigned long line_time_us;
3345         int sr_clock, entries_required;
3346         u32 reg_value;
3347         int line_count;
3348         int planea_htotal = 0, planeb_htotal = 0;
3349         struct drm_crtc *crtc;
3350
3351         /* Need htotal for all active display plane */
3352         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3353                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3355                         if (intel_crtc->plane == 0)
3356                                 planea_htotal = crtc->mode.htotal;
3357                         else
3358                                 planeb_htotal = crtc->mode.htotal;
3359                 }
3360         }
3361
3362         /* Calculate and update the watermark for plane A */
3363         if (planea_clock) {
3364                 entries_required = ((planea_clock / 1000) * pixel_size *
3365                                      ILK_LP0_PLANE_LATENCY) / 1000;
3366                 entries_required = DIV_ROUND_UP(entries_required,
3367                                                 ironlake_display_wm_info.cacheline_size);
3368                 planea_wm = entries_required +
3369                             ironlake_display_wm_info.guard_size;
3370
3371                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3372                         planea_wm = ironlake_display_wm_info.max_wm;
3373
3374                 /* Use the large buffer method to calculate cursor watermark */
3375                 line_time_us = (planea_htotal * 1000) / planea_clock;
3376
3377                 /* Use ns/us then divide to preserve precision */
3378                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3379
3380                 /* calculate the cursor watermark for cursor A */
3381                 entries_required = line_count * 64 * pixel_size;
3382                 entries_required = DIV_ROUND_UP(entries_required,
3383                                                 ironlake_cursor_wm_info.cacheline_size);
3384                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3385                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3386                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3387
3388                 reg_value = I915_READ(WM0_PIPEA_ILK);
3389                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3390                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3391                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3392                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3393                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3394                                 "cursor: %d\n", planea_wm, cursora_wm);
3395         }
3396         /* Calculate and update the watermark for plane B */
3397         if (planeb_clock) {
3398                 entries_required = ((planeb_clock / 1000) * pixel_size *
3399                                      ILK_LP0_PLANE_LATENCY) / 1000;
3400                 entries_required = DIV_ROUND_UP(entries_required,
3401                                                 ironlake_display_wm_info.cacheline_size);
3402                 planeb_wm = entries_required +
3403                             ironlake_display_wm_info.guard_size;
3404
3405                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3406                         planeb_wm = ironlake_display_wm_info.max_wm;
3407
3408                 /* Use the large buffer method to calculate cursor watermark */
3409                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3410
3411                 /* Use ns/us then divide to preserve precision */
3412                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3413
3414                 /* calculate the cursor watermark for cursor B */
3415                 entries_required = line_count * 64 * pixel_size;
3416                 entries_required = DIV_ROUND_UP(entries_required,
3417                                                 ironlake_cursor_wm_info.cacheline_size);
3418                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3419                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3420                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3421
3422                 reg_value = I915_READ(WM0_PIPEB_ILK);
3423                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3424                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3425                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3426                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3427                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3428                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3429         }
3430
3431         /*
3432          * Calculate and update the self-refresh watermark only when one
3433          * display plane is used.
3434          */
3435         if (!planea_clock || !planeb_clock) {
3436
3437                 /* Read the self-refresh latency. The unit is 0.5us */
3438                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3439
3440                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3441                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3442
3443                 /* Use ns/us then divide to preserve precision */
3444                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3445                                / 1000;
3446
3447                 /* calculate the self-refresh watermark for display plane */
3448                 entries_required = line_count * sr_hdisplay * pixel_size;
3449                 entries_required = DIV_ROUND_UP(entries_required,
3450                                                 ironlake_display_srwm_info.cacheline_size);
3451                 sr_wm = entries_required +
3452                         ironlake_display_srwm_info.guard_size;
3453
3454                 /* calculate the self-refresh watermark for display cursor */
3455                 entries_required = line_count * pixel_size * 64;
3456                 entries_required = DIV_ROUND_UP(entries_required,
3457                                                 ironlake_cursor_srwm_info.cacheline_size);
3458                 cursor_wm = entries_required +
3459                             ironlake_cursor_srwm_info.guard_size;
3460
3461                 /* configure watermark and enable self-refresh */
3462                 reg_value = I915_READ(WM1_LP_ILK);
3463                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3464                                WM1_LP_CURSOR_MASK);
3465                 reg_value |= WM1_LP_SR_EN |
3466                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3467                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3468
3469                 I915_WRITE(WM1_LP_ILK, reg_value);
3470                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3471                                 "cursor %d\n", sr_wm, cursor_wm);
3472
3473         } else {
3474                 /* Turn off self refresh if both pipes are enabled */
3475                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3476         }
3477 }
3478 /**
3479  * intel_update_watermarks - update FIFO watermark values based on current modes
3480  *
3481  * Calculate watermark values for the various WM regs based on current mode
3482  * and plane configuration.
3483  *
3484  * There are several cases to deal with here:
3485  *   - normal (i.e. non-self-refresh)
3486  *   - self-refresh (SR) mode
3487  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3488  *   - lines are small relative to FIFO size (buffer can hold more than 2
3489  *     lines), so need to account for TLB latency
3490  *
3491  *   The normal calculation is:
3492  *     watermark = dotclock * bytes per pixel * latency
3493  *   where latency is platform & configuration dependent (we assume pessimal
3494  *   values here).
3495  *
3496  *   The SR calculation is:
3497  *     watermark = (trunc(latency/line time)+1) * surface width *
3498  *       bytes per pixel
3499  *   where
3500  *     line time = htotal / dotclock
3501  *     surface width = hdisplay for normal plane and 64 for cursor
3502  *   and latency is assumed to be high, as above.
3503  *
3504  * The final value programmed to the register should always be rounded up,
3505  * and include an extra 2 entries to account for clock crossings.
3506  *
3507  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3508  * to set the non-SR watermarks to 8.
3509   */
3510 static void intel_update_watermarks(struct drm_device *dev)
3511 {
3512         struct drm_i915_private *dev_priv = dev->dev_private;
3513         struct drm_crtc *crtc;
3514         int sr_hdisplay = 0;
3515         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3516         int enabled = 0, pixel_size = 0;
3517         int sr_htotal = 0;
3518
3519         if (!dev_priv->display.update_wm)
3520                 return;
3521
3522         /* Get the clock config from both planes */
3523         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3524                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3526                         enabled++;
3527                         if (intel_crtc->plane == 0) {
3528                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3529                                           intel_crtc->pipe, crtc->mode.clock);
3530                                 planea_clock = crtc->mode.clock;
3531                         } else {
3532                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3533                                           intel_crtc->pipe, crtc->mode.clock);
3534                                 planeb_clock = crtc->mode.clock;
3535                         }
3536                         sr_hdisplay = crtc->mode.hdisplay;
3537                         sr_clock = crtc->mode.clock;
3538                         sr_htotal = crtc->mode.htotal;
3539                         if (crtc->fb)
3540                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3541                         else
3542                                 pixel_size = 4; /* by default */
3543                 }
3544         }
3545
3546         if (enabled <= 0)
3547                 return;
3548
3549         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3550                                     sr_hdisplay, sr_htotal, pixel_size);
3551 }
3552
3553 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3554                                struct drm_display_mode *mode,
3555                                struct drm_display_mode *adjusted_mode,
3556                                int x, int y,
3557                                struct drm_framebuffer *old_fb)
3558 {
3559         struct drm_device *dev = crtc->dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562         int pipe = intel_crtc->pipe;
3563         int plane = intel_crtc->plane;
3564         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3565         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3566         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3567         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3568         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3569         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3570         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3571         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3572         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3573         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3574         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3575         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3576         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3577         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3578         int refclk, num_connectors = 0;
3579         intel_clock_t clock, reduced_clock;
3580         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3581         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3582         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3583         bool is_edp = false;
3584         struct drm_mode_config *mode_config = &dev->mode_config;
3585         struct drm_encoder *encoder;
3586         struct intel_encoder *intel_encoder = NULL;
3587         const intel_limit_t *limit;
3588         int ret;
3589         struct fdi_m_n m_n = {0};
3590         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3591         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3592         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3593         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3594         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3595         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3596         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3597         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3598         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3599         int lvds_reg = LVDS;
3600         u32 temp;
3601         int sdvo_pixel_multiply;
3602         int target_clock;
3603
3604         drm_vblank_pre_modeset(dev, pipe);
3605
3606         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3607
3608                 if (!encoder || encoder->crtc != crtc)
3609                         continue;
3610
3611                 intel_encoder = enc_to_intel_encoder(encoder);
3612
3613                 switch (intel_encoder->type) {
3614                 case INTEL_OUTPUT_LVDS:
3615                         is_lvds = true;
3616                         break;
3617                 case INTEL_OUTPUT_SDVO:
3618                 case INTEL_OUTPUT_HDMI:
3619                         is_sdvo = true;
3620                         if (intel_encoder->needs_tv_clock)
3621                                 is_tv = true;
3622                         break;
3623                 case INTEL_OUTPUT_DVO:
3624                         is_dvo = true;
3625                         break;
3626                 case INTEL_OUTPUT_TVOUT:
3627                         is_tv = true;
3628                         break;
3629                 case INTEL_OUTPUT_ANALOG:
3630                         is_crt = true;
3631                         break;
3632                 case INTEL_OUTPUT_DISPLAYPORT:
3633                         is_dp = true;
3634                         break;
3635                 case INTEL_OUTPUT_EDP:
3636                         is_edp = true;
3637                         break;
3638                 }
3639
3640                 num_connectors++;
3641         }
3642
3643         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3644                 refclk = dev_priv->lvds_ssc_freq * 1000;
3645                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3646                                         refclk / 1000);
3647         } else if (IS_I9XX(dev)) {
3648                 refclk = 96000;
3649                 if (HAS_PCH_SPLIT(dev))
3650                         refclk = 120000; /* 120Mhz refclk */
3651         } else {
3652                 refclk = 48000;
3653         }
3654
3655
3656         /*
3657          * Returns a set of divisors for the desired target clock with the given
3658          * refclk, or FALSE.  The returned values represent the clock equation:
3659          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3660          */
3661         limit = intel_limit(crtc);
3662         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3663         if (!ok) {
3664                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3665                 drm_vblank_post_modeset(dev, pipe);
3666                 return -EINVAL;
3667         }
3668
3669         /* Ensure that the cursor is valid for the new mode before changing... */
3670         intel_crtc_update_cursor(crtc);
3671
3672         if (is_lvds && dev_priv->lvds_downclock_avail) {
3673                 has_reduced_clock = limit->find_pll(limit, crtc,
3674                                                             dev_priv->lvds_downclock,
3675                                                             refclk,
3676                                                             &reduced_clock);
3677                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3678                         /*
3679                          * If the different P is found, it means that we can't
3680                          * switch the display clock by using the FP0/FP1.
3681                          * In such case we will disable the LVDS downclock
3682                          * feature.
3683                          */
3684                         DRM_DEBUG_KMS("Different P is found for "
3685                                                 "LVDS clock/downclock\n");
3686                         has_reduced_clock = 0;
3687                 }
3688         }
3689         /* SDVO TV has fixed PLL values depend on its clock range,
3690            this mirrors vbios setting. */
3691         if (is_sdvo && is_tv) {
3692                 if (adjusted_mode->clock >= 100000
3693                                 && adjusted_mode->clock < 140500) {
3694                         clock.p1 = 2;
3695                         clock.p2 = 10;
3696                         clock.n = 3;
3697                         clock.m1 = 16;
3698                         clock.m2 = 8;
3699                 } else if (adjusted_mode->clock >= 140500
3700                                 && adjusted_mode->clock <= 200000) {
3701                         clock.p1 = 1;
3702                         clock.p2 = 10;
3703                         clock.n = 6;
3704                         clock.m1 = 12;
3705                         clock.m2 = 8;
3706                 }
3707         }
3708
3709         /* FDI link */
3710         if (HAS_PCH_SPLIT(dev)) {
3711                 int lane = 0, link_bw, bpp;
3712                 /* eDP doesn't require FDI link, so just set DP M/N
3713                    according to current link config */
3714                 if (is_edp) {
3715                         target_clock = mode->clock;
3716                         intel_edp_link_config(intel_encoder,
3717                                         &lane, &link_bw);
3718                 } else {
3719                         /* DP over FDI requires target mode clock
3720                            instead of link clock */
3721                         if (is_dp)
3722                                 target_clock = mode->clock;
3723                         else
3724                                 target_clock = adjusted_mode->clock;
3725                         link_bw = 270000;
3726                 }
3727
3728                 /* determine panel color depth */
3729                 temp = I915_READ(pipeconf_reg);
3730                 temp &= ~PIPE_BPC_MASK;
3731                 if (is_lvds) {
3732                         int lvds_reg = I915_READ(PCH_LVDS);
3733                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3734                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3735                                 temp |= PIPE_8BPC;
3736                         else
3737                                 temp |= PIPE_6BPC;
3738                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3739                         switch (dev_priv->edp_bpp/3) {
3740                         case 8:
3741                                 temp |= PIPE_8BPC;
3742                                 break;
3743                         case 10:
3744                                 temp |= PIPE_10BPC;
3745                                 break;
3746                         case 6:
3747                                 temp |= PIPE_6BPC;
3748                                 break;
3749                         case 12:
3750                                 temp |= PIPE_12BPC;
3751                                 break;
3752                         }
3753                 } else
3754                         temp |= PIPE_8BPC;
3755                 I915_WRITE(pipeconf_reg, temp);
3756                 I915_READ(pipeconf_reg);
3757
3758                 switch (temp & PIPE_BPC_MASK) {
3759                 case PIPE_8BPC:
3760                         bpp = 24;
3761                         break;
3762                 case PIPE_10BPC:
3763                         bpp = 30;
3764                         break;
3765                 case PIPE_6BPC:
3766                         bpp = 18;
3767                         break;
3768                 case PIPE_12BPC:
3769                         bpp = 36;
3770                         break;
3771                 default:
3772                         DRM_ERROR("unknown pipe bpc value\n");
3773                         bpp = 24;
3774                 }
3775
3776                 if (!lane) {
3777                         /*
3778                          * Account for spread spectrum to avoid
3779                          * oversubscribing the link. Max center spread
3780                          * is 2.5%; use 5% for safety's sake.
3781                          */
3782                         u32 bps = target_clock * bpp * 21 / 20;
3783                         lane = bps / (link_bw * 8) + 1;
3784                 }
3785
3786                 intel_crtc->fdi_lanes = lane;
3787
3788                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3789         }
3790
3791         /* Ironlake: try to setup display ref clock before DPLL
3792          * enabling. This is only under driver's control after
3793          * PCH B stepping, previous chipset stepping should be
3794          * ignoring this setting.
3795          */
3796         if (HAS_PCH_SPLIT(dev)) {
3797                 temp = I915_READ(PCH_DREF_CONTROL);
3798                 /* Always enable nonspread source */
3799                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3800                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3801                 I915_WRITE(PCH_DREF_CONTROL, temp);
3802                 POSTING_READ(PCH_DREF_CONTROL);
3803
3804                 temp &= ~DREF_SSC_SOURCE_MASK;
3805                 temp |= DREF_SSC_SOURCE_ENABLE;
3806                 I915_WRITE(PCH_DREF_CONTROL, temp);
3807                 POSTING_READ(PCH_DREF_CONTROL);
3808
3809                 udelay(200);
3810
3811                 if (is_edp) {
3812                         if (dev_priv->lvds_use_ssc) {
3813                                 temp |= DREF_SSC1_ENABLE;
3814                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3815                                 POSTING_READ(PCH_DREF_CONTROL);
3816
3817                                 udelay(200);
3818
3819                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3820                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3821                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3822                                 POSTING_READ(PCH_DREF_CONTROL);
3823                         } else {
3824                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3825                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3826                                 POSTING_READ(PCH_DREF_CONTROL);
3827                         }
3828                 }
3829         }
3830
3831         if (IS_PINEVIEW(dev)) {
3832                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3833                 if (has_reduced_clock)
3834                         fp2 = (1 << reduced_clock.n) << 16 |
3835                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3836         } else {
3837                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3838                 if (has_reduced_clock)
3839                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3840                                 reduced_clock.m2;
3841         }
3842
3843         if (!HAS_PCH_SPLIT(dev))
3844                 dpll = DPLL_VGA_MODE_DIS;
3845
3846         if (IS_I9XX(dev)) {
3847                 if (is_lvds)
3848                         dpll |= DPLLB_MODE_LVDS;
3849                 else
3850                         dpll |= DPLLB_MODE_DAC_SERIAL;
3851                 if (is_sdvo) {
3852                         dpll |= DPLL_DVO_HIGH_SPEED;
3853                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3854                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3855                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3856                         else if (HAS_PCH_SPLIT(dev))
3857                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3858                 }
3859                 if (is_dp)
3860                         dpll |= DPLL_DVO_HIGH_SPEED;
3861
3862                 /* compute bitmask from p1 value */
3863                 if (IS_PINEVIEW(dev))
3864                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3865                 else {
3866                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3867                         /* also FPA1 */
3868                         if (HAS_PCH_SPLIT(dev))
3869                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3870                         if (IS_G4X(dev) && has_reduced_clock)
3871                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3872                 }
3873                 switch (clock.p2) {
3874                 case 5:
3875                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3876                         break;
3877                 case 7:
3878                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3879                         break;
3880                 case 10:
3881                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3882                         break;
3883                 case 14:
3884                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3885                         break;
3886                 }
3887                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3888                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3889         } else {
3890                 if (is_lvds) {
3891                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3892                 } else {
3893                         if (clock.p1 == 2)
3894                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3895                         else
3896                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3897                         if (clock.p2 == 4)
3898                                 dpll |= PLL_P2_DIVIDE_BY_4;
3899                 }
3900         }
3901
3902         if (is_sdvo && is_tv)
3903                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3904         else if (is_tv)
3905                 /* XXX: just matching BIOS for now */
3906                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3907                 dpll |= 3;
3908         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3909                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3910         else
3911                 dpll |= PLL_REF_INPUT_DREFCLK;
3912
3913         /* setup pipeconf */
3914         pipeconf = I915_READ(pipeconf_reg);
3915
3916         /* Set up the display plane register */
3917         dspcntr = DISPPLANE_GAMMA_ENABLE;
3918
3919         /* Ironlake's plane is forced to pipe, bit 24 is to
3920            enable color space conversion */
3921         if (!HAS_PCH_SPLIT(dev)) {
3922                 if (pipe == 0)
3923                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3924                 else
3925                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3926         }
3927
3928         if (pipe == 0 && !IS_I965G(dev)) {
3929                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3930                  * core speed.
3931                  *
3932                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3933                  * pipe == 0 check?
3934                  */
3935                 if (mode->clock >
3936                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3937                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3938                 else
3939                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3940         }
3941
3942         dspcntr |= DISPLAY_PLANE_ENABLE;
3943         pipeconf |= PIPEACONF_ENABLE;
3944         dpll |= DPLL_VCO_ENABLE;
3945
3946
3947         /* Disable the panel fitter if it was on our pipe */
3948         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3949                 I915_WRITE(PFIT_CONTROL, 0);
3950
3951         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3952         drm_mode_debug_printmodeline(mode);
3953
3954         /* assign to Ironlake registers */
3955         if (HAS_PCH_SPLIT(dev)) {
3956                 fp_reg = pch_fp_reg;
3957                 dpll_reg = pch_dpll_reg;
3958         }
3959
3960         if (is_edp) {
3961                 ironlake_disable_pll_edp(crtc);
3962         } else if ((dpll & DPLL_VCO_ENABLE)) {
3963                 I915_WRITE(fp_reg, fp);
3964                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3965                 I915_READ(dpll_reg);
3966                 udelay(150);
3967         }
3968
3969         /* enable transcoder DPLL */
3970         if (HAS_PCH_CPT(dev)) {
3971                 temp = I915_READ(PCH_DPLL_SEL);
3972                 if (trans_dpll_sel == 0)
3973                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3974                 else
3975                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3976                 I915_WRITE(PCH_DPLL_SEL, temp);
3977                 I915_READ(PCH_DPLL_SEL);
3978                 udelay(150);
3979         }
3980
3981         if (HAS_PCH_SPLIT(dev)) {
3982                 pipeconf &= ~PIPE_ENABLE_DITHER;
3983                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3984         }
3985
3986         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3987          * This is an exception to the general rule that mode_set doesn't turn
3988          * things on.
3989          */
3990         if (is_lvds) {
3991                 u32 lvds;
3992
3993                 if (HAS_PCH_SPLIT(dev))
3994                         lvds_reg = PCH_LVDS;
3995
3996                 lvds = I915_READ(lvds_reg);
3997                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3998                 if (pipe == 1) {
3999                         if (HAS_PCH_CPT(dev))
4000                                 lvds |= PORT_TRANS_B_SEL_CPT;
4001                         else
4002                                 lvds |= LVDS_PIPEB_SELECT;
4003                 } else {
4004                         if (HAS_PCH_CPT(dev))
4005                                 lvds &= ~PORT_TRANS_SEL_MASK;
4006                         else
4007                                 lvds &= ~LVDS_PIPEB_SELECT;
4008                 }
4009                 /* set the corresponsding LVDS_BORDER bit */
4010                 lvds |= dev_priv->lvds_border_bits;
4011                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4012                  * set the DPLLs for dual-channel mode or not.
4013                  */
4014                 if (clock.p2 == 7)
4015                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4016                 else
4017                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4018
4019                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4020                  * appropriately here, but we need to look more thoroughly into how
4021                  * panels behave in the two modes.
4022                  */
4023                 /* set the dithering flag */
4024                 if (IS_I965G(dev)) {
4025                         if (dev_priv->lvds_dither) {
4026                                 if (HAS_PCH_SPLIT(dev)) {
4027                                         pipeconf |= PIPE_ENABLE_DITHER;
4028                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
4029                                 } else
4030                                         lvds |= LVDS_ENABLE_DITHER;
4031                         } else {
4032                                 if (!HAS_PCH_SPLIT(dev)) {
4033                                         lvds &= ~LVDS_ENABLE_DITHER;
4034                                 }
4035                         }
4036                 }
4037                 I915_WRITE(lvds_reg, lvds);
4038                 I915_READ(lvds_reg);
4039         }
4040         if (is_dp)
4041                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4042         else if (HAS_PCH_SPLIT(dev)) {
4043                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4044                 if (pipe == 0) {
4045                         I915_WRITE(TRANSA_DATA_M1, 0);
4046                         I915_WRITE(TRANSA_DATA_N1, 0);
4047                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4048                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4049                 } else {
4050                         I915_WRITE(TRANSB_DATA_M1, 0);
4051                         I915_WRITE(TRANSB_DATA_N1, 0);
4052                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4053                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4054                 }
4055         }
4056
4057         if (!is_edp) {
4058                 I915_WRITE(fp_reg, fp);
4059                 I915_WRITE(dpll_reg, dpll);
4060                 I915_READ(dpll_reg);
4061                 /* Wait for the clocks to stabilize. */
4062                 udelay(150);
4063
4064                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4065                         if (is_sdvo) {
4066                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4067                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4068                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4069                         } else
4070                                 I915_WRITE(dpll_md_reg, 0);
4071                 } else {
4072                         /* write it again -- the BIOS does, after all */
4073                         I915_WRITE(dpll_reg, dpll);
4074                 }
4075                 I915_READ(dpll_reg);
4076                 /* Wait for the clocks to stabilize. */
4077                 udelay(150);
4078         }
4079
4080         if (is_lvds && has_reduced_clock && i915_powersave) {
4081                 I915_WRITE(fp_reg + 4, fp2);
4082                 intel_crtc->lowfreq_avail = true;
4083                 if (HAS_PIPE_CXSR(dev)) {
4084                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4085                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4086                 }
4087         } else {
4088                 I915_WRITE(fp_reg + 4, fp);
4089                 intel_crtc->lowfreq_avail = false;
4090                 if (HAS_PIPE_CXSR(dev)) {
4091                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4092                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4093                 }
4094         }
4095
4096         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4097                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4098                 /* the chip adds 2 halflines automatically */
4099                 adjusted_mode->crtc_vdisplay -= 1;
4100                 adjusted_mode->crtc_vtotal -= 1;
4101                 adjusted_mode->crtc_vblank_start -= 1;
4102                 adjusted_mode->crtc_vblank_end -= 1;
4103                 adjusted_mode->crtc_vsync_end -= 1;
4104                 adjusted_mode->crtc_vsync_start -= 1;
4105         } else
4106                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4107
4108         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4109                    ((adjusted_mode->crtc_htotal - 1) << 16));
4110         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4111                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4112         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4113                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4114         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4115                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4116         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4117                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4118         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4119                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4120         /* pipesrc and dspsize control the size that is scaled from, which should
4121          * always be the user's requested size.
4122          */
4123         if (!HAS_PCH_SPLIT(dev)) {
4124                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4125                                 (mode->hdisplay - 1));
4126                 I915_WRITE(dsppos_reg, 0);
4127         }
4128         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4129
4130         if (HAS_PCH_SPLIT(dev)) {
4131                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4132                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4133                 I915_WRITE(link_m1_reg, m_n.link_m);
4134                 I915_WRITE(link_n1_reg, m_n.link_n);
4135
4136                 if (is_edp) {
4137                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4138                 } else {
4139                         /* enable FDI RX PLL too */
4140                         temp = I915_READ(fdi_rx_reg);
4141                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4142                         I915_READ(fdi_rx_reg);
4143                         udelay(200);
4144
4145                         /* enable FDI TX PLL too */
4146                         temp = I915_READ(fdi_tx_reg);
4147                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4148                         I915_READ(fdi_tx_reg);
4149
4150                         /* enable FDI RX PCDCLK */
4151                         temp = I915_READ(fdi_rx_reg);
4152                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4153                         I915_READ(fdi_rx_reg);
4154                         udelay(200);
4155                 }
4156         }
4157
4158         I915_WRITE(pipeconf_reg, pipeconf);
4159         I915_READ(pipeconf_reg);
4160
4161         intel_wait_for_vblank(dev);
4162
4163         if (IS_IRONLAKE(dev)) {
4164                 /* enable address swizzle for tiling buffer */
4165                 temp = I915_READ(DISP_ARB_CTL);
4166                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4167         }
4168
4169         I915_WRITE(dspcntr_reg, dspcntr);
4170
4171         /* Flush the plane changes */
4172         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4173
4174         intel_update_watermarks(dev);
4175
4176         drm_vblank_post_modeset(dev, pipe);
4177
4178         return ret;
4179 }
4180
4181 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4182 void intel_crtc_load_lut(struct drm_crtc *crtc)
4183 {
4184         struct drm_device *dev = crtc->dev;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4187         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4188         int i;
4189
4190         /* The clocks have to be on to load the palette. */
4191         if (!crtc->enabled)
4192                 return;
4193
4194         /* use legacy palette for Ironlake */
4195         if (HAS_PCH_SPLIT(dev))
4196                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4197                                                    LGC_PALETTE_B;
4198
4199         for (i = 0; i < 256; i++) {
4200                 I915_WRITE(palreg + 4 * i,
4201                            (intel_crtc->lut_r[i] << 16) |
4202                            (intel_crtc->lut_g[i] << 8) |
4203                            intel_crtc->lut_b[i]);
4204         }
4205 }
4206
4207 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4208 {
4209         struct drm_device *dev = crtc->dev;
4210         struct drm_i915_private *dev_priv = dev->dev_private;
4211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212         bool visible = base != 0;
4213         u32 cntl;
4214
4215         if (intel_crtc->cursor_visible == visible)
4216                 return;
4217
4218         cntl = I915_READ(CURACNTR);
4219         if (visible) {
4220                 /* On these chipsets we can only modify the base whilst
4221                  * the cursor is disabled.
4222                  */
4223                 I915_WRITE(CURABASE, base);
4224
4225                 cntl &= ~(CURSOR_FORMAT_MASK);
4226                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4227                 cntl |= CURSOR_ENABLE |
4228                         CURSOR_GAMMA_ENABLE |
4229                         CURSOR_FORMAT_ARGB;
4230         } else
4231                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4232         I915_WRITE(CURACNTR, cntl);
4233
4234         intel_crtc->cursor_visible = visible;
4235 }
4236
4237 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4238 {
4239         struct drm_device *dev = crtc->dev;
4240         struct drm_i915_private *dev_priv = dev->dev_private;
4241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242         int pipe = intel_crtc->pipe;
4243         bool visible = base != 0;
4244
4245         if (intel_crtc->cursor_visible != visible) {
4246                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4247                 if (base) {
4248                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4249                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4250                         cntl |= pipe << 28; /* Connect to correct pipe */
4251                 } else {
4252                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4253                         cntl |= CURSOR_MODE_DISABLE;
4254                 }
4255                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4256
4257                 intel_crtc->cursor_visible = visible;
4258         }
4259         /* and commit changes on next vblank */
4260         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4261 }
4262
4263 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4264 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4265 {
4266         struct drm_device *dev = crtc->dev;
4267         struct drm_i915_private *dev_priv = dev->dev_private;
4268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4269         int pipe = intel_crtc->pipe;
4270         int x = intel_crtc->cursor_x;
4271         int y = intel_crtc->cursor_y;
4272         u32 base, pos;
4273         bool visible;
4274
4275         pos = 0;
4276
4277         if (intel_crtc->cursor_on && crtc->fb) {
4278                 base = intel_crtc->cursor_addr;
4279                 if (x > (int) crtc->fb->width)
4280                         base = 0;
4281
4282                 if (y > (int) crtc->fb->height)
4283                         base = 0;
4284         } else
4285                 base = 0;
4286
4287         if (x < 0) {
4288                 if (x + intel_crtc->cursor_width < 0)
4289                         base = 0;
4290
4291                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4292                 x = -x;
4293         }
4294         pos |= x << CURSOR_X_SHIFT;
4295
4296         if (y < 0) {
4297                 if (y + intel_crtc->cursor_height < 0)
4298                         base = 0;
4299
4300                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4301                 y = -y;
4302         }
4303         pos |= y << CURSOR_Y_SHIFT;
4304
4305         visible = base != 0;
4306         if (!visible && !intel_crtc->cursor_visible)
4307                 return;
4308
4309         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4310         if (IS_845G(dev) || IS_I865G(dev))
4311                 i845_update_cursor(crtc, base);
4312         else
4313                 i9xx_update_cursor(crtc, base);
4314
4315         if (visible)
4316                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4317 }
4318
4319 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4320                                  struct drm_file *file_priv,
4321                                  uint32_t handle,
4322                                  uint32_t width, uint32_t height)
4323 {
4324         struct drm_device *dev = crtc->dev;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327         struct drm_gem_object *bo;
4328         struct drm_i915_gem_object *obj_priv;
4329         uint32_t addr;
4330         int ret;
4331
4332         DRM_DEBUG_KMS("\n");
4333
4334         /* if we want to turn off the cursor ignore width and height */
4335         if (!handle) {
4336                 DRM_DEBUG_KMS("cursor off\n");
4337                 addr = 0;
4338                 bo = NULL;
4339                 mutex_lock(&dev->struct_mutex);
4340                 goto finish;
4341         }
4342
4343         /* Currently we only support 64x64 cursors */
4344         if (width != 64 || height != 64) {
4345                 DRM_ERROR("we currently only support 64x64 cursors\n");
4346                 return -EINVAL;
4347         }
4348
4349         bo = drm_gem_object_lookup(dev, file_priv, handle);
4350         if (!bo)
4351                 return -ENOENT;
4352
4353         obj_priv = to_intel_bo(bo);
4354
4355         if (bo->size < width * height * 4) {
4356                 DRM_ERROR("buffer is to small\n");
4357                 ret = -ENOMEM;
4358                 goto fail;
4359         }
4360
4361         /* we only need to pin inside GTT if cursor is non-phy */
4362         mutex_lock(&dev->struct_mutex);
4363         if (!dev_priv->info->cursor_needs_physical) {
4364                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4365                 if (ret) {
4366                         DRM_ERROR("failed to pin cursor bo\n");
4367                         goto fail_locked;
4368                 }
4369
4370                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4371                 if (ret) {
4372                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4373                         goto fail_unpin;
4374                 }
4375
4376                 addr = obj_priv->gtt_offset;
4377         } else {
4378                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4379                 ret = i915_gem_attach_phys_object(dev, bo,
4380                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4381                                                   align);
4382                 if (ret) {
4383                         DRM_ERROR("failed to attach phys object\n");
4384                         goto fail_locked;
4385                 }
4386                 addr = obj_priv->phys_obj->handle->busaddr;
4387         }
4388
4389         if (!IS_I9XX(dev))
4390                 I915_WRITE(CURSIZE, (height << 12) | width);
4391
4392  finish:
4393         if (intel_crtc->cursor_bo) {
4394                 if (dev_priv->info->cursor_needs_physical) {
4395                         if (intel_crtc->cursor_bo != bo)
4396                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4397                 } else
4398                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4399                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4400         }
4401
4402         mutex_unlock(&dev->struct_mutex);
4403
4404         intel_crtc->cursor_addr = addr;
4405         intel_crtc->cursor_bo = bo;
4406         intel_crtc->cursor_width = width;
4407         intel_crtc->cursor_height = height;
4408
4409         intel_crtc_update_cursor(crtc);
4410
4411         return 0;
4412 fail_unpin:
4413         i915_gem_object_unpin(bo);
4414 fail_locked:
4415         mutex_unlock(&dev->struct_mutex);
4416 fail:
4417         drm_gem_object_unreference_unlocked(bo);
4418         return ret;
4419 }
4420
4421 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4422 {
4423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4424
4425         intel_crtc->cursor_x = x;
4426         intel_crtc->cursor_y = y;
4427
4428         intel_crtc_update_cursor(crtc);
4429
4430         return 0;
4431 }
4432
4433 /** Sets the color ramps on behalf of RandR */
4434 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4435                                  u16 blue, int regno)
4436 {
4437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4438
4439         intel_crtc->lut_r[regno] = red >> 8;
4440         intel_crtc->lut_g[regno] = green >> 8;
4441         intel_crtc->lut_b[regno] = blue >> 8;
4442 }
4443
4444 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4445                              u16 *blue, int regno)
4446 {
4447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4448
4449         *red = intel_crtc->lut_r[regno] << 8;
4450         *green = intel_crtc->lut_g[regno] << 8;
4451         *blue = intel_crtc->lut_b[regno] << 8;
4452 }
4453
4454 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4455                                  u16 *blue, uint32_t size)
4456 {
4457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4458         int i;
4459
4460         if (size != 256)
4461                 return;
4462
4463         for (i = 0; i < 256; i++) {
4464                 intel_crtc->lut_r[i] = red[i] >> 8;
4465                 intel_crtc->lut_g[i] = green[i] >> 8;
4466                 intel_crtc->lut_b[i] = blue[i] >> 8;
4467         }
4468
4469         intel_crtc_load_lut(crtc);
4470 }
4471
4472 /**
4473  * Get a pipe with a simple mode set on it for doing load-based monitor
4474  * detection.
4475  *
4476  * It will be up to the load-detect code to adjust the pipe as appropriate for
4477  * its requirements.  The pipe will be connected to no other encoders.
4478  *
4479  * Currently this code will only succeed if there is a pipe with no encoders
4480  * configured for it.  In the future, it could choose to temporarily disable
4481  * some outputs to free up a pipe for its use.
4482  *
4483  * \return crtc, or NULL if no pipes are available.
4484  */
4485
4486 /* VESA 640x480x72Hz mode to set on the pipe */
4487 static struct drm_display_mode load_detect_mode = {
4488         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4489                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4490 };
4491
4492 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4493                                             struct drm_connector *connector,
4494                                             struct drm_display_mode *mode,
4495                                             int *dpms_mode)
4496 {
4497         struct intel_crtc *intel_crtc;
4498         struct drm_crtc *possible_crtc;
4499         struct drm_crtc *supported_crtc =NULL;
4500         struct drm_encoder *encoder = &intel_encoder->enc;
4501         struct drm_crtc *crtc = NULL;
4502         struct drm_device *dev = encoder->dev;
4503         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4504         struct drm_crtc_helper_funcs *crtc_funcs;
4505         int i = -1;
4506
4507         /*
4508          * Algorithm gets a little messy:
4509          *   - if the connector already has an assigned crtc, use it (but make
4510          *     sure it's on first)
4511          *   - try to find the first unused crtc that can drive this connector,
4512          *     and use that if we find one
4513          *   - if there are no unused crtcs available, try to use the first
4514          *     one we found that supports the connector
4515          */
4516
4517         /* See if we already have a CRTC for this connector */
4518         if (encoder->crtc) {
4519                 crtc = encoder->crtc;
4520                 /* Make sure the crtc and connector are running */
4521                 intel_crtc = to_intel_crtc(crtc);
4522                 *dpms_mode = intel_crtc->dpms_mode;
4523                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4524                         crtc_funcs = crtc->helper_private;
4525                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4526                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4527                 }
4528                 return crtc;
4529         }
4530
4531         /* Find an unused one (if possible) */
4532         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4533                 i++;
4534                 if (!(encoder->possible_crtcs & (1 << i)))
4535                         continue;
4536                 if (!possible_crtc->enabled) {
4537                         crtc = possible_crtc;
4538                         break;
4539                 }
4540                 if (!supported_crtc)
4541                         supported_crtc = possible_crtc;
4542         }
4543
4544         /*
4545          * If we didn't find an unused CRTC, don't use any.
4546          */
4547         if (!crtc) {
4548                 return NULL;
4549         }
4550
4551         encoder->crtc = crtc;
4552         connector->encoder = encoder;
4553         intel_encoder->load_detect_temp = true;
4554
4555         intel_crtc = to_intel_crtc(crtc);
4556         *dpms_mode = intel_crtc->dpms_mode;
4557
4558         if (!crtc->enabled) {
4559                 if (!mode)
4560                         mode = &load_detect_mode;
4561                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4562         } else {
4563                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4564                         crtc_funcs = crtc->helper_private;
4565                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4566                 }
4567
4568                 /* Add this connector to the crtc */
4569                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4570                 encoder_funcs->commit(encoder);
4571         }
4572         /* let the connector get through one full cycle before testing */
4573         intel_wait_for_vblank(dev);
4574
4575         return crtc;
4576 }
4577
4578 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4579                                     struct drm_connector *connector, int dpms_mode)
4580 {
4581         struct drm_encoder *encoder = &intel_encoder->enc;
4582         struct drm_device *dev = encoder->dev;
4583         struct drm_crtc *crtc = encoder->crtc;
4584         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4585         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4586
4587         if (intel_encoder->load_detect_temp) {
4588                 encoder->crtc = NULL;
4589                 connector->encoder = NULL;
4590                 intel_encoder->load_detect_temp = false;
4591                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4592                 drm_helper_disable_unused_functions(dev);
4593         }
4594
4595         /* Switch crtc and encoder back off if necessary */
4596         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4597                 if (encoder->crtc == crtc)
4598                         encoder_funcs->dpms(encoder, dpms_mode);
4599                 crtc_funcs->dpms(crtc, dpms_mode);
4600         }
4601 }
4602
4603 /* Returns the clock of the currently programmed mode of the given pipe. */
4604 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4605 {
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4608         int pipe = intel_crtc->pipe;
4609         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4610         u32 fp;
4611         intel_clock_t clock;
4612
4613         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4614                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4615         else
4616                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4617
4618         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4619         if (IS_PINEVIEW(dev)) {
4620                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4621                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4622         } else {
4623                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4624                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4625         }
4626
4627         if (IS_I9XX(dev)) {
4628                 if (IS_PINEVIEW(dev))
4629                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4630                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4631                 else
4632                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4633                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4634
4635                 switch (dpll & DPLL_MODE_MASK) {
4636                 case DPLLB_MODE_DAC_SERIAL:
4637                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4638                                 5 : 10;
4639                         break;
4640                 case DPLLB_MODE_LVDS:
4641                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4642                                 7 : 14;
4643                         break;
4644                 default:
4645                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4646                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4647                         return 0;
4648                 }
4649
4650                 /* XXX: Handle the 100Mhz refclk */
4651                 intel_clock(dev, 96000, &clock);
4652         } else {
4653                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4654
4655                 if (is_lvds) {
4656                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4657                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4658                         clock.p2 = 14;
4659
4660                         if ((dpll & PLL_REF_INPUT_MASK) ==
4661                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4662                                 /* XXX: might not be 66MHz */
4663                                 intel_clock(dev, 66000, &clock);
4664                         } else
4665                                 intel_clock(dev, 48000, &clock);
4666                 } else {
4667                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4668                                 clock.p1 = 2;
4669                         else {
4670                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4671                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4672                         }
4673                         if (dpll & PLL_P2_DIVIDE_BY_4)
4674                                 clock.p2 = 4;
4675                         else
4676                                 clock.p2 = 2;
4677
4678                         intel_clock(dev, 48000, &clock);
4679                 }
4680         }
4681
4682         /* XXX: It would be nice to validate the clocks, but we can't reuse
4683          * i830PllIsValid() because it relies on the xf86_config connector
4684          * configuration being accurate, which it isn't necessarily.
4685          */
4686
4687         return clock.dot;
4688 }
4689
4690 /** Returns the currently programmed mode of the given pipe. */
4691 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4692                                              struct drm_crtc *crtc)
4693 {
4694         struct drm_i915_private *dev_priv = dev->dev_private;
4695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696         int pipe = intel_crtc->pipe;
4697         struct drm_display_mode *mode;
4698         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4699         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4700         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4701         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4702
4703         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4704         if (!mode)
4705                 return NULL;
4706
4707         mode->clock = intel_crtc_clock_get(dev, crtc);
4708         mode->hdisplay = (htot & 0xffff) + 1;
4709         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4710         mode->hsync_start = (hsync & 0xffff) + 1;
4711         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4712         mode->vdisplay = (vtot & 0xffff) + 1;
4713         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4714         mode->vsync_start = (vsync & 0xffff) + 1;
4715         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4716
4717         drm_mode_set_name(mode);
4718         drm_mode_set_crtcinfo(mode, 0);
4719
4720         return mode;
4721 }
4722
4723 #define GPU_IDLE_TIMEOUT 500 /* ms */
4724
4725 /* When this timer fires, we've been idle for awhile */
4726 static void intel_gpu_idle_timer(unsigned long arg)
4727 {
4728         struct drm_device *dev = (struct drm_device *)arg;
4729         drm_i915_private_t *dev_priv = dev->dev_private;
4730
4731         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4732
4733         dev_priv->busy = false;
4734
4735         queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4739
4740 static void intel_crtc_idle_timer(unsigned long arg)
4741 {
4742         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4743         struct drm_crtc *crtc = &intel_crtc->base;
4744         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4745
4746         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4747
4748         intel_crtc->busy = false;
4749
4750         queue_work(dev_priv->wq, &dev_priv->idle_work);
4751 }
4752
4753 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4754 {
4755         struct drm_device *dev = crtc->dev;
4756         drm_i915_private_t *dev_priv = dev->dev_private;
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4758         int pipe = intel_crtc->pipe;
4759         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4760         int dpll = I915_READ(dpll_reg);
4761
4762         if (HAS_PCH_SPLIT(dev))
4763                 return;
4764
4765         if (!dev_priv->lvds_downclock_avail)
4766                 return;
4767
4768         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4769                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4770
4771                 /* Unlock panel regs */
4772                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4773                            PANEL_UNLOCK_REGS);
4774
4775                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4776                 I915_WRITE(dpll_reg, dpll);
4777                 dpll = I915_READ(dpll_reg);
4778                 intel_wait_for_vblank(dev);
4779                 dpll = I915_READ(dpll_reg);
4780                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4781                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4782
4783                 /* ...and lock them again */
4784                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4785         }
4786
4787         /* Schedule downclock */
4788         if (schedule)
4789                 mod_timer(&intel_crtc->idle_timer, jiffies +
4790                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4791 }
4792
4793 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4794 {
4795         struct drm_device *dev = crtc->dev;
4796         drm_i915_private_t *dev_priv = dev->dev_private;
4797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4798         int pipe = intel_crtc->pipe;
4799         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4800         int dpll = I915_READ(dpll_reg);
4801
4802         if (HAS_PCH_SPLIT(dev))
4803                 return;
4804
4805         if (!dev_priv->lvds_downclock_avail)
4806                 return;
4807
4808         /*
4809          * Since this is called by a timer, we should never get here in
4810          * the manual case.
4811          */
4812         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4813                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4814
4815                 /* Unlock panel regs */
4816                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4817                            PANEL_UNLOCK_REGS);
4818
4819                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4820                 I915_WRITE(dpll_reg, dpll);
4821                 dpll = I915_READ(dpll_reg);
4822                 intel_wait_for_vblank(dev);
4823                 dpll = I915_READ(dpll_reg);
4824                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4825                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4826
4827                 /* ...and lock them again */
4828                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4829         }
4830
4831 }
4832
4833 /**
4834  * intel_idle_update - adjust clocks for idleness
4835  * @work: work struct
4836  *
4837  * Either the GPU or display (or both) went idle.  Check the busy status
4838  * here and adjust the CRTC and GPU clocks as necessary.
4839  */
4840 static void intel_idle_update(struct work_struct *work)
4841 {
4842         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4843                                                     idle_work);
4844         struct drm_device *dev = dev_priv->dev;
4845         struct drm_crtc *crtc;
4846         struct intel_crtc *intel_crtc;
4847         int enabled = 0;
4848
4849         if (!i915_powersave)
4850                 return;
4851
4852         mutex_lock(&dev->struct_mutex);
4853
4854         i915_update_gfx_val(dev_priv);
4855
4856         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4857                 /* Skip inactive CRTCs */
4858                 if (!crtc->fb)
4859                         continue;
4860
4861                 enabled++;
4862                 intel_crtc = to_intel_crtc(crtc);
4863                 if (!intel_crtc->busy)
4864                         intel_decrease_pllclock(crtc);
4865         }
4866
4867         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4868                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4869                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4870         }
4871
4872         mutex_unlock(&dev->struct_mutex);
4873 }
4874
4875 /**
4876  * intel_mark_busy - mark the GPU and possibly the display busy
4877  * @dev: drm device
4878  * @obj: object we're operating on
4879  *
4880  * Callers can use this function to indicate that the GPU is busy processing
4881  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4882  * buffer), we'll also mark the display as busy, so we know to increase its
4883  * clock frequency.
4884  */
4885 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4886 {
4887         drm_i915_private_t *dev_priv = dev->dev_private;
4888         struct drm_crtc *crtc = NULL;
4889         struct intel_framebuffer *intel_fb;
4890         struct intel_crtc *intel_crtc;
4891
4892         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4893                 return;
4894
4895         if (!dev_priv->busy) {
4896                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4897                         u32 fw_blc_self;
4898
4899                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4900                         fw_blc_self = I915_READ(FW_BLC_SELF);
4901                         fw_blc_self &= ~FW_BLC_SELF_EN;
4902                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4903                 }
4904                 dev_priv->busy = true;
4905         } else
4906                 mod_timer(&dev_priv->idle_timer, jiffies +
4907                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4908
4909         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4910                 if (!crtc->fb)
4911                         continue;
4912
4913                 intel_crtc = to_intel_crtc(crtc);
4914                 intel_fb = to_intel_framebuffer(crtc->fb);
4915                 if (intel_fb->obj == obj) {
4916                         if (!intel_crtc->busy) {
4917                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4918                                         u32 fw_blc_self;
4919
4920                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4921                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4922                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4923                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4924                                 }
4925                                 /* Non-busy -> busy, upclock */
4926                                 intel_increase_pllclock(crtc, true);
4927                                 intel_crtc->busy = true;
4928                         } else {
4929                                 /* Busy -> busy, put off timer */
4930                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4931                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4932                         }
4933                 }
4934         }
4935 }
4936
4937 static void intel_crtc_destroy(struct drm_crtc *crtc)
4938 {
4939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4940
4941         drm_crtc_cleanup(crtc);
4942         kfree(intel_crtc);
4943 }
4944
4945 struct intel_unpin_work {
4946         struct work_struct work;
4947         struct drm_device *dev;
4948         struct drm_gem_object *old_fb_obj;
4949         struct drm_gem_object *pending_flip_obj;
4950         struct drm_pending_vblank_event *event;
4951         int pending;
4952 };
4953
4954 static void intel_unpin_work_fn(struct work_struct *__work)
4955 {
4956         struct intel_unpin_work *work =
4957                 container_of(__work, struct intel_unpin_work, work);
4958
4959         mutex_lock(&work->dev->struct_mutex);
4960         i915_gem_object_unpin(work->old_fb_obj);
4961         drm_gem_object_unreference(work->pending_flip_obj);
4962         drm_gem_object_unreference(work->old_fb_obj);
4963         mutex_unlock(&work->dev->struct_mutex);
4964         kfree(work);
4965 }
4966
4967 static void do_intel_finish_page_flip(struct drm_device *dev,
4968                                       struct drm_crtc *crtc)
4969 {
4970         drm_i915_private_t *dev_priv = dev->dev_private;
4971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972         struct intel_unpin_work *work;
4973         struct drm_i915_gem_object *obj_priv;
4974         struct drm_pending_vblank_event *e;
4975         struct timeval now;
4976         unsigned long flags;
4977
4978         /* Ignore early vblank irqs */
4979         if (intel_crtc == NULL)
4980                 return;
4981
4982         spin_lock_irqsave(&dev->event_lock, flags);
4983         work = intel_crtc->unpin_work;
4984         if (work == NULL || !work->pending) {
4985                 spin_unlock_irqrestore(&dev->event_lock, flags);
4986                 return;
4987         }
4988
4989         intel_crtc->unpin_work = NULL;
4990         drm_vblank_put(dev, intel_crtc->pipe);
4991
4992         if (work->event) {
4993                 e = work->event;
4994                 do_gettimeofday(&now);
4995                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4996                 e->event.tv_sec = now.tv_sec;
4997                 e->event.tv_usec = now.tv_usec;
4998                 list_add_tail(&e->base.link,
4999                               &e->base.file_priv->event_list);
5000                 wake_up_interruptible(&e->base.file_priv->event_wait);
5001         }
5002
5003         spin_unlock_irqrestore(&dev->event_lock, flags);
5004
5005         obj_priv = to_intel_bo(work->pending_flip_obj);
5006
5007         /* Initial scanout buffer will have a 0 pending flip count */
5008         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
5009             atomic_dec_and_test(&obj_priv->pending_flip))
5010                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
5011         schedule_work(&work->work);
5012
5013         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5014 }
5015
5016 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5017 {
5018         drm_i915_private_t *dev_priv = dev->dev_private;
5019         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5020
5021         do_intel_finish_page_flip(dev, crtc);
5022 }
5023
5024 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5025 {
5026         drm_i915_private_t *dev_priv = dev->dev_private;
5027         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5028
5029         do_intel_finish_page_flip(dev, crtc);
5030 }
5031
5032 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5033 {
5034         drm_i915_private_t *dev_priv = dev->dev_private;
5035         struct intel_crtc *intel_crtc =
5036                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5037         unsigned long flags;
5038
5039         spin_lock_irqsave(&dev->event_lock, flags);
5040         if (intel_crtc->unpin_work) {
5041                 intel_crtc->unpin_work->pending = 1;
5042         } else {
5043                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5044         }
5045         spin_unlock_irqrestore(&dev->event_lock, flags);
5046 }
5047
5048 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5049                                 struct drm_framebuffer *fb,
5050                                 struct drm_pending_vblank_event *event)
5051 {
5052         struct drm_device *dev = crtc->dev;
5053         struct drm_i915_private *dev_priv = dev->dev_private;
5054         struct intel_framebuffer *intel_fb;
5055         struct drm_i915_gem_object *obj_priv;
5056         struct drm_gem_object *obj;
5057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058         struct intel_unpin_work *work;
5059         unsigned long flags, offset;
5060         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5061         int ret, pipesrc;
5062         u32 flip_mask;
5063
5064         work = kzalloc(sizeof *work, GFP_KERNEL);
5065         if (work == NULL)
5066                 return -ENOMEM;
5067
5068         work->event = event;
5069         work->dev = crtc->dev;
5070         intel_fb = to_intel_framebuffer(crtc->fb);
5071         work->old_fb_obj = intel_fb->obj;
5072         INIT_WORK(&work->work, intel_unpin_work_fn);
5073
5074         /* We borrow the event spin lock for protecting unpin_work */
5075         spin_lock_irqsave(&dev->event_lock, flags);
5076         if (intel_crtc->unpin_work) {
5077                 spin_unlock_irqrestore(&dev->event_lock, flags);
5078                 kfree(work);
5079
5080                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5081                 return -EBUSY;
5082         }
5083         intel_crtc->unpin_work = work;
5084         spin_unlock_irqrestore(&dev->event_lock, flags);
5085
5086         intel_fb = to_intel_framebuffer(fb);
5087         obj = intel_fb->obj;
5088
5089         mutex_lock(&dev->struct_mutex);
5090         ret = intel_pin_and_fence_fb_obj(dev, obj);
5091         if (ret)
5092                 goto cleanup_work;
5093
5094         /* Reference the objects for the scheduled work. */
5095         drm_gem_object_reference(work->old_fb_obj);
5096         drm_gem_object_reference(obj);
5097
5098         crtc->fb = fb;
5099         ret = i915_gem_object_flush_write_domain(obj);
5100         if (ret)
5101                 goto cleanup_objs;
5102
5103         ret = drm_vblank_get(dev, intel_crtc->pipe);
5104         if (ret)
5105                 goto cleanup_objs;
5106
5107         obj_priv = to_intel_bo(obj);
5108         atomic_inc(&obj_priv->pending_flip);
5109         work->pending_flip_obj = obj;
5110
5111         if (intel_crtc->plane)
5112                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5113         else
5114                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5115
5116         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5117                 BEGIN_LP_RING(2);
5118                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5119                 OUT_RING(0);
5120                 ADVANCE_LP_RING();
5121         }
5122
5123         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5124         offset = obj_priv->gtt_offset;
5125         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5126
5127         BEGIN_LP_RING(4);
5128         if (IS_I965G(dev)) {
5129                 OUT_RING(MI_DISPLAY_FLIP |
5130                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5131                 OUT_RING(fb->pitch);
5132                 OUT_RING(offset | obj_priv->tiling_mode);
5133                 pipesrc = I915_READ(pipesrc_reg);
5134                 OUT_RING(pipesrc & 0x0fff0fff);
5135         } else if (IS_GEN3(dev)) {
5136                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5137                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5138                 OUT_RING(fb->pitch);
5139                 OUT_RING(offset);
5140                 OUT_RING(MI_NOOP);
5141         } else {
5142                 OUT_RING(MI_DISPLAY_FLIP |
5143                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5144                 OUT_RING(fb->pitch);
5145                 OUT_RING(offset);
5146                 OUT_RING(MI_NOOP);
5147         }
5148         ADVANCE_LP_RING();
5149
5150         mutex_unlock(&dev->struct_mutex);
5151
5152         trace_i915_flip_request(intel_crtc->plane, obj);
5153
5154         return 0;
5155
5156 cleanup_objs:
5157         drm_gem_object_unreference(work->old_fb_obj);
5158         drm_gem_object_unreference(obj);
5159 cleanup_work:
5160         mutex_unlock(&dev->struct_mutex);
5161
5162         spin_lock_irqsave(&dev->event_lock, flags);
5163         intel_crtc->unpin_work = NULL;
5164         spin_unlock_irqrestore(&dev->event_lock, flags);
5165
5166         kfree(work);
5167
5168         return ret;
5169 }
5170
5171 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5172         .dpms = intel_crtc_dpms,
5173         .mode_fixup = intel_crtc_mode_fixup,
5174         .mode_set = intel_crtc_mode_set,
5175         .mode_set_base = intel_pipe_set_base,
5176         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5177         .prepare = intel_crtc_prepare,
5178         .commit = intel_crtc_commit,
5179         .load_lut = intel_crtc_load_lut,
5180 };
5181
5182 static const struct drm_crtc_funcs intel_crtc_funcs = {
5183         .cursor_set = intel_crtc_cursor_set,
5184         .cursor_move = intel_crtc_cursor_move,
5185         .gamma_set = intel_crtc_gamma_set,
5186         .set_config = drm_crtc_helper_set_config,
5187         .destroy = intel_crtc_destroy,
5188         .page_flip = intel_crtc_page_flip,
5189 };
5190
5191
5192 static void intel_crtc_init(struct drm_device *dev, int pipe)
5193 {
5194         drm_i915_private_t *dev_priv = dev->dev_private;
5195         struct intel_crtc *intel_crtc;
5196         int i;
5197
5198         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5199         if (intel_crtc == NULL)
5200                 return;
5201
5202         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5203
5204         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5205         intel_crtc->pipe = pipe;
5206         intel_crtc->plane = pipe;
5207         for (i = 0; i < 256; i++) {
5208                 intel_crtc->lut_r[i] = i;
5209                 intel_crtc->lut_g[i] = i;
5210                 intel_crtc->lut_b[i] = i;
5211         }
5212
5213         /* Swap pipes & planes for FBC on pre-965 */
5214         intel_crtc->pipe = pipe;
5215         intel_crtc->plane = pipe;
5216         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5217                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5218                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5219         }
5220
5221         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5222                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5223         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5224         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5225
5226         intel_crtc->cursor_addr = 0;
5227         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5228         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5229
5230         intel_crtc->busy = false;
5231
5232         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5233                     (unsigned long)intel_crtc);
5234 }
5235
5236 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5237                                 struct drm_file *file_priv)
5238 {
5239         drm_i915_private_t *dev_priv = dev->dev_private;
5240         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5241         struct drm_mode_object *drmmode_obj;
5242         struct intel_crtc *crtc;
5243
5244         if (!dev_priv) {
5245                 DRM_ERROR("called with no initialization\n");
5246                 return -EINVAL;
5247         }
5248
5249         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5250                         DRM_MODE_OBJECT_CRTC);
5251
5252         if (!drmmode_obj) {
5253                 DRM_ERROR("no such CRTC id\n");
5254                 return -EINVAL;
5255         }
5256
5257         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5258         pipe_from_crtc_id->pipe = crtc->pipe;
5259
5260         return 0;
5261 }
5262
5263 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5264 {
5265         struct drm_crtc *crtc = NULL;
5266
5267         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5268                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5269                 if (intel_crtc->pipe == pipe)
5270                         break;
5271         }
5272         return crtc;
5273 }
5274
5275 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5276 {
5277         int index_mask = 0;
5278         struct drm_encoder *encoder;
5279         int entry = 0;
5280
5281         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5282                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5283                 if (type_mask & intel_encoder->clone_mask)
5284                         index_mask |= (1 << entry);
5285                 entry++;
5286         }
5287         return index_mask;
5288 }
5289
5290
5291 static void intel_setup_outputs(struct drm_device *dev)
5292 {
5293         struct drm_i915_private *dev_priv = dev->dev_private;
5294         struct drm_encoder *encoder;
5295         bool dpd_is_edp = false;
5296
5297         if (IS_MOBILE(dev) && !IS_I830(dev))
5298                 intel_lvds_init(dev);
5299
5300         if (HAS_PCH_SPLIT(dev)) {
5301                 dpd_is_edp = intel_dpd_is_edp(dev);
5302
5303                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5304                         intel_dp_init(dev, DP_A);
5305
5306                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5307                         intel_dp_init(dev, PCH_DP_D);
5308         }
5309
5310         intel_crt_init(dev);
5311
5312         if (HAS_PCH_SPLIT(dev)) {
5313                 int found;
5314
5315                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5316                         /* PCH SDVOB multiplex with HDMIB */
5317                         found = intel_sdvo_init(dev, PCH_SDVOB);
5318                         if (!found)
5319                                 intel_hdmi_init(dev, HDMIB);
5320                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5321                                 intel_dp_init(dev, PCH_DP_B);
5322                 }
5323
5324                 if (I915_READ(HDMIC) & PORT_DETECTED)
5325                         intel_hdmi_init(dev, HDMIC);
5326
5327                 if (I915_READ(HDMID) & PORT_DETECTED)
5328                         intel_hdmi_init(dev, HDMID);
5329
5330                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5331                         intel_dp_init(dev, PCH_DP_C);
5332
5333                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5334                         intel_dp_init(dev, PCH_DP_D);
5335
5336         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5337                 bool found = false;
5338
5339                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5340                         DRM_DEBUG_KMS("probing SDVOB\n");
5341                         found = intel_sdvo_init(dev, SDVOB);
5342                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5343                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5344                                 intel_hdmi_init(dev, SDVOB);
5345                         }
5346
5347                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5348                                 DRM_DEBUG_KMS("probing DP_B\n");
5349                                 intel_dp_init(dev, DP_B);
5350                         }
5351                 }
5352
5353                 /* Before G4X SDVOC doesn't have its own detect register */
5354
5355                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5356                         DRM_DEBUG_KMS("probing SDVOC\n");
5357                         found = intel_sdvo_init(dev, SDVOC);
5358                 }
5359
5360                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5361
5362                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5363                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5364                                 intel_hdmi_init(dev, SDVOC);
5365                         }
5366                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5367                                 DRM_DEBUG_KMS("probing DP_C\n");
5368                                 intel_dp_init(dev, DP_C);
5369                         }
5370                 }
5371
5372                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5373                     (I915_READ(DP_D) & DP_DETECTED)) {
5374                         DRM_DEBUG_KMS("probing DP_D\n");
5375                         intel_dp_init(dev, DP_D);
5376                 }
5377         } else if (IS_GEN2(dev))
5378                 intel_dvo_init(dev);
5379
5380         if (SUPPORTS_TV(dev))
5381                 intel_tv_init(dev);
5382
5383         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5384                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5385
5386                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5387                 encoder->possible_clones = intel_encoder_clones(dev,
5388                                                 intel_encoder->clone_mask);
5389         }
5390 }
5391
5392 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5393 {
5394         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5395
5396         drm_framebuffer_cleanup(fb);
5397         drm_gem_object_unreference_unlocked(intel_fb->obj);
5398
5399         kfree(intel_fb);
5400 }
5401
5402 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5403                                                 struct drm_file *file_priv,
5404                                                 unsigned int *handle)
5405 {
5406         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5407         struct drm_gem_object *object = intel_fb->obj;
5408
5409         return drm_gem_handle_create(file_priv, object, handle);
5410 }
5411
5412 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5413         .destroy = intel_user_framebuffer_destroy,
5414         .create_handle = intel_user_framebuffer_create_handle,
5415 };
5416
5417 int intel_framebuffer_init(struct drm_device *dev,
5418                            struct intel_framebuffer *intel_fb,
5419                            struct drm_mode_fb_cmd *mode_cmd,
5420                            struct drm_gem_object *obj)
5421 {
5422         int ret;
5423
5424         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5425         if (ret) {
5426                 DRM_ERROR("framebuffer init failed %d\n", ret);
5427                 return ret;
5428         }
5429
5430         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5431         intel_fb->obj = obj;
5432         return 0;
5433 }
5434
5435 static struct drm_framebuffer *
5436 intel_user_framebuffer_create(struct drm_device *dev,
5437                               struct drm_file *filp,
5438                               struct drm_mode_fb_cmd *mode_cmd)
5439 {
5440         struct drm_gem_object *obj;
5441         struct intel_framebuffer *intel_fb;
5442         int ret;
5443
5444         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5445         if (!obj)
5446                 return NULL;
5447
5448         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5449         if (!intel_fb)
5450                 return NULL;
5451
5452         ret = intel_framebuffer_init(dev, intel_fb,
5453                                      mode_cmd, obj);
5454         if (ret) {
5455                 drm_gem_object_unreference_unlocked(obj);
5456                 kfree(intel_fb);
5457                 return NULL;
5458         }
5459
5460         return &intel_fb->base;
5461 }
5462
5463 static const struct drm_mode_config_funcs intel_mode_funcs = {
5464         .fb_create = intel_user_framebuffer_create,
5465         .output_poll_changed = intel_fb_output_poll_changed,
5466 };
5467
5468 static struct drm_gem_object *
5469 intel_alloc_context_page(struct drm_device *dev)
5470 {
5471         struct drm_gem_object *ctx;
5472         int ret;
5473
5474         ctx = i915_gem_alloc_object(dev, 4096);
5475         if (!ctx) {
5476                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5477                 return NULL;
5478         }
5479
5480         mutex_lock(&dev->struct_mutex);
5481         ret = i915_gem_object_pin(ctx, 4096);
5482         if (ret) {
5483                 DRM_ERROR("failed to pin power context: %d\n", ret);
5484                 goto err_unref;
5485         }
5486
5487         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5488         if (ret) {
5489                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5490                 goto err_unpin;
5491         }
5492         mutex_unlock(&dev->struct_mutex);
5493
5494         return ctx;
5495
5496 err_unpin:
5497         i915_gem_object_unpin(ctx);
5498 err_unref:
5499         drm_gem_object_unreference(ctx);
5500         mutex_unlock(&dev->struct_mutex);
5501         return NULL;
5502 }
5503
5504 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5505 {
5506         struct drm_i915_private *dev_priv = dev->dev_private;
5507         u16 rgvswctl;
5508
5509         rgvswctl = I915_READ16(MEMSWCTL);
5510         if (rgvswctl & MEMCTL_CMD_STS) {
5511                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5512                 return false; /* still busy with another command */
5513         }
5514
5515         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5516                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5517         I915_WRITE16(MEMSWCTL, rgvswctl);
5518         POSTING_READ16(MEMSWCTL);
5519
5520         rgvswctl |= MEMCTL_CMD_STS;
5521         I915_WRITE16(MEMSWCTL, rgvswctl);
5522
5523         return true;
5524 }
5525
5526 void ironlake_enable_drps(struct drm_device *dev)
5527 {
5528         struct drm_i915_private *dev_priv = dev->dev_private;
5529         u32 rgvmodectl = I915_READ(MEMMODECTL);
5530         u8 fmax, fmin, fstart, vstart;
5531
5532         /* 100ms RC evaluation intervals */
5533         I915_WRITE(RCUPEI, 100000);
5534         I915_WRITE(RCDNEI, 100000);
5535
5536         /* Set max/min thresholds to 90ms and 80ms respectively */
5537         I915_WRITE(RCBMAXAVG, 90000);
5538         I915_WRITE(RCBMINAVG, 80000);
5539
5540         I915_WRITE(MEMIHYST, 1);
5541
5542         /* Set up min, max, and cur for interrupt handling */
5543         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5544         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5545         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5546                 MEMMODE_FSTART_SHIFT;
5547         fstart = fmax;
5548
5549         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5550                 PXVFREQ_PX_SHIFT;
5551
5552         dev_priv->fmax = fstart; /* IPS callback will increase this */
5553         dev_priv->fstart = fstart;
5554
5555         dev_priv->max_delay = fmax;
5556         dev_priv->min_delay = fmin;
5557         dev_priv->cur_delay = fstart;
5558
5559         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5560                          fstart);
5561
5562         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5563
5564         /*
5565          * Interrupts will be enabled in ironlake_irq_postinstall
5566          */
5567
5568         I915_WRITE(VIDSTART, vstart);
5569         POSTING_READ(VIDSTART);
5570
5571         rgvmodectl |= MEMMODE_SWMODE_EN;
5572         I915_WRITE(MEMMODECTL, rgvmodectl);
5573
5574         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5575                 DRM_ERROR("stuck trying to change perf mode\n");
5576         msleep(1);
5577
5578         ironlake_set_drps(dev, fstart);
5579
5580         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5581                 I915_READ(0x112e0);
5582         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5583         dev_priv->last_count2 = I915_READ(0x112f4);
5584         getrawmonotonic(&dev_priv->last_time2);
5585 }
5586
5587 void ironlake_disable_drps(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590         u16 rgvswctl = I915_READ16(MEMSWCTL);
5591
5592         /* Ack interrupts, disable EFC interrupt */
5593         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5594         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5595         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5596         I915_WRITE(DEIIR, DE_PCU_EVENT);
5597         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5598
5599         /* Go back to the starting frequency */
5600         ironlake_set_drps(dev, dev_priv->fstart);
5601         msleep(1);
5602         rgvswctl |= MEMCTL_CMD_STS;
5603         I915_WRITE(MEMSWCTL, rgvswctl);
5604         msleep(1);
5605
5606 }
5607
5608 static unsigned long intel_pxfreq(u32 vidfreq)
5609 {
5610         unsigned long freq;
5611         int div = (vidfreq & 0x3f0000) >> 16;
5612         int post = (vidfreq & 0x3000) >> 12;
5613         int pre = (vidfreq & 0x7);
5614
5615         if (!pre)
5616                 return 0;
5617
5618         freq = ((div * 133333) / ((1<<post) * pre));
5619
5620         return freq;
5621 }
5622
5623 void intel_init_emon(struct drm_device *dev)
5624 {
5625         struct drm_i915_private *dev_priv = dev->dev_private;
5626         u32 lcfuse;
5627         u8 pxw[16];
5628         int i;
5629
5630         /* Disable to program */
5631         I915_WRITE(ECR, 0);
5632         POSTING_READ(ECR);
5633
5634         /* Program energy weights for various events */
5635         I915_WRITE(SDEW, 0x15040d00);
5636         I915_WRITE(CSIEW0, 0x007f0000);
5637         I915_WRITE(CSIEW1, 0x1e220004);
5638         I915_WRITE(CSIEW2, 0x04000004);
5639
5640         for (i = 0; i < 5; i++)
5641                 I915_WRITE(PEW + (i * 4), 0);
5642         for (i = 0; i < 3; i++)
5643                 I915_WRITE(DEW + (i * 4), 0);
5644
5645         /* Program P-state weights to account for frequency power adjustment */
5646         for (i = 0; i < 16; i++) {
5647                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5648                 unsigned long freq = intel_pxfreq(pxvidfreq);
5649                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5650                         PXVFREQ_PX_SHIFT;
5651                 unsigned long val;
5652
5653                 val = vid * vid;
5654                 val *= (freq / 1000);
5655                 val *= 255;
5656                 val /= (127*127*900);
5657                 if (val > 0xff)
5658                         DRM_ERROR("bad pxval: %ld\n", val);
5659                 pxw[i] = val;
5660         }
5661         /* Render standby states get 0 weight */
5662         pxw[14] = 0;
5663         pxw[15] = 0;
5664
5665         for (i = 0; i < 4; i++) {
5666                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5667                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5668                 I915_WRITE(PXW + (i * 4), val);
5669         }
5670
5671         /* Adjust magic regs to magic values (more experimental results) */
5672         I915_WRITE(OGW0, 0);
5673         I915_WRITE(OGW1, 0);
5674         I915_WRITE(EG0, 0x00007f00);
5675         I915_WRITE(EG1, 0x0000000e);
5676         I915_WRITE(EG2, 0x000e0000);
5677         I915_WRITE(EG3, 0x68000300);
5678         I915_WRITE(EG4, 0x42000000);
5679         I915_WRITE(EG5, 0x00140031);
5680         I915_WRITE(EG6, 0);
5681         I915_WRITE(EG7, 0);
5682
5683         for (i = 0; i < 8; i++)
5684                 I915_WRITE(PXWL + (i * 4), 0);
5685
5686         /* Enable PMON + select events */
5687         I915_WRITE(ECR, 0x80000019);
5688
5689         lcfuse = I915_READ(LCFUSE02);
5690
5691         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5692 }
5693
5694 void intel_init_clock_gating(struct drm_device *dev)
5695 {
5696         struct drm_i915_private *dev_priv = dev->dev_private;
5697
5698         /*
5699          * Disable clock gating reported to work incorrectly according to the
5700          * specs, but enable as much else as we can.
5701          */
5702         if (HAS_PCH_SPLIT(dev)) {
5703                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5704
5705                 if (IS_IRONLAKE(dev)) {
5706                         /* Required for FBC */
5707                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5708                         /* Required for CxSR */
5709                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5710
5711                         I915_WRITE(PCH_3DCGDIS0,
5712                                    MARIUNIT_CLOCK_GATE_DISABLE |
5713                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5714                 }
5715
5716                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5717
5718                 /*
5719                  * According to the spec the following bits should be set in
5720                  * order to enable memory self-refresh
5721                  * The bit 22/21 of 0x42004
5722                  * The bit 5 of 0x42020
5723                  * The bit 15 of 0x45000
5724                  */
5725                 if (IS_IRONLAKE(dev)) {
5726                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5727                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5728                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5729                         I915_WRITE(ILK_DSPCLK_GATE,
5730                                         (I915_READ(ILK_DSPCLK_GATE) |
5731                                                 ILK_DPARB_CLK_GATE));
5732                         I915_WRITE(DISP_ARB_CTL,
5733                                         (I915_READ(DISP_ARB_CTL) |
5734                                                 DISP_FBC_WM_DIS));
5735                 }
5736                 /*
5737                  * Based on the document from hardware guys the following bits
5738                  * should be set unconditionally in order to enable FBC.
5739                  * The bit 22 of 0x42000
5740                  * The bit 22 of 0x42004
5741                  * The bit 7,8,9 of 0x42020.
5742                  */
5743                 if (IS_IRONLAKE_M(dev)) {
5744                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5745                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5746                                    ILK_FBCQ_DIS);
5747                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5748                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5749                                    ILK_DPARB_GATE);
5750                         I915_WRITE(ILK_DSPCLK_GATE,
5751                                    I915_READ(ILK_DSPCLK_GATE) |
5752                                    ILK_DPFC_DIS1 |
5753                                    ILK_DPFC_DIS2 |
5754                                    ILK_CLK_FBC);
5755                 }
5756                 if (IS_GEN6(dev))
5757                         return;
5758         } else if (IS_G4X(dev)) {
5759                 uint32_t dspclk_gate;
5760                 I915_WRITE(RENCLK_GATE_D1, 0);
5761                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5762                        GS_UNIT_CLOCK_GATE_DISABLE |
5763                        CL_UNIT_CLOCK_GATE_DISABLE);
5764                 I915_WRITE(RAMCLK_GATE_D, 0);
5765                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5766                         OVRUNIT_CLOCK_GATE_DISABLE |
5767                         OVCUNIT_CLOCK_GATE_DISABLE;
5768                 if (IS_GM45(dev))
5769                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5770                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5771         } else if (IS_I965GM(dev)) {
5772                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5773                 I915_WRITE(RENCLK_GATE_D2, 0);
5774                 I915_WRITE(DSPCLK_GATE_D, 0);
5775                 I915_WRITE(RAMCLK_GATE_D, 0);
5776                 I915_WRITE16(DEUC, 0);
5777         } else if (IS_I965G(dev)) {
5778                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5779                        I965_RCC_CLOCK_GATE_DISABLE |
5780                        I965_RCPB_CLOCK_GATE_DISABLE |
5781                        I965_ISC_CLOCK_GATE_DISABLE |
5782                        I965_FBC_CLOCK_GATE_DISABLE);
5783                 I915_WRITE(RENCLK_GATE_D2, 0);
5784         } else if (IS_I9XX(dev)) {
5785                 u32 dstate = I915_READ(D_STATE);
5786
5787                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5788                         DSTATE_DOT_CLOCK_GATING;
5789                 I915_WRITE(D_STATE, dstate);
5790         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5791                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5792         } else if (IS_I830(dev)) {
5793                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5794         }
5795
5796         /*
5797          * GPU can automatically power down the render unit if given a page
5798          * to save state.
5799          */
5800         if (IS_IRONLAKE_M(dev)) {
5801                 if (dev_priv->renderctx == NULL)
5802                         dev_priv->renderctx = intel_alloc_context_page(dev);
5803                 if (dev_priv->renderctx) {
5804                         struct drm_i915_gem_object *obj_priv;
5805                         obj_priv = to_intel_bo(dev_priv->renderctx);
5806                         if (obj_priv) {
5807                                 BEGIN_LP_RING(4);
5808                                 OUT_RING(MI_SET_CONTEXT);
5809                                 OUT_RING(obj_priv->gtt_offset |
5810                                                 MI_MM_SPACE_GTT |
5811                                                 MI_SAVE_EXT_STATE_EN |
5812                                                 MI_RESTORE_EXT_STATE_EN |
5813                                                 MI_RESTORE_INHIBIT);
5814                                 OUT_RING(MI_NOOP);
5815                                 OUT_RING(MI_FLUSH);
5816                                 ADVANCE_LP_RING();
5817                         }
5818                 } else {
5819                         DRM_DEBUG_KMS("Failed to allocate render context."
5820                                       "Disable RC6\n");
5821                         return;
5822                 }
5823         }
5824
5825         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5826                 struct drm_i915_gem_object *obj_priv = NULL;
5827
5828                 if (dev_priv->pwrctx) {
5829                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5830                 } else {
5831                         struct drm_gem_object *pwrctx;
5832
5833                         pwrctx = intel_alloc_context_page(dev);
5834                         if (pwrctx) {
5835                                 dev_priv->pwrctx = pwrctx;
5836                                 obj_priv = to_intel_bo(pwrctx);
5837                         }
5838                 }
5839
5840                 if (obj_priv) {
5841                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5842                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5843                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5844                 }
5845         }
5846 }
5847
5848 /* Set up chip specific display functions */
5849 static void intel_init_display(struct drm_device *dev)
5850 {
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852
5853         /* We always want a DPMS function */
5854         if (HAS_PCH_SPLIT(dev))
5855                 dev_priv->display.dpms = ironlake_crtc_dpms;
5856         else
5857                 dev_priv->display.dpms = i9xx_crtc_dpms;
5858
5859         if (I915_HAS_FBC(dev)) {
5860                 if (IS_IRONLAKE_M(dev)) {
5861                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5862                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5863                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5864                 } else if (IS_GM45(dev)) {
5865                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5866                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5867                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5868                 } else if (IS_I965GM(dev)) {
5869                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5870                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5871                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5872                 }
5873                 /* 855GM needs testing */
5874         }
5875
5876         /* Returns the core display clock speed */
5877         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5878                 dev_priv->display.get_display_clock_speed =
5879                         i945_get_display_clock_speed;
5880         else if (IS_I915G(dev))
5881                 dev_priv->display.get_display_clock_speed =
5882                         i915_get_display_clock_speed;
5883         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5884                 dev_priv->display.get_display_clock_speed =
5885                         i9xx_misc_get_display_clock_speed;
5886         else if (IS_I915GM(dev))
5887                 dev_priv->display.get_display_clock_speed =
5888                         i915gm_get_display_clock_speed;
5889         else if (IS_I865G(dev))
5890                 dev_priv->display.get_display_clock_speed =
5891                         i865_get_display_clock_speed;
5892         else if (IS_I85X(dev))
5893                 dev_priv->display.get_display_clock_speed =
5894                         i855_get_display_clock_speed;
5895         else /* 852, 830 */
5896                 dev_priv->display.get_display_clock_speed =
5897                         i830_get_display_clock_speed;
5898
5899         /* For FIFO watermark updates */
5900         if (HAS_PCH_SPLIT(dev)) {
5901                 if (IS_IRONLAKE(dev)) {
5902                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5903                                 dev_priv->display.update_wm = ironlake_update_wm;
5904                         else {
5905                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5906                                               "Disable CxSR\n");
5907                                 dev_priv->display.update_wm = NULL;
5908                         }
5909                 } else
5910                         dev_priv->display.update_wm = NULL;
5911         } else if (IS_PINEVIEW(dev)) {
5912                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5913                                             dev_priv->is_ddr3,
5914                                             dev_priv->fsb_freq,
5915                                             dev_priv->mem_freq)) {
5916                         DRM_INFO("failed to find known CxSR latency "
5917                                  "(found ddr%s fsb freq %d, mem freq %d), "
5918                                  "disabling CxSR\n",
5919                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5920                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5921                         /* Disable CxSR and never update its watermark again */
5922                         pineview_disable_cxsr(dev);
5923                         dev_priv->display.update_wm = NULL;
5924                 } else
5925                         dev_priv->display.update_wm = pineview_update_wm;
5926         } else if (IS_G4X(dev))
5927                 dev_priv->display.update_wm = g4x_update_wm;
5928         else if (IS_I965G(dev))
5929                 dev_priv->display.update_wm = i965_update_wm;
5930         else if (IS_I9XX(dev)) {
5931                 dev_priv->display.update_wm = i9xx_update_wm;
5932                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5933         } else if (IS_I85X(dev)) {
5934                 dev_priv->display.update_wm = i9xx_update_wm;
5935                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5936         } else {
5937                 dev_priv->display.update_wm = i830_update_wm;
5938                 if (IS_845G(dev))
5939                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5940                 else
5941                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5942         }
5943 }
5944
5945 /*
5946  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5947  * resume, or other times.  This quirk makes sure that's the case for
5948  * affected systems.
5949  */
5950 static void quirk_pipea_force (struct drm_device *dev)
5951 {
5952         struct drm_i915_private *dev_priv = dev->dev_private;
5953
5954         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5955         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5956 }
5957
5958 struct intel_quirk {
5959         int device;
5960         int subsystem_vendor;
5961         int subsystem_device;
5962         void (*hook)(struct drm_device *dev);
5963 };
5964
5965 struct intel_quirk intel_quirks[] = {
5966         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5967         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5968         /* HP Mini needs pipe A force quirk (LP: #322104) */
5969         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5970
5971         /* Thinkpad R31 needs pipe A force quirk */
5972         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5973         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5974         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5975
5976         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5977         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5978         /* ThinkPad X40 needs pipe A force quirk */
5979
5980         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5981         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5982
5983         /* 855 & before need to leave pipe A & dpll A up */
5984         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5985         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5986 };
5987
5988 static void intel_init_quirks(struct drm_device *dev)
5989 {
5990         struct pci_dev *d = dev->pdev;
5991         int i;
5992
5993         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5994                 struct intel_quirk *q = &intel_quirks[i];
5995
5996                 if (d->device == q->device &&
5997                     (d->subsystem_vendor == q->subsystem_vendor ||
5998                      q->subsystem_vendor == PCI_ANY_ID) &&
5999                     (d->subsystem_device == q->subsystem_device ||
6000                      q->subsystem_device == PCI_ANY_ID))
6001                         q->hook(dev);
6002         }
6003 }
6004
6005 void intel_modeset_init(struct drm_device *dev)
6006 {
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008         int i;
6009
6010         drm_mode_config_init(dev);
6011
6012         dev->mode_config.min_width = 0;
6013         dev->mode_config.min_height = 0;
6014
6015         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6016
6017         intel_init_quirks(dev);
6018
6019         intel_init_display(dev);
6020
6021         if (IS_I965G(dev)) {
6022                 dev->mode_config.max_width = 8192;
6023                 dev->mode_config.max_height = 8192;
6024         } else if (IS_I9XX(dev)) {
6025                 dev->mode_config.max_width = 4096;
6026                 dev->mode_config.max_height = 4096;
6027         } else {
6028                 dev->mode_config.max_width = 2048;
6029                 dev->mode_config.max_height = 2048;
6030         }
6031
6032         /* set memory base */
6033         if (IS_I9XX(dev))
6034                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6035         else
6036                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6037
6038         if (IS_MOBILE(dev) || IS_I9XX(dev))
6039                 dev_priv->num_pipe = 2;
6040         else
6041                 dev_priv->num_pipe = 1;
6042         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6043                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6044
6045         for (i = 0; i < dev_priv->num_pipe; i++) {
6046                 intel_crtc_init(dev, i);
6047         }
6048
6049         intel_setup_outputs(dev);
6050
6051         intel_init_clock_gating(dev);
6052
6053         if (IS_IRONLAKE_M(dev)) {
6054                 ironlake_enable_drps(dev);
6055                 intel_init_emon(dev);
6056         }
6057
6058         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6059         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6060                     (unsigned long)dev);
6061
6062         intel_setup_overlay(dev);
6063 }
6064
6065 void intel_modeset_cleanup(struct drm_device *dev)
6066 {
6067         struct drm_i915_private *dev_priv = dev->dev_private;
6068         struct drm_crtc *crtc;
6069         struct intel_crtc *intel_crtc;
6070
6071         mutex_lock(&dev->struct_mutex);
6072
6073         drm_kms_helper_poll_fini(dev);
6074         intel_fbdev_fini(dev);
6075
6076         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6077                 /* Skip inactive CRTCs */
6078                 if (!crtc->fb)
6079                         continue;
6080
6081                 intel_crtc = to_intel_crtc(crtc);
6082                 intel_increase_pllclock(crtc, false);
6083                 del_timer_sync(&intel_crtc->idle_timer);
6084         }
6085
6086         del_timer_sync(&dev_priv->idle_timer);
6087
6088         if (dev_priv->display.disable_fbc)
6089                 dev_priv->display.disable_fbc(dev);
6090
6091         if (dev_priv->renderctx) {
6092                 struct drm_i915_gem_object *obj_priv;
6093
6094                 obj_priv = to_intel_bo(dev_priv->renderctx);
6095                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6096                 I915_READ(CCID);
6097                 i915_gem_object_unpin(dev_priv->renderctx);
6098                 drm_gem_object_unreference(dev_priv->renderctx);
6099         }
6100
6101         if (dev_priv->pwrctx) {
6102                 struct drm_i915_gem_object *obj_priv;
6103
6104                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6105                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6106                 I915_READ(PWRCTXA);
6107                 i915_gem_object_unpin(dev_priv->pwrctx);
6108                 drm_gem_object_unreference(dev_priv->pwrctx);
6109         }
6110
6111         if (IS_IRONLAKE_M(dev))
6112                 ironlake_disable_drps(dev);
6113
6114         mutex_unlock(&dev->struct_mutex);
6115
6116         drm_mode_config_cleanup(dev);
6117 }
6118
6119
6120 /*
6121  * Return which encoder is currently attached for connector.
6122  */
6123 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6124 {
6125         struct drm_mode_object *obj;
6126         struct drm_encoder *encoder;
6127         int i;
6128
6129         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6130                 if (connector->encoder_ids[i] == 0)
6131                         break;
6132
6133                 obj = drm_mode_object_find(connector->dev,
6134                                            connector->encoder_ids[i],
6135                                            DRM_MODE_OBJECT_ENCODER);
6136                 if (!obj)
6137                         continue;
6138
6139                 encoder = obj_to_encoder(obj);
6140                 return encoder;
6141         }
6142         return NULL;
6143 }
6144
6145 /*
6146  * set vga decode state - true == enable VGA decode
6147  */
6148 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6149 {
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         u16 gmch_ctrl;
6152
6153         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6154         if (state)
6155                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6156         else
6157                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6158         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6159         return 0;
6160 }