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1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/i2c.h>
28 #include <linux/slab.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc.h"
32 #include "drm_crtc_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36
37 static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
38 {
39         struct drm_device *dev = encoder->dev;
40         struct drm_i915_private *dev_priv = dev->dev_private;
41         u32 temp, reg;
42
43         if (HAS_PCH_SPLIT(dev))
44                 reg = PCH_ADPA;
45         else
46                 reg = ADPA;
47
48         temp = I915_READ(reg);
49         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
50         temp &= ~ADPA_DAC_ENABLE;
51
52         switch(mode) {
53         case DRM_MODE_DPMS_ON:
54                 temp |= ADPA_DAC_ENABLE;
55                 break;
56         case DRM_MODE_DPMS_STANDBY:
57                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
58                 break;
59         case DRM_MODE_DPMS_SUSPEND:
60                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
61                 break;
62         case DRM_MODE_DPMS_OFF:
63                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
64                 break;
65         }
66
67         I915_WRITE(reg, temp);
68 }
69
70 static int intel_crt_mode_valid(struct drm_connector *connector,
71                                 struct drm_display_mode *mode)
72 {
73         struct drm_device *dev = connector->dev;
74
75         int max_clock = 0;
76         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
77                 return MODE_NO_DBLESCAN;
78
79         if (mode->clock < 25000)
80                 return MODE_CLOCK_LOW;
81
82         if (!IS_I9XX(dev))
83                 max_clock = 350000;
84         else
85                 max_clock = 400000;
86         if (mode->clock > max_clock)
87                 return MODE_CLOCK_HIGH;
88
89         return MODE_OK;
90 }
91
92 static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
93                                  struct drm_display_mode *mode,
94                                  struct drm_display_mode *adjusted_mode)
95 {
96         return true;
97 }
98
99 static void intel_crt_mode_set(struct drm_encoder *encoder,
100                                struct drm_display_mode *mode,
101                                struct drm_display_mode *adjusted_mode)
102 {
103
104         struct drm_device *dev = encoder->dev;
105         struct drm_crtc *crtc = encoder->crtc;
106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
107         struct drm_i915_private *dev_priv = dev->dev_private;
108         int dpll_md_reg;
109         u32 adpa, dpll_md;
110         u32 adpa_reg;
111
112         if (intel_crtc->pipe == 0)
113                 dpll_md_reg = DPLL_A_MD;
114         else
115                 dpll_md_reg = DPLL_B_MD;
116
117         if (HAS_PCH_SPLIT(dev))
118                 adpa_reg = PCH_ADPA;
119         else
120                 adpa_reg = ADPA;
121
122         /*
123          * Disable separate mode multiplier used when cloning SDVO to CRT
124          * XXX this needs to be adjusted when we really are cloning
125          */
126         if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
127                 dpll_md = I915_READ(dpll_md_reg);
128                 I915_WRITE(dpll_md_reg,
129                            dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
130         }
131
132         adpa = 0;
133         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
134                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
135         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
136                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
137
138         if (intel_crtc->pipe == 0) {
139                 if (HAS_PCH_CPT(dev))
140                         adpa |= PORT_TRANS_A_SEL_CPT;
141                 else
142                         adpa |= ADPA_PIPE_A_SELECT;
143                 if (!HAS_PCH_SPLIT(dev))
144                         I915_WRITE(BCLRPAT_A, 0);
145         } else {
146                 if (HAS_PCH_CPT(dev))
147                         adpa |= PORT_TRANS_B_SEL_CPT;
148                 else
149                         adpa |= ADPA_PIPE_B_SELECT;
150                 if (!HAS_PCH_SPLIT(dev))
151                         I915_WRITE(BCLRPAT_B, 0);
152         }
153
154         I915_WRITE(adpa_reg, adpa);
155 }
156
157 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
158 {
159         struct drm_device *dev = connector->dev;
160         struct drm_i915_private *dev_priv = dev->dev_private;
161         u32 adpa, temp;
162         bool ret;
163
164         temp = adpa = I915_READ(PCH_ADPA);
165
166         if (HAS_PCH_CPT(dev)) {
167                 /* Disable DAC before force detect */
168                 I915_WRITE(PCH_ADPA, adpa & ~ADPA_DAC_ENABLE);
169                 (void)I915_READ(PCH_ADPA);
170         } else {
171                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
172                 /* disable HPD first */
173                 I915_WRITE(PCH_ADPA, adpa);
174                 (void)I915_READ(PCH_ADPA);
175         }
176
177         adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
178                         ADPA_CRT_HOTPLUG_WARMUP_10MS |
179                         ADPA_CRT_HOTPLUG_SAMPLE_4S |
180                         ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
181                         ADPA_CRT_HOTPLUG_VOLREF_325MV |
182                         ADPA_CRT_HOTPLUG_ENABLE |
183                         ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
184
185         DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
186         I915_WRITE(PCH_ADPA, adpa);
187
188         if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
189                      1000, 1))
190                 DRM_ERROR("timed out waiting for FORCE_TRIGGER");
191
192         if (HAS_PCH_CPT(dev)) {
193                 I915_WRITE(PCH_ADPA, temp);
194                 (void)I915_READ(PCH_ADPA);
195         }
196
197         /* Check the status to see if both blue and green are on now */
198         adpa = I915_READ(PCH_ADPA);
199         adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
200         if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
201                 (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
202                 ret = true;
203         else
204                 ret = false;
205
206         return ret;
207 }
208
209 /**
210  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
211  *
212  * Not for i915G/i915GM
213  *
214  * \return true if CRT is connected.
215  * \return false if CRT is disconnected.
216  */
217 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
218 {
219         struct drm_device *dev = connector->dev;
220         struct drm_i915_private *dev_priv = dev->dev_private;
221         u32 hotplug_en, orig, stat;
222         bool ret = false;
223         int i, tries = 0;
224
225         if (HAS_PCH_SPLIT(dev))
226                 return intel_ironlake_crt_detect_hotplug(connector);
227
228         /*
229          * On 4 series desktop, CRT detect sequence need to be done twice
230          * to get a reliable result.
231          */
232
233         if (IS_G4X(dev) && !IS_GM45(dev))
234                 tries = 2;
235         else
236                 tries = 1;
237         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
238         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
239
240         for (i = 0; i < tries ; i++) {
241                 /* turn on the FORCE_DETECT */
242                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
243                 /* wait for FORCE_DETECT to go off */
244                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
245                               CRT_HOTPLUG_FORCE_DETECT) == 0,
246                              1000, 1))
247                         DRM_ERROR("timed out waiting for FORCE_DETECT to go off");
248         }
249
250         stat = I915_READ(PORT_HOTPLUG_STAT);
251         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
252                 ret = true;
253
254         /* clear the interrupt we just generated, if any */
255         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
256
257         /* and put the bits back */
258         I915_WRITE(PORT_HOTPLUG_EN, orig);
259
260         return ret;
261 }
262
263 static bool intel_crt_detect_ddc(struct drm_encoder *encoder)
264 {
265         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
266
267         /* CRT should always be at 0, but check anyway */
268         if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
269                 return false;
270
271         return intel_ddc_probe(intel_encoder);
272 }
273
274 static enum drm_connector_status
275 intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
276 {
277         struct drm_encoder *encoder = &intel_encoder->enc;
278         struct drm_device *dev = encoder->dev;
279         struct drm_i915_private *dev_priv = dev->dev_private;
280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
281         uint32_t pipe = intel_crtc->pipe;
282         uint32_t save_bclrpat;
283         uint32_t save_vtotal;
284         uint32_t vtotal, vactive;
285         uint32_t vsample;
286         uint32_t vblank, vblank_start, vblank_end;
287         uint32_t dsl;
288         uint32_t bclrpat_reg;
289         uint32_t vtotal_reg;
290         uint32_t vblank_reg;
291         uint32_t vsync_reg;
292         uint32_t pipeconf_reg;
293         uint32_t pipe_dsl_reg;
294         uint8_t st00;
295         enum drm_connector_status status;
296
297         if (pipe == 0) {
298                 bclrpat_reg = BCLRPAT_A;
299                 vtotal_reg = VTOTAL_A;
300                 vblank_reg = VBLANK_A;
301                 vsync_reg = VSYNC_A;
302                 pipeconf_reg = PIPEACONF;
303                 pipe_dsl_reg = PIPEADSL;
304         } else {
305                 bclrpat_reg = BCLRPAT_B;
306                 vtotal_reg = VTOTAL_B;
307                 vblank_reg = VBLANK_B;
308                 vsync_reg = VSYNC_B;
309                 pipeconf_reg = PIPEBCONF;
310                 pipe_dsl_reg = PIPEBDSL;
311         }
312
313         save_bclrpat = I915_READ(bclrpat_reg);
314         save_vtotal = I915_READ(vtotal_reg);
315         vblank = I915_READ(vblank_reg);
316
317         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
318         vactive = (save_vtotal & 0x7ff) + 1;
319
320         vblank_start = (vblank & 0xfff) + 1;
321         vblank_end = ((vblank >> 16) & 0xfff) + 1;
322
323         /* Set the border color to purple. */
324         I915_WRITE(bclrpat_reg, 0x500050);
325
326         if (IS_I9XX(dev)) {
327                 uint32_t pipeconf = I915_READ(pipeconf_reg);
328                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
329                 /* Wait for next Vblank to substitue
330                  * border color for Color info */
331                 intel_wait_for_vblank(dev);
332                 st00 = I915_READ8(VGA_MSR_WRITE);
333                 status = ((st00 & (1 << 4)) != 0) ?
334                         connector_status_connected :
335                         connector_status_disconnected;
336
337                 I915_WRITE(pipeconf_reg, pipeconf);
338         } else {
339                 bool restore_vblank = false;
340                 int count, detect;
341
342                 /*
343                 * If there isn't any border, add some.
344                 * Yes, this will flicker
345                 */
346                 if (vblank_start <= vactive && vblank_end >= vtotal) {
347                         uint32_t vsync = I915_READ(vsync_reg);
348                         uint32_t vsync_start = (vsync & 0xffff) + 1;
349
350                         vblank_start = vsync_start;
351                         I915_WRITE(vblank_reg,
352                                    (vblank_start - 1) |
353                                    ((vblank_end - 1) << 16));
354                         restore_vblank = true;
355                 }
356                 /* sample in the vertical border, selecting the larger one */
357                 if (vblank_start - vactive >= vtotal - vblank_end)
358                         vsample = (vblank_start + vactive) >> 1;
359                 else
360                         vsample = (vtotal + vblank_end) >> 1;
361
362                 /*
363                  * Wait for the border to be displayed
364                  */
365                 while (I915_READ(pipe_dsl_reg) >= vactive)
366                         ;
367                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
368                         ;
369                 /*
370                  * Watch ST00 for an entire scanline
371                  */
372                 detect = 0;
373                 count = 0;
374                 do {
375                         count++;
376                         /* Read the ST00 VGA status register */
377                         st00 = I915_READ8(VGA_MSR_WRITE);
378                         if (st00 & (1 << 4))
379                                 detect++;
380                 } while ((I915_READ(pipe_dsl_reg) == dsl));
381
382                 /* restore vblank if necessary */
383                 if (restore_vblank)
384                         I915_WRITE(vblank_reg, vblank);
385                 /*
386                  * If more than 3/4 of the scanline detected a monitor,
387                  * then it is assumed to be present. This works even on i830,
388                  * where there isn't any way to force the border color across
389                  * the screen
390                  */
391                 status = detect * 4 > count * 3 ?
392                          connector_status_connected :
393                          connector_status_disconnected;
394         }
395
396         /* Restore previous settings */
397         I915_WRITE(bclrpat_reg, save_bclrpat);
398
399         return status;
400 }
401
402 static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
403 {
404         struct drm_device *dev = connector->dev;
405         struct drm_encoder *encoder = intel_attached_encoder(connector);
406         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
407         struct drm_crtc *crtc;
408         int dpms_mode;
409         enum drm_connector_status status;
410
411         if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
412                 if (intel_crt_detect_hotplug(connector))
413                         return connector_status_connected;
414                 else
415                         return connector_status_disconnected;
416         }
417
418         if (intel_crt_detect_ddc(encoder))
419                 return connector_status_connected;
420
421         /* for pre-945g platforms use load detect */
422         if (encoder->crtc && encoder->crtc->enabled) {
423                 status = intel_crt_load_detect(encoder->crtc, intel_encoder);
424         } else {
425                 crtc = intel_get_load_detect_pipe(intel_encoder, connector,
426                                                   NULL, &dpms_mode);
427                 if (crtc) {
428                         status = intel_crt_load_detect(crtc, intel_encoder);
429                         intel_release_load_detect_pipe(intel_encoder,
430                                                        connector, dpms_mode);
431                 } else
432                         status = connector_status_unknown;
433         }
434
435         return status;
436 }
437
438 static void intel_crt_destroy(struct drm_connector *connector)
439 {
440         drm_sysfs_connector_remove(connector);
441         drm_connector_cleanup(connector);
442         kfree(connector);
443 }
444
445 static int intel_crt_get_modes(struct drm_connector *connector)
446 {
447         int ret;
448         struct drm_encoder *encoder = intel_attached_encoder(connector);
449         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
450         struct i2c_adapter *ddc_bus;
451         struct drm_device *dev = connector->dev;
452
453
454         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
455         if (ret || !IS_G4X(dev))
456                 goto end;
457
458         /* Try to probe digital port for output in DVI-I -> VGA mode. */
459         ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
460
461         if (!ddc_bus) {
462                 dev_printk(KERN_ERR, &connector->dev->pdev->dev,
463                            "DDC bus registration failed for CRTDDC_D.\n");
464                 goto end;
465         }
466         /* Try to get modes by GPIOD port */
467         ret = intel_ddc_get_modes(connector, ddc_bus);
468         intel_i2c_destroy(ddc_bus);
469
470 end:
471         return ret;
472
473 }
474
475 static int intel_crt_set_property(struct drm_connector *connector,
476                                   struct drm_property *property,
477                                   uint64_t value)
478 {
479         return 0;
480 }
481
482 /*
483  * Routines for controlling stuff on the analog port
484  */
485
486 static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
487         .dpms = intel_crt_dpms,
488         .mode_fixup = intel_crt_mode_fixup,
489         .prepare = intel_encoder_prepare,
490         .commit = intel_encoder_commit,
491         .mode_set = intel_crt_mode_set,
492 };
493
494 static const struct drm_connector_funcs intel_crt_connector_funcs = {
495         .dpms = drm_helper_connector_dpms,
496         .detect = intel_crt_detect,
497         .fill_modes = drm_helper_probe_single_connector_modes,
498         .destroy = intel_crt_destroy,
499         .set_property = intel_crt_set_property,
500 };
501
502 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
503         .mode_valid = intel_crt_mode_valid,
504         .get_modes = intel_crt_get_modes,
505         .best_encoder = intel_attached_encoder,
506 };
507
508 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
509         .destroy = intel_encoder_destroy,
510 };
511
512 void intel_crt_init(struct drm_device *dev)
513 {
514         struct drm_connector *connector;
515         struct intel_encoder *intel_encoder;
516         struct intel_connector *intel_connector;
517         struct drm_i915_private *dev_priv = dev->dev_private;
518         u32 i2c_reg;
519
520         intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
521         if (!intel_encoder)
522                 return;
523
524         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
525         if (!intel_connector) {
526                 kfree(intel_encoder);
527                 return;
528         }
529
530         connector = &intel_connector->base;
531         drm_connector_init(dev, &intel_connector->base,
532                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
533
534         drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs,
535                          DRM_MODE_ENCODER_DAC);
536
537         drm_mode_connector_attach_encoder(&intel_connector->base,
538                                           &intel_encoder->enc);
539
540         /* Set up the DDC bus. */
541         if (HAS_PCH_SPLIT(dev))
542                 i2c_reg = PCH_GPIOA;
543         else {
544                 i2c_reg = GPIOA;
545                 /* Use VBT information for CRT DDC if available */
546                 if (dev_priv->crt_ddc_bus != 0)
547                         i2c_reg = dev_priv->crt_ddc_bus;
548         }
549         intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
550         if (!intel_encoder->ddc_bus) {
551                 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
552                            "failed.\n");
553                 return;
554         }
555
556         intel_encoder->type = INTEL_OUTPUT_ANALOG;
557         intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
558                                    (1 << INTEL_ANALOG_CLONE_BIT) |
559                                    (1 << INTEL_SDVO_LVDS_CLONE_BIT);
560         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
561         connector->interlace_allowed = 1;
562         connector->doublescan_allowed = 0;
563
564         drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
565         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
566
567         drm_sysfs_connector_add(connector);
568
569         if (I915_HAS_HOTPLUG(dev))
570                 connector->polled = DRM_CONNECTOR_POLL_HPD;
571         else
572                 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
573
574         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
575 }