2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
58 #include <asm/msidef.h>
59 #include <asm/hypertransport.h>
60 #include <asm/setup.h>
61 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
72 * Is the SiS APIC rmw bug present ?
73 * -1 = don't know, 0 = no, 1 = yes
75 int sis_apic_bug = -1;
77 static DEFINE_RAW_SPINLOCK(ioapic_lock);
78 static DEFINE_RAW_SPINLOCK(vector_lock);
81 * # of IRQ routing registers
83 int nr_ioapic_registers[MAX_IO_APICS];
85 /* I/O APIC entries */
86 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
89 /* IO APIC gsi routing info */
90 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
92 /* The one past the highest gsi number used */
95 /* MP IRQ source entries */
96 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
98 /* # of MP IRQ source entries */
102 static int nr_irqs_gsi = NR_IRQS_LEGACY;
104 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
105 int mp_bus_id_to_type[MAX_MP_BUSSES];
108 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
110 int skip_ioapic_setup;
112 void arch_disable_smp_support(void)
116 noioapicreroute = -1;
118 skip_ioapic_setup = 1;
121 static int __init parse_noapic(char *str)
123 /* disable IO-APIC */
124 arch_disable_smp_support();
127 early_param("noapic", parse_noapic);
129 struct irq_pin_list {
131 struct irq_pin_list *next;
134 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
136 struct irq_pin_list *pin;
138 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
143 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
144 #ifdef CONFIG_SPARSE_IRQ
145 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
147 static struct irq_cfg irq_cfgx[NR_IRQS];
150 int __init arch_early_irq_init(void)
155 if (!legacy_pic->nr_legacy_irqs) {
161 count = ARRAY_SIZE(irq_cfgx);
162 node = cpu_to_node(0);
164 for (i = 0; i < count; i++) {
165 set_irq_chip_data(i, &cfg[i]);
166 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
167 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
169 * For legacy IRQ's, start with assigning irq0 to irq15 to
170 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
172 if (i < legacy_pic->nr_legacy_irqs) {
173 cfg[i].vector = IRQ0_VECTOR + i;
174 cpumask_set_cpu(0, cfg[i].domain);
181 #ifdef CONFIG_SPARSE_IRQ
182 struct irq_cfg *irq_cfg(unsigned int irq)
184 return get_irq_chip_data(irq);
187 static struct irq_cfg *get_one_free_irq_cfg(int node)
191 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
193 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
196 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
198 free_cpumask_var(cfg->domain);
207 int arch_init_chip_data(struct irq_desc *desc, int node)
211 cfg = get_irq_desc_chip_data(desc);
213 cfg = get_one_free_irq_cfg(node);
214 desc->chip_data = cfg;
216 printk(KERN_ERR "can not alloc irq_cfg\n");
224 /* for move_irq_desc */
226 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
228 struct irq_pin_list *old_entry, *head, *tail, *entry;
230 cfg->irq_2_pin = NULL;
231 old_entry = old_cfg->irq_2_pin;
235 entry = get_one_free_irq_2_pin(node);
239 entry->apic = old_entry->apic;
240 entry->pin = old_entry->pin;
243 old_entry = old_entry->next;
245 entry = get_one_free_irq_2_pin(node);
253 /* still use the old one */
256 entry->apic = old_entry->apic;
257 entry->pin = old_entry->pin;
260 old_entry = old_entry->next;
264 cfg->irq_2_pin = head;
267 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
269 struct irq_pin_list *entry, *next;
271 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
274 entry = old_cfg->irq_2_pin;
281 old_cfg->irq_2_pin = NULL;
284 void arch_init_copy_chip_data(struct irq_desc *old_desc,
285 struct irq_desc *desc, int node)
288 struct irq_cfg *old_cfg;
290 cfg = get_one_free_irq_cfg(node);
295 desc->chip_data = cfg;
297 old_cfg = old_desc->chip_data;
299 cfg->vector = old_cfg->vector;
300 cfg->move_in_progress = old_cfg->move_in_progress;
301 cpumask_copy(cfg->domain, old_cfg->domain);
302 cpumask_copy(cfg->old_domain, old_cfg->old_domain);
304 init_copy_irq_2_pin(old_cfg, cfg, node);
307 static void free_irq_cfg(struct irq_cfg *cfg)
309 free_cpumask_var(cfg->domain);
310 free_cpumask_var(cfg->old_domain);
314 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
316 struct irq_cfg *old_cfg, *cfg;
318 old_cfg = get_irq_desc_chip_data(old_desc);
319 cfg = get_irq_desc_chip_data(desc);
325 free_irq_2_pin(old_cfg, cfg);
326 free_irq_cfg(old_cfg);
327 old_desc->chip_data = NULL;
330 /* end for move_irq_desc */
333 struct irq_cfg *irq_cfg(unsigned int irq)
335 return irq < nr_irqs ? irq_cfgx + irq : NULL;
342 unsigned int unused[3];
344 unsigned int unused2[11];
348 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
350 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
351 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
354 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
356 struct io_apic __iomem *io_apic = io_apic_base(apic);
357 writel(vector, &io_apic->eoi);
360 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
363 writel(reg, &io_apic->index);
364 return readl(&io_apic->data);
367 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
369 struct io_apic __iomem *io_apic = io_apic_base(apic);
370 writel(reg, &io_apic->index);
371 writel(value, &io_apic->data);
375 * Re-write a value: to be used for read-modify-write
376 * cycles where the read already set up the index register.
378 * Older SiS APIC requires we rewrite the index register
380 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
382 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 writel(value, &io_apic->data);
389 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
391 struct irq_pin_list *entry;
394 raw_spin_lock_irqsave(&ioapic_lock, flags);
395 for_each_irq_pin(entry, cfg->irq_2_pin) {
400 reg = io_apic_read(entry->apic, 0x10 + pin*2);
401 /* Is the remote IRR bit set? */
402 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
403 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
407 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
413 struct { u32 w1, w2; };
414 struct IO_APIC_route_entry entry;
417 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
419 union entry_union eu;
421 raw_spin_lock_irqsave(&ioapic_lock, flags);
422 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
423 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
424 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
429 * When we write a new IO APIC routing entry, we need to write the high
430 * word first! If the mask bit in the low word is clear, we will enable
431 * the interrupt, and we need to make sure the entry is fully populated
432 * before that happens.
435 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
437 union entry_union eu = {{0, 0}};
440 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
441 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
444 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
447 raw_spin_lock_irqsave(&ioapic_lock, flags);
448 __ioapic_write_entry(apic, pin, e);
449 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
453 * When we mask an IO APIC routing entry, we need to write the low
454 * word first, in order to set the mask bit before we change the
457 static void ioapic_mask_entry(int apic, int pin)
460 union entry_union eu = { .entry.mask = 1 };
462 raw_spin_lock_irqsave(&ioapic_lock, flags);
463 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
464 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
465 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
469 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
470 * shared ISA-space IRQs, so we have to support them. We are super
471 * fast in the common case, and fast for shared ISA-space IRQs.
474 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
476 struct irq_pin_list **last, *entry;
478 /* don't allow duplicates */
479 last = &cfg->irq_2_pin;
480 for_each_irq_pin(entry, cfg->irq_2_pin) {
481 if (entry->apic == apic && entry->pin == pin)
486 entry = get_one_free_irq_2_pin(node);
488 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
499 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
501 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
502 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
506 * Reroute an IRQ to a different pin.
508 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
509 int oldapic, int oldpin,
510 int newapic, int newpin)
512 struct irq_pin_list *entry;
514 for_each_irq_pin(entry, cfg->irq_2_pin) {
515 if (entry->apic == oldapic && entry->pin == oldpin) {
516 entry->apic = newapic;
518 /* every one is different, right? */
523 /* old apic/pin didn't exist, so just add new ones */
524 add_pin_to_irq_node(cfg, node, newapic, newpin);
527 static void __io_apic_modify_irq(struct irq_pin_list *entry,
528 int mask_and, int mask_or,
529 void (*final)(struct irq_pin_list *entry))
531 unsigned int reg, pin;
534 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
537 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
542 static void io_apic_modify_irq(struct irq_cfg *cfg,
543 int mask_and, int mask_or,
544 void (*final)(struct irq_pin_list *entry))
546 struct irq_pin_list *entry;
548 for_each_irq_pin(entry, cfg->irq_2_pin)
549 __io_apic_modify_irq(entry, mask_and, mask_or, final);
552 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
554 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
555 IO_APIC_REDIR_MASKED, NULL);
558 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
560 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
561 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
564 static void io_apic_sync(struct irq_pin_list *entry)
567 * Synchronize the IO-APIC and the CPU by doing
568 * a dummy read from the IO-APIC
570 struct io_apic __iomem *io_apic;
571 io_apic = io_apic_base(entry->apic);
572 readl(&io_apic->data);
575 static void mask_ioapic(struct irq_cfg *cfg)
579 raw_spin_lock_irqsave(&ioapic_lock, flags);
580 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
581 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
584 static void mask_ioapic_irq(struct irq_data *data)
586 mask_ioapic(data->chip_data);
589 static void __unmask_ioapic(struct irq_cfg *cfg)
591 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
594 static void unmask_ioapic(struct irq_cfg *cfg)
598 raw_spin_lock_irqsave(&ioapic_lock, flags);
599 __unmask_ioapic(cfg);
600 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
603 static void unmask_ioapic_irq(struct irq_data *data)
605 unmask_ioapic(data->chip_data);
608 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
610 struct IO_APIC_route_entry entry;
612 /* Check delivery_mode to be sure we're not clearing an SMI pin */
613 entry = ioapic_read_entry(apic, pin);
614 if (entry.delivery_mode == dest_SMI)
617 * Disable it in the IO-APIC irq-routing table:
619 ioapic_mask_entry(apic, pin);
622 static void clear_IO_APIC (void)
626 for (apic = 0; apic < nr_ioapics; apic++)
627 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
628 clear_IO_APIC_pin(apic, pin);
633 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
634 * specific CPU-side IRQs.
638 static int pirq_entries[MAX_PIRQS] = {
639 [0 ... MAX_PIRQS - 1] = -1
642 static int __init ioapic_pirq_setup(char *str)
645 int ints[MAX_PIRQS+1];
647 get_options(str, ARRAY_SIZE(ints), ints);
649 apic_printk(APIC_VERBOSE, KERN_INFO
650 "PIRQ redirection, working around broken MP-BIOS.\n");
652 if (ints[0] < MAX_PIRQS)
655 for (i = 0; i < max; i++) {
656 apic_printk(APIC_VERBOSE, KERN_DEBUG
657 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
659 * PIRQs are mapped upside down, usually.
661 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
666 __setup("pirq=", ioapic_pirq_setup);
667 #endif /* CONFIG_X86_32 */
669 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
672 struct IO_APIC_route_entry **ioapic_entries;
674 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
679 for (apic = 0; apic < nr_ioapics; apic++) {
680 ioapic_entries[apic] =
681 kzalloc(sizeof(struct IO_APIC_route_entry) *
682 nr_ioapic_registers[apic], GFP_ATOMIC);
683 if (!ioapic_entries[apic])
687 return ioapic_entries;
691 kfree(ioapic_entries[apic]);
692 kfree(ioapic_entries);
698 * Saves all the IO-APIC RTE's
700 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
707 for (apic = 0; apic < nr_ioapics; apic++) {
708 if (!ioapic_entries[apic])
711 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
712 ioapic_entries[apic][pin] =
713 ioapic_read_entry(apic, pin);
720 * Mask all IO APIC entries.
722 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
729 for (apic = 0; apic < nr_ioapics; apic++) {
730 if (!ioapic_entries[apic])
733 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
734 struct IO_APIC_route_entry entry;
736 entry = ioapic_entries[apic][pin];
739 ioapic_write_entry(apic, pin, entry);
746 * Restore IO APIC entries which was saved in ioapic_entries.
748 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
755 for (apic = 0; apic < nr_ioapics; apic++) {
756 if (!ioapic_entries[apic])
759 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
760 ioapic_write_entry(apic, pin,
761 ioapic_entries[apic][pin]);
766 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
770 for (apic = 0; apic < nr_ioapics; apic++)
771 kfree(ioapic_entries[apic]);
773 kfree(ioapic_entries);
777 * Find the IRQ entry number of a certain pin.
779 static int find_irq_entry(int apic, int pin, int type)
783 for (i = 0; i < mp_irq_entries; i++)
784 if (mp_irqs[i].irqtype == type &&
785 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
786 mp_irqs[i].dstapic == MP_APIC_ALL) &&
787 mp_irqs[i].dstirq == pin)
794 * Find the pin to which IRQ[irq] (ISA) is connected
796 static int __init find_isa_irq_pin(int irq, int type)
800 for (i = 0; i < mp_irq_entries; i++) {
801 int lbus = mp_irqs[i].srcbus;
803 if (test_bit(lbus, mp_bus_not_pci) &&
804 (mp_irqs[i].irqtype == type) &&
805 (mp_irqs[i].srcbusirq == irq))
807 return mp_irqs[i].dstirq;
812 static int __init find_isa_irq_apic(int irq, int type)
816 for (i = 0; i < mp_irq_entries; i++) {
817 int lbus = mp_irqs[i].srcbus;
819 if (test_bit(lbus, mp_bus_not_pci) &&
820 (mp_irqs[i].irqtype == type) &&
821 (mp_irqs[i].srcbusirq == irq))
824 if (i < mp_irq_entries) {
826 for(apic = 0; apic < nr_ioapics; apic++) {
827 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
835 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
837 * EISA Edge/Level control register, ELCR
839 static int EISA_ELCR(unsigned int irq)
841 if (irq < legacy_pic->nr_legacy_irqs) {
842 unsigned int port = 0x4d0 + (irq >> 3);
843 return (inb(port) >> (irq & 7)) & 1;
845 apic_printk(APIC_VERBOSE, KERN_INFO
846 "Broken MPtable reports ISA irq %d\n", irq);
852 /* ISA interrupts are always polarity zero edge triggered,
853 * when listed as conforming in the MP table. */
855 #define default_ISA_trigger(idx) (0)
856 #define default_ISA_polarity(idx) (0)
858 /* EISA interrupts are always polarity zero and can be edge or level
859 * trigger depending on the ELCR value. If an interrupt is listed as
860 * EISA conforming in the MP table, that means its trigger type must
861 * be read in from the ELCR */
863 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
864 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
866 /* PCI interrupts are always polarity one level triggered,
867 * when listed as conforming in the MP table. */
869 #define default_PCI_trigger(idx) (1)
870 #define default_PCI_polarity(idx) (1)
872 /* MCA interrupts are always polarity zero level triggered,
873 * when listed as conforming in the MP table. */
875 #define default_MCA_trigger(idx) (1)
876 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
878 static int MPBIOS_polarity(int idx)
880 int bus = mp_irqs[idx].srcbus;
884 * Determine IRQ line polarity (high active or low active):
886 switch (mp_irqs[idx].irqflag & 3)
888 case 0: /* conforms, ie. bus-type dependent polarity */
889 if (test_bit(bus, mp_bus_not_pci))
890 polarity = default_ISA_polarity(idx);
892 polarity = default_PCI_polarity(idx);
894 case 1: /* high active */
899 case 2: /* reserved */
901 printk(KERN_WARNING "broken BIOS!!\n");
905 case 3: /* low active */
910 default: /* invalid */
912 printk(KERN_WARNING "broken BIOS!!\n");
920 static int MPBIOS_trigger(int idx)
922 int bus = mp_irqs[idx].srcbus;
926 * Determine IRQ trigger mode (edge or level sensitive):
928 switch ((mp_irqs[idx].irqflag>>2) & 3)
930 case 0: /* conforms, ie. bus-type dependent */
931 if (test_bit(bus, mp_bus_not_pci))
932 trigger = default_ISA_trigger(idx);
934 trigger = default_PCI_trigger(idx);
935 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
936 switch (mp_bus_id_to_type[bus]) {
937 case MP_BUS_ISA: /* ISA pin */
939 /* set before the switch */
942 case MP_BUS_EISA: /* EISA pin */
944 trigger = default_EISA_trigger(idx);
947 case MP_BUS_PCI: /* PCI pin */
949 /* set before the switch */
952 case MP_BUS_MCA: /* MCA pin */
954 trigger = default_MCA_trigger(idx);
959 printk(KERN_WARNING "broken BIOS!!\n");
971 case 2: /* reserved */
973 printk(KERN_WARNING "broken BIOS!!\n");
982 default: /* invalid */
984 printk(KERN_WARNING "broken BIOS!!\n");
992 static inline int irq_polarity(int idx)
994 return MPBIOS_polarity(idx);
997 static inline int irq_trigger(int idx)
999 return MPBIOS_trigger(idx);
1002 static int pin_2_irq(int idx, int apic, int pin)
1005 int bus = mp_irqs[idx].srcbus;
1008 * Debugging check, we are in big trouble if this message pops up!
1010 if (mp_irqs[idx].dstirq != pin)
1011 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1013 if (test_bit(bus, mp_bus_not_pci)) {
1014 irq = mp_irqs[idx].srcbusirq;
1016 u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
1018 if (gsi >= NR_IRQS_LEGACY)
1021 irq = gsi_top + gsi;
1024 #ifdef CONFIG_X86_32
1026 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1028 if ((pin >= 16) && (pin <= 23)) {
1029 if (pirq_entries[pin-16] != -1) {
1030 if (!pirq_entries[pin-16]) {
1031 apic_printk(APIC_VERBOSE, KERN_DEBUG
1032 "disabling PIRQ%d\n", pin-16);
1034 irq = pirq_entries[pin-16];
1035 apic_printk(APIC_VERBOSE, KERN_DEBUG
1036 "using PIRQ%d -> IRQ %d\n",
1047 * Find a specific PCI IRQ entry.
1048 * Not an __init, possibly needed by modules
1050 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1051 struct io_apic_irq_attr *irq_attr)
1053 int apic, i, best_guess = -1;
1055 apic_printk(APIC_DEBUG,
1056 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1058 if (test_bit(bus, mp_bus_not_pci)) {
1059 apic_printk(APIC_VERBOSE,
1060 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1063 for (i = 0; i < mp_irq_entries; i++) {
1064 int lbus = mp_irqs[i].srcbus;
1066 for (apic = 0; apic < nr_ioapics; apic++)
1067 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1068 mp_irqs[i].dstapic == MP_APIC_ALL)
1071 if (!test_bit(lbus, mp_bus_not_pci) &&
1072 !mp_irqs[i].irqtype &&
1074 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1075 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1077 if (!(apic || IO_APIC_IRQ(irq)))
1080 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1081 set_io_apic_irq_attr(irq_attr, apic,
1088 * Use the first all-but-pin matching entry as a
1089 * best-guess fuzzy result for broken mptables.
1091 if (best_guess < 0) {
1092 set_io_apic_irq_attr(irq_attr, apic,
1102 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1104 void lock_vector_lock(void)
1106 /* Used to the online set of cpus does not change
1107 * during assign_irq_vector.
1109 raw_spin_lock(&vector_lock);
1112 void unlock_vector_lock(void)
1114 raw_spin_unlock(&vector_lock);
1118 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1121 * NOTE! The local APIC isn't very good at handling
1122 * multiple interrupts at the same interrupt level.
1123 * As the interrupt level is determined by taking the
1124 * vector number and shifting that right by 4, we
1125 * want to spread these out a bit so that they don't
1126 * all fall in the same interrupt level.
1128 * Also, we've got to be careful not to trash gate
1129 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1131 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1132 static int current_offset = VECTOR_OFFSET_START % 8;
1133 unsigned int old_vector;
1135 cpumask_var_t tmp_mask;
1137 if (cfg->move_in_progress)
1140 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1143 old_vector = cfg->vector;
1145 cpumask_and(tmp_mask, mask, cpu_online_mask);
1146 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1147 if (!cpumask_empty(tmp_mask)) {
1148 free_cpumask_var(tmp_mask);
1153 /* Only try and allocate irqs on cpus that are present */
1155 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1159 apic->vector_allocation_domain(cpu, tmp_mask);
1161 vector = current_vector;
1162 offset = current_offset;
1165 if (vector >= first_system_vector) {
1166 /* If out of vectors on large boxen, must share them. */
1167 offset = (offset + 1) % 8;
1168 vector = FIRST_EXTERNAL_VECTOR + offset;
1170 if (unlikely(current_vector == vector))
1173 if (test_bit(vector, used_vectors))
1176 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1177 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1180 current_vector = vector;
1181 current_offset = offset;
1183 cfg->move_in_progress = 1;
1184 cpumask_copy(cfg->old_domain, cfg->domain);
1186 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1187 per_cpu(vector_irq, new_cpu)[vector] = irq;
1188 cfg->vector = vector;
1189 cpumask_copy(cfg->domain, tmp_mask);
1193 free_cpumask_var(tmp_mask);
1197 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1200 unsigned long flags;
1202 raw_spin_lock_irqsave(&vector_lock, flags);
1203 err = __assign_irq_vector(irq, cfg, mask);
1204 raw_spin_unlock_irqrestore(&vector_lock, flags);
1208 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1212 BUG_ON(!cfg->vector);
1214 vector = cfg->vector;
1215 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1216 per_cpu(vector_irq, cpu)[vector] = -1;
1219 cpumask_clear(cfg->domain);
1221 if (likely(!cfg->move_in_progress))
1223 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1224 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1226 if (per_cpu(vector_irq, cpu)[vector] != irq)
1228 per_cpu(vector_irq, cpu)[vector] = -1;
1232 cfg->move_in_progress = 0;
1235 void __setup_vector_irq(int cpu)
1237 /* Initialize vector_irq on a new cpu */
1239 struct irq_cfg *cfg;
1240 struct irq_desc *desc;
1243 * vector_lock will make sure that we don't run into irq vector
1244 * assignments that might be happening on another cpu in parallel,
1245 * while we setup our initial vector to irq mappings.
1247 raw_spin_lock(&vector_lock);
1248 /* Mark the inuse vectors */
1249 for_each_irq_desc(irq, desc) {
1250 cfg = get_irq_desc_chip_data(desc);
1253 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1254 * will be part of the irq_cfg's domain.
1256 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1257 cpumask_set_cpu(cpu, cfg->domain);
1259 if (!cpumask_test_cpu(cpu, cfg->domain))
1261 vector = cfg->vector;
1262 per_cpu(vector_irq, cpu)[vector] = irq;
1264 /* Mark the free vectors */
1265 for (vector = 0; vector < NR_VECTORS; ++vector) {
1266 irq = per_cpu(vector_irq, cpu)[vector];
1271 if (!cpumask_test_cpu(cpu, cfg->domain))
1272 per_cpu(vector_irq, cpu)[vector] = -1;
1274 raw_spin_unlock(&vector_lock);
1277 static struct irq_chip ioapic_chip;
1278 static struct irq_chip ir_ioapic_chip;
1280 #define IOAPIC_AUTO -1
1281 #define IOAPIC_EDGE 0
1282 #define IOAPIC_LEVEL 1
1284 #ifdef CONFIG_X86_32
1285 static inline int IO_APIC_irq_trigger(int irq)
1289 for (apic = 0; apic < nr_ioapics; apic++) {
1290 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1291 idx = find_irq_entry(apic, pin, mp_INT);
1292 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1293 return irq_trigger(idx);
1297 * nonexistent IRQs are edge default
1302 static inline int IO_APIC_irq_trigger(int irq)
1308 static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
1311 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1312 trigger == IOAPIC_LEVEL)
1313 irq_set_status_flags(irq, IRQ_LEVEL);
1315 irq_clear_status_flags(irq, IRQ_LEVEL);
1317 if (irq_remapped(irq)) {
1318 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1320 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1324 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1325 handle_edge_irq, "edge");
1329 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1330 trigger == IOAPIC_LEVEL)
1331 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1335 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1336 handle_edge_irq, "edge");
1339 int setup_ioapic_entry(int apic_id, int irq,
1340 struct IO_APIC_route_entry *entry,
1341 unsigned int destination, int trigger,
1342 int polarity, int vector, int pin)
1345 * add it to the IO-APIC irq-routing table:
1347 memset(entry,0,sizeof(*entry));
1349 if (intr_remapping_enabled) {
1350 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1352 struct IR_IO_APIC_route_entry *ir_entry =
1353 (struct IR_IO_APIC_route_entry *) entry;
1357 panic("No mapping iommu for ioapic %d\n", apic_id);
1359 index = alloc_irte(iommu, irq, 1);
1361 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1363 prepare_irte(&irte, vector, destination);
1365 /* Set source-id of interrupt request */
1366 set_ioapic_sid(&irte, apic_id);
1368 modify_irte(irq, &irte);
1370 ir_entry->index2 = (index >> 15) & 0x1;
1372 ir_entry->format = 1;
1373 ir_entry->index = (index & 0x7fff);
1375 * IO-APIC RTE will be configured with virtual vector.
1376 * irq handler will do the explicit EOI to the io-apic.
1378 ir_entry->vector = pin;
1380 entry->delivery_mode = apic->irq_delivery_mode;
1381 entry->dest_mode = apic->irq_dest_mode;
1382 entry->dest = destination;
1383 entry->vector = vector;
1386 entry->mask = 0; /* enable IRQ */
1387 entry->trigger = trigger;
1388 entry->polarity = polarity;
1390 /* Mask level triggered irqs.
1391 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1398 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1399 struct irq_cfg *cfg, int trigger, int polarity)
1401 struct IO_APIC_route_entry entry;
1404 if (!IO_APIC_IRQ(irq))
1407 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1408 * controllers like 8259. Now that IO-APIC can handle this irq, update
1411 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1412 apic->vector_allocation_domain(0, cfg->domain);
1414 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1417 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1419 apic_printk(APIC_VERBOSE,KERN_DEBUG
1420 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1421 "IRQ %d Mode:%i Active:%i)\n",
1422 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1423 irq, trigger, polarity);
1426 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1427 dest, trigger, polarity, cfg->vector, pin)) {
1428 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1429 mp_ioapics[apic_id].apicid, pin);
1430 __clear_irq_vector(irq, cfg);
1434 ioapic_register_intr(irq, trigger);
1435 if (irq < legacy_pic->nr_legacy_irqs)
1436 legacy_pic->mask(irq);
1438 ioapic_write_entry(apic_id, pin, entry);
1442 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1443 } mp_ioapic_routing[MAX_IO_APICS];
1445 static void __init setup_IO_APIC_irqs(void)
1447 int apic_id, pin, idx, irq;
1449 struct irq_desc *desc;
1450 struct irq_cfg *cfg;
1451 int node = cpu_to_node(0);
1453 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1455 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1456 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1457 idx = find_irq_entry(apic_id, pin, mp_INT);
1461 apic_printk(APIC_VERBOSE,
1462 KERN_DEBUG " %d-%d",
1463 mp_ioapics[apic_id].apicid, pin);
1465 apic_printk(APIC_VERBOSE, " %d-%d",
1466 mp_ioapics[apic_id].apicid, pin);
1470 apic_printk(APIC_VERBOSE,
1471 " (apicid-pin) not connected\n");
1475 irq = pin_2_irq(idx, apic_id, pin);
1477 if ((apic_id > 0) && (irq > 16))
1481 * Skip the timer IRQ if there's a quirk handler
1482 * installed and if it returns 1:
1484 if (apic->multi_timer_check &&
1485 apic->multi_timer_check(apic_id, irq))
1488 desc = irq_to_desc_alloc_node(irq, node);
1490 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1493 cfg = get_irq_desc_chip_data(desc);
1494 add_pin_to_irq_node(cfg, node, apic_id, pin);
1496 * don't mark it in pin_programmed, so later acpi could
1497 * set it correctly when irq < 16
1499 setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
1504 apic_printk(APIC_VERBOSE,
1505 " (apicid-pin) not connected\n");
1509 * for the gsit that is not in first ioapic
1510 * but could not use acpi_register_gsi()
1511 * like some special sci in IBM x3330
1513 void setup_IO_APIC_irq_extra(u32 gsi)
1515 int apic_id = 0, pin, idx, irq;
1516 int node = cpu_to_node(0);
1517 struct irq_desc *desc;
1518 struct irq_cfg *cfg;
1521 * Convert 'gsi' to 'ioapic.pin'.
1523 apic_id = mp_find_ioapic(gsi);
1527 pin = mp_find_ioapic_pin(apic_id, gsi);
1528 idx = find_irq_entry(apic_id, pin, mp_INT);
1532 irq = pin_2_irq(idx, apic_id, pin);
1533 #ifdef CONFIG_SPARSE_IRQ
1534 desc = irq_to_desc(irq);
1538 desc = irq_to_desc_alloc_node(irq, node);
1540 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1544 cfg = get_irq_desc_chip_data(desc);
1545 add_pin_to_irq_node(cfg, node, apic_id, pin);
1547 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1548 pr_debug("Pin %d-%d already programmed\n",
1549 mp_ioapics[apic_id].apicid, pin);
1552 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1554 setup_ioapic_irq(apic_id, pin, irq, cfg,
1555 irq_trigger(idx), irq_polarity(idx));
1559 * Set up the timer pin, possibly with the 8259A-master behind.
1561 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1564 struct IO_APIC_route_entry entry;
1566 if (intr_remapping_enabled)
1569 memset(&entry, 0, sizeof(entry));
1572 * We use logical delivery to get the timer IRQ
1575 entry.dest_mode = apic->irq_dest_mode;
1576 entry.mask = 0; /* don't mask IRQ for edge */
1577 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1578 entry.delivery_mode = apic->irq_delivery_mode;
1581 entry.vector = vector;
1584 * The timer IRQ doesn't have to know that behind the
1585 * scene we may have a 8259A-master in AEOI mode ...
1587 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1590 * Add it to the IO-APIC irq-routing table:
1592 ioapic_write_entry(apic_id, pin, entry);
1596 __apicdebuginit(void) print_IO_APIC(void)
1599 union IO_APIC_reg_00 reg_00;
1600 union IO_APIC_reg_01 reg_01;
1601 union IO_APIC_reg_02 reg_02;
1602 union IO_APIC_reg_03 reg_03;
1603 unsigned long flags;
1604 struct irq_cfg *cfg;
1605 struct irq_desc *desc;
1608 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1609 for (i = 0; i < nr_ioapics; i++)
1610 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1611 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1614 * We are a bit conservative about what we expect. We have to
1615 * know about every hardware change ASAP.
1617 printk(KERN_INFO "testing the IO APIC.......................\n");
1619 for (apic = 0; apic < nr_ioapics; apic++) {
1621 raw_spin_lock_irqsave(&ioapic_lock, flags);
1622 reg_00.raw = io_apic_read(apic, 0);
1623 reg_01.raw = io_apic_read(apic, 1);
1624 if (reg_01.bits.version >= 0x10)
1625 reg_02.raw = io_apic_read(apic, 2);
1626 if (reg_01.bits.version >= 0x20)
1627 reg_03.raw = io_apic_read(apic, 3);
1628 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1631 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1632 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1633 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1634 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1635 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1637 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1638 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1640 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1641 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1644 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1645 * but the value of reg_02 is read as the previous read register
1646 * value, so ignore it if reg_02 == reg_01.
1648 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1649 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1650 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1654 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1655 * or reg_03, but the value of reg_0[23] is read as the previous read
1656 * register value, so ignore it if reg_03 == reg_0[12].
1658 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1659 reg_03.raw != reg_01.raw) {
1660 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1661 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1664 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1666 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1667 " Stat Dmod Deli Vect:\n");
1669 for (i = 0; i <= reg_01.bits.entries; i++) {
1670 struct IO_APIC_route_entry entry;
1672 entry = ioapic_read_entry(apic, i);
1674 printk(KERN_DEBUG " %02x %03X ",
1679 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1684 entry.delivery_status,
1686 entry.delivery_mode,
1691 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1692 for_each_irq_desc(irq, desc) {
1693 struct irq_pin_list *entry;
1695 cfg = get_irq_desc_chip_data(desc);
1698 entry = cfg->irq_2_pin;
1701 printk(KERN_DEBUG "IRQ%d ", irq);
1702 for_each_irq_pin(entry, cfg->irq_2_pin)
1703 printk("-> %d:%d", entry->apic, entry->pin);
1707 printk(KERN_INFO ".................................... done.\n");
1712 __apicdebuginit(void) print_APIC_field(int base)
1718 for (i = 0; i < 8; i++)
1719 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1721 printk(KERN_CONT "\n");
1724 __apicdebuginit(void) print_local_APIC(void *dummy)
1726 unsigned int i, v, ver, maxlvt;
1729 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1730 smp_processor_id(), hard_smp_processor_id());
1731 v = apic_read(APIC_ID);
1732 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1733 v = apic_read(APIC_LVR);
1734 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1735 ver = GET_APIC_VERSION(v);
1736 maxlvt = lapic_get_maxlvt();
1738 v = apic_read(APIC_TASKPRI);
1739 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1741 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1742 if (!APIC_XAPIC(ver)) {
1743 v = apic_read(APIC_ARBPRI);
1744 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1745 v & APIC_ARBPRI_MASK);
1747 v = apic_read(APIC_PROCPRI);
1748 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1752 * Remote read supported only in the 82489DX and local APIC for
1753 * Pentium processors.
1755 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1756 v = apic_read(APIC_RRR);
1757 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1760 v = apic_read(APIC_LDR);
1761 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1762 if (!x2apic_enabled()) {
1763 v = apic_read(APIC_DFR);
1764 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1766 v = apic_read(APIC_SPIV);
1767 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1769 printk(KERN_DEBUG "... APIC ISR field:\n");
1770 print_APIC_field(APIC_ISR);
1771 printk(KERN_DEBUG "... APIC TMR field:\n");
1772 print_APIC_field(APIC_TMR);
1773 printk(KERN_DEBUG "... APIC IRR field:\n");
1774 print_APIC_field(APIC_IRR);
1776 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1777 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1778 apic_write(APIC_ESR, 0);
1780 v = apic_read(APIC_ESR);
1781 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1784 icr = apic_icr_read();
1785 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1786 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1788 v = apic_read(APIC_LVTT);
1789 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1791 if (maxlvt > 3) { /* PC is LVT#4. */
1792 v = apic_read(APIC_LVTPC);
1793 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1795 v = apic_read(APIC_LVT0);
1796 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1797 v = apic_read(APIC_LVT1);
1798 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1800 if (maxlvt > 2) { /* ERR is LVT#3. */
1801 v = apic_read(APIC_LVTERR);
1802 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1805 v = apic_read(APIC_TMICT);
1806 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1807 v = apic_read(APIC_TMCCT);
1808 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1809 v = apic_read(APIC_TDCR);
1810 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1812 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1813 v = apic_read(APIC_EFEAT);
1814 maxlvt = (v >> 16) & 0xff;
1815 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1816 v = apic_read(APIC_ECTRL);
1817 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1818 for (i = 0; i < maxlvt; i++) {
1819 v = apic_read(APIC_EILVTn(i));
1820 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1826 __apicdebuginit(void) print_local_APICs(int maxcpu)
1834 for_each_online_cpu(cpu) {
1837 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1842 __apicdebuginit(void) print_PIC(void)
1845 unsigned long flags;
1847 if (!legacy_pic->nr_legacy_irqs)
1850 printk(KERN_DEBUG "\nprinting PIC contents\n");
1852 raw_spin_lock_irqsave(&i8259A_lock, flags);
1854 v = inb(0xa1) << 8 | inb(0x21);
1855 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1857 v = inb(0xa0) << 8 | inb(0x20);
1858 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1862 v = inb(0xa0) << 8 | inb(0x20);
1866 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1868 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1870 v = inb(0x4d1) << 8 | inb(0x4d0);
1871 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1874 static int __initdata show_lapic = 1;
1875 static __init int setup_show_lapic(char *arg)
1879 if (strcmp(arg, "all") == 0) {
1880 show_lapic = CONFIG_NR_CPUS;
1882 get_option(&arg, &num);
1889 __setup("show_lapic=", setup_show_lapic);
1891 __apicdebuginit(int) print_ICs(void)
1893 if (apic_verbosity == APIC_QUIET)
1898 /* don't print out if apic is not there */
1899 if (!cpu_has_apic && !apic_from_smp_config())
1902 print_local_APICs(show_lapic);
1908 fs_initcall(print_ICs);
1911 /* Where if anywhere is the i8259 connect in external int mode */
1912 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1914 void __init enable_IO_APIC(void)
1916 int i8259_apic, i8259_pin;
1919 if (!legacy_pic->nr_legacy_irqs)
1922 for(apic = 0; apic < nr_ioapics; apic++) {
1924 /* See if any of the pins is in ExtINT mode */
1925 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1926 struct IO_APIC_route_entry entry;
1927 entry = ioapic_read_entry(apic, pin);
1929 /* If the interrupt line is enabled and in ExtInt mode
1930 * I have found the pin where the i8259 is connected.
1932 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1933 ioapic_i8259.apic = apic;
1934 ioapic_i8259.pin = pin;
1940 /* Look to see what if the MP table has reported the ExtINT */
1941 /* If we could not find the appropriate pin by looking at the ioapic
1942 * the i8259 probably is not connected the ioapic but give the
1943 * mptable a chance anyway.
1945 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1946 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1947 /* Trust the MP table if nothing is setup in the hardware */
1948 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1949 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1950 ioapic_i8259.pin = i8259_pin;
1951 ioapic_i8259.apic = i8259_apic;
1953 /* Complain if the MP table and the hardware disagree */
1954 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1955 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1957 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1961 * Do not trust the IO-APIC being empty at bootup
1967 * Not an __init, needed by the reboot code
1969 void disable_IO_APIC(void)
1972 * Clear the IO-APIC before rebooting:
1976 if (!legacy_pic->nr_legacy_irqs)
1980 * If the i8259 is routed through an IOAPIC
1981 * Put that IOAPIC in virtual wire mode
1982 * so legacy interrupts can be delivered.
1984 * With interrupt-remapping, for now we will use virtual wire A mode,
1985 * as virtual wire B is little complex (need to configure both
1986 * IOAPIC RTE aswell as interrupt-remapping table entry).
1987 * As this gets called during crash dump, keep this simple for now.
1989 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1990 struct IO_APIC_route_entry entry;
1992 memset(&entry, 0, sizeof(entry));
1993 entry.mask = 0; /* Enabled */
1994 entry.trigger = 0; /* Edge */
1996 entry.polarity = 0; /* High */
1997 entry.delivery_status = 0;
1998 entry.dest_mode = 0; /* Physical */
1999 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2001 entry.dest = read_apic_id();
2004 * Add it to the IO-APIC irq-routing table:
2006 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2010 * Use virtual wire A mode when interrupt remapping is enabled.
2012 if (cpu_has_apic || apic_from_smp_config())
2013 disconnect_bsp_APIC(!intr_remapping_enabled &&
2014 ioapic_i8259.pin != -1);
2017 #ifdef CONFIG_X86_32
2019 * function to set the IO-APIC physical IDs based on the
2020 * values stored in the MPC table.
2022 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2025 void __init setup_ioapic_ids_from_mpc(void)
2027 union IO_APIC_reg_00 reg_00;
2028 physid_mask_t phys_id_present_map;
2031 unsigned char old_id;
2032 unsigned long flags;
2037 * Don't check I/O APIC IDs for xAPIC systems. They have
2038 * no meaning without the serial APIC bus.
2040 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2041 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2044 * This is broken; anything with a real cpu count has to
2045 * circumvent this idiocy regardless.
2047 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2050 * Set the IOAPIC ID to the value stored in the MPC table.
2052 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2054 /* Read the register 0 value */
2055 raw_spin_lock_irqsave(&ioapic_lock, flags);
2056 reg_00.raw = io_apic_read(apic_id, 0);
2057 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2059 old_id = mp_ioapics[apic_id].apicid;
2061 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2062 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2063 apic_id, mp_ioapics[apic_id].apicid);
2064 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2066 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2070 * Sanity check, is the ID really free? Every APIC in a
2071 * system must have a unique ID or we get lots of nice
2072 * 'stuck on smp_invalidate_needed IPI wait' messages.
2074 if (apic->check_apicid_used(&phys_id_present_map,
2075 mp_ioapics[apic_id].apicid)) {
2076 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2077 apic_id, mp_ioapics[apic_id].apicid);
2078 for (i = 0; i < get_physical_broadcast(); i++)
2079 if (!physid_isset(i, phys_id_present_map))
2081 if (i >= get_physical_broadcast())
2082 panic("Max APIC ID exceeded!\n");
2083 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2085 physid_set(i, phys_id_present_map);
2086 mp_ioapics[apic_id].apicid = i;
2089 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2090 apic_printk(APIC_VERBOSE, "Setting %d in the "
2091 "phys_id_present_map\n",
2092 mp_ioapics[apic_id].apicid);
2093 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2098 * We need to adjust the IRQ routing table
2099 * if the ID changed.
2101 if (old_id != mp_ioapics[apic_id].apicid)
2102 for (i = 0; i < mp_irq_entries; i++)
2103 if (mp_irqs[i].dstapic == old_id)
2105 = mp_ioapics[apic_id].apicid;
2108 * Read the right value from the MPC table and
2109 * write it into the ID register.
2111 apic_printk(APIC_VERBOSE, KERN_INFO
2112 "...changing IO-APIC physical APIC ID to %d ...",
2113 mp_ioapics[apic_id].apicid);
2115 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2116 raw_spin_lock_irqsave(&ioapic_lock, flags);
2117 io_apic_write(apic_id, 0, reg_00.raw);
2118 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2123 raw_spin_lock_irqsave(&ioapic_lock, flags);
2124 reg_00.raw = io_apic_read(apic_id, 0);
2125 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2126 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2127 printk("could not set ID!\n");
2129 apic_printk(APIC_VERBOSE, " ok.\n");
2134 int no_timer_check __initdata;
2136 static int __init notimercheck(char *s)
2141 __setup("no_timer_check", notimercheck);
2144 * There is a nasty bug in some older SMP boards, their mptable lies
2145 * about the timer IRQ. We do the following to work around the situation:
2147 * - timer IRQ defaults to IO-APIC IRQ
2148 * - if this function detects that timer IRQs are defunct, then we fall
2149 * back to ISA timer IRQs
2151 static int __init timer_irq_works(void)
2153 unsigned long t1 = jiffies;
2154 unsigned long flags;
2159 local_save_flags(flags);
2161 /* Let ten ticks pass... */
2162 mdelay((10 * 1000) / HZ);
2163 local_irq_restore(flags);
2166 * Expect a few ticks at least, to be sure some possible
2167 * glue logic does not lock up after one or two first
2168 * ticks in a non-ExtINT mode. Also the local APIC
2169 * might have cached one ExtINT interrupt. Finally, at
2170 * least one tick may be lost due to delays.
2174 if (time_after(jiffies, t1 + 4))
2180 * In the SMP+IOAPIC case it might happen that there are an unspecified
2181 * number of pending IRQ events unhandled. These cases are very rare,
2182 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2183 * better to do it this way as thus we do not have to be aware of
2184 * 'pending' interrupts in the IRQ path, except at this point.
2187 * Edge triggered needs to resend any interrupt
2188 * that was delayed but this is now handled in the device
2193 * Starting up a edge-triggered IO-APIC interrupt is
2194 * nasty - we need to make sure that we get the edge.
2195 * If it is already asserted for some reason, we need
2196 * return 1 to indicate that is was pending.
2198 * This is not complete - we should be able to fake
2199 * an edge even if it isn't on the 8259A...
2202 static unsigned int startup_ioapic_irq(struct irq_data *data)
2204 int was_pending = 0, irq = data->irq;
2205 unsigned long flags;
2207 raw_spin_lock_irqsave(&ioapic_lock, flags);
2208 if (irq < legacy_pic->nr_legacy_irqs) {
2209 legacy_pic->mask(irq);
2210 if (legacy_pic->irq_pending(irq))
2213 __unmask_ioapic(data->chip_data);
2214 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2219 static int ioapic_retrigger_irq(struct irq_data *data)
2221 struct irq_cfg *cfg = data->chip_data;
2222 unsigned long flags;
2224 raw_spin_lock_irqsave(&vector_lock, flags);
2225 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2226 raw_spin_unlock_irqrestore(&vector_lock, flags);
2232 * Level and edge triggered IO-APIC interrupts need different handling,
2233 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2234 * handled with the level-triggered descriptor, but that one has slightly
2235 * more overhead. Level-triggered interrupts cannot be handled with the
2236 * edge-triggered handler, without risking IRQ storms and other ugly
2241 void send_cleanup_vector(struct irq_cfg *cfg)
2243 cpumask_var_t cleanup_mask;
2245 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2247 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2248 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2250 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2251 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2252 free_cpumask_var(cleanup_mask);
2254 cfg->move_in_progress = 0;
2257 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2260 struct irq_pin_list *entry;
2261 u8 vector = cfg->vector;
2263 for_each_irq_pin(entry, cfg->irq_2_pin) {
2269 * With interrupt-remapping, destination information comes
2270 * from interrupt-remapping table entry.
2272 if (!irq_remapped(irq))
2273 io_apic_write(apic, 0x11 + pin*2, dest);
2274 reg = io_apic_read(apic, 0x10 + pin*2);
2275 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2277 io_apic_modify(apic, 0x10 + pin*2, reg);
2282 * Either sets desc->affinity to a valid value, and returns
2283 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2284 * leaves desc->affinity untouched.
2287 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2288 unsigned int *dest_id)
2290 struct irq_cfg *cfg;
2293 if (!cpumask_intersects(mask, cpu_online_mask))
2297 cfg = get_irq_desc_chip_data(desc);
2298 if (assign_irq_vector(irq, cfg, mask))
2301 cpumask_copy(desc->affinity, mask);
2303 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2308 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2310 struct irq_cfg *cfg;
2311 unsigned long flags;
2317 cfg = get_irq_desc_chip_data(desc);
2319 raw_spin_lock_irqsave(&ioapic_lock, flags);
2320 ret = set_desc_affinity(desc, mask, &dest);
2322 /* Only the high 8 bits are valid. */
2323 dest = SET_APIC_LOGICAL_ID(dest);
2324 __target_IO_APIC_irq(irq, dest, cfg);
2326 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2332 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2334 struct irq_desc *desc;
2336 desc = irq_to_desc(irq);
2338 return set_ioapic_affinity_irq_desc(desc, mask);
2341 #ifdef CONFIG_INTR_REMAP
2344 * Migrate the IO-APIC irq in the presence of intr-remapping.
2346 * For both level and edge triggered, irq migration is a simple atomic
2347 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2349 * For level triggered, we eliminate the io-apic RTE modification (with the
2350 * updated vector information), by using a virtual vector (io-apic pin number).
2351 * Real vector that is used for interrupting cpu will be coming from
2352 * the interrupt-remapping table entry.
2355 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2357 struct irq_cfg *cfg;
2363 if (!cpumask_intersects(mask, cpu_online_mask))
2367 if (get_irte(irq, &irte))
2370 cfg = get_irq_desc_chip_data(desc);
2371 if (assign_irq_vector(irq, cfg, mask))
2374 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2376 irte.vector = cfg->vector;
2377 irte.dest_id = IRTE_DEST(dest);
2380 * Modified the IRTE and flushes the Interrupt entry cache.
2382 modify_irte(irq, &irte);
2384 if (cfg->move_in_progress)
2385 send_cleanup_vector(cfg);
2387 cpumask_copy(desc->affinity, mask);
2393 * Migrates the IRQ destination in the process context.
2395 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2396 const struct cpumask *mask)
2398 return migrate_ioapic_irq_desc(desc, mask);
2400 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2401 const struct cpumask *mask)
2403 struct irq_desc *desc = irq_to_desc(irq);
2405 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2408 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2409 const struct cpumask *mask)
2415 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2417 unsigned vector, me;
2423 me = smp_processor_id();
2424 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2427 struct irq_desc *desc;
2428 struct irq_cfg *cfg;
2429 irq = __get_cpu_var(vector_irq)[vector];
2434 desc = irq_to_desc(irq);
2439 raw_spin_lock(&desc->lock);
2442 * Check if the irq migration is in progress. If so, we
2443 * haven't received the cleanup request yet for this irq.
2445 if (cfg->move_in_progress)
2448 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2451 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2453 * Check if the vector that needs to be cleanedup is
2454 * registered at the cpu's IRR. If so, then this is not
2455 * the best time to clean it up. Lets clean it up in the
2456 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2459 if (irr & (1 << (vector % 32))) {
2460 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2463 __get_cpu_var(vector_irq)[vector] = -1;
2465 raw_spin_unlock(&desc->lock);
2471 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2475 if (likely(!cfg->move_in_progress))
2478 me = smp_processor_id();
2480 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2481 send_cleanup_vector(cfg);
2484 static void irq_complete_move(struct irq_cfg *cfg)
2486 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2489 void irq_force_complete_move(int irq)
2491 struct irq_cfg *cfg = get_irq_chip_data(irq);
2496 __irq_complete_move(cfg, cfg->vector);
2499 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2502 static void ack_apic_edge(struct irq_data *data)
2504 irq_complete_move(data->chip_data);
2505 move_native_irq(data->irq);
2509 atomic_t irq_mis_count;
2512 * IO-APIC versions below 0x20 don't support EOI register.
2513 * For the record, here is the information about various versions:
2515 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2516 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2519 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2520 * version as 0x2. This is an error with documentation and these ICH chips
2521 * use io-apic's of version 0x20.
2523 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2524 * Otherwise, we simulate the EOI message manually by changing the trigger
2525 * mode to edge and then back to level, with RTE being masked during this.
2527 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2529 struct irq_pin_list *entry;
2530 unsigned long flags;
2532 raw_spin_lock_irqsave(&ioapic_lock, flags);
2533 for_each_irq_pin(entry, cfg->irq_2_pin) {
2534 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2536 * Intr-remapping uses pin number as the virtual vector
2537 * in the RTE. Actual vector is programmed in
2538 * intr-remapping table entry. Hence for the io-apic
2539 * EOI we use the pin number.
2541 if (irq_remapped(irq))
2542 io_apic_eoi(entry->apic, entry->pin);
2544 io_apic_eoi(entry->apic, cfg->vector);
2546 __mask_and_edge_IO_APIC_irq(entry);
2547 __unmask_and_level_IO_APIC_irq(entry);
2550 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2553 static void ack_apic_level(struct irq_data *data)
2555 struct irq_cfg *cfg = data->chip_data;
2556 int i, do_unmask_irq = 0, irq = data->irq;
2557 struct irq_desc *desc = irq_to_desc(irq);
2560 irq_complete_move(cfg);
2561 #ifdef CONFIG_GENERIC_PENDING_IRQ
2562 /* If we are moving the irq we need to mask it */
2563 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570 * It appears there is an erratum which affects at least version 0x11
2571 * of I/O APIC (that's the 82093AA and cores integrated into various
2572 * chipsets). Under certain conditions a level-triggered interrupt is
2573 * erroneously delivered as edge-triggered one but the respective IRR
2574 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2575 * message but it will never arrive and further interrupts are blocked
2576 * from the source. The exact reason is so far unknown, but the
2577 * phenomenon was observed when two consecutive interrupt requests
2578 * from a given source get delivered to the same CPU and the source is
2579 * temporarily disabled in between.
2581 * A workaround is to simulate an EOI message manually. We achieve it
2582 * by setting the trigger mode to edge and then to level when the edge
2583 * trigger mode gets detected in the TMR of a local APIC for a
2584 * level-triggered interrupt. We mask the source for the time of the
2585 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2586 * The idea is from Manfred Spraul. --macro
2588 * Also in the case when cpu goes offline, fixup_irqs() will forward
2589 * any unhandled interrupt on the offlined cpu to the new cpu
2590 * destination that is handling the corresponding interrupt. This
2591 * interrupt forwarding is done via IPI's. Hence, in this case also
2592 * level-triggered io-apic interrupt will be seen as an edge
2593 * interrupt in the IRR. And we can't rely on the cpu's EOI
2594 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2595 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2596 * supporting EOI register, we do an explicit EOI to clear the
2597 * remote IRR and on IO-APIC's which don't have an EOI register,
2598 * we use the above logic (mask+edge followed by unmask+level) from
2599 * Manfred Spraul to clear the remote IRR.
2602 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2605 * We must acknowledge the irq before we move it or the acknowledge will
2606 * not propagate properly.
2611 * Tail end of clearing remote IRR bit (either by delivering the EOI
2612 * message via io-apic EOI register write or simulating it using
2613 * mask+edge followed by unnask+level logic) manually when the
2614 * level triggered interrupt is seen as the edge triggered interrupt
2617 if (!(v & (1 << (i & 0x1f)))) {
2618 atomic_inc(&irq_mis_count);
2620 eoi_ioapic_irq(irq, cfg);
2623 /* Now we can move and renable the irq */
2624 if (unlikely(do_unmask_irq)) {
2625 /* Only migrate the irq if the ack has been received.
2627 * On rare occasions the broadcast level triggered ack gets
2628 * delayed going to ioapics, and if we reprogram the
2629 * vector while Remote IRR is still set the irq will never
2632 * To prevent this scenario we read the Remote IRR bit
2633 * of the ioapic. This has two effects.
2634 * - On any sane system the read of the ioapic will
2635 * flush writes (and acks) going to the ioapic from
2637 * - We get to see if the ACK has actually been delivered.
2639 * Based on failed experiments of reprogramming the
2640 * ioapic entry from outside of irq context starting
2641 * with masking the ioapic entry and then polling until
2642 * Remote IRR was clear before reprogramming the
2643 * ioapic I don't trust the Remote IRR bit to be
2644 * completey accurate.
2646 * However there appears to be no other way to plug
2647 * this race, so if the Remote IRR bit is not
2648 * accurate and is causing problems then it is a hardware bug
2649 * and you can go talk to the chipset vendor about it.
2651 if (!io_apic_level_ack_pending(cfg))
2652 move_masked_irq(irq);
2657 #ifdef CONFIG_INTR_REMAP
2658 static void ir_ack_apic_edge(struct irq_data *data)
2663 static void ir_ack_apic_level(struct irq_data *data)
2666 eoi_ioapic_irq(data->irq, data->chip_data);
2668 #endif /* CONFIG_INTR_REMAP */
2670 static struct irq_chip ioapic_chip __read_mostly = {
2672 .irq_startup = startup_ioapic_irq,
2673 .irq_mask = mask_ioapic_irq,
2674 .irq_unmask = unmask_ioapic_irq,
2675 .irq_ack = ack_apic_edge,
2676 .irq_eoi = ack_apic_level,
2678 .set_affinity = set_ioapic_affinity_irq,
2680 .irq_retrigger = ioapic_retrigger_irq,
2683 static struct irq_chip ir_ioapic_chip __read_mostly = {
2684 .name = "IR-IO-APIC",
2685 .irq_startup = startup_ioapic_irq,
2686 .irq_mask = mask_ioapic_irq,
2687 .irq_unmask = unmask_ioapic_irq,
2688 #ifdef CONFIG_INTR_REMAP
2689 .irq_ack = ir_ack_apic_edge,
2690 .irq_eoi = ir_ack_apic_level,
2692 .set_affinity = set_ir_ioapic_affinity_irq,
2695 .irq_retrigger = ioapic_retrigger_irq,
2698 static inline void init_IO_APIC_traps(void)
2701 struct irq_desc *desc;
2702 struct irq_cfg *cfg;
2705 * NOTE! The local APIC isn't very good at handling
2706 * multiple interrupts at the same interrupt level.
2707 * As the interrupt level is determined by taking the
2708 * vector number and shifting that right by 4, we
2709 * want to spread these out a bit so that they don't
2710 * all fall in the same interrupt level.
2712 * Also, we've got to be careful not to trash gate
2713 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2715 for_each_irq_desc(irq, desc) {
2716 cfg = get_irq_desc_chip_data(desc);
2717 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2719 * Hmm.. We don't have an entry for this,
2720 * so default to an old-fashioned 8259
2721 * interrupt if we can..
2723 if (irq < legacy_pic->nr_legacy_irqs)
2724 legacy_pic->make_irq(irq);
2726 /* Strange. Oh, well.. */
2727 desc->chip = &no_irq_chip;
2733 * The local APIC irq-chip implementation:
2736 static void mask_lapic_irq(struct irq_data *data)
2740 v = apic_read(APIC_LVT0);
2741 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2744 static void unmask_lapic_irq(struct irq_data *data)
2748 v = apic_read(APIC_LVT0);
2749 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2752 static void ack_lapic_irq(struct irq_data *data)
2757 static struct irq_chip lapic_chip __read_mostly = {
2758 .name = "local-APIC",
2759 .irq_mask = mask_lapic_irq,
2760 .irq_unmask = unmask_lapic_irq,
2761 .irq_ack = ack_lapic_irq,
2764 static void lapic_register_intr(int irq)
2766 irq_clear_status_flags(irq, IRQ_LEVEL);
2767 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2771 static void __init setup_nmi(void)
2774 * Dirty trick to enable the NMI watchdog ...
2775 * We put the 8259A master into AEOI mode and
2776 * unmask on all local APICs LVT0 as NMI.
2778 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2779 * is from Maciej W. Rozycki - so we do not have to EOI from
2780 * the NMI handler or the timer interrupt.
2782 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2784 enable_NMI_through_LVT0();
2786 apic_printk(APIC_VERBOSE, " done.\n");
2790 * This looks a bit hackish but it's about the only one way of sending
2791 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2792 * not support the ExtINT mode, unfortunately. We need to send these
2793 * cycles as some i82489DX-based boards have glue logic that keeps the
2794 * 8259A interrupt line asserted until INTA. --macro
2796 static inline void __init unlock_ExtINT_logic(void)
2799 struct IO_APIC_route_entry entry0, entry1;
2800 unsigned char save_control, save_freq_select;
2802 pin = find_isa_irq_pin(8, mp_INT);
2807 apic = find_isa_irq_apic(8, mp_INT);
2813 entry0 = ioapic_read_entry(apic, pin);
2814 clear_IO_APIC_pin(apic, pin);
2816 memset(&entry1, 0, sizeof(entry1));
2818 entry1.dest_mode = 0; /* physical delivery */
2819 entry1.mask = 0; /* unmask IRQ now */
2820 entry1.dest = hard_smp_processor_id();
2821 entry1.delivery_mode = dest_ExtINT;
2822 entry1.polarity = entry0.polarity;
2826 ioapic_write_entry(apic, pin, entry1);
2828 save_control = CMOS_READ(RTC_CONTROL);
2829 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2830 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2832 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2837 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2841 CMOS_WRITE(save_control, RTC_CONTROL);
2842 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2843 clear_IO_APIC_pin(apic, pin);
2845 ioapic_write_entry(apic, pin, entry0);
2848 static int disable_timer_pin_1 __initdata;
2849 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2850 static int __init disable_timer_pin_setup(char *arg)
2852 disable_timer_pin_1 = 1;
2855 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2857 int timer_through_8259 __initdata;
2860 * This code may look a bit paranoid, but it's supposed to cooperate with
2861 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2862 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2863 * fanatically on his truly buggy board.
2865 * FIXME: really need to revamp this for all platforms.
2867 static inline void __init check_timer(void)
2869 struct irq_cfg *cfg = get_irq_chip_data(0);
2870 int node = cpu_to_node(0);
2871 int apic1, pin1, apic2, pin2;
2872 unsigned long flags;
2875 local_irq_save(flags);
2878 * get/set the timer IRQ vector:
2880 legacy_pic->mask(0);
2881 assign_irq_vector(0, cfg, apic->target_cpus());
2884 * As IRQ0 is to be enabled in the 8259A, the virtual
2885 * wire has to be disabled in the local APIC. Also
2886 * timer interrupts need to be acknowledged manually in
2887 * the 8259A for the i82489DX when using the NMI
2888 * watchdog as that APIC treats NMIs as level-triggered.
2889 * The AEOI mode will finish them in the 8259A
2892 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2893 legacy_pic->init(1);
2894 #ifdef CONFIG_X86_32
2898 ver = apic_read(APIC_LVR);
2899 ver = GET_APIC_VERSION(ver);
2900 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2904 pin1 = find_isa_irq_pin(0, mp_INT);
2905 apic1 = find_isa_irq_apic(0, mp_INT);
2906 pin2 = ioapic_i8259.pin;
2907 apic2 = ioapic_i8259.apic;
2909 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2910 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2911 cfg->vector, apic1, pin1, apic2, pin2);
2914 * Some BIOS writers are clueless and report the ExtINTA
2915 * I/O APIC input from the cascaded 8259A as the timer
2916 * interrupt input. So just in case, if only one pin
2917 * was found above, try it both directly and through the
2921 if (intr_remapping_enabled)
2922 panic("BIOS bug: timer not connected to IO-APIC");
2926 } else if (pin2 == -1) {
2933 * Ok, does IRQ0 through the IOAPIC work?
2936 add_pin_to_irq_node(cfg, node, apic1, pin1);
2937 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2939 /* for edge trigger, setup_ioapic_irq already
2940 * leave it unmasked.
2941 * so only need to unmask if it is level-trigger
2942 * do we really have level trigger timer?
2945 idx = find_irq_entry(apic1, pin1, mp_INT);
2946 if (idx != -1 && irq_trigger(idx))
2949 if (timer_irq_works()) {
2950 if (nmi_watchdog == NMI_IO_APIC) {
2952 legacy_pic->unmask(0);
2954 if (disable_timer_pin_1 > 0)
2955 clear_IO_APIC_pin(0, pin1);
2958 if (intr_remapping_enabled)
2959 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2960 local_irq_disable();
2961 clear_IO_APIC_pin(apic1, pin1);
2963 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2964 "8254 timer not connected to IO-APIC\n");
2966 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2967 "(IRQ0) through the 8259A ...\n");
2968 apic_printk(APIC_QUIET, KERN_INFO
2969 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2971 * legacy devices should be connected to IO APIC #0
2973 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2974 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2975 legacy_pic->unmask(0);
2976 if (timer_irq_works()) {
2977 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2978 timer_through_8259 = 1;
2979 if (nmi_watchdog == NMI_IO_APIC) {
2980 legacy_pic->mask(0);
2982 legacy_pic->unmask(0);
2987 * Cleanup, just in case ...
2989 local_irq_disable();
2990 legacy_pic->mask(0);
2991 clear_IO_APIC_pin(apic2, pin2);
2992 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2995 if (nmi_watchdog == NMI_IO_APIC) {
2996 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2997 "through the IO-APIC - disabling NMI Watchdog!\n");
2998 nmi_watchdog = NMI_NONE;
3000 #ifdef CONFIG_X86_32
3004 apic_printk(APIC_QUIET, KERN_INFO
3005 "...trying to set up timer as Virtual Wire IRQ...\n");
3007 lapic_register_intr(0);
3008 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3009 legacy_pic->unmask(0);
3011 if (timer_irq_works()) {
3012 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3015 local_irq_disable();
3016 legacy_pic->mask(0);
3017 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3018 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3020 apic_printk(APIC_QUIET, KERN_INFO
3021 "...trying to set up timer as ExtINT IRQ...\n");
3023 legacy_pic->init(0);
3024 legacy_pic->make_irq(0);
3025 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3027 unlock_ExtINT_logic();
3029 if (timer_irq_works()) {
3030 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3033 local_irq_disable();
3034 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3035 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3036 "report. Then try booting with the 'noapic' option.\n");
3038 local_irq_restore(flags);
3042 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3043 * to devices. However there may be an I/O APIC pin available for
3044 * this interrupt regardless. The pin may be left unconnected, but
3045 * typically it will be reused as an ExtINT cascade interrupt for
3046 * the master 8259A. In the MPS case such a pin will normally be
3047 * reported as an ExtINT interrupt in the MP table. With ACPI
3048 * there is no provision for ExtINT interrupts, and in the absence
3049 * of an override it would be treated as an ordinary ISA I/O APIC
3050 * interrupt, that is edge-triggered and unmasked by default. We
3051 * used to do this, but it caused problems on some systems because
3052 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3053 * the same ExtINT cascade interrupt to drive the local APIC of the
3054 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3055 * the I/O APIC in all cases now. No actual device should request
3056 * it anyway. --macro
3058 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3060 void __init setup_IO_APIC(void)
3064 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3066 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3068 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3070 * Set up IO-APIC IRQ routing.
3072 x86_init.mpparse.setup_ioapic_ids();
3075 setup_IO_APIC_irqs();
3076 init_IO_APIC_traps();
3077 if (legacy_pic->nr_legacy_irqs)
3082 * Called after all the initialization is done. If we didnt find any
3083 * APIC bugs then we can allow the modify fast path
3086 static int __init io_apic_bug_finalize(void)
3088 if (sis_apic_bug == -1)
3093 late_initcall(io_apic_bug_finalize);
3095 struct sysfs_ioapic_data {
3096 struct sys_device dev;
3097 struct IO_APIC_route_entry entry[0];
3099 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3101 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3103 struct IO_APIC_route_entry *entry;
3104 struct sysfs_ioapic_data *data;
3107 data = container_of(dev, struct sysfs_ioapic_data, dev);
3108 entry = data->entry;
3109 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3110 *entry = ioapic_read_entry(dev->id, i);
3115 static int ioapic_resume(struct sys_device *dev)
3117 struct IO_APIC_route_entry *entry;
3118 struct sysfs_ioapic_data *data;
3119 unsigned long flags;
3120 union IO_APIC_reg_00 reg_00;
3123 data = container_of(dev, struct sysfs_ioapic_data, dev);
3124 entry = data->entry;
3126 raw_spin_lock_irqsave(&ioapic_lock, flags);
3127 reg_00.raw = io_apic_read(dev->id, 0);
3128 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3129 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3130 io_apic_write(dev->id, 0, reg_00.raw);
3132 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3133 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3134 ioapic_write_entry(dev->id, i, entry[i]);
3139 static struct sysdev_class ioapic_sysdev_class = {
3141 .suspend = ioapic_suspend,
3142 .resume = ioapic_resume,
3145 static int __init ioapic_init_sysfs(void)
3147 struct sys_device * dev;
3150 error = sysdev_class_register(&ioapic_sysdev_class);
3154 for (i = 0; i < nr_ioapics; i++ ) {
3155 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3156 * sizeof(struct IO_APIC_route_entry);
3157 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3158 if (!mp_ioapic_data[i]) {
3159 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3162 dev = &mp_ioapic_data[i]->dev;
3164 dev->cls = &ioapic_sysdev_class;
3165 error = sysdev_register(dev);
3167 kfree(mp_ioapic_data[i]);
3168 mp_ioapic_data[i] = NULL;
3169 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3177 device_initcall(ioapic_init_sysfs);
3180 * Dynamic irq allocate and deallocation
3182 unsigned int create_irq_nr(unsigned int irq_want, int node)
3184 /* Allocate an unused irq */
3187 unsigned long flags;
3188 struct irq_cfg *cfg_new = NULL;
3189 struct irq_desc *desc_new = NULL;
3192 if (irq_want < nr_irqs_gsi)
3193 irq_want = nr_irqs_gsi;
3195 raw_spin_lock_irqsave(&vector_lock, flags);
3196 for (new = irq_want; new < nr_irqs; new++) {
3197 desc_new = irq_to_desc_alloc_node(new, node);
3199 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3202 cfg_new = get_irq_desc_chip_data(desc_new);
3204 if (cfg_new->vector != 0)
3207 desc_new = move_irq_desc(desc_new, node);
3208 cfg_new = get_irq_desc_chip_data(desc_new);
3210 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3214 raw_spin_unlock_irqrestore(&vector_lock, flags);
3217 dynamic_irq_init_keep_chip_data(irq);
3222 int create_irq(void)
3224 int node = cpu_to_node(0);
3225 unsigned int irq_want;
3228 irq_want = nr_irqs_gsi;
3229 irq = create_irq_nr(irq_want, node);
3237 void destroy_irq(unsigned int irq)
3239 unsigned long flags;
3241 dynamic_irq_cleanup_keep_chip_data(irq);
3244 raw_spin_lock_irqsave(&vector_lock, flags);
3245 __clear_irq_vector(irq, get_irq_chip_data(irq));
3246 raw_spin_unlock_irqrestore(&vector_lock, flags);
3250 * MSI message composition
3252 #ifdef CONFIG_PCI_MSI
3253 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3254 struct msi_msg *msg, u8 hpet_id)
3256 struct irq_cfg *cfg;
3264 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3268 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3270 if (irq_remapped(irq)) {
3275 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3276 BUG_ON(ir_index == -1);
3278 prepare_irte(&irte, cfg->vector, dest);
3280 /* Set source-id of interrupt request */
3282 set_msi_sid(&irte, pdev);
3284 set_hpet_sid(&irte, hpet_id);
3286 modify_irte(irq, &irte);
3288 msg->address_hi = MSI_ADDR_BASE_HI;
3289 msg->data = sub_handle;
3290 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3292 MSI_ADDR_IR_INDEX1(ir_index) |
3293 MSI_ADDR_IR_INDEX2(ir_index);
3295 if (x2apic_enabled())
3296 msg->address_hi = MSI_ADDR_BASE_HI |
3297 MSI_ADDR_EXT_DEST_ID(dest);
3299 msg->address_hi = MSI_ADDR_BASE_HI;
3303 ((apic->irq_dest_mode == 0) ?
3304 MSI_ADDR_DEST_MODE_PHYSICAL:
3305 MSI_ADDR_DEST_MODE_LOGICAL) |
3306 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3307 MSI_ADDR_REDIRECTION_CPU:
3308 MSI_ADDR_REDIRECTION_LOWPRI) |
3309 MSI_ADDR_DEST_ID(dest);
3312 MSI_DATA_TRIGGER_EDGE |
3313 MSI_DATA_LEVEL_ASSERT |
3314 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3315 MSI_DATA_DELIVERY_FIXED:
3316 MSI_DATA_DELIVERY_LOWPRI) |
3317 MSI_DATA_VECTOR(cfg->vector);
3323 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3325 struct irq_desc *desc = irq_to_desc(irq);
3326 struct irq_cfg *cfg;
3330 if (set_desc_affinity(desc, mask, &dest))
3333 cfg = get_irq_desc_chip_data(desc);
3335 __get_cached_msi_msg(desc->irq_data.msi_desc, &msg);
3337 msg.data &= ~MSI_DATA_VECTOR_MASK;
3338 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3339 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3340 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3342 __write_msi_msg(desc->irq_data.msi_desc, &msg);
3346 #ifdef CONFIG_INTR_REMAP
3348 * Migrate the MSI irq to another cpumask. This migration is
3349 * done in the process context using interrupt-remapping hardware.
3352 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3354 struct irq_desc *desc = irq_to_desc(irq);
3355 struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
3359 if (get_irte(irq, &irte))
3362 if (set_desc_affinity(desc, mask, &dest))
3365 irte.vector = cfg->vector;
3366 irte.dest_id = IRTE_DEST(dest);
3369 * atomically update the IRTE with the new destination and vector.
3371 modify_irte(irq, &irte);
3374 * After this point, all the interrupts will start arriving
3375 * at the new destination. So, time to cleanup the previous
3376 * vector allocation.
3378 if (cfg->move_in_progress)
3379 send_cleanup_vector(cfg);
3385 #endif /* CONFIG_SMP */
3388 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3389 * which implement the MSI or MSI-X Capability Structure.
3391 static struct irq_chip msi_chip = {
3393 .irq_unmask = unmask_msi_irq,
3394 .irq_mask = mask_msi_irq,
3395 .irq_ack = ack_apic_edge,
3397 .set_affinity = set_msi_irq_affinity,
3399 .irq_retrigger = ioapic_retrigger_irq,
3402 static struct irq_chip msi_ir_chip = {
3403 .name = "IR-PCI-MSI",
3404 .irq_unmask = unmask_msi_irq,
3405 .irq_mask = mask_msi_irq,
3406 #ifdef CONFIG_INTR_REMAP
3407 .irq_ack = ir_ack_apic_edge,
3409 .set_affinity = ir_set_msi_irq_affinity,
3412 .irq_retrigger = ioapic_retrigger_irq,
3416 * Map the PCI dev to the corresponding remapping hardware unit
3417 * and allocate 'nvec' consecutive interrupt-remapping table entries
3420 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3422 struct intel_iommu *iommu;
3425 iommu = map_dev_to_ir(dev);
3428 "Unable to map PCI %s to iommu\n", pci_name(dev));
3432 index = alloc_irte(iommu, irq, nvec);
3435 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3442 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3447 ret = msi_compose_msg(dev, irq, &msg, -1);
3451 set_irq_msi(irq, msidesc);
3452 write_msi_msg(irq, &msg);
3454 if (irq_remapped(irq)) {
3455 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3456 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3458 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3460 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3465 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3467 int node, ret, sub_handle, index = 0;
3468 unsigned int irq, irq_want;
3469 struct msi_desc *msidesc;
3470 struct intel_iommu *iommu = NULL;
3472 /* x86 doesn't support multiple MSI yet */
3473 if (type == PCI_CAP_ID_MSI && nvec > 1)
3476 node = dev_to_node(&dev->dev);
3477 irq_want = nr_irqs_gsi;
3479 list_for_each_entry(msidesc, &dev->msi_list, list) {
3480 irq = create_irq_nr(irq_want, node);
3484 if (!intr_remapping_enabled)
3489 * allocate the consecutive block of IRTE's
3492 index = msi_alloc_irte(dev, irq, nvec);
3498 iommu = map_dev_to_ir(dev);
3504 * setup the mapping between the irq and the IRTE
3505 * base index, the sub_handle pointing to the
3506 * appropriate interrupt remap table entry.
3508 set_irte_irq(irq, iommu, index, sub_handle);
3511 ret = setup_msi_irq(dev, msidesc, irq);
3523 void arch_teardown_msi_irq(unsigned int irq)
3528 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3530 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3532 struct irq_desc *desc = irq_to_desc(irq);
3533 struct irq_cfg *cfg;
3537 if (set_desc_affinity(desc, mask, &dest))
3540 cfg = get_irq_desc_chip_data(desc);
3542 dmar_msi_read(irq, &msg);
3544 msg.data &= ~MSI_DATA_VECTOR_MASK;
3545 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3546 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3547 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3549 dmar_msi_write(irq, &msg);
3554 #endif /* CONFIG_SMP */
3556 static struct irq_chip dmar_msi_type = {
3558 .irq_unmask = dmar_msi_unmask,
3559 .irq_mask = dmar_msi_mask,
3560 .irq_ack = ack_apic_edge,
3562 .set_affinity = dmar_msi_set_affinity,
3564 .irq_retrigger = ioapic_retrigger_irq,
3567 int arch_setup_dmar_msi(unsigned int irq)
3572 ret = msi_compose_msg(NULL, irq, &msg, -1);
3575 dmar_msi_write(irq, &msg);
3576 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3582 #ifdef CONFIG_HPET_TIMER
3585 static int hpet_msi_set_affinity(struct irq_data *data,
3586 const struct cpumask *mask, bool force)
3588 struct irq_desc *desc = irq_to_desc(data->irq);
3589 struct irq_cfg *cfg = data->chip_data;
3593 if (set_desc_affinity(desc, mask, &dest))
3596 hpet_msi_read(data->handler_data, &msg);
3598 msg.data &= ~MSI_DATA_VECTOR_MASK;
3599 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3600 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3601 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3603 hpet_msi_write(data->handler_data, &msg);
3608 #endif /* CONFIG_SMP */
3610 static struct irq_chip ir_hpet_msi_type = {
3611 .name = "IR-HPET_MSI",
3612 .irq_unmask = hpet_msi_unmask,
3613 .irq_mask = hpet_msi_mask,
3614 #ifdef CONFIG_INTR_REMAP
3615 .irq_ack = ir_ack_apic_edge,
3617 .set_affinity = ir_set_msi_irq_affinity,
3620 .irq_retrigger = ioapic_retrigger_irq,
3623 static struct irq_chip hpet_msi_type = {
3625 .irq_unmask = hpet_msi_unmask,
3626 .irq_mask = hpet_msi_mask,
3627 .irq_ack = ack_apic_edge,
3629 .irq_set_affinity = hpet_msi_set_affinity,
3631 .irq_retrigger = ioapic_retrigger_irq,
3634 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3639 if (intr_remapping_enabled) {
3640 struct intel_iommu *iommu = map_hpet_to_ir(id);
3646 index = alloc_irte(iommu, irq, 1);
3651 ret = msi_compose_msg(NULL, irq, &msg, id);
3655 hpet_msi_write(get_irq_data(irq), &msg);
3656 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3657 if (irq_remapped(irq))
3658 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3659 handle_edge_irq, "edge");
3661 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3662 handle_edge_irq, "edge");
3668 #endif /* CONFIG_PCI_MSI */
3670 * Hypertransport interrupt support
3672 #ifdef CONFIG_HT_IRQ
3676 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3678 struct ht_irq_msg msg;
3679 fetch_ht_irq_msg(irq, &msg);
3681 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3682 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3684 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3685 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3687 write_ht_irq_msg(irq, &msg);
3690 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3692 struct irq_desc *desc = irq_to_desc(irq);
3693 struct irq_cfg *cfg;
3696 if (set_desc_affinity(desc, mask, &dest))
3699 cfg = get_irq_desc_chip_data(desc);
3701 target_ht_irq(irq, dest, cfg->vector);
3708 static struct irq_chip ht_irq_chip = {
3710 .irq_mask = mask_ht_irq,
3711 .irq_unmask = unmask_ht_irq,
3712 .irq_ack = ack_apic_edge,
3714 .set_affinity = set_ht_irq_affinity,
3716 .irq_retrigger = ioapic_retrigger_irq,
3719 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3721 struct irq_cfg *cfg;
3728 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3730 struct ht_irq_msg msg;
3733 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3734 apic->target_cpus());
3736 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3740 HT_IRQ_LOW_DEST_ID(dest) |
3741 HT_IRQ_LOW_VECTOR(cfg->vector) |
3742 ((apic->irq_dest_mode == 0) ?
3743 HT_IRQ_LOW_DM_PHYSICAL :
3744 HT_IRQ_LOW_DM_LOGICAL) |
3745 HT_IRQ_LOW_RQEOI_EDGE |
3746 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3747 HT_IRQ_LOW_MT_FIXED :
3748 HT_IRQ_LOW_MT_ARBITRATED) |
3749 HT_IRQ_LOW_IRQ_MASKED;
3751 write_ht_irq_msg(irq, &msg);
3753 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3754 handle_edge_irq, "edge");
3756 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3760 #endif /* CONFIG_HT_IRQ */
3762 int __init io_apic_get_redir_entries (int ioapic)
3764 union IO_APIC_reg_01 reg_01;
3765 unsigned long flags;
3767 raw_spin_lock_irqsave(&ioapic_lock, flags);
3768 reg_01.raw = io_apic_read(ioapic, 1);
3769 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3771 /* The register returns the maximum index redir index
3772 * supported, which is one less than the total number of redir
3775 return reg_01.bits.entries + 1;
3778 void __init probe_nr_irqs_gsi(void)
3782 nr = gsi_top + NR_IRQS_LEGACY;
3783 if (nr > nr_irqs_gsi)
3786 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3789 #ifdef CONFIG_SPARSE_IRQ
3790 int __init arch_probe_nr_irqs(void)
3794 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3795 nr_irqs = NR_VECTORS * nr_cpu_ids;
3797 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3798 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3800 * for MSI and HT dyn irq
3802 nr += nr_irqs_gsi * 16;
3807 return NR_IRQS_LEGACY;
3811 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3812 struct io_apic_irq_attr *irq_attr)
3814 struct irq_desc *desc;
3815 struct irq_cfg *cfg;
3818 int trigger, polarity;
3820 ioapic = irq_attr->ioapic;
3821 if (!IO_APIC_IRQ(irq)) {
3822 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3828 node = dev_to_node(dev);
3830 node = cpu_to_node(0);
3832 desc = irq_to_desc_alloc_node(irq, node);
3834 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3838 pin = irq_attr->ioapic_pin;
3839 trigger = irq_attr->trigger;
3840 polarity = irq_attr->polarity;
3842 cfg = get_irq_desc_chip_data(desc);
3845 * IRQs < 16 are already in the irq_2_pin[] map
3847 if (irq >= legacy_pic->nr_legacy_irqs) {
3848 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3849 printk(KERN_INFO "can not add pin %d for irq %d\n",
3855 setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
3860 int io_apic_set_pci_routing(struct device *dev, int irq,
3861 struct io_apic_irq_attr *irq_attr)
3865 * Avoid pin reprogramming. PRTs typically include entries
3866 * with redundant pin->gsi mappings (but unique PCI devices);
3867 * we only program the IOAPIC on the first.
3869 ioapic = irq_attr->ioapic;
3870 pin = irq_attr->ioapic_pin;
3871 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3872 pr_debug("Pin %d-%d already programmed\n",
3873 mp_ioapics[ioapic].apicid, pin);
3876 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3878 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3881 u8 __init io_apic_unique_id(u8 id)
3883 #ifdef CONFIG_X86_32
3884 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3885 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3886 return io_apic_get_unique_id(nr_ioapics, id);
3891 DECLARE_BITMAP(used, 256);
3893 bitmap_zero(used, 256);
3894 for (i = 0; i < nr_ioapics; i++) {
3895 struct mpc_ioapic *ia = &mp_ioapics[i];
3896 __set_bit(ia->apicid, used);
3898 if (!test_bit(id, used))
3900 return find_first_zero_bit(used, 256);
3904 #ifdef CONFIG_X86_32
3905 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3907 union IO_APIC_reg_00 reg_00;
3908 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3910 unsigned long flags;
3914 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3915 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3916 * supports up to 16 on one shared APIC bus.
3918 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3919 * advantage of new APIC bus architecture.
3922 if (physids_empty(apic_id_map))
3923 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3925 raw_spin_lock_irqsave(&ioapic_lock, flags);
3926 reg_00.raw = io_apic_read(ioapic, 0);
3927 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3929 if (apic_id >= get_physical_broadcast()) {
3930 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3931 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3932 apic_id = reg_00.bits.ID;
3936 * Every APIC in a system must have a unique ID or we get lots of nice
3937 * 'stuck on smp_invalidate_needed IPI wait' messages.
3939 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3941 for (i = 0; i < get_physical_broadcast(); i++) {
3942 if (!apic->check_apicid_used(&apic_id_map, i))
3946 if (i == get_physical_broadcast())
3947 panic("Max apic_id exceeded!\n");
3949 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3950 "trying %d\n", ioapic, apic_id, i);
3955 apic->apicid_to_cpu_present(apic_id, &tmp);
3956 physids_or(apic_id_map, apic_id_map, tmp);
3958 if (reg_00.bits.ID != apic_id) {
3959 reg_00.bits.ID = apic_id;
3961 raw_spin_lock_irqsave(&ioapic_lock, flags);
3962 io_apic_write(ioapic, 0, reg_00.raw);
3963 reg_00.raw = io_apic_read(ioapic, 0);
3964 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3967 if (reg_00.bits.ID != apic_id) {
3968 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3973 apic_printk(APIC_VERBOSE, KERN_INFO
3974 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3980 int __init io_apic_get_version(int ioapic)
3982 union IO_APIC_reg_01 reg_01;
3983 unsigned long flags;
3985 raw_spin_lock_irqsave(&ioapic_lock, flags);
3986 reg_01.raw = io_apic_read(ioapic, 1);
3987 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3989 return reg_01.bits.version;
3992 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3994 int ioapic, pin, idx;
3996 if (skip_ioapic_setup)
3999 ioapic = mp_find_ioapic(gsi);
4003 pin = mp_find_ioapic_pin(ioapic, gsi);
4007 idx = find_irq_entry(ioapic, pin, mp_INT);
4011 *trigger = irq_trigger(idx);
4012 *polarity = irq_polarity(idx);
4017 * This function currently is only a helper for the i386 smp boot process where
4018 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4019 * so mask in all cases should simply be apic->target_cpus()
4022 void __init setup_ioapic_dest(void)
4024 int pin, ioapic, irq, irq_entry;
4025 struct irq_desc *desc;
4026 const struct cpumask *mask;
4028 if (skip_ioapic_setup == 1)
4031 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4032 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4033 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4034 if (irq_entry == -1)
4036 irq = pin_2_irq(irq_entry, ioapic, pin);
4038 if ((ioapic > 0) && (irq > 16))
4041 desc = irq_to_desc(irq);
4044 * Honour affinities which have been set in early boot
4047 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4048 mask = desc->affinity;
4050 mask = apic->target_cpus();
4052 if (intr_remapping_enabled)
4053 set_ir_ioapic_affinity_irq_desc(desc, mask);
4055 set_ioapic_affinity_irq_desc(desc, mask);
4061 #define IOAPIC_RESOURCE_NAME_SIZE 11
4063 static struct resource *ioapic_resources;
4065 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4068 struct resource *res;
4072 if (nr_ioapics <= 0)
4075 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4078 mem = alloc_bootmem(n);
4081 mem += sizeof(struct resource) * nr_ioapics;
4083 for (i = 0; i < nr_ioapics; i++) {
4085 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4086 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4087 mem += IOAPIC_RESOURCE_NAME_SIZE;
4090 ioapic_resources = res;
4095 void __init ioapic_init_mappings(void)
4097 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4098 struct resource *ioapic_res;
4101 ioapic_res = ioapic_setup_resources(nr_ioapics);
4102 for (i = 0; i < nr_ioapics; i++) {
4103 if (smp_found_config) {
4104 ioapic_phys = mp_ioapics[i].apicaddr;
4105 #ifdef CONFIG_X86_32
4108 "WARNING: bogus zero IO-APIC "
4109 "address found in MPTABLE, "
4110 "disabling IO/APIC support!\n");
4111 smp_found_config = 0;
4112 skip_ioapic_setup = 1;
4113 goto fake_ioapic_page;
4117 #ifdef CONFIG_X86_32
4120 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4121 ioapic_phys = __pa(ioapic_phys);
4123 set_fixmap_nocache(idx, ioapic_phys);
4124 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4125 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4129 ioapic_res->start = ioapic_phys;
4130 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4135 void __init ioapic_insert_resources(void)
4138 struct resource *r = ioapic_resources;
4143 "IO APIC resources couldn't be allocated.\n");
4147 for (i = 0; i < nr_ioapics; i++) {
4148 insert_resource(&iomem_resource, r);
4153 int mp_find_ioapic(u32 gsi)
4157 /* Find the IOAPIC that manages this GSI. */
4158 for (i = 0; i < nr_ioapics; i++) {
4159 if ((gsi >= mp_gsi_routing[i].gsi_base)
4160 && (gsi <= mp_gsi_routing[i].gsi_end))
4164 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4168 int mp_find_ioapic_pin(int ioapic, u32 gsi)
4170 if (WARN_ON(ioapic == -1))
4172 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4175 return gsi - mp_gsi_routing[ioapic].gsi_base;
4178 static int bad_ioapic(unsigned long address)
4180 if (nr_ioapics >= MAX_IO_APICS) {
4181 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4182 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4186 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4187 " found in table, skipping!\n");
4193 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4198 if (bad_ioapic(address))
4203 mp_ioapics[idx].type = MP_IOAPIC;
4204 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4205 mp_ioapics[idx].apicaddr = address;
4207 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4208 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4209 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4212 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4213 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4215 entries = io_apic_get_redir_entries(idx);
4216 mp_gsi_routing[idx].gsi_base = gsi_base;
4217 mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
4220 * The number of IO-APIC IRQ registers (== #pins):
4222 nr_ioapic_registers[idx] = entries;
4224 if (mp_gsi_routing[idx].gsi_end >= gsi_top)
4225 gsi_top = mp_gsi_routing[idx].gsi_end + 1;
4227 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4228 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4229 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4230 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4235 /* Enable IOAPIC early just for system timer */
4236 void __init pre_init_apic_IRQ0(void)
4238 struct irq_cfg *cfg;
4240 printk(KERN_INFO "Early APIC setup for system timer0\n");
4242 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4244 irq_to_desc_alloc_node(0, 0);
4249 add_pin_to_irq_node(cfg, 0, 0, 0);
4250 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4252 setup_ioapic_irq(0, 0, 0, cfg, 0, 0);