1 /* linux/arch/arm/mach-s5pv310/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV310 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
27 static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
33 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
35 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
38 /* Core list of CMU_CPU side */
40 static struct clksrc_clk clk_mout_apll = {
45 .sources = &clk_src_apll,
46 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
49 static struct clksrc_clk clk_sclk_apll = {
53 .parent = &clk_mout_apll.clk,
55 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
58 static struct clksrc_clk clk_mout_epll = {
63 .sources = &clk_src_epll,
64 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
67 static struct clksrc_clk clk_mout_mpll = {
72 .sources = &clk_src_mpll,
73 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
76 static struct clk *clkset_moutcore_list[] = {
77 [0] = &clk_sclk_apll.clk,
78 [1] = &clk_mout_mpll.clk,
81 static struct clksrc_sources clkset_moutcore = {
82 .sources = clkset_moutcore_list,
83 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
86 static struct clksrc_clk clk_moutcore = {
91 .sources = &clkset_moutcore,
92 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
95 static struct clksrc_clk clk_coreclk = {
99 .parent = &clk_moutcore.clk,
101 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
104 static struct clksrc_clk clk_armclk = {
108 .parent = &clk_coreclk.clk,
112 static struct clksrc_clk clk_aclk_corem0 = {
114 .name = "aclk_corem0",
116 .parent = &clk_coreclk.clk,
118 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
121 static struct clksrc_clk clk_aclk_cores = {
123 .name = "aclk_cores",
125 .parent = &clk_coreclk.clk,
127 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
130 static struct clksrc_clk clk_aclk_corem1 = {
132 .name = "aclk_corem1",
134 .parent = &clk_coreclk.clk,
136 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
139 static struct clksrc_clk clk_periphclk = {
143 .parent = &clk_coreclk.clk,
145 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
148 static struct clksrc_clk clk_atclk = {
152 .parent = &clk_moutcore.clk,
154 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
157 static struct clksrc_clk clk_pclk_dbg = {
161 .parent = &clk_atclk.clk,
163 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
166 /* Core list of CMU_CORE side */
168 static struct clk *clkset_corebus_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_sclk_apll.clk,
173 static struct clksrc_sources clkset_mout_corebus = {
174 .sources = clkset_corebus_list,
175 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
178 static struct clksrc_clk clk_mout_corebus = {
180 .name = "mout_corebus",
183 .sources = &clkset_mout_corebus,
184 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
187 static struct clksrc_clk clk_sclk_dmc = {
191 .parent = &clk_mout_corebus.clk,
193 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
196 static struct clksrc_clk clk_aclk_cored = {
198 .name = "aclk_cored",
200 .parent = &clk_sclk_dmc.clk,
202 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
205 static struct clksrc_clk clk_aclk_corep = {
207 .name = "aclk_corep",
209 .parent = &clk_aclk_cored.clk,
211 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
214 static struct clksrc_clk clk_aclk_acp = {
218 .parent = &clk_mout_corebus.clk,
220 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
223 static struct clksrc_clk clk_pclk_acp = {
227 .parent = &clk_aclk_acp.clk,
229 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
232 /* Core list of CMU_TOP side */
234 static struct clk *clkset_aclk_top_list[] = {
235 [0] = &clk_mout_mpll.clk,
236 [1] = &clk_sclk_apll.clk,
239 static struct clksrc_sources clkset_aclk_200 = {
240 .sources = clkset_aclk_top_list,
241 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
244 static struct clksrc_clk clk_aclk_200 = {
249 .sources = &clkset_aclk_200,
250 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
251 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
254 static struct clksrc_sources clkset_aclk_100 = {
255 .sources = clkset_aclk_top_list,
256 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
259 static struct clksrc_clk clk_aclk_100 = {
264 .sources = &clkset_aclk_100,
265 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
266 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
269 static struct clksrc_sources clkset_aclk_160 = {
270 .sources = clkset_aclk_top_list,
271 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
274 static struct clksrc_clk clk_aclk_160 = {
279 .sources = &clkset_aclk_160,
280 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
281 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
284 static struct clksrc_sources clkset_aclk_133 = {
285 .sources = clkset_aclk_top_list,
286 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
289 static struct clksrc_clk clk_aclk_133 = {
294 .sources = &clkset_aclk_133,
295 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
296 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
299 static struct clk *clkset_vpllsrc_list[] = {
301 [1] = &clk_sclk_hdmi27m,
304 static struct clksrc_sources clkset_vpllsrc = {
305 .sources = clkset_vpllsrc_list,
306 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
309 static struct clksrc_clk clk_vpllsrc = {
314 .sources = &clkset_vpllsrc,
315 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
318 static struct clk *clkset_sclk_vpll_list[] = {
319 [0] = &clk_vpllsrc.clk,
320 [1] = &clk_fout_vpll,
323 static struct clksrc_sources clkset_sclk_vpll = {
324 .sources = clkset_sclk_vpll_list,
325 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
328 static struct clksrc_clk clk_sclk_vpll = {
333 .sources = &clkset_sclk_vpll,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
337 static struct clk init_clocks_disable[] = {
341 .parent = &clk_aclk_100.clk,
342 .enable = s5pv310_clk_ip_peril_ctrl,
347 static struct clk init_clocks[] = {
351 .enable = s5pv310_clk_ip_peril_ctrl,
356 .enable = s5pv310_clk_ip_peril_ctrl,
361 .enable = s5pv310_clk_ip_peril_ctrl,
366 .enable = s5pv310_clk_ip_peril_ctrl,
371 .enable = s5pv310_clk_ip_peril_ctrl,
376 .enable = s5pv310_clk_ip_peril_ctrl,
381 static struct clk *clkset_group_list[] = {
382 [0] = &clk_ext_xtal_mux,
384 [2] = &clk_sclk_hdmi27m,
385 [6] = &clk_mout_mpll.clk,
386 [7] = &clk_mout_epll.clk,
387 [8] = &clk_sclk_vpll.clk,
390 static struct clksrc_sources clkset_group = {
391 .sources = clkset_group_list,
392 .nr_sources = ARRAY_SIZE(clkset_group_list),
395 static struct clksrc_clk clksrcs[] = {
400 .enable = s5pv310_clk_ip_peril_ctrl,
403 .sources = &clkset_group,
404 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
405 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
410 .enable = s5pv310_clk_ip_peril_ctrl,
413 .sources = &clkset_group,
414 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
415 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
420 .enable = s5pv310_clk_ip_peril_ctrl,
423 .sources = &clkset_group,
424 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
425 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
430 .enable = s5pv310_clk_ip_peril_ctrl,
433 .sources = &clkset_group,
434 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
435 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
440 .enable = s5pv310_clk_ip_peril_ctrl,
441 .ctrlbit = (1 << 24),
443 .sources = &clkset_group,
444 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
445 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
449 /* Clock initialization code */
450 static struct clksrc_clk *sysclks[] = {
478 void __init_or_cpufreq s5pv310_setup_clocks(void)
480 struct clk *xtal_clk;
485 unsigned long vpllsrc;
487 unsigned long armclk;
488 unsigned long aclk_corem0;
489 unsigned long aclk_cores;
490 unsigned long aclk_corem1;
491 unsigned long periphclk;
492 unsigned long sclk_dmc;
493 unsigned long aclk_cored;
494 unsigned long aclk_corep;
495 unsigned long aclk_acp;
496 unsigned long pclk_acp;
499 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
501 xtal_clk = clk_get(NULL, "xtal");
502 BUG_ON(IS_ERR(xtal_clk));
504 xtal = clk_get_rate(xtal_clk);
507 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
509 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
510 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
511 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
512 __raw_readl(S5P_EPLL_CON1), pll_4600);
514 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
515 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
516 __raw_readl(S5P_VPLL_CON1), pll_4650);
518 clk_fout_apll.rate = apll;
519 clk_fout_mpll.rate = mpll;
520 clk_fout_epll.rate = epll;
521 clk_fout_vpll.rate = vpll;
523 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
524 apll, mpll, epll, vpll);
526 armclk = clk_get_rate(&clk_armclk.clk);
527 aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
528 aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
529 aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
530 periphclk = clk_get_rate(&clk_periphclk.clk);
531 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
532 aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
533 aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
534 aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
535 pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
537 printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
538 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
539 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
540 armclk, aclk_corem0, aclk_cores, aclk_corem1,
541 periphclk, sclk_dmc, aclk_cored, aclk_corep,
545 clk_h.rate = sclk_dmc;
546 clk_p.rate = periphclk;
548 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
549 s3c_set_clksrc(&clksrcs[ptr], true);
552 static struct clk *clks[] __initdata = {
553 /* Nothing here yet */
556 void __init s5pv310_register_clocks(void)
562 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
564 printk(KERN_ERR "Failed to register %u clocks\n", ret);
566 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
567 s3c_register_clksrc(sysclks[ptr], 1);
569 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
570 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
572 clkp = init_clocks_disable;
573 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
574 ret = s3c24xx_register_clock(clkp);
576 printk(KERN_ERR "Failed to register clock %s (%d)\n",
579 (clkp->enable)(clkp, 0);