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gianfar: Revive the driver for eTSEC devices (disable timestamping)
[net-next-2.6.git] / drivers / net / gianfar.c
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0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
cc772ab7 85#include <linux/net_tstamp.h>
1da177e4
LT		 86
87#include <asm/io.h>
88#include <asm/irq.h>
89#include <asm/uaccess.h>
90#include <linux/module.h>
1da177e4
LT		 91#include <linux/dma-mapping.h>
92#include <linux/crc32.h>
bb40dcbb
AF		 93#include <linux/mii.h>
94#include <linux/phy.h>
b31a1d8b
AF		 95#include <linux/phy_fixed.h>
96#include <linux/of.h>
1da177e4
LT		 97
98#include "gianfar.h"
1577ecef 99#include "fsl_pq_mdio.h"
1da177e4
LT		 100
101#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 102#undef BRIEF_GFAR_ERRORS
103#undef VERBOSE_GFAR_ERRORS
104
1da177e4 105const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 106const char gfar_driver_version[] = "1.3";
1da177e4 107
1da177e4
LT		 108static int gfar_enet_open(struct net_device *dev);
109static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 110static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 111static void gfar_timeout(struct net_device *dev);
112static int gfar_close(struct net_device *dev);
815b97c6 113struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 114static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 115 struct sk_buff *skb);
1da177e4
LT		 116static int gfar_set_mac_address(struct net_device *dev);
117static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 118static irqreturn_t gfar_error(int irq, void *dev_id);
119static irqreturn_t gfar_transmit(int irq, void *dev_id);
120static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 121static void adjust_link(struct net_device *dev);
122static void init_registers(struct net_device *dev);
123static int init_phy(struct net_device *dev);
b31a1d8b
AF		 124static int gfar_probe(struct of_device *ofdev,
125 const struct of_device_id *match);
126static int gfar_remove(struct of_device *ofdev);
bb40dcbb 127static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 130static void gfar_configure_serdes(struct net_device *dev);
bea3348e 131static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 132#ifdef CONFIG_NET_POLL_CONTROLLER
133static void gfar_netpoll(struct net_device *dev);
134#endif
a12f801d
SG		 135int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
136static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 137static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
138 int amount_pull);
0bbaf069
KG		 139static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
7f7f5316 141void gfar_halt(struct net_device *dev);
d87eb127 142static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 143void gfar_start(struct net_device *dev);
144static void gfar_clear_exact_match(struct net_device *dev);
145static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 146static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 pr_err("%s: Can't allocate RX buffers\n",
215 ndev->name);
216 goto err_rxalloc_fail;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 221 }
8728327e 222
fba4ed03 223 rxbdp++;
8728327e
AV		 224 }
225
8728327e
AV		 226 }
227
228 return 0;
fba4ed03
SG		 229
230err_rxalloc_fail:
231 free_skb_resources(priv);
232 return -ENOMEM;
8728327e
AV		 233}
234
235static int gfar_alloc_skb_resources(struct net_device *ndev)
236{
826aa4a0 237 void *vaddr;
fba4ed03
SG		 238 dma_addr_t addr;
239 int i, j, k;
826aa4a0
AV		 240 struct gfar_private *priv = netdev_priv(ndev);
241 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 242 struct gfar_priv_tx_q *tx_queue = NULL;
243 struct gfar_priv_rx_q *rx_queue = NULL;
244
fba4ed03
SG		 245 priv->total_tx_ring_size = 0;
246 for (i = 0; i < priv->num_tx_queues; i++)
247 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249 priv->total_rx_ring_size = 0;
250 for (i = 0; i < priv->num_rx_queues; i++)
251 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 252
253 /* Allocate memory for the buffer descriptors */
8728327e 254 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 255 sizeof(struct txbd8) * priv->total_tx_ring_size +
256 sizeof(struct rxbd8) * priv->total_rx_ring_size,
257 &addr, GFP_KERNEL);
826aa4a0
AV		 258 if (!vaddr) {
259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
261 ndev->name);
262 return -ENOMEM;
263 }
264
fba4ed03
SG		 265 for (i = 0; i < priv->num_tx_queues; i++) {
266 tx_queue = priv->tx_queue[i];
267 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268 tx_queue->tx_bd_dma_base = addr;
269 tx_queue->dev = ndev;
270 /* enet DMA only understands physical addresses */
271 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 }
826aa4a0 274
826aa4a0 275 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 276 for (i = 0; i < priv->num_rx_queues; i++) {
277 rx_queue = priv->rx_queue[i];
278 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279 rx_queue->rx_bd_dma_base = addr;
280 rx_queue->dev = ndev;
281 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 }
826aa4a0
AV		 284
285 /* Setup the skbuff rings */
fba4ed03
SG		 286 for (i = 0; i < priv->num_tx_queues; i++) {
287 tx_queue = priv->tx_queue[i];
288 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 289 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 290 if (!tx_queue->tx_skbuff) {
291 if (netif_msg_ifup(priv))
292 pr_err("%s: Could not allocate tx_skbuff\n",
293 ndev->name);
294 goto cleanup;
295 }
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 304 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 305
fba4ed03
SG		 306 if (!rx_queue->rx_skbuff) {
307 if (netif_msg_ifup(priv))
308 pr_err("%s: Could not allocate rx_skbuff\n",
309 ndev->name);
310 goto cleanup;
311 }
312
313 for (j = 0; j < rx_queue->rx_ring_size; j++)
314 rx_queue->rx_skbuff[j] = NULL;
315 }
826aa4a0 316
8728327e
AV		 317 if (gfar_init_bds(ndev))
318 goto cleanup;
826aa4a0
AV		 319
320 return 0;
321
322cleanup:
323 free_skb_resources(priv);
324 return -ENOMEM;
325}
326
fba4ed03
SG		 327static void gfar_init_tx_rx_base(struct gfar_private *priv)
328{
46ceb60c 329 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 330 u32 __iomem *baddr;
fba4ed03
SG		 331 int i;
332
333 baddr = &regs->tbase0;
334 for(i = 0; i < priv->num_tx_queues; i++) {
335 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr += 2;
337 }
338
339 baddr = &regs->rbase0;
340 for(i = 0; i < priv->num_rx_queues; i++) {
341 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 baddr += 2;
343 }
344}
345
826aa4a0
AV		 346static void gfar_init_mac(struct net_device *ndev)
347{
348 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 349 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 350 u32 rctrl = 0;
351 u32 tctrl = 0;
352 u32 attrs = 0;
353
fba4ed03
SG		 354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv);
32c513bc 356
826aa4a0 357 /* Configure the coalescing support */
46ceb60c 358 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 359
1ccb8389 360 if (priv->rx_filer_enable) {
fba4ed03 361 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 362 /* Program the RIR0 reg with the required distribution */
363 gfar_write(&regs->rir0, DEFAULT_RIR0);
364 }
826aa4a0
AV		 365
366 if (priv->rx_csum_enable)
367 rctrl |= RCTRL_CHECKSUMMING;
368
369 if (priv->extended_hash) {
370 rctrl |= RCTRL_EXTHASH;
371
372 gfar_clear_exact_match(ndev);
373 rctrl |= RCTRL_EMEN;
374 }
375
376 if (priv->padding) {
377 rctrl &= ~RCTRL_PAL_MASK;
378 rctrl |= RCTRL_PADDING(priv->padding);
379 }
380
cc772ab7
MR		 381 /* Insert receive time stamps into padding alignment bytes */
382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
383 rctrl &= ~RCTRL_PAL_MASK;
384 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8);
385 priv->padding = 8;
386 }
387
826aa4a0
AV		 388 /* keep vlan related bits if it's enabled */
389 if (priv->vlgrp) {
390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 tctrl |= TCTRL_VLINS;
392 }
393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
396
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
399
fba4ed03
SG		 400 tctrl |= TCTRL_TXSCHED_PRIO;
401
826aa4a0
AV		 402 gfar_write(&regs->tctrl, tctrl);
403
404 /* Set the extraction length and index */
405 attrs = ATTRELI_EL(priv->rx_stash_size) |
406 ATTRELI_EI(priv->rx_stash_index);
407
408 gfar_write(&regs->attreli, attrs);
409
410 /* Start with defaults, and add stashing or locking
411 * depending on the approprate variables */
412 attrs = ATTR_INIT_SETTINGS;
413
414 if (priv->bd_stash_en)
415 attrs |= ATTR_BDSTASH;
416
417 if (priv->rx_stash_size != 0)
418 attrs |= ATTR_BUFSTASH;
419
420 gfar_write(&regs->attr, attrs);
421
422 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
423 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
424 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
425}
426
a7f38041
SG		 427static struct net_device_stats *gfar_get_stats(struct net_device *dev)
428{
429 struct gfar_private *priv = netdev_priv(dev);
430 struct netdev_queue *txq;
431 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
432 unsigned long tx_packets = 0, tx_bytes = 0;
433 int i = 0;
434
435 for (i = 0; i < priv->num_rx_queues; i++) {
436 rx_packets += priv->rx_queue[i]->stats.rx_packets;
437 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
438 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
439 }
440
441 dev->stats.rx_packets = rx_packets;
442 dev->stats.rx_bytes = rx_bytes;
443 dev->stats.rx_dropped = rx_dropped;
444
445 for (i = 0; i < priv->num_tx_queues; i++) {
446 txq = netdev_get_tx_queue(dev, i);
447 tx_bytes += txq->tx_bytes;
448 tx_packets += txq->tx_packets;
449 }
450
451 dev->stats.tx_bytes = tx_bytes;
452 dev->stats.tx_packets = tx_packets;
453
454 return &dev->stats;
455}
456
26ccfc37
AF		 457static const struct net_device_ops gfar_netdev_ops = {
458 .ndo_open = gfar_enet_open,
459 .ndo_start_xmit = gfar_start_xmit,
460 .ndo_stop = gfar_close,
461 .ndo_change_mtu = gfar_change_mtu,
462 .ndo_set_multicast_list = gfar_set_multi,
463 .ndo_tx_timeout = gfar_timeout,
464 .ndo_do_ioctl = gfar_ioctl,
a7f38041 465 .ndo_get_stats = gfar_get_stats,
26ccfc37 466 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 467 .ndo_set_mac_address = eth_mac_addr,
468 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 469#ifdef CONFIG_NET_POLL_CONTROLLER
470 .ndo_poll_controller = gfar_netpoll,
471#endif
472};
473
7a8b3372
SG		 474unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
475unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
476
fba4ed03
SG		 477void lock_rx_qs(struct gfar_private *priv)
478{
479 int i = 0x0;
480
481 for (i = 0; i < priv->num_rx_queues; i++)
482 spin_lock(&priv->rx_queue[i]->rxlock);
483}
484
485void lock_tx_qs(struct gfar_private *priv)
486{
487 int i = 0x0;
488
489 for (i = 0; i < priv->num_tx_queues; i++)
490 spin_lock(&priv->tx_queue[i]->txlock);
491}
492
493void unlock_rx_qs(struct gfar_private *priv)
494{
495 int i = 0x0;
496
497 for (i = 0; i < priv->num_rx_queues; i++)
498 spin_unlock(&priv->rx_queue[i]->rxlock);
499}
500
501void unlock_tx_qs(struct gfar_private *priv)
502{
503 int i = 0x0;
504
505 for (i = 0; i < priv->num_tx_queues; i++)
506 spin_unlock(&priv->tx_queue[i]->txlock);
507}
508
7f7f5316
AF		 509/* Returns 1 if incoming frames use an FCB */
510static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 511{
cc772ab7
MR		 512 return priv->vlgrp || priv->rx_csum_enable ||
513 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 514}
bb40dcbb 515
fba4ed03
SG		 516static void free_tx_pointers(struct gfar_private *priv)
517{
518 int i = 0;
519
520 for (i = 0; i < priv->num_tx_queues; i++)
521 kfree(priv->tx_queue[i]);
522}
523
524static void free_rx_pointers(struct gfar_private *priv)
525{
526 int i = 0;
527
528 for (i = 0; i < priv->num_rx_queues; i++)
529 kfree(priv->rx_queue[i]);
530}
531
46ceb60c
SG		 532static void unmap_group_regs(struct gfar_private *priv)
533{
534 int i = 0;
535
536 for (i = 0; i < MAXGROUPS; i++)
537 if (priv->gfargrp[i].regs)
538 iounmap(priv->gfargrp[i].regs);
539}
540
541static void disable_napi(struct gfar_private *priv)
542{
543 int i = 0;
544
545 for (i = 0; i < priv->num_grps; i++)
546 napi_disable(&priv->gfargrp[i].napi);
547}
548
549static void enable_napi(struct gfar_private *priv)
550{
551 int i = 0;
552
553 for (i = 0; i < priv->num_grps; i++)
554 napi_enable(&priv->gfargrp[i].napi);
555}
556
557static int gfar_parse_group(struct device_node *np,
558 struct gfar_private *priv, const char *model)
559{
560 u32 *queue_mask;
46ceb60c 561
7ce97d4f 562 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 563 if (!priv->gfargrp[priv->num_grps].regs)
564 return -ENOMEM;
565
566 priv->gfargrp[priv->num_grps].interruptTransmit =
567 irq_of_parse_and_map(np, 0);
568
569 /* If we aren't the FEC we have multiple interrupts */
570 if (model && strcasecmp(model, "FEC")) {
571 priv->gfargrp[priv->num_grps].interruptReceive =
572 irq_of_parse_and_map(np, 1);
573 priv->gfargrp[priv->num_grps].interruptError =
574 irq_of_parse_and_map(np,2);
575 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
576 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
577 priv->gfargrp[priv->num_grps].interruptError < 0) {
578 return -EINVAL;
579 }
580 }
581
582 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
583 priv->gfargrp[priv->num_grps].priv = priv;
584 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
585 if(priv->mode == MQ_MG_MODE) {
586 queue_mask = (u32 *)of_get_property(np,
587 "fsl,rx-bit-map", NULL);
588 priv->gfargrp[priv->num_grps].rx_bit_map =
589 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,tx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].tx_bit_map =
593 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594 } else {
595 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
596 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
597 }
598 priv->num_grps++;
599
600 return 0;
601}
602
fba4ed03 603static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
b31a1d8b 604{
b31a1d8b
AF		 605 const char *model;
606 const char *ctype;
607 const void *mac_addr;
fba4ed03
SG		 608 int err = 0, i;
609 struct net_device *dev = NULL;
610 struct gfar_private *priv = NULL;
61c7a080 611 struct device_node *np = ofdev->dev.of_node;
46ceb60c 612 struct device_node *child = NULL;
4d7902f2
AF		 613 const u32 *stash;
614 const u32 *stash_len;
615 const u32 *stash_idx;
fba4ed03
SG		 616 unsigned int num_tx_qs, num_rx_qs;
617 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 618
619 if (!np || !of_device_is_available(np))
620 return -ENODEV;
621
fba4ed03
SG		 622 /* parse the num of tx and rx queues */
623 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
624 num_tx_qs = tx_queues ? *tx_queues : 1;
625
626 if (num_tx_qs > MAX_TX_QS) {
627 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
628 num_tx_qs, MAX_TX_QS);
629 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
630 return -EINVAL;
631 }
632
633 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
634 num_rx_qs = rx_queues ? *rx_queues : 1;
635
636 if (num_rx_qs > MAX_RX_QS) {
637 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
638 num_tx_qs, MAX_TX_QS);
639 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
640 return -EINVAL;
641 }
642
643 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
644 dev = *pdev;
645 if (NULL == dev)
646 return -ENOMEM;
647
648 priv = netdev_priv(dev);
61c7a080 649 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 650 priv->ndev = dev;
651
652 dev->num_tx_queues = num_tx_qs;
653 dev->real_num_tx_queues = num_tx_qs;
654 priv->num_tx_queues = num_tx_qs;
655 priv->num_rx_queues = num_rx_qs;
46ceb60c 656 priv->num_grps = 0x0;
b31a1d8b
AF		 657
658 model = of_get_property(np, "model", NULL);
659
46ceb60c
SG		 660 for (i = 0; i < MAXGROUPS; i++)
661 priv->gfargrp[i].regs = NULL;
b31a1d8b 662
46ceb60c
SG		 663 /* Parse and initialize group specific information */
664 if (of_device_is_compatible(np, "fsl,etsec2")) {
665 priv->mode = MQ_MG_MODE;
666 for_each_child_of_node(np, child) {
667 err = gfar_parse_group(child, priv, model);
668 if (err)
669 goto err_grp_init;
b31a1d8b 670 }
46ceb60c
SG		 671 } else {
672 priv->mode = SQ_SG_MODE;
673 err = gfar_parse_group(np, priv, model);
674 if(err)
675 goto err_grp_init;
b31a1d8b
AF		 676 }
677
fba4ed03
SG		 678 for (i = 0; i < priv->num_tx_queues; i++)
679 priv->tx_queue[i] = NULL;
680 for (i = 0; i < priv->num_rx_queues; i++)
681 priv->rx_queue[i] = NULL;
682
683 for (i = 0; i < priv->num_tx_queues; i++) {
ed130589 684 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc(
fba4ed03
SG		 685 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
686 if (!priv->tx_queue[i]) {
687 err = -ENOMEM;
688 goto tx_alloc_failed;
689 }
690 priv->tx_queue[i]->tx_skbuff = NULL;
691 priv->tx_queue[i]->qindex = i;
692 priv->tx_queue[i]->dev = dev;
693 spin_lock_init(&(priv->tx_queue[i]->txlock));
694 }
695
696 for (i = 0; i < priv->num_rx_queues; i++) {
ed130589 697 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
fba4ed03
SG		 698 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
699 if (!priv->rx_queue[i]) {
700 err = -ENOMEM;
701 goto rx_alloc_failed;
702 }
703 priv->rx_queue[i]->rx_skbuff = NULL;
704 priv->rx_queue[i]->qindex = i;
705 priv->rx_queue[i]->dev = dev;
706 spin_lock_init(&(priv->rx_queue[i]->rxlock));
707 }
708
709
4d7902f2
AF		 710 stash = of_get_property(np, "bd-stash", NULL);
711
a12f801d 712 if (stash) {
4d7902f2
AF		 713 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
714 priv->bd_stash_en = 1;
715 }
716
717 stash_len = of_get_property(np, "rx-stash-len", NULL);
718
719 if (stash_len)
720 priv->rx_stash_size = *stash_len;
721
722 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
723
724 if (stash_idx)
725 priv->rx_stash_index = *stash_idx;
726
727 if (stash_len || stash_idx)
728 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
729
b31a1d8b
AF		 730 mac_addr = of_get_mac_address(np);
731 if (mac_addr)
732 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
733
734 if (model && !strcasecmp(model, "TSEC"))
735 priv->device_flags =
736 FSL_GIANFAR_DEV_HAS_GIGABIT |
737 FSL_GIANFAR_DEV_HAS_COALESCE |
738 FSL_GIANFAR_DEV_HAS_RMON |
739 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
740 if (model && !strcasecmp(model, "eTSEC"))
741 priv->device_flags =
742 FSL_GIANFAR_DEV_HAS_GIGABIT |
743 FSL_GIANFAR_DEV_HAS_COALESCE |
744 FSL_GIANFAR_DEV_HAS_RMON |
745 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 746 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 747 FSL_GIANFAR_DEV_HAS_CSUM |
748 FSL_GIANFAR_DEV_HAS_VLAN |
749 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
619baba1 750 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
b31a1d8b
AF		 751
752 ctype = of_get_property(np, "phy-connection-type", NULL);
753
754 /* We only care about rgmii-id. The rest are autodetected */
755 if (ctype && !strcmp(ctype, "rgmii-id"))
756 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
757 else
758 priv->interface = PHY_INTERFACE_MODE_MII;
759
760 if (of_get_property(np, "fsl,magic-packet", NULL))
761 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
762
fe192a49 763 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 764
765 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 766 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 767
768 return 0;
769
fba4ed03
SG		 770rx_alloc_failed:
771 free_rx_pointers(priv);
772tx_alloc_failed:
773 free_tx_pointers(priv);
46ceb60c
SG		 774err_grp_init:
775 unmap_group_regs(priv);
fba4ed03 776 free_netdev(dev);
b31a1d8b
AF		 777 return err;
778}
779
cc772ab7
MR		 780static int gfar_hwtstamp_ioctl(struct net_device *netdev,
781 struct ifreq *ifr, int cmd)
782{
783 struct hwtstamp_config config;
784 struct gfar_private *priv = netdev_priv(netdev);
785
786 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
787 return -EFAULT;
788
789 /* reserved for future extensions */
790 if (config.flags)
791 return -EINVAL;
792
f0ee7acf
MR		 793 switch (config.tx_type) {
794 case HWTSTAMP_TX_OFF:
795 priv->hwts_tx_en = 0;
796 break;
797 case HWTSTAMP_TX_ON:
798 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
799 return -ERANGE;
800 priv->hwts_tx_en = 1;
801 break;
802 default:
cc772ab7 803 return -ERANGE;
f0ee7acf 804 }
cc772ab7
MR		 805
806 switch (config.rx_filter) {
807 case HWTSTAMP_FILTER_NONE:
808 priv->hwts_rx_en = 0;
809 break;
810 default:
811 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
812 return -ERANGE;
813 priv->hwts_rx_en = 1;
814 config.rx_filter = HWTSTAMP_FILTER_ALL;
815 break;
816 }
817
818 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
819 -EFAULT : 0;
820}
821
0faac9f7
CW		 822/* Ioctl MII Interface */
823static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
824{
825 struct gfar_private *priv = netdev_priv(dev);
826
827 if (!netif_running(dev))
828 return -EINVAL;
829
cc772ab7
MR		 830 if (cmd == SIOCSHWTSTAMP)
831 return gfar_hwtstamp_ioctl(dev, rq, cmd);
832
0faac9f7
CW		 833 if (!priv->phydev)
834 return -ENODEV;
835
836 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
837}
838
fba4ed03
SG		 839static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
840{
841 unsigned int new_bit_map = 0x0;
842 int mask = 0x1 << (max_qs - 1), i;
843 for (i = 0; i < max_qs; i++) {
844 if (bit_map & mask)
845 new_bit_map = new_bit_map + (1 << i);
846 mask = mask >> 0x1;
847 }
848 return new_bit_map;
849}
7a8b3372 850
18294ad1
AV		 851static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
852 u32 class)
7a8b3372
SG		 853{
854 u32 rqfpr = FPR_FILER_MASK;
855 u32 rqfcr = 0x0;
856
857 rqfar--;
858 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
859 ftp_rqfpr[rqfar] = rqfpr;
860 ftp_rqfcr[rqfar] = rqfcr;
861 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
862
863 rqfar--;
864 rqfcr = RQFCR_CMP_NOMATCH;
865 ftp_rqfpr[rqfar] = rqfpr;
866 ftp_rqfcr[rqfar] = rqfcr;
867 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
868
869 rqfar--;
870 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
871 rqfpr = class;
872 ftp_rqfcr[rqfar] = rqfcr;
873 ftp_rqfpr[rqfar] = rqfpr;
874 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
875
876 rqfar--;
877 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
878 rqfpr = class;
879 ftp_rqfcr[rqfar] = rqfcr;
880 ftp_rqfpr[rqfar] = rqfpr;
881 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
882
883 return rqfar;
884}
885
886static void gfar_init_filer_table(struct gfar_private *priv)
887{
888 int i = 0x0;
889 u32 rqfar = MAX_FILER_IDX;
890 u32 rqfcr = 0x0;
891 u32 rqfpr = FPR_FILER_MASK;
892
893 /* Default rule */
894 rqfcr = RQFCR_CMP_MATCH;
895 ftp_rqfcr[rqfar] = rqfcr;
896 ftp_rqfpr[rqfar] = rqfpr;
897 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
898
899 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
905
906 /* cur_filer_idx indicated the fisrt non-masked rule */
907 priv->cur_filer_idx = rqfar;
908
909 /* Rest are masked rules */
910 rqfcr = RQFCR_CMP_NOMATCH;
911 for (i = 0; i < rqfar; i++) {
912 ftp_rqfcr[i] = rqfcr;
913 ftp_rqfpr[i] = rqfpr;
914 gfar_write_filer(priv, i, rqfcr, rqfpr);
915 }
916}
917
bb40dcbb
AF		 918/* Set up the ethernet device structure, private data,
919 * and anything else we need before we start */
b31a1d8b
AF		 920static int gfar_probe(struct of_device *ofdev,
921 const struct of_device_id *match)
1da177e4
LT		 922{
923 u32 tempval;
924 struct net_device *dev = NULL;
925 struct gfar_private *priv = NULL;
f4983704 926 struct gfar __iomem *regs = NULL;
46ceb60c 927 int err = 0, i, grp_idx = 0;
c50a5d9a 928 int len_devname;
fba4ed03 929 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 930 u32 isrg = 0;
18294ad1 931 u32 __iomem *baddr;
1da177e4 932
fba4ed03 933 err = gfar_of_init(ofdev, &dev);
1da177e4 934
fba4ed03
SG		 935 if (err)
936 return err;
1da177e4
LT		 937
938 priv = netdev_priv(dev);
4826857f
KG		 939 priv->ndev = dev;
940 priv->ofdev = ofdev;
61c7a080 941 priv->node = ofdev->dev.of_node;
4826857f 942 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 943
d87eb127 944 spin_lock_init(&priv->bflock);
ab939905 945 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 946
b31a1d8b 947 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 948 regs = priv->gfargrp[0].regs;
1da177e4
LT		 949
950 /* Stop the DMA engine now, in case it was running before */
951 /* (The firmware could have used it, and left it running). */
257d938a 952 gfar_halt(dev);
1da177e4
LT		 953
954 /* Reset MAC layer */
f4983704 955 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 956
b98ac702
AF		 957 /* We need to delay at least 3 TX clocks */
958 udelay(2);
959
1da177e4 960 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 961 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 962
963 /* Initialize MACCFG2. */
f4983704 964 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
1da177e4
LT		 965
966 /* Initialize ECNTRL */
f4983704 967 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 968
1da177e4 969 /* Set the dev->base_addr to the gfar reg region */
f4983704 970 dev->base_addr = (unsigned long) regs;
1da177e4 971
b31a1d8b 972 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 973
974 /* Fill in the dev structure */
1da177e4 975 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 976 dev->mtu = 1500;
26ccfc37 977 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 978 dev->ethtool_ops = &gfar_ethtool_ops;
979
fba4ed03 980 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 981 for (i = 0; i < priv->num_grps; i++)
982 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 983
b31a1d8b 984 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 985 priv->rx_csum_enable = 1;
4669bc90 986 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 987 } else
988 priv->rx_csum_enable = 0;
989
990 priv->vlgrp = NULL;
1da177e4 991
26ccfc37 992 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 993 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 994
b31a1d8b 995 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 996 priv->extended_hash = 1;
997 priv->hash_width = 9;
998
f4983704
SG		 999 priv->hash_regs[0] = &regs->igaddr0;
1000 priv->hash_regs[1] = &regs->igaddr1;
1001 priv->hash_regs[2] = &regs->igaddr2;
1002 priv->hash_regs[3] = &regs->igaddr3;
1003 priv->hash_regs[4] = &regs->igaddr4;
1004 priv->hash_regs[5] = &regs->igaddr5;
1005 priv->hash_regs[6] = &regs->igaddr6;
1006 priv->hash_regs[7] = &regs->igaddr7;
1007 priv->hash_regs[8] = &regs->gaddr0;
1008 priv->hash_regs[9] = &regs->gaddr1;
1009 priv->hash_regs[10] = &regs->gaddr2;
1010 priv->hash_regs[11] = &regs->gaddr3;
1011 priv->hash_regs[12] = &regs->gaddr4;
1012 priv->hash_regs[13] = &regs->gaddr5;
1013 priv->hash_regs[14] = &regs->gaddr6;
1014 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1015
1016 } else {
1017 priv->extended_hash = 0;
1018 priv->hash_width = 8;
1019
f4983704
SG		 1020 priv->hash_regs[0] = &regs->gaddr0;
1021 priv->hash_regs[1] = &regs->gaddr1;
1022 priv->hash_regs[2] = &regs->gaddr2;
1023 priv->hash_regs[3] = &regs->gaddr3;
1024 priv->hash_regs[4] = &regs->gaddr4;
1025 priv->hash_regs[5] = &regs->gaddr5;
1026 priv->hash_regs[6] = &regs->gaddr6;
1027 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1028 }
1029
b31a1d8b 1030 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1031 priv->padding = DEFAULT_PADDING;
1032 else
1033 priv->padding = 0;
1034
cc772ab7
MR		 1035 if (dev->features & NETIF_F_IP_CSUM ||
1036 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1037 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1038
46ceb60c
SG		 1039 /* Program the isrg regs only if number of grps > 1 */
1040 if (priv->num_grps > 1) {
1041 baddr = &regs->isrg0;
1042 for (i = 0; i < priv->num_grps; i++) {
1043 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1044 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1045 gfar_write(baddr, isrg);
1046 baddr++;
1047 isrg = 0x0;
1048 }
1049 }
1050
fba4ed03 1051 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1052 * but, for_each_set_bit parses from right to left, which
fba4ed03 1053 * basically reverses the queue numbers */
46ceb60c
SG		 1054 for (i = 0; i< priv->num_grps; i++) {
1055 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1056 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1057 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1058 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1059 }
1060
1061 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1062 * also assign queues to groups */
1063 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1064 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1065 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1066 priv->num_rx_queues) {
1067 priv->gfargrp[grp_idx].num_rx_queues++;
1068 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1069 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1070 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1071 }
1072 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1073 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1074 priv->num_tx_queues) {
1075 priv->gfargrp[grp_idx].num_tx_queues++;
1076 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1077 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1078 tqueue = tqueue | (TQUEUE_EN0 >> i);
1079 }
1080 priv->gfargrp[grp_idx].rstat = rstat;
1081 priv->gfargrp[grp_idx].tstat = tstat;
1082 rstat = tstat =0;
fba4ed03 1083 }
fba4ed03
SG		 1084
1085 gfar_write(&regs->rqueue, rqueue);
1086 gfar_write(&regs->tqueue, tqueue);
1087
1da177e4 1088 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1089
a12f801d 1090 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1091 for (i = 0; i < priv->num_tx_queues; i++) {
1092 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1093 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1094 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1095 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1096 }
a12f801d 1097
fba4ed03
SG		 1098 for (i = 0; i < priv->num_rx_queues; i++) {
1099 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1100 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1101 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1102 }
1da177e4 1103
1ccb8389
SG		 1104 /* enable filer if using multiple RX queues*/
1105 if(priv->num_rx_queues > 1)
1106 priv->rx_filer_enable = 1;
0bbaf069
KG		 1107 /* Enable most messages by default */
1108 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1109
d3eab82b
TP		 1110 /* Carrier starts down, phylib will bring it up */
1111 netif_carrier_off(dev);
1112
1da177e4
LT		 1113 err = register_netdev(dev);
1114
1115 if (err) {
1116 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1117 dev->name);
1118 goto register_fail;
1119 }
1120
2884e5cc
AV		 1121 device_init_wakeup(&dev->dev,
1122 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1123
c50a5d9a
DH		 1124 /* fill out IRQ number and name fields */
1125 len_devname = strlen(dev->name);
46ceb60c
SG		 1126 for (i = 0; i < priv->num_grps; i++) {
1127 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1128 len_devname);
1129 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1130 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1131 "_g", sizeof("_g"));
1132 priv->gfargrp[i].int_name_tx[
1133 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1134 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1135 priv->gfargrp[i].int_name_tx)],
1136 "_tx", sizeof("_tx") + 1);
1137
1138 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1139 len_devname);
1140 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1141 "_g", sizeof("_g"));
1142 priv->gfargrp[i].int_name_rx[
1143 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1144 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1145 priv->gfargrp[i].int_name_rx)],
1146 "_rx", sizeof("_rx") + 1);
1147
1148 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1149 len_devname);
1150 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1151 "_g", sizeof("_g"));
1152 priv->gfargrp[i].int_name_er[strlen(
1153 priv->gfargrp[i].int_name_er)] = i+48;
1154 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1155 priv->gfargrp[i].int_name_er)],
1156 "_er", sizeof("_er") + 1);
1157 } else
1158 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1159 }
c50a5d9a 1160
7a8b3372
SG		 1161 /* Initialize the filer table */
1162 gfar_init_filer_table(priv);
1163
7f7f5316
AF		 1164 /* Create all the sysfs files */
1165 gfar_init_sysfs(dev);
1166
1da177e4 1167 /* Print out the device info */
e174961c 1168 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1169
1170 /* Even more device info helps when determining which kernel */
7f7f5316 1171 /* provided which set of benchmarks. */
1da177e4 1172 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1173 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1174 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1175 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1176 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1177 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1178 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1179
1180 return 0;
1181
1182register_fail:
46ceb60c 1183 unmap_group_regs(priv);
fba4ed03
SG		 1184 free_tx_pointers(priv);
1185 free_rx_pointers(priv);
fe192a49
GL		 1186 if (priv->phy_node)
1187 of_node_put(priv->phy_node);
1188 if (priv->tbi_node)
1189 of_node_put(priv->tbi_node);
1da177e4 1190 free_netdev(dev);
bb40dcbb 1191 return err;
1da177e4
LT		 1192}
1193
b31a1d8b 1194static int gfar_remove(struct of_device *ofdev)
1da177e4 1195{
b31a1d8b 1196 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1197
fe192a49
GL		 1198 if (priv->phy_node)
1199 of_node_put(priv->phy_node);
1200 if (priv->tbi_node)
1201 of_node_put(priv->tbi_node);
1202
b31a1d8b 1203 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1204
d9d8e041 1205 unregister_netdev(priv->ndev);
46ceb60c 1206 unmap_group_regs(priv);
4826857f 1207 free_netdev(priv->ndev);
1da177e4
LT		 1208
1209 return 0;
1210}
1211
d87eb127 1212#ifdef CONFIG_PM
be926fc4
AV		 1213
1214static int gfar_suspend(struct device *dev)
d87eb127 1215{
be926fc4
AV		 1216 struct gfar_private *priv = dev_get_drvdata(dev);
1217 struct net_device *ndev = priv->ndev;
46ceb60c 1218 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1219 unsigned long flags;
1220 u32 tempval;
1221
1222 int magic_packet = priv->wol_en &&
b31a1d8b 1223 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1224
be926fc4 1225 netif_device_detach(ndev);
d87eb127 1226
be926fc4 1227 if (netif_running(ndev)) {
fba4ed03
SG		 1228
1229 local_irq_save(flags);
1230 lock_tx_qs(priv);
1231 lock_rx_qs(priv);
d87eb127 1232
be926fc4 1233 gfar_halt_nodisable(ndev);
d87eb127
SW		 1234
1235 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1236 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1237
1238 tempval &= ~MACCFG1_TX_EN;
1239
1240 if (!magic_packet)
1241 tempval &= ~MACCFG1_RX_EN;
1242
f4983704 1243 gfar_write(&regs->maccfg1, tempval);
d87eb127 1244
fba4ed03
SG		 1245 unlock_rx_qs(priv);
1246 unlock_tx_qs(priv);
1247 local_irq_restore(flags);
d87eb127 1248
46ceb60c 1249 disable_napi(priv);
d87eb127
SW		 1250
1251 if (magic_packet) {
1252 /* Enable interrupt on Magic Packet */
f4983704 1253 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1254
1255 /* Enable Magic Packet mode */
f4983704 1256 tempval = gfar_read(&regs->maccfg2);
d87eb127 1257 tempval |= MACCFG2_MPEN;
f4983704 1258 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1259 } else {
1260 phy_stop(priv->phydev);
1261 }
1262 }
1263
1264 return 0;
1265}
1266
be926fc4 1267static int gfar_resume(struct device *dev)
d87eb127 1268{
be926fc4
AV		 1269 struct gfar_private *priv = dev_get_drvdata(dev);
1270 struct net_device *ndev = priv->ndev;
46ceb60c 1271 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1272 unsigned long flags;
1273 u32 tempval;
1274 int magic_packet = priv->wol_en &&
b31a1d8b 1275 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1276
be926fc4
AV		 1277 if (!netif_running(ndev)) {
1278 netif_device_attach(ndev);
d87eb127
SW		 1279 return 0;
1280 }
1281
1282 if (!magic_packet && priv->phydev)
1283 phy_start(priv->phydev);
1284
1285 /* Disable Magic Packet mode, in case something
1286 * else woke us up.
1287 */
fba4ed03
SG		 1288 local_irq_save(flags);
1289 lock_tx_qs(priv);
1290 lock_rx_qs(priv);
d87eb127 1291
f4983704 1292 tempval = gfar_read(&regs->maccfg2);
d87eb127 1293 tempval &= ~MACCFG2_MPEN;
f4983704 1294 gfar_write(&regs->maccfg2, tempval);
d87eb127 1295
be926fc4 1296 gfar_start(ndev);
d87eb127 1297
fba4ed03
SG		 1298 unlock_rx_qs(priv);
1299 unlock_tx_qs(priv);
1300 local_irq_restore(flags);
d87eb127 1301
be926fc4
AV		 1302 netif_device_attach(ndev);
1303
46ceb60c 1304 enable_napi(priv);
be926fc4
AV		 1305
1306 return 0;
1307}
1308
1309static int gfar_restore(struct device *dev)
1310{
1311 struct gfar_private *priv = dev_get_drvdata(dev);
1312 struct net_device *ndev = priv->ndev;
1313
1314 if (!netif_running(ndev))
1315 return 0;
1316
1317 gfar_init_bds(ndev);
1318 init_registers(ndev);
1319 gfar_set_mac_address(ndev);
1320 gfar_init_mac(ndev);
1321 gfar_start(ndev);
1322
1323 priv->oldlink = 0;
1324 priv->oldspeed = 0;
1325 priv->oldduplex = -1;
1326
1327 if (priv->phydev)
1328 phy_start(priv->phydev);
d87eb127 1329
be926fc4 1330 netif_device_attach(ndev);
5ea681d4 1331 enable_napi(priv);
d87eb127
SW		 1332
1333 return 0;
1334}
be926fc4
AV		 1335
1336static struct dev_pm_ops gfar_pm_ops = {
1337 .suspend = gfar_suspend,
1338 .resume = gfar_resume,
1339 .freeze = gfar_suspend,
1340 .thaw = gfar_resume,
1341 .restore = gfar_restore,
1342};
1343
1344#define GFAR_PM_OPS (&gfar_pm_ops)
1345
d87eb127 1346#else
be926fc4
AV		 1347
1348#define GFAR_PM_OPS NULL
be926fc4 1349
d87eb127 1350#endif
1da177e4 1351
e8a2b6a4
AF		 1352/* Reads the controller's registers to determine what interface
1353 * connects it to the PHY.
1354 */
1355static phy_interface_t gfar_get_interface(struct net_device *dev)
1356{
1357 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1358 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1359 u32 ecntrl;
1360
f4983704 1361 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1362
1363 if (ecntrl & ECNTRL_SGMII_MODE)
1364 return PHY_INTERFACE_MODE_SGMII;
1365
1366 if (ecntrl & ECNTRL_TBI_MODE) {
1367 if (ecntrl & ECNTRL_REDUCED_MODE)
1368 return PHY_INTERFACE_MODE_RTBI;
1369 else
1370 return PHY_INTERFACE_MODE_TBI;
1371 }
1372
1373 if (ecntrl & ECNTRL_REDUCED_MODE) {
1374 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1375 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1376 else {
b31a1d8b 1377 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1378
1379 /*
1380 * This isn't autodetected right now, so it must
1381 * be set by the device tree or platform code.
1382 */
1383 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1384 return PHY_INTERFACE_MODE_RGMII_ID;
1385
e8a2b6a4 1386 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1387 }
e8a2b6a4
AF		 1388 }
1389
b31a1d8b 1390 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1391 return PHY_INTERFACE_MODE_GMII;
1392
1393 return PHY_INTERFACE_MODE_MII;
1394}
1395
1396
bb40dcbb
AF		 1397/* Initializes driver's PHY state, and attaches to the PHY.
1398 * Returns 0 on success.
1da177e4
LT		 1399 */
1400static int init_phy(struct net_device *dev)
1401{
1402 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1403 uint gigabit_support =
b31a1d8b 1404 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1405 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1406 phy_interface_t interface;
1da177e4
LT		 1407
1408 priv->oldlink = 0;
1409 priv->oldspeed = 0;
1410 priv->oldduplex = -1;
1411
e8a2b6a4
AF		 1412 interface = gfar_get_interface(dev);
1413
1db780f8
AV		 1414 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1415 interface);
1416 if (!priv->phydev)
1417 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1418 interface);
1419 if (!priv->phydev) {
1420 dev_err(&dev->dev, "could not attach to PHY\n");
1421 return -ENODEV;
fe192a49 1422 }
1da177e4 1423
d3c12873
KJ		 1424 if (interface == PHY_INTERFACE_MODE_SGMII)
1425 gfar_configure_serdes(dev);
1426
bb40dcbb 1427 /* Remove any features not supported by the controller */
fe192a49
GL		 1428 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1429 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1430
1431 return 0;
1da177e4
LT		 1432}
1433
d0313587
PG		 1434/*
1435 * Initialize TBI PHY interface for communicating with the
1436 * SERDES lynx PHY on the chip. We communicate with this PHY
1437 * through the MDIO bus on each controller, treating it as a
1438 * "normal" PHY at the address found in the TBIPA register. We assume
1439 * that the TBIPA register is valid. Either the MDIO bus code will set
1440 * it to a value that doesn't conflict with other PHYs on the bus, or the
1441 * value doesn't matter, as there are no other PHYs on the bus.
1442 */
d3c12873
KJ		 1443static void gfar_configure_serdes(struct net_device *dev)
1444{
1445 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1446 struct phy_device *tbiphy;
1447
1448 if (!priv->tbi_node) {
1449 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1450 "device tree specify a tbi-handle\n");
1451 return;
1452 }
c132419e 1453
fe192a49
GL		 1454 tbiphy = of_phy_find_device(priv->tbi_node);
1455 if (!tbiphy) {
1456 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1457 return;
1458 }
d3c12873 1459
b31a1d8b
AF		 1460 /*
1461 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1462 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1463 * everything for us? Resetting it takes the link down and requires
1464 * several seconds for it to come back.
1465 */
fe192a49 1466 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1467 return;
d3c12873 1468
d0313587 1469 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1470 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1471
fe192a49 1472 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1473 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1474 ADVERTISE_1000XPSE_ASYM);
1475
fe192a49 1476 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1477 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1478}
1479
1da177e4
LT		 1480static void init_registers(struct net_device *dev)
1481{
1482 struct gfar_private *priv = netdev_priv(dev);
f4983704 1483 struct gfar __iomem *regs = NULL;
46ceb60c 1484 int i = 0;
1da177e4 1485
46ceb60c
SG		 1486 for (i = 0; i < priv->num_grps; i++) {
1487 regs = priv->gfargrp[i].regs;
1488 /* Clear IEVENT */
1489 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1490
46ceb60c
SG		 1491 /* Initialize IMASK */
1492 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1493 }
1da177e4 1494
46ceb60c 1495 regs = priv->gfargrp[0].regs;
1da177e4 1496 /* Init hash registers to zero */
f4983704
SG		 1497 gfar_write(&regs->igaddr0, 0);
1498 gfar_write(&regs->igaddr1, 0);
1499 gfar_write(&regs->igaddr2, 0);
1500 gfar_write(&regs->igaddr3, 0);
1501 gfar_write(&regs->igaddr4, 0);
1502 gfar_write(&regs->igaddr5, 0);
1503 gfar_write(&regs->igaddr6, 0);
1504 gfar_write(&regs->igaddr7, 0);
1505
1506 gfar_write(&regs->gaddr0, 0);
1507 gfar_write(&regs->gaddr1, 0);
1508 gfar_write(&regs->gaddr2, 0);
1509 gfar_write(&regs->gaddr3, 0);
1510 gfar_write(&regs->gaddr4, 0);
1511 gfar_write(&regs->gaddr5, 0);
1512 gfar_write(&regs->gaddr6, 0);
1513 gfar_write(&regs->gaddr7, 0);
1da177e4 1514
1da177e4 1515 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1516 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1517 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1518
1519 /* Mask off the CAM interrupts */
f4983704
SG		 1520 gfar_write(&regs->rmon.cam1, 0xffffffff);
1521 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1522 }
1523
1524 /* Initialize the max receive buffer length */
f4983704 1525 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1526
1da177e4 1527 /* Initialize the Minimum Frame Length Register */
f4983704 1528 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1529}
1530
0bbaf069
KG		 1531
1532/* Halt the receive and transmit queues */
d87eb127 1533static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1534{
1535 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1536 struct gfar __iomem *regs = NULL;
1da177e4 1537 u32 tempval;
46ceb60c 1538 int i = 0;
1da177e4 1539
46ceb60c
SG		 1540 for (i = 0; i < priv->num_grps; i++) {
1541 regs = priv->gfargrp[i].regs;
1542 /* Mask all interrupts */
1543 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1544
46ceb60c
SG		 1545 /* Clear all interrupts */
1546 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1547 }
1da177e4 1548
46ceb60c 1549 regs = priv->gfargrp[0].regs;
1da177e4 1550 /* Stop the DMA, and wait for it to stop */
f4983704 1551 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1552 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1553 != (DMACTRL_GRS | DMACTRL_GTS)) {
1554 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1555 gfar_write(&regs->dmactrl, tempval);
1da177e4 1556
761ed01b
AF		 1557 spin_event_timeout(((gfar_read(&regs->ievent) &
1558 (IEVENT_GRSC | IEVENT_GTSC)) ==
1559 (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1da177e4 1560 }
d87eb127 1561}
d87eb127
SW		 1562
1563/* Halt the receive and transmit queues */
1564void gfar_halt(struct net_device *dev)
1565{
1566 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1567 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1568 u32 tempval;
1da177e4 1569
2a54adc3
SW		 1570 gfar_halt_nodisable(dev);
1571
1da177e4
LT		 1572 /* Disable Rx and Tx */
1573 tempval = gfar_read(&regs->maccfg1);
1574 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1575 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1576}
1577
46ceb60c
SG		 1578static void free_grp_irqs(struct gfar_priv_grp *grp)
1579{
1580 free_irq(grp->interruptError, grp);
1581 free_irq(grp->interruptTransmit, grp);
1582 free_irq(grp->interruptReceive, grp);
1583}
1584
0bbaf069
KG		 1585void stop_gfar(struct net_device *dev)
1586{
1587 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1588 unsigned long flags;
46ceb60c 1589 int i;
0bbaf069 1590
bb40dcbb
AF		 1591 phy_stop(priv->phydev);
1592
a12f801d 1593
0bbaf069 1594 /* Lock it down */
fba4ed03
SG		 1595 local_irq_save(flags);
1596 lock_tx_qs(priv);
1597 lock_rx_qs(priv);
0bbaf069 1598
0bbaf069 1599 gfar_halt(dev);
1da177e4 1600
fba4ed03
SG		 1601 unlock_rx_qs(priv);
1602 unlock_tx_qs(priv);
1603 local_irq_restore(flags);
1da177e4
LT		 1604
1605 /* Free the IRQs */
b31a1d8b 1606 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1607 for (i = 0; i < priv->num_grps; i++)
1608 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1609 } else {
46ceb60c
SG		 1610 for (i = 0; i < priv->num_grps; i++)
1611 free_irq(priv->gfargrp[i].interruptTransmit,
1612 &priv->gfargrp[i]);
1da177e4
LT		 1613 }
1614
1615 free_skb_resources(priv);
1da177e4
LT		 1616}
1617
fba4ed03 1618static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1619{
1da177e4 1620 struct txbd8 *txbdp;
fba4ed03 1621 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1622 int i, j;
1da177e4 1623
a12f801d 1624 txbdp = tx_queue->tx_bd_base;
1da177e4 1625
a12f801d
SG		 1626 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1627 if (!tx_queue->tx_skbuff[i])
4669bc90 1628 continue;
1da177e4 1629
4826857f 1630 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1631 txbdp->length, DMA_TO_DEVICE);
1632 txbdp->lstatus = 0;
fba4ed03
SG		 1633 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1634 j++) {
4669bc90 1635 txbdp++;
4826857f 1636 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1637 txbdp->length, DMA_TO_DEVICE);
1da177e4 1638 }
ad5da7ab 1639 txbdp++;
a12f801d
SG		 1640 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1641 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1642 }
a12f801d 1643 kfree(tx_queue->tx_skbuff);
fba4ed03 1644}
1da177e4 1645
fba4ed03
SG		 1646static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1647{
1648 struct rxbd8 *rxbdp;
1649 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1650 int i;
1da177e4 1651
fba4ed03 1652 rxbdp = rx_queue->rx_bd_base;
1da177e4 1653
a12f801d
SG		 1654 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1655 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1656 dma_unmap_single(&priv->ofdev->dev,
1657 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1658 DMA_FROM_DEVICE);
a12f801d
SG		 1659 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1660 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1661 }
e69edd21
AV		 1662 rxbdp->lstatus = 0;
1663 rxbdp->bufPtr = 0;
1664 rxbdp++;
1da177e4 1665 }
a12f801d 1666 kfree(rx_queue->rx_skbuff);
fba4ed03 1667}
e69edd21 1668
fba4ed03
SG		 1669/* If there are any tx skbs or rx skbs still around, free them.
1670 * Then free tx_skbuff and rx_skbuff */
1671static void free_skb_resources(struct gfar_private *priv)
1672{
1673 struct gfar_priv_tx_q *tx_queue = NULL;
1674 struct gfar_priv_rx_q *rx_queue = NULL;
1675 int i;
1676
1677 /* Go through all the buffer descriptors and free their data buffers */
1678 for (i = 0; i < priv->num_tx_queues; i++) {
1679 tx_queue = priv->tx_queue[i];
7c0d10d3 1680 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1681 free_skb_tx_queue(tx_queue);
1682 }
1683
1684 for (i = 0; i < priv->num_rx_queues; i++) {
1685 rx_queue = priv->rx_queue[i];
7c0d10d3 1686 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1687 free_skb_rx_queue(rx_queue);
1688 }
1689
1690 dma_free_coherent(&priv->ofdev->dev,
1691 sizeof(struct txbd8) * priv->total_tx_ring_size +
1692 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1693 priv->tx_queue[0]->tx_bd_base,
1694 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1695 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1696}
1697
0bbaf069
KG		 1698void gfar_start(struct net_device *dev)
1699{
1700 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1701 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1702 u32 tempval;
46ceb60c 1703 int i = 0;
0bbaf069
KG		 1704
1705 /* Enable Rx and Tx in MACCFG1 */
1706 tempval = gfar_read(&regs->maccfg1);
1707 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1708 gfar_write(&regs->maccfg1, tempval);
1709
1710 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1711 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1712 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1713 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1714
0bbaf069 1715 /* Make sure we aren't stopped */
f4983704 1716 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1717 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1718 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1719
46ceb60c
SG		 1720 for (i = 0; i < priv->num_grps; i++) {
1721 regs = priv->gfargrp[i].regs;
1722 /* Clear THLT/RHLT, so that the DMA starts polling now */
1723 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1724 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1725 /* Unmask the interrupts we look for */
1726 gfar_write(&regs->imask, IMASK_DEFAULT);
1727 }
12dea57b 1728
1ae5dc34 1729 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1730}
1731
46ceb60c 1732void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1733 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1734{
46ceb60c 1735 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1736 u32 __iomem *baddr;
46ceb60c 1737 int i = 0;
1da177e4 1738
46ceb60c
SG		 1739 /* Backward compatible case ---- even if we enable
1740 * multiple queues, there's only single reg to program
1741 */
1742 gfar_write(&regs->txic, 0);
1743 if(likely(priv->tx_queue[0]->txcoalescing))
1744 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1745
46ceb60c
SG		 1746 gfar_write(&regs->rxic, 0);
1747 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1748 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1749
46ceb60c
SG		 1750 if (priv->mode == MQ_MG_MODE) {
1751 baddr = &regs->txic0;
984b3f57 1752 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1753 if (likely(priv->tx_queue[i]->txcoalescing)) {
1754 gfar_write(baddr + i, 0);
1755 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1756 }
1757 }
1758
1759 baddr = &regs->rxic0;
984b3f57 1760 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1761 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1762 gfar_write(baddr + i, 0);
1763 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1764 }
1765 }
1766 }
1767}
1768
1769static int register_grp_irqs(struct gfar_priv_grp *grp)
1770{
1771 struct gfar_private *priv = grp->priv;
1772 struct net_device *dev = priv->ndev;
1773 int err;
1da177e4 1774
1da177e4
LT		 1775 /* If the device has multiple interrupts, register for
1776 * them. Otherwise, only register for the one */
b31a1d8b 1777 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1778 /* Install our interrupt handlers for Error,
1da177e4 1779 * Transmit, and Receive */
46ceb60c
SG		 1780 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1781 grp->int_name_er,grp)) < 0) {
0bbaf069 1782 if (netif_msg_intr(priv))
46ceb60c
SG		 1783 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1784 dev->name, grp->interruptError);
1785
1786 goto err_irq_fail;
1da177e4
LT		 1787 }
1788
46ceb60c
SG		 1789 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1790 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1791 if (netif_msg_intr(priv))
46ceb60c
SG		 1792 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1793 dev->name, grp->interruptTransmit);
1da177e4
LT		 1794 goto tx_irq_fail;
1795 }
1796
46ceb60c
SG		 1797 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1798 grp->int_name_rx, grp)) < 0) {
0bbaf069 1799 if (netif_msg_intr(priv))
46ceb60c
SG		 1800 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1801 dev->name, grp->interruptReceive);
1da177e4
LT		 1802 goto rx_irq_fail;
1803 }
1804 } else {
46ceb60c
SG		 1805 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1806 grp->int_name_tx, grp)) < 0) {
0bbaf069 1807 if (netif_msg_intr(priv))
46ceb60c
SG		 1808 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1809 dev->name, grp->interruptTransmit);
1da177e4
LT		 1810 goto err_irq_fail;
1811 }
1812 }
1813
46ceb60c
SG		 1814 return 0;
1815
1816rx_irq_fail:
1817 free_irq(grp->interruptTransmit, grp);
1818tx_irq_fail:
1819 free_irq(grp->interruptError, grp);
1820err_irq_fail:
1821 return err;
1822
1823}
1824
1825/* Bring the controller up and running */
1826int startup_gfar(struct net_device *ndev)
1827{
1828 struct gfar_private *priv = netdev_priv(ndev);
1829 struct gfar __iomem *regs = NULL;
1830 int err, i, j;
1831
1832 for (i = 0; i < priv->num_grps; i++) {
1833 regs= priv->gfargrp[i].regs;
1834 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1835 }
1836
1837 regs= priv->gfargrp[0].regs;
1838 err = gfar_alloc_skb_resources(ndev);
1839 if (err)
1840 return err;
1841
1842 gfar_init_mac(ndev);
1843
1844 for (i = 0; i < priv->num_grps; i++) {
1845 err = register_grp_irqs(&priv->gfargrp[i]);
1846 if (err) {
1847 for (j = 0; j < i; j++)
1848 free_grp_irqs(&priv->gfargrp[j]);
1849 goto irq_fail;
1850 }
1851 }
1852
7f7f5316 1853 /* Start the controller */
ccc05c6e 1854 gfar_start(ndev);
1da177e4 1855
826aa4a0
AV		 1856 phy_start(priv->phydev);
1857
46ceb60c
SG		 1858 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1859
1da177e4
LT		 1860 return 0;
1861
46ceb60c 1862irq_fail:
e69edd21 1863 free_skb_resources(priv);
1da177e4
LT		 1864 return err;
1865}
1866
1867/* Called when something needs to use the ethernet device */
1868/* Returns 0 for success. */
1869static int gfar_enet_open(struct net_device *dev)
1870{
94e8cc35 1871 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1872 int err;
1873
46ceb60c 1874 enable_napi(priv);
bea3348e 1875
0fd56bb5
AF		 1876 skb_queue_head_init(&priv->rx_recycle);
1877
1da177e4
LT		 1878 /* Initialize a bunch of registers */
1879 init_registers(dev);
1880
1881 gfar_set_mac_address(dev);
1882
1883 err = init_phy(dev);
1884
a12f801d 1885 if (err) {
46ceb60c 1886 disable_napi(priv);
1da177e4 1887 return err;
bea3348e 1888 }
1da177e4
LT		 1889
1890 err = startup_gfar(dev);
db0e8e3f 1891 if (err) {
46ceb60c 1892 disable_napi(priv);
db0e8e3f
AV		 1893 return err;
1894 }
1da177e4 1895
fba4ed03 1896 netif_tx_start_all_queues(dev);
1da177e4 1897
2884e5cc
AV		 1898 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1899
1da177e4
LT		 1900 return err;
1901}
1902
54dc79fe 1903static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1904{
54dc79fe 1905 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1906
1907 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1908
0bbaf069
KG		 1909 return fcb;
1910}
1911
1912static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1913{
7f7f5316 1914 u8 flags = 0;
0bbaf069
KG		 1915
1916 /* If we're here, it's a IP packet with a TCP or UDP
1917 * payload. We set it to checksum, using a pseudo-header
1918 * we provide
1919 */
7f7f5316 1920 flags = TXFCB_DEFAULT;
0bbaf069 1921
7f7f5316
AF		 1922 /* Tell the controller what the protocol is */
1923 /* And provide the already calculated phcs */
eddc9ec5 1924 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1925 flags |= TXFCB_UDP;
4bedb452 1926 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1927 } else
8da32de5 1928 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1929
1930 /* l3os is the distance between the start of the
1931 * frame (skb->data) and the start of the IP hdr.
1932 * l4os is the distance between the start of the
1933 * l3 hdr and the l4 hdr */
bbe735e4 1934 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1935 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1936
7f7f5316 1937 fcb->flags = flags;
0bbaf069
KG		 1938}
1939
7f7f5316 1940void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1941{
7f7f5316 1942 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1943 fcb->vlctl = vlan_tx_tag_get(skb);
1944}
1945
4669bc90
DH		 1946static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1947 struct txbd8 *base, int ring_size)
1948{
1949 struct txbd8 *new_bd = bdp + stride;
1950
1951 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1952}
1953
1954static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1955 int ring_size)
1956{
1957 return skip_txbd(bdp, 1, base, ring_size);
1958}
1959
1da177e4
LT		 1960/* This is called by the kernel when a frame is ready for transmission. */
1961/* It is pointed to by the dev->hard_start_xmit function pointer */
1962static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1963{
1964 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1965 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 1966 struct netdev_queue *txq;
f4983704 1967 struct gfar __iomem *regs = NULL;
0bbaf069 1968 struct txfcb *fcb = NULL;
f0ee7acf 1969 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 1970 u32 lstatus;
f0ee7acf 1971 int i, rq = 0, do_tstamp = 0;
4669bc90 1972 u32 bufaddr;
fef6108d 1973 unsigned long flags;
f0ee7acf
MR		 1974 unsigned int nr_frags, nr_txbds, length;
1975 union skb_shared_tx *shtx;
fba4ed03
SG		 1976
1977 rq = skb->queue_mapping;
1978 tx_queue = priv->tx_queue[rq];
1979 txq = netdev_get_tx_queue(dev, rq);
a12f801d 1980 base = tx_queue->tx_bd_base;
46ceb60c 1981 regs = tx_queue->grp->regs;
f0ee7acf
MR		 1982 shtx = skb_tx(skb);
1983
1984 /* check if time stamp should be generated */
1985 if (unlikely(shtx->hardware && priv->hwts_tx_en))
1986 do_tstamp = 1;
4669bc90 1987
5b28beaf
LY		 1988 /* make space for additional header when fcb is needed */
1989 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
f0ee7acf
MR		 1990 (priv->vlgrp && vlan_tx_tag_present(skb)) ||
1991 unlikely(do_tstamp)) &&
5b28beaf 1992 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 1993 struct sk_buff *skb_new;
1994
1995 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1996 if (!skb_new) {
1997 dev->stats.tx_errors++;
bd14ba84 1998 kfree_skb(skb);
54dc79fe
SH		 1999 return NETDEV_TX_OK;
2000 }
2001 kfree_skb(skb);
2002 skb = skb_new;
2003 }
2004
4669bc90
DH		 2005 /* total number of fragments in the SKB */
2006 nr_frags = skb_shinfo(skb)->nr_frags;
2007
f0ee7acf
MR		 2008 /* calculate the required number of TxBDs for this skb */
2009 if (unlikely(do_tstamp))
2010 nr_txbds = nr_frags + 2;
2011 else
2012 nr_txbds = nr_frags + 1;
2013
4669bc90 2014 /* check if there is space to queue this packet */
f0ee7acf 2015 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2016 /* no space, stop the queue */
fba4ed03 2017 netif_tx_stop_queue(txq);
4669bc90 2018 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2019 return NETDEV_TX_BUSY;
2020 }
1da177e4
LT		 2021
2022 /* Update transmit stats */
a7f38041
SG		 2023 txq->tx_bytes += skb->len;
2024 txq->tx_packets ++;
1da177e4 2025
a12f801d 2026 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2027 lstatus = txbdp->lstatus;
2028
2029 /* Time stamp insertion requires one additional TxBD */
2030 if (unlikely(do_tstamp))
2031 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2032 tx_queue->tx_ring_size);
1da177e4 2033
4669bc90 2034 if (nr_frags == 0) {
f0ee7acf
MR		 2035 if (unlikely(do_tstamp))
2036 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2037 TXBD_INTERRUPT);
2038 else
2039 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2040 } else {
2041 /* Place the fragment addresses and lengths into the TxBDs */
2042 for (i = 0; i < nr_frags; i++) {
2043 /* Point at the next BD, wrapping as needed */
a12f801d 2044 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2045
2046 length = skb_shinfo(skb)->frags[i].size;
2047
2048 lstatus = txbdp->lstatus | length |
2049 BD_LFLAG(TXBD_READY);
2050
2051 /* Handle the last BD specially */
2052 if (i == nr_frags - 1)
2053 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2054
4826857f 2055 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2056 skb_shinfo(skb)->frags[i].page,
2057 skb_shinfo(skb)->frags[i].page_offset,
2058 length,
2059 DMA_TO_DEVICE);
2060
2061 /* set the TxBD length and buffer pointer */
2062 txbdp->bufPtr = bufaddr;
2063 txbdp->lstatus = lstatus;
2064 }
2065
2066 lstatus = txbdp_start->lstatus;
2067 }
1da177e4 2068
0bbaf069 2069 /* Set up checksumming */
12dea57b 2070 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2071 fcb = gfar_add_fcb(skb);
2072 lstatus |= BD_LFLAG(TXBD_TOE);
2073 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2074 }
2075
77ecaf2d 2076 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2077 if (unlikely(NULL == fcb)) {
2078 fcb = gfar_add_fcb(skb);
5a5efed4 2079 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2080 }
54dc79fe
SH		 2081
2082 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2083 }
2084
f0ee7acf
MR		 2085 /* Setup tx hardware time stamping if requested */
2086 if (unlikely(do_tstamp)) {
2087 shtx->in_progress = 1;
2088 if (fcb == NULL)
2089 fcb = gfar_add_fcb(skb);
2090 fcb->ptp = 1;
2091 lstatus |= BD_LFLAG(TXBD_TOE);
2092 }
2093
4826857f 2094 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2095 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2096
f0ee7acf
MR		 2097 /*
2098 * If time stamping is requested one additional TxBD must be set up. The
2099 * first TxBD points to the FCB and must have a data length of
2100 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2101 * the full frame length.
2102 */
2103 if (unlikely(do_tstamp)) {
2104 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2105 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2106 (skb_headlen(skb) - GMAC_FCB_LEN);
2107 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2108 } else {
2109 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2110 }
1da177e4 2111
a3bc1f11
AV		 2112 /*
2113 * We can work in parallel with gfar_clean_tx_ring(), except
2114 * when modifying num_txbdfree. Note that we didn't grab the lock
2115 * when we were reading the num_txbdfree and checking for available
2116 * space, that's because outside of this function it can only grow,
2117 * and once we've got needed space, it cannot suddenly disappear.
2118 *
2119 * The lock also protects us from gfar_error(), which can modify
2120 * regs->tstat and thus retrigger the transfers, which is why we
2121 * also must grab the lock before setting ready bit for the first
2122 * to be transmitted BD.
2123 */
2124 spin_lock_irqsave(&tx_queue->txlock, flags);
2125
4669bc90
DH		 2126 /*
2127 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2128 * semantics (it requires synchronization between cacheable and
2129 * uncacheable mappings, which eieio doesn't provide and which we
2130 * don't need), thus requiring a more expensive sync instruction. At
2131 * some point, the set of architecture-independent barrier functions
2132 * should be expanded to include weaker barriers.
2133 */
3b6330ce 2134 eieio();
7f7f5316 2135
4669bc90
DH		 2136 txbdp_start->lstatus = lstatus;
2137
0eddba52
AV		 2138 eieio(); /* force lstatus write before tx_skbuff */
2139
2140 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2141
4669bc90
DH		 2142 /* Update the current skb pointer to the next entry we will use
2143 * (wrapping if necessary) */
a12f801d
SG		 2144 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2145 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2146
a12f801d 2147 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2148
2149 /* reduce TxBD free count */
f0ee7acf 2150 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2151
2152 /* If the next BD still needs to be cleaned up, then the bds
2153 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2154 if (!tx_queue->num_txbdfree) {
fba4ed03 2155 netif_tx_stop_queue(txq);
1da177e4 2156
09f75cd7 2157 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2158 }
2159
1da177e4 2160 /* Tell the DMA to go go go */
fba4ed03 2161 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2162
2163 /* Unlock priv */
a12f801d 2164 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2165
54dc79fe 2166 return NETDEV_TX_OK;
1da177e4
LT		 2167}
2168
2169/* Stops the kernel queue, and halts the controller */
2170static int gfar_close(struct net_device *dev)
2171{
2172 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2173
46ceb60c 2174 disable_napi(priv);
bea3348e 2175
ab939905 2176 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2177 stop_gfar(dev);
2178
bb40dcbb
AF		 2179 /* Disconnect from the PHY */
2180 phy_disconnect(priv->phydev);
2181 priv->phydev = NULL;
1da177e4 2182
fba4ed03 2183 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2184
2185 return 0;
2186}
2187
1da177e4 2188/* Changes the mac address if the controller is not running. */
f162b9d5 2189static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2190{
7f7f5316 2191 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2192
2193 return 0;
2194}
2195
2196
0bbaf069
KG		 2197/* Enables and disables VLAN insertion/extraction */
2198static void gfar_vlan_rx_register(struct net_device *dev,
2199 struct vlan_group *grp)
2200{
2201 struct gfar_private *priv = netdev_priv(dev);
f4983704 2202 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2203 unsigned long flags;
2204 u32 tempval;
2205
46ceb60c 2206 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2207 local_irq_save(flags);
2208 lock_rx_qs(priv);
0bbaf069 2209
cd1f55a5 2210 priv->vlgrp = grp;
0bbaf069
KG		 2211
2212 if (grp) {
2213 /* Enable VLAN tag insertion */
f4983704 2214 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2215 tempval |= TCTRL_VLINS;
2216
f4983704 2217 gfar_write(&regs->tctrl, tempval);
6aa20a22 2218
0bbaf069 2219 /* Enable VLAN tag extraction */
f4983704 2220 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2221 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2222 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2223 } else {
2224 /* Disable VLAN tag insertion */
f4983704 2225 tempval = gfar_read(&regs->tctrl);
0bbaf069 2226 tempval &= ~TCTRL_VLINS;
f4983704 2227 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2228
2229 /* Disable VLAN tag extraction */
f4983704 2230 tempval = gfar_read(&regs->rctrl);
0bbaf069 2231 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2232 /* If parse is no longer required, then disable parser */
2233 if (tempval & RCTRL_REQ_PARSER)
2234 tempval |= RCTRL_PRSDEP_INIT;
2235 else
2236 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2237 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2238 }
2239
77ecaf2d
DH		 2240 gfar_change_mtu(dev, dev->mtu);
2241
fba4ed03
SG		 2242 unlock_rx_qs(priv);
2243 local_irq_restore(flags);
0bbaf069
KG		 2244}
2245
1da177e4
LT		 2246static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2247{
2248 int tempsize, tempval;
2249 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2250 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2251 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2252 int frame_size = new_mtu + ETH_HLEN;
2253
77ecaf2d 2254 if (priv->vlgrp)
faa89577 2255 frame_size += VLAN_HLEN;
0bbaf069 2256
1da177e4 2257 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2258 if (netif_msg_drv(priv))
2259 printk(KERN_ERR "%s: Invalid MTU setting\n",
2260 dev->name);
1da177e4
LT		 2261 return -EINVAL;
2262 }
2263
77ecaf2d
DH		 2264 if (gfar_uses_fcb(priv))
2265 frame_size += GMAC_FCB_LEN;
2266
2267 frame_size += priv->padding;
2268
1da177e4
LT		 2269 tempsize =
2270 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2271 INCREMENTAL_BUFFER_SIZE;
2272
2273 /* Only stop and start the controller if it isn't already
7f7f5316 2274 * stopped, and we changed something */
1da177e4
LT		 2275 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2276 stop_gfar(dev);
2277
2278 priv->rx_buffer_size = tempsize;
2279
2280 dev->mtu = new_mtu;
2281
f4983704
SG		 2282 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2283 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2284
2285 /* If the mtu is larger than the max size for standard
2286 * ethernet frames (ie, a jumbo frame), then set maccfg2
2287 * to allow huge frames, and to check the length */
f4983704 2288 tempval = gfar_read(&regs->maccfg2);
1da177e4
LT		 2289
2290 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2291 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2292 else
2293 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2294
f4983704 2295 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2296
2297 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2298 startup_gfar(dev);
2299
2300 return 0;
2301}
2302
ab939905 2303/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2304 * transmitted after a set amount of time.
2305 * For now, assume that clearing out all the structures, and
ab939905
SS		 2306 * starting over will fix the problem.
2307 */
2308static void gfar_reset_task(struct work_struct *work)
1da177e4 2309{
ab939905
SS		 2310 struct gfar_private *priv = container_of(work, struct gfar_private,
2311 reset_task);
4826857f 2312 struct net_device *dev = priv->ndev;
1da177e4
LT		 2313
2314 if (dev->flags & IFF_UP) {
fba4ed03 2315 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2316 stop_gfar(dev);
2317 startup_gfar(dev);
fba4ed03 2318 netif_tx_start_all_queues(dev);
1da177e4
LT		 2319 }
2320
263ba320 2321 netif_tx_schedule_all(dev);
1da177e4
LT		 2322}
2323
ab939905
SS		 2324static void gfar_timeout(struct net_device *dev)
2325{
2326 struct gfar_private *priv = netdev_priv(dev);
2327
2328 dev->stats.tx_errors++;
2329 schedule_work(&priv->reset_task);
2330}
2331
1da177e4 2332/* Interrupt Handler for Transmit complete */
a12f801d 2333static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2334{
a12f801d 2335 struct net_device *dev = tx_queue->dev;
d080cd63 2336 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2337 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2338 struct txbd8 *bdp, *next = NULL;
4669bc90 2339 struct txbd8 *lbdp = NULL;
a12f801d 2340 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2341 struct sk_buff *skb;
2342 int skb_dirtytx;
a12f801d 2343 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2344 int frags = 0, nr_txbds = 0;
4669bc90 2345 int i;
d080cd63 2346 int howmany = 0;
4669bc90 2347 u32 lstatus;
f0ee7acf
MR		 2348 size_t buflen;
2349 union skb_shared_tx *shtx;
1da177e4 2350
fba4ed03 2351 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2352 bdp = tx_queue->dirty_tx;
2353 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2354
a12f801d 2355 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2356 unsigned long flags;
2357
4669bc90 2358 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2359
2360 /*
2361 * When time stamping, one additional TxBD must be freed.
2362 * Also, we need to dma_unmap_single() the TxPAL.
2363 */
2364 shtx = skb_tx(skb);
2365 if (unlikely(shtx->in_progress))
2366 nr_txbds = frags + 2;
2367 else
2368 nr_txbds = frags + 1;
2369
2370 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2371
4669bc90 2372 lstatus = lbdp->lstatus;
1da177e4 2373
4669bc90
DH		 2374 /* Only clean completed frames */
2375 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2376 (lstatus & BD_LENGTH_MASK))
2377 break;
2378
f0ee7acf
MR		 2379 if (unlikely(shtx->in_progress)) {
2380 next = next_txbd(bdp, base, tx_ring_size);
2381 buflen = next->length + GMAC_FCB_LEN;
2382 } else
2383 buflen = bdp->length;
2384
2385 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2386 buflen, DMA_TO_DEVICE);
2387
2388 if (unlikely(shtx->in_progress)) {
2389 struct skb_shared_hwtstamps shhwtstamps;
2390 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2391 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2392 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2393 skb_tstamp_tx(skb, &shhwtstamps);
2394 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2395 bdp = next;
2396 }
81183059 2397
4669bc90
DH		 2398 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2399 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2400
4669bc90 2401 for (i = 0; i < frags; i++) {
4826857f 2402 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2403 bdp->bufPtr,
2404 bdp->length,
2405 DMA_TO_DEVICE);
2406 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2407 bdp = next_txbd(bdp, base, tx_ring_size);
2408 }
1da177e4 2409
0fd56bb5
AF		 2410 /*
2411 * If there's room in the queue (limit it to rx_buffer_size)
2412 * we add this skb back into the pool, if it's the right size
2413 */
a12f801d 2414 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 2415 skb_recycle_check(skb, priv->rx_buffer_size +
2416 RXBUF_ALIGNMENT))
2417 __skb_queue_head(&priv->rx_recycle, skb);
2418 else
2419 dev_kfree_skb_any(skb);
2420
a12f801d 2421 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2422
4669bc90
DH		 2423 skb_dirtytx = (skb_dirtytx + 1) &
2424 TX_RING_MOD_MASK(tx_ring_size);
2425
2426 howmany++;
a3bc1f11 2427 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2428 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2429 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2430 }
1da177e4 2431
4669bc90 2432 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2433 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2434 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2435
4669bc90 2436 /* Update dirty indicators */
a12f801d
SG		 2437 tx_queue->skb_dirtytx = skb_dirtytx;
2438 tx_queue->dirty_tx = bdp;
1da177e4 2439
d080cd63
DH		 2440 return howmany;
2441}
2442
f4983704 2443static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2444{
a6d0b91a
AV		 2445 unsigned long flags;
2446
fba4ed03
SG		 2447 spin_lock_irqsave(&gfargrp->grplock, flags);
2448 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2449 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2450 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2451 } else {
2452 /*
2453 * Clear IEVENT, so interrupts aren't called again
2454 * because of the packets that have already arrived.
2455 */
f4983704 2456 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2457 }
fba4ed03 2458 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2459
8c7396ae 2460}
1da177e4 2461
8c7396ae 2462/* Interrupt Handler for Transmit complete */
f4983704 2463static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2464{
f4983704 2465 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2466 return IRQ_HANDLED;
2467}
2468
a12f801d 2469static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2470 struct sk_buff *skb)
2471{
a12f801d 2472 struct net_device *dev = rx_queue->dev;
815b97c6 2473 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2474 dma_addr_t buf;
815b97c6 2475
8a102fe0
AV		 2476 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2477 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2478 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2479}
2480
2481
2482struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 2483{
7f7f5316 2484 unsigned int alignamount;
1da177e4
LT		 2485 struct gfar_private *priv = netdev_priv(dev);
2486 struct sk_buff *skb = NULL;
1da177e4 2487
0fd56bb5
AF		 2488 skb = __skb_dequeue(&priv->rx_recycle);
2489 if (!skb)
2490 skb = netdev_alloc_skb(dev,
2491 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 2492
815b97c6 2493 if (!skb)
1da177e4
LT		 2494 return NULL;
2495
7f7f5316 2496 alignamount = RXBUF_ALIGNMENT -
bea3348e 2497 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 2498
1da177e4
LT		 2499 /* We need the data buffer to be aligned properly. We will reserve
2500 * as many bytes as needed to align the data properly
2501 */
7f7f5316 2502 skb_reserve(skb, alignamount);
a6d36d56 2503 GFAR_CB(skb)->alignamount = alignamount;
1da177e4 2504
1da177e4
LT		 2505 return skb;
2506}
2507
298e1a9e 2508static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2509{
298e1a9e 2510 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2511 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2512 struct gfar_extra_stats *estats = &priv->extra_stats;
2513
2514 /* If the packet was truncated, none of the other errors
2515 * matter */
2516 if (status & RXBD_TRUNCATED) {
2517 stats->rx_length_errors++;
2518
2519 estats->rx_trunc++;
2520
2521 return;
2522 }
2523 /* Count the errors, if there were any */
2524 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2525 stats->rx_length_errors++;
2526
2527 if (status & RXBD_LARGE)
2528 estats->rx_large++;
2529 else
2530 estats->rx_short++;
2531 }
2532 if (status & RXBD_NONOCTET) {
2533 stats->rx_frame_errors++;
2534 estats->rx_nonoctet++;
2535 }
2536 if (status & RXBD_CRCERR) {
2537 estats->rx_crcerr++;
2538 stats->rx_crc_errors++;
2539 }
2540 if (status & RXBD_OVERRUN) {
2541 estats->rx_overrun++;
2542 stats->rx_crc_errors++;
2543 }
2544}
2545
f4983704 2546irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2547{
f4983704 2548 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2549 return IRQ_HANDLED;
2550}
2551
0bbaf069
KG		 2552static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2553{
2554 /* If valid headers were found, and valid sums
2555 * were verified, then we tell the kernel that no
2556 * checksumming is necessary. Otherwise, it is */
7f7f5316 2557 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2558 skb->ip_summed = CHECKSUM_UNNECESSARY;
2559 else
2560 skb->ip_summed = CHECKSUM_NONE;
2561}
2562
2563
1da177e4
LT		 2564/* gfar_process_frame() -- handle one incoming packet if skb
2565 * isn't NULL. */
2566static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2567 int amount_pull)
1da177e4
LT		 2568{
2569 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2570 struct rxfcb *fcb = NULL;
1da177e4 2571
2c2db48a 2572 int ret;
1da177e4 2573
2c2db48a
DH		 2574 /* fcb is at the beginning if exists */
2575 fcb = (struct rxfcb *)skb->data;
0bbaf069 2576
2c2db48a
DH		 2577 /* Remove the FCB from the skb */
2578 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2579 if (amount_pull) {
2580 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2581 skb_pull(skb, amount_pull);
f74dac08 2582 }
0bbaf069 2583
cc772ab7
MR		 2584 /* Get receive timestamp from the skb */
2585 if (priv->hwts_rx_en) {
2586 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2587 u64 *ns = (u64 *) skb->data;
2588 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2589 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2590 }
2591
2592 if (priv->padding)
2593 skb_pull(skb, priv->padding);
2594
2c2db48a
DH		 2595 if (priv->rx_csum_enable)
2596 gfar_rx_checksum(skb, fcb);
0bbaf069 2597
2c2db48a
DH		 2598 /* Tell the skb what kind of packet this is */
2599 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2600
2c2db48a
DH		 2601 /* Send the packet up the stack */
2602 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2603 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2604 else
2605 ret = netif_receive_skb(skb);
0bbaf069 2606
2c2db48a
DH		 2607 if (NET_RX_DROP == ret)
2608 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2609
2610 return 0;
2611}
2612
2613/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2614 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2615 * of frames handled
2616 */
a12f801d 2617int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2618{
a12f801d 2619 struct net_device *dev = rx_queue->dev;
31de198b 2620 struct rxbd8 *bdp, *base;
1da177e4 2621 struct sk_buff *skb;
2c2db48a
DH		 2622 int pkt_len;
2623 int amount_pull;
1da177e4
LT		 2624 int howmany = 0;
2625 struct gfar_private *priv = netdev_priv(dev);
2626
2627 /* Get the first full descriptor */
a12f801d
SG		 2628 bdp = rx_queue->cur_rx;
2629 base = rx_queue->rx_bd_base;
1da177e4 2630
cc772ab7 2631 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2632
1da177e4 2633 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2634 struct sk_buff *newskb;
3b6330ce 2635 rmb();
815b97c6
AF		 2636
2637 /* Add another skb for the future */
2638 newskb = gfar_new_skb(dev);
2639
a12f801d 2640 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2641
4826857f 2642 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2643 priv->rx_buffer_size, DMA_FROM_DEVICE);
2644
815b97c6
AF		 2645 /* We drop the frame if we failed to allocate a new buffer */
2646 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2647 bdp->status & RXBD_ERR)) {
2648 count_errors(bdp->status, dev);
2649
2650 if (unlikely(!newskb))
2651 newskb = skb;
4e2fd555
LB		 2652 else if (skb) {
2653 /*
a6d36d56 2654 * We need to un-reserve() the skb to what it
4e2fd555
LB		 2655 * was before gfar_new_skb() re-aligned
2656 * it to an RXBUF_ALIGNMENT boundary
2657 * before we put the skb back on the
2658 * recycle list.
2659 */
a6d36d56 2660 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
0fd56bb5 2661 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2662 }
815b97c6 2663 } else {
1da177e4 2664 /* Increment the number of packets */
a7f38041 2665 rx_queue->stats.rx_packets++;
1da177e4
LT		 2666 howmany++;
2667
2c2db48a
DH		 2668 if (likely(skb)) {
2669 pkt_len = bdp->length - ETH_FCS_LEN;
2670 /* Remove the FCS from the packet length */
2671 skb_put(skb, pkt_len);
a7f38041 2672 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2673 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2674 gfar_process_frame(dev, skb, amount_pull);
2675
2676 } else {
2677 if (netif_msg_rx_err(priv))
2678 printk(KERN_WARNING
2679 "%s: Missing skb!\n", dev->name);
a7f38041 2680 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2681 priv->extra_stats.rx_skbmissing++;
2682 }
1da177e4 2683
1da177e4
LT		 2684 }
2685
a12f801d 2686 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2687
815b97c6 2688 /* Setup the new bdp */
a12f801d 2689 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2690
2691 /* Update to the next pointer */
a12f801d 2692 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2693
2694 /* update to point at the next skb */
a12f801d
SG		 2695 rx_queue->skb_currx =
2696 (rx_queue->skb_currx + 1) &
2697 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2698 }
2699
2700 /* Update the current rxbd pointer to be the next one */
a12f801d 2701 rx_queue->cur_rx = bdp;
1da177e4 2702
1da177e4
LT		 2703 return howmany;
2704}
2705
bea3348e 2706static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2707{
fba4ed03
SG		 2708 struct gfar_priv_grp *gfargrp = container_of(napi,
2709 struct gfar_priv_grp, napi);
2710 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2711 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2712 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2713 struct gfar_priv_rx_q *rx_queue = NULL;
2714 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2715 int tx_cleaned = 0, i, left_over_budget = budget;
2716 unsigned long serviced_queues = 0;
fba4ed03 2717 int num_queues = 0;
d080cd63 2718
fba4ed03
SG		 2719 num_queues = gfargrp->num_rx_queues;
2720 budget_per_queue = budget/num_queues;
2721
8c7396ae
DH		 2722 /* Clear IEVENT, so interrupts aren't called again
2723 * because of the packets that have already arrived */
f4983704 2724 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2725
fba4ed03 2726 while (num_queues && left_over_budget) {
1da177e4 2727
fba4ed03
SG		 2728 budget_per_queue = left_over_budget/num_queues;
2729 left_over_budget = 0;
2730
984b3f57 2731 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2732 if (test_bit(i, &serviced_queues))
2733 continue;
2734 rx_queue = priv->rx_queue[i];
2735 tx_queue = priv->tx_queue[rx_queue->qindex];
2736
a3bc1f11 2737 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2738 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2739 budget_per_queue);
2740 rx_cleaned += rx_cleaned_per_queue;
2741 if(rx_cleaned_per_queue < budget_per_queue) {
2742 left_over_budget = left_over_budget +
2743 (budget_per_queue - rx_cleaned_per_queue);
2744 set_bit(i, &serviced_queues);
2745 num_queues--;
2746 }
2747 }
2748 }
1da177e4 2749
42199884
AF		 2750 if (tx_cleaned)
2751 return budget;
2752
2753 if (rx_cleaned < budget) {
288379f0 2754 napi_complete(napi);
1da177e4
LT		 2755
2756 /* Clear the halt bit in RSTAT */
fba4ed03 2757 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2758
f4983704 2759 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2760
2761 /* If we are coalescing interrupts, update the timer */
2762 /* Otherwise, clear it */
46ceb60c
SG		 2763 gfar_configure_coalescing(priv,
2764 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2765 }
2766
42199884 2767 return rx_cleaned;
1da177e4 2768}
1da177e4 2769
f2d71c2d
VW		 2770#ifdef CONFIG_NET_POLL_CONTROLLER
2771/*
2772 * Polling 'interrupt' - used by things like netconsole to send skbs
2773 * without having to re-enable interrupts. It's not called while
2774 * the interrupt routine is executing.
2775 */
2776static void gfar_netpoll(struct net_device *dev)
2777{
2778 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2779 int i = 0;
f2d71c2d
VW		 2780
2781 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2782 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2783 for (i = 0; i < priv->num_grps; i++) {
2784 disable_irq(priv->gfargrp[i].interruptTransmit);
2785 disable_irq(priv->gfargrp[i].interruptReceive);
2786 disable_irq(priv->gfargrp[i].interruptError);
2787 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2788 &priv->gfargrp[i]);
2789 enable_irq(priv->gfargrp[i].interruptError);
2790 enable_irq(priv->gfargrp[i].interruptReceive);
2791 enable_irq(priv->gfargrp[i].interruptTransmit);
2792 }
f2d71c2d 2793 } else {
46ceb60c
SG		 2794 for (i = 0; i < priv->num_grps; i++) {
2795 disable_irq(priv->gfargrp[i].interruptTransmit);
2796 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2797 &priv->gfargrp[i]);
2798 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2799 }
f2d71c2d
VW		 2800 }
2801}
2802#endif
2803
1da177e4 2804/* The interrupt handler for devices with one interrupt */
f4983704 2805static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2806{
f4983704 2807 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2808
2809 /* Save ievent for future reference */
f4983704 2810 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2811
1da177e4 2812 /* Check for reception */
538cc7ee 2813 if (events & IEVENT_RX_MASK)
f4983704 2814 gfar_receive(irq, grp_id);
1da177e4
LT		 2815
2816 /* Check for transmit completion */
538cc7ee 2817 if (events & IEVENT_TX_MASK)
f4983704 2818 gfar_transmit(irq, grp_id);
1da177e4 2819
538cc7ee
SS		 2820 /* Check for errors */
2821 if (events & IEVENT_ERR_MASK)
f4983704 2822 gfar_error(irq, grp_id);
1da177e4
LT		 2823
2824 return IRQ_HANDLED;
2825}
2826
1da177e4
LT		 2827/* Called every time the controller might need to be made
2828 * aware of new link state. The PHY code conveys this
bb40dcbb 2829 * information through variables in the phydev structure, and this
1da177e4
LT		 2830 * function converts those variables into the appropriate
2831 * register values, and can bring down the device if needed.
2832 */
2833static void adjust_link(struct net_device *dev)
2834{
2835 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2836 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2837 unsigned long flags;
2838 struct phy_device *phydev = priv->phydev;
2839 int new_state = 0;
2840
fba4ed03
SG		 2841 local_irq_save(flags);
2842 lock_tx_qs(priv);
2843
bb40dcbb
AF		 2844 if (phydev->link) {
2845 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2846 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2847
1da177e4
LT		 2848 /* Now we make sure that we can be in full duplex mode.
2849 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2850 if (phydev->duplex != priv->oldduplex) {
2851 new_state = 1;
2852 if (!(phydev->duplex))
1da177e4 2853 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2854 else
1da177e4 2855 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2856
bb40dcbb 2857 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2858 }
2859
bb40dcbb
AF		 2860 if (phydev->speed != priv->oldspeed) {
2861 new_state = 1;
2862 switch (phydev->speed) {
1da177e4 2863 case 1000:
1da177e4
LT		 2864 tempval =
2865 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2866
2867 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2868 break;
2869 case 100:
2870 case 10:
1da177e4
LT		 2871 tempval =
2872 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2873
2874 /* Reduced mode distinguishes
2875 * between 10 and 100 */
2876 if (phydev->speed == SPEED_100)
2877 ecntrl |= ECNTRL_R100;
2878 else
2879 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2880 break;
2881 default:
0bbaf069
KG		 2882 if (netif_msg_link(priv))
2883 printk(KERN_WARNING
bb40dcbb
AF		 2884 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2885 dev->name, phydev->speed);
1da177e4
LT		 2886 break;
2887 }
2888
bb40dcbb 2889 priv->oldspeed = phydev->speed;
1da177e4
LT		 2890 }
2891
bb40dcbb 2892 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2893 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2894
1da177e4 2895 if (!priv->oldlink) {
bb40dcbb 2896 new_state = 1;
1da177e4 2897 priv->oldlink = 1;
1da177e4 2898 }
bb40dcbb
AF		 2899 } else if (priv->oldlink) {
2900 new_state = 1;
2901 priv->oldlink = 0;
2902 priv->oldspeed = 0;
2903 priv->oldduplex = -1;
1da177e4 2904 }
1da177e4 2905
bb40dcbb
AF		 2906 if (new_state && netif_msg_link(priv))
2907 phy_print_status(phydev);
fba4ed03
SG		 2908 unlock_tx_qs(priv);
2909 local_irq_restore(flags);
bb40dcbb 2910}
1da177e4
LT		 2911
2912/* Update the hash table based on the current list of multicast
2913 * addresses we subscribe to. Also, change the promiscuity of
2914 * the device based on the flags (this function is called
2915 * whenever dev->flags is changed */
2916static void gfar_set_multi(struct net_device *dev)
2917{
22bedad3 2918 struct netdev_hw_addr *ha;
1da177e4 2919 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2920 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 2921 u32 tempval;
2922
a12f801d 2923 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2924 /* Set RCTRL to PROM */
2925 tempval = gfar_read(&regs->rctrl);
2926 tempval |= RCTRL_PROM;
2927 gfar_write(&regs->rctrl, tempval);
2928 } else {
2929 /* Set RCTRL to not PROM */
2930 tempval = gfar_read(&regs->rctrl);
2931 tempval &= ~(RCTRL_PROM);
2932 gfar_write(&regs->rctrl, tempval);
2933 }
6aa20a22 2934
a12f801d 2935 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2936 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2937 gfar_write(&regs->igaddr0, 0xffffffff);
2938 gfar_write(&regs->igaddr1, 0xffffffff);
2939 gfar_write(&regs->igaddr2, 0xffffffff);
2940 gfar_write(&regs->igaddr3, 0xffffffff);
2941 gfar_write(&regs->igaddr4, 0xffffffff);
2942 gfar_write(&regs->igaddr5, 0xffffffff);
2943 gfar_write(&regs->igaddr6, 0xffffffff);
2944 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2945 gfar_write(&regs->gaddr0, 0xffffffff);
2946 gfar_write(&regs->gaddr1, 0xffffffff);
2947 gfar_write(&regs->gaddr2, 0xffffffff);
2948 gfar_write(&regs->gaddr3, 0xffffffff);
2949 gfar_write(&regs->gaddr4, 0xffffffff);
2950 gfar_write(&regs->gaddr5, 0xffffffff);
2951 gfar_write(&regs->gaddr6, 0xffffffff);
2952 gfar_write(&regs->gaddr7, 0xffffffff);
2953 } else {
7f7f5316
AF		 2954 int em_num;
2955 int idx;
2956
1da177e4 2957 /* zero out the hash */
0bbaf069
KG		 2958 gfar_write(&regs->igaddr0, 0x0);
2959 gfar_write(&regs->igaddr1, 0x0);
2960 gfar_write(&regs->igaddr2, 0x0);
2961 gfar_write(&regs->igaddr3, 0x0);
2962 gfar_write(&regs->igaddr4, 0x0);
2963 gfar_write(&regs->igaddr5, 0x0);
2964 gfar_write(&regs->igaddr6, 0x0);
2965 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2966 gfar_write(&regs->gaddr0, 0x0);
2967 gfar_write(&regs->gaddr1, 0x0);
2968 gfar_write(&regs->gaddr2, 0x0);
2969 gfar_write(&regs->gaddr3, 0x0);
2970 gfar_write(&regs->gaddr4, 0x0);
2971 gfar_write(&regs->gaddr5, 0x0);
2972 gfar_write(&regs->gaddr6, 0x0);
2973 gfar_write(&regs->gaddr7, 0x0);
2974
7f7f5316
AF		 2975 /* If we have extended hash tables, we need to
2976 * clear the exact match registers to prepare for
2977 * setting them */
2978 if (priv->extended_hash) {
2979 em_num = GFAR_EM_NUM + 1;
2980 gfar_clear_exact_match(dev);
2981 idx = 1;
2982 } else {
2983 idx = 0;
2984 em_num = 0;
2985 }
2986
4cd24eaf 2987 if (netdev_mc_empty(dev))
1da177e4
LT		 2988 return;
2989
2990 /* Parse the list, and set the appropriate bits */
22bedad3 2991 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 2992 if (idx < em_num) {
22bedad3 2993 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 2994 idx++;
2995 } else
22bedad3 2996 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 2997 }
2998 }
1da177e4
LT		 2999}
3000
7f7f5316
AF		 3001
3002/* Clears each of the exact match registers to zero, so they
3003 * don't interfere with normal reception */
3004static void gfar_clear_exact_match(struct net_device *dev)
3005{
3006 int idx;
3007 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3008
3009 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3010 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3011}
3012
1da177e4
LT		 3013/* Set the appropriate hash bit for the given addr */
3014/* The algorithm works like so:
3015 * 1) Take the Destination Address (ie the multicast address), and
3016 * do a CRC on it (little endian), and reverse the bits of the
3017 * result.
3018 * 2) Use the 8 most significant bits as a hash into a 256-entry
3019 * table. The table is controlled through 8 32-bit registers:
3020 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3021 * gaddr7. This means that the 3 most significant bits in the
3022 * hash index which gaddr register to use, and the 5 other bits
3023 * indicate which bit (assuming an IBM numbering scheme, which
3024 * for PowerPC (tm) is usually the case) in the register holds
3025 * the entry. */
3026static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3027{
3028 u32 tempval;
3029 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3030 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3031 int width = priv->hash_width;
3032 u8 whichbit = (result >> (32 - width)) & 0x1f;
3033 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3034 u32 value = (1 << (31-whichbit));
3035
0bbaf069 3036 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3037 tempval |= value;
0bbaf069 3038 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3039}
3040
7f7f5316
AF		 3041
3042/* There are multiple MAC Address register pairs on some controllers
3043 * This function sets the numth pair to a given address
3044 */
3045static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3046{
3047 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3048 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3049 int idx;
3050 char tmpbuf[MAC_ADDR_LEN];
3051 u32 tempval;
f4983704 3052 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3053
3054 macptr += num*2;
3055
3056 /* Now copy it into the mac registers backwards, cuz */
3057 /* little endian is silly */
3058 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3059 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3060
3061 gfar_write(macptr, *((u32 *) (tmpbuf)));
3062
3063 tempval = *((u32 *) (tmpbuf + 4));
3064
3065 gfar_write(macptr+1, tempval);
3066}
3067
1da177e4 3068/* GFAR error interrupt handler */
f4983704 3069static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3070{
f4983704
SG		 3071 struct gfar_priv_grp *gfargrp = grp_id;
3072 struct gfar __iomem *regs = gfargrp->regs;
3073 struct gfar_private *priv= gfargrp->priv;
3074 struct net_device *dev = priv->ndev;
1da177e4
LT		 3075
3076 /* Save ievent for future reference */
f4983704 3077 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3078
3079 /* Clear IEVENT */
f4983704 3080 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3081
3082 /* Magic Packet is not an error. */
b31a1d8b 3083 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3084 (events & IEVENT_MAG))
3085 events &= ~IEVENT_MAG;
1da177e4
LT		 3086
3087 /* Hmm... */
0bbaf069
KG		 3088 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3089 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 3090 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 3091
3092 /* Update the error counters */
3093 if (events & IEVENT_TXE) {
09f75cd7 3094 dev->stats.tx_errors++;
1da177e4
LT		 3095
3096 if (events & IEVENT_LC)
09f75cd7 3097 dev->stats.tx_window_errors++;
1da177e4 3098 if (events & IEVENT_CRL)
09f75cd7 3099 dev->stats.tx_aborted_errors++;
1da177e4 3100 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3101 unsigned long flags;
3102
0bbaf069 3103 if (netif_msg_tx_err(priv))
538cc7ee
SS		 3104 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3105 "packet dropped.\n", dev->name);
09f75cd7 3106 dev->stats.tx_dropped++;
1da177e4
LT		 3107 priv->extra_stats.tx_underrun++;
3108
836cf7fa
AV		 3109 local_irq_save(flags);
3110 lock_tx_qs(priv);
3111
1da177e4 3112 /* Reactivate the Tx Queues */
fba4ed03 3113 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3114
3115 unlock_tx_qs(priv);
3116 local_irq_restore(flags);
1da177e4 3117 }
0bbaf069
KG		 3118 if (netif_msg_tx_err(priv))
3119 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3120 }
3121 if (events & IEVENT_BSY) {
09f75cd7 3122 dev->stats.rx_errors++;
1da177e4
LT		 3123 priv->extra_stats.rx_bsy++;
3124
f4983704 3125 gfar_receive(irq, grp_id);
1da177e4 3126
0bbaf069 3127 if (netif_msg_rx_err(priv))
538cc7ee 3128 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3129 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3130 }
3131 if (events & IEVENT_BABR) {
09f75cd7 3132 dev->stats.rx_errors++;
1da177e4
LT		 3133 priv->extra_stats.rx_babr++;
3134
0bbaf069 3135 if (netif_msg_rx_err(priv))
538cc7ee 3136 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3137 }
3138 if (events & IEVENT_EBERR) {
3139 priv->extra_stats.eberr++;
0bbaf069 3140 if (netif_msg_rx_err(priv))
538cc7ee 3141 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3142 }
0bbaf069 3143 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3144 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3145
3146 if (events & IEVENT_BABT) {
3147 priv->extra_stats.tx_babt++;
0bbaf069 3148 if (netif_msg_tx_err(priv))
538cc7ee 3149 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3150 }
3151 return IRQ_HANDLED;
3152}
3153
b31a1d8b
AF		 3154static struct of_device_id gfar_match[] =
3155{
3156 {
3157 .type = "network",
3158 .compatible = "gianfar",
3159 },
46ceb60c
SG		 3160 {
3161 .compatible = "fsl,etsec2",
3162 },
b31a1d8b
AF		 3163 {},
3164};
e72701ac 3165MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3166
1da177e4 3167/* Structure for a device driver */
b31a1d8b 3168static struct of_platform_driver gfar_driver = {
4018294b
GL		 3169 .driver = {
3170 .name = "fsl-gianfar",
3171 .owner = THIS_MODULE,
3172 .pm = GFAR_PM_OPS,
3173 .of_match_table = gfar_match,
3174 },
1da177e4
LT		 3175 .probe = gfar_probe,
3176 .remove = gfar_remove,
3177};
3178
3179static int __init gfar_init(void)
3180{
1577ecef 3181 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3182}
3183
3184static void __exit gfar_exit(void)
3185{
b31a1d8b 3186 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3187}
3188
3189module_init(gfar_init);
3190module_exit(gfar_exit);
3191
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