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Commit | Line | Data |
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0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
a12f801d | 11 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 12 | * |
a12f801d SG |
13 | * Copyright 2002-2009 Freescale Semiconductor, Inc. |
14 | * Copyright 2007 MontaVista Software, Inc. | |
1da177e4 LT |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify it | |
17 | * under the terms of the GNU General Public License as published by the | |
18 | * Free Software Foundation; either version 2 of the License, or (at your | |
19 | * option) any later version. | |
20 | * | |
21 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
22 | * RA 11 31 24.2 | |
23 | * Dec +69 19 52 | |
24 | * V 3.84 | |
25 | * B-V +1.62 | |
26 | * | |
27 | * Theory of operation | |
0bbaf069 | 28 | * |
b31a1d8b AF |
29 | * The driver is initialized through of_device. Configuration information |
30 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
31 | * |
32 | * The Gianfar Ethernet Controller uses a ring of buffer | |
33 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
34 | * pointing to the physical address of the start of the ring. |
35 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
36 | * last descriptor of the ring. |
37 | * | |
38 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 39 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
40 | * corresponding bit in the IMASK register is also set (if |
41 | * interrupt coalescing is active, then the interrupt may not | |
42 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 43 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 44 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 45 | * exit. This method will start at the last known empty |
0bbaf069 | 46 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
47 | * are none left with data (NAPI will stop after a set number of |
48 | * packets to give time to other tasks, but will eventually | |
49 | * process all the packets). The data arrives inside a | |
50 | * pre-allocated skb, and so after the skb is passed up to the | |
51 | * stack, a new skb must be allocated, and the address field in | |
52 | * the buffer descriptor must be updated to indicate this new | |
53 | * skb. | |
54 | * | |
55 | * When the kernel requests that a packet be transmitted, the | |
56 | * driver starts where it left off last time, and points the | |
57 | * descriptor at the buffer which was passed in. The driver | |
58 | * then informs the DMA engine that there are packets ready to | |
59 | * be transmitted. Once the controller is finished transmitting | |
60 | * the packet, an interrupt may be triggered (under the same | |
61 | * conditions as for reception, but depending on the TXF bit). | |
62 | * The driver then cleans up the buffer. | |
63 | */ | |
64 | ||
1da177e4 | 65 | #include <linux/kernel.h> |
1da177e4 LT |
66 | #include <linux/string.h> |
67 | #include <linux/errno.h> | |
bb40dcbb | 68 | #include <linux/unistd.h> |
1da177e4 LT |
69 | #include <linux/slab.h> |
70 | #include <linux/interrupt.h> | |
71 | #include <linux/init.h> | |
72 | #include <linux/delay.h> | |
73 | #include <linux/netdevice.h> | |
74 | #include <linux/etherdevice.h> | |
75 | #include <linux/skbuff.h> | |
0bbaf069 | 76 | #include <linux/if_vlan.h> |
1da177e4 LT |
77 | #include <linux/spinlock.h> |
78 | #include <linux/mm.h> | |
fe192a49 | 79 | #include <linux/of_mdio.h> |
b31a1d8b | 80 | #include <linux/of_platform.h> |
0bbaf069 KG |
81 | #include <linux/ip.h> |
82 | #include <linux/tcp.h> | |
83 | #include <linux/udp.h> | |
9c07b884 | 84 | #include <linux/in.h> |
cc772ab7 | 85 | #include <linux/net_tstamp.h> |
1da177e4 LT |
86 | |
87 | #include <asm/io.h> | |
88 | #include <asm/irq.h> | |
89 | #include <asm/uaccess.h> | |
90 | #include <linux/module.h> | |
1da177e4 LT |
91 | #include <linux/dma-mapping.h> |
92 | #include <linux/crc32.h> | |
bb40dcbb AF |
93 | #include <linux/mii.h> |
94 | #include <linux/phy.h> | |
b31a1d8b AF |
95 | #include <linux/phy_fixed.h> |
96 | #include <linux/of.h> | |
1da177e4 LT |
97 | |
98 | #include "gianfar.h" | |
1577ecef | 99 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
100 | |
101 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
102 | #undef BRIEF_GFAR_ERRORS |
103 | #undef VERBOSE_GFAR_ERRORS | |
104 | ||
1da177e4 | 105 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
124 | static int gfar_probe(struct of_device *ofdev, |
125 | const struct of_device_id *match); | |
126 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 127 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
128 | static void gfar_set_multi(struct net_device *dev); |
129 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 130 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 131 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
132 | #ifdef CONFIG_NET_POLL_CONTROLLER |
133 | static void gfar_netpoll(struct net_device *dev); | |
134 | #endif | |
a12f801d SG |
135 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
136 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a DH |
137 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
138 | int amount_pull); | |
0bbaf069 KG |
139 | static void gfar_vlan_rx_register(struct net_device *netdev, |
140 | struct vlan_group *grp); | |
7f7f5316 | 141 | void gfar_halt(struct net_device *dev); |
d87eb127 | 142 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
143 | void gfar_start(struct net_device *dev); |
144 | static void gfar_clear_exact_match(struct net_device *dev); | |
145 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
26ccfc37 | 146 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 147 | |
1da177e4 LT |
148 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
149 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
150 | MODULE_LICENSE("GPL"); | |
151 | ||
a12f801d | 152 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
153 | dma_addr_t buf) |
154 | { | |
8a102fe0 AV |
155 | u32 lstatus; |
156 | ||
157 | bdp->bufPtr = buf; | |
158 | ||
159 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 160 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
161 | lstatus |= BD_LFLAG(RXBD_WRAP); |
162 | ||
163 | eieio(); | |
164 | ||
165 | bdp->lstatus = lstatus; | |
166 | } | |
167 | ||
8728327e | 168 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 169 | { |
8728327e | 170 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
171 | struct gfar_priv_tx_q *tx_queue = NULL; |
172 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
173 | struct txbd8 *txbdp; |
174 | struct rxbd8 *rxbdp; | |
fba4ed03 | 175 | int i, j; |
a12f801d | 176 | |
fba4ed03 SG |
177 | for (i = 0; i < priv->num_tx_queues; i++) { |
178 | tx_queue = priv->tx_queue[i]; | |
179 | /* Initialize some variables in our dev structure */ | |
180 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
181 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
182 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
183 | tx_queue->skb_curtx = 0; | |
184 | tx_queue->skb_dirtytx = 0; | |
185 | ||
186 | /* Initialize Transmit Descriptor Ring */ | |
187 | txbdp = tx_queue->tx_bd_base; | |
188 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
189 | txbdp->lstatus = 0; | |
190 | txbdp->bufPtr = 0; | |
191 | txbdp++; | |
192 | } | |
8728327e | 193 | |
fba4ed03 SG |
194 | /* Set the last descriptor in the ring to indicate wrap */ |
195 | txbdp--; | |
196 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
197 | } |
198 | ||
fba4ed03 SG |
199 | for (i = 0; i < priv->num_rx_queues; i++) { |
200 | rx_queue = priv->rx_queue[i]; | |
201 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
202 | rx_queue->skb_currx = 0; | |
203 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 204 | |
fba4ed03 SG |
205 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
206 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 207 | |
fba4ed03 SG |
208 | if (skb) { |
209 | gfar_init_rxbdp(rx_queue, rxbdp, | |
210 | rxbdp->bufPtr); | |
211 | } else { | |
212 | skb = gfar_new_skb(ndev); | |
213 | if (!skb) { | |
214 | pr_err("%s: Can't allocate RX buffers\n", | |
215 | ndev->name); | |
216 | goto err_rxalloc_fail; | |
217 | } | |
218 | rx_queue->rx_skbuff[j] = skb; | |
219 | ||
220 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 221 | } |
8728327e | 222 | |
fba4ed03 | 223 | rxbdp++; |
8728327e AV |
224 | } |
225 | ||
8728327e AV |
226 | } |
227 | ||
228 | return 0; | |
fba4ed03 SG |
229 | |
230 | err_rxalloc_fail: | |
231 | free_skb_resources(priv); | |
232 | return -ENOMEM; | |
8728327e AV |
233 | } |
234 | ||
235 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
236 | { | |
826aa4a0 | 237 | void *vaddr; |
fba4ed03 SG |
238 | dma_addr_t addr; |
239 | int i, j, k; | |
826aa4a0 AV |
240 | struct gfar_private *priv = netdev_priv(ndev); |
241 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
242 | struct gfar_priv_tx_q *tx_queue = NULL; |
243 | struct gfar_priv_rx_q *rx_queue = NULL; | |
244 | ||
fba4ed03 SG |
245 | priv->total_tx_ring_size = 0; |
246 | for (i = 0; i < priv->num_tx_queues; i++) | |
247 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
248 | ||
249 | priv->total_rx_ring_size = 0; | |
250 | for (i = 0; i < priv->num_rx_queues; i++) | |
251 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
252 | |
253 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 254 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
255 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
256 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
257 | &addr, GFP_KERNEL); | |
826aa4a0 AV |
258 | if (!vaddr) { |
259 | if (netif_msg_ifup(priv)) | |
260 | pr_err("%s: Could not allocate buffer descriptors!\n", | |
261 | ndev->name); | |
262 | return -ENOMEM; | |
263 | } | |
264 | ||
fba4ed03 SG |
265 | for (i = 0; i < priv->num_tx_queues; i++) { |
266 | tx_queue = priv->tx_queue[i]; | |
267 | tx_queue->tx_bd_base = (struct txbd8 *) vaddr; | |
268 | tx_queue->tx_bd_dma_base = addr; | |
269 | tx_queue->dev = ndev; | |
270 | /* enet DMA only understands physical addresses */ | |
271 | addr += sizeof(struct txbd8) *tx_queue->tx_ring_size; | |
272 | vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size; | |
273 | } | |
826aa4a0 | 274 | |
826aa4a0 | 275 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
276 | for (i = 0; i < priv->num_rx_queues; i++) { |
277 | rx_queue = priv->rx_queue[i]; | |
278 | rx_queue->rx_bd_base = (struct rxbd8 *) vaddr; | |
279 | rx_queue->rx_bd_dma_base = addr; | |
280 | rx_queue->dev = ndev; | |
281 | addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size; | |
282 | vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size; | |
283 | } | |
826aa4a0 AV |
284 | |
285 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
286 | for (i = 0; i < priv->num_tx_queues; i++) { |
287 | tx_queue = priv->tx_queue[i]; | |
288 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
a12f801d | 289 | tx_queue->tx_ring_size, GFP_KERNEL); |
fba4ed03 SG |
290 | if (!tx_queue->tx_skbuff) { |
291 | if (netif_msg_ifup(priv)) | |
292 | pr_err("%s: Could not allocate tx_skbuff\n", | |
293 | ndev->name); | |
294 | goto cleanup; | |
295 | } | |
826aa4a0 | 296 | |
fba4ed03 SG |
297 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
298 | tx_queue->tx_skbuff[k] = NULL; | |
299 | } | |
826aa4a0 | 300 | |
fba4ed03 SG |
301 | for (i = 0; i < priv->num_rx_queues; i++) { |
302 | rx_queue = priv->rx_queue[i]; | |
303 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
a12f801d | 304 | rx_queue->rx_ring_size, GFP_KERNEL); |
826aa4a0 | 305 | |
fba4ed03 SG |
306 | if (!rx_queue->rx_skbuff) { |
307 | if (netif_msg_ifup(priv)) | |
308 | pr_err("%s: Could not allocate rx_skbuff\n", | |
309 | ndev->name); | |
310 | goto cleanup; | |
311 | } | |
312 | ||
313 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
314 | rx_queue->rx_skbuff[j] = NULL; | |
315 | } | |
826aa4a0 | 316 | |
8728327e AV |
317 | if (gfar_init_bds(ndev)) |
318 | goto cleanup; | |
826aa4a0 AV |
319 | |
320 | return 0; | |
321 | ||
322 | cleanup: | |
323 | free_skb_resources(priv); | |
324 | return -ENOMEM; | |
325 | } | |
326 | ||
fba4ed03 SG |
327 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
328 | { | |
46ceb60c | 329 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 330 | u32 __iomem *baddr; |
fba4ed03 SG |
331 | int i; |
332 | ||
333 | baddr = ®s->tbase0; | |
334 | for(i = 0; i < priv->num_tx_queues; i++) { | |
335 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); | |
336 | baddr += 2; | |
337 | } | |
338 | ||
339 | baddr = ®s->rbase0; | |
340 | for(i = 0; i < priv->num_rx_queues; i++) { | |
341 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); | |
342 | baddr += 2; | |
343 | } | |
344 | } | |
345 | ||
826aa4a0 AV |
346 | static void gfar_init_mac(struct net_device *ndev) |
347 | { | |
348 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 349 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
350 | u32 rctrl = 0; |
351 | u32 tctrl = 0; | |
352 | u32 attrs = 0; | |
353 | ||
fba4ed03 SG |
354 | /* write the tx/rx base registers */ |
355 | gfar_init_tx_rx_base(priv); | |
32c513bc | 356 | |
826aa4a0 | 357 | /* Configure the coalescing support */ |
46ceb60c | 358 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 359 | |
1ccb8389 | 360 | if (priv->rx_filer_enable) { |
fba4ed03 | 361 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
362 | /* Program the RIR0 reg with the required distribution */ |
363 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
364 | } | |
826aa4a0 AV |
365 | |
366 | if (priv->rx_csum_enable) | |
367 | rctrl |= RCTRL_CHECKSUMMING; | |
368 | ||
369 | if (priv->extended_hash) { | |
370 | rctrl |= RCTRL_EXTHASH; | |
371 | ||
372 | gfar_clear_exact_match(ndev); | |
373 | rctrl |= RCTRL_EMEN; | |
374 | } | |
375 | ||
376 | if (priv->padding) { | |
377 | rctrl &= ~RCTRL_PAL_MASK; | |
378 | rctrl |= RCTRL_PADDING(priv->padding); | |
379 | } | |
380 | ||
cc772ab7 MR |
381 | /* Insert receive time stamps into padding alignment bytes */ |
382 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
383 | rctrl &= ~RCTRL_PAL_MASK; | |
384 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8); | |
385 | priv->padding = 8; | |
386 | } | |
387 | ||
826aa4a0 AV |
388 | /* keep vlan related bits if it's enabled */ |
389 | if (priv->vlgrp) { | |
390 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; | |
391 | tctrl |= TCTRL_VLINS; | |
392 | } | |
393 | ||
394 | /* Init rctrl based on our settings */ | |
395 | gfar_write(®s->rctrl, rctrl); | |
396 | ||
397 | if (ndev->features & NETIF_F_IP_CSUM) | |
398 | tctrl |= TCTRL_INIT_CSUM; | |
399 | ||
fba4ed03 SG |
400 | tctrl |= TCTRL_TXSCHED_PRIO; |
401 | ||
826aa4a0 AV |
402 | gfar_write(®s->tctrl, tctrl); |
403 | ||
404 | /* Set the extraction length and index */ | |
405 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
406 | ATTRELI_EI(priv->rx_stash_index); | |
407 | ||
408 | gfar_write(®s->attreli, attrs); | |
409 | ||
410 | /* Start with defaults, and add stashing or locking | |
411 | * depending on the approprate variables */ | |
412 | attrs = ATTR_INIT_SETTINGS; | |
413 | ||
414 | if (priv->bd_stash_en) | |
415 | attrs |= ATTR_BDSTASH; | |
416 | ||
417 | if (priv->rx_stash_size != 0) | |
418 | attrs |= ATTR_BUFSTASH; | |
419 | ||
420 | gfar_write(®s->attr, attrs); | |
421 | ||
422 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
423 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
424 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
425 | } | |
426 | ||
a7f38041 SG |
427 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
428 | { | |
429 | struct gfar_private *priv = netdev_priv(dev); | |
430 | struct netdev_queue *txq; | |
431 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; | |
432 | unsigned long tx_packets = 0, tx_bytes = 0; | |
433 | int i = 0; | |
434 | ||
435 | for (i = 0; i < priv->num_rx_queues; i++) { | |
436 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
437 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; | |
438 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; | |
439 | } | |
440 | ||
441 | dev->stats.rx_packets = rx_packets; | |
442 | dev->stats.rx_bytes = rx_bytes; | |
443 | dev->stats.rx_dropped = rx_dropped; | |
444 | ||
445 | for (i = 0; i < priv->num_tx_queues; i++) { | |
446 | txq = netdev_get_tx_queue(dev, i); | |
447 | tx_bytes += txq->tx_bytes; | |
448 | tx_packets += txq->tx_packets; | |
449 | } | |
450 | ||
451 | dev->stats.tx_bytes = tx_bytes; | |
452 | dev->stats.tx_packets = tx_packets; | |
453 | ||
454 | return &dev->stats; | |
455 | } | |
456 | ||
26ccfc37 AF |
457 | static const struct net_device_ops gfar_netdev_ops = { |
458 | .ndo_open = gfar_enet_open, | |
459 | .ndo_start_xmit = gfar_start_xmit, | |
460 | .ndo_stop = gfar_close, | |
461 | .ndo_change_mtu = gfar_change_mtu, | |
462 | .ndo_set_multicast_list = gfar_set_multi, | |
463 | .ndo_tx_timeout = gfar_timeout, | |
464 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 465 | .ndo_get_stats = gfar_get_stats, |
26ccfc37 | 466 | .ndo_vlan_rx_register = gfar_vlan_rx_register, |
240c102d BH |
467 | .ndo_set_mac_address = eth_mac_addr, |
468 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
469 | #ifdef CONFIG_NET_POLL_CONTROLLER |
470 | .ndo_poll_controller = gfar_netpoll, | |
471 | #endif | |
472 | }; | |
473 | ||
7a8b3372 SG |
474 | unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; |
475 | unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; | |
476 | ||
fba4ed03 SG |
477 | void lock_rx_qs(struct gfar_private *priv) |
478 | { | |
479 | int i = 0x0; | |
480 | ||
481 | for (i = 0; i < priv->num_rx_queues; i++) | |
482 | spin_lock(&priv->rx_queue[i]->rxlock); | |
483 | } | |
484 | ||
485 | void lock_tx_qs(struct gfar_private *priv) | |
486 | { | |
487 | int i = 0x0; | |
488 | ||
489 | for (i = 0; i < priv->num_tx_queues; i++) | |
490 | spin_lock(&priv->tx_queue[i]->txlock); | |
491 | } | |
492 | ||
493 | void unlock_rx_qs(struct gfar_private *priv) | |
494 | { | |
495 | int i = 0x0; | |
496 | ||
497 | for (i = 0; i < priv->num_rx_queues; i++) | |
498 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
499 | } | |
500 | ||
501 | void unlock_tx_qs(struct gfar_private *priv) | |
502 | { | |
503 | int i = 0x0; | |
504 | ||
505 | for (i = 0; i < priv->num_tx_queues; i++) | |
506 | spin_unlock(&priv->tx_queue[i]->txlock); | |
507 | } | |
508 | ||
7f7f5316 AF |
509 | /* Returns 1 if incoming frames use an FCB */ |
510 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 511 | { |
cc772ab7 MR |
512 | return priv->vlgrp || priv->rx_csum_enable || |
513 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); | |
0bbaf069 | 514 | } |
bb40dcbb | 515 | |
fba4ed03 SG |
516 | static void free_tx_pointers(struct gfar_private *priv) |
517 | { | |
518 | int i = 0; | |
519 | ||
520 | for (i = 0; i < priv->num_tx_queues; i++) | |
521 | kfree(priv->tx_queue[i]); | |
522 | } | |
523 | ||
524 | static void free_rx_pointers(struct gfar_private *priv) | |
525 | { | |
526 | int i = 0; | |
527 | ||
528 | for (i = 0; i < priv->num_rx_queues; i++) | |
529 | kfree(priv->rx_queue[i]); | |
530 | } | |
531 | ||
46ceb60c SG |
532 | static void unmap_group_regs(struct gfar_private *priv) |
533 | { | |
534 | int i = 0; | |
535 | ||
536 | for (i = 0; i < MAXGROUPS; i++) | |
537 | if (priv->gfargrp[i].regs) | |
538 | iounmap(priv->gfargrp[i].regs); | |
539 | } | |
540 | ||
541 | static void disable_napi(struct gfar_private *priv) | |
542 | { | |
543 | int i = 0; | |
544 | ||
545 | for (i = 0; i < priv->num_grps; i++) | |
546 | napi_disable(&priv->gfargrp[i].napi); | |
547 | } | |
548 | ||
549 | static void enable_napi(struct gfar_private *priv) | |
550 | { | |
551 | int i = 0; | |
552 | ||
553 | for (i = 0; i < priv->num_grps; i++) | |
554 | napi_enable(&priv->gfargrp[i].napi); | |
555 | } | |
556 | ||
557 | static int gfar_parse_group(struct device_node *np, | |
558 | struct gfar_private *priv, const char *model) | |
559 | { | |
560 | u32 *queue_mask; | |
561 | u64 addr, size; | |
562 | ||
563 | addr = of_translate_address(np, | |
564 | of_get_address(np, 0, &size, NULL)); | |
565 | priv->gfargrp[priv->num_grps].regs = ioremap(addr, size); | |
566 | ||
567 | if (!priv->gfargrp[priv->num_grps].regs) | |
568 | return -ENOMEM; | |
569 | ||
570 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
571 | irq_of_parse_and_map(np, 0); | |
572 | ||
573 | /* If we aren't the FEC we have multiple interrupts */ | |
574 | if (model && strcasecmp(model, "FEC")) { | |
575 | priv->gfargrp[priv->num_grps].interruptReceive = | |
576 | irq_of_parse_and_map(np, 1); | |
577 | priv->gfargrp[priv->num_grps].interruptError = | |
578 | irq_of_parse_and_map(np,2); | |
579 | if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 || | |
580 | priv->gfargrp[priv->num_grps].interruptReceive < 0 || | |
581 | priv->gfargrp[priv->num_grps].interruptError < 0) { | |
582 | return -EINVAL; | |
583 | } | |
584 | } | |
585 | ||
586 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
587 | priv->gfargrp[priv->num_grps].priv = priv; | |
588 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
589 | if(priv->mode == MQ_MG_MODE) { | |
590 | queue_mask = (u32 *)of_get_property(np, | |
591 | "fsl,rx-bit-map", NULL); | |
592 | priv->gfargrp[priv->num_grps].rx_bit_map = | |
593 | queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps); | |
594 | queue_mask = (u32 *)of_get_property(np, | |
595 | "fsl,tx-bit-map", NULL); | |
596 | priv->gfargrp[priv->num_grps].tx_bit_map = | |
597 | queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
598 | } else { | |
599 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
600 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
601 | } | |
602 | priv->num_grps++; | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
fba4ed03 | 607 | static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev) |
b31a1d8b | 608 | { |
b31a1d8b AF |
609 | const char *model; |
610 | const char *ctype; | |
611 | const void *mac_addr; | |
fba4ed03 SG |
612 | int err = 0, i; |
613 | struct net_device *dev = NULL; | |
614 | struct gfar_private *priv = NULL; | |
615 | struct device_node *np = ofdev->node; | |
46ceb60c | 616 | struct device_node *child = NULL; |
4d7902f2 AF |
617 | const u32 *stash; |
618 | const u32 *stash_len; | |
619 | const u32 *stash_idx; | |
fba4ed03 SG |
620 | unsigned int num_tx_qs, num_rx_qs; |
621 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
622 | |
623 | if (!np || !of_device_is_available(np)) | |
624 | return -ENODEV; | |
625 | ||
fba4ed03 SG |
626 | /* parse the num of tx and rx queues */ |
627 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
628 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
629 | ||
630 | if (num_tx_qs > MAX_TX_QS) { | |
631 | printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", | |
632 | num_tx_qs, MAX_TX_QS); | |
633 | printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); | |
634 | return -EINVAL; | |
635 | } | |
636 | ||
637 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
638 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
639 | ||
640 | if (num_rx_qs > MAX_RX_QS) { | |
641 | printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", | |
642 | num_tx_qs, MAX_TX_QS); | |
643 | printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); | |
644 | return -EINVAL; | |
645 | } | |
646 | ||
647 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
648 | dev = *pdev; | |
649 | if (NULL == dev) | |
650 | return -ENOMEM; | |
651 | ||
652 | priv = netdev_priv(dev); | |
653 | priv->node = ofdev->node; | |
654 | priv->ndev = dev; | |
655 | ||
656 | dev->num_tx_queues = num_tx_qs; | |
657 | dev->real_num_tx_queues = num_tx_qs; | |
658 | priv->num_tx_queues = num_tx_qs; | |
659 | priv->num_rx_queues = num_rx_qs; | |
46ceb60c | 660 | priv->num_grps = 0x0; |
b31a1d8b AF |
661 | |
662 | model = of_get_property(np, "model", NULL); | |
663 | ||
46ceb60c SG |
664 | for (i = 0; i < MAXGROUPS; i++) |
665 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 666 | |
46ceb60c SG |
667 | /* Parse and initialize group specific information */ |
668 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
669 | priv->mode = MQ_MG_MODE; | |
670 | for_each_child_of_node(np, child) { | |
671 | err = gfar_parse_group(child, priv, model); | |
672 | if (err) | |
673 | goto err_grp_init; | |
b31a1d8b | 674 | } |
46ceb60c SG |
675 | } else { |
676 | priv->mode = SQ_SG_MODE; | |
677 | err = gfar_parse_group(np, priv, model); | |
678 | if(err) | |
679 | goto err_grp_init; | |
b31a1d8b AF |
680 | } |
681 | ||
fba4ed03 SG |
682 | for (i = 0; i < priv->num_tx_queues; i++) |
683 | priv->tx_queue[i] = NULL; | |
684 | for (i = 0; i < priv->num_rx_queues; i++) | |
685 | priv->rx_queue[i] = NULL; | |
686 | ||
687 | for (i = 0; i < priv->num_tx_queues; i++) { | |
ed130589 | 688 | priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc( |
fba4ed03 SG |
689 | sizeof (struct gfar_priv_tx_q), GFP_KERNEL); |
690 | if (!priv->tx_queue[i]) { | |
691 | err = -ENOMEM; | |
692 | goto tx_alloc_failed; | |
693 | } | |
694 | priv->tx_queue[i]->tx_skbuff = NULL; | |
695 | priv->tx_queue[i]->qindex = i; | |
696 | priv->tx_queue[i]->dev = dev; | |
697 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
698 | } | |
699 | ||
700 | for (i = 0; i < priv->num_rx_queues; i++) { | |
ed130589 | 701 | priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc( |
fba4ed03 SG |
702 | sizeof (struct gfar_priv_rx_q), GFP_KERNEL); |
703 | if (!priv->rx_queue[i]) { | |
704 | err = -ENOMEM; | |
705 | goto rx_alloc_failed; | |
706 | } | |
707 | priv->rx_queue[i]->rx_skbuff = NULL; | |
708 | priv->rx_queue[i]->qindex = i; | |
709 | priv->rx_queue[i]->dev = dev; | |
710 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
711 | } | |
712 | ||
713 | ||
4d7902f2 AF |
714 | stash = of_get_property(np, "bd-stash", NULL); |
715 | ||
a12f801d | 716 | if (stash) { |
4d7902f2 AF |
717 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
718 | priv->bd_stash_en = 1; | |
719 | } | |
720 | ||
721 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
722 | ||
723 | if (stash_len) | |
724 | priv->rx_stash_size = *stash_len; | |
725 | ||
726 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
727 | ||
728 | if (stash_idx) | |
729 | priv->rx_stash_index = *stash_idx; | |
730 | ||
731 | if (stash_len || stash_idx) | |
732 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
733 | ||
b31a1d8b AF |
734 | mac_addr = of_get_mac_address(np); |
735 | if (mac_addr) | |
736 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
737 | ||
738 | if (model && !strcasecmp(model, "TSEC")) | |
739 | priv->device_flags = | |
740 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
741 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
742 | FSL_GIANFAR_DEV_HAS_RMON | | |
743 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
744 | if (model && !strcasecmp(model, "eTSEC")) | |
745 | priv->device_flags = | |
746 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
747 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
748 | FSL_GIANFAR_DEV_HAS_RMON | | |
749 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 750 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
751 | FSL_GIANFAR_DEV_HAS_CSUM | |
752 | FSL_GIANFAR_DEV_HAS_VLAN | | |
753 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
cc772ab7 MR |
754 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | |
755 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
756 | |
757 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
758 | ||
759 | /* We only care about rgmii-id. The rest are autodetected */ | |
760 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
761 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
762 | else | |
763 | priv->interface = PHY_INTERFACE_MODE_MII; | |
764 | ||
765 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
766 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
767 | ||
fe192a49 | 768 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
769 | |
770 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 771 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
772 | |
773 | return 0; | |
774 | ||
fba4ed03 SG |
775 | rx_alloc_failed: |
776 | free_rx_pointers(priv); | |
777 | tx_alloc_failed: | |
778 | free_tx_pointers(priv); | |
46ceb60c SG |
779 | err_grp_init: |
780 | unmap_group_regs(priv); | |
fba4ed03 | 781 | free_netdev(dev); |
b31a1d8b AF |
782 | return err; |
783 | } | |
784 | ||
cc772ab7 MR |
785 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
786 | struct ifreq *ifr, int cmd) | |
787 | { | |
788 | struct hwtstamp_config config; | |
789 | struct gfar_private *priv = netdev_priv(netdev); | |
790 | ||
791 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
792 | return -EFAULT; | |
793 | ||
794 | /* reserved for future extensions */ | |
795 | if (config.flags) | |
796 | return -EINVAL; | |
797 | ||
798 | if (config.tx_type) | |
799 | return -ERANGE; | |
800 | ||
801 | switch (config.rx_filter) { | |
802 | case HWTSTAMP_FILTER_NONE: | |
803 | priv->hwts_rx_en = 0; | |
804 | break; | |
805 | default: | |
806 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
807 | return -ERANGE; | |
808 | priv->hwts_rx_en = 1; | |
809 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
810 | break; | |
811 | } | |
812 | ||
813 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
814 | -EFAULT : 0; | |
815 | } | |
816 | ||
0faac9f7 CW |
817 | /* Ioctl MII Interface */ |
818 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
819 | { | |
820 | struct gfar_private *priv = netdev_priv(dev); | |
821 | ||
822 | if (!netif_running(dev)) | |
823 | return -EINVAL; | |
824 | ||
cc772ab7 MR |
825 | if (cmd == SIOCSHWTSTAMP) |
826 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
827 | ||
0faac9f7 CW |
828 | if (!priv->phydev) |
829 | return -ENODEV; | |
830 | ||
831 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
832 | } | |
833 | ||
fba4ed03 SG |
834 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
835 | { | |
836 | unsigned int new_bit_map = 0x0; | |
837 | int mask = 0x1 << (max_qs - 1), i; | |
838 | for (i = 0; i < max_qs; i++) { | |
839 | if (bit_map & mask) | |
840 | new_bit_map = new_bit_map + (1 << i); | |
841 | mask = mask >> 0x1; | |
842 | } | |
843 | return new_bit_map; | |
844 | } | |
7a8b3372 | 845 | |
18294ad1 AV |
846 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
847 | u32 class) | |
7a8b3372 SG |
848 | { |
849 | u32 rqfpr = FPR_FILER_MASK; | |
850 | u32 rqfcr = 0x0; | |
851 | ||
852 | rqfar--; | |
853 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
854 | ftp_rqfpr[rqfar] = rqfpr; | |
855 | ftp_rqfcr[rqfar] = rqfcr; | |
856 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); | |
857 | ||
858 | rqfar--; | |
859 | rqfcr = RQFCR_CMP_NOMATCH; | |
860 | ftp_rqfpr[rqfar] = rqfpr; | |
861 | ftp_rqfcr[rqfar] = rqfcr; | |
862 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); | |
863 | ||
864 | rqfar--; | |
865 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
866 | rqfpr = class; | |
867 | ftp_rqfcr[rqfar] = rqfcr; | |
868 | ftp_rqfpr[rqfar] = rqfpr; | |
869 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); | |
870 | ||
871 | rqfar--; | |
872 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
873 | rqfpr = class; | |
874 | ftp_rqfcr[rqfar] = rqfcr; | |
875 | ftp_rqfpr[rqfar] = rqfpr; | |
876 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); | |
877 | ||
878 | return rqfar; | |
879 | } | |
880 | ||
881 | static void gfar_init_filer_table(struct gfar_private *priv) | |
882 | { | |
883 | int i = 0x0; | |
884 | u32 rqfar = MAX_FILER_IDX; | |
885 | u32 rqfcr = 0x0; | |
886 | u32 rqfpr = FPR_FILER_MASK; | |
887 | ||
888 | /* Default rule */ | |
889 | rqfcr = RQFCR_CMP_MATCH; | |
890 | ftp_rqfcr[rqfar] = rqfcr; | |
891 | ftp_rqfpr[rqfar] = rqfpr; | |
892 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); | |
893 | ||
894 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
895 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
896 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
897 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
898 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
899 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
900 | ||
901 | /* cur_filer_idx indicated the fisrt non-masked rule */ | |
902 | priv->cur_filer_idx = rqfar; | |
903 | ||
904 | /* Rest are masked rules */ | |
905 | rqfcr = RQFCR_CMP_NOMATCH; | |
906 | for (i = 0; i < rqfar; i++) { | |
907 | ftp_rqfcr[i] = rqfcr; | |
908 | ftp_rqfpr[i] = rqfpr; | |
909 | gfar_write_filer(priv, i, rqfcr, rqfpr); | |
910 | } | |
911 | } | |
912 | ||
bb40dcbb AF |
913 | /* Set up the ethernet device structure, private data, |
914 | * and anything else we need before we start */ | |
b31a1d8b AF |
915 | static int gfar_probe(struct of_device *ofdev, |
916 | const struct of_device_id *match) | |
1da177e4 LT |
917 | { |
918 | u32 tempval; | |
919 | struct net_device *dev = NULL; | |
920 | struct gfar_private *priv = NULL; | |
f4983704 | 921 | struct gfar __iomem *regs = NULL; |
46ceb60c | 922 | int err = 0, i, grp_idx = 0; |
c50a5d9a | 923 | int len_devname; |
fba4ed03 | 924 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 925 | u32 isrg = 0; |
18294ad1 | 926 | u32 __iomem *baddr; |
1da177e4 | 927 | |
fba4ed03 | 928 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 929 | |
fba4ed03 SG |
930 | if (err) |
931 | return err; | |
1da177e4 LT |
932 | |
933 | priv = netdev_priv(dev); | |
4826857f KG |
934 | priv->ndev = dev; |
935 | priv->ofdev = ofdev; | |
b31a1d8b | 936 | priv->node = ofdev->node; |
4826857f | 937 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 938 | |
d87eb127 | 939 | spin_lock_init(&priv->bflock); |
ab939905 | 940 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 941 | |
b31a1d8b | 942 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 943 | regs = priv->gfargrp[0].regs; |
1da177e4 LT |
944 | |
945 | /* Stop the DMA engine now, in case it was running before */ | |
946 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 947 | gfar_halt(dev); |
1da177e4 LT |
948 | |
949 | /* Reset MAC layer */ | |
f4983704 | 950 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 951 | |
b98ac702 AF |
952 | /* We need to delay at least 3 TX clocks */ |
953 | udelay(2); | |
954 | ||
1da177e4 | 955 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 956 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
957 | |
958 | /* Initialize MACCFG2. */ | |
f4983704 | 959 | gfar_write(®s->maccfg2, MACCFG2_INIT_SETTINGS); |
1da177e4 LT |
960 | |
961 | /* Initialize ECNTRL */ | |
f4983704 | 962 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 963 | |
1da177e4 | 964 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 965 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 966 | |
b31a1d8b | 967 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
968 | |
969 | /* Fill in the dev structure */ | |
1da177e4 | 970 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 971 | dev->mtu = 1500; |
26ccfc37 | 972 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
973 | dev->ethtool_ops = &gfar_ethtool_ops; |
974 | ||
fba4ed03 | 975 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c SG |
976 | for (i = 0; i < priv->num_grps; i++) |
977 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT); | |
a12f801d | 978 | |
b31a1d8b | 979 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 980 | priv->rx_csum_enable = 1; |
4669bc90 | 981 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
982 | } else |
983 | priv->rx_csum_enable = 0; | |
984 | ||
985 | priv->vlgrp = NULL; | |
1da177e4 | 986 | |
26ccfc37 | 987 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 988 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 989 | |
b31a1d8b | 990 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
991 | priv->extended_hash = 1; |
992 | priv->hash_width = 9; | |
993 | ||
f4983704 SG |
994 | priv->hash_regs[0] = ®s->igaddr0; |
995 | priv->hash_regs[1] = ®s->igaddr1; | |
996 | priv->hash_regs[2] = ®s->igaddr2; | |
997 | priv->hash_regs[3] = ®s->igaddr3; | |
998 | priv->hash_regs[4] = ®s->igaddr4; | |
999 | priv->hash_regs[5] = ®s->igaddr5; | |
1000 | priv->hash_regs[6] = ®s->igaddr6; | |
1001 | priv->hash_regs[7] = ®s->igaddr7; | |
1002 | priv->hash_regs[8] = ®s->gaddr0; | |
1003 | priv->hash_regs[9] = ®s->gaddr1; | |
1004 | priv->hash_regs[10] = ®s->gaddr2; | |
1005 | priv->hash_regs[11] = ®s->gaddr3; | |
1006 | priv->hash_regs[12] = ®s->gaddr4; | |
1007 | priv->hash_regs[13] = ®s->gaddr5; | |
1008 | priv->hash_regs[14] = ®s->gaddr6; | |
1009 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1010 | |
1011 | } else { | |
1012 | priv->extended_hash = 0; | |
1013 | priv->hash_width = 8; | |
1014 | ||
f4983704 SG |
1015 | priv->hash_regs[0] = ®s->gaddr0; |
1016 | priv->hash_regs[1] = ®s->gaddr1; | |
1017 | priv->hash_regs[2] = ®s->gaddr2; | |
1018 | priv->hash_regs[3] = ®s->gaddr3; | |
1019 | priv->hash_regs[4] = ®s->gaddr4; | |
1020 | priv->hash_regs[5] = ®s->gaddr5; | |
1021 | priv->hash_regs[6] = ®s->gaddr6; | |
1022 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1023 | } |
1024 | ||
b31a1d8b | 1025 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1026 | priv->padding = DEFAULT_PADDING; |
1027 | else | |
1028 | priv->padding = 0; | |
1029 | ||
cc772ab7 MR |
1030 | if (dev->features & NETIF_F_IP_CSUM || |
1031 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) | |
0bbaf069 | 1032 | dev->hard_header_len += GMAC_FCB_LEN; |
1da177e4 | 1033 | |
46ceb60c SG |
1034 | /* Program the isrg regs only if number of grps > 1 */ |
1035 | if (priv->num_grps > 1) { | |
1036 | baddr = ®s->isrg0; | |
1037 | for (i = 0; i < priv->num_grps; i++) { | |
1038 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1039 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1040 | gfar_write(baddr, isrg); | |
1041 | baddr++; | |
1042 | isrg = 0x0; | |
1043 | } | |
1044 | } | |
1045 | ||
fba4ed03 | 1046 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1047 | * but, for_each_set_bit parses from right to left, which |
fba4ed03 | 1048 | * basically reverses the queue numbers */ |
46ceb60c SG |
1049 | for (i = 0; i< priv->num_grps; i++) { |
1050 | priv->gfargrp[i].tx_bit_map = reverse_bitmap( | |
1051 | priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1052 | priv->gfargrp[i].rx_bit_map = reverse_bitmap( | |
1053 | priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
1054 | } | |
1055 | ||
1056 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
1057 | * also assign queues to groups */ | |
1058 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { | |
1059 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
984b3f57 | 1060 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
46ceb60c SG |
1061 | priv->num_rx_queues) { |
1062 | priv->gfargrp[grp_idx].num_rx_queues++; | |
1063 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1064 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1065 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1066 | } | |
1067 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
984b3f57 | 1068 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
46ceb60c SG |
1069 | priv->num_tx_queues) { |
1070 | priv->gfargrp[grp_idx].num_tx_queues++; | |
1071 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1072 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1073 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1074 | } | |
1075 | priv->gfargrp[grp_idx].rstat = rstat; | |
1076 | priv->gfargrp[grp_idx].tstat = tstat; | |
1077 | rstat = tstat =0; | |
fba4ed03 | 1078 | } |
fba4ed03 SG |
1079 | |
1080 | gfar_write(®s->rqueue, rqueue); | |
1081 | gfar_write(®s->tqueue, tqueue); | |
1082 | ||
1da177e4 | 1083 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1084 | |
a12f801d | 1085 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1086 | for (i = 0; i < priv->num_tx_queues; i++) { |
1087 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1088 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1089 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1090 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1091 | } | |
a12f801d | 1092 | |
fba4ed03 SG |
1093 | for (i = 0; i < priv->num_rx_queues; i++) { |
1094 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1095 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1096 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1097 | } | |
1da177e4 | 1098 | |
1ccb8389 SG |
1099 | /* enable filer if using multiple RX queues*/ |
1100 | if(priv->num_rx_queues > 1) | |
1101 | priv->rx_filer_enable = 1; | |
0bbaf069 KG |
1102 | /* Enable most messages by default */ |
1103 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1104 | ||
d3eab82b TP |
1105 | /* Carrier starts down, phylib will bring it up */ |
1106 | netif_carrier_off(dev); | |
1107 | ||
1da177e4 LT |
1108 | err = register_netdev(dev); |
1109 | ||
1110 | if (err) { | |
1111 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
1112 | dev->name); | |
1113 | goto register_fail; | |
1114 | } | |
1115 | ||
2884e5cc AV |
1116 | device_init_wakeup(&dev->dev, |
1117 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
1118 | ||
c50a5d9a DH |
1119 | /* fill out IRQ number and name fields */ |
1120 | len_devname = strlen(dev->name); | |
46ceb60c SG |
1121 | for (i = 0; i < priv->num_grps; i++) { |
1122 | strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name, | |
1123 | len_devname); | |
1124 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
1125 | strncpy(&priv->gfargrp[i].int_name_tx[len_devname], | |
1126 | "_g", sizeof("_g")); | |
1127 | priv->gfargrp[i].int_name_tx[ | |
1128 | strlen(priv->gfargrp[i].int_name_tx)] = i+48; | |
1129 | strncpy(&priv->gfargrp[i].int_name_tx[strlen( | |
1130 | priv->gfargrp[i].int_name_tx)], | |
1131 | "_tx", sizeof("_tx") + 1); | |
1132 | ||
1133 | strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name, | |
1134 | len_devname); | |
1135 | strncpy(&priv->gfargrp[i].int_name_rx[len_devname], | |
1136 | "_g", sizeof("_g")); | |
1137 | priv->gfargrp[i].int_name_rx[ | |
1138 | strlen(priv->gfargrp[i].int_name_rx)] = i+48; | |
1139 | strncpy(&priv->gfargrp[i].int_name_rx[strlen( | |
1140 | priv->gfargrp[i].int_name_rx)], | |
1141 | "_rx", sizeof("_rx") + 1); | |
1142 | ||
1143 | strncpy(&priv->gfargrp[i].int_name_er[0], dev->name, | |
1144 | len_devname); | |
1145 | strncpy(&priv->gfargrp[i].int_name_er[len_devname], | |
1146 | "_g", sizeof("_g")); | |
1147 | priv->gfargrp[i].int_name_er[strlen( | |
1148 | priv->gfargrp[i].int_name_er)] = i+48; | |
1149 | strncpy(&priv->gfargrp[i].int_name_er[strlen(\ | |
1150 | priv->gfargrp[i].int_name_er)], | |
1151 | "_er", sizeof("_er") + 1); | |
1152 | } else | |
1153 | priv->gfargrp[i].int_name_tx[len_devname] = '\0'; | |
1154 | } | |
c50a5d9a | 1155 | |
7a8b3372 SG |
1156 | /* Initialize the filer table */ |
1157 | gfar_init_filer_table(priv); | |
1158 | ||
7f7f5316 AF |
1159 | /* Create all the sysfs files */ |
1160 | gfar_init_sysfs(dev); | |
1161 | ||
1da177e4 | 1162 | /* Print out the device info */ |
e174961c | 1163 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
1164 | |
1165 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 1166 | /* provided which set of benchmarks. */ |
1da177e4 | 1167 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
fba4ed03 | 1168 | for (i = 0; i < priv->num_rx_queues; i++) |
ddc01b3b | 1169 | printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n", |
fba4ed03 SG |
1170 | dev->name, i, priv->rx_queue[i]->rx_ring_size); |
1171 | for(i = 0; i < priv->num_tx_queues; i++) | |
ddc01b3b | 1172 | printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n", |
fba4ed03 | 1173 | dev->name, i, priv->tx_queue[i]->tx_ring_size); |
1da177e4 LT |
1174 | |
1175 | return 0; | |
1176 | ||
1177 | register_fail: | |
46ceb60c | 1178 | unmap_group_regs(priv); |
fba4ed03 SG |
1179 | free_tx_pointers(priv); |
1180 | free_rx_pointers(priv); | |
fe192a49 GL |
1181 | if (priv->phy_node) |
1182 | of_node_put(priv->phy_node); | |
1183 | if (priv->tbi_node) | |
1184 | of_node_put(priv->tbi_node); | |
1da177e4 | 1185 | free_netdev(dev); |
bb40dcbb | 1186 | return err; |
1da177e4 LT |
1187 | } |
1188 | ||
b31a1d8b | 1189 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 1190 | { |
b31a1d8b | 1191 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1192 | |
fe192a49 GL |
1193 | if (priv->phy_node) |
1194 | of_node_put(priv->phy_node); | |
1195 | if (priv->tbi_node) | |
1196 | of_node_put(priv->tbi_node); | |
1197 | ||
b31a1d8b | 1198 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1199 | |
d9d8e041 | 1200 | unregister_netdev(priv->ndev); |
46ceb60c | 1201 | unmap_group_regs(priv); |
4826857f | 1202 | free_netdev(priv->ndev); |
1da177e4 LT |
1203 | |
1204 | return 0; | |
1205 | } | |
1206 | ||
d87eb127 | 1207 | #ifdef CONFIG_PM |
be926fc4 AV |
1208 | |
1209 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1210 | { |
be926fc4 AV |
1211 | struct gfar_private *priv = dev_get_drvdata(dev); |
1212 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1213 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1214 | unsigned long flags; |
1215 | u32 tempval; | |
1216 | ||
1217 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1218 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1219 | |
be926fc4 | 1220 | netif_device_detach(ndev); |
d87eb127 | 1221 | |
be926fc4 | 1222 | if (netif_running(ndev)) { |
fba4ed03 SG |
1223 | |
1224 | local_irq_save(flags); | |
1225 | lock_tx_qs(priv); | |
1226 | lock_rx_qs(priv); | |
d87eb127 | 1227 | |
be926fc4 | 1228 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1229 | |
1230 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1231 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1232 | |
1233 | tempval &= ~MACCFG1_TX_EN; | |
1234 | ||
1235 | if (!magic_packet) | |
1236 | tempval &= ~MACCFG1_RX_EN; | |
1237 | ||
f4983704 | 1238 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1239 | |
fba4ed03 SG |
1240 | unlock_rx_qs(priv); |
1241 | unlock_tx_qs(priv); | |
1242 | local_irq_restore(flags); | |
d87eb127 | 1243 | |
46ceb60c | 1244 | disable_napi(priv); |
d87eb127 SW |
1245 | |
1246 | if (magic_packet) { | |
1247 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1248 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1249 | |
1250 | /* Enable Magic Packet mode */ | |
f4983704 | 1251 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1252 | tempval |= MACCFG2_MPEN; |
f4983704 | 1253 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1254 | } else { |
1255 | phy_stop(priv->phydev); | |
1256 | } | |
1257 | } | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
be926fc4 | 1262 | static int gfar_resume(struct device *dev) |
d87eb127 | 1263 | { |
be926fc4 AV |
1264 | struct gfar_private *priv = dev_get_drvdata(dev); |
1265 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1266 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1267 | unsigned long flags; |
1268 | u32 tempval; | |
1269 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1270 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1271 | |
be926fc4 AV |
1272 | if (!netif_running(ndev)) { |
1273 | netif_device_attach(ndev); | |
d87eb127 SW |
1274 | return 0; |
1275 | } | |
1276 | ||
1277 | if (!magic_packet && priv->phydev) | |
1278 | phy_start(priv->phydev); | |
1279 | ||
1280 | /* Disable Magic Packet mode, in case something | |
1281 | * else woke us up. | |
1282 | */ | |
fba4ed03 SG |
1283 | local_irq_save(flags); |
1284 | lock_tx_qs(priv); | |
1285 | lock_rx_qs(priv); | |
d87eb127 | 1286 | |
f4983704 | 1287 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1288 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1289 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1290 | |
be926fc4 | 1291 | gfar_start(ndev); |
d87eb127 | 1292 | |
fba4ed03 SG |
1293 | unlock_rx_qs(priv); |
1294 | unlock_tx_qs(priv); | |
1295 | local_irq_restore(flags); | |
d87eb127 | 1296 | |
be926fc4 AV |
1297 | netif_device_attach(ndev); |
1298 | ||
46ceb60c | 1299 | enable_napi(priv); |
be926fc4 AV |
1300 | |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int gfar_restore(struct device *dev) | |
1305 | { | |
1306 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1307 | struct net_device *ndev = priv->ndev; | |
1308 | ||
1309 | if (!netif_running(ndev)) | |
1310 | return 0; | |
1311 | ||
1312 | gfar_init_bds(ndev); | |
1313 | init_registers(ndev); | |
1314 | gfar_set_mac_address(ndev); | |
1315 | gfar_init_mac(ndev); | |
1316 | gfar_start(ndev); | |
1317 | ||
1318 | priv->oldlink = 0; | |
1319 | priv->oldspeed = 0; | |
1320 | priv->oldduplex = -1; | |
1321 | ||
1322 | if (priv->phydev) | |
1323 | phy_start(priv->phydev); | |
d87eb127 | 1324 | |
be926fc4 | 1325 | netif_device_attach(ndev); |
5ea681d4 | 1326 | enable_napi(priv); |
d87eb127 SW |
1327 | |
1328 | return 0; | |
1329 | } | |
be926fc4 AV |
1330 | |
1331 | static struct dev_pm_ops gfar_pm_ops = { | |
1332 | .suspend = gfar_suspend, | |
1333 | .resume = gfar_resume, | |
1334 | .freeze = gfar_suspend, | |
1335 | .thaw = gfar_resume, | |
1336 | .restore = gfar_restore, | |
1337 | }; | |
1338 | ||
1339 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1340 | ||
1341 | static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state) | |
1342 | { | |
1343 | return gfar_suspend(&ofdev->dev); | |
1344 | } | |
1345 | ||
1346 | static int gfar_legacy_resume(struct of_device *ofdev) | |
1347 | { | |
1348 | return gfar_resume(&ofdev->dev); | |
1349 | } | |
1350 | ||
d87eb127 | 1351 | #else |
be926fc4 AV |
1352 | |
1353 | #define GFAR_PM_OPS NULL | |
1354 | #define gfar_legacy_suspend NULL | |
1355 | #define gfar_legacy_resume NULL | |
1356 | ||
d87eb127 | 1357 | #endif |
1da177e4 | 1358 | |
e8a2b6a4 AF |
1359 | /* Reads the controller's registers to determine what interface |
1360 | * connects it to the PHY. | |
1361 | */ | |
1362 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1363 | { | |
1364 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1365 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1366 | u32 ecntrl; |
1367 | ||
f4983704 | 1368 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1369 | |
1370 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1371 | return PHY_INTERFACE_MODE_SGMII; | |
1372 | ||
1373 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1374 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1375 | return PHY_INTERFACE_MODE_RTBI; | |
1376 | else | |
1377 | return PHY_INTERFACE_MODE_TBI; | |
1378 | } | |
1379 | ||
1380 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
1381 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
1382 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 1383 | else { |
b31a1d8b | 1384 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
1385 | |
1386 | /* | |
1387 | * This isn't autodetected right now, so it must | |
1388 | * be set by the device tree or platform code. | |
1389 | */ | |
1390 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1391 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1392 | ||
e8a2b6a4 | 1393 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1394 | } |
e8a2b6a4 AF |
1395 | } |
1396 | ||
b31a1d8b | 1397 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1398 | return PHY_INTERFACE_MODE_GMII; |
1399 | ||
1400 | return PHY_INTERFACE_MODE_MII; | |
1401 | } | |
1402 | ||
1403 | ||
bb40dcbb AF |
1404 | /* Initializes driver's PHY state, and attaches to the PHY. |
1405 | * Returns 0 on success. | |
1da177e4 LT |
1406 | */ |
1407 | static int init_phy(struct net_device *dev) | |
1408 | { | |
1409 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1410 | uint gigabit_support = |
b31a1d8b | 1411 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1412 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1413 | phy_interface_t interface; |
1da177e4 LT |
1414 | |
1415 | priv->oldlink = 0; | |
1416 | priv->oldspeed = 0; | |
1417 | priv->oldduplex = -1; | |
1418 | ||
e8a2b6a4 AF |
1419 | interface = gfar_get_interface(dev); |
1420 | ||
1db780f8 AV |
1421 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1422 | interface); | |
1423 | if (!priv->phydev) | |
1424 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1425 | interface); | |
1426 | if (!priv->phydev) { | |
1427 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1428 | return -ENODEV; | |
fe192a49 | 1429 | } |
1da177e4 | 1430 | |
d3c12873 KJ |
1431 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1432 | gfar_configure_serdes(dev); | |
1433 | ||
bb40dcbb | 1434 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1435 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1436 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1437 | |
1438 | return 0; | |
1da177e4 LT |
1439 | } |
1440 | ||
d0313587 PG |
1441 | /* |
1442 | * Initialize TBI PHY interface for communicating with the | |
1443 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
1444 | * through the MDIO bus on each controller, treating it as a | |
1445 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1446 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1447 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1448 | * value doesn't matter, as there are no other PHYs on the bus. | |
1449 | */ | |
d3c12873 KJ |
1450 | static void gfar_configure_serdes(struct net_device *dev) |
1451 | { | |
1452 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1453 | struct phy_device *tbiphy; |
1454 | ||
1455 | if (!priv->tbi_node) { | |
1456 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1457 | "device tree specify a tbi-handle\n"); | |
1458 | return; | |
1459 | } | |
c132419e | 1460 | |
fe192a49 GL |
1461 | tbiphy = of_phy_find_device(priv->tbi_node); |
1462 | if (!tbiphy) { | |
1463 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1464 | return; |
1465 | } | |
d3c12873 | 1466 | |
b31a1d8b AF |
1467 | /* |
1468 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
1469 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1470 | * everything for us? Resetting it takes the link down and requires | |
1471 | * several seconds for it to come back. | |
1472 | */ | |
fe192a49 | 1473 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1474 | return; |
d3c12873 | 1475 | |
d0313587 | 1476 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1477 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1478 | |
fe192a49 | 1479 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
1480 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1481 | ADVERTISE_1000XPSE_ASYM); | |
1482 | ||
fe192a49 | 1483 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
1484 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
1485 | } | |
1486 | ||
1da177e4 LT |
1487 | static void init_registers(struct net_device *dev) |
1488 | { | |
1489 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1490 | struct gfar __iomem *regs = NULL; |
46ceb60c | 1491 | int i = 0; |
1da177e4 | 1492 | |
46ceb60c SG |
1493 | for (i = 0; i < priv->num_grps; i++) { |
1494 | regs = priv->gfargrp[i].regs; | |
1495 | /* Clear IEVENT */ | |
1496 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1497 | |
46ceb60c SG |
1498 | /* Initialize IMASK */ |
1499 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1500 | } | |
1da177e4 | 1501 | |
46ceb60c | 1502 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1503 | /* Init hash registers to zero */ |
f4983704 SG |
1504 | gfar_write(®s->igaddr0, 0); |
1505 | gfar_write(®s->igaddr1, 0); | |
1506 | gfar_write(®s->igaddr2, 0); | |
1507 | gfar_write(®s->igaddr3, 0); | |
1508 | gfar_write(®s->igaddr4, 0); | |
1509 | gfar_write(®s->igaddr5, 0); | |
1510 | gfar_write(®s->igaddr6, 0); | |
1511 | gfar_write(®s->igaddr7, 0); | |
1512 | ||
1513 | gfar_write(®s->gaddr0, 0); | |
1514 | gfar_write(®s->gaddr1, 0); | |
1515 | gfar_write(®s->gaddr2, 0); | |
1516 | gfar_write(®s->gaddr3, 0); | |
1517 | gfar_write(®s->gaddr4, 0); | |
1518 | gfar_write(®s->gaddr5, 0); | |
1519 | gfar_write(®s->gaddr6, 0); | |
1520 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1521 | |
1da177e4 | 1522 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1523 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1524 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1525 | |
1526 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1527 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1528 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1529 | } |
1530 | ||
1531 | /* Initialize the max receive buffer length */ | |
f4983704 | 1532 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1533 | |
1da177e4 | 1534 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1535 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1536 | } |
1537 | ||
0bbaf069 KG |
1538 | |
1539 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1540 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1541 | { |
1542 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1543 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1544 | u32 tempval; |
46ceb60c | 1545 | int i = 0; |
1da177e4 | 1546 | |
46ceb60c SG |
1547 | for (i = 0; i < priv->num_grps; i++) { |
1548 | regs = priv->gfargrp[i].regs; | |
1549 | /* Mask all interrupts */ | |
1550 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1551 | |
46ceb60c SG |
1552 | /* Clear all interrupts */ |
1553 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1554 | } | |
1da177e4 | 1555 | |
46ceb60c | 1556 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1557 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1558 | tempval = gfar_read(®s->dmactrl); |
1da177e4 LT |
1559 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) |
1560 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
1561 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
f4983704 | 1562 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1563 | |
f4983704 | 1564 | while (!(gfar_read(®s->ievent) & |
1da177e4 LT |
1565 | (IEVENT_GRSC | IEVENT_GTSC))) |
1566 | cpu_relax(); | |
1567 | } | |
d87eb127 | 1568 | } |
d87eb127 SW |
1569 | |
1570 | /* Halt the receive and transmit queues */ | |
1571 | void gfar_halt(struct net_device *dev) | |
1572 | { | |
1573 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1574 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1575 | u32 tempval; |
1da177e4 | 1576 | |
2a54adc3 SW |
1577 | gfar_halt_nodisable(dev); |
1578 | ||
1da177e4 LT |
1579 | /* Disable Rx and Tx */ |
1580 | tempval = gfar_read(®s->maccfg1); | |
1581 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1582 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1583 | } |
1584 | ||
46ceb60c SG |
1585 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1586 | { | |
1587 | free_irq(grp->interruptError, grp); | |
1588 | free_irq(grp->interruptTransmit, grp); | |
1589 | free_irq(grp->interruptReceive, grp); | |
1590 | } | |
1591 | ||
0bbaf069 KG |
1592 | void stop_gfar(struct net_device *dev) |
1593 | { | |
1594 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1595 | unsigned long flags; |
46ceb60c | 1596 | int i; |
0bbaf069 | 1597 | |
bb40dcbb AF |
1598 | phy_stop(priv->phydev); |
1599 | ||
a12f801d | 1600 | |
0bbaf069 | 1601 | /* Lock it down */ |
fba4ed03 SG |
1602 | local_irq_save(flags); |
1603 | lock_tx_qs(priv); | |
1604 | lock_rx_qs(priv); | |
0bbaf069 | 1605 | |
0bbaf069 | 1606 | gfar_halt(dev); |
1da177e4 | 1607 | |
fba4ed03 SG |
1608 | unlock_rx_qs(priv); |
1609 | unlock_tx_qs(priv); | |
1610 | local_irq_restore(flags); | |
1da177e4 LT |
1611 | |
1612 | /* Free the IRQs */ | |
b31a1d8b | 1613 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1614 | for (i = 0; i < priv->num_grps; i++) |
1615 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1616 | } else { |
46ceb60c SG |
1617 | for (i = 0; i < priv->num_grps; i++) |
1618 | free_irq(priv->gfargrp[i].interruptTransmit, | |
1619 | &priv->gfargrp[i]); | |
1da177e4 LT |
1620 | } |
1621 | ||
1622 | free_skb_resources(priv); | |
1da177e4 LT |
1623 | } |
1624 | ||
fba4ed03 | 1625 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1626 | { |
1da177e4 | 1627 | struct txbd8 *txbdp; |
fba4ed03 | 1628 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1629 | int i, j; |
1da177e4 | 1630 | |
a12f801d | 1631 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1632 | |
a12f801d SG |
1633 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1634 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1635 | continue; |
1da177e4 | 1636 | |
4826857f | 1637 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
1638 | txbdp->length, DMA_TO_DEVICE); |
1639 | txbdp->lstatus = 0; | |
fba4ed03 SG |
1640 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
1641 | j++) { | |
4669bc90 | 1642 | txbdp++; |
4826857f | 1643 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 1644 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1645 | } |
ad5da7ab | 1646 | txbdp++; |
a12f801d SG |
1647 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1648 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1649 | } |
a12f801d | 1650 | kfree(tx_queue->tx_skbuff); |
fba4ed03 | 1651 | } |
1da177e4 | 1652 | |
fba4ed03 SG |
1653 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1654 | { | |
1655 | struct rxbd8 *rxbdp; | |
1656 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1657 | int i; | |
1da177e4 | 1658 | |
fba4ed03 | 1659 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1660 | |
a12f801d SG |
1661 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1662 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 SG |
1663 | dma_unmap_single(&priv->ofdev->dev, |
1664 | rxbdp->bufPtr, priv->rx_buffer_size, | |
e69edd21 | 1665 | DMA_FROM_DEVICE); |
a12f801d SG |
1666 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1667 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1668 | } |
e69edd21 AV |
1669 | rxbdp->lstatus = 0; |
1670 | rxbdp->bufPtr = 0; | |
1671 | rxbdp++; | |
1da177e4 | 1672 | } |
a12f801d | 1673 | kfree(rx_queue->rx_skbuff); |
fba4ed03 | 1674 | } |
e69edd21 | 1675 | |
fba4ed03 SG |
1676 | /* If there are any tx skbs or rx skbs still around, free them. |
1677 | * Then free tx_skbuff and rx_skbuff */ | |
1678 | static void free_skb_resources(struct gfar_private *priv) | |
1679 | { | |
1680 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1681 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1682 | int i; | |
1683 | ||
1684 | /* Go through all the buffer descriptors and free their data buffers */ | |
1685 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1686 | tx_queue = priv->tx_queue[i]; | |
7c0d10d3 | 1687 | if(tx_queue->tx_skbuff) |
fba4ed03 SG |
1688 | free_skb_tx_queue(tx_queue); |
1689 | } | |
1690 | ||
1691 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1692 | rx_queue = priv->rx_queue[i]; | |
7c0d10d3 | 1693 | if(rx_queue->rx_skbuff) |
fba4ed03 SG |
1694 | free_skb_rx_queue(rx_queue); |
1695 | } | |
1696 | ||
1697 | dma_free_coherent(&priv->ofdev->dev, | |
1698 | sizeof(struct txbd8) * priv->total_tx_ring_size + | |
1699 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1700 | priv->tx_queue[0]->tx_bd_base, | |
1701 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1702 | } |
1703 | ||
0bbaf069 KG |
1704 | void gfar_start(struct net_device *dev) |
1705 | { | |
1706 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1707 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1708 | u32 tempval; |
46ceb60c | 1709 | int i = 0; |
0bbaf069 KG |
1710 | |
1711 | /* Enable Rx and Tx in MACCFG1 */ | |
1712 | tempval = gfar_read(®s->maccfg1); | |
1713 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1714 | gfar_write(®s->maccfg1, tempval); | |
1715 | ||
1716 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1717 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1718 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1719 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1720 | |
0bbaf069 | 1721 | /* Make sure we aren't stopped */ |
f4983704 | 1722 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1723 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1724 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1725 | |
46ceb60c SG |
1726 | for (i = 0; i < priv->num_grps; i++) { |
1727 | regs = priv->gfargrp[i].regs; | |
1728 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1729 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1730 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1731 | /* Unmask the interrupts we look for */ | |
1732 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1733 | } | |
12dea57b DH |
1734 | |
1735 | dev->trans_start = jiffies; | |
0bbaf069 KG |
1736 | } |
1737 | ||
46ceb60c | 1738 | void gfar_configure_coalescing(struct gfar_private *priv, |
18294ad1 | 1739 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1740 | { |
46ceb60c | 1741 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1742 | u32 __iomem *baddr; |
46ceb60c | 1743 | int i = 0; |
1da177e4 | 1744 | |
46ceb60c SG |
1745 | /* Backward compatible case ---- even if we enable |
1746 | * multiple queues, there's only single reg to program | |
1747 | */ | |
1748 | gfar_write(®s->txic, 0); | |
1749 | if(likely(priv->tx_queue[0]->txcoalescing)) | |
1750 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1da177e4 | 1751 | |
46ceb60c SG |
1752 | gfar_write(®s->rxic, 0); |
1753 | if(unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1754 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
815b97c6 | 1755 | |
46ceb60c SG |
1756 | if (priv->mode == MQ_MG_MODE) { |
1757 | baddr = ®s->txic0; | |
984b3f57 | 1758 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
46ceb60c SG |
1759 | if (likely(priv->tx_queue[i]->txcoalescing)) { |
1760 | gfar_write(baddr + i, 0); | |
1761 | gfar_write(baddr + i, priv->tx_queue[i]->txic); | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | baddr = ®s->rxic0; | |
984b3f57 | 1766 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
46ceb60c SG |
1767 | if (likely(priv->rx_queue[i]->rxcoalescing)) { |
1768 | gfar_write(baddr + i, 0); | |
1769 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); | |
1770 | } | |
1771 | } | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1776 | { | |
1777 | struct gfar_private *priv = grp->priv; | |
1778 | struct net_device *dev = priv->ndev; | |
1779 | int err; | |
1da177e4 | 1780 | |
1da177e4 LT |
1781 | /* If the device has multiple interrupts, register for |
1782 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1783 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1784 | /* Install our interrupt handlers for Error, |
1da177e4 | 1785 | * Transmit, and Receive */ |
46ceb60c SG |
1786 | if ((err = request_irq(grp->interruptError, gfar_error, 0, |
1787 | grp->int_name_er,grp)) < 0) { | |
0bbaf069 | 1788 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1789 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1790 | dev->name, grp->interruptError); | |
1791 | ||
1792 | goto err_irq_fail; | |
1da177e4 LT |
1793 | } |
1794 | ||
46ceb60c SG |
1795 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
1796 | 0, grp->int_name_tx, grp)) < 0) { | |
0bbaf069 | 1797 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1798 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1799 | dev->name, grp->interruptTransmit); | |
1da177e4 LT |
1800 | goto tx_irq_fail; |
1801 | } | |
1802 | ||
46ceb60c SG |
1803 | if ((err = request_irq(grp->interruptReceive, gfar_receive, 0, |
1804 | grp->int_name_rx, grp)) < 0) { | |
0bbaf069 | 1805 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1806 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1807 | dev->name, grp->interruptReceive); | |
1da177e4 LT |
1808 | goto rx_irq_fail; |
1809 | } | |
1810 | } else { | |
46ceb60c SG |
1811 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0, |
1812 | grp->int_name_tx, grp)) < 0) { | |
0bbaf069 | 1813 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1814 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1815 | dev->name, grp->interruptTransmit); | |
1da177e4 LT |
1816 | goto err_irq_fail; |
1817 | } | |
1818 | } | |
1819 | ||
46ceb60c SG |
1820 | return 0; |
1821 | ||
1822 | rx_irq_fail: | |
1823 | free_irq(grp->interruptTransmit, grp); | |
1824 | tx_irq_fail: | |
1825 | free_irq(grp->interruptError, grp); | |
1826 | err_irq_fail: | |
1827 | return err; | |
1828 | ||
1829 | } | |
1830 | ||
1831 | /* Bring the controller up and running */ | |
1832 | int startup_gfar(struct net_device *ndev) | |
1833 | { | |
1834 | struct gfar_private *priv = netdev_priv(ndev); | |
1835 | struct gfar __iomem *regs = NULL; | |
1836 | int err, i, j; | |
1837 | ||
1838 | for (i = 0; i < priv->num_grps; i++) { | |
1839 | regs= priv->gfargrp[i].regs; | |
1840 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1841 | } | |
1842 | ||
1843 | regs= priv->gfargrp[0].regs; | |
1844 | err = gfar_alloc_skb_resources(ndev); | |
1845 | if (err) | |
1846 | return err; | |
1847 | ||
1848 | gfar_init_mac(ndev); | |
1849 | ||
1850 | for (i = 0; i < priv->num_grps; i++) { | |
1851 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1852 | if (err) { | |
1853 | for (j = 0; j < i; j++) | |
1854 | free_grp_irqs(&priv->gfargrp[j]); | |
1855 | goto irq_fail; | |
1856 | } | |
1857 | } | |
1858 | ||
7f7f5316 | 1859 | /* Start the controller */ |
ccc05c6e | 1860 | gfar_start(ndev); |
1da177e4 | 1861 | |
826aa4a0 AV |
1862 | phy_start(priv->phydev); |
1863 | ||
46ceb60c SG |
1864 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1865 | ||
1da177e4 LT |
1866 | return 0; |
1867 | ||
46ceb60c | 1868 | irq_fail: |
e69edd21 | 1869 | free_skb_resources(priv); |
1da177e4 LT |
1870 | return err; |
1871 | } | |
1872 | ||
1873 | /* Called when something needs to use the ethernet device */ | |
1874 | /* Returns 0 for success. */ | |
1875 | static int gfar_enet_open(struct net_device *dev) | |
1876 | { | |
94e8cc35 | 1877 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1878 | int err; |
1879 | ||
46ceb60c | 1880 | enable_napi(priv); |
bea3348e | 1881 | |
0fd56bb5 AF |
1882 | skb_queue_head_init(&priv->rx_recycle); |
1883 | ||
1da177e4 LT |
1884 | /* Initialize a bunch of registers */ |
1885 | init_registers(dev); | |
1886 | ||
1887 | gfar_set_mac_address(dev); | |
1888 | ||
1889 | err = init_phy(dev); | |
1890 | ||
a12f801d | 1891 | if (err) { |
46ceb60c | 1892 | disable_napi(priv); |
1da177e4 | 1893 | return err; |
bea3348e | 1894 | } |
1da177e4 LT |
1895 | |
1896 | err = startup_gfar(dev); | |
db0e8e3f | 1897 | if (err) { |
46ceb60c | 1898 | disable_napi(priv); |
db0e8e3f AV |
1899 | return err; |
1900 | } | |
1da177e4 | 1901 | |
fba4ed03 | 1902 | netif_tx_start_all_queues(dev); |
1da177e4 | 1903 | |
2884e5cc AV |
1904 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1905 | ||
1da177e4 LT |
1906 | return err; |
1907 | } | |
1908 | ||
54dc79fe | 1909 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1910 | { |
54dc79fe | 1911 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1912 | |
1913 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1914 | |
0bbaf069 KG |
1915 | return fcb; |
1916 | } | |
1917 | ||
1918 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1919 | { | |
7f7f5316 | 1920 | u8 flags = 0; |
0bbaf069 KG |
1921 | |
1922 | /* If we're here, it's a IP packet with a TCP or UDP | |
1923 | * payload. We set it to checksum, using a pseudo-header | |
1924 | * we provide | |
1925 | */ | |
7f7f5316 | 1926 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1927 | |
7f7f5316 AF |
1928 | /* Tell the controller what the protocol is */ |
1929 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1930 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1931 | flags |= TXFCB_UDP; |
4bedb452 | 1932 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1933 | } else |
8da32de5 | 1934 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1935 | |
1936 | /* l3os is the distance between the start of the | |
1937 | * frame (skb->data) and the start of the IP hdr. | |
1938 | * l4os is the distance between the start of the | |
1939 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1940 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1941 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1942 | |
7f7f5316 | 1943 | fcb->flags = flags; |
0bbaf069 KG |
1944 | } |
1945 | ||
7f7f5316 | 1946 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1947 | { |
7f7f5316 | 1948 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1949 | fcb->vlctl = vlan_tx_tag_get(skb); |
1950 | } | |
1951 | ||
4669bc90 DH |
1952 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1953 | struct txbd8 *base, int ring_size) | |
1954 | { | |
1955 | struct txbd8 *new_bd = bdp + stride; | |
1956 | ||
1957 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1958 | } | |
1959 | ||
1960 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1961 | int ring_size) | |
1962 | { | |
1963 | return skip_txbd(bdp, 1, base, ring_size); | |
1964 | } | |
1965 | ||
1da177e4 LT |
1966 | /* This is called by the kernel when a frame is ready for transmission. */ |
1967 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1968 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1969 | { | |
1970 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 1971 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 1972 | struct netdev_queue *txq; |
f4983704 | 1973 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 1974 | struct txfcb *fcb = NULL; |
4669bc90 | 1975 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1976 | u32 lstatus; |
fba4ed03 | 1977 | int i, rq = 0; |
4669bc90 | 1978 | u32 bufaddr; |
fef6108d | 1979 | unsigned long flags; |
4669bc90 DH |
1980 | unsigned int nr_frags, length; |
1981 | ||
fba4ed03 SG |
1982 | |
1983 | rq = skb->queue_mapping; | |
1984 | tx_queue = priv->tx_queue[rq]; | |
1985 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 1986 | base = tx_queue->tx_bd_base; |
46ceb60c | 1987 | regs = tx_queue->grp->regs; |
4669bc90 | 1988 | |
5b28beaf LY |
1989 | /* make space for additional header when fcb is needed */ |
1990 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
1991 | (priv->vlgrp && vlan_tx_tag_present(skb))) && | |
1992 | (skb_headroom(skb) < GMAC_FCB_LEN)) { | |
54dc79fe SH |
1993 | struct sk_buff *skb_new; |
1994 | ||
1995 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
1996 | if (!skb_new) { | |
1997 | dev->stats.tx_errors++; | |
bd14ba84 | 1998 | kfree_skb(skb); |
54dc79fe SH |
1999 | return NETDEV_TX_OK; |
2000 | } | |
2001 | kfree_skb(skb); | |
2002 | skb = skb_new; | |
2003 | } | |
2004 | ||
4669bc90 DH |
2005 | /* total number of fragments in the SKB */ |
2006 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2007 | ||
4669bc90 | 2008 | /* check if there is space to queue this packet */ |
a12f801d | 2009 | if ((nr_frags+1) > tx_queue->num_txbdfree) { |
4669bc90 | 2010 | /* no space, stop the queue */ |
fba4ed03 | 2011 | netif_tx_stop_queue(txq); |
4669bc90 | 2012 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2013 | return NETDEV_TX_BUSY; |
2014 | } | |
1da177e4 LT |
2015 | |
2016 | /* Update transmit stats */ | |
a7f38041 SG |
2017 | txq->tx_bytes += skb->len; |
2018 | txq->tx_packets ++; | |
1da177e4 | 2019 | |
a12f801d | 2020 | txbdp = txbdp_start = tx_queue->cur_tx; |
1da177e4 | 2021 | |
4669bc90 DH |
2022 | if (nr_frags == 0) { |
2023 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
2024 | } else { | |
2025 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2026 | for (i = 0; i < nr_frags; i++) { | |
2027 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2028 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2029 | |
2030 | length = skb_shinfo(skb)->frags[i].size; | |
2031 | ||
2032 | lstatus = txbdp->lstatus | length | | |
2033 | BD_LFLAG(TXBD_READY); | |
2034 | ||
2035 | /* Handle the last BD specially */ | |
2036 | if (i == nr_frags - 1) | |
2037 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2038 | |
4826857f | 2039 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
2040 | skb_shinfo(skb)->frags[i].page, |
2041 | skb_shinfo(skb)->frags[i].page_offset, | |
2042 | length, | |
2043 | DMA_TO_DEVICE); | |
2044 | ||
2045 | /* set the TxBD length and buffer pointer */ | |
2046 | txbdp->bufPtr = bufaddr; | |
2047 | txbdp->lstatus = lstatus; | |
2048 | } | |
2049 | ||
2050 | lstatus = txbdp_start->lstatus; | |
2051 | } | |
1da177e4 | 2052 | |
0bbaf069 | 2053 | /* Set up checksumming */ |
12dea57b | 2054 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe SH |
2055 | fcb = gfar_add_fcb(skb); |
2056 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2057 | gfar_tx_checksum(skb, fcb); | |
0bbaf069 KG |
2058 | } |
2059 | ||
77ecaf2d | 2060 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2061 | if (unlikely(NULL == fcb)) { |
2062 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2063 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2064 | } |
54dc79fe SH |
2065 | |
2066 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2067 | } |
2068 | ||
4669bc90 | 2069 | /* setup the TxBD length and buffer pointer for the first BD */ |
4826857f | 2070 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 2071 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2072 | |
4669bc90 | 2073 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 2074 | |
a3bc1f11 AV |
2075 | /* |
2076 | * We can work in parallel with gfar_clean_tx_ring(), except | |
2077 | * when modifying num_txbdfree. Note that we didn't grab the lock | |
2078 | * when we were reading the num_txbdfree and checking for available | |
2079 | * space, that's because outside of this function it can only grow, | |
2080 | * and once we've got needed space, it cannot suddenly disappear. | |
2081 | * | |
2082 | * The lock also protects us from gfar_error(), which can modify | |
2083 | * regs->tstat and thus retrigger the transfers, which is why we | |
2084 | * also must grab the lock before setting ready bit for the first | |
2085 | * to be transmitted BD. | |
2086 | */ | |
2087 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2088 | ||
4669bc90 DH |
2089 | /* |
2090 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
2091 | * semantics (it requires synchronization between cacheable and |
2092 | * uncacheable mappings, which eieio doesn't provide and which we | |
2093 | * don't need), thus requiring a more expensive sync instruction. At | |
2094 | * some point, the set of architecture-independent barrier functions | |
2095 | * should be expanded to include weaker barriers. | |
2096 | */ | |
3b6330ce | 2097 | eieio(); |
7f7f5316 | 2098 | |
4669bc90 DH |
2099 | txbdp_start->lstatus = lstatus; |
2100 | ||
0eddba52 AV |
2101 | eieio(); /* force lstatus write before tx_skbuff */ |
2102 | ||
2103 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2104 | ||
4669bc90 DH |
2105 | /* Update the current skb pointer to the next entry we will use |
2106 | * (wrapping if necessary) */ | |
a12f801d SG |
2107 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
2108 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); | |
4669bc90 | 2109 | |
a12f801d | 2110 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2111 | |
2112 | /* reduce TxBD free count */ | |
a12f801d | 2113 | tx_queue->num_txbdfree -= (nr_frags + 1); |
4669bc90 DH |
2114 | |
2115 | dev->trans_start = jiffies; | |
1da177e4 LT |
2116 | |
2117 | /* If the next BD still needs to be cleaned up, then the bds | |
2118 | are full. We need to tell the kernel to stop sending us stuff. */ | |
a12f801d | 2119 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2120 | netif_tx_stop_queue(txq); |
1da177e4 | 2121 | |
09f75cd7 | 2122 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2123 | } |
2124 | ||
1da177e4 | 2125 | /* Tell the DMA to go go go */ |
fba4ed03 | 2126 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2127 | |
2128 | /* Unlock priv */ | |
a12f801d | 2129 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2130 | |
54dc79fe | 2131 | return NETDEV_TX_OK; |
1da177e4 LT |
2132 | } |
2133 | ||
2134 | /* Stops the kernel queue, and halts the controller */ | |
2135 | static int gfar_close(struct net_device *dev) | |
2136 | { | |
2137 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2138 | |
46ceb60c | 2139 | disable_napi(priv); |
bea3348e | 2140 | |
0fd56bb5 | 2141 | skb_queue_purge(&priv->rx_recycle); |
ab939905 | 2142 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2143 | stop_gfar(dev); |
2144 | ||
bb40dcbb AF |
2145 | /* Disconnect from the PHY */ |
2146 | phy_disconnect(priv->phydev); | |
2147 | priv->phydev = NULL; | |
1da177e4 | 2148 | |
fba4ed03 | 2149 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2150 | |
2151 | return 0; | |
2152 | } | |
2153 | ||
1da177e4 | 2154 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2155 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2156 | { |
7f7f5316 | 2157 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2158 | |
2159 | return 0; | |
2160 | } | |
2161 | ||
2162 | ||
0bbaf069 KG |
2163 | /* Enables and disables VLAN insertion/extraction */ |
2164 | static void gfar_vlan_rx_register(struct net_device *dev, | |
2165 | struct vlan_group *grp) | |
2166 | { | |
2167 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2168 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2169 | unsigned long flags; |
2170 | u32 tempval; | |
2171 | ||
46ceb60c | 2172 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2173 | local_irq_save(flags); |
2174 | lock_rx_qs(priv); | |
0bbaf069 | 2175 | |
cd1f55a5 | 2176 | priv->vlgrp = grp; |
0bbaf069 KG |
2177 | |
2178 | if (grp) { | |
2179 | /* Enable VLAN tag insertion */ | |
f4983704 | 2180 | tempval = gfar_read(®s->tctrl); |
0bbaf069 KG |
2181 | tempval |= TCTRL_VLINS; |
2182 | ||
f4983704 | 2183 | gfar_write(®s->tctrl, tempval); |
6aa20a22 | 2184 | |
0bbaf069 | 2185 | /* Enable VLAN tag extraction */ |
f4983704 | 2186 | tempval = gfar_read(®s->rctrl); |
77ecaf2d | 2187 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
f4983704 | 2188 | gfar_write(®s->rctrl, tempval); |
0bbaf069 KG |
2189 | } else { |
2190 | /* Disable VLAN tag insertion */ | |
f4983704 | 2191 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2192 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2193 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2194 | |
2195 | /* Disable VLAN tag extraction */ | |
f4983704 | 2196 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2197 | tempval &= ~RCTRL_VLEX; |
77ecaf2d DH |
2198 | /* If parse is no longer required, then disable parser */ |
2199 | if (tempval & RCTRL_REQ_PARSER) | |
2200 | tempval |= RCTRL_PRSDEP_INIT; | |
2201 | else | |
2202 | tempval &= ~RCTRL_PRSDEP_INIT; | |
f4983704 | 2203 | gfar_write(®s->rctrl, tempval); |
0bbaf069 KG |
2204 | } |
2205 | ||
77ecaf2d DH |
2206 | gfar_change_mtu(dev, dev->mtu); |
2207 | ||
fba4ed03 SG |
2208 | unlock_rx_qs(priv); |
2209 | local_irq_restore(flags); | |
0bbaf069 KG |
2210 | } |
2211 | ||
1da177e4 LT |
2212 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2213 | { | |
2214 | int tempsize, tempval; | |
2215 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2216 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2217 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2218 | int frame_size = new_mtu + ETH_HLEN; |
2219 | ||
77ecaf2d | 2220 | if (priv->vlgrp) |
faa89577 | 2221 | frame_size += VLAN_HLEN; |
0bbaf069 | 2222 | |
1da177e4 | 2223 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
2224 | if (netif_msg_drv(priv)) |
2225 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
2226 | dev->name); | |
1da177e4 LT |
2227 | return -EINVAL; |
2228 | } | |
2229 | ||
77ecaf2d DH |
2230 | if (gfar_uses_fcb(priv)) |
2231 | frame_size += GMAC_FCB_LEN; | |
2232 | ||
2233 | frame_size += priv->padding; | |
2234 | ||
1da177e4 LT |
2235 | tempsize = |
2236 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
2237 | INCREMENTAL_BUFFER_SIZE; | |
2238 | ||
2239 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 2240 | * stopped, and we changed something */ |
1da177e4 LT |
2241 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2242 | stop_gfar(dev); | |
2243 | ||
2244 | priv->rx_buffer_size = tempsize; | |
2245 | ||
2246 | dev->mtu = new_mtu; | |
2247 | ||
f4983704 SG |
2248 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2249 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2250 | |
2251 | /* If the mtu is larger than the max size for standard | |
2252 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
2253 | * to allow huge frames, and to check the length */ | |
f4983704 | 2254 | tempval = gfar_read(®s->maccfg2); |
1da177e4 LT |
2255 | |
2256 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
2257 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2258 | else | |
2259 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2260 | ||
f4983704 | 2261 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2262 | |
2263 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2264 | startup_gfar(dev); | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | ||
ab939905 | 2269 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2270 | * transmitted after a set amount of time. |
2271 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2272 | * starting over will fix the problem. |
2273 | */ | |
2274 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2275 | { |
ab939905 SS |
2276 | struct gfar_private *priv = container_of(work, struct gfar_private, |
2277 | reset_task); | |
4826857f | 2278 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2279 | |
2280 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2281 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2282 | stop_gfar(dev); |
2283 | startup_gfar(dev); | |
fba4ed03 | 2284 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2285 | } |
2286 | ||
263ba320 | 2287 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2288 | } |
2289 | ||
ab939905 SS |
2290 | static void gfar_timeout(struct net_device *dev) |
2291 | { | |
2292 | struct gfar_private *priv = netdev_priv(dev); | |
2293 | ||
2294 | dev->stats.tx_errors++; | |
2295 | schedule_work(&priv->reset_task); | |
2296 | } | |
2297 | ||
1da177e4 | 2298 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2299 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2300 | { |
a12f801d | 2301 | struct net_device *dev = tx_queue->dev; |
d080cd63 | 2302 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2303 | struct gfar_priv_rx_q *rx_queue = NULL; |
4669bc90 DH |
2304 | struct txbd8 *bdp; |
2305 | struct txbd8 *lbdp = NULL; | |
a12f801d | 2306 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2307 | struct sk_buff *skb; |
2308 | int skb_dirtytx; | |
a12f801d | 2309 | int tx_ring_size = tx_queue->tx_ring_size; |
4669bc90 DH |
2310 | int frags = 0; |
2311 | int i; | |
d080cd63 | 2312 | int howmany = 0; |
4669bc90 | 2313 | u32 lstatus; |
1da177e4 | 2314 | |
fba4ed03 | 2315 | rx_queue = priv->rx_queue[tx_queue->qindex]; |
a12f801d SG |
2316 | bdp = tx_queue->dirty_tx; |
2317 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2318 | |
a12f801d | 2319 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2320 | unsigned long flags; |
2321 | ||
4669bc90 DH |
2322 | frags = skb_shinfo(skb)->nr_frags; |
2323 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 2324 | |
4669bc90 | 2325 | lstatus = lbdp->lstatus; |
1da177e4 | 2326 | |
4669bc90 DH |
2327 | /* Only clean completed frames */ |
2328 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
2329 | (lstatus & BD_LENGTH_MASK)) | |
2330 | break; | |
2331 | ||
4826857f | 2332 | dma_unmap_single(&priv->ofdev->dev, |
4669bc90 DH |
2333 | bdp->bufPtr, |
2334 | bdp->length, | |
2335 | DMA_TO_DEVICE); | |
81183059 | 2336 | |
4669bc90 DH |
2337 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2338 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2339 | |
4669bc90 | 2340 | for (i = 0; i < frags; i++) { |
4826857f | 2341 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
2342 | bdp->bufPtr, |
2343 | bdp->length, | |
2344 | DMA_TO_DEVICE); | |
2345 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2346 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2347 | } | |
1da177e4 | 2348 | |
0fd56bb5 AF |
2349 | /* |
2350 | * If there's room in the queue (limit it to rx_buffer_size) | |
2351 | * we add this skb back into the pool, if it's the right size | |
2352 | */ | |
a12f801d | 2353 | if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size && |
0fd56bb5 AF |
2354 | skb_recycle_check(skb, priv->rx_buffer_size + |
2355 | RXBUF_ALIGNMENT)) | |
2356 | __skb_queue_head(&priv->rx_recycle, skb); | |
2357 | else | |
2358 | dev_kfree_skb_any(skb); | |
2359 | ||
a12f801d | 2360 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2361 | |
4669bc90 DH |
2362 | skb_dirtytx = (skb_dirtytx + 1) & |
2363 | TX_RING_MOD_MASK(tx_ring_size); | |
2364 | ||
2365 | howmany++; | |
a3bc1f11 | 2366 | spin_lock_irqsave(&tx_queue->txlock, flags); |
a12f801d | 2367 | tx_queue->num_txbdfree += frags + 1; |
a3bc1f11 | 2368 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2369 | } |
1da177e4 | 2370 | |
4669bc90 | 2371 | /* If we freed a buffer, we can restart transmission, if necessary */ |
fba4ed03 SG |
2372 | if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree) |
2373 | netif_wake_subqueue(dev, tx_queue->qindex); | |
1da177e4 | 2374 | |
4669bc90 | 2375 | /* Update dirty indicators */ |
a12f801d SG |
2376 | tx_queue->skb_dirtytx = skb_dirtytx; |
2377 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2378 | |
d080cd63 DH |
2379 | return howmany; |
2380 | } | |
2381 | ||
f4983704 | 2382 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2383 | { |
a6d0b91a AV |
2384 | unsigned long flags; |
2385 | ||
fba4ed03 SG |
2386 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2387 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2388 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2389 | __napi_schedule(&gfargrp->napi); |
8707bdd4 JP |
2390 | } else { |
2391 | /* | |
2392 | * Clear IEVENT, so interrupts aren't called again | |
2393 | * because of the packets that have already arrived. | |
2394 | */ | |
f4983704 | 2395 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2396 | } |
fba4ed03 | 2397 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2398 | |
8c7396ae | 2399 | } |
1da177e4 | 2400 | |
8c7396ae | 2401 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2402 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2403 | { |
f4983704 | 2404 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2405 | return IRQ_HANDLED; |
2406 | } | |
2407 | ||
a12f801d | 2408 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 AF |
2409 | struct sk_buff *skb) |
2410 | { | |
a12f801d | 2411 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2412 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2413 | dma_addr_t buf; |
815b97c6 | 2414 | |
8a102fe0 AV |
2415 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2416 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2417 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2418 | } |
2419 | ||
2420 | ||
2421 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 2422 | { |
7f7f5316 | 2423 | unsigned int alignamount; |
1da177e4 LT |
2424 | struct gfar_private *priv = netdev_priv(dev); |
2425 | struct sk_buff *skb = NULL; | |
1da177e4 | 2426 | |
0fd56bb5 AF |
2427 | skb = __skb_dequeue(&priv->rx_recycle); |
2428 | if (!skb) | |
2429 | skb = netdev_alloc_skb(dev, | |
2430 | priv->rx_buffer_size + RXBUF_ALIGNMENT); | |
1da177e4 | 2431 | |
815b97c6 | 2432 | if (!skb) |
1da177e4 LT |
2433 | return NULL; |
2434 | ||
7f7f5316 | 2435 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 2436 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 2437 | |
1da177e4 LT |
2438 | /* We need the data buffer to be aligned properly. We will reserve |
2439 | * as many bytes as needed to align the data properly | |
2440 | */ | |
7f7f5316 | 2441 | skb_reserve(skb, alignamount); |
a6d36d56 | 2442 | GFAR_CB(skb)->alignamount = alignamount; |
1da177e4 | 2443 | |
1da177e4 LT |
2444 | return skb; |
2445 | } | |
2446 | ||
298e1a9e | 2447 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2448 | { |
298e1a9e | 2449 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2450 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2451 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2452 | ||
2453 | /* If the packet was truncated, none of the other errors | |
2454 | * matter */ | |
2455 | if (status & RXBD_TRUNCATED) { | |
2456 | stats->rx_length_errors++; | |
2457 | ||
2458 | estats->rx_trunc++; | |
2459 | ||
2460 | return; | |
2461 | } | |
2462 | /* Count the errors, if there were any */ | |
2463 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2464 | stats->rx_length_errors++; | |
2465 | ||
2466 | if (status & RXBD_LARGE) | |
2467 | estats->rx_large++; | |
2468 | else | |
2469 | estats->rx_short++; | |
2470 | } | |
2471 | if (status & RXBD_NONOCTET) { | |
2472 | stats->rx_frame_errors++; | |
2473 | estats->rx_nonoctet++; | |
2474 | } | |
2475 | if (status & RXBD_CRCERR) { | |
2476 | estats->rx_crcerr++; | |
2477 | stats->rx_crc_errors++; | |
2478 | } | |
2479 | if (status & RXBD_OVERRUN) { | |
2480 | estats->rx_overrun++; | |
2481 | stats->rx_crc_errors++; | |
2482 | } | |
2483 | } | |
2484 | ||
f4983704 | 2485 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2486 | { |
f4983704 | 2487 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2488 | return IRQ_HANDLED; |
2489 | } | |
2490 | ||
0bbaf069 KG |
2491 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2492 | { | |
2493 | /* If valid headers were found, and valid sums | |
2494 | * were verified, then we tell the kernel that no | |
2495 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 2496 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2497 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2498 | else | |
2499 | skb->ip_summed = CHECKSUM_NONE; | |
2500 | } | |
2501 | ||
2502 | ||
1da177e4 LT |
2503 | /* gfar_process_frame() -- handle one incoming packet if skb |
2504 | * isn't NULL. */ | |
2505 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 2506 | int amount_pull) |
1da177e4 LT |
2507 | { |
2508 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2509 | struct rxfcb *fcb = NULL; |
1da177e4 | 2510 | |
2c2db48a | 2511 | int ret; |
1da177e4 | 2512 | |
2c2db48a DH |
2513 | /* fcb is at the beginning if exists */ |
2514 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2515 | |
2c2db48a DH |
2516 | /* Remove the FCB from the skb */ |
2517 | /* Remove the padded bytes, if there are any */ | |
f74dac08 SG |
2518 | if (amount_pull) { |
2519 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2520 | skb_pull(skb, amount_pull); |
f74dac08 | 2521 | } |
0bbaf069 | 2522 | |
cc772ab7 MR |
2523 | /* Get receive timestamp from the skb */ |
2524 | if (priv->hwts_rx_en) { | |
2525 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2526 | u64 *ns = (u64 *) skb->data; | |
2527 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
2528 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2529 | } | |
2530 | ||
2531 | if (priv->padding) | |
2532 | skb_pull(skb, priv->padding); | |
2533 | ||
2c2db48a DH |
2534 | if (priv->rx_csum_enable) |
2535 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 2536 | |
2c2db48a DH |
2537 | /* Tell the skb what kind of packet this is */ |
2538 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2539 | |
2c2db48a DH |
2540 | /* Send the packet up the stack */ |
2541 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
2542 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
2543 | else | |
2544 | ret = netif_receive_skb(skb); | |
0bbaf069 | 2545 | |
2c2db48a DH |
2546 | if (NET_RX_DROP == ret) |
2547 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
2548 | |
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 2553 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
2554 | * of frames handled |
2555 | */ | |
a12f801d | 2556 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2557 | { |
a12f801d | 2558 | struct net_device *dev = rx_queue->dev; |
31de198b | 2559 | struct rxbd8 *bdp, *base; |
1da177e4 | 2560 | struct sk_buff *skb; |
2c2db48a DH |
2561 | int pkt_len; |
2562 | int amount_pull; | |
1da177e4 LT |
2563 | int howmany = 0; |
2564 | struct gfar_private *priv = netdev_priv(dev); | |
2565 | ||
2566 | /* Get the first full descriptor */ | |
a12f801d SG |
2567 | bdp = rx_queue->cur_rx; |
2568 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2569 | |
cc772ab7 | 2570 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2571 | |
1da177e4 | 2572 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2573 | struct sk_buff *newskb; |
3b6330ce | 2574 | rmb(); |
815b97c6 AF |
2575 | |
2576 | /* Add another skb for the future */ | |
2577 | newskb = gfar_new_skb(dev); | |
2578 | ||
a12f801d | 2579 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2580 | |
4826857f | 2581 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
2582 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
2583 | ||
815b97c6 AF |
2584 | /* We drop the frame if we failed to allocate a new buffer */ |
2585 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
2586 | bdp->status & RXBD_ERR)) { | |
2587 | count_errors(bdp->status, dev); | |
2588 | ||
2589 | if (unlikely(!newskb)) | |
2590 | newskb = skb; | |
4e2fd555 LB |
2591 | else if (skb) { |
2592 | /* | |
a6d36d56 | 2593 | * We need to un-reserve() the skb to what it |
4e2fd555 LB |
2594 | * was before gfar_new_skb() re-aligned |
2595 | * it to an RXBUF_ALIGNMENT boundary | |
2596 | * before we put the skb back on the | |
2597 | * recycle list. | |
2598 | */ | |
a6d36d56 | 2599 | skb_reserve(skb, -GFAR_CB(skb)->alignamount); |
0fd56bb5 | 2600 | __skb_queue_head(&priv->rx_recycle, skb); |
4e2fd555 | 2601 | } |
815b97c6 | 2602 | } else { |
1da177e4 | 2603 | /* Increment the number of packets */ |
a7f38041 | 2604 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2605 | howmany++; |
2606 | ||
2c2db48a DH |
2607 | if (likely(skb)) { |
2608 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2609 | /* Remove the FCS from the packet length */ | |
2610 | skb_put(skb, pkt_len); | |
a7f38041 | 2611 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2612 | skb_record_rx_queue(skb, rx_queue->qindex); |
2c2db48a DH |
2613 | gfar_process_frame(dev, skb, amount_pull); |
2614 | ||
2615 | } else { | |
2616 | if (netif_msg_rx_err(priv)) | |
2617 | printk(KERN_WARNING | |
2618 | "%s: Missing skb!\n", dev->name); | |
a7f38041 | 2619 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2620 | priv->extra_stats.rx_skbmissing++; |
2621 | } | |
1da177e4 | 2622 | |
1da177e4 LT |
2623 | } |
2624 | ||
a12f801d | 2625 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2626 | |
815b97c6 | 2627 | /* Setup the new bdp */ |
a12f801d | 2628 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2629 | |
2630 | /* Update to the next pointer */ | |
a12f801d | 2631 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2632 | |
2633 | /* update to point at the next skb */ | |
a12f801d SG |
2634 | rx_queue->skb_currx = |
2635 | (rx_queue->skb_currx + 1) & | |
2636 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2637 | } |
2638 | ||
2639 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2640 | rx_queue->cur_rx = bdp; |
1da177e4 | 2641 | |
1da177e4 LT |
2642 | return howmany; |
2643 | } | |
2644 | ||
bea3348e | 2645 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2646 | { |
fba4ed03 SG |
2647 | struct gfar_priv_grp *gfargrp = container_of(napi, |
2648 | struct gfar_priv_grp, napi); | |
2649 | struct gfar_private *priv = gfargrp->priv; | |
46ceb60c | 2650 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2651 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2652 | struct gfar_priv_rx_q *rx_queue = NULL; |
2653 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2654 | int tx_cleaned = 0, i, left_over_budget = budget; |
2655 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2656 | int num_queues = 0; |
d080cd63 | 2657 | |
fba4ed03 SG |
2658 | num_queues = gfargrp->num_rx_queues; |
2659 | budget_per_queue = budget/num_queues; | |
2660 | ||
8c7396ae DH |
2661 | /* Clear IEVENT, so interrupts aren't called again |
2662 | * because of the packets that have already arrived */ | |
f4983704 | 2663 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2664 | |
fba4ed03 | 2665 | while (num_queues && left_over_budget) { |
1da177e4 | 2666 | |
fba4ed03 SG |
2667 | budget_per_queue = left_over_budget/num_queues; |
2668 | left_over_budget = 0; | |
2669 | ||
984b3f57 | 2670 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2671 | if (test_bit(i, &serviced_queues)) |
2672 | continue; | |
2673 | rx_queue = priv->rx_queue[i]; | |
2674 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2675 | ||
a3bc1f11 | 2676 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
fba4ed03 SG |
2677 | rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, |
2678 | budget_per_queue); | |
2679 | rx_cleaned += rx_cleaned_per_queue; | |
2680 | if(rx_cleaned_per_queue < budget_per_queue) { | |
2681 | left_over_budget = left_over_budget + | |
2682 | (budget_per_queue - rx_cleaned_per_queue); | |
2683 | set_bit(i, &serviced_queues); | |
2684 | num_queues--; | |
2685 | } | |
2686 | } | |
2687 | } | |
1da177e4 | 2688 | |
42199884 AF |
2689 | if (tx_cleaned) |
2690 | return budget; | |
2691 | ||
2692 | if (rx_cleaned < budget) { | |
288379f0 | 2693 | napi_complete(napi); |
1da177e4 LT |
2694 | |
2695 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2696 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2697 | |
f4983704 | 2698 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 LT |
2699 | |
2700 | /* If we are coalescing interrupts, update the timer */ | |
2701 | /* Otherwise, clear it */ | |
46ceb60c SG |
2702 | gfar_configure_coalescing(priv, |
2703 | gfargrp->rx_bit_map, gfargrp->tx_bit_map); | |
1da177e4 LT |
2704 | } |
2705 | ||
42199884 | 2706 | return rx_cleaned; |
1da177e4 | 2707 | } |
1da177e4 | 2708 | |
f2d71c2d VW |
2709 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2710 | /* | |
2711 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
2712 | * without having to re-enable interrupts. It's not called while | |
2713 | * the interrupt routine is executing. | |
2714 | */ | |
2715 | static void gfar_netpoll(struct net_device *dev) | |
2716 | { | |
2717 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2718 | int i = 0; |
f2d71c2d VW |
2719 | |
2720 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2721 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2722 | for (i = 0; i < priv->num_grps; i++) { |
2723 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2724 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2725 | disable_irq(priv->gfargrp[i].interruptError); | |
2726 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2727 | &priv->gfargrp[i]); | |
2728 | enable_irq(priv->gfargrp[i].interruptError); | |
2729 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2730 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2731 | } | |
f2d71c2d | 2732 | } else { |
46ceb60c SG |
2733 | for (i = 0; i < priv->num_grps; i++) { |
2734 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2735 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2736 | &priv->gfargrp[i]); | |
2737 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
43de004b | 2738 | } |
f2d71c2d VW |
2739 | } |
2740 | } | |
2741 | #endif | |
2742 | ||
1da177e4 | 2743 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2744 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2745 | { |
f4983704 | 2746 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2747 | |
2748 | /* Save ievent for future reference */ | |
f4983704 | 2749 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2750 | |
1da177e4 | 2751 | /* Check for reception */ |
538cc7ee | 2752 | if (events & IEVENT_RX_MASK) |
f4983704 | 2753 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2754 | |
2755 | /* Check for transmit completion */ | |
538cc7ee | 2756 | if (events & IEVENT_TX_MASK) |
f4983704 | 2757 | gfar_transmit(irq, grp_id); |
1da177e4 | 2758 | |
538cc7ee SS |
2759 | /* Check for errors */ |
2760 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2761 | gfar_error(irq, grp_id); |
1da177e4 LT |
2762 | |
2763 | return IRQ_HANDLED; | |
2764 | } | |
2765 | ||
1da177e4 LT |
2766 | /* Called every time the controller might need to be made |
2767 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2768 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2769 | * function converts those variables into the appropriate |
2770 | * register values, and can bring down the device if needed. | |
2771 | */ | |
2772 | static void adjust_link(struct net_device *dev) | |
2773 | { | |
2774 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2775 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2776 | unsigned long flags; |
2777 | struct phy_device *phydev = priv->phydev; | |
2778 | int new_state = 0; | |
2779 | ||
fba4ed03 SG |
2780 | local_irq_save(flags); |
2781 | lock_tx_qs(priv); | |
2782 | ||
bb40dcbb AF |
2783 | if (phydev->link) { |
2784 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2785 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2786 | |
1da177e4 LT |
2787 | /* Now we make sure that we can be in full duplex mode. |
2788 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2789 | if (phydev->duplex != priv->oldduplex) { |
2790 | new_state = 1; | |
2791 | if (!(phydev->duplex)) | |
1da177e4 | 2792 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2793 | else |
1da177e4 | 2794 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2795 | |
bb40dcbb | 2796 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2797 | } |
2798 | ||
bb40dcbb AF |
2799 | if (phydev->speed != priv->oldspeed) { |
2800 | new_state = 1; | |
2801 | switch (phydev->speed) { | |
1da177e4 | 2802 | case 1000: |
1da177e4 LT |
2803 | tempval = |
2804 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2805 | |
2806 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2807 | break; |
2808 | case 100: | |
2809 | case 10: | |
1da177e4 LT |
2810 | tempval = |
2811 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2812 | |
2813 | /* Reduced mode distinguishes | |
2814 | * between 10 and 100 */ | |
2815 | if (phydev->speed == SPEED_100) | |
2816 | ecntrl |= ECNTRL_R100; | |
2817 | else | |
2818 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2819 | break; |
2820 | default: | |
0bbaf069 KG |
2821 | if (netif_msg_link(priv)) |
2822 | printk(KERN_WARNING | |
bb40dcbb AF |
2823 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2824 | dev->name, phydev->speed); | |
1da177e4 LT |
2825 | break; |
2826 | } | |
2827 | ||
bb40dcbb | 2828 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2829 | } |
2830 | ||
bb40dcbb | 2831 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2832 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2833 | |
1da177e4 | 2834 | if (!priv->oldlink) { |
bb40dcbb | 2835 | new_state = 1; |
1da177e4 | 2836 | priv->oldlink = 1; |
1da177e4 | 2837 | } |
bb40dcbb AF |
2838 | } else if (priv->oldlink) { |
2839 | new_state = 1; | |
2840 | priv->oldlink = 0; | |
2841 | priv->oldspeed = 0; | |
2842 | priv->oldduplex = -1; | |
1da177e4 | 2843 | } |
1da177e4 | 2844 | |
bb40dcbb AF |
2845 | if (new_state && netif_msg_link(priv)) |
2846 | phy_print_status(phydev); | |
fba4ed03 SG |
2847 | unlock_tx_qs(priv); |
2848 | local_irq_restore(flags); | |
bb40dcbb | 2849 | } |
1da177e4 LT |
2850 | |
2851 | /* Update the hash table based on the current list of multicast | |
2852 | * addresses we subscribe to. Also, change the promiscuity of | |
2853 | * the device based on the flags (this function is called | |
2854 | * whenever dev->flags is changed */ | |
2855 | static void gfar_set_multi(struct net_device *dev) | |
2856 | { | |
22bedad3 | 2857 | struct netdev_hw_addr *ha; |
1da177e4 | 2858 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 2859 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
2860 | u32 tempval; |
2861 | ||
a12f801d | 2862 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
2863 | /* Set RCTRL to PROM */ |
2864 | tempval = gfar_read(®s->rctrl); | |
2865 | tempval |= RCTRL_PROM; | |
2866 | gfar_write(®s->rctrl, tempval); | |
2867 | } else { | |
2868 | /* Set RCTRL to not PROM */ | |
2869 | tempval = gfar_read(®s->rctrl); | |
2870 | tempval &= ~(RCTRL_PROM); | |
2871 | gfar_write(®s->rctrl, tempval); | |
2872 | } | |
6aa20a22 | 2873 | |
a12f801d | 2874 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 2875 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
2876 | gfar_write(®s->igaddr0, 0xffffffff); |
2877 | gfar_write(®s->igaddr1, 0xffffffff); | |
2878 | gfar_write(®s->igaddr2, 0xffffffff); | |
2879 | gfar_write(®s->igaddr3, 0xffffffff); | |
2880 | gfar_write(®s->igaddr4, 0xffffffff); | |
2881 | gfar_write(®s->igaddr5, 0xffffffff); | |
2882 | gfar_write(®s->igaddr6, 0xffffffff); | |
2883 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2884 | gfar_write(®s->gaddr0, 0xffffffff); |
2885 | gfar_write(®s->gaddr1, 0xffffffff); | |
2886 | gfar_write(®s->gaddr2, 0xffffffff); | |
2887 | gfar_write(®s->gaddr3, 0xffffffff); | |
2888 | gfar_write(®s->gaddr4, 0xffffffff); | |
2889 | gfar_write(®s->gaddr5, 0xffffffff); | |
2890 | gfar_write(®s->gaddr6, 0xffffffff); | |
2891 | gfar_write(®s->gaddr7, 0xffffffff); | |
2892 | } else { | |
7f7f5316 AF |
2893 | int em_num; |
2894 | int idx; | |
2895 | ||
1da177e4 | 2896 | /* zero out the hash */ |
0bbaf069 KG |
2897 | gfar_write(®s->igaddr0, 0x0); |
2898 | gfar_write(®s->igaddr1, 0x0); | |
2899 | gfar_write(®s->igaddr2, 0x0); | |
2900 | gfar_write(®s->igaddr3, 0x0); | |
2901 | gfar_write(®s->igaddr4, 0x0); | |
2902 | gfar_write(®s->igaddr5, 0x0); | |
2903 | gfar_write(®s->igaddr6, 0x0); | |
2904 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2905 | gfar_write(®s->gaddr0, 0x0); |
2906 | gfar_write(®s->gaddr1, 0x0); | |
2907 | gfar_write(®s->gaddr2, 0x0); | |
2908 | gfar_write(®s->gaddr3, 0x0); | |
2909 | gfar_write(®s->gaddr4, 0x0); | |
2910 | gfar_write(®s->gaddr5, 0x0); | |
2911 | gfar_write(®s->gaddr6, 0x0); | |
2912 | gfar_write(®s->gaddr7, 0x0); | |
2913 | ||
7f7f5316 AF |
2914 | /* If we have extended hash tables, we need to |
2915 | * clear the exact match registers to prepare for | |
2916 | * setting them */ | |
2917 | if (priv->extended_hash) { | |
2918 | em_num = GFAR_EM_NUM + 1; | |
2919 | gfar_clear_exact_match(dev); | |
2920 | idx = 1; | |
2921 | } else { | |
2922 | idx = 0; | |
2923 | em_num = 0; | |
2924 | } | |
2925 | ||
4cd24eaf | 2926 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
2927 | return; |
2928 | ||
2929 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 2930 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 2931 | if (idx < em_num) { |
22bedad3 | 2932 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
2933 | idx++; |
2934 | } else | |
22bedad3 | 2935 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
2936 | } |
2937 | } | |
2938 | ||
2939 | return; | |
2940 | } | |
2941 | ||
7f7f5316 AF |
2942 | |
2943 | /* Clears each of the exact match registers to zero, so they | |
2944 | * don't interfere with normal reception */ | |
2945 | static void gfar_clear_exact_match(struct net_device *dev) | |
2946 | { | |
2947 | int idx; | |
2948 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2949 | ||
2950 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2951 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2952 | } | |
2953 | ||
1da177e4 LT |
2954 | /* Set the appropriate hash bit for the given addr */ |
2955 | /* The algorithm works like so: | |
2956 | * 1) Take the Destination Address (ie the multicast address), and | |
2957 | * do a CRC on it (little endian), and reverse the bits of the | |
2958 | * result. | |
2959 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2960 | * table. The table is controlled through 8 32-bit registers: | |
2961 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2962 | * gaddr7. This means that the 3 most significant bits in the | |
2963 | * hash index which gaddr register to use, and the 5 other bits | |
2964 | * indicate which bit (assuming an IBM numbering scheme, which | |
2965 | * for PowerPC (tm) is usually the case) in the register holds | |
2966 | * the entry. */ | |
2967 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2968 | { | |
2969 | u32 tempval; | |
2970 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2971 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2972 | int width = priv->hash_width; |
2973 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2974 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2975 | u32 value = (1 << (31-whichbit)); |
2976 | ||
0bbaf069 | 2977 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2978 | tempval |= value; |
0bbaf069 | 2979 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2980 | |
2981 | return; | |
2982 | } | |
2983 | ||
7f7f5316 AF |
2984 | |
2985 | /* There are multiple MAC Address register pairs on some controllers | |
2986 | * This function sets the numth pair to a given address | |
2987 | */ | |
2988 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2989 | { | |
2990 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2991 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 AF |
2992 | int idx; |
2993 | char tmpbuf[MAC_ADDR_LEN]; | |
2994 | u32 tempval; | |
f4983704 | 2995 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
2996 | |
2997 | macptr += num*2; | |
2998 | ||
2999 | /* Now copy it into the mac registers backwards, cuz */ | |
3000 | /* little endian is silly */ | |
3001 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
3002 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
3003 | ||
3004 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3005 | ||
3006 | tempval = *((u32 *) (tmpbuf + 4)); | |
3007 | ||
3008 | gfar_write(macptr+1, tempval); | |
3009 | } | |
3010 | ||
1da177e4 | 3011 | /* GFAR error interrupt handler */ |
f4983704 | 3012 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3013 | { |
f4983704 SG |
3014 | struct gfar_priv_grp *gfargrp = grp_id; |
3015 | struct gfar __iomem *regs = gfargrp->regs; | |
3016 | struct gfar_private *priv= gfargrp->priv; | |
3017 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3018 | |
3019 | /* Save ievent for future reference */ | |
f4983704 | 3020 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3021 | |
3022 | /* Clear IEVENT */ | |
f4983704 | 3023 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3024 | |
3025 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3026 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3027 | (events & IEVENT_MAG)) |
3028 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3029 | |
3030 | /* Hmm... */ | |
0bbaf069 KG |
3031 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
3032 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
f4983704 | 3033 | dev->name, events, gfar_read(®s->imask)); |
1da177e4 LT |
3034 | |
3035 | /* Update the error counters */ | |
3036 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3037 | dev->stats.tx_errors++; |
1da177e4 LT |
3038 | |
3039 | if (events & IEVENT_LC) | |
09f75cd7 | 3040 | dev->stats.tx_window_errors++; |
1da177e4 | 3041 | if (events & IEVENT_CRL) |
09f75cd7 | 3042 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3043 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3044 | unsigned long flags; |
3045 | ||
0bbaf069 | 3046 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
3047 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
3048 | "packet dropped.\n", dev->name); | |
09f75cd7 | 3049 | dev->stats.tx_dropped++; |
1da177e4 LT |
3050 | priv->extra_stats.tx_underrun++; |
3051 | ||
836cf7fa AV |
3052 | local_irq_save(flags); |
3053 | lock_tx_qs(priv); | |
3054 | ||
1da177e4 | 3055 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3056 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3057 | |
3058 | unlock_tx_qs(priv); | |
3059 | local_irq_restore(flags); | |
1da177e4 | 3060 | } |
0bbaf069 KG |
3061 | if (netif_msg_tx_err(priv)) |
3062 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
3063 | } |
3064 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3065 | dev->stats.rx_errors++; |
1da177e4 LT |
3066 | priv->extra_stats.rx_bsy++; |
3067 | ||
f4983704 | 3068 | gfar_receive(irq, grp_id); |
1da177e4 | 3069 | |
0bbaf069 | 3070 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3071 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
f4983704 | 3072 | dev->name, gfar_read(®s->rstat)); |
1da177e4 LT |
3073 | } |
3074 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3075 | dev->stats.rx_errors++; |
1da177e4 LT |
3076 | priv->extra_stats.rx_babr++; |
3077 | ||
0bbaf069 | 3078 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3079 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
3080 | } |
3081 | if (events & IEVENT_EBERR) { | |
3082 | priv->extra_stats.eberr++; | |
0bbaf069 | 3083 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3084 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 3085 | } |
0bbaf069 | 3086 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 3087 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
3088 | |
3089 | if (events & IEVENT_BABT) { | |
3090 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 3091 | if (netif_msg_tx_err(priv)) |
538cc7ee | 3092 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
3093 | } |
3094 | return IRQ_HANDLED; | |
3095 | } | |
3096 | ||
b31a1d8b AF |
3097 | static struct of_device_id gfar_match[] = |
3098 | { | |
3099 | { | |
3100 | .type = "network", | |
3101 | .compatible = "gianfar", | |
3102 | }, | |
46ceb60c SG |
3103 | { |
3104 | .compatible = "fsl,etsec2", | |
3105 | }, | |
b31a1d8b AF |
3106 | {}, |
3107 | }; | |
e72701ac | 3108 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3109 | |
1da177e4 | 3110 | /* Structure for a device driver */ |
b31a1d8b AF |
3111 | static struct of_platform_driver gfar_driver = { |
3112 | .name = "fsl-gianfar", | |
3113 | .match_table = gfar_match, | |
3114 | ||
1da177e4 LT |
3115 | .probe = gfar_probe, |
3116 | .remove = gfar_remove, | |
be926fc4 AV |
3117 | .suspend = gfar_legacy_suspend, |
3118 | .resume = gfar_legacy_resume, | |
3119 | .driver.pm = GFAR_PM_OPS, | |
1da177e4 LT |
3120 | }; |
3121 | ||
3122 | static int __init gfar_init(void) | |
3123 | { | |
1577ecef | 3124 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
3125 | } |
3126 | ||
3127 | static void __exit gfar_exit(void) | |
3128 | { | |
b31a1d8b | 3129 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
3130 | } |
3131 | ||
3132 | module_init(gfar_init); | |
3133 | module_exit(gfar_exit); | |
3134 |