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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 7 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
8 | * |
9 | * Authors: | |
10 | * Yaniv Kamay <yaniv@qumranet.com> | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
edf88417 AK |
17 | #include <linux/kvm_host.h> |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
5fdbf976 | 21 | #include "kvm_cache_regs.h" |
fe4c7b19 | 22 | #include "x86.h" |
e495606d | 23 | |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
6aa8b732 | 31 | |
67ec6607 | 32 | #include <asm/tlbflush.h> |
e495606d | 33 | #include <asm/desc.h> |
6aa8b732 | 34 | |
63d1142f | 35 | #include <asm/virtext.h> |
229456fc | 36 | #include "trace.h" |
63d1142f | 37 | |
4ecac3fd AK |
38 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
39 | ||
6aa8b732 AK |
40 | MODULE_AUTHOR("Qumranet"); |
41 | MODULE_LICENSE("GPL"); | |
42 | ||
43 | #define IOPM_ALLOC_ORDER 2 | |
44 | #define MSRPM_ALLOC_ORDER 1 | |
45 | ||
6aa8b732 AK |
46 | #define SEG_TYPE_LDT 2 |
47 | #define SEG_TYPE_BUSY_TSS16 3 | |
48 | ||
6bc31bdc AP |
49 | #define SVM_FEATURE_NPT (1 << 0) |
50 | #define SVM_FEATURE_LBRV (1 << 1) | |
51 | #define SVM_FEATURE_SVML (1 << 2) | |
52 | #define SVM_FEATURE_NRIP (1 << 3) | |
53 | #define SVM_FEATURE_PAUSE_FILTER (1 << 10) | |
80b7706e | 54 | |
410e4d57 JR |
55 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
56 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
57 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
58 | ||
24e09cbf JR |
59 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
60 | ||
67ec6607 JR |
61 | static bool erratum_383_found __read_mostly; |
62 | ||
6c8166a7 AK |
63 | static const u32 host_save_user_msrs[] = { |
64 | #ifdef CONFIG_X86_64 | |
65 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
66 | MSR_FS_BASE, | |
67 | #endif | |
68 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
69 | }; | |
70 | ||
71 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
72 | ||
73 | struct kvm_vcpu; | |
74 | ||
e6aa9abd JR |
75 | struct nested_state { |
76 | struct vmcb *hsave; | |
77 | u64 hsave_msr; | |
4a810181 | 78 | u64 vm_cr_msr; |
e6aa9abd JR |
79 | u64 vmcb; |
80 | ||
81 | /* These are the merged vectors */ | |
82 | u32 *msrpm; | |
83 | ||
84 | /* gpa pointers to the real vectors */ | |
85 | u64 vmcb_msrpm; | |
ce2ac085 | 86 | u64 vmcb_iopm; |
aad42c64 | 87 | |
cd3ff653 JR |
88 | /* A VMEXIT is required but not yet emulated */ |
89 | bool exit_required; | |
90 | ||
aad42c64 JR |
91 | /* cache for intercepts of the guest */ |
92 | u16 intercept_cr_read; | |
93 | u16 intercept_cr_write; | |
94 | u16 intercept_dr_read; | |
95 | u16 intercept_dr_write; | |
96 | u32 intercept_exceptions; | |
97 | u64 intercept; | |
98 | ||
e6aa9abd JR |
99 | }; |
100 | ||
323c3d80 JR |
101 | #define MSRPM_OFFSETS 16 |
102 | static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; | |
103 | ||
6c8166a7 AK |
104 | struct vcpu_svm { |
105 | struct kvm_vcpu vcpu; | |
106 | struct vmcb *vmcb; | |
107 | unsigned long vmcb_pa; | |
108 | struct svm_cpu_data *svm_data; | |
109 | uint64_t asid_generation; | |
110 | uint64_t sysenter_esp; | |
111 | uint64_t sysenter_eip; | |
112 | ||
113 | u64 next_rip; | |
114 | ||
115 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
116 | u64 host_gs_base; | |
6c8166a7 AK |
117 | |
118 | u32 *msrpm; | |
6c8166a7 | 119 | |
e6aa9abd | 120 | struct nested_state nested; |
6be7d306 JK |
121 | |
122 | bool nmi_singlestep; | |
66b7138f JK |
123 | |
124 | unsigned int3_injected; | |
125 | unsigned long int3_rip; | |
6c8166a7 AK |
126 | }; |
127 | ||
455716fa JR |
128 | #define MSR_INVALID 0xffffffffU |
129 | ||
ac72a9b7 JR |
130 | static struct svm_direct_access_msrs { |
131 | u32 index; /* Index of the MSR */ | |
132 | bool always; /* True if intercept is always on */ | |
133 | } direct_access_msrs[] = { | |
8c06585d | 134 | { .index = MSR_STAR, .always = true }, |
ac72a9b7 JR |
135 | { .index = MSR_IA32_SYSENTER_CS, .always = true }, |
136 | #ifdef CONFIG_X86_64 | |
137 | { .index = MSR_GS_BASE, .always = true }, | |
138 | { .index = MSR_FS_BASE, .always = true }, | |
139 | { .index = MSR_KERNEL_GS_BASE, .always = true }, | |
140 | { .index = MSR_LSTAR, .always = true }, | |
141 | { .index = MSR_CSTAR, .always = true }, | |
142 | { .index = MSR_SYSCALL_MASK, .always = true }, | |
143 | #endif | |
144 | { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false }, | |
145 | { .index = MSR_IA32_LASTBRANCHTOIP, .always = false }, | |
146 | { .index = MSR_IA32_LASTINTFROMIP, .always = false }, | |
147 | { .index = MSR_IA32_LASTINTTOIP, .always = false }, | |
148 | { .index = MSR_INVALID, .always = false }, | |
6c8166a7 AK |
149 | }; |
150 | ||
709ddebf JR |
151 | /* enable NPT for AMD64 and X86 with PAE */ |
152 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
153 | static bool npt_enabled = true; | |
154 | #else | |
e0231715 | 155 | static bool npt_enabled; |
709ddebf | 156 | #endif |
6c7dac72 JR |
157 | static int npt = 1; |
158 | ||
159 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 160 | |
4b6e4dca | 161 | static int nested = 1; |
236de055 AG |
162 | module_param(nested, int, S_IRUGO); |
163 | ||
44874f84 | 164 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 165 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 166 | |
410e4d57 | 167 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
b8e88bc8 | 168 | static int nested_svm_intercept(struct vcpu_svm *svm); |
cf74a78b | 169 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
170 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
171 | bool has_error_code, u32 error_code); | |
172 | ||
a2fa3e9f GH |
173 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
174 | { | |
fb3f0f51 | 175 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
176 | } |
177 | ||
3d6368ef AG |
178 | static inline bool is_nested(struct vcpu_svm *svm) |
179 | { | |
e6aa9abd | 180 | return svm->nested.vmcb; |
3d6368ef AG |
181 | } |
182 | ||
2af9194d JR |
183 | static inline void enable_gif(struct vcpu_svm *svm) |
184 | { | |
185 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
186 | } | |
187 | ||
188 | static inline void disable_gif(struct vcpu_svm *svm) | |
189 | { | |
190 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
191 | } | |
192 | ||
193 | static inline bool gif_set(struct vcpu_svm *svm) | |
194 | { | |
195 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
196 | } | |
197 | ||
4866d5e3 | 198 | static unsigned long iopm_base; |
6aa8b732 AK |
199 | |
200 | struct kvm_ldttss_desc { | |
201 | u16 limit0; | |
202 | u16 base0; | |
e0231715 JR |
203 | unsigned base1:8, type:5, dpl:2, p:1; |
204 | unsigned limit1:4, zero0:3, g:1, base2:8; | |
6aa8b732 AK |
205 | u32 base3; |
206 | u32 zero1; | |
207 | } __attribute__((packed)); | |
208 | ||
209 | struct svm_cpu_data { | |
210 | int cpu; | |
211 | ||
5008fdf5 AK |
212 | u64 asid_generation; |
213 | u32 max_asid; | |
214 | u32 next_asid; | |
6aa8b732 AK |
215 | struct kvm_ldttss_desc *tss_desc; |
216 | ||
217 | struct page *save_area; | |
218 | }; | |
219 | ||
220 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 221 | static uint32_t svm_features; |
6aa8b732 AK |
222 | |
223 | struct svm_init_data { | |
224 | int cpu; | |
225 | int r; | |
226 | }; | |
227 | ||
228 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
229 | ||
9d8f549d | 230 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
231 | #define MSRS_RANGE_SIZE 2048 |
232 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
233 | ||
455716fa JR |
234 | static u32 svm_msrpm_offset(u32 msr) |
235 | { | |
236 | u32 offset; | |
237 | int i; | |
238 | ||
239 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
240 | if (msr < msrpm_ranges[i] || | |
241 | msr >= msrpm_ranges[i] + MSRS_IN_RANGE) | |
242 | continue; | |
243 | ||
244 | offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */ | |
245 | offset += (i * MSRS_RANGE_SIZE); /* add range offset */ | |
246 | ||
247 | /* Now we have the u8 offset - but need the u32 offset */ | |
248 | return offset / 4; | |
249 | } | |
250 | ||
251 | /* MSR not in any range */ | |
252 | return MSR_INVALID; | |
253 | } | |
254 | ||
6aa8b732 AK |
255 | #define MAX_INST_SIZE 15 |
256 | ||
80b7706e JR |
257 | static inline u32 svm_has(u32 feat) |
258 | { | |
259 | return svm_features & feat; | |
260 | } | |
261 | ||
6aa8b732 AK |
262 | static inline void clgi(void) |
263 | { | |
4ecac3fd | 264 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
265 | } |
266 | ||
267 | static inline void stgi(void) | |
268 | { | |
4ecac3fd | 269 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
270 | } |
271 | ||
272 | static inline void invlpga(unsigned long addr, u32 asid) | |
273 | { | |
e0231715 | 274 | asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid)); |
6aa8b732 AK |
275 | } |
276 | ||
6aa8b732 AK |
277 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
278 | { | |
a2fa3e9f | 279 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
280 | } |
281 | ||
282 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
283 | { | |
284 | force_new_asid(vcpu); | |
285 | } | |
286 | ||
287 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
288 | { | |
6dc696d4 | 289 | vcpu->arch.efer = efer; |
709ddebf | 290 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 291 | efer &= ~EFER_LME; |
6aa8b732 | 292 | |
9962d032 | 293 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
6aa8b732 AK |
294 | } |
295 | ||
6aa8b732 AK |
296 | static int is_external_interrupt(u32 info) |
297 | { | |
298 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
299 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
300 | } | |
301 | ||
2809f5d2 GC |
302 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
303 | { | |
304 | struct vcpu_svm *svm = to_svm(vcpu); | |
305 | u32 ret = 0; | |
306 | ||
307 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
48005f64 | 308 | ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
309 | return ret & mask; |
310 | } | |
311 | ||
312 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
313 | { | |
314 | struct vcpu_svm *svm = to_svm(vcpu); | |
315 | ||
316 | if (mask == 0) | |
317 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
318 | else | |
319 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
320 | ||
321 | } | |
322 | ||
6aa8b732 AK |
323 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
324 | { | |
a2fa3e9f GH |
325 | struct vcpu_svm *svm = to_svm(vcpu); |
326 | ||
6bc31bdc AP |
327 | if (svm->vmcb->control.next_rip != 0) |
328 | svm->next_rip = svm->vmcb->control.next_rip; | |
329 | ||
a2fa3e9f | 330 | if (!svm->next_rip) { |
851ba692 | 331 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
332 | EMULATE_DONE) |
333 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
334 | return; |
335 | } | |
5fdbf976 MT |
336 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
337 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
338 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 339 | |
5fdbf976 | 340 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 341 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
342 | } |
343 | ||
116a4752 | 344 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
345 | bool has_error_code, u32 error_code, |
346 | bool reinject) | |
116a4752 JK |
347 | { |
348 | struct vcpu_svm *svm = to_svm(vcpu); | |
349 | ||
e0231715 JR |
350 | /* |
351 | * If we are within a nested VM we'd better #VMEXIT and let the guest | |
352 | * handle the exception | |
353 | */ | |
ce7ddec4 JR |
354 | if (!reinject && |
355 | nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
116a4752 JK |
356 | return; |
357 | ||
66b7138f JK |
358 | if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) { |
359 | unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu); | |
360 | ||
361 | /* | |
362 | * For guest debugging where we have to reinject #BP if some | |
363 | * INT3 is guest-owned: | |
364 | * Emulate nRIP by moving RIP forward. Will fail if injection | |
365 | * raises a fault that is not intercepted. Still better than | |
366 | * failing in all cases. | |
367 | */ | |
368 | skip_emulated_instruction(&svm->vcpu); | |
369 | rip = kvm_rip_read(&svm->vcpu); | |
370 | svm->int3_rip = rip + svm->vmcb->save.cs.base; | |
371 | svm->int3_injected = rip - old_rip; | |
372 | } | |
373 | ||
116a4752 JK |
374 | svm->vmcb->control.event_inj = nr |
375 | | SVM_EVTINJ_VALID | |
376 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
377 | | SVM_EVTINJ_TYPE_EXEPT; | |
378 | svm->vmcb->control.event_inj_err = error_code; | |
379 | } | |
380 | ||
67ec6607 JR |
381 | static void svm_init_erratum_383(void) |
382 | { | |
383 | u32 low, high; | |
384 | int err; | |
385 | u64 val; | |
386 | ||
1be85a6d | 387 | if (!cpu_has_amd_erratum(amd_erratum_383)) |
67ec6607 JR |
388 | return; |
389 | ||
390 | /* Use _safe variants to not break nested virtualization */ | |
391 | val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); | |
392 | if (err) | |
393 | return; | |
394 | ||
395 | val |= (1ULL << 47); | |
396 | ||
397 | low = lower_32_bits(val); | |
398 | high = upper_32_bits(val); | |
399 | ||
400 | native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); | |
401 | ||
402 | erratum_383_found = true; | |
403 | } | |
404 | ||
6aa8b732 AK |
405 | static int has_svm(void) |
406 | { | |
63d1142f | 407 | const char *msg; |
6aa8b732 | 408 | |
63d1142f | 409 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 410 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
411 | return 0; |
412 | } | |
413 | ||
6aa8b732 AK |
414 | return 1; |
415 | } | |
416 | ||
417 | static void svm_hardware_disable(void *garbage) | |
418 | { | |
2c8dceeb | 419 | cpu_svm_disable(); |
6aa8b732 AK |
420 | } |
421 | ||
10474ae8 | 422 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
423 | { |
424 | ||
0fe1e009 | 425 | struct svm_cpu_data *sd; |
6aa8b732 | 426 | uint64_t efer; |
89a27f4d | 427 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
428 | struct desc_struct *gdt; |
429 | int me = raw_smp_processor_id(); | |
430 | ||
10474ae8 AG |
431 | rdmsrl(MSR_EFER, efer); |
432 | if (efer & EFER_SVME) | |
433 | return -EBUSY; | |
434 | ||
6aa8b732 | 435 | if (!has_svm()) { |
e6732a5a ZA |
436 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
437 | me); | |
10474ae8 | 438 | return -EINVAL; |
6aa8b732 | 439 | } |
0fe1e009 | 440 | sd = per_cpu(svm_data, me); |
6aa8b732 | 441 | |
0fe1e009 | 442 | if (!sd) { |
e6732a5a | 443 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 444 | me); |
10474ae8 | 445 | return -EINVAL; |
6aa8b732 AK |
446 | } |
447 | ||
0fe1e009 TH |
448 | sd->asid_generation = 1; |
449 | sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
450 | sd->next_asid = sd->max_asid + 1; | |
6aa8b732 | 451 | |
d6ab1ed4 | 452 | native_store_gdt(&gdt_descr); |
89a27f4d | 453 | gdt = (struct desc_struct *)gdt_descr.address; |
0fe1e009 | 454 | sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
6aa8b732 | 455 | |
9962d032 | 456 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 | 457 | |
d0316554 | 458 | wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT); |
10474ae8 | 459 | |
67ec6607 JR |
460 | svm_init_erratum_383(); |
461 | ||
10474ae8 | 462 | return 0; |
6aa8b732 AK |
463 | } |
464 | ||
0da1db75 JR |
465 | static void svm_cpu_uninit(int cpu) |
466 | { | |
0fe1e009 | 467 | struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id()); |
0da1db75 | 468 | |
0fe1e009 | 469 | if (!sd) |
0da1db75 JR |
470 | return; |
471 | ||
472 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
0fe1e009 TH |
473 | __free_page(sd->save_area); |
474 | kfree(sd); | |
0da1db75 JR |
475 | } |
476 | ||
6aa8b732 AK |
477 | static int svm_cpu_init(int cpu) |
478 | { | |
0fe1e009 | 479 | struct svm_cpu_data *sd; |
6aa8b732 AK |
480 | int r; |
481 | ||
0fe1e009 TH |
482 | sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); |
483 | if (!sd) | |
6aa8b732 | 484 | return -ENOMEM; |
0fe1e009 TH |
485 | sd->cpu = cpu; |
486 | sd->save_area = alloc_page(GFP_KERNEL); | |
6aa8b732 | 487 | r = -ENOMEM; |
0fe1e009 | 488 | if (!sd->save_area) |
6aa8b732 AK |
489 | goto err_1; |
490 | ||
0fe1e009 | 491 | per_cpu(svm_data, cpu) = sd; |
6aa8b732 AK |
492 | |
493 | return 0; | |
494 | ||
495 | err_1: | |
0fe1e009 | 496 | kfree(sd); |
6aa8b732 AK |
497 | return r; |
498 | ||
499 | } | |
500 | ||
ac72a9b7 JR |
501 | static bool valid_msr_intercept(u32 index) |
502 | { | |
503 | int i; | |
504 | ||
505 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) | |
506 | if (direct_access_msrs[i].index == index) | |
507 | return true; | |
508 | ||
509 | return false; | |
510 | } | |
511 | ||
bfc733a7 RR |
512 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
513 | int read, int write) | |
6aa8b732 | 514 | { |
455716fa JR |
515 | u8 bit_read, bit_write; |
516 | unsigned long tmp; | |
517 | u32 offset; | |
6aa8b732 | 518 | |
ac72a9b7 JR |
519 | /* |
520 | * If this warning triggers extend the direct_access_msrs list at the | |
521 | * beginning of the file | |
522 | */ | |
523 | WARN_ON(!valid_msr_intercept(msr)); | |
524 | ||
455716fa JR |
525 | offset = svm_msrpm_offset(msr); |
526 | bit_read = 2 * (msr & 0x0f); | |
527 | bit_write = 2 * (msr & 0x0f) + 1; | |
528 | tmp = msrpm[offset]; | |
529 | ||
530 | BUG_ON(offset == MSR_INVALID); | |
531 | ||
532 | read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp); | |
533 | write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp); | |
534 | ||
535 | msrpm[offset] = tmp; | |
6aa8b732 AK |
536 | } |
537 | ||
f65c229c | 538 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
6aa8b732 AK |
539 | { |
540 | int i; | |
541 | ||
f65c229c JR |
542 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); |
543 | ||
ac72a9b7 JR |
544 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { |
545 | if (!direct_access_msrs[i].always) | |
546 | continue; | |
547 | ||
548 | set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1); | |
549 | } | |
f65c229c JR |
550 | } |
551 | ||
323c3d80 JR |
552 | static void add_msr_offset(u32 offset) |
553 | { | |
554 | int i; | |
555 | ||
556 | for (i = 0; i < MSRPM_OFFSETS; ++i) { | |
557 | ||
558 | /* Offset already in list? */ | |
559 | if (msrpm_offsets[i] == offset) | |
bfc733a7 | 560 | return; |
323c3d80 JR |
561 | |
562 | /* Slot used by another offset? */ | |
563 | if (msrpm_offsets[i] != MSR_INVALID) | |
564 | continue; | |
565 | ||
566 | /* Add offset to list */ | |
567 | msrpm_offsets[i] = offset; | |
568 | ||
569 | return; | |
6aa8b732 | 570 | } |
323c3d80 JR |
571 | |
572 | /* | |
573 | * If this BUG triggers the msrpm_offsets table has an overflow. Just | |
574 | * increase MSRPM_OFFSETS in this case. | |
575 | */ | |
bfc733a7 | 576 | BUG(); |
6aa8b732 AK |
577 | } |
578 | ||
323c3d80 | 579 | static void init_msrpm_offsets(void) |
f65c229c | 580 | { |
323c3d80 | 581 | int i; |
f65c229c | 582 | |
323c3d80 JR |
583 | memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); |
584 | ||
585 | for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { | |
586 | u32 offset; | |
587 | ||
588 | offset = svm_msrpm_offset(direct_access_msrs[i].index); | |
589 | BUG_ON(offset == MSR_INVALID); | |
590 | ||
591 | add_msr_offset(offset); | |
592 | } | |
f65c229c JR |
593 | } |
594 | ||
24e09cbf JR |
595 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
596 | { | |
597 | u32 *msrpm = svm->msrpm; | |
598 | ||
599 | svm->vmcb->control.lbr_ctl = 1; | |
600 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
601 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
602 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
603 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
604 | } | |
605 | ||
606 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
607 | { | |
608 | u32 *msrpm = svm->msrpm; | |
609 | ||
610 | svm->vmcb->control.lbr_ctl = 0; | |
611 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
612 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
613 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
614 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
615 | } | |
616 | ||
6aa8b732 AK |
617 | static __init int svm_hardware_setup(void) |
618 | { | |
619 | int cpu; | |
620 | struct page *iopm_pages; | |
f65c229c | 621 | void *iopm_va; |
6aa8b732 AK |
622 | int r; |
623 | ||
6aa8b732 AK |
624 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
625 | ||
626 | if (!iopm_pages) | |
627 | return -ENOMEM; | |
c8681339 AL |
628 | |
629 | iopm_va = page_address(iopm_pages); | |
630 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
631 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
632 | ||
323c3d80 JR |
633 | init_msrpm_offsets(); |
634 | ||
50a37eb4 JR |
635 | if (boot_cpu_has(X86_FEATURE_NX)) |
636 | kvm_enable_efer_bits(EFER_NX); | |
637 | ||
1b2fd70c AG |
638 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
639 | kvm_enable_efer_bits(EFER_FFXSR); | |
640 | ||
236de055 AG |
641 | if (nested) { |
642 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
eec4b140 | 643 | kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE); |
236de055 AG |
644 | } |
645 | ||
3230bb47 | 646 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
647 | r = svm_cpu_init(cpu); |
648 | if (r) | |
f65c229c | 649 | goto err; |
6aa8b732 | 650 | } |
33bd6a0b JR |
651 | |
652 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
653 | ||
e3da3acd JR |
654 | if (!svm_has(SVM_FEATURE_NPT)) |
655 | npt_enabled = false; | |
656 | ||
6c7dac72 JR |
657 | if (npt_enabled && !npt) { |
658 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
659 | npt_enabled = false; | |
660 | } | |
661 | ||
18552672 | 662 | if (npt_enabled) { |
e3da3acd | 663 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 664 | kvm_enable_tdp(); |
5f4cb662 JR |
665 | } else |
666 | kvm_disable_tdp(); | |
e3da3acd | 667 | |
6aa8b732 AK |
668 | return 0; |
669 | ||
f65c229c | 670 | err: |
6aa8b732 AK |
671 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
672 | iopm_base = 0; | |
673 | return r; | |
674 | } | |
675 | ||
676 | static __exit void svm_hardware_unsetup(void) | |
677 | { | |
0da1db75 JR |
678 | int cpu; |
679 | ||
3230bb47 | 680 | for_each_possible_cpu(cpu) |
0da1db75 JR |
681 | svm_cpu_uninit(cpu); |
682 | ||
6aa8b732 | 683 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 684 | iopm_base = 0; |
6aa8b732 AK |
685 | } |
686 | ||
687 | static void init_seg(struct vmcb_seg *seg) | |
688 | { | |
689 | seg->selector = 0; | |
690 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
e0231715 | 691 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ |
6aa8b732 AK |
692 | seg->limit = 0xffff; |
693 | seg->base = 0; | |
694 | } | |
695 | ||
696 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
697 | { | |
698 | seg->selector = 0; | |
699 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
700 | seg->limit = 0xffff; | |
701 | seg->base = 0; | |
702 | } | |
703 | ||
e6101a96 | 704 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 705 | { |
e6101a96 JR |
706 | struct vmcb_control_area *control = &svm->vmcb->control; |
707 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 | 708 | |
bff78274 AK |
709 | svm->vcpu.fpu_active = 1; |
710 | ||
e0231715 | 711 | control->intercept_cr_read = INTERCEPT_CR0_MASK | |
6aa8b732 | 712 | INTERCEPT_CR3_MASK | |
649d6864 | 713 | INTERCEPT_CR4_MASK; |
6aa8b732 | 714 | |
e0231715 | 715 | control->intercept_cr_write = INTERCEPT_CR0_MASK | |
6aa8b732 | 716 | INTERCEPT_CR3_MASK | |
80a8119c AK |
717 | INTERCEPT_CR4_MASK | |
718 | INTERCEPT_CR8_MASK; | |
6aa8b732 | 719 | |
e0231715 | 720 | control->intercept_dr_read = INTERCEPT_DR0_MASK | |
6aa8b732 AK |
721 | INTERCEPT_DR1_MASK | |
722 | INTERCEPT_DR2_MASK | | |
727f5a23 JK |
723 | INTERCEPT_DR3_MASK | |
724 | INTERCEPT_DR4_MASK | | |
725 | INTERCEPT_DR5_MASK | | |
726 | INTERCEPT_DR6_MASK | | |
727 | INTERCEPT_DR7_MASK; | |
6aa8b732 | 728 | |
e0231715 | 729 | control->intercept_dr_write = INTERCEPT_DR0_MASK | |
6aa8b732 AK |
730 | INTERCEPT_DR1_MASK | |
731 | INTERCEPT_DR2_MASK | | |
732 | INTERCEPT_DR3_MASK | | |
727f5a23 | 733 | INTERCEPT_DR4_MASK | |
6aa8b732 | 734 | INTERCEPT_DR5_MASK | |
727f5a23 | 735 | INTERCEPT_DR6_MASK | |
6aa8b732 AK |
736 | INTERCEPT_DR7_MASK; |
737 | ||
7aa81cc0 | 738 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
739 | (1 << UD_VECTOR) | |
740 | (1 << MC_VECTOR); | |
6aa8b732 AK |
741 | |
742 | ||
e0231715 | 743 | control->intercept = (1ULL << INTERCEPT_INTR) | |
6aa8b732 | 744 | (1ULL << INTERCEPT_NMI) | |
0152527b | 745 | (1ULL << INTERCEPT_SMI) | |
d225157b | 746 | (1ULL << INTERCEPT_SELECTIVE_CR0) | |
6aa8b732 | 747 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 748 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 749 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 750 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
751 | (1ULL << INTERCEPT_INVLPGA) | |
752 | (1ULL << INTERCEPT_IOIO_PROT) | | |
753 | (1ULL << INTERCEPT_MSR_PROT) | | |
754 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 755 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
756 | (1ULL << INTERCEPT_VMRUN) | |
757 | (1ULL << INTERCEPT_VMMCALL) | | |
758 | (1ULL << INTERCEPT_VMLOAD) | | |
759 | (1ULL << INTERCEPT_VMSAVE) | | |
760 | (1ULL << INTERCEPT_STGI) | | |
761 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 762 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 763 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
764 | (1ULL << INTERCEPT_MONITOR) | |
765 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
766 | |
767 | control->iopm_base_pa = iopm_base; | |
f65c229c | 768 | control->msrpm_base_pa = __pa(svm->msrpm); |
58877679 | 769 | control->tsc_offset = 0-native_read_tsc(); |
6aa8b732 AK |
770 | control->int_ctl = V_INTR_MASKING_MASK; |
771 | ||
772 | init_seg(&save->es); | |
773 | init_seg(&save->ss); | |
774 | init_seg(&save->ds); | |
775 | init_seg(&save->fs); | |
776 | init_seg(&save->gs); | |
777 | ||
778 | save->cs.selector = 0xf000; | |
779 | /* Executable/Readable Code Segment */ | |
780 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
781 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
782 | save->cs.limit = 0xffff; | |
d92899a0 AK |
783 | /* |
784 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
785 | * be consistent with it. | |
786 | * | |
787 | * Replace when we have real mode working for vmx. | |
788 | */ | |
789 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
790 | |
791 | save->gdtr.limit = 0xffff; | |
792 | save->idtr.limit = 0xffff; | |
793 | ||
794 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
795 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
796 | ||
9962d032 | 797 | save->efer = EFER_SVME; |
d77c26fc | 798 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
799 | save->dr7 = 0x400; |
800 | save->rflags = 2; | |
801 | save->rip = 0x0000fff0; | |
5fdbf976 | 802 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 | 803 | |
e0231715 JR |
804 | /* |
805 | * This is the guest-visible cr0 value. | |
18fa000a | 806 | * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. |
6aa8b732 | 807 | */ |
18fa000a | 808 | svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
49a9b07e | 809 | (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0); |
18fa000a | 810 | |
66aee91a | 811 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 812 | /* rdx = ?? */ |
709ddebf JR |
813 | |
814 | if (npt_enabled) { | |
815 | /* Setup VMCB for Nested Paging */ | |
816 | control->nested_ctl = 1; | |
a7052897 MT |
817 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
818 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf | 819 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
888f9f3e AK |
820 | control->intercept_cr_read &= ~INTERCEPT_CR3_MASK; |
821 | control->intercept_cr_write &= ~INTERCEPT_CR3_MASK; | |
709ddebf | 822 | save->g_pat = 0x0007040600070406ULL; |
709ddebf JR |
823 | save->cr3 = 0; |
824 | save->cr4 = 0; | |
825 | } | |
a79d2f18 | 826 | force_new_asid(&svm->vcpu); |
1371d904 | 827 | |
e6aa9abd | 828 | svm->nested.vmcb = 0; |
2af9194d JR |
829 | svm->vcpu.arch.hflags = 0; |
830 | ||
565d0998 ML |
831 | if (svm_has(SVM_FEATURE_PAUSE_FILTER)) { |
832 | control->pause_filter_count = 3000; | |
833 | control->intercept |= (1ULL << INTERCEPT_PAUSE); | |
834 | } | |
835 | ||
2af9194d | 836 | enable_gif(svm); |
6aa8b732 AK |
837 | } |
838 | ||
e00c8cf2 | 839 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
840 | { |
841 | struct vcpu_svm *svm = to_svm(vcpu); | |
842 | ||
e6101a96 | 843 | init_vmcb(svm); |
70433389 | 844 | |
c5af89b6 | 845 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 846 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
847 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
848 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 849 | } |
5fdbf976 MT |
850 | vcpu->arch.regs_avail = ~0; |
851 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
852 | |
853 | return 0; | |
04d2cc77 AK |
854 | } |
855 | ||
fb3f0f51 | 856 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 857 | { |
a2fa3e9f | 858 | struct vcpu_svm *svm; |
6aa8b732 | 859 | struct page *page; |
f65c229c | 860 | struct page *msrpm_pages; |
b286d5d8 | 861 | struct page *hsave_page; |
3d6368ef | 862 | struct page *nested_msrpm_pages; |
fb3f0f51 | 863 | int err; |
6aa8b732 | 864 | |
c16f862d | 865 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
866 | if (!svm) { |
867 | err = -ENOMEM; | |
868 | goto out; | |
869 | } | |
870 | ||
871 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
872 | if (err) | |
873 | goto free_svm; | |
874 | ||
b7af4043 | 875 | err = -ENOMEM; |
6aa8b732 | 876 | page = alloc_page(GFP_KERNEL); |
b7af4043 | 877 | if (!page) |
fb3f0f51 | 878 | goto uninit; |
6aa8b732 | 879 | |
f65c229c JR |
880 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); |
881 | if (!msrpm_pages) | |
b7af4043 | 882 | goto free_page1; |
3d6368ef AG |
883 | |
884 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
885 | if (!nested_msrpm_pages) | |
b7af4043 | 886 | goto free_page2; |
f65c229c | 887 | |
b286d5d8 AG |
888 | hsave_page = alloc_page(GFP_KERNEL); |
889 | if (!hsave_page) | |
b7af4043 TY |
890 | goto free_page3; |
891 | ||
e6aa9abd | 892 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 893 | |
b7af4043 TY |
894 | svm->msrpm = page_address(msrpm_pages); |
895 | svm_vcpu_init_msrpm(svm->msrpm); | |
896 | ||
e6aa9abd | 897 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
323c3d80 | 898 | svm_vcpu_init_msrpm(svm->nested.msrpm); |
3d6368ef | 899 | |
a2fa3e9f GH |
900 | svm->vmcb = page_address(page); |
901 | clear_page(svm->vmcb); | |
902 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
903 | svm->asid_generation = 0; | |
e6101a96 | 904 | init_vmcb(svm); |
a2fa3e9f | 905 | |
10ab25cd JK |
906 | err = fx_init(&svm->vcpu); |
907 | if (err) | |
908 | goto free_page4; | |
909 | ||
ad312c7c | 910 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 911 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 912 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 913 | |
fb3f0f51 | 914 | return &svm->vcpu; |
36241b8c | 915 | |
10ab25cd JK |
916 | free_page4: |
917 | __free_page(hsave_page); | |
b7af4043 TY |
918 | free_page3: |
919 | __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER); | |
920 | free_page2: | |
921 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
922 | free_page1: | |
923 | __free_page(page); | |
fb3f0f51 RR |
924 | uninit: |
925 | kvm_vcpu_uninit(&svm->vcpu); | |
926 | free_svm: | |
a4770347 | 927 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
928 | out: |
929 | return ERR_PTR(err); | |
6aa8b732 AK |
930 | } |
931 | ||
932 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
933 | { | |
a2fa3e9f GH |
934 | struct vcpu_svm *svm = to_svm(vcpu); |
935 | ||
fb3f0f51 | 936 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 937 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
938 | __free_page(virt_to_page(svm->nested.hsave)); |
939 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 940 | kvm_vcpu_uninit(vcpu); |
a4770347 | 941 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
942 | } |
943 | ||
15ad7146 | 944 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 945 | { |
a2fa3e9f | 946 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 947 | int i; |
0cc5064d | 948 | |
0cc5064d | 949 | if (unlikely(cpu != vcpu->cpu)) { |
e935d48e | 950 | u64 delta; |
0cc5064d | 951 | |
953899b6 JR |
952 | if (check_tsc_unstable()) { |
953 | /* | |
954 | * Make sure that the guest sees a monotonically | |
955 | * increasing TSC. | |
956 | */ | |
957 | delta = vcpu->arch.host_tsc - native_read_tsc(); | |
958 | svm->vmcb->control.tsc_offset += delta; | |
959 | if (is_nested(svm)) | |
960 | svm->nested.hsave->control.tsc_offset += delta; | |
961 | } | |
0cc5064d | 962 | vcpu->cpu = cpu; |
2f599714 | 963 | kvm_migrate_timers(vcpu); |
4b656b12 | 964 | svm->asid_generation = 0; |
0cc5064d | 965 | } |
94dfbdb3 AL |
966 | |
967 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 968 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
969 | } |
970 | ||
971 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
972 | { | |
a2fa3e9f | 973 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
974 | int i; |
975 | ||
e1beb1d3 | 976 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 977 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 978 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 979 | |
e935d48e | 980 | vcpu->arch.host_tsc = native_read_tsc(); |
6aa8b732 AK |
981 | } |
982 | ||
6aa8b732 AK |
983 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
984 | { | |
a2fa3e9f | 985 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
986 | } |
987 | ||
988 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
989 | { | |
a2fa3e9f | 990 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
991 | } |
992 | ||
6de4f3ad AK |
993 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
994 | { | |
995 | switch (reg) { | |
996 | case VCPU_EXREG_PDPTR: | |
997 | BUG_ON(!npt_enabled); | |
998 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
999 | break; | |
1000 | default: | |
1001 | BUG(); | |
1002 | } | |
1003 | } | |
1004 | ||
f0b85051 AG |
1005 | static void svm_set_vintr(struct vcpu_svm *svm) |
1006 | { | |
1007 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
1008 | } | |
1009 | ||
1010 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
1011 | { | |
1012 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1013 | } | |
1014 | ||
6aa8b732 AK |
1015 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
1016 | { | |
a2fa3e9f | 1017 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
1018 | |
1019 | switch (seg) { | |
1020 | case VCPU_SREG_CS: return &save->cs; | |
1021 | case VCPU_SREG_DS: return &save->ds; | |
1022 | case VCPU_SREG_ES: return &save->es; | |
1023 | case VCPU_SREG_FS: return &save->fs; | |
1024 | case VCPU_SREG_GS: return &save->gs; | |
1025 | case VCPU_SREG_SS: return &save->ss; | |
1026 | case VCPU_SREG_TR: return &save->tr; | |
1027 | case VCPU_SREG_LDTR: return &save->ldtr; | |
1028 | } | |
1029 | BUG(); | |
8b6d44c7 | 1030 | return NULL; |
6aa8b732 AK |
1031 | } |
1032 | ||
1033 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
1034 | { | |
1035 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1036 | ||
1037 | return s->base; | |
1038 | } | |
1039 | ||
1040 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
1041 | struct kvm_segment *var, int seg) | |
1042 | { | |
1043 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
1044 | ||
1045 | var->base = s->base; | |
1046 | var->limit = s->limit; | |
1047 | var->selector = s->selector; | |
1048 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
1049 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
1050 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
1051 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
1052 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
1053 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
1054 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
1055 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 1056 | |
e0231715 JR |
1057 | /* |
1058 | * AMD's VMCB does not have an explicit unusable field, so emulate it | |
19bca6ab AP |
1059 | * for cross vendor migration purposes by "not present" |
1060 | */ | |
1061 | var->unusable = !var->present || (var->type == 0); | |
1062 | ||
1fbdc7a5 AP |
1063 | switch (seg) { |
1064 | case VCPU_SREG_CS: | |
1065 | /* | |
1066 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
1067 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
1068 | * Intel's VMENTRY has a check on the 'G' bit. | |
1069 | */ | |
25022acc | 1070 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
1071 | break; |
1072 | case VCPU_SREG_TR: | |
1073 | /* | |
1074 | * Work around a bug where the busy flag in the tr selector | |
1075 | * isn't exposed | |
1076 | */ | |
c0d09828 | 1077 | var->type |= 0x2; |
1fbdc7a5 AP |
1078 | break; |
1079 | case VCPU_SREG_DS: | |
1080 | case VCPU_SREG_ES: | |
1081 | case VCPU_SREG_FS: | |
1082 | case VCPU_SREG_GS: | |
1083 | /* | |
1084 | * The accessed bit must always be set in the segment | |
1085 | * descriptor cache, although it can be cleared in the | |
1086 | * descriptor, the cached bit always remains at 1. Since | |
1087 | * Intel has a check on this, set it here to support | |
1088 | * cross-vendor migration. | |
1089 | */ | |
1090 | if (!var->unusable) | |
1091 | var->type |= 0x1; | |
1092 | break; | |
b586eb02 | 1093 | case VCPU_SREG_SS: |
e0231715 JR |
1094 | /* |
1095 | * On AMD CPUs sometimes the DB bit in the segment | |
b586eb02 AP |
1096 | * descriptor is left as 1, although the whole segment has |
1097 | * been made unusable. Clear it here to pass an Intel VMX | |
1098 | * entry check when cross vendor migrating. | |
1099 | */ | |
1100 | if (var->unusable) | |
1101 | var->db = 0; | |
1102 | break; | |
1fbdc7a5 | 1103 | } |
6aa8b732 AK |
1104 | } |
1105 | ||
2e4d2653 IE |
1106 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
1107 | { | |
1108 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
1109 | ||
1110 | return save->cpl; | |
1111 | } | |
1112 | ||
89a27f4d | 1113 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1114 | { |
a2fa3e9f GH |
1115 | struct vcpu_svm *svm = to_svm(vcpu); |
1116 | ||
89a27f4d GN |
1117 | dt->size = svm->vmcb->save.idtr.limit; |
1118 | dt->address = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
1119 | } |
1120 | ||
89a27f4d | 1121 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1122 | { |
a2fa3e9f GH |
1123 | struct vcpu_svm *svm = to_svm(vcpu); |
1124 | ||
89a27f4d GN |
1125 | svm->vmcb->save.idtr.limit = dt->size; |
1126 | svm->vmcb->save.idtr.base = dt->address ; | |
6aa8b732 AK |
1127 | } |
1128 | ||
89a27f4d | 1129 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1130 | { |
a2fa3e9f GH |
1131 | struct vcpu_svm *svm = to_svm(vcpu); |
1132 | ||
89a27f4d GN |
1133 | dt->size = svm->vmcb->save.gdtr.limit; |
1134 | dt->address = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
1135 | } |
1136 | ||
89a27f4d | 1137 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 1138 | { |
a2fa3e9f GH |
1139 | struct vcpu_svm *svm = to_svm(vcpu); |
1140 | ||
89a27f4d GN |
1141 | svm->vmcb->save.gdtr.limit = dt->size; |
1142 | svm->vmcb->save.gdtr.base = dt->address ; | |
6aa8b732 AK |
1143 | } |
1144 | ||
e8467fda AK |
1145 | static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
1146 | { | |
1147 | } | |
1148 | ||
25c4c276 | 1149 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
1150 | { |
1151 | } | |
1152 | ||
d225157b AK |
1153 | static void update_cr0_intercept(struct vcpu_svm *svm) |
1154 | { | |
66a562f7 | 1155 | struct vmcb *vmcb = svm->vmcb; |
d225157b AK |
1156 | ulong gcr0 = svm->vcpu.arch.cr0; |
1157 | u64 *hcr0 = &svm->vmcb->save.cr0; | |
1158 | ||
1159 | if (!svm->vcpu.fpu_active) | |
1160 | *hcr0 |= SVM_CR0_SELECTIVE_MASK; | |
1161 | else | |
1162 | *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK) | |
1163 | | (gcr0 & SVM_CR0_SELECTIVE_MASK); | |
1164 | ||
1165 | ||
1166 | if (gcr0 == *hcr0 && svm->vcpu.fpu_active) { | |
66a562f7 JR |
1167 | vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; |
1168 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1169 | if (is_nested(svm)) { | |
1170 | struct vmcb *hsave = svm->nested.hsave; | |
1171 | ||
1172 | hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK; | |
1173 | hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK; | |
1174 | vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read; | |
1175 | vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write; | |
1176 | } | |
d225157b AK |
1177 | } else { |
1178 | svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1179 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
66a562f7 JR |
1180 | if (is_nested(svm)) { |
1181 | struct vmcb *hsave = svm->nested.hsave; | |
1182 | ||
1183 | hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK; | |
1184 | hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK; | |
1185 | } | |
d225157b AK |
1186 | } |
1187 | } | |
1188 | ||
6aa8b732 AK |
1189 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1190 | { | |
a2fa3e9f GH |
1191 | struct vcpu_svm *svm = to_svm(vcpu); |
1192 | ||
7f5d8b56 JR |
1193 | if (is_nested(svm)) { |
1194 | /* | |
1195 | * We are here because we run in nested mode, the host kvm | |
1196 | * intercepts cr0 writes but the l1 hypervisor does not. | |
1197 | * But the L1 hypervisor may intercept selective cr0 writes. | |
1198 | * This needs to be checked here. | |
1199 | */ | |
1200 | unsigned long old, new; | |
1201 | ||
1202 | /* Remove bits that would trigger a real cr0 write intercept */ | |
1203 | old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK; | |
1204 | new = cr0 & SVM_CR0_SELECTIVE_MASK; | |
1205 | ||
1206 | if (old == new) { | |
1207 | /* cr0 write with ts and mp unchanged */ | |
1208 | svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE; | |
1209 | if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) | |
1210 | return; | |
1211 | } | |
1212 | } | |
1213 | ||
05b3e0c2 | 1214 | #ifdef CONFIG_X86_64 |
f6801dff | 1215 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 1216 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
f6801dff | 1217 | vcpu->arch.efer |= EFER_LMA; |
2b5203ee | 1218 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1219 | } |
1220 | ||
d77c26fc | 1221 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
f6801dff | 1222 | vcpu->arch.efer &= ~EFER_LMA; |
2b5203ee | 1223 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
1224 | } |
1225 | } | |
1226 | #endif | |
ad312c7c | 1227 | vcpu->arch.cr0 = cr0; |
888f9f3e AK |
1228 | |
1229 | if (!npt_enabled) | |
1230 | cr0 |= X86_CR0_PG | X86_CR0_WP; | |
02daab21 AK |
1231 | |
1232 | if (!vcpu->fpu_active) | |
334df50a | 1233 | cr0 |= X86_CR0_TS; |
709ddebf JR |
1234 | /* |
1235 | * re-enable caching here because the QEMU bios | |
1236 | * does not do it - this results in some delay at | |
1237 | * reboot | |
1238 | */ | |
1239 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1240 | svm->vmcb->save.cr0 = cr0; |
d225157b | 1241 | update_cr0_intercept(svm); |
6aa8b732 AK |
1242 | } |
1243 | ||
1244 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1245 | { | |
6394b649 | 1246 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1247 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1248 | ||
1249 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1250 | force_new_asid(vcpu); | |
6394b649 | 1251 | |
ec077263 JR |
1252 | vcpu->arch.cr4 = cr4; |
1253 | if (!npt_enabled) | |
1254 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1255 | cr4 |= host_cr4_mce; |
ec077263 | 1256 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1257 | } |
1258 | ||
1259 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1260 | struct kvm_segment *var, int seg) | |
1261 | { | |
a2fa3e9f | 1262 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1263 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1264 | ||
1265 | s->base = var->base; | |
1266 | s->limit = var->limit; | |
1267 | s->selector = var->selector; | |
1268 | if (var->unusable) | |
1269 | s->attrib = 0; | |
1270 | else { | |
1271 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1272 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1273 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1274 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1275 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1276 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1277 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1278 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1279 | } | |
1280 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1281 | svm->vmcb->save.cpl |
1282 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1283 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1284 | ||
1285 | } | |
1286 | ||
44c11430 | 1287 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1288 | { |
d0bfb940 JK |
1289 | struct vcpu_svm *svm = to_svm(vcpu); |
1290 | ||
d0bfb940 JK |
1291 | svm->vmcb->control.intercept_exceptions &= |
1292 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 | 1293 | |
6be7d306 | 1294 | if (svm->nmi_singlestep) |
44c11430 GN |
1295 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); |
1296 | ||
d0bfb940 JK |
1297 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1298 | if (vcpu->guest_debug & | |
1299 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1300 | svm->vmcb->control.intercept_exceptions |= | |
1301 | 1 << DB_VECTOR; | |
1302 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1303 | svm->vmcb->control.intercept_exceptions |= | |
1304 | 1 << BP_VECTOR; | |
1305 | } else | |
1306 | vcpu->guest_debug = 0; | |
44c11430 GN |
1307 | } |
1308 | ||
355be0b9 | 1309 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1310 | { |
44c11430 GN |
1311 | struct vcpu_svm *svm = to_svm(vcpu); |
1312 | ||
ae675ef0 JK |
1313 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1314 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1315 | else | |
1316 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1317 | ||
355be0b9 | 1318 | update_db_intercept(vcpu); |
6aa8b732 AK |
1319 | } |
1320 | ||
1321 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1322 | { | |
94dfbdb3 | 1323 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1324 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1325 | #endif |
6aa8b732 AK |
1326 | } |
1327 | ||
1328 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1329 | { | |
94dfbdb3 | 1330 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1331 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1332 | #endif |
6aa8b732 AK |
1333 | } |
1334 | ||
0fe1e009 | 1335 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd) |
6aa8b732 | 1336 | { |
0fe1e009 TH |
1337 | if (sd->next_asid > sd->max_asid) { |
1338 | ++sd->asid_generation; | |
1339 | sd->next_asid = 1; | |
a2fa3e9f | 1340 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1341 | } |
1342 | ||
0fe1e009 TH |
1343 | svm->asid_generation = sd->asid_generation; |
1344 | svm->vmcb->control.asid = sd->next_asid++; | |
6aa8b732 AK |
1345 | } |
1346 | ||
020df079 | 1347 | static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value) |
6aa8b732 | 1348 | { |
42dbaa5a | 1349 | struct vcpu_svm *svm = to_svm(vcpu); |
42dbaa5a | 1350 | |
020df079 | 1351 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
1352 | } |
1353 | ||
851ba692 | 1354 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1355 | { |
6aa8b732 AK |
1356 | u64 fault_address; |
1357 | u32 error_code; | |
6aa8b732 | 1358 | |
a2fa3e9f GH |
1359 | fault_address = svm->vmcb->control.exit_info_2; |
1360 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1361 | |
229456fc | 1362 | trace_kvm_page_fault(fault_address, error_code); |
52c7847d AK |
1363 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) |
1364 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1365 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1366 | } |
1367 | ||
851ba692 | 1368 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1369 | { |
851ba692 AK |
1370 | struct kvm_run *kvm_run = svm->vcpu.run; |
1371 | ||
d0bfb940 | 1372 | if (!(svm->vcpu.guest_debug & |
44c11430 | 1373 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
6be7d306 | 1374 | !svm->nmi_singlestep) { |
d0bfb940 JK |
1375 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1376 | return 1; | |
1377 | } | |
44c11430 | 1378 | |
6be7d306 JK |
1379 | if (svm->nmi_singlestep) { |
1380 | svm->nmi_singlestep = false; | |
44c11430 GN |
1381 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) |
1382 | svm->vmcb->save.rflags &= | |
1383 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1384 | update_db_intercept(&svm->vcpu); | |
1385 | } | |
1386 | ||
1387 | if (svm->vcpu.guest_debug & | |
e0231715 | 1388 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) { |
44c11430 GN |
1389 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1390 | kvm_run->debug.arch.pc = | |
1391 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1392 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | return 1; | |
d0bfb940 JK |
1397 | } |
1398 | ||
851ba692 | 1399 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1400 | { |
851ba692 AK |
1401 | struct kvm_run *kvm_run = svm->vcpu.run; |
1402 | ||
d0bfb940 JK |
1403 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1404 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1405 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1406 | return 0; | |
1407 | } | |
1408 | ||
851ba692 | 1409 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1410 | { |
1411 | int er; | |
1412 | ||
851ba692 | 1413 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1414 | if (er != EMULATE_DONE) |
7ee5d940 | 1415 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1416 | return 1; |
1417 | } | |
1418 | ||
6b52d186 | 1419 | static void svm_fpu_activate(struct kvm_vcpu *vcpu) |
7807fa6c | 1420 | { |
6b52d186 | 1421 | struct vcpu_svm *svm = to_svm(vcpu); |
66a562f7 JR |
1422 | u32 excp; |
1423 | ||
1424 | if (is_nested(svm)) { | |
1425 | u32 h_excp, n_excp; | |
1426 | ||
1427 | h_excp = svm->nested.hsave->control.intercept_exceptions; | |
1428 | n_excp = svm->nested.intercept_exceptions; | |
1429 | h_excp &= ~(1 << NM_VECTOR); | |
1430 | excp = h_excp | n_excp; | |
1431 | } else { | |
1432 | excp = svm->vmcb->control.intercept_exceptions; | |
e0231715 | 1433 | excp &= ~(1 << NM_VECTOR); |
66a562f7 JR |
1434 | } |
1435 | ||
1436 | svm->vmcb->control.intercept_exceptions = excp; | |
1437 | ||
e756fc62 | 1438 | svm->vcpu.fpu_active = 1; |
d225157b | 1439 | update_cr0_intercept(svm); |
6b52d186 | 1440 | } |
a2fa3e9f | 1441 | |
6b52d186 AK |
1442 | static int nm_interception(struct vcpu_svm *svm) |
1443 | { | |
1444 | svm_fpu_activate(&svm->vcpu); | |
a2fa3e9f | 1445 | return 1; |
7807fa6c AL |
1446 | } |
1447 | ||
67ec6607 JR |
1448 | static bool is_erratum_383(void) |
1449 | { | |
1450 | int err, i; | |
1451 | u64 value; | |
1452 | ||
1453 | if (!erratum_383_found) | |
1454 | return false; | |
1455 | ||
1456 | value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); | |
1457 | if (err) | |
1458 | return false; | |
1459 | ||
1460 | /* Bit 62 may or may not be set for this mce */ | |
1461 | value &= ~(1ULL << 62); | |
1462 | ||
1463 | if (value != 0xb600000000010015ULL) | |
1464 | return false; | |
1465 | ||
1466 | /* Clear MCi_STATUS registers */ | |
1467 | for (i = 0; i < 6; ++i) | |
1468 | native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); | |
1469 | ||
1470 | value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); | |
1471 | if (!err) { | |
1472 | u32 low, high; | |
1473 | ||
1474 | value &= ~(1ULL << 2); | |
1475 | low = lower_32_bits(value); | |
1476 | high = upper_32_bits(value); | |
1477 | ||
1478 | native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); | |
1479 | } | |
1480 | ||
1481 | /* Flush tlb to evict multi-match entries */ | |
1482 | __flush_tlb_all(); | |
1483 | ||
1484 | return true; | |
1485 | } | |
1486 | ||
fe5913e4 | 1487 | static void svm_handle_mce(struct vcpu_svm *svm) |
53371b50 | 1488 | { |
67ec6607 JR |
1489 | if (is_erratum_383()) { |
1490 | /* | |
1491 | * Erratum 383 triggered. Guest state is corrupt so kill the | |
1492 | * guest. | |
1493 | */ | |
1494 | pr_err("KVM: Guest triggered AMD Erratum 383\n"); | |
1495 | ||
a8eeb04a | 1496 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu); |
67ec6607 JR |
1497 | |
1498 | return; | |
1499 | } | |
1500 | ||
53371b50 JR |
1501 | /* |
1502 | * On an #MC intercept the MCE handler is not called automatically in | |
1503 | * the host. So do it by hand here. | |
1504 | */ | |
1505 | asm volatile ( | |
1506 | "int $0x12\n"); | |
1507 | /* not sure if we ever come back to this point */ | |
1508 | ||
fe5913e4 JR |
1509 | return; |
1510 | } | |
1511 | ||
1512 | static int mc_interception(struct vcpu_svm *svm) | |
1513 | { | |
53371b50 JR |
1514 | return 1; |
1515 | } | |
1516 | ||
851ba692 | 1517 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1518 | { |
851ba692 AK |
1519 | struct kvm_run *kvm_run = svm->vcpu.run; |
1520 | ||
46fe4ddd JR |
1521 | /* |
1522 | * VMCB is undefined after a SHUTDOWN intercept | |
1523 | * so reinitialize it. | |
1524 | */ | |
a2fa3e9f | 1525 | clear_page(svm->vmcb); |
e6101a96 | 1526 | init_vmcb(svm); |
46fe4ddd JR |
1527 | |
1528 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1529 | return 0; | |
1530 | } | |
1531 | ||
851ba692 | 1532 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1533 | { |
cf8f70bf | 1534 | struct kvm_vcpu *vcpu = &svm->vcpu; |
d77c26fc | 1535 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1536 | int size, in, string; |
039576c0 | 1537 | unsigned port; |
6aa8b732 | 1538 | |
e756fc62 | 1539 | ++svm->vcpu.stat.io_exits; |
e70669ab | 1540 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
039576c0 | 1541 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
cf8f70bf | 1542 | if (string || in) |
6d77dbfc | 1543 | return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE; |
cf8f70bf | 1544 | |
039576c0 AK |
1545 | port = io_info >> 16; |
1546 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
cf8f70bf | 1547 | svm->next_rip = svm->vmcb->control.exit_info_2; |
e93f36bc | 1548 | skip_emulated_instruction(&svm->vcpu); |
cf8f70bf GN |
1549 | |
1550 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
1551 | } |
1552 | ||
851ba692 | 1553 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1554 | { |
1555 | return 1; | |
1556 | } | |
1557 | ||
851ba692 | 1558 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1559 | { |
1560 | ++svm->vcpu.stat.irq_exits; | |
1561 | return 1; | |
1562 | } | |
1563 | ||
851ba692 | 1564 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1565 | { |
1566 | return 1; | |
1567 | } | |
1568 | ||
851ba692 | 1569 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1570 | { |
5fdbf976 | 1571 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1572 | skip_emulated_instruction(&svm->vcpu); |
1573 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1574 | } |
1575 | ||
851ba692 | 1576 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1577 | { |
5fdbf976 | 1578 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1579 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1580 | kvm_emulate_hypercall(&svm->vcpu); |
1581 | return 1; | |
02e235bc AK |
1582 | } |
1583 | ||
c0725420 AG |
1584 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1585 | { | |
f6801dff | 1586 | if (!(svm->vcpu.arch.efer & EFER_SVME) |
c0725420 AG |
1587 | || !is_paging(&svm->vcpu)) { |
1588 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1589 | return 1; | |
1590 | } | |
1591 | ||
1592 | if (svm->vmcb->save.cpl) { | |
1593 | kvm_inject_gp(&svm->vcpu, 0); | |
1594 | return 1; | |
1595 | } | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
cf74a78b AG |
1600 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1601 | bool has_error_code, u32 error_code) | |
1602 | { | |
b8e88bc8 JR |
1603 | int vmexit; |
1604 | ||
0295ad7d JR |
1605 | if (!is_nested(svm)) |
1606 | return 0; | |
cf74a78b | 1607 | |
0295ad7d JR |
1608 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1609 | svm->vmcb->control.exit_code_hi = 0; | |
1610 | svm->vmcb->control.exit_info_1 = error_code; | |
1611 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1612 | ||
b8e88bc8 JR |
1613 | vmexit = nested_svm_intercept(svm); |
1614 | if (vmexit == NESTED_EXIT_DONE) | |
1615 | svm->nested.exit_required = true; | |
1616 | ||
1617 | return vmexit; | |
cf74a78b AG |
1618 | } |
1619 | ||
8fe54654 JR |
1620 | /* This function returns true if it is save to enable the irq window */ |
1621 | static inline bool nested_svm_intr(struct vcpu_svm *svm) | |
cf74a78b | 1622 | { |
26666957 | 1623 | if (!is_nested(svm)) |
8fe54654 | 1624 | return true; |
cf74a78b | 1625 | |
26666957 | 1626 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
8fe54654 | 1627 | return true; |
cf74a78b | 1628 | |
26666957 | 1629 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
8fe54654 | 1630 | return false; |
cf74a78b | 1631 | |
197717d5 JR |
1632 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1633 | svm->vmcb->control.exit_info_1 = 0; | |
1634 | svm->vmcb->control.exit_info_2 = 0; | |
26666957 | 1635 | |
cd3ff653 JR |
1636 | if (svm->nested.intercept & 1ULL) { |
1637 | /* | |
1638 | * The #vmexit can't be emulated here directly because this | |
1639 | * code path runs with irqs and preemtion disabled. A | |
1640 | * #vmexit emulation might sleep. Only signal request for | |
1641 | * the #vmexit here. | |
1642 | */ | |
1643 | svm->nested.exit_required = true; | |
236649de | 1644 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
8fe54654 | 1645 | return false; |
cf74a78b AG |
1646 | } |
1647 | ||
8fe54654 | 1648 | return true; |
cf74a78b AG |
1649 | } |
1650 | ||
887f500c JR |
1651 | /* This function returns true if it is save to enable the nmi window */ |
1652 | static inline bool nested_svm_nmi(struct vcpu_svm *svm) | |
1653 | { | |
1654 | if (!is_nested(svm)) | |
1655 | return true; | |
1656 | ||
1657 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) | |
1658 | return true; | |
1659 | ||
1660 | svm->vmcb->control.exit_code = SVM_EXIT_NMI; | |
1661 | svm->nested.exit_required = true; | |
1662 | ||
1663 | return false; | |
cf74a78b AG |
1664 | } |
1665 | ||
7597f129 | 1666 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page) |
34f80cfa JR |
1667 | { |
1668 | struct page *page; | |
1669 | ||
6c3bd3d7 JR |
1670 | might_sleep(); |
1671 | ||
34f80cfa | 1672 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1673 | if (is_error_page(page)) |
1674 | goto error; | |
1675 | ||
7597f129 JR |
1676 | *_page = page; |
1677 | ||
1678 | return kmap(page); | |
34f80cfa JR |
1679 | |
1680 | error: | |
1681 | kvm_release_page_clean(page); | |
1682 | kvm_inject_gp(&svm->vcpu, 0); | |
1683 | ||
1684 | return NULL; | |
1685 | } | |
1686 | ||
7597f129 | 1687 | static void nested_svm_unmap(struct page *page) |
34f80cfa | 1688 | { |
7597f129 | 1689 | kunmap(page); |
34f80cfa JR |
1690 | kvm_release_page_dirty(page); |
1691 | } | |
34f80cfa | 1692 | |
ce2ac085 JR |
1693 | static int nested_svm_intercept_ioio(struct vcpu_svm *svm) |
1694 | { | |
1695 | unsigned port; | |
1696 | u8 val, bit; | |
1697 | u64 gpa; | |
34f80cfa | 1698 | |
ce2ac085 JR |
1699 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT))) |
1700 | return NESTED_EXIT_HOST; | |
34f80cfa | 1701 | |
ce2ac085 JR |
1702 | port = svm->vmcb->control.exit_info_1 >> 16; |
1703 | gpa = svm->nested.vmcb_iopm + (port / 8); | |
1704 | bit = port % 8; | |
1705 | val = 0; | |
1706 | ||
1707 | if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1)) | |
1708 | val &= (1 << bit); | |
1709 | ||
1710 | return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; | |
34f80cfa JR |
1711 | } |
1712 | ||
d2477826 | 1713 | static int nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1714 | { |
0d6b3537 JR |
1715 | u32 offset, msr, value; |
1716 | int write, mask; | |
4c2161ae | 1717 | |
3d62d9aa | 1718 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
d2477826 | 1719 | return NESTED_EXIT_HOST; |
3d62d9aa | 1720 | |
0d6b3537 JR |
1721 | msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1722 | offset = svm_msrpm_offset(msr); | |
1723 | write = svm->vmcb->control.exit_info_1 & 1; | |
1724 | mask = 1 << ((2 * (msr & 0xf)) + write); | |
3d62d9aa | 1725 | |
0d6b3537 JR |
1726 | if (offset == MSR_INVALID) |
1727 | return NESTED_EXIT_DONE; | |
4c2161ae | 1728 | |
0d6b3537 JR |
1729 | /* Offset is in 32 bit units but need in 8 bit units */ |
1730 | offset *= 4; | |
4c2161ae | 1731 | |
0d6b3537 JR |
1732 | if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4)) |
1733 | return NESTED_EXIT_DONE; | |
3d62d9aa | 1734 | |
0d6b3537 | 1735 | return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; |
4c2161ae JR |
1736 | } |
1737 | ||
410e4d57 | 1738 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1739 | { |
cf74a78b | 1740 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1741 | |
410e4d57 JR |
1742 | switch (exit_code) { |
1743 | case SVM_EXIT_INTR: | |
1744 | case SVM_EXIT_NMI: | |
ff47a49b | 1745 | case SVM_EXIT_EXCP_BASE + MC_VECTOR: |
410e4d57 | 1746 | return NESTED_EXIT_HOST; |
410e4d57 | 1747 | case SVM_EXIT_NPF: |
e0231715 | 1748 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1749 | if (npt_enabled) |
1750 | return NESTED_EXIT_HOST; | |
1751 | break; | |
410e4d57 | 1752 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: |
e0231715 | 1753 | /* When we're shadowing, trap PFs */ |
410e4d57 JR |
1754 | if (!npt_enabled) |
1755 | return NESTED_EXIT_HOST; | |
1756 | break; | |
66a562f7 JR |
1757 | case SVM_EXIT_EXCP_BASE + NM_VECTOR: |
1758 | nm_interception(svm); | |
1759 | break; | |
410e4d57 JR |
1760 | default: |
1761 | break; | |
cf74a78b AG |
1762 | } |
1763 | ||
410e4d57 JR |
1764 | return NESTED_EXIT_CONTINUE; |
1765 | } | |
1766 | ||
1767 | /* | |
1768 | * If this function returns true, this #vmexit was already handled | |
1769 | */ | |
b8e88bc8 | 1770 | static int nested_svm_intercept(struct vcpu_svm *svm) |
410e4d57 JR |
1771 | { |
1772 | u32 exit_code = svm->vmcb->control.exit_code; | |
1773 | int vmexit = NESTED_EXIT_HOST; | |
1774 | ||
cf74a78b | 1775 | switch (exit_code) { |
9c4e40b9 | 1776 | case SVM_EXIT_MSR: |
3d62d9aa | 1777 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1778 | break; |
ce2ac085 JR |
1779 | case SVM_EXIT_IOIO: |
1780 | vmexit = nested_svm_intercept_ioio(svm); | |
1781 | break; | |
cf74a78b AG |
1782 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1783 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1784 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1785 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1786 | break; |
1787 | } | |
1788 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1789 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1790 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1791 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1792 | break; |
1793 | } | |
1794 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1795 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1796 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1797 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1798 | break; |
1799 | } | |
1800 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1801 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1802 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1803 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1804 | break; |
1805 | } | |
1806 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1807 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1808 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1809 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1810 | break; |
1811 | } | |
228070b1 JR |
1812 | case SVM_EXIT_ERR: { |
1813 | vmexit = NESTED_EXIT_DONE; | |
1814 | break; | |
1815 | } | |
cf74a78b AG |
1816 | default: { |
1817 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
aad42c64 | 1818 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1819 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1820 | } |
1821 | } | |
1822 | ||
b8e88bc8 JR |
1823 | return vmexit; |
1824 | } | |
1825 | ||
1826 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1827 | { | |
1828 | int vmexit; | |
1829 | ||
1830 | vmexit = nested_svm_intercept(svm); | |
1831 | ||
1832 | if (vmexit == NESTED_EXIT_DONE) | |
9c4e40b9 | 1833 | nested_svm_vmexit(svm); |
9c4e40b9 JR |
1834 | |
1835 | return vmexit; | |
cf74a78b AG |
1836 | } |
1837 | ||
0460a979 JR |
1838 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1839 | { | |
1840 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1841 | struct vmcb_control_area *from = &from_vmcb->control; | |
1842 | ||
1843 | dst->intercept_cr_read = from->intercept_cr_read; | |
1844 | dst->intercept_cr_write = from->intercept_cr_write; | |
1845 | dst->intercept_dr_read = from->intercept_dr_read; | |
1846 | dst->intercept_dr_write = from->intercept_dr_write; | |
1847 | dst->intercept_exceptions = from->intercept_exceptions; | |
1848 | dst->intercept = from->intercept; | |
1849 | dst->iopm_base_pa = from->iopm_base_pa; | |
1850 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1851 | dst->tsc_offset = from->tsc_offset; | |
1852 | dst->asid = from->asid; | |
1853 | dst->tlb_ctl = from->tlb_ctl; | |
1854 | dst->int_ctl = from->int_ctl; | |
1855 | dst->int_vector = from->int_vector; | |
1856 | dst->int_state = from->int_state; | |
1857 | dst->exit_code = from->exit_code; | |
1858 | dst->exit_code_hi = from->exit_code_hi; | |
1859 | dst->exit_info_1 = from->exit_info_1; | |
1860 | dst->exit_info_2 = from->exit_info_2; | |
1861 | dst->exit_int_info = from->exit_int_info; | |
1862 | dst->exit_int_info_err = from->exit_int_info_err; | |
1863 | dst->nested_ctl = from->nested_ctl; | |
1864 | dst->event_inj = from->event_inj; | |
1865 | dst->event_inj_err = from->event_inj_err; | |
1866 | dst->nested_cr3 = from->nested_cr3; | |
1867 | dst->lbr_ctl = from->lbr_ctl; | |
1868 | } | |
1869 | ||
34f80cfa | 1870 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1871 | { |
34f80cfa | 1872 | struct vmcb *nested_vmcb; |
e6aa9abd | 1873 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1874 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 1875 | struct page *page; |
cf74a78b | 1876 | |
17897f36 JR |
1877 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
1878 | vmcb->control.exit_info_1, | |
1879 | vmcb->control.exit_info_2, | |
1880 | vmcb->control.exit_int_info, | |
1881 | vmcb->control.exit_int_info_err); | |
1882 | ||
7597f129 | 1883 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page); |
34f80cfa JR |
1884 | if (!nested_vmcb) |
1885 | return 1; | |
1886 | ||
06fc7772 JR |
1887 | /* Exit nested SVM mode */ |
1888 | svm->nested.vmcb = 0; | |
1889 | ||
cf74a78b | 1890 | /* Give the current vmcb to the guest */ |
33740e40 JR |
1891 | disable_gif(svm); |
1892 | ||
1893 | nested_vmcb->save.es = vmcb->save.es; | |
1894 | nested_vmcb->save.cs = vmcb->save.cs; | |
1895 | nested_vmcb->save.ss = vmcb->save.ss; | |
1896 | nested_vmcb->save.ds = vmcb->save.ds; | |
1897 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1898 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
cdbbdc12 | 1899 | nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu); |
2be4fc7a | 1900 | nested_vmcb->save.cr3 = svm->vcpu.arch.cr3; |
33740e40 | 1901 | nested_vmcb->save.cr2 = vmcb->save.cr2; |
cdbbdc12 | 1902 | nested_vmcb->save.cr4 = svm->vcpu.arch.cr4; |
33740e40 JR |
1903 | nested_vmcb->save.rflags = vmcb->save.rflags; |
1904 | nested_vmcb->save.rip = vmcb->save.rip; | |
1905 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1906 | nested_vmcb->save.rax = vmcb->save.rax; | |
1907 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1908 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1909 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1910 | ||
1911 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1912 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1913 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1914 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1915 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1916 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1917 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1918 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1919 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
8d23c466 AG |
1920 | |
1921 | /* | |
1922 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
1923 | * to make sure that we do not lose injected events. So check event_inj | |
1924 | * here and copy it to exit_int_info if it is valid. | |
1925 | * Exit_int_info and event_inj can't be both valid because the case | |
1926 | * below only happens on a VMRUN instruction intercept which has | |
1927 | * no valid exit_int_info set. | |
1928 | */ | |
1929 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
1930 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
1931 | ||
1932 | nc->exit_int_info = vmcb->control.event_inj; | |
1933 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
1934 | } | |
1935 | ||
33740e40 JR |
1936 | nested_vmcb->control.tlb_ctl = 0; |
1937 | nested_vmcb->control.event_inj = 0; | |
1938 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
1939 | |
1940 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1941 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1942 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1943 | ||
cf74a78b | 1944 | /* Restore the original control entries */ |
0460a979 | 1945 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b | 1946 | |
219b65dc AG |
1947 | kvm_clear_exception_queue(&svm->vcpu); |
1948 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b AG |
1949 | |
1950 | /* Restore selected save entries */ | |
1951 | svm->vmcb->save.es = hsave->save.es; | |
1952 | svm->vmcb->save.cs = hsave->save.cs; | |
1953 | svm->vmcb->save.ss = hsave->save.ss; | |
1954 | svm->vmcb->save.ds = hsave->save.ds; | |
1955 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1956 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1957 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1958 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1959 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1960 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1961 | if (npt_enabled) { | |
1962 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1963 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1964 | } else { | |
2390218b | 1965 | (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3); |
cf74a78b AG |
1966 | } |
1967 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1968 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1969 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1970 | svm->vmcb->save.dr7 = 0; | |
1971 | svm->vmcb->save.cpl = 0; | |
1972 | svm->vmcb->control.exit_int_info = 0; | |
1973 | ||
7597f129 | 1974 | nested_svm_unmap(page); |
cf74a78b AG |
1975 | |
1976 | kvm_mmu_reset_context(&svm->vcpu); | |
1977 | kvm_mmu_load(&svm->vcpu); | |
1978 | ||
1979 | return 0; | |
1980 | } | |
3d6368ef | 1981 | |
9738b2c9 | 1982 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 1983 | { |
323c3d80 JR |
1984 | /* |
1985 | * This function merges the msr permission bitmaps of kvm and the | |
1986 | * nested vmcb. It is omptimized in that it only merges the parts where | |
1987 | * the kvm msr permission bitmap may contain zero bits | |
1988 | */ | |
3d6368ef | 1989 | int i; |
9738b2c9 | 1990 | |
323c3d80 JR |
1991 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
1992 | return true; | |
9738b2c9 | 1993 | |
323c3d80 JR |
1994 | for (i = 0; i < MSRPM_OFFSETS; i++) { |
1995 | u32 value, p; | |
1996 | u64 offset; | |
9738b2c9 | 1997 | |
323c3d80 JR |
1998 | if (msrpm_offsets[i] == 0xffffffff) |
1999 | break; | |
3d6368ef | 2000 | |
0d6b3537 JR |
2001 | p = msrpm_offsets[i]; |
2002 | offset = svm->nested.vmcb_msrpm + (p * 4); | |
323c3d80 JR |
2003 | |
2004 | if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4)) | |
2005 | return false; | |
2006 | ||
2007 | svm->nested.msrpm[p] = svm->msrpm[p] | value; | |
2008 | } | |
3d6368ef | 2009 | |
323c3d80 | 2010 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
9738b2c9 JR |
2011 | |
2012 | return true; | |
3d6368ef AG |
2013 | } |
2014 | ||
9738b2c9 | 2015 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 2016 | { |
9738b2c9 | 2017 | struct vmcb *nested_vmcb; |
e6aa9abd | 2018 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 2019 | struct vmcb *vmcb = svm->vmcb; |
7597f129 | 2020 | struct page *page; |
06fc7772 | 2021 | u64 vmcb_gpa; |
3d6368ef | 2022 | |
06fc7772 | 2023 | vmcb_gpa = svm->vmcb->save.rax; |
3d6368ef | 2024 | |
7597f129 | 2025 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9738b2c9 JR |
2026 | if (!nested_vmcb) |
2027 | return false; | |
2028 | ||
ecf1405d | 2029 | trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa, |
0ac406de JR |
2030 | nested_vmcb->save.rip, |
2031 | nested_vmcb->control.int_ctl, | |
2032 | nested_vmcb->control.event_inj, | |
2033 | nested_vmcb->control.nested_ctl); | |
2034 | ||
2e554e8d JR |
2035 | trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read, |
2036 | nested_vmcb->control.intercept_cr_write, | |
2037 | nested_vmcb->control.intercept_exceptions, | |
2038 | nested_vmcb->control.intercept); | |
2039 | ||
3d6368ef | 2040 | /* Clear internal status */ |
219b65dc AG |
2041 | kvm_clear_exception_queue(&svm->vcpu); |
2042 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef | 2043 | |
e0231715 JR |
2044 | /* |
2045 | * Save the old vmcb, so we don't need to pick what we save, but can | |
2046 | * restore everything when a VMEXIT occurs | |
2047 | */ | |
defbba56 JR |
2048 | hsave->save.es = vmcb->save.es; |
2049 | hsave->save.cs = vmcb->save.cs; | |
2050 | hsave->save.ss = vmcb->save.ss; | |
2051 | hsave->save.ds = vmcb->save.ds; | |
2052 | hsave->save.gdtr = vmcb->save.gdtr; | |
2053 | hsave->save.idtr = vmcb->save.idtr; | |
f6801dff | 2054 | hsave->save.efer = svm->vcpu.arch.efer; |
4d4ec087 | 2055 | hsave->save.cr0 = kvm_read_cr0(&svm->vcpu); |
defbba56 JR |
2056 | hsave->save.cr4 = svm->vcpu.arch.cr4; |
2057 | hsave->save.rflags = vmcb->save.rflags; | |
2058 | hsave->save.rip = svm->next_rip; | |
2059 | hsave->save.rsp = vmcb->save.rsp; | |
2060 | hsave->save.rax = vmcb->save.rax; | |
2061 | if (npt_enabled) | |
2062 | hsave->save.cr3 = vmcb->save.cr3; | |
2063 | else | |
2064 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
2065 | ||
0460a979 | 2066 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
2067 | |
2068 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
2069 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
2070 | else | |
2071 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
2072 | ||
2073 | /* Load the nested guest state */ | |
2074 | svm->vmcb->save.es = nested_vmcb->save.es; | |
2075 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
2076 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
2077 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
2078 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
2079 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
2080 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
2081 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
2082 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
2083 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
2084 | if (npt_enabled) { | |
2085 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
2086 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
0e5cbe36 | 2087 | } else |
2390218b | 2088 | (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); |
0e5cbe36 JR |
2089 | |
2090 | /* Guest paging mode is active - reset mmu */ | |
2091 | kvm_mmu_reset_context(&svm->vcpu); | |
2092 | ||
defbba56 | 2093 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
2094 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
2095 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
2096 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
e0231715 | 2097 | |
3d6368ef AG |
2098 | /* In case we don't even reach vcpu_run, the fields are not updated */ |
2099 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
2100 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
2101 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
2102 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
2103 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
2104 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
2105 | ||
f7138538 | 2106 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL; |
ce2ac085 | 2107 | svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL; |
3d6368ef | 2108 | |
aad42c64 JR |
2109 | /* cache intercepts */ |
2110 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
2111 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
2112 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
2113 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
2114 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
2115 | svm->nested.intercept = nested_vmcb->control.intercept; | |
2116 | ||
3d6368ef | 2117 | force_new_asid(&svm->vcpu); |
3d6368ef | 2118 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
3d6368ef AG |
2119 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) |
2120 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
2121 | else | |
2122 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
2123 | ||
88ab24ad JR |
2124 | if (svm->vcpu.arch.hflags & HF_VINTR_MASK) { |
2125 | /* We only want the cr8 intercept bits of the guest */ | |
2126 | svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK; | |
2127 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
2128 | } | |
2129 | ||
0d945bd9 JR |
2130 | /* We don't want to see VMMCALLs from a nested guest */ |
2131 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL); | |
2132 | ||
e0231715 JR |
2133 | /* |
2134 | * We don't want a nested guest to be more powerful than the guest, so | |
2135 | * all intercepts are ORed | |
2136 | */ | |
88ab24ad JR |
2137 | svm->vmcb->control.intercept_cr_read |= |
2138 | nested_vmcb->control.intercept_cr_read; | |
2139 | svm->vmcb->control.intercept_cr_write |= | |
2140 | nested_vmcb->control.intercept_cr_write; | |
2141 | svm->vmcb->control.intercept_dr_read |= | |
2142 | nested_vmcb->control.intercept_dr_read; | |
2143 | svm->vmcb->control.intercept_dr_write |= | |
2144 | nested_vmcb->control.intercept_dr_write; | |
2145 | svm->vmcb->control.intercept_exceptions |= | |
2146 | nested_vmcb->control.intercept_exceptions; | |
2147 | ||
2148 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
2149 | ||
2150 | svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl; | |
3d6368ef AG |
2151 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; |
2152 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
2153 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
3d6368ef AG |
2154 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; |
2155 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
2156 | ||
7597f129 | 2157 | nested_svm_unmap(page); |
9738b2c9 | 2158 | |
06fc7772 JR |
2159 | /* nested_vmcb is our indicator if nested SVM is activated */ |
2160 | svm->nested.vmcb = vmcb_gpa; | |
9738b2c9 | 2161 | |
2af9194d | 2162 | enable_gif(svm); |
3d6368ef | 2163 | |
9738b2c9 | 2164 | return true; |
3d6368ef AG |
2165 | } |
2166 | ||
9966bf68 | 2167 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
2168 | { |
2169 | to_vmcb->save.fs = from_vmcb->save.fs; | |
2170 | to_vmcb->save.gs = from_vmcb->save.gs; | |
2171 | to_vmcb->save.tr = from_vmcb->save.tr; | |
2172 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
2173 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
2174 | to_vmcb->save.star = from_vmcb->save.star; | |
2175 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
2176 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
2177 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
2178 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
2179 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
2180 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
2181 | } |
2182 | ||
851ba692 | 2183 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 2184 | { |
9966bf68 | 2185 | struct vmcb *nested_vmcb; |
7597f129 | 2186 | struct page *page; |
9966bf68 | 2187 | |
5542675b AG |
2188 | if (nested_svm_check_permissions(svm)) |
2189 | return 1; | |
2190 | ||
2191 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2192 | skip_emulated_instruction(&svm->vcpu); | |
2193 | ||
7597f129 | 2194 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2195 | if (!nested_vmcb) |
2196 | return 1; | |
2197 | ||
2198 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
7597f129 | 2199 | nested_svm_unmap(page); |
5542675b AG |
2200 | |
2201 | return 1; | |
2202 | } | |
2203 | ||
851ba692 | 2204 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 2205 | { |
9966bf68 | 2206 | struct vmcb *nested_vmcb; |
7597f129 | 2207 | struct page *page; |
9966bf68 | 2208 | |
5542675b AG |
2209 | if (nested_svm_check_permissions(svm)) |
2210 | return 1; | |
2211 | ||
2212 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2213 | skip_emulated_instruction(&svm->vcpu); | |
2214 | ||
7597f129 | 2215 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page); |
9966bf68 JR |
2216 | if (!nested_vmcb) |
2217 | return 1; | |
2218 | ||
2219 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
7597f129 | 2220 | nested_svm_unmap(page); |
5542675b AG |
2221 | |
2222 | return 1; | |
2223 | } | |
2224 | ||
851ba692 | 2225 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef | 2226 | { |
3d6368ef AG |
2227 | if (nested_svm_check_permissions(svm)) |
2228 | return 1; | |
2229 | ||
2230 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2231 | skip_emulated_instruction(&svm->vcpu); | |
2232 | ||
9738b2c9 | 2233 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
2234 | return 1; |
2235 | ||
9738b2c9 | 2236 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
2237 | goto failed; |
2238 | ||
2239 | return 1; | |
2240 | ||
2241 | failed: | |
2242 | ||
2243 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
2244 | svm->vmcb->control.exit_code_hi = 0; | |
2245 | svm->vmcb->control.exit_info_1 = 0; | |
2246 | svm->vmcb->control.exit_info_2 = 0; | |
2247 | ||
2248 | nested_svm_vmexit(svm); | |
3d6368ef AG |
2249 | |
2250 | return 1; | |
2251 | } | |
2252 | ||
851ba692 | 2253 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2254 | { |
2255 | if (nested_svm_check_permissions(svm)) | |
2256 | return 1; | |
2257 | ||
2258 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2259 | skip_emulated_instruction(&svm->vcpu); | |
2260 | ||
2af9194d | 2261 | enable_gif(svm); |
1371d904 AG |
2262 | |
2263 | return 1; | |
2264 | } | |
2265 | ||
851ba692 | 2266 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
2267 | { |
2268 | if (nested_svm_check_permissions(svm)) | |
2269 | return 1; | |
2270 | ||
2271 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2272 | skip_emulated_instruction(&svm->vcpu); | |
2273 | ||
2af9194d | 2274 | disable_gif(svm); |
1371d904 AG |
2275 | |
2276 | /* After a CLGI no interrupts should come */ | |
2277 | svm_clear_vintr(svm); | |
2278 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
2279 | ||
2280 | return 1; | |
2281 | } | |
2282 | ||
851ba692 | 2283 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
2284 | { |
2285 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ff092385 | 2286 | |
ec1ff790 JR |
2287 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
2288 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
2289 | ||
ff092385 AG |
2290 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
2291 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
2292 | ||
2293 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
2294 | skip_emulated_instruction(&svm->vcpu); | |
2295 | return 1; | |
2296 | } | |
2297 | ||
532a46b9 JR |
2298 | static int skinit_interception(struct vcpu_svm *svm) |
2299 | { | |
2300 | trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]); | |
2301 | ||
2302 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
2303 | return 1; | |
2304 | } | |
2305 | ||
851ba692 | 2306 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 2307 | { |
7ee5d940 | 2308 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
2309 | return 1; |
2310 | } | |
2311 | ||
851ba692 | 2312 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 2313 | { |
37817f29 | 2314 | u16 tss_selector; |
64a7ec06 GN |
2315 | int reason; |
2316 | int int_type = svm->vmcb->control.exit_int_info & | |
2317 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2318 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2319 | uint32_t type = |
2320 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2321 | uint32_t idt_v = | |
2322 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
e269fb21 JK |
2323 | bool has_error_code = false; |
2324 | u32 error_code = 0; | |
37817f29 IE |
2325 | |
2326 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2327 | |
37817f29 IE |
2328 | if (svm->vmcb->control.exit_info_2 & |
2329 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2330 | reason = TASK_SWITCH_IRET; |
2331 | else if (svm->vmcb->control.exit_info_2 & | |
2332 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2333 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2334 | else if (idt_v) |
64a7ec06 GN |
2335 | reason = TASK_SWITCH_GATE; |
2336 | else | |
2337 | reason = TASK_SWITCH_CALL; | |
2338 | ||
fe8e7f83 GN |
2339 | if (reason == TASK_SWITCH_GATE) { |
2340 | switch (type) { | |
2341 | case SVM_EXITINTINFO_TYPE_NMI: | |
2342 | svm->vcpu.arch.nmi_injected = false; | |
2343 | break; | |
2344 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
e269fb21 JK |
2345 | if (svm->vmcb->control.exit_info_2 & |
2346 | (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) { | |
2347 | has_error_code = true; | |
2348 | error_code = | |
2349 | (u32)svm->vmcb->control.exit_info_2; | |
2350 | } | |
fe8e7f83 GN |
2351 | kvm_clear_exception_queue(&svm->vcpu); |
2352 | break; | |
2353 | case SVM_EXITINTINFO_TYPE_INTR: | |
2354 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2355 | break; | |
2356 | default: | |
2357 | break; | |
2358 | } | |
2359 | } | |
64a7ec06 | 2360 | |
8317c298 GN |
2361 | if (reason != TASK_SWITCH_GATE || |
2362 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2363 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2364 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2365 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 | 2366 | |
acb54517 GN |
2367 | if (kvm_task_switch(&svm->vcpu, tss_selector, reason, |
2368 | has_error_code, error_code) == EMULATE_FAIL) { | |
2369 | svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
2370 | svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
2371 | svm->vcpu.run->internal.ndata = 0; | |
2372 | return 0; | |
2373 | } | |
2374 | return 1; | |
6aa8b732 AK |
2375 | } |
2376 | ||
851ba692 | 2377 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2378 | { |
5fdbf976 | 2379 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2380 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2381 | return 1; |
6aa8b732 AK |
2382 | } |
2383 | ||
851ba692 | 2384 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2385 | { |
2386 | ++svm->vcpu.stat.nmi_window_exits; | |
061e2fd1 | 2387 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
44c11430 | 2388 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2389 | return 1; |
2390 | } | |
2391 | ||
851ba692 | 2392 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2393 | { |
6d77dbfc | 2394 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
a7052897 MT |
2395 | } |
2396 | ||
851ba692 | 2397 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2398 | { |
6d77dbfc | 2399 | return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE; |
6aa8b732 AK |
2400 | } |
2401 | ||
851ba692 | 2402 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2403 | { |
851ba692 AK |
2404 | struct kvm_run *kvm_run = svm->vcpu.run; |
2405 | ||
0a5fff19 GN |
2406 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2407 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2408 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2409 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2410 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2411 | return 1; |
95ba8273 | 2412 | } |
0a5fff19 GN |
2413 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2414 | return 1; | |
1d075434 JR |
2415 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2416 | return 0; | |
2417 | } | |
2418 | ||
6aa8b732 AK |
2419 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2420 | { | |
a2fa3e9f GH |
2421 | struct vcpu_svm *svm = to_svm(vcpu); |
2422 | ||
6aa8b732 | 2423 | switch (ecx) { |
af24a4e4 | 2424 | case MSR_IA32_TSC: { |
20824f30 | 2425 | u64 tsc_offset; |
6aa8b732 | 2426 | |
20824f30 JR |
2427 | if (is_nested(svm)) |
2428 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2429 | else | |
2430 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2431 | ||
2432 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2433 | break; |
2434 | } | |
8c06585d | 2435 | case MSR_STAR: |
a2fa3e9f | 2436 | *data = svm->vmcb->save.star; |
6aa8b732 | 2437 | break; |
0e859cac | 2438 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2439 | case MSR_LSTAR: |
a2fa3e9f | 2440 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2441 | break; |
2442 | case MSR_CSTAR: | |
a2fa3e9f | 2443 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2444 | break; |
2445 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2446 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2447 | break; |
2448 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2449 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2450 | break; |
2451 | #endif | |
2452 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2453 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2454 | break; |
2455 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2456 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2457 | break; |
2458 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2459 | *data = svm->sysenter_esp; |
6aa8b732 | 2460 | break; |
e0231715 JR |
2461 | /* |
2462 | * Nobody will change the following 5 values in the VMCB so we can | |
2463 | * safely return them on rdmsr. They will always be 0 until LBRV is | |
2464 | * implemented. | |
2465 | */ | |
a2938c80 JR |
2466 | case MSR_IA32_DEBUGCTLMSR: |
2467 | *data = svm->vmcb->save.dbgctl; | |
2468 | break; | |
2469 | case MSR_IA32_LASTBRANCHFROMIP: | |
2470 | *data = svm->vmcb->save.br_from; | |
2471 | break; | |
2472 | case MSR_IA32_LASTBRANCHTOIP: | |
2473 | *data = svm->vmcb->save.br_to; | |
2474 | break; | |
2475 | case MSR_IA32_LASTINTFROMIP: | |
2476 | *data = svm->vmcb->save.last_excp_from; | |
2477 | break; | |
2478 | case MSR_IA32_LASTINTTOIP: | |
2479 | *data = svm->vmcb->save.last_excp_to; | |
2480 | break; | |
b286d5d8 | 2481 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2482 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2483 | break; |
eb6f302e | 2484 | case MSR_VM_CR: |
4a810181 | 2485 | *data = svm->nested.vm_cr_msr; |
eb6f302e | 2486 | break; |
c8a73f18 AG |
2487 | case MSR_IA32_UCODE_REV: |
2488 | *data = 0x01000065; | |
2489 | break; | |
6aa8b732 | 2490 | default: |
3bab1f5d | 2491 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2492 | } |
2493 | return 0; | |
2494 | } | |
2495 | ||
851ba692 | 2496 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2497 | { |
ad312c7c | 2498 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2499 | u64 data; |
2500 | ||
59200273 AK |
2501 | if (svm_get_msr(&svm->vcpu, ecx, &data)) { |
2502 | trace_kvm_msr_read_ex(ecx); | |
c1a5d4f9 | 2503 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 | 2504 | } else { |
229456fc | 2505 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2506 | |
5fdbf976 | 2507 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2508 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2509 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2510 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2511 | } |
2512 | return 1; | |
2513 | } | |
2514 | ||
4a810181 JR |
2515 | static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data) |
2516 | { | |
2517 | struct vcpu_svm *svm = to_svm(vcpu); | |
2518 | int svm_dis, chg_mask; | |
2519 | ||
2520 | if (data & ~SVM_VM_CR_VALID_MASK) | |
2521 | return 1; | |
2522 | ||
2523 | chg_mask = SVM_VM_CR_VALID_MASK; | |
2524 | ||
2525 | if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK) | |
2526 | chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK); | |
2527 | ||
2528 | svm->nested.vm_cr_msr &= ~chg_mask; | |
2529 | svm->nested.vm_cr_msr |= (data & chg_mask); | |
2530 | ||
2531 | svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK; | |
2532 | ||
2533 | /* check for svm_disable while efer.svme is set */ | |
2534 | if (svm_dis && (vcpu->arch.efer & EFER_SVME)) | |
2535 | return 1; | |
2536 | ||
2537 | return 0; | |
2538 | } | |
2539 | ||
6aa8b732 AK |
2540 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) |
2541 | { | |
a2fa3e9f GH |
2542 | struct vcpu_svm *svm = to_svm(vcpu); |
2543 | ||
6aa8b732 | 2544 | switch (ecx) { |
af24a4e4 | 2545 | case MSR_IA32_TSC: { |
20824f30 JR |
2546 | u64 tsc_offset = data - native_read_tsc(); |
2547 | u64 g_tsc_offset = 0; | |
2548 | ||
2549 | if (is_nested(svm)) { | |
2550 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2551 | svm->nested.hsave->control.tsc_offset; | |
2552 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2553 | } | |
2554 | ||
2555 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
6aa8b732 | 2556 | |
6aa8b732 AK |
2557 | break; |
2558 | } | |
8c06585d | 2559 | case MSR_STAR: |
a2fa3e9f | 2560 | svm->vmcb->save.star = data; |
6aa8b732 | 2561 | break; |
49b14f24 | 2562 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2563 | case MSR_LSTAR: |
a2fa3e9f | 2564 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2565 | break; |
2566 | case MSR_CSTAR: | |
a2fa3e9f | 2567 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2568 | break; |
2569 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2570 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2571 | break; |
2572 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2573 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2574 | break; |
2575 | #endif | |
2576 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2577 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2578 | break; |
2579 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2580 | svm->sysenter_eip = data; |
a2fa3e9f | 2581 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2582 | break; |
2583 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2584 | svm->sysenter_esp = data; |
a2fa3e9f | 2585 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2586 | break; |
a2938c80 | 2587 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2588 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2589 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2590 | __func__, data); |
24e09cbf JR |
2591 | break; |
2592 | } | |
2593 | if (data & DEBUGCTL_RESERVED_BITS) | |
2594 | return 1; | |
2595 | ||
2596 | svm->vmcb->save.dbgctl = data; | |
2597 | if (data & (1ULL<<0)) | |
2598 | svm_enable_lbrv(svm); | |
2599 | else | |
2600 | svm_disable_lbrv(svm); | |
a2938c80 | 2601 | break; |
b286d5d8 | 2602 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2603 | svm->nested.hsave_msr = data; |
62b9abaa | 2604 | break; |
3c5d0a44 | 2605 | case MSR_VM_CR: |
4a810181 | 2606 | return svm_set_vm_cr(vcpu, data); |
3c5d0a44 | 2607 | case MSR_VM_IGNNE: |
3c5d0a44 AG |
2608 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2609 | break; | |
6aa8b732 | 2610 | default: |
3bab1f5d | 2611 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2612 | } |
2613 | return 0; | |
2614 | } | |
2615 | ||
851ba692 | 2616 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2617 | { |
ad312c7c | 2618 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2619 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2620 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2621 | |
af9ca2d7 | 2622 | |
5fdbf976 | 2623 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
59200273 AK |
2624 | if (svm_set_msr(&svm->vcpu, ecx, data)) { |
2625 | trace_kvm_msr_write_ex(ecx, data); | |
c1a5d4f9 | 2626 | kvm_inject_gp(&svm->vcpu, 0); |
59200273 AK |
2627 | } else { |
2628 | trace_kvm_msr_write(ecx, data); | |
e756fc62 | 2629 | skip_emulated_instruction(&svm->vcpu); |
59200273 | 2630 | } |
6aa8b732 AK |
2631 | return 1; |
2632 | } | |
2633 | ||
851ba692 | 2634 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2635 | { |
e756fc62 | 2636 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2637 | return wrmsr_interception(svm); |
6aa8b732 | 2638 | else |
851ba692 | 2639 | return rdmsr_interception(svm); |
6aa8b732 AK |
2640 | } |
2641 | ||
851ba692 | 2642 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2643 | { |
851ba692 AK |
2644 | struct kvm_run *kvm_run = svm->vcpu.run; |
2645 | ||
f0b85051 | 2646 | svm_clear_vintr(svm); |
85f455f7 | 2647 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2648 | /* |
2649 | * If the user space waits to inject interrupts, exit as soon as | |
2650 | * possible | |
2651 | */ | |
8061823a GN |
2652 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2653 | kvm_run->request_interrupt_window && | |
2654 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2655 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2656 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2657 | return 0; | |
2658 | } | |
2659 | ||
2660 | return 1; | |
2661 | } | |
2662 | ||
565d0998 ML |
2663 | static int pause_interception(struct vcpu_svm *svm) |
2664 | { | |
2665 | kvm_vcpu_on_spin(&(svm->vcpu)); | |
2666 | return 1; | |
2667 | } | |
2668 | ||
851ba692 | 2669 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
e0231715 JR |
2670 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2671 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2672 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
2673 | [SVM_EXIT_READ_CR8] = emulate_on_interception, | |
d225157b | 2674 | [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, |
e0231715 JR |
2675 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, |
2676 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2677 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
2678 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, | |
2679 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
6aa8b732 AK |
2680 | [SVM_EXIT_READ_DR1] = emulate_on_interception, |
2681 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2682 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
727f5a23 JK |
2683 | [SVM_EXIT_READ_DR4] = emulate_on_interception, |
2684 | [SVM_EXIT_READ_DR5] = emulate_on_interception, | |
2685 | [SVM_EXIT_READ_DR6] = emulate_on_interception, | |
2686 | [SVM_EXIT_READ_DR7] = emulate_on_interception, | |
6aa8b732 AK |
2687 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, |
2688 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2689 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2690 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
727f5a23 | 2691 | [SVM_EXIT_WRITE_DR4] = emulate_on_interception, |
6aa8b732 | 2692 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, |
727f5a23 | 2693 | [SVM_EXIT_WRITE_DR6] = emulate_on_interception, |
6aa8b732 | 2694 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, |
d0bfb940 JK |
2695 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2696 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2697 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
e0231715 JR |
2698 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
2699 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, | |
2700 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, | |
2701 | [SVM_EXIT_INTR] = intr_interception, | |
c47f098d | 2702 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2703 | [SVM_EXIT_SMI] = nop_on_interception, |
2704 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2705 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 | 2706 | [SVM_EXIT_CPUID] = cpuid_interception, |
95ba8273 | 2707 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2708 | [SVM_EXIT_INVD] = emulate_on_interception, |
565d0998 | 2709 | [SVM_EXIT_PAUSE] = pause_interception, |
6aa8b732 | 2710 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2711 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2712 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
e0231715 | 2713 | [SVM_EXIT_IOIO] = io_interception, |
6aa8b732 AK |
2714 | [SVM_EXIT_MSR] = msr_interception, |
2715 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2716 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2717 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2718 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2719 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2720 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2721 | [SVM_EXIT_STGI] = stgi_interception, |
2722 | [SVM_EXIT_CLGI] = clgi_interception, | |
532a46b9 | 2723 | [SVM_EXIT_SKINIT] = skinit_interception, |
cf5a94d1 | 2724 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2725 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2726 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2727 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2728 | }; |
2729 | ||
3f10c846 JR |
2730 | void dump_vmcb(struct kvm_vcpu *vcpu) |
2731 | { | |
2732 | struct vcpu_svm *svm = to_svm(vcpu); | |
2733 | struct vmcb_control_area *control = &svm->vmcb->control; | |
2734 | struct vmcb_save_area *save = &svm->vmcb->save; | |
2735 | ||
2736 | pr_err("VMCB Control Area:\n"); | |
2737 | pr_err("cr_read: %04x\n", control->intercept_cr_read); | |
2738 | pr_err("cr_write: %04x\n", control->intercept_cr_write); | |
2739 | pr_err("dr_read: %04x\n", control->intercept_dr_read); | |
2740 | pr_err("dr_write: %04x\n", control->intercept_dr_write); | |
2741 | pr_err("exceptions: %08x\n", control->intercept_exceptions); | |
2742 | pr_err("intercepts: %016llx\n", control->intercept); | |
2743 | pr_err("pause filter count: %d\n", control->pause_filter_count); | |
2744 | pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa); | |
2745 | pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa); | |
2746 | pr_err("tsc_offset: %016llx\n", control->tsc_offset); | |
2747 | pr_err("asid: %d\n", control->asid); | |
2748 | pr_err("tlb_ctl: %d\n", control->tlb_ctl); | |
2749 | pr_err("int_ctl: %08x\n", control->int_ctl); | |
2750 | pr_err("int_vector: %08x\n", control->int_vector); | |
2751 | pr_err("int_state: %08x\n", control->int_state); | |
2752 | pr_err("exit_code: %08x\n", control->exit_code); | |
2753 | pr_err("exit_info1: %016llx\n", control->exit_info_1); | |
2754 | pr_err("exit_info2: %016llx\n", control->exit_info_2); | |
2755 | pr_err("exit_int_info: %08x\n", control->exit_int_info); | |
2756 | pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err); | |
2757 | pr_err("nested_ctl: %lld\n", control->nested_ctl); | |
2758 | pr_err("nested_cr3: %016llx\n", control->nested_cr3); | |
2759 | pr_err("event_inj: %08x\n", control->event_inj); | |
2760 | pr_err("event_inj_err: %08x\n", control->event_inj_err); | |
2761 | pr_err("lbr_ctl: %lld\n", control->lbr_ctl); | |
2762 | pr_err("next_rip: %016llx\n", control->next_rip); | |
2763 | pr_err("VMCB State Save Area:\n"); | |
2764 | pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n", | |
2765 | save->es.selector, save->es.attrib, | |
2766 | save->es.limit, save->es.base); | |
2767 | pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2768 | save->cs.selector, save->cs.attrib, | |
2769 | save->cs.limit, save->cs.base); | |
2770 | pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n", | |
2771 | save->ss.selector, save->ss.attrib, | |
2772 | save->ss.limit, save->ss.base); | |
2773 | pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n", | |
2774 | save->ds.selector, save->ds.attrib, | |
2775 | save->ds.limit, save->ds.base); | |
2776 | pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2777 | save->fs.selector, save->fs.attrib, | |
2778 | save->fs.limit, save->fs.base); | |
2779 | pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n", | |
2780 | save->gs.selector, save->gs.attrib, | |
2781 | save->gs.limit, save->gs.base); | |
2782 | pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2783 | save->gdtr.selector, save->gdtr.attrib, | |
2784 | save->gdtr.limit, save->gdtr.base); | |
2785 | pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2786 | save->ldtr.selector, save->ldtr.attrib, | |
2787 | save->ldtr.limit, save->ldtr.base); | |
2788 | pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2789 | save->idtr.selector, save->idtr.attrib, | |
2790 | save->idtr.limit, save->idtr.base); | |
2791 | pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n", | |
2792 | save->tr.selector, save->tr.attrib, | |
2793 | save->tr.limit, save->tr.base); | |
2794 | pr_err("cpl: %d efer: %016llx\n", | |
2795 | save->cpl, save->efer); | |
2796 | pr_err("cr0: %016llx cr2: %016llx\n", | |
2797 | save->cr0, save->cr2); | |
2798 | pr_err("cr3: %016llx cr4: %016llx\n", | |
2799 | save->cr3, save->cr4); | |
2800 | pr_err("dr6: %016llx dr7: %016llx\n", | |
2801 | save->dr6, save->dr7); | |
2802 | pr_err("rip: %016llx rflags: %016llx\n", | |
2803 | save->rip, save->rflags); | |
2804 | pr_err("rsp: %016llx rax: %016llx\n", | |
2805 | save->rsp, save->rax); | |
2806 | pr_err("star: %016llx lstar: %016llx\n", | |
2807 | save->star, save->lstar); | |
2808 | pr_err("cstar: %016llx sfmask: %016llx\n", | |
2809 | save->cstar, save->sfmask); | |
2810 | pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n", | |
2811 | save->kernel_gs_base, save->sysenter_cs); | |
2812 | pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n", | |
2813 | save->sysenter_esp, save->sysenter_eip); | |
2814 | pr_err("gpat: %016llx dbgctl: %016llx\n", | |
2815 | save->g_pat, save->dbgctl); | |
2816 | pr_err("br_from: %016llx br_to: %016llx\n", | |
2817 | save->br_from, save->br_to); | |
2818 | pr_err("excp_from: %016llx excp_to: %016llx\n", | |
2819 | save->last_excp_from, save->last_excp_to); | |
2820 | ||
2821 | } | |
2822 | ||
851ba692 | 2823 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2824 | { |
04d2cc77 | 2825 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2826 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2827 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2828 | |
5bfd8b54 | 2829 | trace_kvm_exit(exit_code, vcpu); |
af9ca2d7 | 2830 | |
2be4fc7a JR |
2831 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK)) |
2832 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2833 | if (npt_enabled) | |
2834 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
af9ca2d7 | 2835 | |
cd3ff653 JR |
2836 | if (unlikely(svm->nested.exit_required)) { |
2837 | nested_svm_vmexit(svm); | |
2838 | svm->nested.exit_required = false; | |
2839 | ||
2840 | return 1; | |
2841 | } | |
2842 | ||
cf74a78b | 2843 | if (is_nested(svm)) { |
410e4d57 JR |
2844 | int vmexit; |
2845 | ||
d8cabddf JR |
2846 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
2847 | svm->vmcb->control.exit_info_1, | |
2848 | svm->vmcb->control.exit_info_2, | |
2849 | svm->vmcb->control.exit_int_info, | |
2850 | svm->vmcb->control.exit_int_info_err); | |
2851 | ||
410e4d57 JR |
2852 | vmexit = nested_svm_exit_special(svm); |
2853 | ||
2854 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2855 | vmexit = nested_svm_exit_handled(svm); | |
2856 | ||
2857 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 2858 | return 1; |
cf74a78b AG |
2859 | } |
2860 | ||
a5c3832d JR |
2861 | svm_complete_interrupts(svm); |
2862 | ||
04d2cc77 AK |
2863 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
2864 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2865 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2866 | = svm->vmcb->control.exit_code; | |
3f10c846 JR |
2867 | pr_err("KVM: FAILED VMRUN WITH VMCB:\n"); |
2868 | dump_vmcb(vcpu); | |
04d2cc77 AK |
2869 | return 0; |
2870 | } | |
2871 | ||
a2fa3e9f | 2872 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 2873 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
fe8e7f83 | 2874 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) |
6aa8b732 AK |
2875 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2876 | "exit_code 0x%x\n", | |
b8688d51 | 2877 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2878 | exit_code); |
2879 | ||
9d8f549d | 2880 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2881 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2882 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2883 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2884 | return 0; |
2885 | } | |
2886 | ||
851ba692 | 2887 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
2888 | } |
2889 | ||
2890 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2891 | { | |
2892 | int cpu = raw_smp_processor_id(); | |
2893 | ||
0fe1e009 TH |
2894 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
2895 | sd->tss_desc->type = 9; /* available 32/64-bit TSS */ | |
6aa8b732 AK |
2896 | load_TR_desc(); |
2897 | } | |
2898 | ||
e756fc62 | 2899 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2900 | { |
2901 | int cpu = raw_smp_processor_id(); | |
2902 | ||
0fe1e009 | 2903 | struct svm_cpu_data *sd = per_cpu(svm_data, cpu); |
6aa8b732 | 2904 | |
a2fa3e9f | 2905 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 | 2906 | /* FIXME: handle wraparound of asid_generation */ |
0fe1e009 TH |
2907 | if (svm->asid_generation != sd->asid_generation) |
2908 | new_asid(svm, sd); | |
6aa8b732 AK |
2909 | } |
2910 | ||
95ba8273 GN |
2911 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
2912 | { | |
2913 | struct vcpu_svm *svm = to_svm(vcpu); | |
2914 | ||
2915 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2916 | vcpu->arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 2917 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
95ba8273 GN |
2918 | ++vcpu->stat.nmi_injections; |
2919 | } | |
6aa8b732 | 2920 | |
85f455f7 | 2921 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2922 | { |
2923 | struct vmcb_control_area *control; | |
2924 | ||
e756fc62 | 2925 | control = &svm->vmcb->control; |
85f455f7 | 2926 | control->int_vector = irq; |
6aa8b732 AK |
2927 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2928 | control->int_ctl |= V_IRQ_MASK | | |
2929 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2930 | } | |
2931 | ||
66fd3f7f | 2932 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
2933 | { |
2934 | struct vcpu_svm *svm = to_svm(vcpu); | |
2935 | ||
2af9194d | 2936 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 2937 | |
9fb2d2b4 GN |
2938 | trace_kvm_inj_virq(vcpu->arch.interrupt.nr); |
2939 | ++vcpu->stat.irq_injections; | |
2940 | ||
219b65dc AG |
2941 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
2942 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
2943 | } |
2944 | ||
95ba8273 | 2945 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
2946 | { |
2947 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 2948 | |
88ab24ad JR |
2949 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
2950 | return; | |
2951 | ||
95ba8273 | 2952 | if (irr == -1) |
aaacfc9a JR |
2953 | return; |
2954 | ||
95ba8273 GN |
2955 | if (tpr >= irr) |
2956 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2957 | } | |
aaacfc9a | 2958 | |
95ba8273 GN |
2959 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
2960 | { | |
2961 | struct vcpu_svm *svm = to_svm(vcpu); | |
2962 | struct vmcb *vmcb = svm->vmcb; | |
924584cc JR |
2963 | int ret; |
2964 | ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2965 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
2966 | ret = ret && gif_set(svm) && nested_svm_nmi(svm); | |
2967 | ||
2968 | return ret; | |
aaacfc9a JR |
2969 | } |
2970 | ||
3cfc3092 JK |
2971 | static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu) |
2972 | { | |
2973 | struct vcpu_svm *svm = to_svm(vcpu); | |
2974 | ||
2975 | return !!(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
2976 | } | |
2977 | ||
2978 | static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
2979 | { | |
2980 | struct vcpu_svm *svm = to_svm(vcpu); | |
2981 | ||
2982 | if (masked) { | |
2983 | svm->vcpu.arch.hflags |= HF_NMI_MASK; | |
061e2fd1 | 2984 | svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
2985 | } else { |
2986 | svm->vcpu.arch.hflags &= ~HF_NMI_MASK; | |
061e2fd1 | 2987 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET); |
3cfc3092 JK |
2988 | } |
2989 | } | |
2990 | ||
78646121 GN |
2991 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
2992 | { | |
2993 | struct vcpu_svm *svm = to_svm(vcpu); | |
2994 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
2995 | int ret; |
2996 | ||
2997 | if (!gif_set(svm) || | |
2998 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
2999 | return 0; | |
3000 | ||
3001 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
3002 | ||
3003 | if (is_nested(svm)) | |
3004 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
3005 | ||
3006 | return ret; | |
78646121 GN |
3007 | } |
3008 | ||
9222be18 | 3009 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 3010 | { |
219b65dc | 3011 | struct vcpu_svm *svm = to_svm(vcpu); |
219b65dc | 3012 | |
e0231715 JR |
3013 | /* |
3014 | * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes | |
3015 | * 1, because that's a separate STGI/VMRUN intercept. The next time we | |
3016 | * get that intercept, this function will be called again though and | |
3017 | * we'll get the vintr intercept. | |
3018 | */ | |
8fe54654 | 3019 | if (gif_set(svm) && nested_svm_intr(svm)) { |
219b65dc AG |
3020 | svm_set_vintr(svm); |
3021 | svm_inject_irq(svm, 0x0); | |
3022 | } | |
85f455f7 ED |
3023 | } |
3024 | ||
95ba8273 | 3025 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 3026 | { |
04d2cc77 | 3027 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 3028 | |
44c11430 GN |
3029 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
3030 | == HF_NMI_MASK) | |
3031 | return; /* IRET will cause a vm exit */ | |
3032 | ||
e0231715 JR |
3033 | /* |
3034 | * Something prevents NMI from been injected. Single step over possible | |
3035 | * problem (IRET or exception injection or interrupt shadow) | |
3036 | */ | |
6be7d306 | 3037 | svm->nmi_singlestep = true; |
44c11430 GN |
3038 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); |
3039 | update_db_intercept(vcpu); | |
c1150d8c DL |
3040 | } |
3041 | ||
cbc94022 IE |
3042 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
3043 | { | |
3044 | return 0; | |
3045 | } | |
3046 | ||
d9e368d6 AK |
3047 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
3048 | { | |
3049 | force_new_asid(vcpu); | |
3050 | } | |
3051 | ||
04d2cc77 AK |
3052 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
3053 | { | |
3054 | } | |
3055 | ||
d7bf8221 JR |
3056 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
3057 | { | |
3058 | struct vcpu_svm *svm = to_svm(vcpu); | |
3059 | ||
88ab24ad JR |
3060 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
3061 | return; | |
3062 | ||
d7bf8221 JR |
3063 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { |
3064 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 3065 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
3066 | } |
3067 | } | |
3068 | ||
649d6864 JR |
3069 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
3070 | { | |
3071 | struct vcpu_svm *svm = to_svm(vcpu); | |
3072 | u64 cr8; | |
3073 | ||
88ab24ad JR |
3074 | if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK)) |
3075 | return; | |
3076 | ||
649d6864 JR |
3077 | cr8 = kvm_get_cr8(vcpu); |
3078 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
3079 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
3080 | } | |
3081 | ||
9222be18 GN |
3082 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
3083 | { | |
3084 | u8 vector; | |
3085 | int type; | |
3086 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
66b7138f JK |
3087 | unsigned int3_injected = svm->int3_injected; |
3088 | ||
3089 | svm->int3_injected = 0; | |
9222be18 | 3090 | |
44c11430 GN |
3091 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) |
3092 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
3093 | ||
9222be18 GN |
3094 | svm->vcpu.arch.nmi_injected = false; |
3095 | kvm_clear_exception_queue(&svm->vcpu); | |
3096 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3097 | ||
3098 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
3099 | return; | |
3100 | ||
3101 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
3102 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
3103 | ||
3104 | switch (type) { | |
3105 | case SVM_EXITINTINFO_TYPE_NMI: | |
3106 | svm->vcpu.arch.nmi_injected = true; | |
3107 | break; | |
3108 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
66b7138f JK |
3109 | /* |
3110 | * In case of software exceptions, do not reinject the vector, | |
3111 | * but re-execute the instruction instead. Rewind RIP first | |
3112 | * if we emulated INT3 before. | |
3113 | */ | |
3114 | if (kvm_exception_is_soft(vector)) { | |
3115 | if (vector == BP_VECTOR && int3_injected && | |
3116 | kvm_is_linear_rip(&svm->vcpu, svm->int3_rip)) | |
3117 | kvm_rip_write(&svm->vcpu, | |
3118 | kvm_rip_read(&svm->vcpu) - | |
3119 | int3_injected); | |
9222be18 | 3120 | break; |
66b7138f | 3121 | } |
9222be18 GN |
3122 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { |
3123 | u32 err = svm->vmcb->control.exit_int_info_err; | |
ce7ddec4 | 3124 | kvm_requeue_exception_e(&svm->vcpu, vector, err); |
9222be18 GN |
3125 | |
3126 | } else | |
ce7ddec4 | 3127 | kvm_requeue_exception(&svm->vcpu, vector); |
9222be18 GN |
3128 | break; |
3129 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 3130 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
3131 | break; |
3132 | default: | |
3133 | break; | |
3134 | } | |
3135 | } | |
3136 | ||
80e31d4f AK |
3137 | #ifdef CONFIG_X86_64 |
3138 | #define R "r" | |
3139 | #else | |
3140 | #define R "e" | |
3141 | #endif | |
3142 | ||
851ba692 | 3143 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 3144 | { |
a2fa3e9f | 3145 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
3146 | u16 fs_selector; |
3147 | u16 gs_selector; | |
3148 | u16 ldt_selector; | |
d9e368d6 | 3149 | |
2041a06a JR |
3150 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
3151 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
3152 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
3153 | ||
cd3ff653 JR |
3154 | /* |
3155 | * A vmexit emulation is required before the vcpu can be executed | |
3156 | * again. | |
3157 | */ | |
3158 | if (unlikely(svm->nested.exit_required)) | |
3159 | return; | |
3160 | ||
e756fc62 | 3161 | pre_svm_run(svm); |
6aa8b732 | 3162 | |
649d6864 JR |
3163 | sync_lapic_to_cr8(vcpu); |
3164 | ||
6aa8b732 | 3165 | save_host_msrs(vcpu); |
d6e88aec AK |
3166 | fs_selector = kvm_read_fs(); |
3167 | gs_selector = kvm_read_gs(); | |
3168 | ldt_selector = kvm_read_ldt(); | |
cda0ffdd | 3169 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
3170 | /* required for live migration with NPT */ |
3171 | if (npt_enabled) | |
3172 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 3173 | |
04d2cc77 AK |
3174 | clgi(); |
3175 | ||
3176 | local_irq_enable(); | |
36241b8c | 3177 | |
6aa8b732 | 3178 | asm volatile ( |
80e31d4f AK |
3179 | "push %%"R"bp; \n\t" |
3180 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
3181 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
3182 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
3183 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
3184 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
3185 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 3186 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3187 | "mov %c[r8](%[svm]), %%r8 \n\t" |
3188 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
3189 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
3190 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
3191 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
3192 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
3193 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
3194 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
3195 | #endif |
3196 | ||
6aa8b732 | 3197 | /* Enter guest mode */ |
80e31d4f AK |
3198 | "push %%"R"ax \n\t" |
3199 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
3200 | __ex(SVM_VMLOAD) "\n\t" |
3201 | __ex(SVM_VMRUN) "\n\t" | |
3202 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 3203 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
3204 | |
3205 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
3206 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
3207 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
3208 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
3209 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
3210 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
3211 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 3212 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
3213 | "mov %%r8, %c[r8](%[svm]) \n\t" |
3214 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
3215 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
3216 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
3217 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
3218 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
3219 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
3220 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 3221 | #endif |
80e31d4f | 3222 | "pop %%"R"bp" |
6aa8b732 | 3223 | : |
fb3f0f51 | 3224 | : [svm]"a"(svm), |
6aa8b732 | 3225 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
3226 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
3227 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3228 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3229 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3230 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3231 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 3232 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3233 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
3234 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
3235 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
3236 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
3237 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
3238 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
3239 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
3240 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 3241 | #endif |
54a08c04 | 3242 | : "cc", "memory" |
80e31d4f | 3243 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 3244 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
3245 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
3246 | #endif | |
3247 | ); | |
6aa8b732 | 3248 | |
ad312c7c | 3249 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
3250 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
3251 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
3252 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 3253 | |
d6e88aec AK |
3254 | kvm_load_fs(fs_selector); |
3255 | kvm_load_gs(gs_selector); | |
3256 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
3257 | load_host_msrs(vcpu); |
3258 | ||
3259 | reload_tss(vcpu); | |
3260 | ||
56ba47dd AK |
3261 | local_irq_disable(); |
3262 | ||
3263 | stgi(); | |
3264 | ||
d7bf8221 JR |
3265 | sync_cr8_to_lapic(vcpu); |
3266 | ||
a2fa3e9f | 3267 | svm->next_rip = 0; |
9222be18 | 3268 | |
6de4f3ad AK |
3269 | if (npt_enabled) { |
3270 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
3271 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
3272 | } | |
fe5913e4 JR |
3273 | |
3274 | /* | |
3275 | * We need to handle MC intercepts here before the vcpu has a chance to | |
3276 | * change the physical cpu | |
3277 | */ | |
3278 | if (unlikely(svm->vmcb->control.exit_code == | |
3279 | SVM_EXIT_EXCP_BASE + MC_VECTOR)) | |
3280 | svm_handle_mce(svm); | |
6aa8b732 AK |
3281 | } |
3282 | ||
80e31d4f AK |
3283 | #undef R |
3284 | ||
6aa8b732 AK |
3285 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
3286 | { | |
a2fa3e9f GH |
3287 | struct vcpu_svm *svm = to_svm(vcpu); |
3288 | ||
709ddebf JR |
3289 | if (npt_enabled) { |
3290 | svm->vmcb->control.nested_cr3 = root; | |
3291 | force_new_asid(vcpu); | |
3292 | return; | |
3293 | } | |
3294 | ||
a2fa3e9f | 3295 | svm->vmcb->save.cr3 = root; |
6aa8b732 AK |
3296 | force_new_asid(vcpu); |
3297 | } | |
3298 | ||
6aa8b732 AK |
3299 | static int is_disabled(void) |
3300 | { | |
6031a61c JR |
3301 | u64 vm_cr; |
3302 | ||
3303 | rdmsrl(MSR_VM_CR, vm_cr); | |
3304 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
3305 | return 1; | |
3306 | ||
6aa8b732 AK |
3307 | return 0; |
3308 | } | |
3309 | ||
102d8325 IM |
3310 | static void |
3311 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
3312 | { | |
3313 | /* | |
3314 | * Patch in the VMMCALL instruction: | |
3315 | */ | |
3316 | hypercall[0] = 0x0f; | |
3317 | hypercall[1] = 0x01; | |
3318 | hypercall[2] = 0xd9; | |
102d8325 IM |
3319 | } |
3320 | ||
002c7f7c YS |
3321 | static void svm_check_processor_compat(void *rtn) |
3322 | { | |
3323 | *(int *)rtn = 0; | |
3324 | } | |
3325 | ||
774ead3a AK |
3326 | static bool svm_cpu_has_accelerated_tpr(void) |
3327 | { | |
3328 | return false; | |
3329 | } | |
3330 | ||
67253af5 SY |
3331 | static int get_npt_level(void) |
3332 | { | |
3333 | #ifdef CONFIG_X86_64 | |
3334 | return PT64_ROOT_LEVEL; | |
3335 | #else | |
3336 | return PT32E_ROOT_LEVEL; | |
3337 | #endif | |
3338 | } | |
3339 | ||
4b12f0de | 3340 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
3341 | { |
3342 | return 0; | |
3343 | } | |
3344 | ||
0e851880 SY |
3345 | static void svm_cpuid_update(struct kvm_vcpu *vcpu) |
3346 | { | |
3347 | } | |
3348 | ||
d4330ef2 JR |
3349 | static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
3350 | { | |
c2c63a49 JR |
3351 | switch (func) { |
3352 | case 0x8000000A: | |
3353 | entry->eax = 1; /* SVM revision 1 */ | |
3354 | entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper | |
3355 | ASID emulation to nested SVM */ | |
3356 | entry->ecx = 0; /* Reserved */ | |
3357 | entry->edx = 0; /* Do not support any additional features */ | |
3358 | ||
3359 | break; | |
3360 | } | |
d4330ef2 JR |
3361 | } |
3362 | ||
229456fc | 3363 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
e0231715 JR |
3364 | { SVM_EXIT_READ_CR0, "read_cr0" }, |
3365 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
3366 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
3367 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
3368 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
3369 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
3370 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
3371 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
3372 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
3373 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
3374 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
3375 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
3376 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
3377 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
3378 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
3379 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
3380 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
3381 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
229456fc MT |
3382 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, |
3383 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
3384 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
3385 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
3386 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
3387 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
3388 | { SVM_EXIT_INTR, "interrupt" }, | |
3389 | { SVM_EXIT_NMI, "nmi" }, | |
3390 | { SVM_EXIT_SMI, "smi" }, | |
3391 | { SVM_EXIT_INIT, "init" }, | |
3392 | { SVM_EXIT_VINTR, "vintr" }, | |
3393 | { SVM_EXIT_CPUID, "cpuid" }, | |
3394 | { SVM_EXIT_INVD, "invd" }, | |
3395 | { SVM_EXIT_HLT, "hlt" }, | |
3396 | { SVM_EXIT_INVLPG, "invlpg" }, | |
3397 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
3398 | { SVM_EXIT_IOIO, "io" }, | |
3399 | { SVM_EXIT_MSR, "msr" }, | |
3400 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
3401 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
3402 | { SVM_EXIT_VMRUN, "vmrun" }, | |
3403 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
3404 | { SVM_EXIT_VMLOAD, "vmload" }, | |
3405 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
3406 | { SVM_EXIT_STGI, "stgi" }, | |
3407 | { SVM_EXIT_CLGI, "clgi" }, | |
3408 | { SVM_EXIT_SKINIT, "skinit" }, | |
3409 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
3410 | { SVM_EXIT_MONITOR, "monitor" }, | |
3411 | { SVM_EXIT_MWAIT, "mwait" }, | |
3412 | { SVM_EXIT_NPF, "npf" }, | |
3413 | { -1, NULL } | |
3414 | }; | |
3415 | ||
17cc3935 | 3416 | static int svm_get_lpage_level(void) |
344f414f | 3417 | { |
17cc3935 | 3418 | return PT_PDPE_LEVEL; |
344f414f JR |
3419 | } |
3420 | ||
4e47c7a6 SY |
3421 | static bool svm_rdtscp_supported(void) |
3422 | { | |
3423 | return false; | |
3424 | } | |
3425 | ||
f5f48ee1 SY |
3426 | static bool svm_has_wbinvd_exit(void) |
3427 | { | |
3428 | return true; | |
3429 | } | |
3430 | ||
02daab21 AK |
3431 | static void svm_fpu_deactivate(struct kvm_vcpu *vcpu) |
3432 | { | |
3433 | struct vcpu_svm *svm = to_svm(vcpu); | |
3434 | ||
02daab21 | 3435 | svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR; |
66a562f7 JR |
3436 | if (is_nested(svm)) |
3437 | svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR; | |
3438 | update_cr0_intercept(svm); | |
02daab21 AK |
3439 | } |
3440 | ||
cbdd1bea | 3441 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
3442 | .cpu_has_kvm_support = has_svm, |
3443 | .disabled_by_bios = is_disabled, | |
3444 | .hardware_setup = svm_hardware_setup, | |
3445 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 3446 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
3447 | .hardware_enable = svm_hardware_enable, |
3448 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 3449 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
3450 | |
3451 | .vcpu_create = svm_create_vcpu, | |
3452 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 3453 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 3454 | |
04d2cc77 | 3455 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
3456 | .vcpu_load = svm_vcpu_load, |
3457 | .vcpu_put = svm_vcpu_put, | |
3458 | ||
3459 | .set_guest_debug = svm_guest_debug, | |
3460 | .get_msr = svm_get_msr, | |
3461 | .set_msr = svm_set_msr, | |
3462 | .get_segment_base = svm_get_segment_base, | |
3463 | .get_segment = svm_get_segment, | |
3464 | .set_segment = svm_set_segment, | |
2e4d2653 | 3465 | .get_cpl = svm_get_cpl, |
1747fb71 | 3466 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
e8467fda | 3467 | .decache_cr0_guest_bits = svm_decache_cr0_guest_bits, |
25c4c276 | 3468 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 3469 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
3470 | .set_cr3 = svm_set_cr3, |
3471 | .set_cr4 = svm_set_cr4, | |
3472 | .set_efer = svm_set_efer, | |
3473 | .get_idt = svm_get_idt, | |
3474 | .set_idt = svm_set_idt, | |
3475 | .get_gdt = svm_get_gdt, | |
3476 | .set_gdt = svm_set_gdt, | |
020df079 | 3477 | .set_dr7 = svm_set_dr7, |
6de4f3ad | 3478 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
3479 | .get_rflags = svm_get_rflags, |
3480 | .set_rflags = svm_set_rflags, | |
6b52d186 | 3481 | .fpu_activate = svm_fpu_activate, |
02daab21 | 3482 | .fpu_deactivate = svm_fpu_deactivate, |
6aa8b732 | 3483 | |
6aa8b732 | 3484 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 3485 | |
6aa8b732 | 3486 | .run = svm_vcpu_run, |
04d2cc77 | 3487 | .handle_exit = handle_exit, |
6aa8b732 | 3488 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
3489 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
3490 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 3491 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 3492 | .set_irq = svm_set_irq, |
95ba8273 | 3493 | .set_nmi = svm_inject_nmi, |
298101da | 3494 | .queue_exception = svm_queue_exception, |
78646121 | 3495 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 | 3496 | .nmi_allowed = svm_nmi_allowed, |
3cfc3092 JK |
3497 | .get_nmi_mask = svm_get_nmi_mask, |
3498 | .set_nmi_mask = svm_set_nmi_mask, | |
95ba8273 GN |
3499 | .enable_nmi_window = enable_nmi_window, |
3500 | .enable_irq_window = enable_irq_window, | |
3501 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
3502 | |
3503 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 3504 | .get_tdp_level = get_npt_level, |
4b12f0de | 3505 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
3506 | |
3507 | .exit_reasons_str = svm_exit_reasons_str, | |
17cc3935 | 3508 | .get_lpage_level = svm_get_lpage_level, |
0e851880 SY |
3509 | |
3510 | .cpuid_update = svm_cpuid_update, | |
4e47c7a6 SY |
3511 | |
3512 | .rdtscp_supported = svm_rdtscp_supported, | |
d4330ef2 JR |
3513 | |
3514 | .set_supported_cpuid = svm_set_supported_cpuid, | |
f5f48ee1 SY |
3515 | |
3516 | .has_wbinvd_exit = svm_has_wbinvd_exit, | |
6aa8b732 AK |
3517 | }; |
3518 | ||
3519 | static int __init svm_init(void) | |
3520 | { | |
cb498ea2 | 3521 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
0ee75bea | 3522 | __alignof__(struct vcpu_svm), THIS_MODULE); |
6aa8b732 AK |
3523 | } |
3524 | ||
3525 | static void __exit svm_exit(void) | |
3526 | { | |
cb498ea2 | 3527 | kvm_exit(); |
6aa8b732 AK |
3528 | } |
3529 | ||
3530 | module_init(svm_init) | |
3531 | module_exit(svm_exit) |