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KVM: SVM: Handle MCEs early in the vmexit process
[net-next-2.6.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
6bc31bdc
AP		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
49#define SVM_FEATURE_SVML (1 << 2)
50#define SVM_FEATURE_NRIP (1 << 3)
51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
ce2ac085 82 u64 vmcb_iopm;
aad42c64 83
cd3ff653
JR		 84 /* A VMEXIT is required but not yet emulated */
85 bool exit_required;
86
aad42c64
JR		 87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read;
89 u16 intercept_cr_write;
90 u16 intercept_dr_read;
91 u16 intercept_dr_write;
92 u32 intercept_exceptions;
93 u64 intercept;
94
e6aa9abd
JR		 95};
96
323c3d80
JR		 97#define MSRPM_OFFSETS 16
98static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
99
6c8166a7
AK		 100struct vcpu_svm {
101 struct kvm_vcpu vcpu;
102 struct vmcb *vmcb;
103 unsigned long vmcb_pa;
104 struct svm_cpu_data *svm_data;
105 uint64_t asid_generation;
106 uint64_t sysenter_esp;
107 uint64_t sysenter_eip;
108
109 u64 next_rip;
110
111 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
112 u64 host_gs_base;
6c8166a7
AK		 113
114 u32 *msrpm;
6c8166a7 115
e6aa9abd 116 struct nested_state nested;
6be7d306
JK		 117
118 bool nmi_singlestep;
66b7138f
JK		 119
120 unsigned int3_injected;
121 unsigned long int3_rip;
6c8166a7
AK		 122};
123
455716fa
JR		 124#define MSR_INVALID 0xffffffffU
125
ac72a9b7
JR		 126static struct svm_direct_access_msrs {
127 u32 index; /* Index of the MSR */
128 bool always; /* True if intercept is always on */
129} direct_access_msrs[] = {
130 { .index = MSR_K6_STAR, .always = true },
131 { .index = MSR_IA32_SYSENTER_CS, .always = true },
132#ifdef CONFIG_X86_64
133 { .index = MSR_GS_BASE, .always = true },
134 { .index = MSR_FS_BASE, .always = true },
135 { .index = MSR_KERNEL_GS_BASE, .always = true },
136 { .index = MSR_LSTAR, .always = true },
137 { .index = MSR_CSTAR, .always = true },
138 { .index = MSR_SYSCALL_MASK, .always = true },
139#endif
140 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
141 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
142 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
143 { .index = MSR_IA32_LASTINTTOIP, .always = false },
144 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 145};
146
709ddebf
JR		 147/* enable NPT for AMD64 and X86 with PAE */
148#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149static bool npt_enabled = true;
150#else
e0231715 151static bool npt_enabled;
709ddebf 152#endif
6c7dac72
JR		 153static int npt = 1;
154
155module_param(npt, int, S_IRUGO);
e3da3acd 156
4b6e4dca 157static int nested = 1;
236de055
AG		 158module_param(nested, int, S_IRUGO);
159
44874f84 160static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 161static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 162
410e4d57 163static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 164static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 165static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 166static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
167 bool has_error_code, u32 error_code);
168
a2fa3e9f
GH		 169static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
170{
fb3f0f51 171 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 172}
173
3d6368ef
AG		 174static inline bool is_nested(struct vcpu_svm *svm)
175{
e6aa9abd 176 return svm->nested.vmcb;
3d6368ef
AG		 177}
178
2af9194d
JR		 179static inline void enable_gif(struct vcpu_svm *svm)
180{
181 svm->vcpu.arch.hflags |= HF_GIF_MASK;
182}
183
184static inline void disable_gif(struct vcpu_svm *svm)
185{
186 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
187}
188
189static inline bool gif_set(struct vcpu_svm *svm)
190{
191 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
192}
193
4866d5e3 194static unsigned long iopm_base;
6aa8b732
AK		 195
196struct kvm_ldttss_desc {
197 u16 limit0;
198 u16 base0;
e0231715
JR		 199 unsigned base1:8, type:5, dpl:2, p:1;
200 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 201 u32 base3;
202 u32 zero1;
203} __attribute__((packed));
204
205struct svm_cpu_data {
206 int cpu;
207
5008fdf5
AK		 208 u64 asid_generation;
209 u32 max_asid;
210 u32 next_asid;
6aa8b732
AK		 211 struct kvm_ldttss_desc *tss_desc;
212
213 struct page *save_area;
214};
215
216static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 217static uint32_t svm_features;
6aa8b732
AK		 218
219struct svm_init_data {
220 int cpu;
221 int r;
222};
223
224static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
225
9d8f549d 226#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 227#define MSRS_RANGE_SIZE 2048
228#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
229
455716fa
JR		 230static u32 svm_msrpm_offset(u32 msr)
231{
232 u32 offset;
233 int i;
234
235 for (i = 0; i < NUM_MSR_MAPS; i++) {
236 if (msr < msrpm_ranges[i] ||
237 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
238 continue;
239
240 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
241 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
242
243 /* Now we have the u8 offset - but need the u32 offset */
244 return offset / 4;
245 }
246
247 /* MSR not in any range */
248 return MSR_INVALID;
249}
250
6aa8b732
AK		 251#define MAX_INST_SIZE 15
252
80b7706e
JR		 253static inline u32 svm_has(u32 feat)
254{
255 return svm_features & feat;
256}
257
6aa8b732
AK		 258static inline void clgi(void)
259{
4ecac3fd 260 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 261}
262
263static inline void stgi(void)
264{
4ecac3fd 265 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 266}
267
268static inline void invlpga(unsigned long addr, u32 asid)
269{
e0231715 270 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 271}
272
6aa8b732
AK		 273static inline void force_new_asid(struct kvm_vcpu *vcpu)
274{
a2fa3e9f 275 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 276}
277
278static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
279{
280 force_new_asid(vcpu);
281}
282
283static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
284{
709ddebf 285 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 286 efer &= ~EFER_LME;
6aa8b732 287
9962d032 288 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 289 vcpu->arch.efer = efer;
6aa8b732
AK		 290}
291
6aa8b732
AK		 292static int is_external_interrupt(u32 info)
293{
294 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
295 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
296}
297
2809f5d2
GC		 298static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
299{
300 struct vcpu_svm *svm = to_svm(vcpu);
301 u32 ret = 0;
302
303 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 304 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 305 return ret & mask;
306}
307
308static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
309{
310 struct vcpu_svm *svm = to_svm(vcpu);
311
312 if (mask == 0)
313 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
314 else
315 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
316
317}
318
6aa8b732
AK		 319static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
320{
a2fa3e9f
GH		 321 struct vcpu_svm *svm = to_svm(vcpu);
322
6bc31bdc
AP		 323 if (svm->vmcb->control.next_rip != 0)
324 svm->next_rip = svm->vmcb->control.next_rip;
325
a2fa3e9f 326 if (!svm->next_rip) {
851ba692 327 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 328 EMULATE_DONE)
329 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 330 return;
331 }
5fdbf976
MT		 332 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
333 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
334 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 335
5fdbf976 336 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 337 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 338}
339
116a4752 340static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 341 bool has_error_code, u32 error_code,
342 bool reinject)
116a4752
JK		 343{
344 struct vcpu_svm *svm = to_svm(vcpu);
345
e0231715
JR		 346 /*
347 * If we are within a nested VM we'd better #VMEXIT and let the guest
348 * handle the exception
349 */
ce7ddec4
JR		 350 if (!reinject &&
351 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 352 return;
353
66b7138f
JK		 354 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
355 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
356
357 /*
358 * For guest debugging where we have to reinject #BP if some
359 * INT3 is guest-owned:
360 * Emulate nRIP by moving RIP forward. Will fail if injection
361 * raises a fault that is not intercepted. Still better than
362 * failing in all cases.
363 */
364 skip_emulated_instruction(&svm->vcpu);
365 rip = kvm_rip_read(&svm->vcpu);
366 svm->int3_rip = rip + svm->vmcb->save.cs.base;
367 svm->int3_injected = rip - old_rip;
368 }
369
116a4752
JK		 370 svm->vmcb->control.event_inj = nr
371 | SVM_EVTINJ_VALID
372 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
373 | SVM_EVTINJ_TYPE_EXEPT;
374 svm->vmcb->control.event_inj_err = error_code;
375}
376
6aa8b732
AK		 377static int has_svm(void)
378{
63d1142f 379 const char *msg;
6aa8b732 380
63d1142f 381 if (!cpu_has_svm(&msg)) {
ff81ff10 382 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 383 return 0;
384 }
385
6aa8b732
AK		 386 return 1;
387}
388
389static void svm_hardware_disable(void *garbage)
390{
2c8dceeb 391 cpu_svm_disable();
6aa8b732
AK		 392}
393
10474ae8 394static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 395{
396
0fe1e009 397 struct svm_cpu_data *sd;
6aa8b732 398 uint64_t efer;
89a27f4d 399 struct desc_ptr gdt_descr;
6aa8b732
AK		 400 struct desc_struct *gdt;
401 int me = raw_smp_processor_id();
402
10474ae8
AG		 403 rdmsrl(MSR_EFER, efer);
404 if (efer & EFER_SVME)
405 return -EBUSY;
406
6aa8b732 407 if (!has_svm()) {
e6732a5a
ZA		 408 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
409 me);
10474ae8 410 return -EINVAL;
6aa8b732 411 }
0fe1e009 412 sd = per_cpu(svm_data, me);
6aa8b732 413
0fe1e009 414 if (!sd) {
e6732a5a 415 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 416 me);
10474ae8 417 return -EINVAL;
6aa8b732
AK		 418 }
419
0fe1e009
TH		 420 sd->asid_generation = 1;
421 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
422 sd->next_asid = sd->max_asid + 1;
6aa8b732 423
d6ab1ed4 424 native_store_gdt(&gdt_descr);
89a27f4d 425 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 426 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 427
9962d032 428 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 429
d0316554 430 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 431
432 return 0;
6aa8b732
AK		 433}
434
0da1db75
JR		 435static void svm_cpu_uninit(int cpu)
436{
0fe1e009 437 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 438
0fe1e009 439 if (!sd)
0da1db75
JR		 440 return;
441
442 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 443 __free_page(sd->save_area);
444 kfree(sd);
0da1db75
JR		 445}
446
6aa8b732
AK		 447static int svm_cpu_init(int cpu)
448{
0fe1e009 449 struct svm_cpu_data *sd;
6aa8b732
AK		 450 int r;
451
0fe1e009
TH		 452 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
453 if (!sd)
6aa8b732 454 return -ENOMEM;
0fe1e009
TH		 455 sd->cpu = cpu;
456 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 457 r = -ENOMEM;
0fe1e009 458 if (!sd->save_area)
6aa8b732
AK		 459 goto err_1;
460
0fe1e009 461 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 462
463 return 0;
464
465err_1:
0fe1e009 466 kfree(sd);
6aa8b732
AK		 467 return r;
468
469}
470
ac72a9b7
JR		 471static bool valid_msr_intercept(u32 index)
472{
473 int i;
474
475 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
476 if (direct_access_msrs[i].index == index)
477 return true;
478
479 return false;
480}
481
bfc733a7
RR		 482static void set_msr_interception(u32 *msrpm, unsigned msr,
483 int read, int write)
6aa8b732 484{
455716fa
JR		 485 u8 bit_read, bit_write;
486 unsigned long tmp;
487 u32 offset;
6aa8b732 488
ac72a9b7
JR		 489 /*
490 * If this warning triggers extend the direct_access_msrs list at the
491 * beginning of the file
492 */
493 WARN_ON(!valid_msr_intercept(msr));
494
455716fa
JR		 495 offset = svm_msrpm_offset(msr);
496 bit_read = 2 * (msr & 0x0f);
497 bit_write = 2 * (msr & 0x0f) + 1;
498 tmp = msrpm[offset];
499
500 BUG_ON(offset == MSR_INVALID);
501
502 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
503 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
504
505 msrpm[offset] = tmp;
6aa8b732
AK		 506}
507
f65c229c 508static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 509{
510 int i;
511
f65c229c
JR		 512 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
513
ac72a9b7
JR		 514 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
515 if (!direct_access_msrs[i].always)
516 continue;
517
518 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
519 }
f65c229c
JR		 520}
521
323c3d80
JR		 522static void add_msr_offset(u32 offset)
523{
524 int i;
525
526 for (i = 0; i < MSRPM_OFFSETS; ++i) {
527
528 /* Offset already in list? */
529 if (msrpm_offsets[i] == offset)
bfc733a7 530 return;
323c3d80
JR		 531
532 /* Slot used by another offset? */
533 if (msrpm_offsets[i] != MSR_INVALID)
534 continue;
535
536 /* Add offset to list */
537 msrpm_offsets[i] = offset;
538
539 return;
6aa8b732 540 }
323c3d80
JR		 541
542 /*
543 * If this BUG triggers the msrpm_offsets table has an overflow. Just
544 * increase MSRPM_OFFSETS in this case.
545 */
bfc733a7 546 BUG();
6aa8b732
AK		 547}
548
323c3d80 549static void init_msrpm_offsets(void)
f65c229c 550{
323c3d80 551 int i;
f65c229c 552
323c3d80
JR		 553 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
554
555 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
556 u32 offset;
557
558 offset = svm_msrpm_offset(direct_access_msrs[i].index);
559 BUG_ON(offset == MSR_INVALID);
560
561 add_msr_offset(offset);
562 }
f65c229c
JR		 563}
564
24e09cbf
JR		 565static void svm_enable_lbrv(struct vcpu_svm *svm)
566{
567 u32 *msrpm = svm->msrpm;
568
569 svm->vmcb->control.lbr_ctl = 1;
570 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
571 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
572 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
573 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
574}
575
576static void svm_disable_lbrv(struct vcpu_svm *svm)
577{
578 u32 *msrpm = svm->msrpm;
579
580 svm->vmcb->control.lbr_ctl = 0;
581 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
582 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
583 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
584 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
585}
586
6aa8b732
AK		 587static __init int svm_hardware_setup(void)
588{
589 int cpu;
590 struct page *iopm_pages;
f65c229c 591 void *iopm_va;
6aa8b732
AK		 592 int r;
593
6aa8b732
AK		 594 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
595
596 if (!iopm_pages)
597 return -ENOMEM;
c8681339
AL		 598
599 iopm_va = page_address(iopm_pages);
600 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 601 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
602
323c3d80
JR		 603 init_msrpm_offsets();
604
50a37eb4
JR		 605 if (boot_cpu_has(X86_FEATURE_NX))
606 kvm_enable_efer_bits(EFER_NX);
607
1b2fd70c
AG		 608 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
609 kvm_enable_efer_bits(EFER_FFXSR);
610
236de055
AG		 611 if (nested) {
612 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
613 kvm_enable_efer_bits(EFER_SVME);
614 }
615
3230bb47 616 for_each_possible_cpu(cpu) {
6aa8b732
AK		 617 r = svm_cpu_init(cpu);
618 if (r)
f65c229c 619 goto err;
6aa8b732 620 }
33bd6a0b
JR		 621
622 svm_features = cpuid_edx(SVM_CPUID_FUNC);
623
e3da3acd
JR		 624 if (!svm_has(SVM_FEATURE_NPT))
625 npt_enabled = false;
626
6c7dac72
JR		 627 if (npt_enabled && !npt) {
628 printk(KERN_INFO "kvm: Nested Paging disabled\n");
629 npt_enabled = false;
630 }
631
18552672 632 if (npt_enabled) {
e3da3acd 633 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 634 kvm_enable_tdp();
5f4cb662
JR		 635 } else
636 kvm_disable_tdp();
e3da3acd 637
6aa8b732
AK		 638 return 0;
639
f65c229c 640err:
6aa8b732
AK		 641 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
642 iopm_base = 0;
643 return r;
644}
645
646static __exit void svm_hardware_unsetup(void)
647{
0da1db75
JR		 648 int cpu;
649
3230bb47 650 for_each_possible_cpu(cpu)
0da1db75
JR		 651 svm_cpu_uninit(cpu);
652
6aa8b732 653 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 654 iopm_base = 0;
6aa8b732
AK		 655}
656
657static void init_seg(struct vmcb_seg *seg)
658{
659 seg->selector = 0;
660 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 661 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 662 seg->limit = 0xffff;
663 seg->base = 0;
664}
665
666static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
667{
668 seg->selector = 0;
669 seg->attrib = SVM_SELECTOR_P_MASK | type;
670 seg->limit = 0xffff;
671 seg->base = 0;
672}
673
e6101a96 674static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 675{
e6101a96
JR		 676 struct vmcb_control_area *control = &svm->vmcb->control;
677 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 678
bff78274
AK		 679 svm->vcpu.fpu_active = 1;
680
e0231715 681 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 682 INTERCEPT_CR3_MASK |
649d6864 683 INTERCEPT_CR4_MASK;
6aa8b732 684
e0231715 685 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 686 INTERCEPT_CR3_MASK |
80a8119c
AK		 687 INTERCEPT_CR4_MASK |
688 INTERCEPT_CR8_MASK;
6aa8b732 689
e0231715 690 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 691 INTERCEPT_DR1_MASK |
692 INTERCEPT_DR2_MASK |
727f5a23
JK		 693 INTERCEPT_DR3_MASK |
694 INTERCEPT_DR4_MASK |
695 INTERCEPT_DR5_MASK |
696 INTERCEPT_DR6_MASK |
697 INTERCEPT_DR7_MASK;
6aa8b732 698
e0231715 699 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 700 INTERCEPT_DR1_MASK |
701 INTERCEPT_DR2_MASK |
702 INTERCEPT_DR3_MASK |
727f5a23 703 INTERCEPT_DR4_MASK |
6aa8b732 704 INTERCEPT_DR5_MASK |
727f5a23 705 INTERCEPT_DR6_MASK |
6aa8b732
AK		 706 INTERCEPT_DR7_MASK;
707
7aa81cc0 708 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 709 (1 << UD_VECTOR) |
710 (1 << MC_VECTOR);
6aa8b732
AK		 711
712
e0231715 713 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 714 (1ULL << INTERCEPT_NMI) |
0152527b 715 (1ULL << INTERCEPT_SMI) |
d225157b 716 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 717 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 718 (1ULL << INTERCEPT_INVD) |
6aa8b732 719 (1ULL << INTERCEPT_HLT) |
a7052897 720 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 721 (1ULL << INTERCEPT_INVLPGA) |
722 (1ULL << INTERCEPT_IOIO_PROT) |
723 (1ULL << INTERCEPT_MSR_PROT) |
724 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 725 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 726 (1ULL << INTERCEPT_VMRUN) |
727 (1ULL << INTERCEPT_VMMCALL) |
728 (1ULL << INTERCEPT_VMLOAD) |
729 (1ULL << INTERCEPT_VMSAVE) |
730 (1ULL << INTERCEPT_STGI) |
731 (1ULL << INTERCEPT_CLGI) |
916ce236 732 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 733 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 734 (1ULL << INTERCEPT_MONITOR) |
735 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 736
737 control->iopm_base_pa = iopm_base;
f65c229c 738 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 739 control->tsc_offset = 0;
6aa8b732
AK		 740 control->int_ctl = V_INTR_MASKING_MASK;
741
742 init_seg(&save->es);
743 init_seg(&save->ss);
744 init_seg(&save->ds);
745 init_seg(&save->fs);
746 init_seg(&save->gs);
747
748 save->cs.selector = 0xf000;
749 /* Executable/Readable Code Segment */
750 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
751 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
752 save->cs.limit = 0xffff;
d92899a0
AK		 753 /*
754 * cs.base should really be 0xffff0000, but vmx can't handle that, so
755 * be consistent with it.
756 *
757 * Replace when we have real mode working for vmx.
758 */
759 save->cs.base = 0xf0000;
6aa8b732
AK		 760
761 save->gdtr.limit = 0xffff;
762 save->idtr.limit = 0xffff;
763
764 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
765 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
766
9962d032 767 save->efer = EFER_SVME;
d77c26fc 768 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 769 save->dr7 = 0x400;
770 save->rflags = 2;
771 save->rip = 0x0000fff0;
5fdbf976 772 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 773
e0231715
JR		 774 /*
775 * This is the guest-visible cr0 value.
18fa000a 776 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 777 */
18fa000a
EH		 778 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
779 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
780
66aee91a 781 save->cr4 = X86_CR4_PAE;
6aa8b732 782 /* rdx = ?? */
709ddebf
JR		 783
784 if (npt_enabled) {
785 /* Setup VMCB for Nested Paging */
786 control->nested_ctl = 1;
a7052897
MT		 787 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
788 (1ULL << INTERCEPT_INVLPG));
709ddebf 789 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 790 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
791 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 792 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 793 save->cr3 = 0;
794 save->cr4 = 0;
795 }
a79d2f18 796 force_new_asid(&svm->vcpu);
1371d904 797
e6aa9abd 798 svm->nested.vmcb = 0;
2af9194d
JR		 799 svm->vcpu.arch.hflags = 0;
800
565d0998
ML		 801 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
802 control->pause_filter_count = 3000;
803 control->intercept |= (1ULL << INTERCEPT_PAUSE);
804 }
805
2af9194d 806 enable_gif(svm);
6aa8b732
AK		 807}
808
e00c8cf2 809static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 810{
811 struct vcpu_svm *svm = to_svm(vcpu);
812
e6101a96 813 init_vmcb(svm);
70433389 814
c5af89b6 815 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 816 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 817 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
818 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 819 }
5fdbf976
MT		 820 vcpu->arch.regs_avail = ~0;
821 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 822
823 return 0;
04d2cc77
AK		 824}
825
fb3f0f51 826static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 827{
a2fa3e9f 828 struct vcpu_svm *svm;
6aa8b732 829 struct page *page;
f65c229c 830 struct page *msrpm_pages;
b286d5d8 831 struct page *hsave_page;
3d6368ef 832 struct page *nested_msrpm_pages;
fb3f0f51 833 int err;
6aa8b732 834
c16f862d 835 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 836 if (!svm) {
837 err = -ENOMEM;
838 goto out;
839 }
840
841 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
842 if (err)
843 goto free_svm;
844
b7af4043 845 err = -ENOMEM;
6aa8b732 846 page = alloc_page(GFP_KERNEL);
b7af4043 847 if (!page)
fb3f0f51 848 goto uninit;
6aa8b732 849
f65c229c
JR		 850 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
851 if (!msrpm_pages)
b7af4043 852 goto free_page1;
3d6368ef
AG		 853
854 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
855 if (!nested_msrpm_pages)
b7af4043 856 goto free_page2;
f65c229c 857
b286d5d8
AG		 858 hsave_page = alloc_page(GFP_KERNEL);
859 if (!hsave_page)
b7af4043
TY		 860 goto free_page3;
861
e6aa9abd 862 svm->nested.hsave = page_address(hsave_page);
b286d5d8 863
b7af4043
TY		 864 svm->msrpm = page_address(msrpm_pages);
865 svm_vcpu_init_msrpm(svm->msrpm);
866
e6aa9abd 867 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 868 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 869
a2fa3e9f
GH		 870 svm->vmcb = page_address(page);
871 clear_page(svm->vmcb);
872 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
873 svm->asid_generation = 0;
e6101a96 874 init_vmcb(svm);
a2fa3e9f 875
fb3f0f51 876 fx_init(&svm->vcpu);
ad312c7c 877 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 878 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 879 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 880
fb3f0f51 881 return &svm->vcpu;
36241b8c 882
b7af4043
TY		 883free_page3:
884 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
885free_page2:
886 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
887free_page1:
888 __free_page(page);
fb3f0f51
RR		 889uninit:
890 kvm_vcpu_uninit(&svm->vcpu);
891free_svm:
a4770347 892 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 893out:
894 return ERR_PTR(err);
6aa8b732
AK		 895}
896
897static void svm_free_vcpu(struct kvm_vcpu *vcpu)
898{
a2fa3e9f
GH		 899 struct vcpu_svm *svm = to_svm(vcpu);
900
fb3f0f51 901 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 902 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 903 __free_page(virt_to_page(svm->nested.hsave));
904 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 905 kvm_vcpu_uninit(vcpu);
a4770347 906 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 907}
908
15ad7146 909static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 910{
a2fa3e9f 911 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 912 int i;
0cc5064d 913
0cc5064d 914 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 915 u64 delta;
0cc5064d 916
953899b6
JR		 917 if (check_tsc_unstable()) {
918 /*
919 * Make sure that the guest sees a monotonically
920 * increasing TSC.
921 */
922 delta = vcpu->arch.host_tsc - native_read_tsc();
923 svm->vmcb->control.tsc_offset += delta;
924 if (is_nested(svm))
925 svm->nested.hsave->control.tsc_offset += delta;
926 }
0cc5064d 927 vcpu->cpu = cpu;
2f599714 928 kvm_migrate_timers(vcpu);
4b656b12 929 svm->asid_generation = 0;
0cc5064d 930 }
94dfbdb3
AL		 931
932 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 933 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 934}
935
936static void svm_vcpu_put(struct kvm_vcpu *vcpu)
937{
a2fa3e9f 938 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 939 int i;
940
e1beb1d3 941 ++vcpu->stat.host_state_reload;
94dfbdb3 942 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 943 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 944
e935d48e 945 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 946}
947
6aa8b732
AK		 948static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
949{
a2fa3e9f 950 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 951}
952
953static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
954{
a2fa3e9f 955 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 956}
957
6de4f3ad
AK		 958static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
959{
960 switch (reg) {
961 case VCPU_EXREG_PDPTR:
962 BUG_ON(!npt_enabled);
963 load_pdptrs(vcpu, vcpu->arch.cr3);
964 break;
965 default:
966 BUG();
967 }
968}
969
f0b85051
AG		 970static void svm_set_vintr(struct vcpu_svm *svm)
971{
972 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
973}
974
975static void svm_clear_vintr(struct vcpu_svm *svm)
976{
977 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
978}
979
6aa8b732
AK		 980static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
981{
a2fa3e9f 982 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 983
984 switch (seg) {
985 case VCPU_SREG_CS: return &save->cs;
986 case VCPU_SREG_DS: return &save->ds;
987 case VCPU_SREG_ES: return &save->es;
988 case VCPU_SREG_FS: return &save->fs;
989 case VCPU_SREG_GS: return &save->gs;
990 case VCPU_SREG_SS: return &save->ss;
991 case VCPU_SREG_TR: return &save->tr;
992 case VCPU_SREG_LDTR: return &save->ldtr;
993 }
994 BUG();
8b6d44c7 995 return NULL;
6aa8b732
AK		 996}
997
998static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
999{
1000 struct vmcb_seg *s = svm_seg(vcpu, seg);
1001
1002 return s->base;
1003}
1004
1005static void svm_get_segment(struct kvm_vcpu *vcpu,
1006 struct kvm_segment *var, int seg)
1007{
1008 struct vmcb_seg *s = svm_seg(vcpu, seg);
1009
1010 var->base = s->base;
1011 var->limit = s->limit;
1012 var->selector = s->selector;
1013 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1014 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1015 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1016 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1017 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1018 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1019 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1020 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1021
e0231715
JR		 1022 /*
1023 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1024 * for cross vendor migration purposes by "not present"
1025 */
1026 var->unusable = !var->present || (var->type == 0);
1027
1fbdc7a5
AP		 1028 switch (seg) {
1029 case VCPU_SREG_CS:
1030 /*
1031 * SVM always stores 0 for the 'G' bit in the CS selector in
1032 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1033 * Intel's VMENTRY has a check on the 'G' bit.
1034 */
25022acc 1035 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1036 break;
1037 case VCPU_SREG_TR:
1038 /*
1039 * Work around a bug where the busy flag in the tr selector
1040 * isn't exposed
1041 */
c0d09828 1042 var->type |= 0x2;
1fbdc7a5
AP		 1043 break;
1044 case VCPU_SREG_DS:
1045 case VCPU_SREG_ES:
1046 case VCPU_SREG_FS:
1047 case VCPU_SREG_GS:
1048 /*
1049 * The accessed bit must always be set in the segment
1050 * descriptor cache, although it can be cleared in the
1051 * descriptor, the cached bit always remains at 1. Since
1052 * Intel has a check on this, set it here to support
1053 * cross-vendor migration.
1054 */
1055 if (!var->unusable)
1056 var->type |= 0x1;
1057 break;
b586eb02 1058 case VCPU_SREG_SS:
e0231715
JR		 1059 /*
1060 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1061 * descriptor is left as 1, although the whole segment has
1062 * been made unusable. Clear it here to pass an Intel VMX
1063 * entry check when cross vendor migrating.
1064 */
1065 if (var->unusable)
1066 var->db = 0;
1067 break;
1fbdc7a5 1068 }
6aa8b732
AK		 1069}
1070
2e4d2653
IE		 1071static int svm_get_cpl(struct kvm_vcpu *vcpu)
1072{
1073 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1074
1075 return save->cpl;
1076}
1077
89a27f4d 1078static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1079{
a2fa3e9f
GH		 1080 struct vcpu_svm *svm = to_svm(vcpu);
1081
89a27f4d
GN		 1082 dt->size = svm->vmcb->save.idtr.limit;
1083 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1084}
1085
89a27f4d 1086static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1087{
a2fa3e9f
GH		 1088 struct vcpu_svm *svm = to_svm(vcpu);
1089
89a27f4d
GN		 1090 svm->vmcb->save.idtr.limit = dt->size;
1091 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1092}
1093
89a27f4d 1094static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1095{
a2fa3e9f
GH		 1096 struct vcpu_svm *svm = to_svm(vcpu);
1097
89a27f4d
GN		 1098 dt->size = svm->vmcb->save.gdtr.limit;
1099 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1100}
1101
89a27f4d 1102static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1103{
a2fa3e9f
GH		 1104 struct vcpu_svm *svm = to_svm(vcpu);
1105
89a27f4d
GN		 1106 svm->vmcb->save.gdtr.limit = dt->size;
1107 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1108}
1109
e8467fda
AK		 1110static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1111{
1112}
1113
25c4c276 1114static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1115{
1116}
1117
d225157b
AK		 1118static void update_cr0_intercept(struct vcpu_svm *svm)
1119{
66a562f7 1120 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1121 ulong gcr0 = svm->vcpu.arch.cr0;
1122 u64 *hcr0 = &svm->vmcb->save.cr0;
1123
1124 if (!svm->vcpu.fpu_active)
1125 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1126 else
1127 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1128 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1129
1130
1131 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1132 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1133 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1134 if (is_nested(svm)) {
1135 struct vmcb *hsave = svm->nested.hsave;
1136
1137 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1138 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1139 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1140 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1141 }
d225157b
AK		 1142 } else {
1143 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1144 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1145 if (is_nested(svm)) {
1146 struct vmcb *hsave = svm->nested.hsave;
1147
1148 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1149 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1150 }
d225157b
AK		 1151 }
1152}
1153
6aa8b732
AK		 1154static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1155{
a2fa3e9f
GH		 1156 struct vcpu_svm *svm = to_svm(vcpu);
1157
7f5d8b56
JR		 1158 if (is_nested(svm)) {
1159 /*
1160 * We are here because we run in nested mode, the host kvm
1161 * intercepts cr0 writes but the l1 hypervisor does not.
1162 * But the L1 hypervisor may intercept selective cr0 writes.
1163 * This needs to be checked here.
1164 */
1165 unsigned long old, new;
1166
1167 /* Remove bits that would trigger a real cr0 write intercept */
1168 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1169 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1170
1171 if (old == new) {
1172 /* cr0 write with ts and mp unchanged */
1173 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1174 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1175 return;
1176 }
1177 }
1178
05b3e0c2 1179#ifdef CONFIG_X86_64
f6801dff 1180 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1181 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1182 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1183 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1184 }
1185
d77c26fc 1186 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1187 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1188 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1189 }
1190 }
1191#endif
ad312c7c 1192 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1193
1194 if (!npt_enabled)
1195 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1196
1197 if (!vcpu->fpu_active)
334df50a 1198 cr0 |= X86_CR0_TS;
709ddebf
JR		 1199 /*
1200 * re-enable caching here because the QEMU bios
1201 * does not do it - this results in some delay at
1202 * reboot
1203 */
1204 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1205 svm->vmcb->save.cr0 = cr0;
d225157b 1206 update_cr0_intercept(svm);
6aa8b732
AK		 1207}
1208
1209static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1210{
6394b649 1211 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1212 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1213
1214 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1215 force_new_asid(vcpu);
6394b649 1216
ec077263
JR		 1217 vcpu->arch.cr4 = cr4;
1218 if (!npt_enabled)
1219 cr4 |= X86_CR4_PAE;
6394b649 1220 cr4 |= host_cr4_mce;
ec077263 1221 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1222}
1223
1224static void svm_set_segment(struct kvm_vcpu *vcpu,
1225 struct kvm_segment *var, int seg)
1226{
a2fa3e9f 1227 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1228 struct vmcb_seg *s = svm_seg(vcpu, seg);
1229
1230 s->base = var->base;
1231 s->limit = var->limit;
1232 s->selector = var->selector;
1233 if (var->unusable)
1234 s->attrib = 0;
1235 else {
1236 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1237 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1238 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1239 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1240 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1241 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1242 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1243 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1244 }
1245 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1246 svm->vmcb->save.cpl
1247 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1248 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1249
1250}
1251
44c11430 1252static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1253{
d0bfb940
JK		 1254 struct vcpu_svm *svm = to_svm(vcpu);
1255
d0bfb940
JK		 1256 svm->vmcb->control.intercept_exceptions &=
1257 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1258
6be7d306 1259 if (svm->nmi_singlestep)
44c11430
GN		 1260 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1261
d0bfb940
JK		 1262 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1263 if (vcpu->guest_debug &
1264 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1265 svm->vmcb->control.intercept_exceptions |=
1266 1 << DB_VECTOR;
1267 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1268 svm->vmcb->control.intercept_exceptions |=
1269 1 << BP_VECTOR;
1270 } else
1271 vcpu->guest_debug = 0;
44c11430
GN		 1272}
1273
355be0b9 1274static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1275{
44c11430
GN		 1276 struct vcpu_svm *svm = to_svm(vcpu);
1277
ae675ef0
JK		 1278 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1279 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1280 else
1281 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1282
355be0b9 1283 update_db_intercept(vcpu);
6aa8b732
AK		 1284}
1285
1286static void load_host_msrs(struct kvm_vcpu *vcpu)
1287{
94dfbdb3 1288#ifdef CONFIG_X86_64
a2fa3e9f 1289 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1290#endif
6aa8b732
AK		 1291}
1292
1293static void save_host_msrs(struct kvm_vcpu *vcpu)
1294{
94dfbdb3 1295#ifdef CONFIG_X86_64
a2fa3e9f 1296 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1297#endif
6aa8b732
AK		 1298}
1299
0fe1e009 1300static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1301{
0fe1e009
TH		 1302 if (sd->next_asid > sd->max_asid) {
1303 ++sd->asid_generation;
1304 sd->next_asid = 1;
a2fa3e9f 1305 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1306 }
1307
0fe1e009
TH		 1308 svm->asid_generation = sd->asid_generation;
1309 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1310}
1311
020df079 1312static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1313{
42dbaa5a 1314 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1315
020df079 1316 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1317}
1318
851ba692 1319static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1320{
6aa8b732
AK		 1321 u64 fault_address;
1322 u32 error_code;
6aa8b732 1323
a2fa3e9f
GH		 1324 fault_address = svm->vmcb->control.exit_info_2;
1325 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1326
229456fc 1327 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1328 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1329 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1330 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1331}
1332
851ba692 1333static int db_interception(struct vcpu_svm *svm)
d0bfb940 1334{
851ba692
AK		 1335 struct kvm_run *kvm_run = svm->vcpu.run;
1336
d0bfb940 1337 if (!(svm->vcpu.guest_debug &
44c11430 1338 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1339 !svm->nmi_singlestep) {
d0bfb940
JK		 1340 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1341 return 1;
1342 }
44c11430 1343
6be7d306
JK		 1344 if (svm->nmi_singlestep) {
1345 svm->nmi_singlestep = false;
44c11430
GN		 1346 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1347 svm->vmcb->save.rflags &=
1348 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1349 update_db_intercept(&svm->vcpu);
1350 }
1351
1352 if (svm->vcpu.guest_debug &
e0231715 1353 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1354 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1355 kvm_run->debug.arch.pc =
1356 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1357 kvm_run->debug.arch.exception = DB_VECTOR;
1358 return 0;
1359 }
1360
1361 return 1;
d0bfb940
JK		 1362}
1363
851ba692 1364static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1365{
851ba692
AK		 1366 struct kvm_run *kvm_run = svm->vcpu.run;
1367
d0bfb940
JK		 1368 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1369 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1370 kvm_run->debug.arch.exception = BP_VECTOR;
1371 return 0;
1372}
1373
851ba692 1374static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1375{
1376 int er;
1377
851ba692 1378 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1379 if (er != EMULATE_DONE)
7ee5d940 1380 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1381 return 1;
1382}
1383
6b52d186 1384static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1385{
6b52d186 1386 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1387 u32 excp;
1388
1389 if (is_nested(svm)) {
1390 u32 h_excp, n_excp;
1391
1392 h_excp = svm->nested.hsave->control.intercept_exceptions;
1393 n_excp = svm->nested.intercept_exceptions;
1394 h_excp &= ~(1 << NM_VECTOR);
1395 excp = h_excp | n_excp;
1396 } else {
1397 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1398 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1399 }
1400
1401 svm->vmcb->control.intercept_exceptions = excp;
1402
e756fc62 1403 svm->vcpu.fpu_active = 1;
d225157b 1404 update_cr0_intercept(svm);
6b52d186 1405}
a2fa3e9f 1406
6b52d186
AK		 1407static int nm_interception(struct vcpu_svm *svm)
1408{
1409 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1410 return 1;
7807fa6c
AL		 1411}
1412
fe5913e4 1413static void svm_handle_mce(struct vcpu_svm *svm)
53371b50
JR		 1414{
1415 /*
1416 * On an #MC intercept the MCE handler is not called automatically in
1417 * the host. So do it by hand here.
1418 */
1419 asm volatile (
1420 "int $0x12\n");
1421 /* not sure if we ever come back to this point */
1422
fe5913e4
JR		 1423 return;
1424}
1425
1426static int mc_interception(struct vcpu_svm *svm)
1427{
53371b50
JR		 1428 return 1;
1429}
1430
851ba692 1431static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1432{
851ba692
AK		 1433 struct kvm_run *kvm_run = svm->vcpu.run;
1434
46fe4ddd
JR		 1435 /*
1436 * VMCB is undefined after a SHUTDOWN intercept
1437 * so reinitialize it.
1438 */
a2fa3e9f 1439 clear_page(svm->vmcb);
e6101a96 1440 init_vmcb(svm);
46fe4ddd
JR		 1441
1442 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1443 return 0;
1444}
1445
851ba692 1446static int io_interception(struct vcpu_svm *svm)
6aa8b732 1447{
cf8f70bf 1448 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1449 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1450 int size, in, string;
039576c0 1451 unsigned port;
6aa8b732 1452
e756fc62 1453 ++svm->vcpu.stat.io_exits;
e70669ab 1454 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1455 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf
GN		 1456 if (string || in)
1457 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1458
039576c0
AK		 1459 port = io_info >> 16;
1460 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1461 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1462 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1463
1464 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1465}
1466
851ba692 1467static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1468{
1469 return 1;
1470}
1471
851ba692 1472static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1473{
1474 ++svm->vcpu.stat.irq_exits;
1475 return 1;
1476}
1477
851ba692 1478static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1479{
1480 return 1;
1481}
1482
851ba692 1483static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1484{
5fdbf976 1485 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1486 skip_emulated_instruction(&svm->vcpu);
1487 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1488}
1489
851ba692 1490static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1491{
5fdbf976 1492 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1493 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1494 kvm_emulate_hypercall(&svm->vcpu);
1495 return 1;
02e235bc
AK		 1496}
1497
c0725420
AG		 1498static int nested_svm_check_permissions(struct vcpu_svm *svm)
1499{
f6801dff 1500 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1501 || !is_paging(&svm->vcpu)) {
1502 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1503 return 1;
1504 }
1505
1506 if (svm->vmcb->save.cpl) {
1507 kvm_inject_gp(&svm->vcpu, 0);
1508 return 1;
1509 }
1510
1511 return 0;
1512}
1513
cf74a78b
AG		 1514static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1515 bool has_error_code, u32 error_code)
1516{
b8e88bc8
JR		 1517 int vmexit;
1518
0295ad7d
JR		 1519 if (!is_nested(svm))
1520 return 0;
cf74a78b 1521
0295ad7d
JR		 1522 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1523 svm->vmcb->control.exit_code_hi = 0;
1524 svm->vmcb->control.exit_info_1 = error_code;
1525 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1526
b8e88bc8
JR		 1527 vmexit = nested_svm_intercept(svm);
1528 if (vmexit == NESTED_EXIT_DONE)
1529 svm->nested.exit_required = true;
1530
1531 return vmexit;
cf74a78b
AG		 1532}
1533
8fe54654
JR		 1534/* This function returns true if it is save to enable the irq window */
1535static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1536{
26666957 1537 if (!is_nested(svm))
8fe54654 1538 return true;
cf74a78b 1539
26666957 1540 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1541 return true;
cf74a78b 1542
26666957 1543 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1544 return false;
cf74a78b 1545
197717d5
JR		 1546 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1547 svm->vmcb->control.exit_info_1 = 0;
1548 svm->vmcb->control.exit_info_2 = 0;
26666957 1549
cd3ff653
JR		 1550 if (svm->nested.intercept & 1ULL) {
1551 /*
1552 * The #vmexit can't be emulated here directly because this
1553 * code path runs with irqs and preemtion disabled. A
1554 * #vmexit emulation might sleep. Only signal request for
1555 * the #vmexit here.
1556 */
1557 svm->nested.exit_required = true;
236649de 1558 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1559 return false;
cf74a78b
AG		 1560 }
1561
8fe54654 1562 return true;
cf74a78b
AG		 1563}
1564
887f500c
JR		 1565/* This function returns true if it is save to enable the nmi window */
1566static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1567{
1568 if (!is_nested(svm))
1569 return true;
1570
1571 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1572 return true;
1573
1574 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1575 svm->nested.exit_required = true;
1576
1577 return false;
cf74a78b
AG		 1578}
1579
7597f129 1580static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1581{
1582 struct page *page;
1583
6c3bd3d7
JR		 1584 might_sleep();
1585
34f80cfa 1586 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1587 if (is_error_page(page))
1588 goto error;
1589
7597f129
JR		 1590 *_page = page;
1591
1592 return kmap(page);
34f80cfa
JR		 1593
1594error:
1595 kvm_release_page_clean(page);
1596 kvm_inject_gp(&svm->vcpu, 0);
1597
1598 return NULL;
1599}
1600
7597f129 1601static void nested_svm_unmap(struct page *page)
34f80cfa 1602{
7597f129 1603 kunmap(page);
34f80cfa
JR		 1604 kvm_release_page_dirty(page);
1605}
34f80cfa 1606
ce2ac085
JR		 1607static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1608{
1609 unsigned port;
1610 u8 val, bit;
1611 u64 gpa;
34f80cfa 1612
ce2ac085
JR		 1613 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1614 return NESTED_EXIT_HOST;
34f80cfa 1615
ce2ac085
JR		 1616 port = svm->vmcb->control.exit_info_1 >> 16;
1617 gpa = svm->nested.vmcb_iopm + (port / 8);
1618 bit = port % 8;
1619 val = 0;
1620
1621 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1622 val &= (1 << bit);
1623
1624 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1625}
1626
d2477826 1627static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1628{
0d6b3537
JR		 1629 u32 offset, msr, value;
1630 int write, mask;
4c2161ae 1631
3d62d9aa 1632 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1633 return NESTED_EXIT_HOST;
3d62d9aa 1634
0d6b3537
JR		 1635 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1636 offset = svm_msrpm_offset(msr);
1637 write = svm->vmcb->control.exit_info_1 & 1;
1638 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1639
0d6b3537
JR		 1640 if (offset == MSR_INVALID)
1641 return NESTED_EXIT_DONE;
4c2161ae 1642
0d6b3537
JR		 1643 /* Offset is in 32 bit units but need in 8 bit units */
1644 offset *= 4;
4c2161ae 1645
0d6b3537
JR		 1646 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1647 return NESTED_EXIT_DONE;
3d62d9aa 1648
0d6b3537 1649 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1650}
1651
410e4d57 1652static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1653{
cf74a78b 1654 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1655
410e4d57
JR		 1656 switch (exit_code) {
1657 case SVM_EXIT_INTR:
1658 case SVM_EXIT_NMI:
ff47a49b 1659 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1660 return NESTED_EXIT_HOST;
410e4d57 1661 case SVM_EXIT_NPF:
e0231715 1662 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1663 if (npt_enabled)
1664 return NESTED_EXIT_HOST;
1665 break;
410e4d57 1666 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1667 /* When we're shadowing, trap PFs */
410e4d57
JR		 1668 if (!npt_enabled)
1669 return NESTED_EXIT_HOST;
1670 break;
66a562f7
JR		 1671 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1672 nm_interception(svm);
1673 break;
410e4d57
JR		 1674 default:
1675 break;
cf74a78b
AG		 1676 }
1677
410e4d57
JR		 1678 return NESTED_EXIT_CONTINUE;
1679}
1680
1681/*
1682 * If this function returns true, this #vmexit was already handled
1683 */
b8e88bc8 1684static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1685{
1686 u32 exit_code = svm->vmcb->control.exit_code;
1687 int vmexit = NESTED_EXIT_HOST;
1688
cf74a78b 1689 switch (exit_code) {
9c4e40b9 1690 case SVM_EXIT_MSR:
3d62d9aa 1691 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1692 break;
ce2ac085
JR		 1693 case SVM_EXIT_IOIO:
1694 vmexit = nested_svm_intercept_ioio(svm);
1695 break;
cf74a78b
AG		 1696 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1697 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1698 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1699 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1700 break;
1701 }
1702 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1703 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1704 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1705 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1706 break;
1707 }
1708 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1709 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1710 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1711 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1712 break;
1713 }
1714 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1715 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1716 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1717 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1718 break;
1719 }
1720 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1721 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1722 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1723 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1724 break;
1725 }
228070b1
JR		 1726 case SVM_EXIT_ERR: {
1727 vmexit = NESTED_EXIT_DONE;
1728 break;
1729 }
cf74a78b
AG		 1730 default: {
1731 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1732 if (svm->nested.intercept & exit_bits)
410e4d57 1733 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1734 }
1735 }
1736
b8e88bc8
JR		 1737 return vmexit;
1738}
1739
1740static int nested_svm_exit_handled(struct vcpu_svm *svm)
1741{
1742 int vmexit;
1743
1744 vmexit = nested_svm_intercept(svm);
1745
1746 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1747 nested_svm_vmexit(svm);
9c4e40b9
JR		 1748
1749 return vmexit;
cf74a78b
AG		 1750}
1751
0460a979
JR		 1752static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1753{
1754 struct vmcb_control_area *dst = &dst_vmcb->control;
1755 struct vmcb_control_area *from = &from_vmcb->control;
1756
1757 dst->intercept_cr_read = from->intercept_cr_read;
1758 dst->intercept_cr_write = from->intercept_cr_write;
1759 dst->intercept_dr_read = from->intercept_dr_read;
1760 dst->intercept_dr_write = from->intercept_dr_write;
1761 dst->intercept_exceptions = from->intercept_exceptions;
1762 dst->intercept = from->intercept;
1763 dst->iopm_base_pa = from->iopm_base_pa;
1764 dst->msrpm_base_pa = from->msrpm_base_pa;
1765 dst->tsc_offset = from->tsc_offset;
1766 dst->asid = from->asid;
1767 dst->tlb_ctl = from->tlb_ctl;
1768 dst->int_ctl = from->int_ctl;
1769 dst->int_vector = from->int_vector;
1770 dst->int_state = from->int_state;
1771 dst->exit_code = from->exit_code;
1772 dst->exit_code_hi = from->exit_code_hi;
1773 dst->exit_info_1 = from->exit_info_1;
1774 dst->exit_info_2 = from->exit_info_2;
1775 dst->exit_int_info = from->exit_int_info;
1776 dst->exit_int_info_err = from->exit_int_info_err;
1777 dst->nested_ctl = from->nested_ctl;
1778 dst->event_inj = from->event_inj;
1779 dst->event_inj_err = from->event_inj_err;
1780 dst->nested_cr3 = from->nested_cr3;
1781 dst->lbr_ctl = from->lbr_ctl;
1782}
1783
34f80cfa 1784static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1785{
34f80cfa 1786 struct vmcb *nested_vmcb;
e6aa9abd 1787 struct vmcb *hsave = svm->nested.hsave;
33740e40 1788 struct vmcb *vmcb = svm->vmcb;
7597f129 1789 struct page *page;
cf74a78b 1790
17897f36
JR		 1791 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1792 vmcb->control.exit_info_1,
1793 vmcb->control.exit_info_2,
1794 vmcb->control.exit_int_info,
1795 vmcb->control.exit_int_info_err);
1796
7597f129 1797 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1798 if (!nested_vmcb)
1799 return 1;
1800
06fc7772
JR		 1801 /* Exit nested SVM mode */
1802 svm->nested.vmcb = 0;
1803
cf74a78b 1804 /* Give the current vmcb to the guest */
33740e40
JR		 1805 disable_gif(svm);
1806
1807 nested_vmcb->save.es = vmcb->save.es;
1808 nested_vmcb->save.cs = vmcb->save.cs;
1809 nested_vmcb->save.ss = vmcb->save.ss;
1810 nested_vmcb->save.ds = vmcb->save.ds;
1811 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1812 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1813 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1814 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1815 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1816 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1817 nested_vmcb->save.rflags = vmcb->save.rflags;
1818 nested_vmcb->save.rip = vmcb->save.rip;
1819 nested_vmcb->save.rsp = vmcb->save.rsp;
1820 nested_vmcb->save.rax = vmcb->save.rax;
1821 nested_vmcb->save.dr7 = vmcb->save.dr7;
1822 nested_vmcb->save.dr6 = vmcb->save.dr6;
1823 nested_vmcb->save.cpl = vmcb->save.cpl;
1824
1825 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1826 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1827 nested_vmcb->control.int_state = vmcb->control.int_state;
1828 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1829 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1830 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1831 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1832 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1833 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1834
1835 /*
1836 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1837 * to make sure that we do not lose injected events. So check event_inj
1838 * here and copy it to exit_int_info if it is valid.
1839 * Exit_int_info and event_inj can't be both valid because the case
1840 * below only happens on a VMRUN instruction intercept which has
1841 * no valid exit_int_info set.
1842 */
1843 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1844 struct vmcb_control_area *nc = &nested_vmcb->control;
1845
1846 nc->exit_int_info = vmcb->control.event_inj;
1847 nc->exit_int_info_err = vmcb->control.event_inj_err;
1848 }
1849
33740e40
JR		 1850 nested_vmcb->control.tlb_ctl = 0;
1851 nested_vmcb->control.event_inj = 0;
1852 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1853
1854 /* We always set V_INTR_MASKING and remember the old value in hflags */
1855 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1856 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1857
cf74a78b 1858 /* Restore the original control entries */
0460a979 1859 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1860
219b65dc
AG		 1861 kvm_clear_exception_queue(&svm->vcpu);
1862 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1863
1864 /* Restore selected save entries */
1865 svm->vmcb->save.es = hsave->save.es;
1866 svm->vmcb->save.cs = hsave->save.cs;
1867 svm->vmcb->save.ss = hsave->save.ss;
1868 svm->vmcb->save.ds = hsave->save.ds;
1869 svm->vmcb->save.gdtr = hsave->save.gdtr;
1870 svm->vmcb->save.idtr = hsave->save.idtr;
1871 svm->vmcb->save.rflags = hsave->save.rflags;
1872 svm_set_efer(&svm->vcpu, hsave->save.efer);
1873 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1874 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1875 if (npt_enabled) {
1876 svm->vmcb->save.cr3 = hsave->save.cr3;
1877 svm->vcpu.arch.cr3 = hsave->save.cr3;
1878 } else {
1879 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1880 }
1881 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1882 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1883 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1884 svm->vmcb->save.dr7 = 0;
1885 svm->vmcb->save.cpl = 0;
1886 svm->vmcb->control.exit_int_info = 0;
1887
7597f129 1888 nested_svm_unmap(page);
cf74a78b
AG		 1889
1890 kvm_mmu_reset_context(&svm->vcpu);
1891 kvm_mmu_load(&svm->vcpu);
1892
1893 return 0;
1894}
3d6368ef 1895
9738b2c9 1896static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1897{
323c3d80
JR		 1898 /*
1899 * This function merges the msr permission bitmaps of kvm and the
1900 * nested vmcb. It is omptimized in that it only merges the parts where
1901 * the kvm msr permission bitmap may contain zero bits
1902 */
3d6368ef 1903 int i;
9738b2c9 1904
323c3d80
JR		 1905 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1906 return true;
9738b2c9 1907
323c3d80
JR		 1908 for (i = 0; i < MSRPM_OFFSETS; i++) {
1909 u32 value, p;
1910 u64 offset;
9738b2c9 1911
323c3d80
JR		 1912 if (msrpm_offsets[i] == 0xffffffff)
1913 break;
3d6368ef 1914
0d6b3537
JR		 1915 p = msrpm_offsets[i];
1916 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1917
1918 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1919 return false;
1920
1921 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1922 }
3d6368ef 1923
323c3d80 1924 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 1925
1926 return true;
3d6368ef
AG		 1927}
1928
9738b2c9 1929static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1930{
9738b2c9 1931 struct vmcb *nested_vmcb;
e6aa9abd 1932 struct vmcb *hsave = svm->nested.hsave;
defbba56 1933 struct vmcb *vmcb = svm->vmcb;
7597f129 1934 struct page *page;
06fc7772 1935 u64 vmcb_gpa;
3d6368ef 1936
06fc7772 1937 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1938
7597f129 1939 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1940 if (!nested_vmcb)
1941 return false;
1942
ecf1405d 1943 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1944 nested_vmcb->save.rip,
1945 nested_vmcb->control.int_ctl,
1946 nested_vmcb->control.event_inj,
1947 nested_vmcb->control.nested_ctl);
1948
2e554e8d
JR		 1949 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1950 nested_vmcb->control.intercept_cr_write,
1951 nested_vmcb->control.intercept_exceptions,
1952 nested_vmcb->control.intercept);
1953
3d6368ef 1954 /* Clear internal status */
219b65dc
AG		 1955 kvm_clear_exception_queue(&svm->vcpu);
1956 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1957
e0231715
JR		 1958 /*
1959 * Save the old vmcb, so we don't need to pick what we save, but can
1960 * restore everything when a VMEXIT occurs
1961 */
defbba56
JR		 1962 hsave->save.es = vmcb->save.es;
1963 hsave->save.cs = vmcb->save.cs;
1964 hsave->save.ss = vmcb->save.ss;
1965 hsave->save.ds = vmcb->save.ds;
1966 hsave->save.gdtr = vmcb->save.gdtr;
1967 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1968 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1969 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1970 hsave->save.cr4 = svm->vcpu.arch.cr4;
1971 hsave->save.rflags = vmcb->save.rflags;
1972 hsave->save.rip = svm->next_rip;
1973 hsave->save.rsp = vmcb->save.rsp;
1974 hsave->save.rax = vmcb->save.rax;
1975 if (npt_enabled)
1976 hsave->save.cr3 = vmcb->save.cr3;
1977 else
1978 hsave->save.cr3 = svm->vcpu.arch.cr3;
1979
0460a979 1980 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1981
1982 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1983 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1984 else
1985 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1986
1987 /* Load the nested guest state */
1988 svm->vmcb->save.es = nested_vmcb->save.es;
1989 svm->vmcb->save.cs = nested_vmcb->save.cs;
1990 svm->vmcb->save.ss = nested_vmcb->save.ss;
1991 svm->vmcb->save.ds = nested_vmcb->save.ds;
1992 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1993 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1994 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1995 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1996 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1997 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1998 if (npt_enabled) {
1999 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2000 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2001 } else
3d6368ef 2002 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2003
2004 /* Guest paging mode is active - reset mmu */
2005 kvm_mmu_reset_context(&svm->vcpu);
2006
defbba56 2007 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2008 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2009 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2010 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2011
3d6368ef
AG		 2012 /* In case we don't even reach vcpu_run, the fields are not updated */
2013 svm->vmcb->save.rax = nested_vmcb->save.rax;
2014 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2015 svm->vmcb->save.rip = nested_vmcb->save.rip;
2016 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2017 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2018 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2019
f7138538 2020 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2021 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2022
aad42c64
JR		 2023 /* cache intercepts */
2024 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2025 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2026 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2027 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2028 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2029 svm->nested.intercept = nested_vmcb->control.intercept;
2030
3d6368ef 2031 force_new_asid(&svm->vcpu);
3d6368ef 2032 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2033 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2034 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2035 else
2036 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2037
88ab24ad
JR		 2038 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2039 /* We only want the cr8 intercept bits of the guest */
2040 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2041 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2042 }
2043
0d945bd9
JR		 2044 /* We don't want to see VMMCALLs from a nested guest */
2045 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2046
e0231715
JR		 2047 /*
2048 * We don't want a nested guest to be more powerful than the guest, so
2049 * all intercepts are ORed
2050 */
88ab24ad
JR		 2051 svm->vmcb->control.intercept_cr_read |=
2052 nested_vmcb->control.intercept_cr_read;
2053 svm->vmcb->control.intercept_cr_write |=
2054 nested_vmcb->control.intercept_cr_write;
2055 svm->vmcb->control.intercept_dr_read |=
2056 nested_vmcb->control.intercept_dr_read;
2057 svm->vmcb->control.intercept_dr_write |=
2058 nested_vmcb->control.intercept_dr_write;
2059 svm->vmcb->control.intercept_exceptions |=
2060 nested_vmcb->control.intercept_exceptions;
2061
2062 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2063
2064 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2065 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2066 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2067 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2068 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2069 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2070
7597f129 2071 nested_svm_unmap(page);
9738b2c9 2072
06fc7772
JR		 2073 /* nested_vmcb is our indicator if nested SVM is activated */
2074 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2075
2af9194d 2076 enable_gif(svm);
3d6368ef 2077
9738b2c9 2078 return true;
3d6368ef
AG		 2079}
2080
9966bf68 2081static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2082{
2083 to_vmcb->save.fs = from_vmcb->save.fs;
2084 to_vmcb->save.gs = from_vmcb->save.gs;
2085 to_vmcb->save.tr = from_vmcb->save.tr;
2086 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2087 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2088 to_vmcb->save.star = from_vmcb->save.star;
2089 to_vmcb->save.lstar = from_vmcb->save.lstar;
2090 to_vmcb->save.cstar = from_vmcb->save.cstar;
2091 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2092 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2093 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2094 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2095}
2096
851ba692 2097static int vmload_interception(struct vcpu_svm *svm)
5542675b 2098{
9966bf68 2099 struct vmcb *nested_vmcb;
7597f129 2100 struct page *page;
9966bf68 2101
5542675b
AG		 2102 if (nested_svm_check_permissions(svm))
2103 return 1;
2104
2105 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2106 skip_emulated_instruction(&svm->vcpu);
2107
7597f129 2108 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2109 if (!nested_vmcb)
2110 return 1;
2111
2112 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2113 nested_svm_unmap(page);
5542675b
AG		 2114
2115 return 1;
2116}
2117
851ba692 2118static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2119{
9966bf68 2120 struct vmcb *nested_vmcb;
7597f129 2121 struct page *page;
9966bf68 2122
5542675b
AG		 2123 if (nested_svm_check_permissions(svm))
2124 return 1;
2125
2126 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2127 skip_emulated_instruction(&svm->vcpu);
2128
7597f129 2129 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2130 if (!nested_vmcb)
2131 return 1;
2132
2133 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2134 nested_svm_unmap(page);
5542675b
AG		 2135
2136 return 1;
2137}
2138
851ba692 2139static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2140{
3d6368ef
AG		 2141 if (nested_svm_check_permissions(svm))
2142 return 1;
2143
2144 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2145 skip_emulated_instruction(&svm->vcpu);
2146
9738b2c9 2147 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2148 return 1;
2149
9738b2c9 2150 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2151 goto failed;
2152
2153 return 1;
2154
2155failed:
2156
2157 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2158 svm->vmcb->control.exit_code_hi = 0;
2159 svm->vmcb->control.exit_info_1 = 0;
2160 svm->vmcb->control.exit_info_2 = 0;
2161
2162 nested_svm_vmexit(svm);
3d6368ef
AG		 2163
2164 return 1;
2165}
2166
851ba692 2167static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2168{
2169 if (nested_svm_check_permissions(svm))
2170 return 1;
2171
2172 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2173 skip_emulated_instruction(&svm->vcpu);
2174
2af9194d 2175 enable_gif(svm);
1371d904
AG		 2176
2177 return 1;
2178}
2179
851ba692 2180static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2181{
2182 if (nested_svm_check_permissions(svm))
2183 return 1;
2184
2185 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2186 skip_emulated_instruction(&svm->vcpu);
2187
2af9194d 2188 disable_gif(svm);
1371d904
AG		 2189
2190 /* After a CLGI no interrupts should come */
2191 svm_clear_vintr(svm);
2192 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2193
2194 return 1;
2195}
2196
851ba692 2197static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2198{
2199 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2200
ec1ff790
JR		 2201 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2202 vcpu->arch.regs[VCPU_REGS_RAX]);
2203
ff092385
AG		 2204 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2205 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2206
2207 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2208 skip_emulated_instruction(&svm->vcpu);
2209 return 1;
2210}
2211
532a46b9
JR		 2212static int skinit_interception(struct vcpu_svm *svm)
2213{
2214 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2215
2216 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2217 return 1;
2218}
2219
851ba692 2220static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2221{
7ee5d940 2222 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2223 return 1;
2224}
2225
851ba692 2226static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2227{
37817f29 2228 u16 tss_selector;
64a7ec06
GN		 2229 int reason;
2230 int int_type = svm->vmcb->control.exit_int_info &
2231 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2232 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2233 uint32_t type =
2234 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2235 uint32_t idt_v =
2236 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2237 bool has_error_code = false;
2238 u32 error_code = 0;
37817f29
IE		 2239
2240 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2241
37817f29
IE		 2242 if (svm->vmcb->control.exit_info_2 &
2243 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2244 reason = TASK_SWITCH_IRET;
2245 else if (svm->vmcb->control.exit_info_2 &
2246 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2247 reason = TASK_SWITCH_JMP;
fe8e7f83 2248 else if (idt_v)
64a7ec06
GN		 2249 reason = TASK_SWITCH_GATE;
2250 else
2251 reason = TASK_SWITCH_CALL;
2252
fe8e7f83
GN		 2253 if (reason == TASK_SWITCH_GATE) {
2254 switch (type) {
2255 case SVM_EXITINTINFO_TYPE_NMI:
2256 svm->vcpu.arch.nmi_injected = false;
2257 break;
2258 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2259 if (svm->vmcb->control.exit_info_2 &
2260 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2261 has_error_code = true;
2262 error_code =
2263 (u32)svm->vmcb->control.exit_info_2;
2264 }
fe8e7f83
GN		 2265 kvm_clear_exception_queue(&svm->vcpu);
2266 break;
2267 case SVM_EXITINTINFO_TYPE_INTR:
2268 kvm_clear_interrupt_queue(&svm->vcpu);
2269 break;
2270 default:
2271 break;
2272 }
2273 }
64a7ec06 2274
8317c298
GN		 2275 if (reason != TASK_SWITCH_GATE ||
2276 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2277 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2278 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2279 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2280
acb54517
GN		 2281 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2282 has_error_code, error_code) == EMULATE_FAIL) {
2283 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2284 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2285 svm->vcpu.run->internal.ndata = 0;
2286 return 0;
2287 }
2288 return 1;
6aa8b732
AK		 2289}
2290
851ba692 2291static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2292{
5fdbf976 2293 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2294 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2295 return 1;
6aa8b732
AK		 2296}
2297
851ba692 2298static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2299{
2300 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2301 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2302 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2303 return 1;
2304}
2305
851ba692 2306static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2307{
851ba692 2308 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2309 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2310 return 1;
2311}
2312
851ba692 2313static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2314{
851ba692 2315 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2316 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2317 return 1;
2318}
2319
851ba692 2320static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2321{
851ba692
AK		 2322 struct kvm_run *kvm_run = svm->vcpu.run;
2323
0a5fff19
GN		 2324 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2325 /* instruction emulation calls kvm_set_cr8() */
851ba692 2326 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2327 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2328 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2329 return 1;
95ba8273 2330 }
0a5fff19
GN		 2331 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2332 return 1;
1d075434
JR		 2333 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2334 return 0;
2335}
2336
6aa8b732
AK		 2337static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2338{
a2fa3e9f
GH		 2339 struct vcpu_svm *svm = to_svm(vcpu);
2340
6aa8b732 2341 switch (ecx) {
af24a4e4 2342 case MSR_IA32_TSC: {
20824f30 2343 u64 tsc_offset;
6aa8b732 2344
20824f30
JR		 2345 if (is_nested(svm))
2346 tsc_offset = svm->nested.hsave->control.tsc_offset;
2347 else
2348 tsc_offset = svm->vmcb->control.tsc_offset;
2349
2350 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2351 break;
2352 }
0e859cac 2353 case MSR_K6_STAR:
a2fa3e9f 2354 *data = svm->vmcb->save.star;
6aa8b732 2355 break;
0e859cac 2356#ifdef CONFIG_X86_64
6aa8b732 2357 case MSR_LSTAR:
a2fa3e9f 2358 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2359 break;
2360 case MSR_CSTAR:
a2fa3e9f 2361 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2362 break;
2363 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2364 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2365 break;
2366 case MSR_SYSCALL_MASK:
a2fa3e9f 2367 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2368 break;
2369#endif
2370 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2371 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2372 break;
2373 case MSR_IA32_SYSENTER_EIP:
017cb99e 2374 *data = svm->sysenter_eip;
6aa8b732
AK		 2375 break;
2376 case MSR_IA32_SYSENTER_ESP:
017cb99e 2377 *data = svm->sysenter_esp;
6aa8b732 2378 break;
e0231715
JR		 2379 /*
2380 * Nobody will change the following 5 values in the VMCB so we can
2381 * safely return them on rdmsr. They will always be 0 until LBRV is
2382 * implemented.
2383 */
a2938c80
JR		 2384 case MSR_IA32_DEBUGCTLMSR:
2385 *data = svm->vmcb->save.dbgctl;
2386 break;
2387 case MSR_IA32_LASTBRANCHFROMIP:
2388 *data = svm->vmcb->save.br_from;
2389 break;
2390 case MSR_IA32_LASTBRANCHTOIP:
2391 *data = svm->vmcb->save.br_to;
2392 break;
2393 case MSR_IA32_LASTINTFROMIP:
2394 *data = svm->vmcb->save.last_excp_from;
2395 break;
2396 case MSR_IA32_LASTINTTOIP:
2397 *data = svm->vmcb->save.last_excp_to;
2398 break;
b286d5d8 2399 case MSR_VM_HSAVE_PA:
e6aa9abd 2400 *data = svm->nested.hsave_msr;
b286d5d8 2401 break;
eb6f302e 2402 case MSR_VM_CR:
4a810181 2403 *data = svm->nested.vm_cr_msr;
eb6f302e 2404 break;
c8a73f18
AG		 2405 case MSR_IA32_UCODE_REV:
2406 *data = 0x01000065;
2407 break;
6aa8b732 2408 default:
3bab1f5d 2409 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2410 }
2411 return 0;
2412}
2413
851ba692 2414static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2415{
ad312c7c 2416 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2417 u64 data;
2418
59200273
AK		 2419 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2420 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2421 kvm_inject_gp(&svm->vcpu, 0);
59200273 2422 } else {
229456fc 2423 trace_kvm_msr_read(ecx, data);
af9ca2d7 2424
5fdbf976 2425 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2426 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2427 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2428 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2429 }
2430 return 1;
2431}
2432
4a810181
JR		 2433static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2434{
2435 struct vcpu_svm *svm = to_svm(vcpu);
2436 int svm_dis, chg_mask;
2437
2438 if (data & ~SVM_VM_CR_VALID_MASK)
2439 return 1;
2440
2441 chg_mask = SVM_VM_CR_VALID_MASK;
2442
2443 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2444 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2445
2446 svm->nested.vm_cr_msr &= ~chg_mask;
2447 svm->nested.vm_cr_msr |= (data & chg_mask);
2448
2449 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2450
2451 /* check for svm_disable while efer.svme is set */
2452 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2453 return 1;
2454
2455 return 0;
2456}
2457
6aa8b732
AK		 2458static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2459{
a2fa3e9f
GH		 2460 struct vcpu_svm *svm = to_svm(vcpu);
2461
6aa8b732 2462 switch (ecx) {
af24a4e4 2463 case MSR_IA32_TSC: {
20824f30
JR		 2464 u64 tsc_offset = data - native_read_tsc();
2465 u64 g_tsc_offset = 0;
2466
2467 if (is_nested(svm)) {
2468 g_tsc_offset = svm->vmcb->control.tsc_offset -
2469 svm->nested.hsave->control.tsc_offset;
2470 svm->nested.hsave->control.tsc_offset = tsc_offset;
2471 }
2472
2473 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2474
6aa8b732
AK		 2475 break;
2476 }
0e859cac 2477 case MSR_K6_STAR:
a2fa3e9f 2478 svm->vmcb->save.star = data;
6aa8b732 2479 break;
49b14f24 2480#ifdef CONFIG_X86_64
6aa8b732 2481 case MSR_LSTAR:
a2fa3e9f 2482 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2483 break;
2484 case MSR_CSTAR:
a2fa3e9f 2485 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2486 break;
2487 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2488 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2489 break;
2490 case MSR_SYSCALL_MASK:
a2fa3e9f 2491 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2492 break;
2493#endif
2494 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2495 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2496 break;
2497 case MSR_IA32_SYSENTER_EIP:
017cb99e 2498 svm->sysenter_eip = data;
a2fa3e9f 2499 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2500 break;
2501 case MSR_IA32_SYSENTER_ESP:
017cb99e 2502 svm->sysenter_esp = data;
a2fa3e9f 2503 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2504 break;
a2938c80 2505 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2506 if (!svm_has(SVM_FEATURE_LBRV)) {
2507 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2508 __func__, data);
24e09cbf
JR		 2509 break;
2510 }
2511 if (data & DEBUGCTL_RESERVED_BITS)
2512 return 1;
2513
2514 svm->vmcb->save.dbgctl = data;
2515 if (data & (1ULL<<0))
2516 svm_enable_lbrv(svm);
2517 else
2518 svm_disable_lbrv(svm);
a2938c80 2519 break;
b286d5d8 2520 case MSR_VM_HSAVE_PA:
e6aa9abd 2521 svm->nested.hsave_msr = data;
62b9abaa 2522 break;
3c5d0a44 2523 case MSR_VM_CR:
4a810181 2524 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2525 case MSR_VM_IGNNE:
3c5d0a44
AG		 2526 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2527 break;
6aa8b732 2528 default:
3bab1f5d 2529 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2530 }
2531 return 0;
2532}
2533
851ba692 2534static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2535{
ad312c7c 2536 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2537 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2538 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2539
af9ca2d7 2540
5fdbf976 2541 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2542 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2543 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2544 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2545 } else {
2546 trace_kvm_msr_write(ecx, data);
e756fc62 2547 skip_emulated_instruction(&svm->vcpu);
59200273 2548 }
6aa8b732
AK		 2549 return 1;
2550}
2551
851ba692 2552static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2553{
e756fc62 2554 if (svm->vmcb->control.exit_info_1)
851ba692 2555 return wrmsr_interception(svm);
6aa8b732 2556 else
851ba692 2557 return rdmsr_interception(svm);
6aa8b732
AK		 2558}
2559
851ba692 2560static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2561{
851ba692
AK		 2562 struct kvm_run *kvm_run = svm->vcpu.run;
2563
f0b85051 2564 svm_clear_vintr(svm);
85f455f7 2565 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2566 /*
2567 * If the user space waits to inject interrupts, exit as soon as
2568 * possible
2569 */
8061823a
GN		 2570 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2571 kvm_run->request_interrupt_window &&
2572 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2573 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2574 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2575 return 0;
2576 }
2577
2578 return 1;
2579}
2580
565d0998
ML		 2581static int pause_interception(struct vcpu_svm *svm)
2582{
2583 kvm_vcpu_on_spin(&(svm->vcpu));
2584 return 1;
2585}
2586
851ba692 2587static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2588 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2589 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2590 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2591 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2592 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2593 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2594 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2595 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2596 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2597 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2598 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2599 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2600 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2601 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2602 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2603 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2604 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2605 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2606 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2607 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2608 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2609 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2610 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2611 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2612 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2613 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2614 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2615 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2616 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2617 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2618 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2619 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2620 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2621 [SVM_EXIT_SMI] = nop_on_interception,
2622 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2623 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2624 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2625 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2626 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2627 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2628 [SVM_EXIT_HLT] = halt_interception,
a7052897 2629 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2630 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2631 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2632 [SVM_EXIT_MSR] = msr_interception,
2633 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2634 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2635 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2636 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2637 [SVM_EXIT_VMLOAD] = vmload_interception,
2638 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2639 [SVM_EXIT_STGI] = stgi_interception,
2640 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2641 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2642 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2643 [SVM_EXIT_MONITOR] = invalid_op_interception,
2644 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2645 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2646};
2647
851ba692 2648static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2649{
04d2cc77 2650 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2651 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2652 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2653
5bfd8b54 2654 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2655
2be4fc7a
JR		 2656 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2657 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2658 if (npt_enabled)
2659 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2660
cd3ff653
JR		 2661 if (unlikely(svm->nested.exit_required)) {
2662 nested_svm_vmexit(svm);
2663 svm->nested.exit_required = false;
2664
2665 return 1;
2666 }
2667
cf74a78b 2668 if (is_nested(svm)) {
410e4d57
JR		 2669 int vmexit;
2670
d8cabddf
JR		 2671 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2672 svm->vmcb->control.exit_info_1,
2673 svm->vmcb->control.exit_info_2,
2674 svm->vmcb->control.exit_int_info,
2675 svm->vmcb->control.exit_int_info_err);
2676
410e4d57
JR		 2677 vmexit = nested_svm_exit_special(svm);
2678
2679 if (vmexit == NESTED_EXIT_CONTINUE)
2680 vmexit = nested_svm_exit_handled(svm);
2681
2682 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2683 return 1;
cf74a78b
AG		 2684 }
2685
a5c3832d
JR		 2686 svm_complete_interrupts(svm);
2687
04d2cc77
AK		 2688 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2689 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2690 kvm_run->fail_entry.hardware_entry_failure_reason
2691 = svm->vmcb->control.exit_code;
2692 return 0;
2693 }
2694
a2fa3e9f 2695 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2696 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2697 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2698 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2699 "exit_code 0x%x\n",
b8688d51 2700 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2701 exit_code);
2702
9d8f549d 2703 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2704 || !svm_exit_handlers[exit_code]) {
6aa8b732 2705 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2706 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2707 return 0;
2708 }
2709
851ba692 2710 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2711}
2712
2713static void reload_tss(struct kvm_vcpu *vcpu)
2714{
2715 int cpu = raw_smp_processor_id();
2716
0fe1e009
TH		 2717 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2718 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2719 load_TR_desc();
2720}
2721
e756fc62 2722static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2723{
2724 int cpu = raw_smp_processor_id();
2725
0fe1e009 2726 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2727
a2fa3e9f 2728 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2729 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2730 if (svm->asid_generation != sd->asid_generation)
2731 new_asid(svm, sd);
6aa8b732
AK		 2732}
2733
95ba8273
GN		 2734static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2735{
2736 struct vcpu_svm *svm = to_svm(vcpu);
2737
2738 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2739 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2740 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2741 ++vcpu->stat.nmi_injections;
2742}
6aa8b732 2743
85f455f7 2744static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2745{
2746 struct vmcb_control_area *control;
2747
229456fc 2748 trace_kvm_inj_virq(irq);
af9ca2d7 2749
fa89a817 2750 ++svm->vcpu.stat.irq_injections;
e756fc62 2751 control = &svm->vmcb->control;
85f455f7 2752 control->int_vector = irq;
6aa8b732
AK		 2753 control->int_ctl &= ~V_INTR_PRIO_MASK;
2754 control->int_ctl |= V_IRQ_MASK |
2755 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2756}
2757
66fd3f7f 2758static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2759{
2760 struct vcpu_svm *svm = to_svm(vcpu);
2761
2af9194d 2762 BUG_ON(!(gif_set(svm)));
cf74a78b 2763
219b65dc
AG		 2764 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2765 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2766}
2767
95ba8273 2768static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2769{
2770 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2771
88ab24ad
JR		 2772 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2773 return;
2774
95ba8273 2775 if (irr == -1)
aaacfc9a
JR		 2776 return;
2777
95ba8273
GN		 2778 if (tpr >= irr)
2779 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2780}
aaacfc9a 2781
95ba8273
GN		 2782static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2783{
2784 struct vcpu_svm *svm = to_svm(vcpu);
2785 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2786 int ret;
2787 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2788 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2789 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2790
2791 return ret;
aaacfc9a
JR		 2792}
2793
3cfc3092
JK		 2794static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2795{
2796 struct vcpu_svm *svm = to_svm(vcpu);
2797
2798 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2799}
2800
2801static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2802{
2803 struct vcpu_svm *svm = to_svm(vcpu);
2804
2805 if (masked) {
2806 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 2807 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2808 } else {
2809 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 2810 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 2811 }
2812}
2813
78646121
GN		 2814static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2815{
2816 struct vcpu_svm *svm = to_svm(vcpu);
2817 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2818 int ret;
2819
2820 if (!gif_set(svm) ||
2821 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2822 return 0;
2823
2824 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2825
2826 if (is_nested(svm))
2827 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2828
2829 return ret;
78646121
GN		 2830}
2831
9222be18 2832static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2833{
219b65dc 2834 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2835
e0231715
JR		 2836 /*
2837 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2838 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2839 * get that intercept, this function will be called again though and
2840 * we'll get the vintr intercept.
2841 */
8fe54654 2842 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2843 svm_set_vintr(svm);
2844 svm_inject_irq(svm, 0x0);
2845 }
85f455f7
ED		 2846}
2847
95ba8273 2848static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2849{
04d2cc77 2850 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2851
44c11430
GN		 2852 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2853 == HF_NMI_MASK)
2854 return; /* IRET will cause a vm exit */
2855
e0231715
JR		 2856 /*
2857 * Something prevents NMI from been injected. Single step over possible
2858 * problem (IRET or exception injection or interrupt shadow)
2859 */
6be7d306 2860 svm->nmi_singlestep = true;
44c11430
GN		 2861 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2862 update_db_intercept(vcpu);
c1150d8c
DL		 2863}
2864
cbc94022
IE		 2865static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2866{
2867 return 0;
2868}
2869
d9e368d6
AK		 2870static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2871{
2872 force_new_asid(vcpu);
2873}
2874
04d2cc77
AK		 2875static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2876{
2877}
2878
d7bf8221
JR		 2879static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2880{
2881 struct vcpu_svm *svm = to_svm(vcpu);
2882
88ab24ad
JR		 2883 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2884 return;
2885
d7bf8221
JR		 2886 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2887 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2888 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2889 }
2890}
2891
649d6864
JR		 2892static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2893{
2894 struct vcpu_svm *svm = to_svm(vcpu);
2895 u64 cr8;
2896
88ab24ad
JR		 2897 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2898 return;
2899
649d6864
JR		 2900 cr8 = kvm_get_cr8(vcpu);
2901 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2902 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2903}
2904
9222be18
GN		 2905static void svm_complete_interrupts(struct vcpu_svm *svm)
2906{
2907 u8 vector;
2908 int type;
2909 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2910 unsigned int3_injected = svm->int3_injected;
2911
2912 svm->int3_injected = 0;
9222be18 2913
44c11430
GN		 2914 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2915 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2916
9222be18
GN		 2917 svm->vcpu.arch.nmi_injected = false;
2918 kvm_clear_exception_queue(&svm->vcpu);
2919 kvm_clear_interrupt_queue(&svm->vcpu);
2920
2921 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2922 return;
2923
2924 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2925 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2926
2927 switch (type) {
2928 case SVM_EXITINTINFO_TYPE_NMI:
2929 svm->vcpu.arch.nmi_injected = true;
2930 break;
2931 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 2932 /*
2933 * In case of software exceptions, do not reinject the vector,
2934 * but re-execute the instruction instead. Rewind RIP first
2935 * if we emulated INT3 before.
2936 */
2937 if (kvm_exception_is_soft(vector)) {
2938 if (vector == BP_VECTOR && int3_injected &&
2939 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2940 kvm_rip_write(&svm->vcpu,
2941 kvm_rip_read(&svm->vcpu) -
2942 int3_injected);
9222be18 2943 break;
66b7138f 2944 }
9222be18
GN		 2945 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2946 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 2947 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 2948
2949 } else
ce7ddec4 2950 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 2951 break;
2952 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2953 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2954 break;
2955 default:
2956 break;
2957 }
2958}
2959
80e31d4f
AK		 2960#ifdef CONFIG_X86_64
2961#define R "r"
2962#else
2963#define R "e"
2964#endif
2965
851ba692 2966static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2967{
a2fa3e9f 2968 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2969 u16 fs_selector;
2970 u16 gs_selector;
2971 u16 ldt_selector;
d9e368d6 2972
2041a06a
JR		 2973 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2974 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2975 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2976
cd3ff653
JR		 2977 /*
2978 * A vmexit emulation is required before the vcpu can be executed
2979 * again.
2980 */
2981 if (unlikely(svm->nested.exit_required))
2982 return;
2983
e756fc62 2984 pre_svm_run(svm);
6aa8b732 2985
649d6864
JR		 2986 sync_lapic_to_cr8(vcpu);
2987
6aa8b732 2988 save_host_msrs(vcpu);
d6e88aec
AK		 2989 fs_selector = kvm_read_fs();
2990 gs_selector = kvm_read_gs();
2991 ldt_selector = kvm_read_ldt();
cda0ffdd 2992 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2993 /* required for live migration with NPT */
2994 if (npt_enabled)
2995 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2996
04d2cc77
AK		 2997 clgi();
2998
2999 local_irq_enable();
36241b8c 3000
6aa8b732 3001 asm volatile (
80e31d4f
AK		 3002 "push %%"R"bp; \n\t"
3003 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3004 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3005 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3006 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3007 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3008 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3009#ifdef CONFIG_X86_64
fb3f0f51
RR		 3010 "mov %c[r8](%[svm]), %%r8 \n\t"
3011 "mov %c[r9](%[svm]), %%r9 \n\t"
3012 "mov %c[r10](%[svm]), %%r10 \n\t"
3013 "mov %c[r11](%[svm]), %%r11 \n\t"
3014 "mov %c[r12](%[svm]), %%r12 \n\t"
3015 "mov %c[r13](%[svm]), %%r13 \n\t"
3016 "mov %c[r14](%[svm]), %%r14 \n\t"
3017 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3018#endif
3019
6aa8b732 3020 /* Enter guest mode */
80e31d4f
AK		 3021 "push %%"R"ax \n\t"
3022 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3023 __ex(SVM_VMLOAD) "\n\t"
3024 __ex(SVM_VMRUN) "\n\t"
3025 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3026 "pop %%"R"ax \n\t"
6aa8b732
AK		 3027
3028 /* Save guest registers, load host registers */
80e31d4f
AK		 3029 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3030 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3031 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3032 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3033 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3034 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3035#ifdef CONFIG_X86_64
fb3f0f51
RR		 3036 "mov %%r8, %c[r8](%[svm]) \n\t"
3037 "mov %%r9, %c[r9](%[svm]) \n\t"
3038 "mov %%r10, %c[r10](%[svm]) \n\t"
3039 "mov %%r11, %c[r11](%[svm]) \n\t"
3040 "mov %%r12, %c[r12](%[svm]) \n\t"
3041 "mov %%r13, %c[r13](%[svm]) \n\t"
3042 "mov %%r14, %c[r14](%[svm]) \n\t"
3043 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3044#endif
80e31d4f 3045 "pop %%"R"bp"
6aa8b732 3046 :
fb3f0f51 3047 : [svm]"a"(svm),
6aa8b732 3048 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3049 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3050 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3051 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3052 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3053 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3054 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3055#ifdef CONFIG_X86_64
ad312c7c
ZX		 3056 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3057 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3058 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3059 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3060 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3061 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3062 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3063 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3064#endif
54a08c04 3065 : "cc", "memory"
80e31d4f 3066 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3067#ifdef CONFIG_X86_64
54a08c04
LV		 3068 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3069#endif
3070 );
6aa8b732 3071
ad312c7c 3072 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3073 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3074 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3075 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3076
d6e88aec
AK		 3077 kvm_load_fs(fs_selector);
3078 kvm_load_gs(gs_selector);
3079 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3080 load_host_msrs(vcpu);
3081
3082 reload_tss(vcpu);
3083
56ba47dd
AK		 3084 local_irq_disable();
3085
3086 stgi();
3087
d7bf8221
JR		 3088 sync_cr8_to_lapic(vcpu);
3089
a2fa3e9f 3090 svm->next_rip = 0;
9222be18 3091
6de4f3ad
AK		 3092 if (npt_enabled) {
3093 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3094 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3095 }
fe5913e4
JR		 3096
3097 /*
3098 * We need to handle MC intercepts here before the vcpu has a chance to
3099 * change the physical cpu
3100 */
3101 if (unlikely(svm->vmcb->control.exit_code ==
3102 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3103 svm_handle_mce(svm);
6aa8b732
AK		 3104}
3105
80e31d4f
AK		 3106#undef R
3107
6aa8b732
AK		 3108static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3109{
a2fa3e9f
GH		 3110 struct vcpu_svm *svm = to_svm(vcpu);
3111
709ddebf
JR		 3112 if (npt_enabled) {
3113 svm->vmcb->control.nested_cr3 = root;
3114 force_new_asid(vcpu);
3115 return;
3116 }
3117
a2fa3e9f 3118 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3119 force_new_asid(vcpu);
3120}
3121
6aa8b732
AK		 3122static int is_disabled(void)
3123{
6031a61c
JR		 3124 u64 vm_cr;
3125
3126 rdmsrl(MSR_VM_CR, vm_cr);
3127 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3128 return 1;
3129
6aa8b732
AK		 3130 return 0;
3131}
3132
102d8325
IM		 3133static void
3134svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3135{
3136 /*
3137 * Patch in the VMMCALL instruction:
3138 */
3139 hypercall[0] = 0x0f;
3140 hypercall[1] = 0x01;
3141 hypercall[2] = 0xd9;
102d8325
IM		 3142}
3143
002c7f7c
YS		 3144static void svm_check_processor_compat(void *rtn)
3145{
3146 *(int *)rtn = 0;
3147}
3148
774ead3a
AK		 3149static bool svm_cpu_has_accelerated_tpr(void)
3150{
3151 return false;
3152}
3153
67253af5
SY		 3154static int get_npt_level(void)
3155{
3156#ifdef CONFIG_X86_64
3157 return PT64_ROOT_LEVEL;
3158#else
3159 return PT32E_ROOT_LEVEL;
3160#endif
3161}
3162
4b12f0de 3163static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3164{
3165 return 0;
3166}
3167
0e851880
SY		 3168static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3169{
3170}
3171
d4330ef2
JR		 3172static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3173{
c2c63a49
JR		 3174 switch (func) {
3175 case 0x8000000A:
3176 entry->eax = 1; /* SVM revision 1 */
3177 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3178 ASID emulation to nested SVM */
3179 entry->ecx = 0; /* Reserved */
3180 entry->edx = 0; /* Do not support any additional features */
3181
3182 break;
3183 }
d4330ef2
JR		 3184}
3185
229456fc 3186static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3187 { SVM_EXIT_READ_CR0, "read_cr0" },
3188 { SVM_EXIT_READ_CR3, "read_cr3" },
3189 { SVM_EXIT_READ_CR4, "read_cr4" },
3190 { SVM_EXIT_READ_CR8, "read_cr8" },
3191 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3192 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3193 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3194 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3195 { SVM_EXIT_READ_DR0, "read_dr0" },
3196 { SVM_EXIT_READ_DR1, "read_dr1" },
3197 { SVM_EXIT_READ_DR2, "read_dr2" },
3198 { SVM_EXIT_READ_DR3, "read_dr3" },
3199 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3200 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3201 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3202 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3203 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3204 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3205 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3206 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3207 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3208 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3209 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3210 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3211 { SVM_EXIT_INTR, "interrupt" },
3212 { SVM_EXIT_NMI, "nmi" },
3213 { SVM_EXIT_SMI, "smi" },
3214 { SVM_EXIT_INIT, "init" },
3215 { SVM_EXIT_VINTR, "vintr" },
3216 { SVM_EXIT_CPUID, "cpuid" },
3217 { SVM_EXIT_INVD, "invd" },
3218 { SVM_EXIT_HLT, "hlt" },
3219 { SVM_EXIT_INVLPG, "invlpg" },
3220 { SVM_EXIT_INVLPGA, "invlpga" },
3221 { SVM_EXIT_IOIO, "io" },
3222 { SVM_EXIT_MSR, "msr" },
3223 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3224 { SVM_EXIT_SHUTDOWN, "shutdown" },
3225 { SVM_EXIT_VMRUN, "vmrun" },
3226 { SVM_EXIT_VMMCALL, "hypercall" },
3227 { SVM_EXIT_VMLOAD, "vmload" },
3228 { SVM_EXIT_VMSAVE, "vmsave" },
3229 { SVM_EXIT_STGI, "stgi" },
3230 { SVM_EXIT_CLGI, "clgi" },
3231 { SVM_EXIT_SKINIT, "skinit" },
3232 { SVM_EXIT_WBINVD, "wbinvd" },
3233 { SVM_EXIT_MONITOR, "monitor" },
3234 { SVM_EXIT_MWAIT, "mwait" },
3235 { SVM_EXIT_NPF, "npf" },
3236 { -1, NULL }
3237};
3238
17cc3935 3239static int svm_get_lpage_level(void)
344f414f 3240{
17cc3935 3241 return PT_PDPE_LEVEL;
344f414f
JR		 3242}
3243
4e47c7a6
SY		 3244static bool svm_rdtscp_supported(void)
3245{
3246 return false;
3247}
3248
02daab21
AK		 3249static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3250{
3251 struct vcpu_svm *svm = to_svm(vcpu);
3252
02daab21 3253 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3254 if (is_nested(svm))
3255 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3256 update_cr0_intercept(svm);
02daab21
AK		 3257}
3258
cbdd1bea 3259static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3260 .cpu_has_kvm_support = has_svm,
3261 .disabled_by_bios = is_disabled,
3262 .hardware_setup = svm_hardware_setup,
3263 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3264 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3265 .hardware_enable = svm_hardware_enable,
3266 .hardware_disable = svm_hardware_disable,
774ead3a 3267 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3268
3269 .vcpu_create = svm_create_vcpu,
3270 .vcpu_free = svm_free_vcpu,
04d2cc77 3271 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3272
04d2cc77 3273 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3274 .vcpu_load = svm_vcpu_load,
3275 .vcpu_put = svm_vcpu_put,
3276
3277 .set_guest_debug = svm_guest_debug,
3278 .get_msr = svm_get_msr,
3279 .set_msr = svm_set_msr,
3280 .get_segment_base = svm_get_segment_base,
3281 .get_segment = svm_get_segment,
3282 .set_segment = svm_set_segment,
2e4d2653 3283 .get_cpl = svm_get_cpl,
1747fb71 3284 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3285 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3286 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3287 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3288 .set_cr3 = svm_set_cr3,
3289 .set_cr4 = svm_set_cr4,
3290 .set_efer = svm_set_efer,
3291 .get_idt = svm_get_idt,
3292 .set_idt = svm_set_idt,
3293 .get_gdt = svm_get_gdt,
3294 .set_gdt = svm_set_gdt,
020df079 3295 .set_dr7 = svm_set_dr7,
6de4f3ad 3296 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3297 .get_rflags = svm_get_rflags,
3298 .set_rflags = svm_set_rflags,
6b52d186 3299 .fpu_activate = svm_fpu_activate,
02daab21 3300 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3301
6aa8b732 3302 .tlb_flush = svm_flush_tlb,
6aa8b732 3303
6aa8b732 3304 .run = svm_vcpu_run,
04d2cc77 3305 .handle_exit = handle_exit,
6aa8b732 3306 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3307 .set_interrupt_shadow = svm_set_interrupt_shadow,
3308 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3309 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3310 .set_irq = svm_set_irq,
95ba8273 3311 .set_nmi = svm_inject_nmi,
298101da 3312 .queue_exception = svm_queue_exception,
78646121 3313 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3314 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3315 .get_nmi_mask = svm_get_nmi_mask,
3316 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3317 .enable_nmi_window = enable_nmi_window,
3318 .enable_irq_window = enable_irq_window,
3319 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3320
3321 .set_tss_addr = svm_set_tss_addr,
67253af5 3322 .get_tdp_level = get_npt_level,
4b12f0de 3323 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3324
3325 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3326 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3327
3328 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3329
3330 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3331
3332 .set_supported_cpuid = svm_set_supported_cpuid,
6aa8b732
AK		 3333};
3334
3335static int __init svm_init(void)
3336{
cb498ea2 3337 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3338 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3339}
3340
3341static void __exit svm_exit(void)
3342{
cb498ea2 3343 kvm_exit();
6aa8b732
AK		 3344}
3345
3346module_init(svm_init)
3347module_exit(svm_exit)
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