#include <linux/version.h>
#define DRV_NAME "jme"
-#define DRV_VERSION "0.6"
+#define DRV_VERSION "0.9"
#define PFX DRV_NAME ": "
#ifdef DEBUG
#define rx_dbg(args...)
#endif
+#ifdef QUEUE_DEBUG
+#define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
+#else
+#define queue_dbg(args...)
+#endif
+
#ifdef CSUM_DEBUG
#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
#else
#define csum_dbg(args...)
#endif
+#ifdef VLAN_DEBUG
+#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
+#else
+#define vlan_dbg(args...)
+#endif
+
#define jprintk(devname, fmt, args...) \
printk(KERN_INFO "%s: " fmt, devname, ## args)
#define PCC_P3_THRESHOLD 3*1024*1024
#define PCC_P2_THRESHOLD 800
#define PCC_INTR_THRESHOLD 800
-#define PCC_TX_TO 100
-#define PCC_TX_CNT 16
+#define PCC_TX_TO 333
+#define PCC_TX_CNT 8
/*
* TX/RX Descriptors
* TX/RX Ring DESC Count Must be multiple of 16
* RX Ring DESC Count Must be <= 1024
*/
-#define RING_DESC_NR 512 /* Must be power of 2 */
#define RING_DESC_ALIGN 16 /* Descriptor alignment */
#define TX_DESC_SIZE 16
#define TX_RING_NR 8
-#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
-#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE)
+#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
struct txdesc {
union {
TXFLAG_LSEN = 0x02,
TXFLAG_TAGON = 0x01,
};
+#define TXDESC_MSS_SHIFT 2
enum jme_rxdescwb_flags_bits {
TXWBFLAG_OWN = 0x80,
TXWBFLAG_INT = 0x40,
#define RX_DESC_SIZE 16
#define RX_RING_NR 4
-#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
-#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE)
+#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
#define RX_BUF_DMA_ALIGN 8
#define RX_PREPAD_SIZE 10
int nr_desc;
};
+#define MAX_RING_DESC_NR 1024
struct jme_ring {
void* alloc; /* pointer to allocated memory */
volatile void* desc; /* pointer to ring memory */
dma_addr_t dma; /* phys address for ring dma */
/* Buffer information corresponding to each descriptor */
- struct jme_buffer_info bufinf[RING_DESC_NR];
+ struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
- u16 next_to_use;
- u16 next_to_clean;
+ int next_to_use;
+ int next_to_clean;
atomic_t nr_free;
};
__u32 reg_rxcs;
__u32 reg_rxmcs;
__u32 reg_ghc;
+ __u32 reg_pmcs;
__u32 phylink;
+ __u32 tx_ring_size;
+ __u32 tx_ring_mask;
+ __u32 tx_wake_threshold;
+ __u32 rx_ring_size;
+ __u32 rx_ring_mask;
__u8 mrrs;
- unsigned int oldmtu;
+ struct ethtool_cmd old_ecmd;
+ unsigned int old_mtu;
+ struct vlan_group* vlgrp;
struct dynpcc_info dpi;
atomic_t intr_sem;
atomic_t link_changing;
};
enum jme_flags_bits {
JME_FLAG_MSI = 0x00000001,
+ JME_FLAG_SSET = 0x00000002,
+ JME_FLAG_TXCSUM = 0x00000004,
+ JME_FLAG_TSO = 0x00000008,
};
#define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
#define TX_TIMEOUT (5*HZ)
TXCS_DEFAULT = TXCS_FIFOTH_4QW |
TXCS_BURST,
};
-#define JME_TX_DISABLE_TIMEOUT 5 /* 5 msec */
+#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
/*
* TX MAC Control/Status Bits
RXCS_RETRYGAP_256ns |
RXCS_RETRYCNT_32,
};
-#define JME_RX_DISABLE_TIMEOUT 5 /* 5 msec */
+#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
/*
* RX MAC Control/Status Bits
RXMCS_VTAGRM = 0x00000004,
RXMCS_PREPAD = 0x00000002,
RXMCS_CHECKSUM = 0x00000001,
-
+
RXMCS_DEFAULT = RXMCS_VTAGRM |
RXMCS_PREPAD |
RXMCS_FLOWCTRL |
RXMCS_CHECKSUM,
};
+/*
+ * Wakeup Frame setup interface registers
+ */
+#define WAKEUP_FRAME_NR 8
+#define WAKEUP_FRAME_MASK_DWNR 4
+enum jme_wfoi_bit_masks {
+ WFOI_MASK_SEL = 0x00000070,
+ WFOI_CRC_SEL = 0x00000008,
+ WFOI_FRAME_SEL = 0x00000007,
+};
+enum jme_wfoi_shifts {
+ WFOI_MASK_SHIFT = 4,
+};
+
/*
* SMI Related definitions
*/
GHC_SPEED_1000M = 0x00000030,
};
+/*
+ * Power management control and status register
+ */
+enum jme_pmcs_bit_masks {
+ PMCS_WF7DET = 0x80000000,
+ PMCS_WF6DET = 0x40000000,
+ PMCS_WF5DET = 0x20000000,
+ PMCS_WF4DET = 0x10000000,
+ PMCS_WF3DET = 0x08000000,
+ PMCS_WF2DET = 0x04000000,
+ PMCS_WF1DET = 0x02000000,
+ PMCS_WF0DET = 0x01000000,
+ PMCS_LFDET = 0x00040000,
+ PMCS_LRDET = 0x00020000,
+ PMCS_MFDET = 0x00010000,
+ PMCS_WF7EN = 0x00008000,
+ PMCS_WF6EN = 0x00004000,
+ PMCS_WF5EN = 0x00002000,
+ PMCS_WF4EN = 0x00001000,
+ PMCS_WF3EN = 0x00000800,
+ PMCS_WF2EN = 0x00000400,
+ PMCS_WF1EN = 0x00000200,
+ PMCS_WF0EN = 0x00000100,
+ PMCS_LFEN = 0x00000004,
+ PMCS_LREN = 0x00000002,
+ PMCS_MFEN = 0x00000001,
+};
+
/*
* Giga PHY Status Registers
*/