2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/version.h>
26 #define DRV_NAME "jme"
27 #define DRV_VERSION "0.9"
28 #define PFX DRV_NAME ": "
31 #define dprintk(devname, fmt, args...) \
32 printk(KERN_DEBUG "%s: " fmt, devname, ## args)
34 #define dprintk(devname, fmt, args...)
38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
40 #define tx_dbg(args...)
44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
46 #define rx_dbg(args...)
50 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
52 #define queue_dbg(args...)
56 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
58 #define csum_dbg(args...)
62 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
64 #define vlan_dbg(args...)
67 #define jprintk(devname, fmt, args...) \
68 printk(KERN_INFO "%s: " fmt, devname, ## args)
70 #define jeprintk(devname, fmt, args...) \
71 printk(KERN_ERR "%s: " fmt, devname, ## args)
73 #define DEFAULT_MSG_ENABLE \
81 #define PCI_CONF_DCSR_MRRS 0x59
82 #define PCI_CONF_DCSR_MRRS_MASK 0x70
83 enum pci_conf_dcsr_mrrs_vals {
92 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
93 #define MIN_ETHERNET_PACKET_SIZE 60
95 enum dynamic_pcc_values {
109 unsigned long last_bytes;
110 unsigned long last_pkts;
111 unsigned long intr_cnt;
113 unsigned char attempt;
116 #define PCC_INTERVAL_US 100000
117 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
118 #define PCC_P3_THRESHOLD 3*1024*1024
119 #define PCC_P2_THRESHOLD 800
120 #define PCC_INTR_THRESHOLD 800
121 #define PCC_TX_TO 333
127 * TX/RX Ring DESC Count Must be multiple of 16
128 * RX Ring DESC Count Must be <= 1024
130 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
132 #define TX_DESC_SIZE 16
134 #define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
193 enum jme_txdesc_flags_bits {
203 #define TXDESC_MSS_SHIFT 2
204 enum jme_rxdescwb_flags_bits {
207 TXWBFLAG_TMOUT = 0x20,
208 TXWBFLAG_TRYOUT = 0x10,
211 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
217 #define RX_DESC_SIZE 16
219 #define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
221 #define RX_BUF_DMA_ALIGN 8
222 #define RX_PREPAD_SIZE 10
223 #define ETH_CRC_LEN 2
224 #define RX_VLANHDR_LEN 2
225 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
271 enum jme_rxdesc_flags_bits {
276 enum jme_rxwbdesc_flags_bits {
277 RXWBFLAG_OWN = 0x8000,
278 RXWBFLAG_INT = 0x4000,
279 RXWBFLAG_MF = 0x2000,
280 RXWBFLAG_64BIT = 0x2000,
281 RXWBFLAG_TCPON = 0x1000,
282 RXWBFLAG_UDPON = 0x0800,
283 RXWBFLAG_IPCS = 0x0400,
284 RXWBFLAG_TCPCS = 0x0200,
285 RXWBFLAG_UDPCS = 0x0100,
286 RXWBFLAG_TAGON = 0x0080,
287 RXWBFLAG_IPV4 = 0x0040,
288 RXWBFLAG_IPV6 = 0x0020,
289 RXWBFLAG_PAUSE = 0x0010,
290 RXWBFLAG_MAGIC = 0x0008,
291 RXWBFLAG_WAKEUP = 0x0004,
292 RXWBFLAG_DEST = 0x0003,
293 RXWBFLAG_DEST_UNI = 0x0001,
294 RXWBFLAG_DEST_MUL = 0x0002,
295 RXWBFLAG_DEST_BRO = 0x0003,
297 enum jme_rxwbdesc_desccnt_mask {
298 RXWBDCNT_WBCPL = 0x80,
299 RXWBDCNT_DCNT = 0x7F,
301 enum jme_rxwbdesc_errstat_bits {
302 RXWBERR_LIMIT = 0x80,
303 RXWBERR_MIIER = 0x40,
304 RXWBERR_NIBON = 0x20,
305 RXWBERR_COLON = 0x10,
306 RXWBERR_ABORT = 0x08,
307 RXWBERR_SHORT = 0x04,
308 RXWBERR_OVERUN = 0x02,
309 RXWBERR_CRCERR = 0x01,
310 RXWBERR_ALLERR = 0xFF,
313 struct jme_buffer_info {
320 #define MAX_RING_DESC_NR 1024
322 void* alloc; /* pointer to allocated memory */
323 volatile void* desc; /* pointer to ring memory */
324 dma_addr_t dmaalloc; /* phys address of ring alloc */
325 dma_addr_t dma; /* phys address for ring dma */
327 /* Buffer information corresponding to each descriptor */
328 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
336 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
337 #define NET_STAT(priv) priv->stats
338 #define NETDEV_GET_STATS(netdev, fun_ptr) \
339 netdev->get_stats = fun_ptr
340 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
342 #define NET_STAT(priv) priv->dev->stats
343 #define NETDEV_GET_STATS(netdev, fun_ptr)
344 #define DECLARE_NET_DEVICE_STATS
348 * Jmac Adapter Private data
350 #define SHADOW_REG_NR 8
352 struct pci_dev *pdev;
353 struct net_device *dev;
355 dma_addr_t shadow_dma;
357 struct mii_if_info mii_if;
358 struct jme_ring rxring[RX_RING_NR];
359 struct jme_ring txring[TX_RING_NR];
361 spinlock_t macaddr_lock;
362 spinlock_t rxmcs_lock;
363 struct tasklet_struct rxempty_task;
364 struct tasklet_struct rxclean_task;
365 struct tasklet_struct txclean_task;
366 struct tasklet_struct linkch_task;
367 struct tasklet_struct pcc_task;
378 __u32 tx_wake_threshold;
382 struct ethtool_cmd old_ecmd;
383 unsigned int old_mtu;
384 struct vlan_group* vlgrp;
385 struct dynpcc_info dpi;
387 atomic_t link_changing;
388 atomic_t tx_cleaning;
389 atomic_t rx_cleaning;
390 DECLARE_NET_DEVICE_STATS
392 enum shadow_reg_val {
395 enum jme_flags_bits {
396 JME_FLAG_MSI = 0x00000001,
397 JME_FLAG_SSET = 0x00000002,
398 JME_FLAG_TXCSUM = 0x00000004,
399 JME_FLAG_TSO = 0x00000008,
401 #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
402 #define TX_TIMEOUT (5*HZ)
408 enum jme_iomap_offsets {
415 enum jme_iomap_lens {
422 enum jme_iomap_regs {
423 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
424 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
425 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
426 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
427 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
428 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
429 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
430 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
432 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
433 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
434 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
435 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
436 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
437 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
438 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
439 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
440 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
441 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
442 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
443 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
445 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
446 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
447 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
450 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
451 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
452 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
455 JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */
456 JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */
457 JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */
458 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
459 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
460 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
461 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
462 JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
463 JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */
464 JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */
465 JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */
466 JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */
470 * TX Control/Status Bits
473 TXCS_QUEUE7S = 0x00008000,
474 TXCS_QUEUE6S = 0x00004000,
475 TXCS_QUEUE5S = 0x00002000,
476 TXCS_QUEUE4S = 0x00001000,
477 TXCS_QUEUE3S = 0x00000800,
478 TXCS_QUEUE2S = 0x00000400,
479 TXCS_QUEUE1S = 0x00000200,
480 TXCS_QUEUE0S = 0x00000100,
481 TXCS_FIFOTH = 0x000000C0,
482 TXCS_DMASIZE = 0x00000030,
483 TXCS_BURST = 0x00000004,
484 TXCS_ENABLE = 0x00000001,
486 enum jme_txcs_value {
487 TXCS_FIFOTH_16QW = 0x000000C0,
488 TXCS_FIFOTH_12QW = 0x00000080,
489 TXCS_FIFOTH_8QW = 0x00000040,
490 TXCS_FIFOTH_4QW = 0x00000000,
492 TXCS_DMASIZE_64B = 0x00000000,
493 TXCS_DMASIZE_128B = 0x00000010,
494 TXCS_DMASIZE_256B = 0x00000020,
495 TXCS_DMASIZE_512B = 0x00000030,
497 TXCS_SELECT_QUEUE0 = 0x00000000,
498 TXCS_SELECT_QUEUE1 = 0x00010000,
499 TXCS_SELECT_QUEUE2 = 0x00020000,
500 TXCS_SELECT_QUEUE3 = 0x00030000,
501 TXCS_SELECT_QUEUE4 = 0x00040000,
502 TXCS_SELECT_QUEUE5 = 0x00050000,
503 TXCS_SELECT_QUEUE6 = 0x00060000,
504 TXCS_SELECT_QUEUE7 = 0x00070000,
506 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
509 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
512 * TX MAC Control/Status Bits
514 enum jme_txmcs_bit_masks {
515 TXMCS_IFG2 = 0xC0000000,
516 TXMCS_IFG1 = 0x30000000,
517 TXMCS_TTHOLD = 0x00000300,
518 TXMCS_FBURST = 0x00000080,
519 TXMCS_CARRIEREXT = 0x00000040,
520 TXMCS_DEFER = 0x00000020,
521 TXMCS_BACKOFF = 0x00000010,
522 TXMCS_CARRIERSENSE = 0x00000008,
523 TXMCS_COLLISION = 0x00000004,
524 TXMCS_CRC = 0x00000002,
525 TXMCS_PADDING = 0x00000001,
527 enum jme_txmcs_values {
528 TXMCS_IFG2_6_4 = 0x00000000,
529 TXMCS_IFG2_8_5 = 0x40000000,
530 TXMCS_IFG2_10_6 = 0x80000000,
531 TXMCS_IFG2_12_7 = 0xC0000000,
533 TXMCS_IFG1_8_4 = 0x00000000,
534 TXMCS_IFG1_12_6 = 0x10000000,
535 TXMCS_IFG1_16_8 = 0x20000000,
536 TXMCS_IFG1_20_10 = 0x30000000,
538 TXMCS_TTHOLD_1_8 = 0x00000000,
539 TXMCS_TTHOLD_1_4 = 0x00000100,
540 TXMCS_TTHOLD_1_2 = 0x00000200,
541 TXMCS_TTHOLD_FULL = 0x00000300,
543 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
551 enum jme_txpfc_bits_masks {
552 TXPFC_VLAN_TAG = 0xFFFF0000,
553 TXPFC_VLAN_EN = 0x00008000,
554 TXPFC_PF_EN = 0x00000001,
557 enum jme_txtrhd_bits_masks {
558 TXTRHD_TXPEN = 0x80000000,
559 TXTRHD_TXP = 0x7FFFFF00,
560 TXTRHD_TXREN = 0x00000080,
561 TXTRHD_TXRL = 0x0000007F,
563 enum jme_txtrhd_shifts {
564 TXTRHD_TXP_SHIFT = 8,
565 TXTRHD_TXRL_SHIFT = 0,
570 * RX Control/Status Bits
572 enum jme_rxcs_bit_masks {
573 /* FIFO full threshold for transmitting Tx Pause Packet */
574 RXCS_FIFOTHTP = 0x30000000,
575 /* FIFO threshold for processing next packet */
576 RXCS_FIFOTHNP = 0x0C000000,
577 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
578 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
579 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
580 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
581 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
582 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
583 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
584 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
585 RXCS_QST = 0x00000004, /* Receive queue start */
586 RXCS_SUSPEND = 0x00000002,
587 RXCS_ENABLE = 0x00000001,
589 enum jme_rxcs_values {
590 RXCS_FIFOTHTP_16T = 0x00000000,
591 RXCS_FIFOTHTP_32T = 0x10000000,
592 RXCS_FIFOTHTP_64T = 0x20000000,
593 RXCS_FIFOTHTP_128T = 0x30000000,
595 RXCS_FIFOTHNP_16QW = 0x00000000,
596 RXCS_FIFOTHNP_32QW = 0x04000000,
597 RXCS_FIFOTHNP_64QW = 0x08000000,
598 RXCS_FIFOTHNP_128QW = 0x0C000000,
600 RXCS_DMAREQSZ_16B = 0x00000000,
601 RXCS_DMAREQSZ_32B = 0x01000000,
602 RXCS_DMAREQSZ_64B = 0x02000000,
603 RXCS_DMAREQSZ_128B = 0x03000000,
605 RXCS_QUEUESEL_Q0 = 0x00000000,
606 RXCS_QUEUESEL_Q1 = 0x00010000,
607 RXCS_QUEUESEL_Q2 = 0x00020000,
608 RXCS_QUEUESEL_Q3 = 0x00030000,
610 RXCS_RETRYGAP_256ns = 0x00000000,
611 RXCS_RETRYGAP_512ns = 0x00001000,
612 RXCS_RETRYGAP_1024ns = 0x00002000,
613 RXCS_RETRYGAP_2048ns = 0x00003000,
614 RXCS_RETRYGAP_4096ns = 0x00004000,
615 RXCS_RETRYGAP_8192ns = 0x00005000,
616 RXCS_RETRYGAP_16384ns = 0x00006000,
617 RXCS_RETRYGAP_32768ns = 0x00007000,
619 RXCS_RETRYCNT_0 = 0x00000000,
620 RXCS_RETRYCNT_4 = 0x00000100,
621 RXCS_RETRYCNT_8 = 0x00000200,
622 RXCS_RETRYCNT_12 = 0x00000300,
623 RXCS_RETRYCNT_16 = 0x00000400,
624 RXCS_RETRYCNT_20 = 0x00000500,
625 RXCS_RETRYCNT_24 = 0x00000600,
626 RXCS_RETRYCNT_28 = 0x00000700,
627 RXCS_RETRYCNT_32 = 0x00000800,
628 RXCS_RETRYCNT_36 = 0x00000900,
629 RXCS_RETRYCNT_40 = 0x00000A00,
630 RXCS_RETRYCNT_44 = 0x00000B00,
631 RXCS_RETRYCNT_48 = 0x00000C00,
632 RXCS_RETRYCNT_52 = 0x00000D00,
633 RXCS_RETRYCNT_56 = 0x00000E00,
634 RXCS_RETRYCNT_60 = 0x00000F00,
636 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
637 RXCS_FIFOTHNP_128QW |
639 RXCS_RETRYGAP_256ns |
642 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
645 * RX MAC Control/Status Bits
647 enum jme_rxmcs_bits {
648 RXMCS_ALLFRAME = 0x00000800,
649 RXMCS_BRDFRAME = 0x00000400,
650 RXMCS_MULFRAME = 0x00000200,
651 RXMCS_UNIFRAME = 0x00000100,
652 RXMCS_ALLMULFRAME = 0x00000080,
653 RXMCS_MULFILTERED = 0x00000040,
654 RXMCS_RXCOLLDEC = 0x00000020,
655 RXMCS_FLOWCTRL = 0x00000008,
656 RXMCS_VTAGRM = 0x00000004,
657 RXMCS_PREPAD = 0x00000002,
658 RXMCS_CHECKSUM = 0x00000001,
660 RXMCS_DEFAULT = RXMCS_VTAGRM |
667 * Wakeup Frame setup interface registers
669 #define WAKEUP_FRAME_NR 8
670 #define WAKEUP_FRAME_MASK_DWNR 4
671 enum jme_wfoi_bit_masks {
672 WFOI_MASK_SEL = 0x00000070,
673 WFOI_CRC_SEL = 0x00000008,
674 WFOI_FRAME_SEL = 0x00000007,
676 enum jme_wfoi_shifts {
681 * SMI Related definitions
683 enum jme_smi_bit_mask
685 SMI_DATA_MASK = 0xFFFF0000,
686 SMI_REG_ADDR_MASK = 0x0000F800,
687 SMI_PHY_ADDR_MASK = 0x000007C0,
688 SMI_OP_WRITE = 0x00000020,
689 /* Set to 1, after req done it'll be cleared to 0 */
690 SMI_OP_REQ = 0x00000010,
691 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
692 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
693 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
694 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
696 enum jme_smi_bit_shift
699 SMI_REG_ADDR_SHIFT = 11,
700 SMI_PHY_ADDR_SHIFT = 6,
702 __always_inline __u32 smi_reg_addr(int x)
704 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
706 __always_inline __u32 smi_phy_addr(int x)
708 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
710 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
713 * Global Host Control
715 enum jme_ghc_bit_mask {
716 GHC_SWRST = 0x40000000,
717 GHC_DPX = 0x00000040,
718 GHC_SPEED = 0x00000030,
719 GHC_LINK_POLL = 0x00000001,
721 enum jme_ghc_speed_val {
722 GHC_SPEED_10M = 0x00000010,
723 GHC_SPEED_100M = 0x00000020,
724 GHC_SPEED_1000M = 0x00000030,
728 * Power management control and status register
730 enum jme_pmcs_bit_masks {
731 PMCS_WF7DET = 0x80000000,
732 PMCS_WF6DET = 0x40000000,
733 PMCS_WF5DET = 0x20000000,
734 PMCS_WF4DET = 0x10000000,
735 PMCS_WF3DET = 0x08000000,
736 PMCS_WF2DET = 0x04000000,
737 PMCS_WF1DET = 0x02000000,
738 PMCS_WF0DET = 0x01000000,
739 PMCS_LFDET = 0x00040000,
740 PMCS_LRDET = 0x00020000,
741 PMCS_MFDET = 0x00010000,
742 PMCS_WF7EN = 0x00008000,
743 PMCS_WF6EN = 0x00004000,
744 PMCS_WF5EN = 0x00002000,
745 PMCS_WF4EN = 0x00001000,
746 PMCS_WF3EN = 0x00000800,
747 PMCS_WF2EN = 0x00000400,
748 PMCS_WF1EN = 0x00000200,
749 PMCS_WF0EN = 0x00000100,
750 PMCS_LFEN = 0x00000004,
751 PMCS_LREN = 0x00000002,
752 PMCS_MFEN = 0x00000001,
756 * Giga PHY Status Registers
758 enum jme_phy_link_bit_mask {
759 PHY_LINK_SPEED_MASK = 0x0000C000,
760 PHY_LINK_DUPLEX = 0x00002000,
761 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
762 PHY_LINK_UP = 0x00000400,
763 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
764 PHY_LINK_MDI_STAT = 0x00000040,
766 enum jme_phy_link_speed_val {
767 PHY_LINK_SPEED_10M = 0x00000000,
768 PHY_LINK_SPEED_100M = 0x00004000,
769 PHY_LINK_SPEED_1000M = 0x00008000,
771 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
774 * SMB Control and Status
776 enum jme_smbcsr_bit_mask {
777 SMBCSR_CNACK = 0x00020000,
778 SMBCSR_RELOAD = 0x00010000,
779 SMBCSR_EEPROMD = 0x00000020,
781 #define JME_SMB_TIMEOUT 10 /* 10 msec */
784 * Timer Control/Status Register
786 enum jme_tmcsr_bit_masks {
787 TMCSR_SWIT = 0x80000000,
788 TMCSR_EN = 0x01000000,
789 TMCSR_CNT = 0x00FFFFFF,
794 * General Purpost REG-0
796 enum jme_gpreg0_masks {
797 GPREG0_DISSH = 0xFF000000,
798 GPREG0_PCIRLMT = 0x00300000,
799 GPREG0_PCCNOMUTCLR = 0x00040000,
800 GPREG0_PCCTMR = 0x00000300,
801 GPREG0_PHYADDR = 0x0000001F,
803 enum jme_gpreg0_vals {
804 GPREG0_DISSH_DW7 = 0x80000000,
805 GPREG0_DISSH_DW6 = 0x40000000,
806 GPREG0_DISSH_DW5 = 0x20000000,
807 GPREG0_DISSH_DW4 = 0x10000000,
808 GPREG0_DISSH_DW3 = 0x08000000,
809 GPREG0_DISSH_DW2 = 0x04000000,
810 GPREG0_DISSH_DW1 = 0x02000000,
811 GPREG0_DISSH_DW0 = 0x01000000,
812 GPREG0_DISSH_ALL = 0xFF000000,
814 GPREG0_PCIRLMT_8 = 0x00000000,
815 GPREG0_PCIRLMT_6 = 0x00100000,
816 GPREG0_PCIRLMT_5 = 0x00200000,
817 GPREG0_PCIRLMT_4 = 0x00300000,
819 GPREG0_PCCTMR_16ns = 0x00000000,
820 GPREG0_PCCTMR_256ns = 0x00000100,
821 GPREG0_PCCTMR_1us = 0x00000200,
822 GPREG0_PCCTMR_1ms = 0x00000300,
824 GPREG0_PHYADDR_1 = 0x00000001,
826 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
833 * Interrupt Status Bits
835 enum jme_interrupt_bits
837 INTR_SWINTR = 0x80000000,
838 INTR_TMINTR = 0x40000000,
839 INTR_LINKCH = 0x20000000,
840 INTR_PAUSERCV = 0x10000000,
841 INTR_MAGICRCV = 0x08000000,
842 INTR_WAKERCV = 0x04000000,
843 INTR_PCCRX0TO = 0x02000000,
844 INTR_PCCRX1TO = 0x01000000,
845 INTR_PCCRX2TO = 0x00800000,
846 INTR_PCCRX3TO = 0x00400000,
847 INTR_PCCTXTO = 0x00200000,
848 INTR_PCCRX0 = 0x00100000,
849 INTR_PCCRX1 = 0x00080000,
850 INTR_PCCRX2 = 0x00040000,
851 INTR_PCCRX3 = 0x00020000,
852 INTR_PCCTX = 0x00010000,
853 INTR_RX3EMP = 0x00008000,
854 INTR_RX2EMP = 0x00004000,
855 INTR_RX1EMP = 0x00002000,
856 INTR_RX0EMP = 0x00001000,
857 INTR_RX3 = 0x00000800,
858 INTR_RX2 = 0x00000400,
859 INTR_RX1 = 0x00000200,
860 INTR_RX0 = 0x00000100,
861 INTR_TX7 = 0x00000080,
862 INTR_TX6 = 0x00000040,
863 INTR_TX5 = 0x00000020,
864 INTR_TX4 = 0x00000010,
865 INTR_TX3 = 0x00000008,
866 INTR_TX2 = 0x00000004,
867 INTR_TX1 = 0x00000002,
868 INTR_TX0 = 0x00000001,
870 static const __u32 INTR_ENABLE = INTR_SWINTR |
880 * PCC Control Registers
882 enum jme_pccrx_masks {
883 PCCRXTO_MASK = 0xFFFF0000,
884 PCCRX_MASK = 0x0000FF00,
886 enum jme_pcctx_masks {
887 PCCTXTO_MASK = 0xFFFF0000,
888 PCCTX_MASK = 0x0000FF00,
889 PCCTX_QS_MASK = 0x000000FF,
891 enum jme_pccrx_shifts {
895 enum jme_pcctx_shifts {
899 enum jme_pcctx_bits {
900 PCCTXQ0_EN = 0x00000001,
901 PCCTXQ1_EN = 0x00000002,
902 PCCTXQ2_EN = 0x00000004,
903 PCCTXQ3_EN = 0x00000008,
904 PCCTXQ4_EN = 0x00000010,
905 PCCTXQ5_EN = 0x00000020,
906 PCCTXQ6_EN = 0x00000040,
907 PCCTXQ7_EN = 0x00000080,
912 * Shadow base address register bits
914 enum jme_shadow_base_address_bits {
919 * Read/Write MMaped I/O Registers
921 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
923 return le32_to_cpu(readl((__u8*)jme->regs + reg));
925 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
927 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
929 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
932 * Read after write should cause flush
934 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
935 readl((__u8*)jme->regs + reg);
939 * Function prototypes for ethtool
941 static void jme_get_drvinfo(struct net_device *netdev,
942 struct ethtool_drvinfo *info);
943 static int jme_get_settings(struct net_device *netdev,
944 struct ethtool_cmd *ecmd);
945 static int jme_set_settings(struct net_device *netdev,
946 struct ethtool_cmd *ecmd);
947 static u32 jme_get_link(struct net_device *netdev);
951 * Function prototypes for netdev
953 static int jme_open(struct net_device *netdev);
954 static int jme_close(struct net_device *netdev);
955 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
956 static int jme_set_macaddr(struct net_device *netdev, void *p);
957 static void jme_set_multi(struct net_device *netdev);