jme: Fix hardware action of full-duplex

[jme.git] / jme.c

diff --git a/jme.c b/jme.c
index 992b624bb230530cde6c065a3894fc49505afad4..ee39a05d848d384bbfedf939de675033811dc933 100644 (file)
--- a/jme.c
+++ b/jme.c
@@ -339,13 +339,13 @@ jme_linkstat_from_phy(struct jme_adapter *jme)
 }
 
 static inline void
-jme_set_phyfifoa(struct jme_adapter *jme)
+jme_set_phyfifo_5level(struct jme_adapter *jme)
 {
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 }
 
 static inline void
-jme_set_phyfifob(struct jme_adapter *jme)
+jme_set_phyfifo_8level(struct jme_adapter *jme)
 {
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 }
@@ -442,16 +442,14 @@ jme_check_link(struct net_device *netdev, int testonly)
 
                if (phylink & PHY_LINK_DUPLEX) {
                        jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
+                       jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
                        ghc |= GHC_DPX;
                } else {
                        jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
                                                TXMCS_BACKOFF |
                                                TXMCS_CARRIERSENSE |
                                                TXMCS_COLLISION);
-                       jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
-                               ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
-                               TXTRHD_TXREN |
-                               ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
+                       jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
                }
 
                gpreg1 = GPREG1_DEFAULT;
@@ -460,15 +458,15 @@ jme_check_link(struct net_device *netdev, int testonly)
                                gpreg1 |= GPREG1_HALFMODEPATCH;
                        switch (phylink & PHY_LINK_SPEED_MASK) {
                        case PHY_LINK_SPEED_10M:
-                               jme_set_phyfifoa(jme);
+                               jme_set_phyfifo_8level(jme);
                                gpreg1 |= GPREG1_RSSPATCH;
                                break;
                        case PHY_LINK_SPEED_100M:
-                               jme_set_phyfifob(jme);
+                               jme_set_phyfifo_5level(jme);
                                gpreg1 |= GPREG1_RSSPATCH;
                                break;
                        case PHY_LINK_SPEED_1000M:
-                               jme_set_phyfifoa(jme);
+                               jme_set_phyfifo_8level(jme);
                                break;
                        default:
                                break;
@@ -1602,6 +1600,38 @@ jme_free_irq(struct jme_adapter *jme)
        }
 }
 
+static inline void
+jme_new_phy_on(struct jme_adapter *jme)
+{
+       u32 reg;
+
+       reg = jread32(jme, JME_PHY_PWR);
+       reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
+                PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
+       jwrite32(jme, JME_PHY_PWR, reg);
+
+       pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
+       reg &= ~PE1_GPREG0_PBG;
+       reg |= PE1_GPREG0_ENBG;
+       pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
+}
+
+static inline void
+jme_new_phy_off(struct jme_adapter *jme)
+{
+       u32 reg;
+
+       reg = jread32(jme, JME_PHY_PWR);
+       reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
+              PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
+       jwrite32(jme, JME_PHY_PWR, reg);
+
+       pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
+       reg &= ~PE1_GPREG0_PBG;
+       reg |= PE1_GPREG0_PDD3COLD;
+       pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
+}
+
 static inline void
 jme_phy_on(struct jme_adapter *jme)
 {
@@ -1610,6 +1640,22 @@ jme_phy_on(struct jme_adapter *jme)
        bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
        bmcr &= ~BMCR_PDOWN;
        jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
+
+       if (new_phy_power_ctrl(jme->chip_main_rev))
+               jme_new_phy_on(jme);
+}
+
+static inline void
+jme_phy_off(struct jme_adapter *jme)
+{
+       u32 bmcr;
+
+       bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
+       bmcr |= BMCR_PDOWN;
+       jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
+
+       if (new_phy_power_ctrl(jme->chip_main_rev))
+               jme_new_phy_off(jme);
 }
 
 static int
@@ -1632,12 +1678,11 @@ jme_open(struct net_device *netdev)
 
        jme_start_irq(jme);
 
-       if (test_bit(JME_FLAG_SSET, &jme->flags)) {
-               jme_phy_on(jme);
+       jme_phy_on(jme);
+       if (test_bit(JME_FLAG_SSET, &jme->flags))
                jme_set_settings(netdev, &jme->old_ecmd);
-       } else {
+       else
                jme_reset_phy_processor(jme);
-       }
 
        jme_reset_link(jme);
 
@@ -1683,12 +1728,6 @@ jme_wait_link(struct jme_adapter *jme)
        }
 }
 
-static inline void
-jme_phy_off(struct jme_adapter *jme)
-{
-       jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
-}
-
 static void
 jme_powersave_phy(struct jme_adapter *jme)
 {
@@ -3075,7 +3114,7 @@ jme_init_one(struct pci_dev *pdev,
        jme->mii_if.mdio_write = jme_mdio_write;
 
        jme_clear_pm(jme);
-       jme_set_phyfifoa(jme);
+       jme_set_phyfifo_5level(jme);
        pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
        if (!jme->fpgaver)
                jme_phy_init(jme);
@@ -3216,12 +3255,11 @@ jme_resume(struct pci_dev *pdev)
        jme_clear_pm(jme);
        pci_restore_state(pdev);
 
-       if (test_bit(JME_FLAG_SSET, &jme->flags)) {
-               jme_phy_on(jme);
+       jme_phy_on(jme);
+       if (test_bit(JME_FLAG_SSET, &jme->flags))
                jme_set_settings(netdev, &jme->old_ecmd);
-       } else {
+       else
                jme_reset_phy_processor(jme);
-       }
 
        jme_start_irq(jme);
        netif_device_attach(netdev);