2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
63 jme_mdio_read(struct net_device *netdev, int phy, int reg)
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
93 jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
96 struct jme_adapter *jme = netdev_priv(netdev);
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
115 jme_reset_phy_processor(struct jme_adapter *jme)
119 jme_mdio_write(jme->dev,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
130 val = jme_mdio_read(jme->dev,
134 jme_mdio_write(jme->dev,
136 MII_BMCR, val | BMCR_RESET);
140 jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
150 jwrite32(jme, JME_WFODP, crc);
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
161 jwrite32(jme, JME_WFODP, mask[i]);
167 jme_reset_mac_processor(struct jme_adapter *jme)
169 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
170 u32 crc = 0xCDCDCDCD;
174 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
176 jwrite32(jme, JME_GHC, jme->reg_ghc);
178 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_RXQDC, 0x00000000);
181 jwrite32(jme, JME_RXNDA, 0x00000000);
182 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
183 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
184 jwrite32(jme, JME_TXQDC, 0x00000000);
185 jwrite32(jme, JME_TXNDA, 0x00000000);
187 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
188 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
189 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
190 jme_setup_wakeup_frame(jme, mask, crc, i);
192 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
194 gpreg0 = GPREG0_DEFAULT;
195 jwrite32(jme, JME_GPREG0, gpreg0);
196 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
200 jme_reset_ghc_speed(struct jme_adapter *jme)
202 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
203 jwrite32(jme, JME_GHC, jme->reg_ghc);
207 jme_clear_pm(struct jme_adapter *jme)
209 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
210 pci_set_power_state(jme->pdev, PCI_D0);
211 pci_enable_wake(jme->pdev, PCI_D0, false);
215 jme_reload_eeprom(struct jme_adapter *jme)
220 val = jread32(jme, JME_SMBCSR);
222 if (val & SMBCSR_EEPROMD) {
224 jwrite32(jme, JME_SMBCSR, val);
225 val |= SMBCSR_RELOAD;
226 jwrite32(jme, JME_SMBCSR, val);
229 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
231 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
236 pr_err("eeprom reload timeout\n");
245 jme_load_macaddr(struct net_device *netdev)
247 struct jme_adapter *jme = netdev_priv(netdev);
248 unsigned char macaddr[6];
251 spin_lock_bh(&jme->macaddr_lock);
252 val = jread32(jme, JME_RXUMA_LO);
253 macaddr[0] = (val >> 0) & 0xFF;
254 macaddr[1] = (val >> 8) & 0xFF;
255 macaddr[2] = (val >> 16) & 0xFF;
256 macaddr[3] = (val >> 24) & 0xFF;
257 val = jread32(jme, JME_RXUMA_HI);
258 macaddr[4] = (val >> 0) & 0xFF;
259 macaddr[5] = (val >> 8) & 0xFF;
260 memcpy(netdev->dev_addr, macaddr, 6);
261 spin_unlock_bh(&jme->macaddr_lock);
265 jme_set_rx_pcc(struct jme_adapter *jme, int p)
269 jwrite32(jme, JME_PCCRX0,
270 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
271 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 jwrite32(jme, JME_PCCRX0,
275 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
276 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 jwrite32(jme, JME_PCCRX0,
280 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
281 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 jwrite32(jme, JME_PCCRX0,
285 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
286 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
293 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
294 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
298 jme_start_irq(struct jme_adapter *jme)
300 register struct dynpcc_info *dpi = &(jme->dpi);
302 jme_set_rx_pcc(jme, PCC_P1);
304 dpi->attempt = PCC_P1;
307 jwrite32(jme, JME_PCCTX,
308 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
309 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
316 jwrite32(jme, JME_IENS, INTR_ENABLE);
320 jme_stop_irq(struct jme_adapter *jme)
325 jwrite32f(jme, JME_IENC, INTR_ENABLE);
329 jme_linkstat_from_phy(struct jme_adapter *jme)
333 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
334 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
335 if (bmsr & BMSR_ANCOMP)
336 phylink |= PHY_LINK_AUTONEG_COMPLETE;
342 jme_set_phyfifoa(struct jme_adapter *jme)
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
348 jme_set_phyfifob(struct jme_adapter *jme)
350 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
354 jme_check_link(struct net_device *netdev, int testonly)
356 struct jme_adapter *jme = netdev_priv(netdev);
357 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
364 phylink = jme_linkstat_from_phy(jme);
366 phylink = jread32(jme, JME_PHY_LINK);
368 if (phylink & PHY_LINK_UP) {
369 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
371 * If we did not enable AN
372 * Speed/Duplex Info should be obtained from SMI
374 phylink = PHY_LINK_UP;
376 bmcr = jme_mdio_read(jme->dev,
380 phylink |= ((bmcr & BMCR_SPEED1000) &&
381 (bmcr & BMCR_SPEED100) == 0) ?
382 PHY_LINK_SPEED_1000M :
383 (bmcr & BMCR_SPEED100) ?
384 PHY_LINK_SPEED_100M :
387 phylink |= (bmcr & BMCR_FULLDPLX) ?
390 strcat(linkmsg, "Forced: ");
393 * Keep polling for speed/duplex resolve complete
395 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
401 phylink = jme_linkstat_from_phy(jme);
403 phylink = jread32(jme, JME_PHY_LINK);
406 pr_err("Waiting speed resolve timeout\n");
408 strcat(linkmsg, "ANed: ");
411 if (jme->phylink == phylink) {
418 jme->phylink = phylink;
420 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
422 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
423 switch (phylink & PHY_LINK_SPEED_MASK) {
424 case PHY_LINK_SPEED_10M:
425 ghc |= GHC_SPEED_10M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "10 Mbps, ");
429 case PHY_LINK_SPEED_100M:
430 ghc |= GHC_SPEED_100M |
431 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
432 strcat(linkmsg, "100 Mbps, ");
434 case PHY_LINK_SPEED_1000M:
435 ghc |= GHC_SPEED_1000M |
436 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
437 strcat(linkmsg, "1000 Mbps, ");
443 if (phylink & PHY_LINK_DUPLEX) {
444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
447 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
451 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
452 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
454 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
457 gpreg1 = GPREG1_DEFAULT;
458 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
459 if (!(phylink & PHY_LINK_DUPLEX))
460 gpreg1 |= GPREG1_HALFMODEPATCH;
461 switch (phylink & PHY_LINK_SPEED_MASK) {
462 case PHY_LINK_SPEED_10M:
463 jme_set_phyfifoa(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
466 case PHY_LINK_SPEED_100M:
467 jme_set_phyfifob(jme);
468 gpreg1 |= GPREG1_RSSPATCH;
470 case PHY_LINK_SPEED_1000M:
471 jme_set_phyfifoa(jme);
478 jwrite32(jme, JME_GPREG1, gpreg1);
479 jwrite32(jme, JME_GHC, ghc);
482 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
485 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
488 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
489 netif_carrier_on(netdev);
494 netif_info(jme, link, jme->dev, "Link is down\n");
496 netif_carrier_off(netdev);
504 jme_setup_tx_resources(struct jme_adapter *jme)
506 struct jme_ring *txring = &(jme->txring[0]);
508 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
509 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
519 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
521 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
522 txring->next_to_use = 0;
523 atomic_set(&txring->next_to_clean, 0);
524 atomic_set(&txring->nr_free, jme->tx_ring_size);
526 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
527 jme->tx_ring_size, GFP_ATOMIC);
528 if (unlikely(!(txring->bufinf)))
529 goto err_free_txring;
532 * Initialize Transmit Descriptors
534 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
535 memset(txring->bufinf, 0,
536 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
541 dma_free_coherent(&(jme->pdev->dev),
542 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
548 txring->dmaalloc = 0;
550 txring->bufinf = NULL;
556 jme_free_tx_resources(struct jme_adapter *jme)
559 struct jme_ring *txring = &(jme->txring[0]);
560 struct jme_buffer_info *txbi;
563 if (txring->bufinf) {
564 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
565 txbi = txring->bufinf + i;
567 dev_kfree_skb(txbi->skb);
573 txbi->start_xmit = 0;
575 kfree(txring->bufinf);
578 dma_free_coherent(&(jme->pdev->dev),
579 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
583 txring->alloc = NULL;
585 txring->dmaalloc = 0;
587 txring->bufinf = NULL;
589 txring->next_to_use = 0;
590 atomic_set(&txring->next_to_clean, 0);
591 atomic_set(&txring->nr_free, 0);
595 jme_enable_tx_engine(struct jme_adapter *jme)
600 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
604 * Setup TX Queue 0 DMA Bass Address
606 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
608 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
611 * Setup TX Descptor Count
613 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
619 jwrite32(jme, JME_TXCS, jme->reg_txcs |
626 jme_restart_tx_engine(struct jme_adapter *jme)
631 jwrite32(jme, JME_TXCS, jme->reg_txcs |
637 jme_disable_tx_engine(struct jme_adapter *jme)
645 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
648 val = jread32(jme, JME_TXCS);
649 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
651 val = jread32(jme, JME_TXCS);
656 pr_err("Disable TX engine timeout\n");
660 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
662 struct jme_ring *rxring = &(jme->rxring[0]);
663 register struct rxdesc *rxdesc = rxring->desc;
664 struct jme_buffer_info *rxbi = rxring->bufinf;
670 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
671 rxdesc->desc1.bufaddrl = cpu_to_le32(
672 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
673 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
674 if (jme->dev->features & NETIF_F_HIGHDMA)
675 rxdesc->desc1.flags = RXFLAG_64BIT;
677 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
681 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
683 struct jme_ring *rxring = &(jme->rxring[0]);
684 struct jme_buffer_info *rxbi = rxring->bufinf + i;
687 skb = netdev_alloc_skb(jme->dev,
688 jme->dev->mtu + RX_EXTRA_LEN);
691 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
696 rxbi->len = skb_tailroom(skb);
697 rxbi->mapping = pci_map_page(jme->pdev,
698 virt_to_page(skb->data),
699 offset_in_page(skb->data),
707 jme_free_rx_buf(struct jme_adapter *jme, int i)
709 struct jme_ring *rxring = &(jme->rxring[0]);
710 struct jme_buffer_info *rxbi = rxring->bufinf;
714 pci_unmap_page(jme->pdev,
718 dev_kfree_skb(rxbi->skb);
726 jme_free_rx_resources(struct jme_adapter *jme)
729 struct jme_ring *rxring = &(jme->rxring[0]);
732 if (rxring->bufinf) {
733 for (i = 0 ; i < jme->rx_ring_size ; ++i)
734 jme_free_rx_buf(jme, i);
735 kfree(rxring->bufinf);
738 dma_free_coherent(&(jme->pdev->dev),
739 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
742 rxring->alloc = NULL;
744 rxring->dmaalloc = 0;
746 rxring->bufinf = NULL;
748 rxring->next_to_use = 0;
749 atomic_set(&rxring->next_to_clean, 0);
753 jme_setup_rx_resources(struct jme_adapter *jme)
756 struct jme_ring *rxring = &(jme->rxring[0]);
758 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
759 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
768 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
770 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
771 rxring->next_to_use = 0;
772 atomic_set(&rxring->next_to_clean, 0);
774 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
775 jme->rx_ring_size, GFP_ATOMIC);
776 if (unlikely(!(rxring->bufinf)))
777 goto err_free_rxring;
780 * Initiallize Receive Descriptors
782 memset(rxring->bufinf, 0,
783 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
784 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
785 if (unlikely(jme_make_new_rx_buf(jme, i))) {
786 jme_free_rx_resources(jme);
790 jme_set_clean_rxdesc(jme, i);
796 dma_free_coherent(&(jme->pdev->dev),
797 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
802 rxring->dmaalloc = 0;
804 rxring->bufinf = NULL;
810 jme_enable_rx_engine(struct jme_adapter *jme)
815 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
820 * Setup RX DMA Bass Address
822 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
823 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
824 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
827 * Setup RX Descriptor Count
829 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
832 * Setup Unicast Filter
834 jme_set_multi(jme->dev);
840 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
847 jme_restart_rx_engine(struct jme_adapter *jme)
852 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
859 jme_disable_rx_engine(struct jme_adapter *jme)
867 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
870 val = jread32(jme, JME_RXCS);
871 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
873 val = jread32(jme, JME_RXCS);
878 pr_err("Disable RX engine timeout\n");
883 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
885 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
889 == RXWBFLAG_TCPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
895 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
896 == RXWBFLAG_UDPON)) {
897 if (flags & RXWBFLAG_IPV4)
898 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
902 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
904 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
912 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
914 struct jme_ring *rxring = &(jme->rxring[0]);
915 struct rxdesc *rxdesc = rxring->desc;
916 struct jme_buffer_info *rxbi = rxring->bufinf;
924 pci_dma_sync_single_for_cpu(jme->pdev,
929 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
930 pci_dma_sync_single_for_device(jme->pdev,
935 ++(NET_STAT(jme).rx_dropped);
937 framesize = le16_to_cpu(rxdesc->descwb.framesize)
940 skb_reserve(skb, RX_PREPAD_SIZE);
941 skb_put(skb, framesize);
942 skb->protocol = eth_type_trans(skb, jme->dev);
944 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
945 skb->ip_summed = CHECKSUM_UNNECESSARY;
947 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
948 skb->ip_summed = CHECKSUM_NONE;
950 skb_checksum_none_assert(skb);
953 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
955 jme->jme_vlan_rx(skb, jme->vlgrp,
956 le16_to_cpu(rxdesc->descwb.vlan));
957 NET_STAT(jme).rx_bytes += 4;
965 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
966 cpu_to_le16(RXWBFLAG_DEST_MUL))
967 ++(NET_STAT(jme).multicast);
969 NET_STAT(jme).rx_bytes += framesize;
970 ++(NET_STAT(jme).rx_packets);
973 jme_set_clean_rxdesc(jme, idx);
978 jme_process_receive(struct jme_adapter *jme, int limit)
980 struct jme_ring *rxring = &(jme->rxring[0]);
981 struct rxdesc *rxdesc = rxring->desc;
982 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
984 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
987 if (unlikely(atomic_read(&jme->link_changing) != 1))
990 if (unlikely(!netif_carrier_ok(jme->dev)))
993 i = atomic_read(&rxring->next_to_clean);
995 rxdesc = rxring->desc;
998 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
999 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1004 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1006 if (unlikely(desccnt > 1 ||
1007 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1009 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1010 ++(NET_STAT(jme).rx_crc_errors);
1011 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1012 ++(NET_STAT(jme).rx_fifo_errors);
1014 ++(NET_STAT(jme).rx_errors);
1017 limit -= desccnt - 1;
1019 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1020 jme_set_clean_rxdesc(jme, j);
1021 j = (j + 1) & (mask);
1025 jme_alloc_and_feed_skb(jme, i);
1028 i = (i + desccnt) & (mask);
1032 atomic_set(&rxring->next_to_clean, i);
1035 atomic_inc(&jme->rx_cleaning);
1037 return limit > 0 ? limit : 0;
1042 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1044 if (likely(atmp == dpi->cur)) {
1049 if (dpi->attempt == atmp) {
1052 dpi->attempt = atmp;
1059 jme_dynamic_pcc(struct jme_adapter *jme)
1061 register struct dynpcc_info *dpi = &(jme->dpi);
1063 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1064 jme_attempt_pcc(dpi, PCC_P3);
1065 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1066 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1067 jme_attempt_pcc(dpi, PCC_P2);
1069 jme_attempt_pcc(dpi, PCC_P1);
1071 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1072 if (dpi->attempt < dpi->cur)
1073 tasklet_schedule(&jme->rxclean_task);
1074 jme_set_rx_pcc(jme, dpi->attempt);
1075 dpi->cur = dpi->attempt;
1081 jme_start_pcc_timer(struct jme_adapter *jme)
1083 struct dynpcc_info *dpi = &(jme->dpi);
1084 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1085 dpi->last_pkts = NET_STAT(jme).rx_packets;
1087 jwrite32(jme, JME_TMCSR,
1088 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1092 jme_stop_pcc_timer(struct jme_adapter *jme)
1094 jwrite32(jme, JME_TMCSR, 0);
1098 jme_shutdown_nic(struct jme_adapter *jme)
1102 phylink = jme_linkstat_from_phy(jme);
1104 if (!(phylink & PHY_LINK_UP)) {
1106 * Disable all interrupt before issue timer
1109 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1114 jme_pcc_tasklet(unsigned long arg)
1116 struct jme_adapter *jme = (struct jme_adapter *)arg;
1117 struct net_device *netdev = jme->dev;
1119 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1120 jme_shutdown_nic(jme);
1124 if (unlikely(!netif_carrier_ok(netdev) ||
1125 (atomic_read(&jme->link_changing) != 1)
1127 jme_stop_pcc_timer(jme);
1131 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1132 jme_dynamic_pcc(jme);
1134 jme_start_pcc_timer(jme);
1138 jme_polling_mode(struct jme_adapter *jme)
1140 jme_set_rx_pcc(jme, PCC_OFF);
1144 jme_interrupt_mode(struct jme_adapter *jme)
1146 jme_set_rx_pcc(jme, PCC_P1);
1150 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1153 apmc = jread32(jme, JME_APMC);
1154 return apmc & JME_APMC_PSEUDO_HP_EN;
1158 jme_start_shutdown_timer(struct jme_adapter *jme)
1162 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1163 apmc &= ~JME_APMC_EPIEN_CTRL;
1165 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1168 jwrite32f(jme, JME_APMC, apmc);
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172 jwrite32(jme, JME_TMCSR,
1173 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1177 jme_stop_shutdown_timer(struct jme_adapter *jme)
1181 jwrite32f(jme, JME_TMCSR, 0);
1182 jwrite32f(jme, JME_TIMER2, 0);
1183 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1185 apmc = jread32(jme, JME_APMC);
1186 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1187 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1189 jwrite32f(jme, JME_APMC, apmc);
1193 jme_link_change_tasklet(unsigned long arg)
1195 struct jme_adapter *jme = (struct jme_adapter *)arg;
1196 struct net_device *netdev = jme->dev;
1199 while (!atomic_dec_and_test(&jme->link_changing)) {
1200 atomic_inc(&jme->link_changing);
1201 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1202 while (atomic_read(&jme->link_changing) != 1)
1203 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1206 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1209 jme->old_mtu = netdev->mtu;
1210 netif_stop_queue(netdev);
1211 if (jme_pseudo_hotplug_enabled(jme))
1212 jme_stop_shutdown_timer(jme);
1214 jme_stop_pcc_timer(jme);
1215 tasklet_disable(&jme->txclean_task);
1216 tasklet_disable(&jme->rxclean_task);
1217 tasklet_disable(&jme->rxempty_task);
1219 if (netif_carrier_ok(netdev)) {
1220 jme_reset_ghc_speed(jme);
1221 jme_disable_rx_engine(jme);
1222 jme_disable_tx_engine(jme);
1223 jme_reset_mac_processor(jme);
1224 jme_free_rx_resources(jme);
1225 jme_free_tx_resources(jme);
1227 if (test_bit(JME_FLAG_POLL, &jme->flags))
1228 jme_polling_mode(jme);
1230 netif_carrier_off(netdev);
1233 jme_check_link(netdev, 0);
1234 if (netif_carrier_ok(netdev)) {
1235 rc = jme_setup_rx_resources(jme);
1237 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1238 goto out_enable_tasklet;
1241 rc = jme_setup_tx_resources(jme);
1243 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1244 goto err_out_free_rx_resources;
1247 jme_enable_rx_engine(jme);
1248 jme_enable_tx_engine(jme);
1250 netif_start_queue(netdev);
1252 if (test_bit(JME_FLAG_POLL, &jme->flags))
1253 jme_interrupt_mode(jme);
1255 jme_start_pcc_timer(jme);
1256 } else if (jme_pseudo_hotplug_enabled(jme)) {
1257 jme_start_shutdown_timer(jme);
1260 goto out_enable_tasklet;
1262 err_out_free_rx_resources:
1263 jme_free_rx_resources(jme);
1265 tasklet_enable(&jme->txclean_task);
1266 tasklet_hi_enable(&jme->rxclean_task);
1267 tasklet_hi_enable(&jme->rxempty_task);
1269 atomic_inc(&jme->link_changing);
1273 jme_rx_clean_tasklet(unsigned long arg)
1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
1276 struct dynpcc_info *dpi = &(jme->dpi);
1278 jme_process_receive(jme, jme->rx_ring_size);
1284 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1286 struct jme_adapter *jme = jme_napi_priv(holder);
1290 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1292 while (atomic_read(&jme->rx_empty) > 0) {
1293 atomic_dec(&jme->rx_empty);
1294 ++(NET_STAT(jme).rx_dropped);
1295 jme_restart_rx_engine(jme);
1297 atomic_inc(&jme->rx_empty);
1300 JME_RX_COMPLETE(netdev, holder);
1301 jme_interrupt_mode(jme);
1304 JME_NAPI_WEIGHT_SET(budget, rest);
1305 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1309 jme_rx_empty_tasklet(unsigned long arg)
1311 struct jme_adapter *jme = (struct jme_adapter *)arg;
1313 if (unlikely(atomic_read(&jme->link_changing) != 1))
1316 if (unlikely(!netif_carrier_ok(jme->dev)))
1319 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1321 jme_rx_clean_tasklet(arg);
1323 while (atomic_read(&jme->rx_empty) > 0) {
1324 atomic_dec(&jme->rx_empty);
1325 ++(NET_STAT(jme).rx_dropped);
1326 jme_restart_rx_engine(jme);
1328 atomic_inc(&jme->rx_empty);
1332 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1334 struct jme_ring *txring = &(jme->txring[0]);
1337 if (unlikely(netif_queue_stopped(jme->dev) &&
1338 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1339 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1340 netif_wake_queue(jme->dev);
1346 jme_tx_clean_tasklet(unsigned long arg)
1348 struct jme_adapter *jme = (struct jme_adapter *)arg;
1349 struct jme_ring *txring = &(jme->txring[0]);
1350 struct txdesc *txdesc = txring->desc;
1351 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1352 int i, j, cnt = 0, max, err, mask;
1354 tx_dbg(jme, "Into txclean\n");
1356 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1359 if (unlikely(atomic_read(&jme->link_changing) != 1))
1362 if (unlikely(!netif_carrier_ok(jme->dev)))
1365 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1366 mask = jme->tx_ring_mask;
1368 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1372 if (likely(ctxbi->skb &&
1373 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1375 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1376 i, ctxbi->nr_desc, jiffies);
1378 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1380 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1381 ttxbi = txbi + ((i + j) & (mask));
1382 txdesc[(i + j) & (mask)].dw[0] = 0;
1384 pci_unmap_page(jme->pdev,
1393 dev_kfree_skb(ctxbi->skb);
1395 cnt += ctxbi->nr_desc;
1397 if (unlikely(err)) {
1398 ++(NET_STAT(jme).tx_carrier_errors);
1400 ++(NET_STAT(jme).tx_packets);
1401 NET_STAT(jme).tx_bytes += ctxbi->len;
1406 ctxbi->start_xmit = 0;
1412 i = (i + ctxbi->nr_desc) & mask;
1417 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1418 atomic_set(&txring->next_to_clean, i);
1419 atomic_add(cnt, &txring->nr_free);
1421 jme_wake_queue_if_stopped(jme);
1424 atomic_inc(&jme->tx_cleaning);
1428 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1433 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1435 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1437 * Link change event is critical
1438 * all other events are ignored
1440 jwrite32(jme, JME_IEVE, intrstat);
1441 tasklet_schedule(&jme->linkch_task);
1445 if (intrstat & INTR_TMINTR) {
1446 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1447 tasklet_schedule(&jme->pcc_task);
1450 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1451 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1452 tasklet_schedule(&jme->txclean_task);
1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1456 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1462 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1463 if (intrstat & INTR_RX0EMP)
1464 atomic_inc(&jme->rx_empty);
1466 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1467 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1468 jme_polling_mode(jme);
1469 JME_RX_SCHEDULE(jme);
1473 if (intrstat & INTR_RX0EMP) {
1474 atomic_inc(&jme->rx_empty);
1475 tasklet_hi_schedule(&jme->rxempty_task);
1476 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1477 tasklet_hi_schedule(&jme->rxclean_task);
1483 * Re-enable interrupt
1485 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1488 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1490 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1493 jme_intr(int irq, void *dev_id)
1496 struct net_device *netdev = dev_id;
1497 struct jme_adapter *jme = netdev_priv(netdev);
1500 intrstat = jread32(jme, JME_IEVE);
1503 * Check if it's really an interrupt for us
1505 if (unlikely((intrstat & INTR_ENABLE) == 0))
1509 * Check if the device still exist
1511 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1514 jme_intr_msi(jme, intrstat);
1519 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1521 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1524 jme_msi(int irq, void *dev_id)
1527 struct net_device *netdev = dev_id;
1528 struct jme_adapter *jme = netdev_priv(netdev);
1531 intrstat = jread32(jme, JME_IEVE);
1533 jme_intr_msi(jme, intrstat);
1539 jme_reset_link(struct jme_adapter *jme)
1541 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1545 jme_restart_an(struct jme_adapter *jme)
1549 spin_lock_bh(&jme->phy_lock);
1550 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1551 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1552 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1553 spin_unlock_bh(&jme->phy_lock);
1557 jme_request_irq(struct jme_adapter *jme)
1560 struct net_device *netdev = jme->dev;
1561 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1562 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1563 int irq_flags = SA_SHIRQ;
1565 irq_handler_t handler = jme_intr;
1566 int irq_flags = IRQF_SHARED;
1569 if (!pci_enable_msi(jme->pdev)) {
1570 set_bit(JME_FLAG_MSI, &jme->flags);
1575 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1579 "Unable to request %s interrupt (return: %d)\n",
1580 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1583 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1584 pci_disable_msi(jme->pdev);
1585 clear_bit(JME_FLAG_MSI, &jme->flags);
1588 netdev->irq = jme->pdev->irq;
1595 jme_free_irq(struct jme_adapter *jme)
1597 free_irq(jme->pdev->irq, jme->dev);
1598 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1599 pci_disable_msi(jme->pdev);
1600 clear_bit(JME_FLAG_MSI, &jme->flags);
1601 jme->dev->irq = jme->pdev->irq;
1606 jme_phy_on(struct jme_adapter *jme)
1610 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1611 bmcr &= ~BMCR_PDOWN;
1612 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1616 jme_open(struct net_device *netdev)
1618 struct jme_adapter *jme = netdev_priv(netdev);
1622 JME_NAPI_ENABLE(jme);
1624 tasklet_enable(&jme->linkch_task);
1625 tasklet_enable(&jme->txclean_task);
1626 tasklet_hi_enable(&jme->rxclean_task);
1627 tasklet_hi_enable(&jme->rxempty_task);
1629 rc = jme_request_irq(jme);
1635 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1637 jme_set_settings(netdev, &jme->old_ecmd);
1639 jme_reset_phy_processor(jme);
1642 jme_reset_link(jme);
1647 netif_stop_queue(netdev);
1648 netif_carrier_off(netdev);
1653 jme_set_100m_half(struct jme_adapter *jme)
1658 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1659 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1660 BMCR_SPEED1000 | BMCR_FULLDPLX);
1661 tmp |= BMCR_SPEED100;
1664 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1667 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1669 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1672 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1674 jme_wait_link(struct jme_adapter *jme)
1676 u32 phylink, to = JME_WAIT_LINK_TIME;
1679 phylink = jme_linkstat_from_phy(jme);
1680 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1682 phylink = jme_linkstat_from_phy(jme);
1687 jme_phy_off(struct jme_adapter *jme)
1689 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1693 jme_powersave_phy(struct jme_adapter *jme)
1695 if (jme->reg_pmcs) {
1696 jme_set_100m_half(jme);
1698 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1701 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1708 jme_close(struct net_device *netdev)
1710 struct jme_adapter *jme = netdev_priv(netdev);
1712 netif_stop_queue(netdev);
1713 netif_carrier_off(netdev);
1718 JME_NAPI_DISABLE(jme);
1720 tasklet_disable(&jme->linkch_task);
1721 tasklet_disable(&jme->txclean_task);
1722 tasklet_disable(&jme->rxclean_task);
1723 tasklet_disable(&jme->rxempty_task);
1725 jme_reset_ghc_speed(jme);
1726 jme_disable_rx_engine(jme);
1727 jme_disable_tx_engine(jme);
1728 jme_reset_mac_processor(jme);
1729 jme_free_rx_resources(jme);
1730 jme_free_tx_resources(jme);
1738 jme_alloc_txdesc(struct jme_adapter *jme,
1739 struct sk_buff *skb)
1741 struct jme_ring *txring = &(jme->txring[0]);
1742 int idx, nr_alloc, mask = jme->tx_ring_mask;
1744 idx = txring->next_to_use;
1745 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1747 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1750 atomic_sub(nr_alloc, &txring->nr_free);
1752 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1758 jme_fill_tx_map(struct pci_dev *pdev,
1759 struct txdesc *txdesc,
1760 struct jme_buffer_info *txbi,
1768 dmaaddr = pci_map_page(pdev,
1774 pci_dma_sync_single_for_device(pdev,
1781 txdesc->desc2.flags = TXFLAG_OWN;
1782 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1783 txdesc->desc2.datalen = cpu_to_le16(len);
1784 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1785 txdesc->desc2.bufaddrl = cpu_to_le32(
1786 (__u64)dmaaddr & 0xFFFFFFFFUL);
1788 txbi->mapping = dmaaddr;
1793 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1795 struct jme_ring *txring = &(jme->txring[0]);
1796 struct txdesc *txdesc = txring->desc, *ctxdesc;
1797 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1798 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1799 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1800 int mask = jme->tx_ring_mask;
1801 struct skb_frag_struct *frag;
1804 for (i = 0 ; i < nr_frags ; ++i) {
1805 frag = &skb_shinfo(skb)->frags[i];
1806 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1807 ctxbi = txbi + ((idx + i + 2) & (mask));
1809 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1810 frag->page_offset, frag->size, hidma);
1813 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1814 ctxdesc = txdesc + ((idx + 1) & (mask));
1815 ctxbi = txbi + ((idx + 1) & (mask));
1816 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1817 offset_in_page(skb->data), len, hidma);
1822 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1825 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1826 skb_shinfo(skb)->tso_size
1828 skb_shinfo(skb)->gso_size
1830 && skb_header_cloned(skb) &&
1831 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1840 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1842 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1843 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1845 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1848 *flags |= TXFLAG_LSEN;
1850 if (skb->protocol == htons(ETH_P_IP)) {
1851 struct iphdr *iph = ip_hdr(skb);
1854 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1859 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1861 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1874 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1876 #ifdef CHECKSUM_PARTIAL
1877 if (skb->ip_summed == CHECKSUM_PARTIAL)
1879 if (skb->ip_summed == CHECKSUM_HW)
1884 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1885 if (skb->protocol == htons(ETH_P_IP))
1886 ip_proto = ip_hdr(skb)->protocol;
1887 else if (skb->protocol == htons(ETH_P_IPV6))
1888 ip_proto = ipv6_hdr(skb)->nexthdr;
1892 switch (skb->protocol) {
1893 case htons(ETH_P_IP):
1894 ip_proto = ip_hdr(skb)->protocol;
1896 case htons(ETH_P_IPV6):
1897 ip_proto = ipv6_hdr(skb)->nexthdr;
1907 *flags |= TXFLAG_TCPCS;
1910 *flags |= TXFLAG_UDPCS;
1913 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1920 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1922 if (vlan_tx_tag_present(skb)) {
1923 *flags |= TXFLAG_TAGON;
1924 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1929 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1931 struct jme_ring *txring = &(jme->txring[0]);
1932 struct txdesc *txdesc;
1933 struct jme_buffer_info *txbi;
1936 txdesc = (struct txdesc *)txring->desc + idx;
1937 txbi = txring->bufinf + idx;
1943 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1945 * Set OWN bit at final.
1946 * When kernel transmit faster than NIC.
1947 * And NIC trying to send this descriptor before we tell
1948 * it to start sending this TX queue.
1949 * Other fields are already filled correctly.
1952 flags = TXFLAG_OWN | TXFLAG_INT;
1954 * Set checksum flags while not tso
1956 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1957 jme_tx_csum(jme, skb, &flags);
1958 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1959 jme_map_tx_skb(jme, skb, idx);
1960 txdesc->desc1.flags = flags;
1962 * Set tx buffer info after telling NIC to send
1963 * For better tx_clean timing
1966 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1968 txbi->len = skb->len;
1969 txbi->start_xmit = jiffies;
1970 if (!txbi->start_xmit)
1971 txbi->start_xmit = (0UL-1);
1977 jme_stop_queue_if_full(struct jme_adapter *jme)
1979 struct jme_ring *txring = &(jme->txring[0]);
1980 struct jme_buffer_info *txbi = txring->bufinf;
1981 int idx = atomic_read(&txring->next_to_clean);
1986 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1987 netif_stop_queue(jme->dev);
1988 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1990 if (atomic_read(&txring->nr_free)
1991 >= (jme->tx_wake_threshold)) {
1992 netif_wake_queue(jme->dev);
1993 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1997 if (unlikely(txbi->start_xmit &&
1998 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2000 netif_stop_queue(jme->dev);
2001 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2006 * This function is already protected by netif_tx_lock()
2009 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2014 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2016 struct jme_adapter *jme = netdev_priv(netdev);
2019 if (unlikely(jme_expand_header(jme, skb))) {
2020 ++(NET_STAT(jme).tx_dropped);
2021 return NETDEV_TX_OK;
2024 idx = jme_alloc_txdesc(jme, skb);
2026 if (unlikely(idx < 0)) {
2027 netif_stop_queue(netdev);
2028 netif_err(jme, tx_err, jme->dev,
2029 "BUG! Tx ring full when queue awake!\n");
2031 return NETDEV_TX_BUSY;
2034 jme_fill_tx_desc(jme, skb, idx);
2036 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2037 TXCS_SELECT_QUEUE0 |
2040 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2041 netdev->trans_start = jiffies;
2044 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2045 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2046 jme_stop_queue_if_full(jme);
2048 return NETDEV_TX_OK;
2052 jme_set_macaddr(struct net_device *netdev, void *p)
2054 struct jme_adapter *jme = netdev_priv(netdev);
2055 struct sockaddr *addr = p;
2058 if (netif_running(netdev))
2061 spin_lock_bh(&jme->macaddr_lock);
2062 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2064 val = (addr->sa_data[3] & 0xff) << 24 |
2065 (addr->sa_data[2] & 0xff) << 16 |
2066 (addr->sa_data[1] & 0xff) << 8 |
2067 (addr->sa_data[0] & 0xff);
2068 jwrite32(jme, JME_RXUMA_LO, val);
2069 val = (addr->sa_data[5] & 0xff) << 8 |
2070 (addr->sa_data[4] & 0xff);
2071 jwrite32(jme, JME_RXUMA_HI, val);
2072 spin_unlock_bh(&jme->macaddr_lock);
2078 jme_set_multi(struct net_device *netdev)
2080 struct jme_adapter *jme = netdev_priv(netdev);
2081 u32 mc_hash[2] = {};
2082 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2086 spin_lock_bh(&jme->rxmcs_lock);
2088 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2090 if (netdev->flags & IFF_PROMISC) {
2091 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2092 } else if (netdev->flags & IFF_ALLMULTI) {
2093 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2094 } else if (netdev->flags & IFF_MULTICAST) {
2095 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2096 struct dev_mc_list *mclist;
2098 struct netdev_hw_addr *ha;
2102 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2103 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2104 for (i = 0, mclist = netdev->mc_list;
2105 mclist && i < netdev->mc_count;
2106 ++i, mclist = mclist->next) {
2107 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2108 netdev_for_each_mc_addr(mclist, netdev) {
2110 netdev_for_each_mc_addr(ha, netdev) {
2112 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2113 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2115 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2117 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2120 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2121 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2125 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2127 spin_unlock_bh(&jme->rxmcs_lock);
2131 jme_change_mtu(struct net_device *netdev, int new_mtu)
2133 struct jme_adapter *jme = netdev_priv(netdev);
2135 if (new_mtu == jme->old_mtu)
2138 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2139 ((new_mtu) < IPV6_MIN_MTU))
2142 if (new_mtu > 4000) {
2143 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2144 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2145 jme_restart_rx_engine(jme);
2147 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2148 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2149 jme_restart_rx_engine(jme);
2152 if (new_mtu > 1900) {
2153 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2154 NETIF_F_TSO | NETIF_F_TSO6);
2156 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2157 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2158 if (test_bit(JME_FLAG_TSO, &jme->flags))
2159 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2162 netdev->mtu = new_mtu;
2163 jme_reset_link(jme);
2169 jme_tx_timeout(struct net_device *netdev)
2171 struct jme_adapter *jme = netdev_priv(netdev);
2174 jme_reset_phy_processor(jme);
2175 if (test_bit(JME_FLAG_SSET, &jme->flags))
2176 jme_set_settings(netdev, &jme->old_ecmd);
2179 * Force to Reset the link again
2181 jme_reset_link(jme);
2184 static inline void jme_pause_rx(struct jme_adapter *jme)
2186 atomic_dec(&jme->link_changing);
2188 jme_set_rx_pcc(jme, PCC_OFF);
2189 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2190 JME_NAPI_DISABLE(jme);
2192 tasklet_disable(&jme->rxclean_task);
2193 tasklet_disable(&jme->rxempty_task);
2197 static inline void jme_resume_rx(struct jme_adapter *jme)
2199 struct dynpcc_info *dpi = &(jme->dpi);
2201 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2202 JME_NAPI_ENABLE(jme);
2204 tasklet_hi_enable(&jme->rxclean_task);
2205 tasklet_hi_enable(&jme->rxempty_task);
2208 dpi->attempt = PCC_P1;
2210 jme_set_rx_pcc(jme, PCC_P1);
2212 atomic_inc(&jme->link_changing);
2216 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2218 struct jme_adapter *jme = netdev_priv(netdev);
2225 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2227 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2229 struct jme_adapter *jme = netdev_priv(netdev);
2233 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2234 jme->vlgrp->vlan_devices[vid] = NULL;
2236 vlan_group_set_device(jme->vlgrp, vid, NULL);
2244 jme_get_drvinfo(struct net_device *netdev,
2245 struct ethtool_drvinfo *info)
2247 struct jme_adapter *jme = netdev_priv(netdev);
2249 strcpy(info->driver, DRV_NAME);
2250 strcpy(info->version, DRV_VERSION);
2251 strcpy(info->bus_info, pci_name(jme->pdev));
2255 jme_get_regs_len(struct net_device *netdev)
2261 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2265 for (i = 0 ; i < len ; i += 4)
2266 p[i >> 2] = jread32(jme, reg + i);
2270 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2273 u16 *p16 = (u16 *)p;
2275 for (i = 0 ; i < reg_nr ; ++i)
2276 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2280 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2282 struct jme_adapter *jme = netdev_priv(netdev);
2283 u32 *p32 = (u32 *)p;
2285 memset(p, 0xFF, JME_REG_LEN);
2288 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2291 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2294 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2297 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2300 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2304 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2306 struct jme_adapter *jme = netdev_priv(netdev);
2308 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2309 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2311 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2312 ecmd->use_adaptive_rx_coalesce = false;
2313 ecmd->rx_coalesce_usecs = 0;
2314 ecmd->rx_max_coalesced_frames = 0;
2318 ecmd->use_adaptive_rx_coalesce = true;
2320 switch (jme->dpi.cur) {
2322 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2323 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2326 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2327 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2330 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2331 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2341 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2343 struct jme_adapter *jme = netdev_priv(netdev);
2344 struct dynpcc_info *dpi = &(jme->dpi);
2346 if (netif_running(netdev))
2349 if (ecmd->use_adaptive_rx_coalesce &&
2350 test_bit(JME_FLAG_POLL, &jme->flags)) {
2351 clear_bit(JME_FLAG_POLL, &jme->flags);
2352 jme->jme_rx = netif_rx;
2353 jme->jme_vlan_rx = vlan_hwaccel_rx;
2355 dpi->attempt = PCC_P1;
2357 jme_set_rx_pcc(jme, PCC_P1);
2358 jme_interrupt_mode(jme);
2359 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2360 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2361 set_bit(JME_FLAG_POLL, &jme->flags);
2362 jme->jme_rx = netif_receive_skb;
2363 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2364 jme_interrupt_mode(jme);
2371 jme_get_pauseparam(struct net_device *netdev,
2372 struct ethtool_pauseparam *ecmd)
2374 struct jme_adapter *jme = netdev_priv(netdev);
2377 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2378 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2380 spin_lock_bh(&jme->phy_lock);
2381 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2382 spin_unlock_bh(&jme->phy_lock);
2385 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2389 jme_set_pauseparam(struct net_device *netdev,
2390 struct ethtool_pauseparam *ecmd)
2392 struct jme_adapter *jme = netdev_priv(netdev);
2395 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2396 (ecmd->tx_pause != 0)) {
2399 jme->reg_txpfc |= TXPFC_PF_EN;
2401 jme->reg_txpfc &= ~TXPFC_PF_EN;
2403 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2406 spin_lock_bh(&jme->rxmcs_lock);
2407 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2408 (ecmd->rx_pause != 0)) {
2411 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2413 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2415 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2417 spin_unlock_bh(&jme->rxmcs_lock);
2419 spin_lock_bh(&jme->phy_lock);
2420 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2421 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2422 (ecmd->autoneg != 0)) {
2425 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2427 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2429 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2430 MII_ADVERTISE, val);
2432 spin_unlock_bh(&jme->phy_lock);
2438 jme_get_wol(struct net_device *netdev,
2439 struct ethtool_wolinfo *wol)
2441 struct jme_adapter *jme = netdev_priv(netdev);
2443 wol->supported = WAKE_MAGIC | WAKE_PHY;
2447 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2448 wol->wolopts |= WAKE_PHY;
2450 if (jme->reg_pmcs & PMCS_MFEN)
2451 wol->wolopts |= WAKE_MAGIC;
2456 jme_set_wol(struct net_device *netdev,
2457 struct ethtool_wolinfo *wol)
2459 struct jme_adapter *jme = netdev_priv(netdev);
2461 if (wol->wolopts & (WAKE_MAGICSECURE |
2470 if (wol->wolopts & WAKE_PHY)
2471 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2473 if (wol->wolopts & WAKE_MAGIC)
2474 jme->reg_pmcs |= PMCS_MFEN;
2476 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2482 jme_get_settings(struct net_device *netdev,
2483 struct ethtool_cmd *ecmd)
2485 struct jme_adapter *jme = netdev_priv(netdev);
2488 spin_lock_bh(&jme->phy_lock);
2489 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2490 spin_unlock_bh(&jme->phy_lock);
2495 jme_set_settings(struct net_device *netdev,
2496 struct ethtool_cmd *ecmd)
2498 struct jme_adapter *jme = netdev_priv(netdev);
2501 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2505 * Check If user changed duplex only while force_media.
2506 * Hardware would not generate link change interrupt.
2508 if (jme->mii_if.force_media &&
2509 ecmd->autoneg != AUTONEG_ENABLE &&
2510 (jme->mii_if.full_duplex != ecmd->duplex))
2513 spin_lock_bh(&jme->phy_lock);
2514 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2515 spin_unlock_bh(&jme->phy_lock);
2519 jme_reset_link(jme);
2520 jme->old_ecmd = *ecmd;
2521 set_bit(JME_FLAG_SSET, &jme->flags);
2528 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2531 struct jme_adapter *jme = netdev_priv(netdev);
2532 struct mii_ioctl_data *mii_data = if_mii(rq);
2533 unsigned int duplex_chg;
2535 if (cmd == SIOCSMIIREG) {
2536 u16 val = mii_data->val_in;
2537 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2538 (val & BMCR_SPEED1000))
2542 spin_lock_bh(&jme->phy_lock);
2543 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2544 spin_unlock_bh(&jme->phy_lock);
2546 if (!rc && (cmd == SIOCSMIIREG)) {
2548 jme_reset_link(jme);
2549 jme_get_settings(netdev, &jme->old_ecmd);
2550 set_bit(JME_FLAG_SSET, &jme->flags);
2557 jme_get_link(struct net_device *netdev)
2559 struct jme_adapter *jme = netdev_priv(netdev);
2560 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2564 jme_get_msglevel(struct net_device *netdev)
2566 struct jme_adapter *jme = netdev_priv(netdev);
2567 return jme->msg_enable;
2571 jme_set_msglevel(struct net_device *netdev, u32 value)
2573 struct jme_adapter *jme = netdev_priv(netdev);
2574 jme->msg_enable = value;
2578 jme_get_rx_csum(struct net_device *netdev)
2580 struct jme_adapter *jme = netdev_priv(netdev);
2581 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2585 jme_set_rx_csum(struct net_device *netdev, u32 on)
2587 struct jme_adapter *jme = netdev_priv(netdev);
2589 spin_lock_bh(&jme->rxmcs_lock);
2591 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2593 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2594 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2595 spin_unlock_bh(&jme->rxmcs_lock);
2601 jme_set_tx_csum(struct net_device *netdev, u32 on)
2603 struct jme_adapter *jme = netdev_priv(netdev);
2606 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2607 if (netdev->mtu <= 1900)
2609 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2611 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2613 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2620 jme_set_tso(struct net_device *netdev, u32 on)
2622 struct jme_adapter *jme = netdev_priv(netdev);
2625 set_bit(JME_FLAG_TSO, &jme->flags);
2626 if (netdev->mtu <= 1900)
2627 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2629 clear_bit(JME_FLAG_TSO, &jme->flags);
2630 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2637 jme_nway_reset(struct net_device *netdev)
2639 struct jme_adapter *jme = netdev_priv(netdev);
2640 jme_restart_an(jme);
2645 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2650 val = jread32(jme, JME_SMBCSR);
2651 to = JME_SMB_BUSY_TIMEOUT;
2652 while ((val & SMBCSR_BUSY) && --to) {
2654 val = jread32(jme, JME_SMBCSR);
2657 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2661 jwrite32(jme, JME_SMBINTF,
2662 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2663 SMBINTF_HWRWN_READ |
2666 val = jread32(jme, JME_SMBINTF);
2667 to = JME_SMB_BUSY_TIMEOUT;
2668 while ((val & SMBINTF_HWCMD) && --to) {
2670 val = jread32(jme, JME_SMBINTF);
2673 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2677 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2681 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2686 val = jread32(jme, JME_SMBCSR);
2687 to = JME_SMB_BUSY_TIMEOUT;
2688 while ((val & SMBCSR_BUSY) && --to) {
2690 val = jread32(jme, JME_SMBCSR);
2693 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2697 jwrite32(jme, JME_SMBINTF,
2698 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2699 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2700 SMBINTF_HWRWN_WRITE |
2703 val = jread32(jme, JME_SMBINTF);
2704 to = JME_SMB_BUSY_TIMEOUT;
2705 while ((val & SMBINTF_HWCMD) && --to) {
2707 val = jread32(jme, JME_SMBINTF);
2710 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2718 jme_get_eeprom_len(struct net_device *netdev)
2720 struct jme_adapter *jme = netdev_priv(netdev);
2722 val = jread32(jme, JME_SMBCSR);
2723 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2727 jme_get_eeprom(struct net_device *netdev,
2728 struct ethtool_eeprom *eeprom, u8 *data)
2730 struct jme_adapter *jme = netdev_priv(netdev);
2731 int i, offset = eeprom->offset, len = eeprom->len;
2734 * ethtool will check the boundary for us
2736 eeprom->magic = JME_EEPROM_MAGIC;
2737 for (i = 0 ; i < len ; ++i)
2738 data[i] = jme_smb_read(jme, i + offset);
2744 jme_set_eeprom(struct net_device *netdev,
2745 struct ethtool_eeprom *eeprom, u8 *data)
2747 struct jme_adapter *jme = netdev_priv(netdev);
2748 int i, offset = eeprom->offset, len = eeprom->len;
2750 if (eeprom->magic != JME_EEPROM_MAGIC)
2754 * ethtool will check the boundary for us
2756 for (i = 0 ; i < len ; ++i)
2757 jme_smb_write(jme, i + offset, data[i]);
2762 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2763 static struct ethtool_ops jme_ethtool_ops = {
2765 static const struct ethtool_ops jme_ethtool_ops = {
2767 .get_drvinfo = jme_get_drvinfo,
2768 .get_regs_len = jme_get_regs_len,
2769 .get_regs = jme_get_regs,
2770 .get_coalesce = jme_get_coalesce,
2771 .set_coalesce = jme_set_coalesce,
2772 .get_pauseparam = jme_get_pauseparam,
2773 .set_pauseparam = jme_set_pauseparam,
2774 .get_wol = jme_get_wol,
2775 .set_wol = jme_set_wol,
2776 .get_settings = jme_get_settings,
2777 .set_settings = jme_set_settings,
2778 .get_link = jme_get_link,
2779 .get_msglevel = jme_get_msglevel,
2780 .set_msglevel = jme_set_msglevel,
2781 .get_rx_csum = jme_get_rx_csum,
2782 .set_rx_csum = jme_set_rx_csum,
2783 .set_tx_csum = jme_set_tx_csum,
2784 .set_tso = jme_set_tso,
2785 .set_sg = ethtool_op_set_sg,
2786 .nway_reset = jme_nway_reset,
2787 .get_eeprom_len = jme_get_eeprom_len,
2788 .get_eeprom = jme_get_eeprom,
2789 .set_eeprom = jme_set_eeprom,
2793 jme_pci_dma64(struct pci_dev *pdev)
2795 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2796 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2797 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2799 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2802 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2803 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2805 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2809 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2810 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2811 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2813 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2816 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2817 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2819 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2823 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2824 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2825 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2827 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2828 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2836 jme_phy_init(struct jme_adapter *jme)
2840 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2841 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2845 jme_check_hw_ver(struct jme_adapter *jme)
2849 chipmode = jread32(jme, JME_CHIPMODE);
2851 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2852 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2853 jme->chip_main_rev = jme->chiprev & 0xF;
2854 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2857 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2858 static const struct net_device_ops jme_netdev_ops = {
2859 .ndo_open = jme_open,
2860 .ndo_stop = jme_close,
2861 .ndo_validate_addr = eth_validate_addr,
2862 .ndo_do_ioctl = jme_ioctl,
2863 .ndo_start_xmit = jme_start_xmit,
2864 .ndo_set_mac_address = jme_set_macaddr,
2865 .ndo_set_multicast_list = jme_set_multi,
2866 .ndo_change_mtu = jme_change_mtu,
2867 .ndo_tx_timeout = jme_tx_timeout,
2868 .ndo_vlan_rx_register = jme_vlan_rx_register,
2872 static int __devinit
2873 jme_init_one(struct pci_dev *pdev,
2874 const struct pci_device_id *ent)
2876 int rc = 0, using_dac, i;
2877 struct net_device *netdev;
2878 struct jme_adapter *jme;
2883 * set up PCI device basics
2885 rc = pci_enable_device(pdev);
2887 pr_err("Cannot enable PCI device\n");
2891 using_dac = jme_pci_dma64(pdev);
2892 if (using_dac < 0) {
2893 pr_err("Cannot set PCI DMA Mask\n");
2895 goto err_out_disable_pdev;
2898 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2899 pr_err("No PCI resource region found\n");
2901 goto err_out_disable_pdev;
2904 rc = pci_request_regions(pdev, DRV_NAME);
2906 pr_err("Cannot obtain PCI resource region\n");
2907 goto err_out_disable_pdev;
2910 pci_set_master(pdev);
2913 * alloc and init net device
2915 netdev = alloc_etherdev(sizeof(*jme));
2917 pr_err("Cannot allocate netdev structure\n");
2919 goto err_out_release_regions;
2921 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2922 netdev->netdev_ops = &jme_netdev_ops;
2924 netdev->open = jme_open;
2925 netdev->stop = jme_close;
2926 netdev->do_ioctl = jme_ioctl;
2927 netdev->hard_start_xmit = jme_start_xmit;
2928 netdev->set_mac_address = jme_set_macaddr;
2929 netdev->set_multicast_list = jme_set_multi;
2930 netdev->change_mtu = jme_change_mtu;
2931 netdev->tx_timeout = jme_tx_timeout;
2932 netdev->vlan_rx_register = jme_vlan_rx_register;
2933 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2934 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2936 NETDEV_GET_STATS(netdev, &jme_get_stats);
2938 netdev->ethtool_ops = &jme_ethtool_ops;
2939 netdev->watchdog_timeo = TX_TIMEOUT;
2940 netdev->features = NETIF_F_IP_CSUM |
2945 NETIF_F_HW_VLAN_TX |
2948 netdev->features |= NETIF_F_HIGHDMA;
2950 SET_NETDEV_DEV(netdev, &pdev->dev);
2951 pci_set_drvdata(pdev, netdev);
2956 jme = netdev_priv(netdev);
2959 jme->jme_rx = netif_rx;
2960 jme->jme_vlan_rx = vlan_hwaccel_rx;
2961 jme->old_mtu = netdev->mtu = 1500;
2963 jme->tx_ring_size = 1 << 10;
2964 jme->tx_ring_mask = jme->tx_ring_size - 1;
2965 jme->tx_wake_threshold = 1 << 9;
2966 jme->rx_ring_size = 1 << 9;
2967 jme->rx_ring_mask = jme->rx_ring_size - 1;
2968 jme->msg_enable = JME_DEF_MSG_ENABLE;
2969 jme->regs = ioremap(pci_resource_start(pdev, 0),
2970 pci_resource_len(pdev, 0));
2972 pr_err("Mapping PCI resource region error\n");
2974 goto err_out_free_netdev;
2978 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2979 jwrite32(jme, JME_APMC, apmc);
2980 } else if (force_pseudohp) {
2981 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2982 jwrite32(jme, JME_APMC, apmc);
2985 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2987 spin_lock_init(&jme->phy_lock);
2988 spin_lock_init(&jme->macaddr_lock);
2989 spin_lock_init(&jme->rxmcs_lock);
2991 atomic_set(&jme->link_changing, 1);
2992 atomic_set(&jme->rx_cleaning, 1);
2993 atomic_set(&jme->tx_cleaning, 1);
2994 atomic_set(&jme->rx_empty, 1);
2996 tasklet_init(&jme->pcc_task,
2998 (unsigned long) jme);
2999 tasklet_init(&jme->linkch_task,
3000 jme_link_change_tasklet,
3001 (unsigned long) jme);
3002 tasklet_init(&jme->txclean_task,
3003 jme_tx_clean_tasklet,
3004 (unsigned long) jme);
3005 tasklet_init(&jme->rxclean_task,
3006 jme_rx_clean_tasklet,
3007 (unsigned long) jme);
3008 tasklet_init(&jme->rxempty_task,
3009 jme_rx_empty_tasklet,
3010 (unsigned long) jme);
3011 tasklet_disable_nosync(&jme->linkch_task);
3012 tasklet_disable_nosync(&jme->txclean_task);
3013 tasklet_disable_nosync(&jme->rxclean_task);
3014 tasklet_disable_nosync(&jme->rxempty_task);
3015 jme->dpi.cur = PCC_P1;
3018 jme->reg_rxcs = RXCS_DEFAULT;
3019 jme->reg_rxmcs = RXMCS_DEFAULT;
3021 jme->reg_pmcs = PMCS_MFEN;
3022 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3023 set_bit(JME_FLAG_TSO, &jme->flags);
3026 * Get Max Read Req Size from PCI Config Space
3028 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3029 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3030 switch (jme->mrrs) {
3032 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3035 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3038 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3043 * Must check before reset_mac_processor
3045 jme_check_hw_ver(jme);
3046 jme->mii_if.dev = netdev;
3048 jme->mii_if.phy_id = 0;
3049 for (i = 1 ; i < 32 ; ++i) {
3050 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3051 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3052 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3053 jme->mii_if.phy_id = i;
3058 if (!jme->mii_if.phy_id) {
3060 pr_err("Can not find phy_id\n");
3064 jme->reg_ghc |= GHC_LINK_POLL;
3066 jme->mii_if.phy_id = 1;
3068 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3069 jme->mii_if.supports_gmii = true;
3071 jme->mii_if.supports_gmii = false;
3072 jme->mii_if.phy_id_mask = 0x1F;
3073 jme->mii_if.reg_num_mask = 0x1F;
3074 jme->mii_if.mdio_read = jme_mdio_read;
3075 jme->mii_if.mdio_write = jme_mdio_write;
3078 jme_set_phyfifoa(jme);
3079 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3085 * Reset MAC processor and reload EEPROM for MAC Address
3087 jme_reset_mac_processor(jme);
3088 rc = jme_reload_eeprom(jme);
3090 pr_err("Reload eeprom for reading MAC Address error\n");
3093 jme_load_macaddr(netdev);
3096 * Tell stack that we are not ready to work until open()
3098 netif_carrier_off(netdev);
3100 rc = register_netdev(netdev);
3102 pr_err("Cannot register net device\n");
3106 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3107 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3108 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3109 "JMC250 Gigabit Ethernet" :
3110 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3111 "JMC260 Fast Ethernet" : "Unknown",
3112 (jme->fpgaver != 0) ? " (FPGA)" : "",
3113 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3115 netdev->dev_addr[0],
3116 netdev->dev_addr[1],
3117 netdev->dev_addr[2],
3118 netdev->dev_addr[3],
3119 netdev->dev_addr[4],
3120 netdev->dev_addr[5]);
3126 err_out_free_netdev:
3127 pci_set_drvdata(pdev, NULL);
3128 free_netdev(netdev);
3129 err_out_release_regions:
3130 pci_release_regions(pdev);
3131 err_out_disable_pdev:
3132 pci_disable_device(pdev);
3137 static void __devexit
3138 jme_remove_one(struct pci_dev *pdev)
3140 struct net_device *netdev = pci_get_drvdata(pdev);
3141 struct jme_adapter *jme = netdev_priv(netdev);
3143 unregister_netdev(netdev);
3145 pci_set_drvdata(pdev, NULL);
3146 free_netdev(netdev);
3147 pci_release_regions(pdev);
3148 pci_disable_device(pdev);
3153 jme_shutdown(struct pci_dev *pdev)
3155 struct net_device *netdev = pci_get_drvdata(pdev);
3156 struct jme_adapter *jme = netdev_priv(netdev);
3158 jme_powersave_phy(jme);
3159 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3160 pci_enable_wake(pdev, PCI_D3hot, true);
3162 pci_pme_active(pdev, true);
3168 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3170 struct net_device *netdev = pci_get_drvdata(pdev);
3171 struct jme_adapter *jme = netdev_priv(netdev);
3173 atomic_dec(&jme->link_changing);
3175 netif_device_detach(netdev);
3176 netif_stop_queue(netdev);
3179 tasklet_disable(&jme->txclean_task);
3180 tasklet_disable(&jme->rxclean_task);
3181 tasklet_disable(&jme->rxempty_task);
3183 if (netif_carrier_ok(netdev)) {
3184 if (test_bit(JME_FLAG_POLL, &jme->flags))
3185 jme_polling_mode(jme);
3187 jme_stop_pcc_timer(jme);
3188 jme_reset_ghc_speed(jme);
3189 jme_disable_rx_engine(jme);
3190 jme_disable_tx_engine(jme);
3191 jme_reset_mac_processor(jme);
3192 jme_free_rx_resources(jme);
3193 jme_free_tx_resources(jme);
3194 netif_carrier_off(netdev);
3198 tasklet_enable(&jme->txclean_task);
3199 tasklet_hi_enable(&jme->rxclean_task);
3200 tasklet_hi_enable(&jme->rxempty_task);
3202 pci_save_state(pdev);
3203 jme_powersave_phy(jme);
3204 pci_enable_wake(pdev, PCI_D3hot, true);
3205 pci_set_power_state(pdev, PCI_D3hot);
3211 jme_resume(struct pci_dev *pdev)
3213 struct net_device *netdev = pci_get_drvdata(pdev);
3214 struct jme_adapter *jme = netdev_priv(netdev);
3217 pci_restore_state(pdev);
3219 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3221 jme_set_settings(netdev, &jme->old_ecmd);
3223 jme_reset_phy_processor(jme);
3227 netif_device_attach(netdev);
3229 atomic_inc(&jme->link_changing);
3231 jme_reset_link(jme);
3237 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3238 static struct pci_device_id jme_pci_tbl[] = {
3240 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3242 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3243 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3247 static struct pci_driver jme_driver = {
3249 .id_table = jme_pci_tbl,
3250 .probe = jme_init_one,
3251 .remove = __devexit_p(jme_remove_one),
3253 .suspend = jme_suspend,
3254 .resume = jme_resume,
3255 #endif /* CONFIG_PM */
3256 .shutdown = jme_shutdown,
3260 jme_init_module(void)
3262 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3263 return pci_register_driver(&jme_driver);
3267 jme_cleanup_module(void)
3269 pci_unregister_driver(&jme_driver);
3272 module_init(jme_init_module);
3273 module_exit(jme_cleanup_module);
3275 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3276 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3277 MODULE_LICENSE("GPL");
3278 MODULE_VERSION(DRV_VERSION);
3279 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);