Import jme 0.4 source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/version.h>
25
26 #define DRV_NAME        "jme"
27 #define DRV_VERSION     "0.4"
28 #define PFX DRV_NAME    ": "
29
30 #ifdef DEBUG
31 #define dprintk(devname, fmt, args...) \
32         printk(KERN_DEBUG PFX "%s: " fmt, devname, ## args)
33 #else
34 #define dprintk(devname, fmt, args...)
35 #endif
36
37 #ifdef TX_DEBUG
38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
39 #else
40 #define tx_dbg(args...)
41 #endif
42
43 #ifdef RX_DEBUG
44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
45 #else
46 #define rx_dbg(args...)
47 #endif
48
49 #define jprintk(devname, fmt, args...) \
50         printk(KERN_INFO PFX "%s: " fmt, devname, ## args)
51
52 #define jeprintk(devname, fmt, args...) \
53         printk(KERN_ERR PFX "%s: " fmt, devname, ## args)
54
55 #define USE_IEVE_SHADOW 0
56
57 #define DEFAULT_MSG_ENABLE        \
58         (NETIF_MSG_DRV          | \
59          NETIF_MSG_PROBE        | \
60          NETIF_MSG_LINK         | \
61          NETIF_MSG_TIMER        | \
62          NETIF_MSG_RX_ERR       | \
63          NETIF_MSG_TX_ERR)
64
65 #define PCI_CONF_DCSR_MRRS      0x59
66 #define PCI_CONF_DCSR_MRRS_MASK 0x70
67 enum pci_conf_dcsr_mrrs_vals {
68         MRRS_128B       = 0x00,
69         MRRS_256B       = 0x10,
70         MRRS_512B       = 0x20,
71         MRRS_1024B      = 0x30,
72         MRRS_2048B      = 0x40,
73         MRRS_4096B      = 0x50,
74 };
75
76 enum dynamic_pcc_values {
77         PCC_P1          = 1,
78         PCC_P2          = 2,
79         PCC_P3          = 3,
80
81         PCC_P1_TO       = 1,
82         PCC_P2_TO       = 250,
83         PCC_P3_TO       = 1000,
84
85         PCC_P1_CNT      = 1,
86         PCC_P2_CNT      = 64,
87         PCC_P3_CNT      = 255,
88 };
89 struct dynpcc_info {
90         unsigned long   check_point;
91         unsigned long   last_bytes;
92         unsigned long   last_pkts;
93         unsigned char   cur;
94         unsigned char   attempt;
95         unsigned char   cnt;
96 };
97 #define PCC_INTERVAL (HZ / 10)
98 #define PCC_P3_THRESHOLD 3*1024*1024
99 #define PCC_P2_THRESHOLD 1000
100
101 /*
102  * TX/RX Descriptors
103  *
104  * TX/RX Ring DESC Count Must be multiple of 16
105  * RX Ring DESC Count Must be <= 1024
106  */
107 #define RING_DESC_NR            512     /* Must be power of 2 */
108 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
109
110 #define TX_DESC_SIZE            16
111 #define TX_RING_NR              8
112 #define TX_RING_ALLOC_SIZE      (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
113 #define TX_RING_SIZE            (RING_DESC_NR * TX_DESC_SIZE)
114
115 struct txdesc {
116         union {
117                 __u8  all[16];
118                 __u32 dw[4];
119                 struct {
120                         /* DW0 */
121                         __u16 vlan;
122                         __u8 rsv1;
123                         __u8 flags;
124
125                         /* DW1 */
126                         __u16 datalen;
127                         __u16 mss;
128
129                         /* DW2 */
130                         __u16 pktsize;
131                         __u16 rsv2;
132
133                         /* DW3 */
134                         __u32 bufaddr;
135                 } desc1;
136                 struct {
137                         /* DW0 */
138                         __u16 rsv1;
139                         __u8 rsv2;
140                         __u8 flags;
141
142                         /* DW1 */
143                         __u16 datalen;
144                         __u16 rsv3;
145
146                         /* DW2 */
147                         __u32 bufaddrh;
148
149                         /* DW3 */
150                         __u32 bufaddrl;
151                 } desc2;
152         };
153 };
154 enum jme_txdesc_flag_bits {
155         TXFLAG_OWN      = 0x80,
156         TXFLAG_INT      = 0x40,
157         TXFLAG_64BIT    = 0x20,
158         TXFLAG_TCPCS    = 0x10,
159         TXFLAG_UDPCS    = 0x08,
160         TXFLAG_IPCS     = 0x04,
161         TXFLAG_LSEN     = 0x02,
162         TXFLAG_TAGON    = 0x01,
163 };
164
165
166 #define RX_DESC_SIZE            16
167 #define RX_RING_NR              4
168 #define RX_RING_ALLOC_SIZE      (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
169 #define RX_RING_SIZE            (RING_DESC_NR * RX_DESC_SIZE)
170
171 #define RX_BUF_DMA_ALIGN        8
172 //#define RX_BUF_SIZE           1600
173 #define RX_BUF_SIZE             9200
174 //#define RX_BUF_SIZE           4000
175 #define RX_PREPAD_SIZE          10
176
177 /*
178  * Will use mtu in the future
179  */
180 #define RX_BUF_ALLOC_SIZE       RX_BUF_SIZE + RX_BUF_DMA_ALIGN
181
182 struct rxdesc {
183         union {
184                 __u8   all[16];
185                 __le32 dw[4];
186                 struct {
187                         /* DW0 */
188                         __le16 rsv2;
189                         __u8 rsv1;
190                         __u8 flags;
191
192                         /* DW1 */
193                         __le16 datalen;
194                         __le16 wbcpl;
195
196                         /* DW2 */
197                         __le32 bufaddrh;
198
199                         /* DW3 */
200                         __le32 bufaddrl;
201                 } desc1;
202                 struct {
203                         /* DW0 */
204                         __le16 vlan;
205                         __le16 flags;
206
207                         /* DW1 */
208                         __le16 framesize;
209                         __u8 errstat;
210                         __u8 desccnt;
211
212                         /* DW2 */
213                         __le32 rsshash;
214
215                         /* DW3 */
216                         __u8   hashfun;
217                         __u8   hashtype;
218                         __le16 resrv;
219                 } descwb;
220         };
221 };
222 enum jme_rxdesc_flags_bits {
223         RXFLAG_OWN      = 0x80,
224         RXFLAG_INT      = 0x40,
225         RXFLAG_64BIT    = 0x20,
226 };
227 enum jme_rxwbdesc_flags_bits {
228         RXWBFLAG_OWN            = 0x8000,
229         RXWBFLAG_INT            = 0x4000,
230         RXWBFLAG_MF             = 0x2000,
231         RXWBFLAG_64BIT          = 0x2000,
232         RXWBFLAG_TCPON          = 0x1000,
233         RXWBFLAG_UDPON          = 0x0800,
234         RXWBFLAG_IPCS           = 0x0400,
235         RXWBFLAG_TCPCS          = 0x0200,
236         RXWBFLAG_UDPCS          = 0x0100,
237         RXWBFLAG_TAGON          = 0x0080,
238         RXWBFLAG_IPV4           = 0x0040,
239         RXWBFLAG_IPV6           = 0x0020,
240         RXWBFLAG_PAUSE          = 0x0010,
241         RXWBFLAG_MAGIC          = 0x0008,
242         RXWBFLAG_WAKEUP         = 0x0004,
243         RXWBFLAG_DEST           = 0x0003,
244         RXWBFLAG_DEST_UNI       = 0x0001,
245         RXWBFLAG_DEST_MUL       = 0x0002,
246         RXWBFLAG_DEST_BRO       = 0x0003,
247 };
248 enum jme_rxwbdesc_desccnt_mask {
249         RXWBDCNT_WBCPL  = 0x80,
250         RXWBDCNT_DCNT   = 0x7F,
251 };
252 enum jme_rxwbdesc_errstat_bits {
253         RXWBERR_LIMIT   = 0x80,
254         RXWBERR_MIIER   = 0x40,
255         RXWBERR_NIBON   = 0x20,
256         RXWBERR_COLON   = 0x10,
257         RXWBERR_ABORT   = 0x08,
258         RXWBERR_SHORT   = 0x04,
259         RXWBERR_OVERUN  = 0x02,
260         RXWBERR_CRCERR  = 0x01,
261         RXWBERR_ALLERR  = 0xFF,
262 };
263
264 struct jme_buffer_info {
265         struct sk_buff *skb;
266         dma_addr_t mapping;
267         int len;
268         int nr_desc;
269 };
270
271 struct jme_ring {
272         void* alloc;            /* pointer to allocated memory */
273         volatile void* desc;    /* pointer to ring memory  */
274         dma_addr_t dmaalloc;    /* phys address of ring alloc */
275         dma_addr_t dma;         /* phys address for ring dma */
276
277         /* Buffer information corresponding to each descriptor */
278         struct jme_buffer_info bufinf[RING_DESC_NR];
279
280         u16 next_to_use;
281         u16 next_to_clean;
282
283         u16 nr_free;
284 };
285
286 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
287 #define NET_STAT(priv) priv->stats
288 #define NETDEV_GET_STATS(netdev, fun_ptr) \
289         netdev->get_stats = fun_ptr
290 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
291 #else
292 #define NET_STAT(priv) priv->dev->stats
293 #define NETDEV_GET_STATS(netdev, fun_ptr)
294 #define DECLARE_NET_DEVICE_STATS
295 #endif
296
297 /*
298  * Jmac Adapter Private data
299  */
300 #define SHADOW_REG_NR 8
301 struct jme_adapter {
302         struct pci_dev          *pdev;
303         struct net_device       *dev;
304         void __iomem            *regs;
305         dma_addr_t              shadow_dma;
306         __u32                   *shadow_regs;
307         struct mii_if_info      mii_if;
308         struct jme_ring         rxring[RX_RING_NR];
309         struct jme_ring         txring[TX_RING_NR];
310         spinlock_t              tx_lock;
311         spinlock_t              phy_lock;
312         spinlock_t              macaddr_lock;
313         struct tasklet_struct   rxempty_task;
314         struct tasklet_struct   rxclean_task;
315         struct tasklet_struct   txclean_task;
316         struct tasklet_struct   linkch_task;
317         __u32                   reg_txcs;
318         __u32                   reg_rxmcs;
319         __u32                   reg_ghc;
320         __u32                   phylink;
321         __u8                    mrrs;
322         struct dynpcc_info      dpi;
323         atomic_t                intr_sem;
324         atomic_t                link_changing;
325         atomic_t                tx_cleaning;
326         atomic_t                rx_cleaning;
327         DECLARE_NET_DEVICE_STATS
328 };
329 enum shadow_reg_val {
330         SHADOW_IEVE = 0,
331 };
332 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
333
334 /*
335  * MMaped I/O Resters
336  */
337 enum jme_iomap_offsets {
338         JME_MAC         = 0x0000,
339         JME_PHY         = 0x0400,
340         JME_MISC        = 0x0800,
341         JME_RSS         = 0x0C00,
342 };
343
344 enum jme_iomap_regs {
345         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
346         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
347         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
348         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
349         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
350         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
351         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
352         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
353
354         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
355         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
356         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
357         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
358         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
359         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
360         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
361         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
362         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
363         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
364         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
365         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
366
367         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
368         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
369         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
370
371
372         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
373         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
374         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
375
376
377         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
378         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
379         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
380         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
381         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
382         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
383         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
384         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
385         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
386         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
387         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
388 };
389
390 /*
391  * TX Control/Status Bits
392  */
393 enum jme_txcs_bits {
394         TXCS_QUEUE7S    = 0x00008000,
395         TXCS_QUEUE6S    = 0x00004000,
396         TXCS_QUEUE5S    = 0x00002000,
397         TXCS_QUEUE4S    = 0x00001000,
398         TXCS_QUEUE3S    = 0x00000800,
399         TXCS_QUEUE2S    = 0x00000400,
400         TXCS_QUEUE1S    = 0x00000200,
401         TXCS_QUEUE0S    = 0x00000100,
402         TXCS_FIFOTH     = 0x000000C0,
403         TXCS_DMASIZE    = 0x00000030,
404         TXCS_BURST      = 0x00000004,
405         TXCS_ENABLE     = 0x00000001,
406 };
407 enum jme_txcs_value {
408         TXCS_FIFOTH_16QW        = 0x000000C0,
409         TXCS_FIFOTH_12QW        = 0x00000080,
410         TXCS_FIFOTH_8QW         = 0x00000040,
411         TXCS_FIFOTH_4QW         = 0x00000000,
412
413         TXCS_DMASIZE_64B        = 0x00000000,
414         TXCS_DMASIZE_128B       = 0x00000010,
415         TXCS_DMASIZE_256B       = 0x00000020,
416         TXCS_DMASIZE_512B       = 0x00000030,
417
418         TXCS_SELECT_QUEUE0      = 0x00000000,
419         TXCS_SELECT_QUEUE1      = 0x00010000,
420         TXCS_SELECT_QUEUE2      = 0x00020000,
421         TXCS_SELECT_QUEUE3      = 0x00030000,
422         TXCS_SELECT_QUEUE4      = 0x00040000,
423         TXCS_SELECT_QUEUE5      = 0x00050000,
424         TXCS_SELECT_QUEUE6      = 0x00060000,
425         TXCS_SELECT_QUEUE7      = 0x00070000,
426
427         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
428                                   TXCS_BURST,
429 };
430 #define JME_TX_DISABLE_TIMEOUT 100 /* 100 msec */
431
432 /*
433  * TX MAC Control/Status Bits
434  */
435 enum jme_txmcs_bit_masks {
436         TXMCS_IFG2              = 0xC0000000,
437         TXMCS_IFG1              = 0x30000000,
438         TXMCS_TTHOLD            = 0x00000300,
439         TXMCS_FBURST            = 0x00000080,
440         TXMCS_CARRIEREXT        = 0x00000040,
441         TXMCS_DEFER             = 0x00000020,
442         TXMCS_BACKOFF           = 0x00000010,
443         TXMCS_CARRIERSENSE      = 0x00000008,
444         TXMCS_COLLISION         = 0x00000004,
445         TXMCS_CRC               = 0x00000002,
446         TXMCS_PADDING           = 0x00000001,
447 };
448 enum jme_txmcs_values {
449         TXMCS_IFG2_6_4          = 0x00000000,
450         TXMCS_IFG2_8_5          = 0x40000000,
451         TXMCS_IFG2_10_6         = 0x80000000,
452         TXMCS_IFG2_12_7         = 0xC0000000,
453
454         TXMCS_IFG1_8_4          = 0x00000000,
455         TXMCS_IFG1_12_6         = 0x10000000,
456         TXMCS_IFG1_16_8         = 0x20000000,
457         TXMCS_IFG1_20_10        = 0x30000000,
458
459         TXMCS_TTHOLD_1_8        = 0x00000000,
460         TXMCS_TTHOLD_1_4        = 0x00000100,
461         TXMCS_TTHOLD_1_2        = 0x00000200,
462         TXMCS_TTHOLD_FULL       = 0x00000300,
463
464         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
465                                   TXMCS_IFG1_16_8 |
466                                   TXMCS_TTHOLD_FULL |
467                                   TXMCS_DEFER |
468                                   TXMCS_CRC |
469                                   TXMCS_PADDING,
470 };
471
472
473 /*
474  * RX Control/Status Bits
475  */
476 enum jme_rxcs_bit_masks {
477         /* FIFO full threshold for transmitting Tx Pause Packet */
478         RXCS_FIFOTHTP   = 0x30000000,
479         /* FIFO threshold for processing next packet */
480         RXCS_FIFOTHNP   = 0x0C000000,
481         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
482         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
483         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
484         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
485         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
486         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
487         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
488         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
489         RXCS_QST        = 0x00000004, /* Receive queue start */
490         RXCS_SUSPEND    = 0x00000002,
491         RXCS_ENABLE     = 0x00000001,
492 };
493 enum jme_rxcs_values {
494         RXCS_FIFOTHTP_16T       = 0x00000000,
495         RXCS_FIFOTHTP_32T       = 0x10000000,
496         RXCS_FIFOTHTP_64T       = 0x20000000,
497         RXCS_FIFOTHTP_128T      = 0x30000000,
498
499         RXCS_FIFOTHNP_16QW      = 0x00000000,
500         RXCS_FIFOTHNP_32QW      = 0x04000000,
501         RXCS_FIFOTHNP_64QW      = 0x08000000,
502         RXCS_FIFOTHNP_128QW     = 0x0C000000,
503
504         RXCS_DMAREQSZ_16B       = 0x00000000,
505         RXCS_DMAREQSZ_32B       = 0x01000000,
506         RXCS_DMAREQSZ_64B       = 0x02000000,
507         RXCS_DMAREQSZ_128B      = 0x03000000,
508
509         RXCS_QUEUESEL_Q0        = 0x00000000,
510         RXCS_QUEUESEL_Q1        = 0x00010000,
511         RXCS_QUEUESEL_Q2        = 0x00020000,
512         RXCS_QUEUESEL_Q3        = 0x00030000,
513
514         RXCS_RETRYGAP_256ns     = 0x00000000,
515         RXCS_RETRYGAP_512ns     = 0x00001000,
516         RXCS_RETRYGAP_1024ns    = 0x00002000,
517         RXCS_RETRYGAP_2048ns    = 0x00003000,
518         RXCS_RETRYGAP_4096ns    = 0x00004000,
519         RXCS_RETRYGAP_8192ns    = 0x00005000,
520         RXCS_RETRYGAP_16384ns   = 0x00006000,
521         RXCS_RETRYGAP_32768ns   = 0x00007000,
522
523         RXCS_RETRYCNT_0         = 0x00000000,
524         RXCS_RETRYCNT_4         = 0x00000100,
525         RXCS_RETRYCNT_8         = 0x00000200,
526         RXCS_RETRYCNT_12        = 0x00000300,
527         RXCS_RETRYCNT_16        = 0x00000400,
528         RXCS_RETRYCNT_20        = 0x00000500,
529         RXCS_RETRYCNT_24        = 0x00000600,
530         RXCS_RETRYCNT_28        = 0x00000700,
531         RXCS_RETRYCNT_32        = 0x00000800,
532         RXCS_RETRYCNT_36        = 0x00000900,
533         RXCS_RETRYCNT_40        = 0x00000A00,
534         RXCS_RETRYCNT_44        = 0x00000B00,
535         RXCS_RETRYCNT_48        = 0x00000C00,
536         RXCS_RETRYCNT_52        = 0x00000D00,
537         RXCS_RETRYCNT_56        = 0x00000E00,
538         RXCS_RETRYCNT_60        = 0x00000F00,
539
540         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
541                                   RXCS_FIFOTHNP_128QW |
542                                   RXCS_DMAREQSZ_128B |
543                                   RXCS_RETRYGAP_256ns |
544                                   RXCS_RETRYCNT_32,
545 };
546 #define JME_RX_DISABLE_TIMEOUT 100 /* 100 msec */
547
548 /*
549  * RX MAC Control/Status Bits
550  */
551 enum jme_rxmcs_bits {
552         RXMCS_ALLFRAME          = 0x00000800,
553         RXMCS_BRDFRAME          = 0x00000400,
554         RXMCS_MULFRAME          = 0x00000200,
555         RXMCS_UNIFRAME          = 0x00000100,
556         RXMCS_ALLMULFRAME       = 0x00000080,
557         RXMCS_MULFILTERED       = 0x00000040,
558         RXMCS_RXCOLLDEC         = 0x00000020,
559         RXMCS_FLOWCTRL          = 0x00000008,
560         RXMCS_VTAGRM            = 0x00000004,
561         RXMCS_PREPAD            = 0x00000002,
562         RXMCS_CHECKSUM          = 0x00000001,
563 };
564
565 /*
566  * SMI Related definitions
567  */
568 enum jme_smi_bit_mask
569 {
570         SMI_DATA_MASK           = 0xFFFF0000,
571         SMI_REG_ADDR_MASK       = 0x0000F800,
572         SMI_PHY_ADDR_MASK       = 0x000007C0,
573         SMI_OP_WRITE            = 0x00000020,
574         /* Set to 1, after req done it'll be cleared to 0 */
575         SMI_OP_REQ              = 0x00000010,
576         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
577         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
578         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
579         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
580 };
581 enum jme_smi_bit_shift
582 {
583         SMI_DATA_SHIFT          = 16,
584         SMI_REG_ADDR_SHIFT      = 11,
585         SMI_PHY_ADDR_SHIFT      = 6,
586 };
587 __always_inline __u32 smi_reg_addr(int x)
588 {
589         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
590 }
591 __always_inline __u32 smi_phy_addr(int x)
592 {
593         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
594 }
595 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
596
597 /*
598  * Global Host Control
599  */
600 enum jme_ghc_bit_mask {
601         GHC_SWRST       = 0x40000000,
602         GHC_DPX         = 0x00000040,
603         GHC_SPEED       = 0x00000030,
604         GHC_LINK_POLL   = 0x00000001,
605 };
606 enum jme_ghc_speed_val {
607         GHC_SPEED_10M   = 0x00000010,
608         GHC_SPEED_100M  = 0x00000020,
609         GHC_SPEED_1000M = 0x00000030,
610 };
611
612 /*
613  * Giga PHY Status Registers
614  */
615 enum jme_phy_link_bit_mask {
616         PHY_LINK_SPEED_MASK             = 0x0000C000,
617         PHY_LINK_DUPLEX                 = 0x00002000,
618         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
619         PHY_LINK_UP                     = 0x00000400,
620         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
621         PHY_LINK_MDI_STAT               = 0x00000040,
622 };
623 enum jme_phy_link_speed_val {
624         PHY_LINK_SPEED_10M              = 0x00000000,
625         PHY_LINK_SPEED_100M             = 0x00004000,
626         PHY_LINK_SPEED_1000M            = 0x00008000,
627 };
628 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
629
630 /*
631  * SMB Control and Status
632  */
633 enum jme_smbcsr_bit_mask
634 {
635         SMBCSR_CNACK    = 0x00020000,
636         SMBCSR_RELOAD   = 0x00010000,
637         SMBCSR_EEPROMD  = 0x00000020,
638 };
639 #define JME_SMB_TIMEOUT 10 /* 10 msec */
640
641
642 /*
643  * General Purpost REG-0
644  */
645 enum jme_gpreg0_masks {
646         GPREG0_DISSH            = 0xFF000000,
647         GPREG0_PCIRLMT          = 0x00300000,
648         GPREG0_PCCNOMUTCLR      = 0x00040000,
649         GPREG0_PCCTMR           = 0x00000300,
650         GPREG0_PHYADDR          = 0x0000001F,
651 };
652 enum jme_gpreg0_vals {
653         GPREG0_DISSH_DW7        = 0x80000000,
654         GPREG0_DISSH_DW6        = 0x40000000,
655         GPREG0_DISSH_DW5        = 0x20000000,
656         GPREG0_DISSH_DW4        = 0x10000000,
657         GPREG0_DISSH_DW3        = 0x08000000,
658         GPREG0_DISSH_DW2        = 0x04000000,
659         GPREG0_DISSH_DW1        = 0x02000000,
660         GPREG0_DISSH_DW0        = 0x01000000,
661         GPREG0_DISSH_ALL        = 0xFF000000,
662
663         GPREG0_PCIRLMT_8        = 0x00000000,
664         GPREG0_PCIRLMT_6        = 0x00100000,
665         GPREG0_PCIRLMT_5        = 0x00200000,
666         GPREG0_PCIRLMT_4        = 0x00300000,
667
668         GPREG0_PCCTMR_16ns      = 0x00000000,
669         GPREG0_PCCTMR_256ns     = 0x00000100,
670         GPREG0_PCCTMR_1us       = 0x00000200,
671         GPREG0_PCCTMR_1ms       = 0x00000300,
672
673         GPREG0_PHYADDR_1        = 0x00000001,
674
675         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
676                                   GPREG0_PCCNOMUTCLR |
677                                   GPREG0_PCCTMR_1us |
678                                   GPREG0_PHYADDR_1,
679 };
680
681 /*
682  * Interrupt Status Bits
683  */
684 enum jme_interrupt_bits
685 {
686         INTR_SWINTR     = 0x80000000,
687         INTR_TMINTR     = 0x40000000,
688         INTR_LINKCH     = 0x20000000,
689         INTR_PAUSERCV   = 0x10000000,
690         INTR_MAGICRCV   = 0x08000000,
691         INTR_WAKERCV    = 0x04000000,
692         INTR_PCCRX0TO   = 0x02000000,
693         INTR_PCCRX1TO   = 0x01000000,
694         INTR_PCCRX2TO   = 0x00800000,
695         INTR_PCCRX3TO   = 0x00400000,
696         INTR_PCCTXTO    = 0x00200000,
697         INTR_PCCRX0     = 0x00100000,
698         INTR_PCCRX1     = 0x00080000,
699         INTR_PCCRX2     = 0x00040000,
700         INTR_PCCRX3     = 0x00020000,
701         INTR_PCCTX      = 0x00010000,
702         INTR_RX3EMP     = 0x00008000,
703         INTR_RX2EMP     = 0x00004000,
704         INTR_RX1EMP     = 0x00002000,
705         INTR_RX0EMP     = 0x00001000,
706         INTR_RX3        = 0x00000800,
707         INTR_RX2        = 0x00000400,
708         INTR_RX1        = 0x00000200,
709         INTR_RX0        = 0x00000100,
710         INTR_TX7        = 0x00000080,
711         INTR_TX6        = 0x00000040,
712         INTR_TX5        = 0x00000020,
713         INTR_TX4        = 0x00000010,
714         INTR_TX3        = 0x00000008,
715         INTR_TX2        = 0x00000004,
716         INTR_TX1        = 0x00000002,
717         INTR_TX0        = 0x00000001,
718 };
719 static const __u32 INTR_ENABLE = INTR_LINKCH |
720                                  INTR_RX0EMP |
721                                  INTR_PCCRX0TO |
722                                  INTR_PCCRX0 |
723                                  INTR_PCCTXTO |
724                                  INTR_PCCTX;
725
726 /*
727  * PCC Control Registers
728  */
729 enum jme_pccrx_masks {
730         PCCRXTO_MASK    = 0xFFFF0000,
731         PCCRX_MASK      = 0x0000FF00,
732 };
733 enum jme_pcctx_masks {
734         PCCTXTO_MASK    = 0xFFFF0000,
735         PCCTX_MASK      = 0x0000FF00,
736         PCCTX_QS_MASK   = 0x000000FF,
737 };
738 enum jme_pccrx_shifts {
739         PCCRXTO_SHIFT   = 16,
740         PCCRX_SHIFT     = 8,
741 };
742 enum jme_pcctx_shifts {
743         PCCTXTO_SHIFT   = 16,
744         PCCTX_SHIFT     = 8,
745 };
746 enum jme_pcctx_bits {
747         PCCTXQ0_EN      = 0x00000001,
748         PCCTXQ1_EN      = 0x00000002,
749         PCCTXQ2_EN      = 0x00000004,
750         PCCTXQ3_EN      = 0x00000008,
751         PCCTXQ4_EN      = 0x00000010,
752         PCCTXQ5_EN      = 0x00000020,
753         PCCTXQ6_EN      = 0x00000040,
754         PCCTXQ7_EN      = 0x00000080,
755 };
756
757
758 /*
759  * Shadow base address register bits
760  */
761 enum jme_shadow_base_address_bits {
762         SHBA_POSTEN     = 0x1,
763 };
764
765 /*
766  * Read/Write MMaped I/O Registers
767  */
768 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
769 {
770         return le32_to_cpu(readl(jme->regs + reg));
771 }
772 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
773 {
774         writel(cpu_to_le32(val), jme->regs + reg);
775 }
776 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
777 {
778         /*
779          * Read after write should cause flush
780          */
781         writel(cpu_to_le32(val), jme->regs + reg);
782         readl(jme->regs + reg);
783 }
784
785 /*
786  * Function prototypes for ethtool
787  */
788 static void jme_get_drvinfo(struct net_device *netdev,
789                              struct ethtool_drvinfo *info);
790 static int jme_get_settings(struct net_device *netdev,
791                              struct ethtool_cmd *ecmd);
792 static int jme_set_settings(struct net_device *netdev,
793                              struct ethtool_cmd *ecmd);
794 static u32 jme_get_link(struct net_device *netdev);
795
796
797 /*
798  * Function prototypes for netdev
799  */
800 static int jme_open(struct net_device *netdev);
801 static int jme_close(struct net_device *netdev);
802 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
803 static int jme_set_macaddr(struct net_device *netdev, void *p);
804 static void jme_set_multi(struct net_device *netdev);
805
806