jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #ifndef __JME_H_INCLUDED__
  26 #define __JME_H_INCLUDED__
  27 #include <linux/interrupt.h>
  28
  29 #define DRV_NAME        "jme"
  30 #define DRV_VERSION     "1.0.8.2-jmmod"
  31 #define PFX             DRV_NAME ": "
  32
  33 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  34 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  35
  36 /*
  37  * Message related definitions
  38  */
  39 #define JME_DEF_MSG_ENABLE \
  40         (NETIF_MSG_PROBE | \
  41         NETIF_MSG_LINK | \
  42         NETIF_MSG_RX_ERR | \
  43         NETIF_MSG_TX_ERR | \
  44         NETIF_MSG_HW)
  45
  46 #ifndef pr_err
  47 #define pr_err(fmt, arg...) \
  48         printk(KERN_ERR fmt, ##arg)
  49 #endif
  50 #ifndef netdev_err
  51 #define netdev_err(netdev, fmt, arg...) \
  52         pr_err(fmt, ##arg)
  53 #endif
  54
  55 #ifdef TX_DEBUG
  56 #define tx_dbg(priv, fmt, args...)                                      \
  57         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  58 #else
  59 #define tx_dbg(priv, fmt, args...)                                      \
  60 do {                                                                    \
  61         if (0)                                                          \
  62                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  63 } while (0)
  64 #endif
  65
  66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  67 #define jme_msg(msglvl, type, priv, fmt, args...) \
  68         if (netif_msg_##type(priv)) \
  69                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
  70
  71 #define msg_probe(priv, fmt, args...) \
  72         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
  73
  74 #define msg_link(priv, fmt, args...) \
  75         jme_msg(KERN_INFO, link, priv, fmt, ## args)
  76
  77 #define msg_intr(priv, fmt, args...) \
  78         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
  79
  80 #define msg_rx_err(priv, fmt, args...) \
  81         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
  82
  83 #define msg_rx_status(priv, fmt, args...) \
  84         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
  85
  86 #define msg_tx_err(priv, fmt, args...) \
  87         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
  88
  89 #define msg_tx_done(priv, fmt, args...) \
  90         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
  91
  92 #define msg_tx_queued(priv, fmt, args...) \
  93         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
  94
  95 #define msg_hw(priv, fmt, args...) \
  96         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
  97
  98 #ifndef netif_info
  99 #define netif_info(priv, type, dev, fmt, args...) \
 100         msg_ ## type(priv, fmt, ## args)
 101 #endif
 102 #ifndef netif_err
 103 #define netif_err(priv, type, dev, fmt, args...) \
 104         msg_ ## type(priv, fmt, ## args)
 105 #endif
 106 #endif
 107
 108 #ifndef NETIF_F_TSO6
 109 #define NETIF_F_TSO6 0
 110 #endif
 111 #ifndef NETIF_F_IPV6_CSUM
 112 #define NETIF_F_IPV6_CSUM 0
 113 #endif
 114
 115 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
 116 #define __USE_NDO_FIX_FEATURES__
 117 #endif
 118
 119 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,1,0)
 120 #define __UNIFY_VLAN_RX_PATH__
 121 #define __USE_NDO_SET_RX_MODE__
 122 #endif
 123
 124 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
 125 #define __USE_SKB_FRAG_API__
 126 #endif
 127
 128 /*
 129  * Extra PCI Configuration space interface
 130  */
 131 #define PCI_DCSR_MRRS           0x59
 132 #define PCI_DCSR_MRRS_MASK      0x70
 133
 134 enum pci_dcsr_mrrs_vals {
 135         MRRS_128B       = 0x00,
 136         MRRS_256B       = 0x10,
 137         MRRS_512B       = 0x20,
 138         MRRS_1024B      = 0x30,
 139         MRRS_2048B      = 0x40,
 140         MRRS_4096B      = 0x50,
 141 };
 142
 143 #define PCI_SPI                 0xB0
 144
 145 enum pci_spi_bits {
 146         SPI_EN          = 0x10,
 147         SPI_MISO        = 0x08,
 148         SPI_MOSI        = 0x04,
 149         SPI_SCLK        = 0x02,
 150         SPI_CS          = 0x01,
 151 };
 152
 153 struct jme_spi_op {
 154         void __user *uwbuf;
 155         void __user *urbuf;
 156         __u8    wn;     /* Number of write actions */
 157         __u8    rn;     /* Number of read actions */
 158         __u8    bitn;   /* Number of bits per action */
 159         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
 160         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
 161
 162         /* Internal use only */
 163         u8      *kwbuf;
 164         u8      *krbuf;
 165         u8      sr;
 166         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
 167 };
 168
 169 enum jme_spi_op_bits {
 170         SPI_MODE_CPHA   = 0x01,
 171         SPI_MODE_CPOL   = 0x02,
 172         SPI_MODE_DUP    = 0x80,
 173 };
 174
 175 #define HALF_US 500     /* 500 ns */
 176
 177 #define PCI_PRIV_PE1            0xE4
 178
 179 enum pci_priv_pe1_bit_masks {
 180         PE1_ASPMSUPRT   = 0x00000003, /*
 181                                        * RW:
 182                                        * Aspm_support[1:0]
 183                                        * (R/W Port of 5C[11:10])
 184                                        */
 185         PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
 186         PE1_RDYDMA      = 0x00000008, /* RO: ~link.rdy_for_dma */
 187         PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
 188         PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
 189         PE1_GPREG0      = 0x0000FF00, /*
 190                                        * SRW:
 191                                        * Cfg_gp_reg0
 192                                        * [7:6] phy_giga BG control
 193                                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
 194                                        * [4:0] Reserved
 195                                        */
 196         PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
 197         PE1_GPREG1      = 0x00FF0000, /* RW: Cfg_gp_reg1 */
 198         PE1_REVID       = 0xFF000000, /* RO: Rev ID */
 199 };
 200
 201 enum pci_priv_pe1_values {
 202         PE1_GPREG0_ENBG         = 0x00000000, /* en BG */
 203         PE1_GPREG0_PDD3COLD     = 0x00004000, /* giga_PD + d3cold */
 204         PE1_GPREG0_PDPCIESD     = 0x00008000, /* giga_PD + pcie_shutdown */
 205         PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
 206 };
 207
 208 /*
 209  * Dynamic(adaptive)/Static PCC values
 210  */
 211 enum dynamic_pcc_values {
 212         PCC_OFF         = 0,
 213         PCC_P1          = 1,
 214         PCC_P2          = 2,
 215         PCC_P3          = 3,
 216
 217         PCC_OFF_TO      = 0,
 218         PCC_P1_TO       = 1,
 219         PCC_P2_TO       = 64,
 220         PCC_P3_TO       = 128,
 221
 222         PCC_OFF_CNT     = 0,
 223         PCC_P1_CNT      = 1,
 224         PCC_P2_CNT      = 16,
 225         PCC_P3_CNT      = 32,
 226 };
 227 struct dynpcc_info {
 228         unsigned long   last_bytes;
 229         unsigned long   last_pkts;
 230         unsigned long   intr_cnt;
 231         unsigned char   cur;
 232         unsigned char   attempt;
 233         unsigned char   cnt;
 234 };
 235 #define PCC_INTERVAL_US 100000
 236 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 237 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 238 #define PCC_P2_THRESHOLD 800
 239 #define PCC_INTR_THRESHOLD 800
 240 #define PCC_TX_TO 1000
 241 #define PCC_TX_CNT 8
 242
 243 /*
 244  * TX/RX Descriptors
 245  *
 246  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 247  */
 248 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 249 #define TX_DESC_SIZE            16
 250 #define TX_RING_NR              8
 251 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 252
 253 struct txdesc {
 254         union {
 255                 __u8    all[16];
 256                 __le32  dw[4];
 257                 struct {
 258                         /* DW0 */
 259                         __le16  vlan;
 260                         __u8    rsv1;
 261                         __u8    flags;
 262
 263                         /* DW1 */
 264                         __le16  datalen;
 265                         __le16  mss;
 266
 267                         /* DW2 */
 268                         __le16  pktsize;
 269                         __le16  rsv2;
 270
 271                         /* DW3 */
 272                         __le32  bufaddr;
 273                 } desc1;
 274                 struct {
 275                         /* DW0 */
 276                         __le16  rsv1;
 277                         __u8    rsv2;
 278                         __u8    flags;
 279
 280                         /* DW1 */
 281                         __le16  datalen;
 282                         __le16  rsv3;
 283
 284                         /* DW2 */
 285                         __le32  bufaddrh;
 286
 287                         /* DW3 */
 288                         __le32  bufaddrl;
 289                 } desc2;
 290                 struct {
 291                         /* DW0 */
 292                         __u8    ehdrsz;
 293                         __u8    rsv1;
 294                         __u8    rsv2;
 295                         __u8    flags;
 296
 297                         /* DW1 */
 298                         __le16  trycnt;
 299                         __le16  segcnt;
 300
 301                         /* DW2 */
 302                         __le16  pktsz;
 303                         __le16  rsv3;
 304
 305                         /* DW3 */
 306                         __le32  bufaddrl;
 307                 } descwb;
 308         };
 309 };
 310
 311 enum jme_txdesc_flags_bits {
 312         TXFLAG_OWN      = 0x80,
 313         TXFLAG_INT      = 0x40,
 314         TXFLAG_64BIT    = 0x20,
 315         TXFLAG_TCPCS    = 0x10,
 316         TXFLAG_UDPCS    = 0x08,
 317         TXFLAG_IPCS     = 0x04,
 318         TXFLAG_LSEN     = 0x02,
 319         TXFLAG_TAGON    = 0x01,
 320 };
 321
 322 #define TXDESC_MSS_SHIFT        2
 323 enum jme_txwbdesc_flags_bits {
 324         TXWBFLAG_OWN    = 0x80,
 325         TXWBFLAG_INT    = 0x40,
 326         TXWBFLAG_TMOUT  = 0x20,
 327         TXWBFLAG_TRYOUT = 0x10,
 328         TXWBFLAG_COL    = 0x08,
 329
 330         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 331                           TXWBFLAG_TRYOUT |
 332                           TXWBFLAG_COL,
 333 };
 334
 335 #define RX_DESC_SIZE            16
 336 #define RX_RING_NR              4
 337 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 338 #define RX_BUF_DMA_ALIGN        8
 339 #define RX_PREPAD_SIZE          10
 340 #define ETH_CRC_LEN             2
 341 #define RX_VLANHDR_LEN          2
 342 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 343                                 ETH_HLEN + \
 344                                 ETH_CRC_LEN + \
 345                                 RX_VLANHDR_LEN + \
 346                                 RX_BUF_DMA_ALIGN)
 347
 348 struct rxdesc {
 349         union {
 350                 __u8    all[16];
 351                 __le32  dw[4];
 352                 struct {
 353                         /* DW0 */
 354                         __le16  rsv2;
 355                         __u8    rsv1;
 356                         __u8    flags;
 357
 358                         /* DW1 */
 359                         __le16  datalen;
 360                         __le16  wbcpl;
 361
 362                         /* DW2 */
 363                         __le32  bufaddrh;
 364
 365                         /* DW3 */
 366                         __le32  bufaddrl;
 367                 } desc1;
 368                 struct {
 369                         /* DW0 */
 370                         __le16  vlan;
 371                         __le16  flags;
 372
 373                         /* DW1 */
 374                         __le16  framesize;
 375                         __u8    errstat;
 376                         __u8    desccnt;
 377
 378                         /* DW2 */
 379                         __le32  rsshash;
 380
 381                         /* DW3 */
 382                         __u8    hashfun;
 383                         __u8    hashtype;
 384                         __le16  resrv;
 385                 } descwb;
 386         };
 387 };
 388
 389 enum jme_rxdesc_flags_bits {
 390         RXFLAG_OWN      = 0x80,
 391         RXFLAG_INT      = 0x40,
 392         RXFLAG_64BIT    = 0x20,
 393 };
 394
 395 enum jme_rxwbdesc_flags_bits {
 396         RXWBFLAG_OWN            = 0x8000,
 397         RXWBFLAG_INT            = 0x4000,
 398         RXWBFLAG_MF             = 0x2000,
 399         RXWBFLAG_64BIT          = 0x2000,
 400         RXWBFLAG_TCPON          = 0x1000,
 401         RXWBFLAG_UDPON          = 0x0800,
 402         RXWBFLAG_IPCS           = 0x0400,
 403         RXWBFLAG_TCPCS          = 0x0200,
 404         RXWBFLAG_UDPCS          = 0x0100,
 405         RXWBFLAG_TAGON          = 0x0080,
 406         RXWBFLAG_IPV4           = 0x0040,
 407         RXWBFLAG_IPV6           = 0x0020,
 408         RXWBFLAG_PAUSE          = 0x0010,
 409         RXWBFLAG_MAGIC          = 0x0008,
 410         RXWBFLAG_WAKEUP         = 0x0004,
 411         RXWBFLAG_DEST           = 0x0003,
 412         RXWBFLAG_DEST_UNI       = 0x0001,
 413         RXWBFLAG_DEST_MUL       = 0x0002,
 414         RXWBFLAG_DEST_BRO       = 0x0003,
 415 };
 416
 417 enum jme_rxwbdesc_desccnt_mask {
 418         RXWBDCNT_WBCPL  = 0x80,
 419         RXWBDCNT_DCNT   = 0x7F,
 420 };
 421
 422 enum jme_rxwbdesc_errstat_bits {
 423         RXWBERR_LIMIT   = 0x80,
 424         RXWBERR_MIIER   = 0x40,
 425         RXWBERR_NIBON   = 0x20,
 426         RXWBERR_COLON   = 0x10,
 427         RXWBERR_ABORT   = 0x08,
 428         RXWBERR_SHORT   = 0x04,
 429         RXWBERR_OVERUN  = 0x02,
 430         RXWBERR_CRCERR  = 0x01,
 431         RXWBERR_ALLERR  = 0xFF,
 432 };
 433
 434 /*
 435  * Buffer information corresponding to ring descriptors.
 436  */
 437 struct jme_buffer_info {
 438         struct sk_buff *skb;
 439         dma_addr_t mapping;
 440         int len;
 441         int nr_desc;
 442         unsigned long start_xmit;
 443 };
 444
 445 /*
 446  * The structure holding buffer information and ring descriptors all together.
 447  */
 448 struct jme_ring {
 449         void *alloc;            /* pointer to allocated memory */
 450         void *desc;             /* pointer to ring memory  */
 451         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 452         dma_addr_t dma;         /* phys address for ring dma */
 453
 454         /* Buffer information corresponding to each descriptor */
 455         struct jme_buffer_info *bufinf;
 456
 457         int next_to_use;
 458         atomic_t next_to_clean;
 459         atomic_t nr_free;
 460 };
 461
 462 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
 463 #define false 0
 464 #define true 0
 465 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
 466 #define PCI_VENDOR_ID_JMICRON           0x197B
 467 #endif
 468
 469 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
 470 #define PCI_VDEVICE(vendor, device)             \
 471         PCI_VENDOR_ID_##vendor, (device),       \
 472         PCI_ANY_ID, PCI_ANY_ID, 0, 0
 473 #endif
 474
 475 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 476 #define NET_STAT(priv) priv->stats
 477 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 478         netdev->get_stats = fun_ptr
 479 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 480 /*
 481  * CentOS 5.2 have *_hdr helpers back-ported
 482  */
 483 #ifdef RHEL_RELEASE_CODE
 484 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
 485 #define __DEFINE_IPHDR_HELPERS__
 486 #endif
 487 #else
 488 #define __DEFINE_IPHDR_HELPERS__
 489 #endif
 490 #else
 491 #define NET_STAT(priv) (priv->dev->stats)
 492 #define NETDEV_GET_STATS(netdev, fun_ptr)
 493 #define DECLARE_NET_DEVICE_STATS
 494 #endif
 495
 496 #ifdef __DEFINE_IPHDR_HELPERS__
 497 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
 498 {
 499         return skb->nh.iph;
 500 }
 501
 502 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
 503 {
 504         return skb->nh.ipv6h;
 505 }
 506
 507 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 508 {
 509         return skb->h.th;
 510 }
 511 #endif
 512
 513 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 514 #define DECLARE_NAPI_STRUCT
 515 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 516         dev->poll = pollfn; \
 517         dev->weight = q;
 518 #define JME_NAPI_HOLDER(holder) struct net_device *holder
 519 #define JME_NAPI_WEIGHT(w) int *w
 520 #define JME_NAPI_WEIGHT_VAL(w) *w
 521 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
 522 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
 523 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
 524 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
 525 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
 526 #define JME_RX_SCHEDULE_PREP(priv) \
 527         netif_rx_schedule_prep(priv->dev)
 528 #define JME_RX_SCHEDULE(priv) \
 529         __netif_rx_schedule(priv->dev);
 530 #else
 531 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 532 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 533         netif_napi_add(dev, napis, pollfn, q);
 534 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 535 #define JME_NAPI_WEIGHT(w) int w
 536 #define JME_NAPI_WEIGHT_VAL(w) w
 537 #define JME_NAPI_WEIGHT_SET(w, r)
 538 #define DECLARE_NETDEV
 539 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 540 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 541 #define JME_NAPI_DISABLE(priv) \
 542         if (!napi_disable_pending(&priv->napi)) \
 543                 napi_disable(&priv->napi);
 544 #define JME_RX_SCHEDULE_PREP(priv) \
 545         napi_schedule_prep(&priv->napi)
 546 #define JME_RX_SCHEDULE(priv) \
 547         __napi_schedule(&priv->napi);
 548 #endif
 549
 550 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
 551 #define JME_NEW_PM_API
 552 #endif
 553
 554 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
 555 static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
 556 {
 557         return ep->speed;
 558 }
 559 #endif
 560
 561 /*
 562  * Jmac Adapter Private data
 563  */
 564 struct jme_adapter {
 565         struct pci_dev          *pdev;
 566         struct net_device       *dev;
 567         void __iomem            *regs;
 568         struct mii_if_info      mii_if;
 569         struct jme_ring         rxring[RX_RING_NR];
 570         struct jme_ring         txring[TX_RING_NR];
 571         spinlock_t              phy_lock;
 572         spinlock_t              macaddr_lock;
 573         spinlock_t              rxmcs_lock;
 574         struct tasklet_struct   rxempty_task;
 575         struct tasklet_struct   rxclean_task;
 576         struct tasklet_struct   txclean_task;
 577         struct tasklet_struct   linkch_task;
 578         struct tasklet_struct   pcc_task;
 579         unsigned long           flags;
 580         u32                     reg_txcs;
 581         u32                     reg_txpfc;
 582         u32                     reg_rxcs;
 583         u32                     reg_rxmcs;
 584         u32                     reg_ghc;
 585         u32                     reg_pmcs;
 586         u32                     reg_gpreg1;
 587         u32                     phylink;
 588         u32                     tx_ring_size;
 589         u32                     tx_ring_mask;
 590         u32                     tx_wake_threshold;
 591         u32                     rx_ring_size;
 592         u32                     rx_ring_mask;
 593         u8                      mrrs;
 594         unsigned int            fpgaver;
 595         u8                      chiprev;
 596         u8                      chip_main_rev;
 597         u8                      chip_sub_rev;
 598         u8                      pcirev;
 599         u32                     msg_enable;
 600         struct ethtool_cmd      old_ecmd;
 601         unsigned int            old_mtu;
 602 #ifndef __UNIFY_VLAN_RX_PATH__
 603         struct vlan_group       *vlgrp;
 604 #endif
 605         struct dynpcc_info      dpi;
 606         atomic_t                intr_sem;
 607         atomic_t                link_changing;
 608         atomic_t                tx_cleaning;
 609         atomic_t                rx_cleaning;
 610         atomic_t                rx_empty;
 611         int                     (*jme_rx)(struct sk_buff *skb);
 612 #ifndef __UNIFY_VLAN_RX_PATH__
 613         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 614                                           struct vlan_group *grp,
 615                                           unsigned short vlan_tag);
 616 #endif
 617         DECLARE_NAPI_STRUCT
 618         DECLARE_NET_DEVICE_STATS
 619 };
 620
 621 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 622 static struct net_device_stats *
 623 jme_get_stats(struct net_device *netdev)
 624 {
 625         struct jme_adapter *jme = netdev_priv(netdev);
 626         return &jme->stats;
 627 }
 628 #endif
 629
 630 enum jme_flags_bits {
 631         JME_FLAG_MSI            = 1,
 632         JME_FLAG_SSET           = 2,
 633 #ifndef __USE_NDO_FIX_FEATURES__
 634         JME_FLAG_TXCSUM         = 3,
 635         JME_FLAG_TSO            = 4,
 636 #endif
 637         JME_FLAG_POLL           = 5,
 638         JME_FLAG_SHUTDOWN       = 6,
 639 };
 640
 641 #define TX_TIMEOUT              (5 * HZ)
 642 #define JME_REG_LEN             0x500
 643 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 644
 645 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 646 static inline struct jme_adapter*
 647 jme_napi_priv(struct net_device *holder)
 648 {
 649         struct jme_adapter *jme;
 650         jme = netdev_priv(holder);
 651         return jme;
 652 }
 653 #else
 654 static inline struct jme_adapter*
 655 jme_napi_priv(struct napi_struct *napi)
 656 {
 657         struct jme_adapter *jme;
 658         jme = container_of(napi, struct jme_adapter, napi);
 659         return jme;
 660 }
 661 #endif
 662
 663 /*
 664  * MMaped I/O Resters
 665  */
 666 enum jme_iomap_offsets {
 667         JME_MAC         = 0x0000,
 668         JME_PHY         = 0x0400,
 669         JME_MISC        = 0x0800,
 670         JME_RSS         = 0x0C00,
 671 };
 672
 673 enum jme_iomap_lens {
 674         JME_MAC_LEN     = 0x80,
 675         JME_PHY_LEN     = 0x58,
 676         JME_MISC_LEN    = 0x98,
 677         JME_RSS_LEN     = 0xFF,
 678 };
 679
 680 enum jme_iomap_regs {
 681         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 682         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 683         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 684         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 685         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 686         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 687         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 688         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 689
 690         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 691         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 692         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 693         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 694         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 695         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 696         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 697         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 698         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 699         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 700         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 701         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 702
 703         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 704         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 705         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 706
 707
 708         JME_PHY_PWR     = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
 709         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 710         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 711         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 712         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 713
 714
 715         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 716         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 717         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 718         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 719         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 720         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 721         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 722         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 723         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 724         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 725         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 726         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 727         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 728         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 729         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 730         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 731 };
 732
 733 /*
 734  * TX Control/Status Bits
 735  */
 736 enum jme_txcs_bits {
 737         TXCS_QUEUE7S    = 0x00008000,
 738         TXCS_QUEUE6S    = 0x00004000,
 739         TXCS_QUEUE5S    = 0x00002000,
 740         TXCS_QUEUE4S    = 0x00001000,
 741         TXCS_QUEUE3S    = 0x00000800,
 742         TXCS_QUEUE2S    = 0x00000400,
 743         TXCS_QUEUE1S    = 0x00000200,
 744         TXCS_QUEUE0S    = 0x00000100,
 745         TXCS_FIFOTH     = 0x000000C0,
 746         TXCS_DMASIZE    = 0x00000030,
 747         TXCS_BURST      = 0x00000004,
 748         TXCS_ENABLE     = 0x00000001,
 749 };
 750
 751 enum jme_txcs_value {
 752         TXCS_FIFOTH_16QW        = 0x000000C0,
 753         TXCS_FIFOTH_12QW        = 0x00000080,
 754         TXCS_FIFOTH_8QW         = 0x00000040,
 755         TXCS_FIFOTH_4QW         = 0x00000000,
 756
 757         TXCS_DMASIZE_64B        = 0x00000000,
 758         TXCS_DMASIZE_128B       = 0x00000010,
 759         TXCS_DMASIZE_256B       = 0x00000020,
 760         TXCS_DMASIZE_512B       = 0x00000030,
 761
 762         TXCS_SELECT_QUEUE0      = 0x00000000,
 763         TXCS_SELECT_QUEUE1      = 0x00010000,
 764         TXCS_SELECT_QUEUE2      = 0x00020000,
 765         TXCS_SELECT_QUEUE3      = 0x00030000,
 766         TXCS_SELECT_QUEUE4      = 0x00040000,
 767         TXCS_SELECT_QUEUE5      = 0x00050000,
 768         TXCS_SELECT_QUEUE6      = 0x00060000,
 769         TXCS_SELECT_QUEUE7      = 0x00070000,
 770
 771         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 772                                   TXCS_BURST,
 773 };
 774
 775 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 776
 777 /*
 778  * TX MAC Control/Status Bits
 779  */
 780 enum jme_txmcs_bit_masks {
 781         TXMCS_IFG2              = 0xC0000000,
 782         TXMCS_IFG1              = 0x30000000,
 783         TXMCS_TTHOLD            = 0x00000300,
 784         TXMCS_FBURST            = 0x00000080,
 785         TXMCS_CARRIEREXT        = 0x00000040,
 786         TXMCS_DEFER             = 0x00000020,
 787         TXMCS_BACKOFF           = 0x00000010,
 788         TXMCS_CARRIERSENSE      = 0x00000008,
 789         TXMCS_COLLISION         = 0x00000004,
 790         TXMCS_CRC               = 0x00000002,
 791         TXMCS_PADDING           = 0x00000001,
 792 };
 793
 794 enum jme_txmcs_values {
 795         TXMCS_IFG2_6_4          = 0x00000000,
 796         TXMCS_IFG2_8_5          = 0x40000000,
 797         TXMCS_IFG2_10_6         = 0x80000000,
 798         TXMCS_IFG2_12_7         = 0xC0000000,
 799
 800         TXMCS_IFG1_8_4          = 0x00000000,
 801         TXMCS_IFG1_12_6         = 0x10000000,
 802         TXMCS_IFG1_16_8         = 0x20000000,
 803         TXMCS_IFG1_20_10        = 0x30000000,
 804
 805         TXMCS_TTHOLD_1_8        = 0x00000000,
 806         TXMCS_TTHOLD_1_4        = 0x00000100,
 807         TXMCS_TTHOLD_1_2        = 0x00000200,
 808         TXMCS_TTHOLD_FULL       = 0x00000300,
 809
 810         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 811                                   TXMCS_IFG1_16_8 |
 812                                   TXMCS_TTHOLD_FULL |
 813                                   TXMCS_DEFER |
 814                                   TXMCS_CRC |
 815                                   TXMCS_PADDING,
 816 };
 817
 818 enum jme_txpfc_bits_masks {
 819         TXPFC_VLAN_TAG          = 0xFFFF0000,
 820         TXPFC_VLAN_EN           = 0x00008000,
 821         TXPFC_PF_EN             = 0x00000001,
 822 };
 823
 824 enum jme_txtrhd_bits_masks {
 825         TXTRHD_TXPEN            = 0x80000000,
 826         TXTRHD_TXP              = 0x7FFFFF00,
 827         TXTRHD_TXREN            = 0x00000080,
 828         TXTRHD_TXRL             = 0x0000007F,
 829 };
 830
 831 enum jme_txtrhd_shifts {
 832         TXTRHD_TXP_SHIFT        = 8,
 833         TXTRHD_TXRL_SHIFT       = 0,
 834 };
 835
 836 enum jme_txtrhd_values {
 837         TXTRHD_FULLDUPLEX       = 0x00000000,
 838         TXTRHD_HALFDUPLEX       = TXTRHD_TXPEN |
 839                                   ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
 840                                   TXTRHD_TXREN |
 841                                   ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
 842 };
 843
 844 /*
 845  * RX Control/Status Bits
 846  */
 847 enum jme_rxcs_bit_masks {
 848         /* FIFO full threshold for transmitting Tx Pause Packet */
 849         RXCS_FIFOTHTP   = 0x30000000,
 850         /* FIFO threshold for processing next packet */
 851         RXCS_FIFOTHNP   = 0x0C000000,
 852         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 853         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 854         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 855         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 856         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 857         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 858         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 859         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 860         RXCS_QST        = 0x00000004, /* Receive queue start */
 861         RXCS_SUSPEND    = 0x00000002,
 862         RXCS_ENABLE     = 0x00000001,
 863 };
 864
 865 enum jme_rxcs_values {
 866         RXCS_FIFOTHTP_16T       = 0x00000000,
 867         RXCS_FIFOTHTP_32T       = 0x10000000,
 868         RXCS_FIFOTHTP_64T       = 0x20000000,
 869         RXCS_FIFOTHTP_128T      = 0x30000000,
 870
 871         RXCS_FIFOTHNP_16QW      = 0x00000000,
 872         RXCS_FIFOTHNP_32QW      = 0x04000000,
 873         RXCS_FIFOTHNP_64QW      = 0x08000000,
 874         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 875
 876         RXCS_DMAREQSZ_16B       = 0x00000000,
 877         RXCS_DMAREQSZ_32B       = 0x01000000,
 878         RXCS_DMAREQSZ_64B       = 0x02000000,
 879         RXCS_DMAREQSZ_128B      = 0x03000000,
 880
 881         RXCS_QUEUESEL_Q0        = 0x00000000,
 882         RXCS_QUEUESEL_Q1        = 0x00010000,
 883         RXCS_QUEUESEL_Q2        = 0x00020000,
 884         RXCS_QUEUESEL_Q3        = 0x00030000,
 885
 886         RXCS_RETRYGAP_256ns     = 0x00000000,
 887         RXCS_RETRYGAP_512ns     = 0x00001000,
 888         RXCS_RETRYGAP_1024ns    = 0x00002000,
 889         RXCS_RETRYGAP_2048ns    = 0x00003000,
 890         RXCS_RETRYGAP_4096ns    = 0x00004000,
 891         RXCS_RETRYGAP_8192ns    = 0x00005000,
 892         RXCS_RETRYGAP_16384ns   = 0x00006000,
 893         RXCS_RETRYGAP_32768ns   = 0x00007000,
 894
 895         RXCS_RETRYCNT_0         = 0x00000000,
 896         RXCS_RETRYCNT_4         = 0x00000100,
 897         RXCS_RETRYCNT_8         = 0x00000200,
 898         RXCS_RETRYCNT_12        = 0x00000300,
 899         RXCS_RETRYCNT_16        = 0x00000400,
 900         RXCS_RETRYCNT_20        = 0x00000500,
 901         RXCS_RETRYCNT_24        = 0x00000600,
 902         RXCS_RETRYCNT_28        = 0x00000700,
 903         RXCS_RETRYCNT_32        = 0x00000800,
 904         RXCS_RETRYCNT_36        = 0x00000900,
 905         RXCS_RETRYCNT_40        = 0x00000A00,
 906         RXCS_RETRYCNT_44        = 0x00000B00,
 907         RXCS_RETRYCNT_48        = 0x00000C00,
 908         RXCS_RETRYCNT_52        = 0x00000D00,
 909         RXCS_RETRYCNT_56        = 0x00000E00,
 910         RXCS_RETRYCNT_60        = 0x00000F00,
 911
 912         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 913                                   RXCS_FIFOTHNP_128QW |
 914                                   RXCS_DMAREQSZ_128B |
 915                                   RXCS_RETRYGAP_256ns |
 916                                   RXCS_RETRYCNT_32,
 917 };
 918
 919 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 920
 921 /*
 922  * RX MAC Control/Status Bits
 923  */
 924 enum jme_rxmcs_bits {
 925         RXMCS_ALLFRAME          = 0x00000800,
 926         RXMCS_BRDFRAME          = 0x00000400,
 927         RXMCS_MULFRAME          = 0x00000200,
 928         RXMCS_UNIFRAME          = 0x00000100,
 929         RXMCS_ALLMULFRAME       = 0x00000080,
 930         RXMCS_MULFILTERED       = 0x00000040,
 931         RXMCS_RXCOLLDEC         = 0x00000020,
 932         RXMCS_FLOWCTRL          = 0x00000008,
 933         RXMCS_VTAGRM            = 0x00000004,
 934         RXMCS_PREPAD            = 0x00000002,
 935         RXMCS_CHECKSUM          = 0x00000001,
 936
 937         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 938                                   RXMCS_PREPAD |
 939                                   RXMCS_FLOWCTRL |
 940                                   RXMCS_CHECKSUM,
 941 };
 942
 943 /*
 944  * Wakeup Frame setup interface registers
 945  */
 946 #define WAKEUP_FRAME_NR 8
 947 #define WAKEUP_FRAME_MASK_DWNR  4
 948
 949 enum jme_wfoi_bit_masks {
 950         WFOI_MASK_SEL           = 0x00000070,
 951         WFOI_CRC_SEL            = 0x00000008,
 952         WFOI_FRAME_SEL          = 0x00000007,
 953 };
 954
 955 enum jme_wfoi_shifts {
 956         WFOI_MASK_SHIFT         = 4,
 957 };
 958
 959 /*
 960  * SMI Related definitions
 961  */
 962 enum jme_smi_bit_mask {
 963         SMI_DATA_MASK           = 0xFFFF0000,
 964         SMI_REG_ADDR_MASK       = 0x0000F800,
 965         SMI_PHY_ADDR_MASK       = 0x000007C0,
 966         SMI_OP_WRITE            = 0x00000020,
 967         /* Set to 1, after req done it'll be cleared to 0 */
 968         SMI_OP_REQ              = 0x00000010,
 969         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 970         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 971         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 972         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 973 };
 974
 975 enum jme_smi_bit_shift {
 976         SMI_DATA_SHIFT          = 16,
 977         SMI_REG_ADDR_SHIFT      = 11,
 978         SMI_PHY_ADDR_SHIFT      = 6,
 979 };
 980
 981 static inline u32 smi_reg_addr(int x)
 982 {
 983         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 984 }
 985
 986 static inline u32 smi_phy_addr(int x)
 987 {
 988         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 989 }
 990
 991 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 992 #define JME_PHY_REG_NR 32
 993
 994 /*
 995  * Global Host Control
 996  */
 997 enum jme_ghc_bit_mask {
 998         GHC_SWRST               = 0x40000000,
 999         GHC_TO_CLK_SRC          = 0x00C00000,
1000         GHC_TXMAC_CLK_SRC       = 0x00300000,
1001         GHC_DPX                 = 0x00000040,
1002         GHC_SPEED               = 0x00000030,
1003         GHC_LINK_POLL           = 0x00000001,
1004 };
1005
1006 enum jme_ghc_speed_val {
1007         GHC_SPEED_10M           = 0x00000010,
1008         GHC_SPEED_100M          = 0x00000020,
1009         GHC_SPEED_1000M         = 0x00000030,
1010 };
1011
1012 enum jme_ghc_to_clk {
1013         GHC_TO_CLK_OFF          = 0x00000000,
1014         GHC_TO_CLK_GPHY         = 0x00400000,
1015         GHC_TO_CLK_PCIE         = 0x00800000,
1016         GHC_TO_CLK_INVALID      = 0x00C00000,
1017 };
1018
1019 enum jme_ghc_txmac_clk {
1020         GHC_TXMAC_CLK_OFF       = 0x00000000,
1021         GHC_TXMAC_CLK_GPHY      = 0x00100000,
1022         GHC_TXMAC_CLK_PCIE      = 0x00200000,
1023         GHC_TXMAC_CLK_INVALID   = 0x00300000,
1024 };
1025
1026 /*
1027  * Power management control and status register
1028  */
1029 enum jme_pmcs_bit_masks {
1030         PMCS_STMASK     = 0xFFFF0000,
1031         PMCS_WF7DET     = 0x80000000,
1032         PMCS_WF6DET     = 0x40000000,
1033         PMCS_WF5DET     = 0x20000000,
1034         PMCS_WF4DET     = 0x10000000,
1035         PMCS_WF3DET     = 0x08000000,
1036         PMCS_WF2DET     = 0x04000000,
1037         PMCS_WF1DET     = 0x02000000,
1038         PMCS_WF0DET     = 0x01000000,
1039         PMCS_LFDET      = 0x00040000,
1040         PMCS_LRDET      = 0x00020000,
1041         PMCS_MFDET      = 0x00010000,
1042         PMCS_ENMASK     = 0x0000FFFF,
1043         PMCS_WF7EN      = 0x00008000,
1044         PMCS_WF6EN      = 0x00004000,
1045         PMCS_WF5EN      = 0x00002000,
1046         PMCS_WF4EN      = 0x00001000,
1047         PMCS_WF3EN      = 0x00000800,
1048         PMCS_WF2EN      = 0x00000400,
1049         PMCS_WF1EN      = 0x00000200,
1050         PMCS_WF0EN      = 0x00000100,
1051         PMCS_LFEN       = 0x00000004,
1052         PMCS_LREN       = 0x00000002,
1053         PMCS_MFEN       = 0x00000001,
1054 };
1055
1056 /*
1057  * New PHY Power Control Register
1058  */
1059 enum jme_phy_pwr_bit_masks {
1060         PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1061         PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1062         PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1063         PHY_PWR_CLKSEL  = 0x08000000, /*
1064                                        * XTL_OUT Clock select
1065                                        * (an internal free-running clock)
1066                                        * 0: xtl_out = phy_giga.A_XTL25_O
1067                                        * 1: xtl_out = phy_giga.PD_OSC
1068                                        */
1069 };
1070
1071 /*
1072  * Giga PHY Status Registers
1073  */
1074 enum jme_phy_link_bit_mask {
1075         PHY_LINK_SPEED_MASK             = 0x0000C000,
1076         PHY_LINK_DUPLEX                 = 0x00002000,
1077         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
1078         PHY_LINK_UP                     = 0x00000400,
1079         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
1080         PHY_LINK_MDI_STAT               = 0x00000040,
1081 };
1082
1083 enum jme_phy_link_speed_val {
1084         PHY_LINK_SPEED_10M              = 0x00000000,
1085         PHY_LINK_SPEED_100M             = 0x00004000,
1086         PHY_LINK_SPEED_1000M            = 0x00008000,
1087 };
1088
1089 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
1090
1091 /*
1092  * SMB Control and Status
1093  */
1094 enum jme_smbcsr_bit_mask {
1095         SMBCSR_CNACK    = 0x00020000,
1096         SMBCSR_RELOAD   = 0x00010000,
1097         SMBCSR_EEPROMD  = 0x00000020,
1098         SMBCSR_INITDONE = 0x00000010,
1099         SMBCSR_BUSY     = 0x0000000F,
1100 };
1101
1102 enum jme_smbintf_bit_mask {
1103         SMBINTF_HWDATR  = 0xFF000000,
1104         SMBINTF_HWDATW  = 0x00FF0000,
1105         SMBINTF_HWADDR  = 0x0000FF00,
1106         SMBINTF_HWRWN   = 0x00000020,
1107         SMBINTF_HWCMD   = 0x00000010,
1108         SMBINTF_FASTM   = 0x00000008,
1109         SMBINTF_GPIOSCL = 0x00000004,
1110         SMBINTF_GPIOSDA = 0x00000002,
1111         SMBINTF_GPIOEN  = 0x00000001,
1112 };
1113
1114 enum jme_smbintf_vals {
1115         SMBINTF_HWRWN_READ      = 0x00000020,
1116         SMBINTF_HWRWN_WRITE     = 0x00000000,
1117 };
1118
1119 enum jme_smbintf_shifts {
1120         SMBINTF_HWDATR_SHIFT    = 24,
1121         SMBINTF_HWDATW_SHIFT    = 16,
1122         SMBINTF_HWADDR_SHIFT    = 8,
1123 };
1124
1125 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1126 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1127 #define JME_SMB_LEN 256
1128 #define JME_EEPROM_MAGIC 0x250
1129
1130 /*
1131  * Timer Control/Status Register
1132  */
1133 enum jme_tmcsr_bit_masks {
1134         TMCSR_SWIT      = 0x80000000,
1135         TMCSR_EN        = 0x01000000,
1136         TMCSR_CNT       = 0x00FFFFFF,
1137 };
1138
1139 /*
1140  * General Purpose REG-0
1141  */
1142 enum jme_gpreg0_masks {
1143         GPREG0_DISSH            = 0xFF000000,
1144         GPREG0_PCIRLMT          = 0x00300000,
1145         GPREG0_PCCNOMUTCLR      = 0x00040000,
1146         GPREG0_LNKINTPOLL       = 0x00001000,
1147         GPREG0_PCCTMR           = 0x00000300,
1148         GPREG0_PHYADDR          = 0x0000001F,
1149 };
1150
1151 enum jme_gpreg0_vals {
1152         GPREG0_DISSH_DW7        = 0x80000000,
1153         GPREG0_DISSH_DW6        = 0x40000000,
1154         GPREG0_DISSH_DW5        = 0x20000000,
1155         GPREG0_DISSH_DW4        = 0x10000000,
1156         GPREG0_DISSH_DW3        = 0x08000000,
1157         GPREG0_DISSH_DW2        = 0x04000000,
1158         GPREG0_DISSH_DW1        = 0x02000000,
1159         GPREG0_DISSH_DW0        = 0x01000000,
1160         GPREG0_DISSH_ALL        = 0xFF000000,
1161
1162         GPREG0_PCIRLMT_8        = 0x00000000,
1163         GPREG0_PCIRLMT_6        = 0x00100000,
1164         GPREG0_PCIRLMT_5        = 0x00200000,
1165         GPREG0_PCIRLMT_4        = 0x00300000,
1166
1167         GPREG0_PCCTMR_16ns      = 0x00000000,
1168         GPREG0_PCCTMR_256ns     = 0x00000100,
1169         GPREG0_PCCTMR_1us       = 0x00000200,
1170         GPREG0_PCCTMR_1ms       = 0x00000300,
1171
1172         GPREG0_PHYADDR_1        = 0x00000001,
1173
1174         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1175                                   GPREG0_PCCTMR_1us |
1176                                   GPREG0_PHYADDR_1,
1177 };
1178
1179 /*
1180  * General Purpose REG-1
1181  */
1182 enum jme_gpreg1_bit_masks {
1183         GPREG1_RXCLKOFF         = 0x04000000,
1184         GPREG1_PCREQN           = 0x00020000,
1185         GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
1186         GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
1187         GPREG1_INTRDELAYUNIT    = 0x00000018,
1188         GPREG1_INTRDELAYENABLE  = 0x00000007,
1189 };
1190
1191 enum jme_gpreg1_vals {
1192         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1193         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1194         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1195         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1196
1197         GPREG1_INTDLYEN_1U      = 0x00000001,
1198         GPREG1_INTDLYEN_2U      = 0x00000002,
1199         GPREG1_INTDLYEN_3U      = 0x00000003,
1200         GPREG1_INTDLYEN_4U      = 0x00000004,
1201         GPREG1_INTDLYEN_5U      = 0x00000005,
1202         GPREG1_INTDLYEN_6U      = 0x00000006,
1203         GPREG1_INTDLYEN_7U      = 0x00000007,
1204
1205         GPREG1_DEFAULT          = GPREG1_PCREQN,
1206 };
1207
1208 /*
1209  * Interrupt Status Bits
1210  */
1211 enum jme_interrupt_bits {
1212         INTR_SWINTR     = 0x80000000,
1213         INTR_TMINTR     = 0x40000000,
1214         INTR_LINKCH     = 0x20000000,
1215         INTR_PAUSERCV   = 0x10000000,
1216         INTR_MAGICRCV   = 0x08000000,
1217         INTR_WAKERCV    = 0x04000000,
1218         INTR_PCCRX0TO   = 0x02000000,
1219         INTR_PCCRX1TO   = 0x01000000,
1220         INTR_PCCRX2TO   = 0x00800000,
1221         INTR_PCCRX3TO   = 0x00400000,
1222         INTR_PCCTXTO    = 0x00200000,
1223         INTR_PCCRX0     = 0x00100000,
1224         INTR_PCCRX1     = 0x00080000,
1225         INTR_PCCRX2     = 0x00040000,
1226         INTR_PCCRX3     = 0x00020000,
1227         INTR_PCCTX      = 0x00010000,
1228         INTR_RX3EMP     = 0x00008000,
1229         INTR_RX2EMP     = 0x00004000,
1230         INTR_RX1EMP     = 0x00002000,
1231         INTR_RX0EMP     = 0x00001000,
1232         INTR_RX3        = 0x00000800,
1233         INTR_RX2        = 0x00000400,
1234         INTR_RX1        = 0x00000200,
1235         INTR_RX0        = 0x00000100,
1236         INTR_TX7        = 0x00000080,
1237         INTR_TX6        = 0x00000040,
1238         INTR_TX5        = 0x00000020,
1239         INTR_TX4        = 0x00000010,
1240         INTR_TX3        = 0x00000008,
1241         INTR_TX2        = 0x00000004,
1242         INTR_TX1        = 0x00000002,
1243         INTR_TX0        = 0x00000001,
1244 };
1245
1246 static const u32 INTR_ENABLE = INTR_SWINTR |
1247                                  INTR_TMINTR |
1248                                  INTR_LINKCH |
1249                                  INTR_PCCRX0TO |
1250                                  INTR_PCCRX0 |
1251                                  INTR_PCCTXTO |
1252                                  INTR_PCCTX |
1253                                  INTR_RX0EMP;
1254
1255 /*
1256  * PCC Control Registers
1257  */
1258 enum jme_pccrx_masks {
1259         PCCRXTO_MASK    = 0xFFFF0000,
1260         PCCRX_MASK      = 0x0000FF00,
1261 };
1262
1263 enum jme_pcctx_masks {
1264         PCCTXTO_MASK    = 0xFFFF0000,
1265         PCCTX_MASK      = 0x0000FF00,
1266         PCCTX_QS_MASK   = 0x000000FF,
1267 };
1268
1269 enum jme_pccrx_shifts {
1270         PCCRXTO_SHIFT   = 16,
1271         PCCRX_SHIFT     = 8,
1272 };
1273
1274 enum jme_pcctx_shifts {
1275         PCCTXTO_SHIFT   = 16,
1276         PCCTX_SHIFT     = 8,
1277 };
1278
1279 enum jme_pcctx_bits {
1280         PCCTXQ0_EN      = 0x00000001,
1281         PCCTXQ1_EN      = 0x00000002,
1282         PCCTXQ2_EN      = 0x00000004,
1283         PCCTXQ3_EN      = 0x00000008,
1284         PCCTXQ4_EN      = 0x00000010,
1285         PCCTXQ5_EN      = 0x00000020,
1286         PCCTXQ6_EN      = 0x00000040,
1287         PCCTXQ7_EN      = 0x00000080,
1288 };
1289
1290 /*
1291  * Chip Mode Register
1292  */
1293 enum jme_chipmode_bit_masks {
1294         CM_FPGAVER_MASK         = 0xFFFF0000,
1295         CM_CHIPREV_MASK         = 0x0000FF00,
1296         CM_CHIPMODE_MASK        = 0x0000000F,
1297 };
1298
1299 enum jme_chipmode_shifts {
1300         CM_FPGAVER_SHIFT        = 16,
1301         CM_CHIPREV_SHIFT        = 8,
1302 };
1303
1304 /*
1305  * Aggressive Power Mode Control
1306  */
1307 enum jme_apmc_bits {
1308         JME_APMC_PCIE_SD_EN     = 0x40000000,
1309         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1310         JME_APMC_EPIEN          = 0x04000000,
1311         JME_APMC_EPIEN_CTRL     = 0x03000000,
1312 };
1313
1314 enum jme_apmc_values {
1315         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1316         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1317 };
1318
1319 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1320
1321 #ifdef REG_DEBUG
1322 static char *MAC_REG_NAME[] = {
1323         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1324         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1325         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1326         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1327         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1328         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1329         "JME_PMCS"};
1330
1331 static char *PE_REG_NAME[] = {
1332         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1333         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1334         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1335         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1336         "JME_SMBCSR",   "JME_SMBINTF"};
1337
1338 static char *MISC_REG_NAME[] = {
1339         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1340         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1341         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1342         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1343         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1344         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1345         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1346         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1347         "JME_PCCSRX0"};
1348
1349 static inline void reg_dbg(const struct jme_adapter *jme,
1350                 const char *msg, u32 val, u32 reg)
1351 {
1352         const char *regname;
1353         switch (reg & 0xF00) {
1354         case 0x000:
1355                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1356                 break;
1357         case 0x400:
1358                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1359                 break;
1360         case 0x800:
1361                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1362                 break;
1363         default:
1364                 regname = PE_REG_NAME[0];
1365         }
1366         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1367                         msg, val, regname);
1368 }
1369 #else
1370 static inline void reg_dbg(const struct jme_adapter *jme,
1371                 const char *msg, u32 val, u32 reg) {}
1372 #endif
1373
1374 /*
1375  * Read/Write MMaped I/O Registers
1376  */
1377 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1378 {
1379         return readl(jme->regs + reg);
1380 }
1381
1382 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1383 {
1384         reg_dbg(jme, "REG WRITE", val, reg);
1385         writel(val, jme->regs + reg);
1386         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1387 }
1388
1389 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1390 {
1391         /*
1392          * Read after write should cause flush
1393          */
1394         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1395         writel(val, jme->regs + reg);
1396         readl(jme->regs + reg);
1397         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1398 }
1399
1400 /*
1401  * PHY Regs
1402  */
1403 enum jme_phy_reg17_bit_masks {
1404         PREG17_SPEED            = 0xC000,
1405         PREG17_DUPLEX           = 0x2000,
1406         PREG17_SPDRSV           = 0x0800,
1407         PREG17_LNKUP            = 0x0400,
1408         PREG17_MDI              = 0x0040,
1409 };
1410
1411 enum jme_phy_reg17_vals {
1412         PREG17_SPEED_10M        = 0x0000,
1413         PREG17_SPEED_100M       = 0x4000,
1414         PREG17_SPEED_1000M      = 0x8000,
1415 };
1416
1417 #define BMSR_ANCOMP               0x0020
1418
1419 /*
1420  * Workaround
1421  */
1422 static inline int is_buggy250(unsigned short device, u8 chiprev)
1423 {
1424         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1425 }
1426
1427 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1428 {
1429         return chip_main_rev >= 5;
1430 }
1431
1432 /*
1433  * Function prototypes
1434  */
1435 static int jme_set_settings(struct net_device *netdev,
1436                                 struct ethtool_cmd *ecmd);
1437 static void jme_set_unicastaddr(struct net_device *netdev);
1438 static void jme_set_multi(struct net_device *netdev);
1439
1440 #endif
1441