jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #ifndef __JME_H_INCLUDED__
  26 #define __JME_H_INCLUDED__
  27 #include <linux/interrupt.h>
  28
  29 #define DRV_NAME        "jme"
  30 #define DRV_VERSION     "1.0.8.2-jmmod"
  31 #define PFX             DRV_NAME ": "
  32
  33 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  34 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  35
  36 /*
  37  * Message related definitions
  38  */
  39 #define JME_DEF_MSG_ENABLE \
  40         (NETIF_MSG_PROBE | \
  41         NETIF_MSG_LINK | \
  42         NETIF_MSG_RX_ERR | \
  43         NETIF_MSG_TX_ERR | \
  44         NETIF_MSG_HW)
  45
  46 #ifndef pr_err
  47 #define pr_err(fmt, arg...) \
  48         printk(KERN_ERR fmt, ##arg)
  49 #endif
  50 #ifndef netdev_err
  51 #define netdev_err(netdev, fmt, arg...) \
  52         pr_err(fmt, ##arg)
  53 #endif
  54
  55 #ifdef TX_DEBUG
  56 #define tx_dbg(priv, fmt, args...)                                      \
  57         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  58 #else
  59 #define tx_dbg(priv, fmt, args...)                                      \
  60 do {                                                                    \
  61         if (0)                                                          \
  62                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  63 } while (0)
  64 #endif
  65
  66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
  67 #define jme_msg(msglvl, type, priv, fmt, args...) \
  68         if (netif_msg_##type(priv)) \
  69                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
  70
  71 #define msg_probe(priv, fmt, args...) \
  72         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
  73
  74 #define msg_link(priv, fmt, args...) \
  75         jme_msg(KERN_INFO, link, priv, fmt, ## args)
  76
  77 #define msg_intr(priv, fmt, args...) \
  78         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
  79
  80 #define msg_rx_err(priv, fmt, args...) \
  81         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
  82
  83 #define msg_rx_status(priv, fmt, args...) \
  84         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
  85
  86 #define msg_tx_err(priv, fmt, args...) \
  87         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
  88
  89 #define msg_tx_done(priv, fmt, args...) \
  90         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
  91
  92 #define msg_tx_queued(priv, fmt, args...) \
  93         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
  94
  95 #define msg_hw(priv, fmt, args...) \
  96         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
  97
  98 #ifndef netif_info
  99 #define netif_info(priv, type, dev, fmt, args...) \
 100         msg_ ## type(priv, fmt, ## args)
 101 #endif
 102 #ifndef netif_err
 103 #define netif_err(priv, type, dev, fmt, args...) \
 104         msg_ ## type(priv, fmt, ## args)
 105 #endif
 106 #endif
 107
 108 #ifndef NETIF_F_TSO6
 109 #define NETIF_F_TSO6 0
 110 #endif
 111 #ifndef NETIF_F_IPV6_CSUM
 112 #define NETIF_F_IPV6_CSUM 0
 113 #endif
 114
 115 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
 116 #define __USE_NDO_FIX_FEATURES__
 117 #endif
 118
 119 /*
 120  * Extra PCI Configuration space interface
 121  */
 122 #define PCI_DCSR_MRRS           0x59
 123 #define PCI_DCSR_MRRS_MASK      0x70
 124
 125 enum pci_dcsr_mrrs_vals {
 126         MRRS_128B       = 0x00,
 127         MRRS_256B       = 0x10,
 128         MRRS_512B       = 0x20,
 129         MRRS_1024B      = 0x30,
 130         MRRS_2048B      = 0x40,
 131         MRRS_4096B      = 0x50,
 132 };
 133
 134 #define PCI_SPI                 0xB0
 135
 136 enum pci_spi_bits {
 137         SPI_EN          = 0x10,
 138         SPI_MISO        = 0x08,
 139         SPI_MOSI        = 0x04,
 140         SPI_SCLK        = 0x02,
 141         SPI_CS          = 0x01,
 142 };
 143
 144 struct jme_spi_op {
 145         void __user *uwbuf;
 146         void __user *urbuf;
 147         __u8    wn;     /* Number of write actions */
 148         __u8    rn;     /* Number of read actions */
 149         __u8    bitn;   /* Number of bits per action */
 150         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
 151         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
 152
 153         /* Internal use only */
 154         u8      *kwbuf;
 155         u8      *krbuf;
 156         u8      sr;
 157         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
 158 };
 159
 160 enum jme_spi_op_bits {
 161         SPI_MODE_CPHA   = 0x01,
 162         SPI_MODE_CPOL   = 0x02,
 163         SPI_MODE_DUP    = 0x80,
 164 };
 165
 166 #define HALF_US 500     /* 500 ns */
 167 #define JMESPIIOCTL     SIOCDEVPRIVATE
 168
 169 #define PCI_PRIV_PE1            0xE4
 170
 171 enum pci_priv_pe1_bit_masks {
 172         PE1_ASPMSUPRT   = 0x00000003, /*
 173                                        * RW:
 174                                        * Aspm_support[1:0]
 175                                        * (R/W Port of 5C[11:10])
 176                                        */
 177         PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
 178         PE1_RDYDMA      = 0x00000008, /* RO: ~link.rdy_for_dma */
 179         PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
 180         PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
 181         PE1_GPREG0      = 0x0000FF00, /*
 182                                        * SRW:
 183                                        * Cfg_gp_reg0
 184                                        * [7:6] phy_giga BG control
 185                                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
 186                                        * [4:0] Reserved
 187                                        */
 188         PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
 189         PE1_GPREG1      = 0x00FF0000, /* RW: Cfg_gp_reg1 */
 190         PE1_REVID       = 0xFF000000, /* RO: Rev ID */
 191 };
 192
 193 enum pci_priv_pe1_values {
 194         PE1_GPREG0_ENBG         = 0x00000000, /* en BG */
 195         PE1_GPREG0_PDD3COLD     = 0x00004000, /* giga_PD + d3cold */
 196         PE1_GPREG0_PDPCIESD     = 0x00008000, /* giga_PD + pcie_shutdown */
 197         PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
 198 };
 199
 200 /*
 201  * Dynamic(adaptive)/Static PCC values
 202  */
 203 enum dynamic_pcc_values {
 204         PCC_OFF         = 0,
 205         PCC_P1          = 1,
 206         PCC_P2          = 2,
 207         PCC_P3          = 3,
 208
 209         PCC_OFF_TO      = 0,
 210         PCC_P1_TO       = 1,
 211         PCC_P2_TO       = 64,
 212         PCC_P3_TO       = 128,
 213
 214         PCC_OFF_CNT     = 0,
 215         PCC_P1_CNT      = 1,
 216         PCC_P2_CNT      = 16,
 217         PCC_P3_CNT      = 32,
 218 };
 219 struct dynpcc_info {
 220         unsigned long   last_bytes;
 221         unsigned long   last_pkts;
 222         unsigned long   intr_cnt;
 223         unsigned char   cur;
 224         unsigned char   attempt;
 225         unsigned char   cnt;
 226 };
 227 #define PCC_INTERVAL_US 100000
 228 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 229 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 230 #define PCC_P2_THRESHOLD 800
 231 #define PCC_INTR_THRESHOLD 800
 232 #define PCC_TX_TO 1000
 233 #define PCC_TX_CNT 8
 234
 235 /*
 236  * TX/RX Descriptors
 237  *
 238  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 239  */
 240 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 241 #define TX_DESC_SIZE            16
 242 #define TX_RING_NR              8
 243 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 244
 245 struct txdesc {
 246         union {
 247                 __u8    all[16];
 248                 __le32  dw[4];
 249                 struct {
 250                         /* DW0 */
 251                         __le16  vlan;
 252                         __u8    rsv1;
 253                         __u8    flags;
 254
 255                         /* DW1 */
 256                         __le16  datalen;
 257                         __le16  mss;
 258
 259                         /* DW2 */
 260                         __le16  pktsize;
 261                         __le16  rsv2;
 262
 263                         /* DW3 */
 264                         __le32  bufaddr;
 265                 } desc1;
 266                 struct {
 267                         /* DW0 */
 268                         __le16  rsv1;
 269                         __u8    rsv2;
 270                         __u8    flags;
 271
 272                         /* DW1 */
 273                         __le16  datalen;
 274                         __le16  rsv3;
 275
 276                         /* DW2 */
 277                         __le32  bufaddrh;
 278
 279                         /* DW3 */
 280                         __le32  bufaddrl;
 281                 } desc2;
 282                 struct {
 283                         /* DW0 */
 284                         __u8    ehdrsz;
 285                         __u8    rsv1;
 286                         __u8    rsv2;
 287                         __u8    flags;
 288
 289                         /* DW1 */
 290                         __le16  trycnt;
 291                         __le16  segcnt;
 292
 293                         /* DW2 */
 294                         __le16  pktsz;
 295                         __le16  rsv3;
 296
 297                         /* DW3 */
 298                         __le32  bufaddrl;
 299                 } descwb;
 300         };
 301 };
 302
 303 enum jme_txdesc_flags_bits {
 304         TXFLAG_OWN      = 0x80,
 305         TXFLAG_INT      = 0x40,
 306         TXFLAG_64BIT    = 0x20,
 307         TXFLAG_TCPCS    = 0x10,
 308         TXFLAG_UDPCS    = 0x08,
 309         TXFLAG_IPCS     = 0x04,
 310         TXFLAG_LSEN     = 0x02,
 311         TXFLAG_TAGON    = 0x01,
 312 };
 313
 314 #define TXDESC_MSS_SHIFT        2
 315 enum jme_txwbdesc_flags_bits {
 316         TXWBFLAG_OWN    = 0x80,
 317         TXWBFLAG_INT    = 0x40,
 318         TXWBFLAG_TMOUT  = 0x20,
 319         TXWBFLAG_TRYOUT = 0x10,
 320         TXWBFLAG_COL    = 0x08,
 321
 322         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 323                           TXWBFLAG_TRYOUT |
 324                           TXWBFLAG_COL,
 325 };
 326
 327 #define RX_DESC_SIZE            16
 328 #define RX_RING_NR              4
 329 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 330 #define RX_BUF_DMA_ALIGN        8
 331 #define RX_PREPAD_SIZE          10
 332 #define ETH_CRC_LEN             2
 333 #define RX_VLANHDR_LEN          2
 334 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 335                                 ETH_HLEN + \
 336                                 ETH_CRC_LEN + \
 337                                 RX_VLANHDR_LEN + \
 338                                 RX_BUF_DMA_ALIGN)
 339
 340 struct rxdesc {
 341         union {
 342                 __u8    all[16];
 343                 __le32  dw[4];
 344                 struct {
 345                         /* DW0 */
 346                         __le16  rsv2;
 347                         __u8    rsv1;
 348                         __u8    flags;
 349
 350                         /* DW1 */
 351                         __le16  datalen;
 352                         __le16  wbcpl;
 353
 354                         /* DW2 */
 355                         __le32  bufaddrh;
 356
 357                         /* DW3 */
 358                         __le32  bufaddrl;
 359                 } desc1;
 360                 struct {
 361                         /* DW0 */
 362                         __le16  vlan;
 363                         __le16  flags;
 364
 365                         /* DW1 */
 366                         __le16  framesize;
 367                         __u8    errstat;
 368                         __u8    desccnt;
 369
 370                         /* DW2 */
 371                         __le32  rsshash;
 372
 373                         /* DW3 */
 374                         __u8    hashfun;
 375                         __u8    hashtype;
 376                         __le16  resrv;
 377                 } descwb;
 378         };
 379 };
 380
 381 enum jme_rxdesc_flags_bits {
 382         RXFLAG_OWN      = 0x80,
 383         RXFLAG_INT      = 0x40,
 384         RXFLAG_64BIT    = 0x20,
 385 };
 386
 387 enum jme_rxwbdesc_flags_bits {
 388         RXWBFLAG_OWN            = 0x8000,
 389         RXWBFLAG_INT            = 0x4000,
 390         RXWBFLAG_MF             = 0x2000,
 391         RXWBFLAG_64BIT          = 0x2000,
 392         RXWBFLAG_TCPON          = 0x1000,
 393         RXWBFLAG_UDPON          = 0x0800,
 394         RXWBFLAG_IPCS           = 0x0400,
 395         RXWBFLAG_TCPCS          = 0x0200,
 396         RXWBFLAG_UDPCS          = 0x0100,
 397         RXWBFLAG_TAGON          = 0x0080,
 398         RXWBFLAG_IPV4           = 0x0040,
 399         RXWBFLAG_IPV6           = 0x0020,
 400         RXWBFLAG_PAUSE          = 0x0010,
 401         RXWBFLAG_MAGIC          = 0x0008,
 402         RXWBFLAG_WAKEUP         = 0x0004,
 403         RXWBFLAG_DEST           = 0x0003,
 404         RXWBFLAG_DEST_UNI       = 0x0001,
 405         RXWBFLAG_DEST_MUL       = 0x0002,
 406         RXWBFLAG_DEST_BRO       = 0x0003,
 407 };
 408
 409 enum jme_rxwbdesc_desccnt_mask {
 410         RXWBDCNT_WBCPL  = 0x80,
 411         RXWBDCNT_DCNT   = 0x7F,
 412 };
 413
 414 enum jme_rxwbdesc_errstat_bits {
 415         RXWBERR_LIMIT   = 0x80,
 416         RXWBERR_MIIER   = 0x40,
 417         RXWBERR_NIBON   = 0x20,
 418         RXWBERR_COLON   = 0x10,
 419         RXWBERR_ABORT   = 0x08,
 420         RXWBERR_SHORT   = 0x04,
 421         RXWBERR_OVERUN  = 0x02,
 422         RXWBERR_CRCERR  = 0x01,
 423         RXWBERR_ALLERR  = 0xFF,
 424 };
 425
 426 /*
 427  * Buffer information corresponding to ring descriptors.
 428  */
 429 struct jme_buffer_info {
 430         struct sk_buff *skb;
 431         dma_addr_t mapping;
 432         int len;
 433         int nr_desc;
 434         unsigned long start_xmit;
 435 };
 436
 437 /*
 438  * The structure holding buffer information and ring descriptors all together.
 439  */
 440 struct jme_ring {
 441         void *alloc;            /* pointer to allocated memory */
 442         void *desc;             /* pointer to ring memory  */
 443         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 444         dma_addr_t dma;         /* phys address for ring dma */
 445
 446         /* Buffer information corresponding to each descriptor */
 447         struct jme_buffer_info *bufinf;
 448
 449         int next_to_use;
 450         atomic_t next_to_clean;
 451         atomic_t nr_free;
 452 };
 453
 454 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
 455 #define false 0
 456 #define true 0
 457 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
 458 #define PCI_VENDOR_ID_JMICRON           0x197B
 459 #endif
 460
 461 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
 462 #define PCI_VDEVICE(vendor, device)             \
 463         PCI_VENDOR_ID_##vendor, (device),       \
 464         PCI_ANY_ID, PCI_ANY_ID, 0, 0
 465 #endif
 466
 467 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 468 #define NET_STAT(priv) priv->stats
 469 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 470         netdev->get_stats = fun_ptr
 471 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 472 /*
 473  * CentOS 5.2 have *_hdr helpers back-ported
 474  */
 475 #ifdef RHEL_RELEASE_CODE
 476 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
 477 #define __DEFINE_IPHDR_HELPERS__
 478 #endif
 479 #else
 480 #define __DEFINE_IPHDR_HELPERS__
 481 #endif
 482 #else
 483 #define NET_STAT(priv) (priv->dev->stats)
 484 #define NETDEV_GET_STATS(netdev, fun_ptr)
 485 #define DECLARE_NET_DEVICE_STATS
 486 #endif
 487
 488 #ifdef __DEFINE_IPHDR_HELPERS__
 489 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
 490 {
 491         return skb->nh.iph;
 492 }
 493
 494 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
 495 {
 496         return skb->nh.ipv6h;
 497 }
 498
 499 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 500 {
 501         return skb->h.th;
 502 }
 503 #endif
 504
 505 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 506 #define DECLARE_NAPI_STRUCT
 507 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 508         dev->poll = pollfn; \
 509         dev->weight = q;
 510 #define JME_NAPI_HOLDER(holder) struct net_device *holder
 511 #define JME_NAPI_WEIGHT(w) int *w
 512 #define JME_NAPI_WEIGHT_VAL(w) *w
 513 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
 514 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
 515 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
 516 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
 517 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
 518 #define JME_RX_SCHEDULE_PREP(priv) \
 519         netif_rx_schedule_prep(priv->dev)
 520 #define JME_RX_SCHEDULE(priv) \
 521         __netif_rx_schedule(priv->dev);
 522 #else
 523 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 524 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 525         netif_napi_add(dev, napis, pollfn, q);
 526 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 527 #define JME_NAPI_WEIGHT(w) int w
 528 #define JME_NAPI_WEIGHT_VAL(w) w
 529 #define JME_NAPI_WEIGHT_SET(w, r)
 530 #define DECLARE_NETDEV
 531 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 532 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 533 #define JME_NAPI_DISABLE(priv) \
 534         if (!napi_disable_pending(&priv->napi)) \
 535                 napi_disable(&priv->napi);
 536 #define JME_RX_SCHEDULE_PREP(priv) \
 537         napi_schedule_prep(&priv->napi)
 538 #define JME_RX_SCHEDULE(priv) \
 539         __napi_schedule(&priv->napi);
 540 #endif
 541
 542 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
 543 #define JME_NEW_PM_API
 544 #endif
 545
 546 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
 547 static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
 548 {
 549         return ep->speed;
 550 }
 551 #endif
 552
 553 /*
 554  * Jmac Adapter Private data
 555  */
 556 struct jme_adapter {
 557         struct pci_dev          *pdev;
 558         struct net_device       *dev;
 559         void __iomem            *regs;
 560         struct mii_if_info      mii_if;
 561         struct jme_ring         rxring[RX_RING_NR];
 562         struct jme_ring         txring[TX_RING_NR];
 563         spinlock_t              phy_lock;
 564         spinlock_t              macaddr_lock;
 565         spinlock_t              rxmcs_lock;
 566         struct tasklet_struct   rxempty_task;
 567         struct tasklet_struct   rxclean_task;
 568         struct tasklet_struct   txclean_task;
 569         struct tasklet_struct   linkch_task;
 570         struct tasklet_struct   pcc_task;
 571         unsigned long           flags;
 572         u32                     reg_txcs;
 573         u32                     reg_txpfc;
 574         u32                     reg_rxcs;
 575         u32                     reg_rxmcs;
 576         u32                     reg_ghc;
 577         u32                     reg_pmcs;
 578         u32                     reg_gpreg1;
 579         u32                     phylink;
 580         u32                     tx_ring_size;
 581         u32                     tx_ring_mask;
 582         u32                     tx_wake_threshold;
 583         u32                     rx_ring_size;
 584         u32                     rx_ring_mask;
 585         u8                      mrrs;
 586         unsigned int            fpgaver;
 587         u8                      chiprev;
 588         u8                      chip_main_rev;
 589         u8                      chip_sub_rev;
 590         u8                      pcirev;
 591         u32                     msg_enable;
 592         struct ethtool_cmd      old_ecmd;
 593         unsigned int            old_mtu;
 594         struct vlan_group       *vlgrp;
 595         struct dynpcc_info      dpi;
 596         atomic_t                intr_sem;
 597         atomic_t                link_changing;
 598         atomic_t                tx_cleaning;
 599         atomic_t                rx_cleaning;
 600         atomic_t                rx_empty;
 601         int                     (*jme_rx)(struct sk_buff *skb);
 602         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 603                                           struct vlan_group *grp,
 604                                           unsigned short vlan_tag);
 605         DECLARE_NAPI_STRUCT
 606         DECLARE_NET_DEVICE_STATS
 607 };
 608
 609 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 610 static struct net_device_stats *
 611 jme_get_stats(struct net_device *netdev)
 612 {
 613         struct jme_adapter *jme = netdev_priv(netdev);
 614         return &jme->stats;
 615 }
 616 #endif
 617
 618 enum jme_flags_bits {
 619         JME_FLAG_MSI            = 1,
 620         JME_FLAG_SSET           = 2,
 621 #ifndef __USE_NDO_FIX_FEATURES__
 622         JME_FLAG_TXCSUM         = 3,
 623         JME_FLAG_TSO            = 4,
 624 #endif
 625         JME_FLAG_POLL           = 5,
 626         JME_FLAG_SHUTDOWN       = 6,
 627 };
 628
 629 #define TX_TIMEOUT              (5 * HZ)
 630 #define JME_REG_LEN             0x500
 631 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 632
 633 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
 634 static inline struct jme_adapter*
 635 jme_napi_priv(struct net_device *holder)
 636 {
 637         struct jme_adapter *jme;
 638         jme = netdev_priv(holder);
 639         return jme;
 640 }
 641 #else
 642 static inline struct jme_adapter*
 643 jme_napi_priv(struct napi_struct *napi)
 644 {
 645         struct jme_adapter *jme;
 646         jme = container_of(napi, struct jme_adapter, napi);
 647         return jme;
 648 }
 649 #endif
 650
 651 /*
 652  * MMaped I/O Resters
 653  */
 654 enum jme_iomap_offsets {
 655         JME_MAC         = 0x0000,
 656         JME_PHY         = 0x0400,
 657         JME_MISC        = 0x0800,
 658         JME_RSS         = 0x0C00,
 659 };
 660
 661 enum jme_iomap_lens {
 662         JME_MAC_LEN     = 0x80,
 663         JME_PHY_LEN     = 0x58,
 664         JME_MISC_LEN    = 0x98,
 665         JME_RSS_LEN     = 0xFF,
 666 };
 667
 668 enum jme_iomap_regs {
 669         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 670         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 671         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 672         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 673         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 674         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 675         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 676         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 677
 678         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 679         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 680         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 681         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 682         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 683         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 684         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 685         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 686         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 687         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 688         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 689         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 690
 691         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 692         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 693         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 694
 695
 696         JME_PHY_PWR     = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
 697         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 698         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 699         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 700         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 701
 702
 703         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 704         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 705         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 706         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 707         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 708         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 709         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 710         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 711         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 712         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 713         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 714         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 715         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 716         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 717         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 718         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 719 };
 720
 721 /*
 722  * TX Control/Status Bits
 723  */
 724 enum jme_txcs_bits {
 725         TXCS_QUEUE7S    = 0x00008000,
 726         TXCS_QUEUE6S    = 0x00004000,
 727         TXCS_QUEUE5S    = 0x00002000,
 728         TXCS_QUEUE4S    = 0x00001000,
 729         TXCS_QUEUE3S    = 0x00000800,
 730         TXCS_QUEUE2S    = 0x00000400,
 731         TXCS_QUEUE1S    = 0x00000200,
 732         TXCS_QUEUE0S    = 0x00000100,
 733         TXCS_FIFOTH     = 0x000000C0,
 734         TXCS_DMASIZE    = 0x00000030,
 735         TXCS_BURST      = 0x00000004,
 736         TXCS_ENABLE     = 0x00000001,
 737 };
 738
 739 enum jme_txcs_value {
 740         TXCS_FIFOTH_16QW        = 0x000000C0,
 741         TXCS_FIFOTH_12QW        = 0x00000080,
 742         TXCS_FIFOTH_8QW         = 0x00000040,
 743         TXCS_FIFOTH_4QW         = 0x00000000,
 744
 745         TXCS_DMASIZE_64B        = 0x00000000,
 746         TXCS_DMASIZE_128B       = 0x00000010,
 747         TXCS_DMASIZE_256B       = 0x00000020,
 748         TXCS_DMASIZE_512B       = 0x00000030,
 749
 750         TXCS_SELECT_QUEUE0      = 0x00000000,
 751         TXCS_SELECT_QUEUE1      = 0x00010000,
 752         TXCS_SELECT_QUEUE2      = 0x00020000,
 753         TXCS_SELECT_QUEUE3      = 0x00030000,
 754         TXCS_SELECT_QUEUE4      = 0x00040000,
 755         TXCS_SELECT_QUEUE5      = 0x00050000,
 756         TXCS_SELECT_QUEUE6      = 0x00060000,
 757         TXCS_SELECT_QUEUE7      = 0x00070000,
 758
 759         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 760                                   TXCS_BURST,
 761 };
 762
 763 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 764
 765 /*
 766  * TX MAC Control/Status Bits
 767  */
 768 enum jme_txmcs_bit_masks {
 769         TXMCS_IFG2              = 0xC0000000,
 770         TXMCS_IFG1              = 0x30000000,
 771         TXMCS_TTHOLD            = 0x00000300,
 772         TXMCS_FBURST            = 0x00000080,
 773         TXMCS_CARRIEREXT        = 0x00000040,
 774         TXMCS_DEFER             = 0x00000020,
 775         TXMCS_BACKOFF           = 0x00000010,
 776         TXMCS_CARRIERSENSE      = 0x00000008,
 777         TXMCS_COLLISION         = 0x00000004,
 778         TXMCS_CRC               = 0x00000002,
 779         TXMCS_PADDING           = 0x00000001,
 780 };
 781
 782 enum jme_txmcs_values {
 783         TXMCS_IFG2_6_4          = 0x00000000,
 784         TXMCS_IFG2_8_5          = 0x40000000,
 785         TXMCS_IFG2_10_6         = 0x80000000,
 786         TXMCS_IFG2_12_7         = 0xC0000000,
 787
 788         TXMCS_IFG1_8_4          = 0x00000000,
 789         TXMCS_IFG1_12_6         = 0x10000000,
 790         TXMCS_IFG1_16_8         = 0x20000000,
 791         TXMCS_IFG1_20_10        = 0x30000000,
 792
 793         TXMCS_TTHOLD_1_8        = 0x00000000,
 794         TXMCS_TTHOLD_1_4        = 0x00000100,
 795         TXMCS_TTHOLD_1_2        = 0x00000200,
 796         TXMCS_TTHOLD_FULL       = 0x00000300,
 797
 798         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 799                                   TXMCS_IFG1_16_8 |
 800                                   TXMCS_TTHOLD_FULL |
 801                                   TXMCS_DEFER |
 802                                   TXMCS_CRC |
 803                                   TXMCS_PADDING,
 804 };
 805
 806 enum jme_txpfc_bits_masks {
 807         TXPFC_VLAN_TAG          = 0xFFFF0000,
 808         TXPFC_VLAN_EN           = 0x00008000,
 809         TXPFC_PF_EN             = 0x00000001,
 810 };
 811
 812 enum jme_txtrhd_bits_masks {
 813         TXTRHD_TXPEN            = 0x80000000,
 814         TXTRHD_TXP              = 0x7FFFFF00,
 815         TXTRHD_TXREN            = 0x00000080,
 816         TXTRHD_TXRL             = 0x0000007F,
 817 };
 818
 819 enum jme_txtrhd_shifts {
 820         TXTRHD_TXP_SHIFT        = 8,
 821         TXTRHD_TXRL_SHIFT       = 0,
 822 };
 823
 824 enum jme_txtrhd_values {
 825         TXTRHD_FULLDUPLEX       = 0x00000000,
 826         TXTRHD_HALFDUPLEX       = TXTRHD_TXPEN |
 827                                   ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
 828                                   TXTRHD_TXREN |
 829                                   ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
 830 };
 831
 832 /*
 833  * RX Control/Status Bits
 834  */
 835 enum jme_rxcs_bit_masks {
 836         /* FIFO full threshold for transmitting Tx Pause Packet */
 837         RXCS_FIFOTHTP   = 0x30000000,
 838         /* FIFO threshold for processing next packet */
 839         RXCS_FIFOTHNP   = 0x0C000000,
 840         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 841         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 842         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 843         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 844         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 845         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 846         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 847         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 848         RXCS_QST        = 0x00000004, /* Receive queue start */
 849         RXCS_SUSPEND    = 0x00000002,
 850         RXCS_ENABLE     = 0x00000001,
 851 };
 852
 853 enum jme_rxcs_values {
 854         RXCS_FIFOTHTP_16T       = 0x00000000,
 855         RXCS_FIFOTHTP_32T       = 0x10000000,
 856         RXCS_FIFOTHTP_64T       = 0x20000000,
 857         RXCS_FIFOTHTP_128T      = 0x30000000,
 858
 859         RXCS_FIFOTHNP_16QW      = 0x00000000,
 860         RXCS_FIFOTHNP_32QW      = 0x04000000,
 861         RXCS_FIFOTHNP_64QW      = 0x08000000,
 862         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 863
 864         RXCS_DMAREQSZ_16B       = 0x00000000,
 865         RXCS_DMAREQSZ_32B       = 0x01000000,
 866         RXCS_DMAREQSZ_64B       = 0x02000000,
 867         RXCS_DMAREQSZ_128B      = 0x03000000,
 868
 869         RXCS_QUEUESEL_Q0        = 0x00000000,
 870         RXCS_QUEUESEL_Q1        = 0x00010000,
 871         RXCS_QUEUESEL_Q2        = 0x00020000,
 872         RXCS_QUEUESEL_Q3        = 0x00030000,
 873
 874         RXCS_RETRYGAP_256ns     = 0x00000000,
 875         RXCS_RETRYGAP_512ns     = 0x00001000,
 876         RXCS_RETRYGAP_1024ns    = 0x00002000,
 877         RXCS_RETRYGAP_2048ns    = 0x00003000,
 878         RXCS_RETRYGAP_4096ns    = 0x00004000,
 879         RXCS_RETRYGAP_8192ns    = 0x00005000,
 880         RXCS_RETRYGAP_16384ns   = 0x00006000,
 881         RXCS_RETRYGAP_32768ns   = 0x00007000,
 882
 883         RXCS_RETRYCNT_0         = 0x00000000,
 884         RXCS_RETRYCNT_4         = 0x00000100,
 885         RXCS_RETRYCNT_8         = 0x00000200,
 886         RXCS_RETRYCNT_12        = 0x00000300,
 887         RXCS_RETRYCNT_16        = 0x00000400,
 888         RXCS_RETRYCNT_20        = 0x00000500,
 889         RXCS_RETRYCNT_24        = 0x00000600,
 890         RXCS_RETRYCNT_28        = 0x00000700,
 891         RXCS_RETRYCNT_32        = 0x00000800,
 892         RXCS_RETRYCNT_36        = 0x00000900,
 893         RXCS_RETRYCNT_40        = 0x00000A00,
 894         RXCS_RETRYCNT_44        = 0x00000B00,
 895         RXCS_RETRYCNT_48        = 0x00000C00,
 896         RXCS_RETRYCNT_52        = 0x00000D00,
 897         RXCS_RETRYCNT_56        = 0x00000E00,
 898         RXCS_RETRYCNT_60        = 0x00000F00,
 899
 900         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 901                                   RXCS_FIFOTHNP_128QW |
 902                                   RXCS_DMAREQSZ_128B |
 903                                   RXCS_RETRYGAP_256ns |
 904                                   RXCS_RETRYCNT_32,
 905 };
 906
 907 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 908
 909 /*
 910  * RX MAC Control/Status Bits
 911  */
 912 enum jme_rxmcs_bits {
 913         RXMCS_ALLFRAME          = 0x00000800,
 914         RXMCS_BRDFRAME          = 0x00000400,
 915         RXMCS_MULFRAME          = 0x00000200,
 916         RXMCS_UNIFRAME          = 0x00000100,
 917         RXMCS_ALLMULFRAME       = 0x00000080,
 918         RXMCS_MULFILTERED       = 0x00000040,
 919         RXMCS_RXCOLLDEC         = 0x00000020,
 920         RXMCS_FLOWCTRL          = 0x00000008,
 921         RXMCS_VTAGRM            = 0x00000004,
 922         RXMCS_PREPAD            = 0x00000002,
 923         RXMCS_CHECKSUM          = 0x00000001,
 924
 925         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 926                                   RXMCS_PREPAD |
 927                                   RXMCS_FLOWCTRL |
 928                                   RXMCS_CHECKSUM,
 929 };
 930
 931 /*
 932  * Wakeup Frame setup interface registers
 933  */
 934 #define WAKEUP_FRAME_NR 8
 935 #define WAKEUP_FRAME_MASK_DWNR  4
 936
 937 enum jme_wfoi_bit_masks {
 938         WFOI_MASK_SEL           = 0x00000070,
 939         WFOI_CRC_SEL            = 0x00000008,
 940         WFOI_FRAME_SEL          = 0x00000007,
 941 };
 942
 943 enum jme_wfoi_shifts {
 944         WFOI_MASK_SHIFT         = 4,
 945 };
 946
 947 /*
 948  * SMI Related definitions
 949  */
 950 enum jme_smi_bit_mask {
 951         SMI_DATA_MASK           = 0xFFFF0000,
 952         SMI_REG_ADDR_MASK       = 0x0000F800,
 953         SMI_PHY_ADDR_MASK       = 0x000007C0,
 954         SMI_OP_WRITE            = 0x00000020,
 955         /* Set to 1, after req done it'll be cleared to 0 */
 956         SMI_OP_REQ              = 0x00000010,
 957         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 958         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 959         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 960         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 961 };
 962
 963 enum jme_smi_bit_shift {
 964         SMI_DATA_SHIFT          = 16,
 965         SMI_REG_ADDR_SHIFT      = 11,
 966         SMI_PHY_ADDR_SHIFT      = 6,
 967 };
 968
 969 static inline u32 smi_reg_addr(int x)
 970 {
 971         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 972 }
 973
 974 static inline u32 smi_phy_addr(int x)
 975 {
 976         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 977 }
 978
 979 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 980 #define JME_PHY_REG_NR 32
 981
 982 /*
 983  * Global Host Control
 984  */
 985 enum jme_ghc_bit_mask {
 986         GHC_SWRST               = 0x40000000,
 987         GHC_TO_CLK_SRC          = 0x00C00000,
 988         GHC_TXMAC_CLK_SRC       = 0x00300000,
 989         GHC_DPX                 = 0x00000040,
 990         GHC_SPEED               = 0x00000030,
 991         GHC_LINK_POLL           = 0x00000001,
 992 };
 993
 994 enum jme_ghc_speed_val {
 995         GHC_SPEED_10M           = 0x00000010,
 996         GHC_SPEED_100M          = 0x00000020,
 997         GHC_SPEED_1000M         = 0x00000030,
 998 };
 999
1000 enum jme_ghc_to_clk {
1001         GHC_TO_CLK_OFF          = 0x00000000,
1002         GHC_TO_CLK_GPHY         = 0x00400000,
1003         GHC_TO_CLK_PCIE         = 0x00800000,
1004         GHC_TO_CLK_INVALID      = 0x00C00000,
1005 };
1006
1007 enum jme_ghc_txmac_clk {
1008         GHC_TXMAC_CLK_OFF       = 0x00000000,
1009         GHC_TXMAC_CLK_GPHY      = 0x00100000,
1010         GHC_TXMAC_CLK_PCIE      = 0x00200000,
1011         GHC_TXMAC_CLK_INVALID   = 0x00300000,
1012 };
1013
1014 /*
1015  * Power management control and status register
1016  */
1017 enum jme_pmcs_bit_masks {
1018         PMCS_STMASK     = 0xFFFF0000,
1019         PMCS_WF7DET     = 0x80000000,
1020         PMCS_WF6DET     = 0x40000000,
1021         PMCS_WF5DET     = 0x20000000,
1022         PMCS_WF4DET     = 0x10000000,
1023         PMCS_WF3DET     = 0x08000000,
1024         PMCS_WF2DET     = 0x04000000,
1025         PMCS_WF1DET     = 0x02000000,
1026         PMCS_WF0DET     = 0x01000000,
1027         PMCS_LFDET      = 0x00040000,
1028         PMCS_LRDET      = 0x00020000,
1029         PMCS_MFDET      = 0x00010000,
1030         PMCS_ENMASK     = 0x0000FFFF,
1031         PMCS_WF7EN      = 0x00008000,
1032         PMCS_WF6EN      = 0x00004000,
1033         PMCS_WF5EN      = 0x00002000,
1034         PMCS_WF4EN      = 0x00001000,
1035         PMCS_WF3EN      = 0x00000800,
1036         PMCS_WF2EN      = 0x00000400,
1037         PMCS_WF1EN      = 0x00000200,
1038         PMCS_WF0EN      = 0x00000100,
1039         PMCS_LFEN       = 0x00000004,
1040         PMCS_LREN       = 0x00000002,
1041         PMCS_MFEN       = 0x00000001,
1042 };
1043
1044 /*
1045  * New PHY Power Control Register
1046  */
1047 enum jme_phy_pwr_bit_masks {
1048         PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1049         PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1050         PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1051         PHY_PWR_CLKSEL  = 0x08000000, /*
1052                                        * XTL_OUT Clock select
1053                                        * (an internal free-running clock)
1054                                        * 0: xtl_out = phy_giga.A_XTL25_O
1055                                        * 1: xtl_out = phy_giga.PD_OSC
1056                                        */
1057 };
1058
1059 /*
1060  * Giga PHY Status Registers
1061  */
1062 enum jme_phy_link_bit_mask {
1063         PHY_LINK_SPEED_MASK             = 0x0000C000,
1064         PHY_LINK_DUPLEX                 = 0x00002000,
1065         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
1066         PHY_LINK_UP                     = 0x00000400,
1067         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
1068         PHY_LINK_MDI_STAT               = 0x00000040,
1069 };
1070
1071 enum jme_phy_link_speed_val {
1072         PHY_LINK_SPEED_10M              = 0x00000000,
1073         PHY_LINK_SPEED_100M             = 0x00004000,
1074         PHY_LINK_SPEED_1000M            = 0x00008000,
1075 };
1076
1077 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
1078
1079 /*
1080  * SMB Control and Status
1081  */
1082 enum jme_smbcsr_bit_mask {
1083         SMBCSR_CNACK    = 0x00020000,
1084         SMBCSR_RELOAD   = 0x00010000,
1085         SMBCSR_EEPROMD  = 0x00000020,
1086         SMBCSR_INITDONE = 0x00000010,
1087         SMBCSR_BUSY     = 0x0000000F,
1088 };
1089
1090 enum jme_smbintf_bit_mask {
1091         SMBINTF_HWDATR  = 0xFF000000,
1092         SMBINTF_HWDATW  = 0x00FF0000,
1093         SMBINTF_HWADDR  = 0x0000FF00,
1094         SMBINTF_HWRWN   = 0x00000020,
1095         SMBINTF_HWCMD   = 0x00000010,
1096         SMBINTF_FASTM   = 0x00000008,
1097         SMBINTF_GPIOSCL = 0x00000004,
1098         SMBINTF_GPIOSDA = 0x00000002,
1099         SMBINTF_GPIOEN  = 0x00000001,
1100 };
1101
1102 enum jme_smbintf_vals {
1103         SMBINTF_HWRWN_READ      = 0x00000020,
1104         SMBINTF_HWRWN_WRITE     = 0x00000000,
1105 };
1106
1107 enum jme_smbintf_shifts {
1108         SMBINTF_HWDATR_SHIFT    = 24,
1109         SMBINTF_HWDATW_SHIFT    = 16,
1110         SMBINTF_HWADDR_SHIFT    = 8,
1111 };
1112
1113 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1114 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1115 #define JME_SMB_LEN 256
1116 #define JME_EEPROM_MAGIC 0x250
1117
1118 /*
1119  * Timer Control/Status Register
1120  */
1121 enum jme_tmcsr_bit_masks {
1122         TMCSR_SWIT      = 0x80000000,
1123         TMCSR_EN        = 0x01000000,
1124         TMCSR_CNT       = 0x00FFFFFF,
1125 };
1126
1127 /*
1128  * General Purpose REG-0
1129  */
1130 enum jme_gpreg0_masks {
1131         GPREG0_DISSH            = 0xFF000000,
1132         GPREG0_PCIRLMT          = 0x00300000,
1133         GPREG0_PCCNOMUTCLR      = 0x00040000,
1134         GPREG0_LNKINTPOLL       = 0x00001000,
1135         GPREG0_PCCTMR           = 0x00000300,
1136         GPREG0_PHYADDR          = 0x0000001F,
1137 };
1138
1139 enum jme_gpreg0_vals {
1140         GPREG0_DISSH_DW7        = 0x80000000,
1141         GPREG0_DISSH_DW6        = 0x40000000,
1142         GPREG0_DISSH_DW5        = 0x20000000,
1143         GPREG0_DISSH_DW4        = 0x10000000,
1144         GPREG0_DISSH_DW3        = 0x08000000,
1145         GPREG0_DISSH_DW2        = 0x04000000,
1146         GPREG0_DISSH_DW1        = 0x02000000,
1147         GPREG0_DISSH_DW0        = 0x01000000,
1148         GPREG0_DISSH_ALL        = 0xFF000000,
1149
1150         GPREG0_PCIRLMT_8        = 0x00000000,
1151         GPREG0_PCIRLMT_6        = 0x00100000,
1152         GPREG0_PCIRLMT_5        = 0x00200000,
1153         GPREG0_PCIRLMT_4        = 0x00300000,
1154
1155         GPREG0_PCCTMR_16ns      = 0x00000000,
1156         GPREG0_PCCTMR_256ns     = 0x00000100,
1157         GPREG0_PCCTMR_1us       = 0x00000200,
1158         GPREG0_PCCTMR_1ms       = 0x00000300,
1159
1160         GPREG0_PHYADDR_1        = 0x00000001,
1161
1162         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1163                                   GPREG0_PCCTMR_1us |
1164                                   GPREG0_PHYADDR_1,
1165 };
1166
1167 /*
1168  * General Purpose REG-1
1169  */
1170 enum jme_gpreg1_bit_masks {
1171         GPREG1_RXCLKOFF         = 0x04000000,
1172         GPREG1_PCREQN           = 0x00020000,
1173         GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
1174         GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
1175         GPREG1_INTRDELAYUNIT    = 0x00000018,
1176         GPREG1_INTRDELAYENABLE  = 0x00000007,
1177 };
1178
1179 enum jme_gpreg1_vals {
1180         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1181         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1182         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1183         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1184
1185         GPREG1_INTDLYEN_1U      = 0x00000001,
1186         GPREG1_INTDLYEN_2U      = 0x00000002,
1187         GPREG1_INTDLYEN_3U      = 0x00000003,
1188         GPREG1_INTDLYEN_4U      = 0x00000004,
1189         GPREG1_INTDLYEN_5U      = 0x00000005,
1190         GPREG1_INTDLYEN_6U      = 0x00000006,
1191         GPREG1_INTDLYEN_7U      = 0x00000007,
1192
1193         GPREG1_DEFAULT          = GPREG1_PCREQN,
1194 };
1195
1196 /*
1197  * Interrupt Status Bits
1198  */
1199 enum jme_interrupt_bits {
1200         INTR_SWINTR     = 0x80000000,
1201         INTR_TMINTR     = 0x40000000,
1202         INTR_LINKCH     = 0x20000000,
1203         INTR_PAUSERCV   = 0x10000000,
1204         INTR_MAGICRCV   = 0x08000000,
1205         INTR_WAKERCV    = 0x04000000,
1206         INTR_PCCRX0TO   = 0x02000000,
1207         INTR_PCCRX1TO   = 0x01000000,
1208         INTR_PCCRX2TO   = 0x00800000,
1209         INTR_PCCRX3TO   = 0x00400000,
1210         INTR_PCCTXTO    = 0x00200000,
1211         INTR_PCCRX0     = 0x00100000,
1212         INTR_PCCRX1     = 0x00080000,
1213         INTR_PCCRX2     = 0x00040000,
1214         INTR_PCCRX3     = 0x00020000,
1215         INTR_PCCTX      = 0x00010000,
1216         INTR_RX3EMP     = 0x00008000,
1217         INTR_RX2EMP     = 0x00004000,
1218         INTR_RX1EMP     = 0x00002000,
1219         INTR_RX0EMP     = 0x00001000,
1220         INTR_RX3        = 0x00000800,
1221         INTR_RX2        = 0x00000400,
1222         INTR_RX1        = 0x00000200,
1223         INTR_RX0        = 0x00000100,
1224         INTR_TX7        = 0x00000080,
1225         INTR_TX6        = 0x00000040,
1226         INTR_TX5        = 0x00000020,
1227         INTR_TX4        = 0x00000010,
1228         INTR_TX3        = 0x00000008,
1229         INTR_TX2        = 0x00000004,
1230         INTR_TX1        = 0x00000002,
1231         INTR_TX0        = 0x00000001,
1232 };
1233
1234 static const u32 INTR_ENABLE = INTR_SWINTR |
1235                                  INTR_TMINTR |
1236                                  INTR_LINKCH |
1237                                  INTR_PCCRX0TO |
1238                                  INTR_PCCRX0 |
1239                                  INTR_PCCTXTO |
1240                                  INTR_PCCTX |
1241                                  INTR_RX0EMP;
1242
1243 /*
1244  * PCC Control Registers
1245  */
1246 enum jme_pccrx_masks {
1247         PCCRXTO_MASK    = 0xFFFF0000,
1248         PCCRX_MASK      = 0x0000FF00,
1249 };
1250
1251 enum jme_pcctx_masks {
1252         PCCTXTO_MASK    = 0xFFFF0000,
1253         PCCTX_MASK      = 0x0000FF00,
1254         PCCTX_QS_MASK   = 0x000000FF,
1255 };
1256
1257 enum jme_pccrx_shifts {
1258         PCCRXTO_SHIFT   = 16,
1259         PCCRX_SHIFT     = 8,
1260 };
1261
1262 enum jme_pcctx_shifts {
1263         PCCTXTO_SHIFT   = 16,
1264         PCCTX_SHIFT     = 8,
1265 };
1266
1267 enum jme_pcctx_bits {
1268         PCCTXQ0_EN      = 0x00000001,
1269         PCCTXQ1_EN      = 0x00000002,
1270         PCCTXQ2_EN      = 0x00000004,
1271         PCCTXQ3_EN      = 0x00000008,
1272         PCCTXQ4_EN      = 0x00000010,
1273         PCCTXQ5_EN      = 0x00000020,
1274         PCCTXQ6_EN      = 0x00000040,
1275         PCCTXQ7_EN      = 0x00000080,
1276 };
1277
1278 /*
1279  * Chip Mode Register
1280  */
1281 enum jme_chipmode_bit_masks {
1282         CM_FPGAVER_MASK         = 0xFFFF0000,
1283         CM_CHIPREV_MASK         = 0x0000FF00,
1284         CM_CHIPMODE_MASK        = 0x0000000F,
1285 };
1286
1287 enum jme_chipmode_shifts {
1288         CM_FPGAVER_SHIFT        = 16,
1289         CM_CHIPREV_SHIFT        = 8,
1290 };
1291
1292 /*
1293  * Aggressive Power Mode Control
1294  */
1295 enum jme_apmc_bits {
1296         JME_APMC_PCIE_SD_EN     = 0x40000000,
1297         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1298         JME_APMC_EPIEN          = 0x04000000,
1299         JME_APMC_EPIEN_CTRL     = 0x03000000,
1300 };
1301
1302 enum jme_apmc_values {
1303         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1304         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1305 };
1306
1307 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1308
1309 #ifdef REG_DEBUG
1310 static char *MAC_REG_NAME[] = {
1311         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1312         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1313         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1314         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1315         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1316         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1317         "JME_PMCS"};
1318
1319 static char *PE_REG_NAME[] = {
1320         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1321         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1322         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1323         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1324         "JME_SMBCSR",   "JME_SMBINTF"};
1325
1326 static char *MISC_REG_NAME[] = {
1327         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1328         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1329         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1330         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1331         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1332         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1333         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1334         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1335         "JME_PCCSRX0"};
1336
1337 static inline void reg_dbg(const struct jme_adapter *jme,
1338                 const char *msg, u32 val, u32 reg)
1339 {
1340         const char *regname;
1341         switch (reg & 0xF00) {
1342         case 0x000:
1343                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1344                 break;
1345         case 0x400:
1346                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1347                 break;
1348         case 0x800:
1349                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1350                 break;
1351         default:
1352                 regname = PE_REG_NAME[0];
1353         }
1354         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1355                         msg, val, regname);
1356 }
1357 #else
1358 static inline void reg_dbg(const struct jme_adapter *jme,
1359                 const char *msg, u32 val, u32 reg) {}
1360 #endif
1361
1362 /*
1363  * Read/Write MMaped I/O Registers
1364  */
1365 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1366 {
1367         return readl(jme->regs + reg);
1368 }
1369
1370 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1371 {
1372         reg_dbg(jme, "REG WRITE", val, reg);
1373         writel(val, jme->regs + reg);
1374         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1375 }
1376
1377 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1378 {
1379         /*
1380          * Read after write should cause flush
1381          */
1382         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1383         writel(val, jme->regs + reg);
1384         readl(jme->regs + reg);
1385         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1386 }
1387
1388 /*
1389  * PHY Regs
1390  */
1391 enum jme_phy_reg17_bit_masks {
1392         PREG17_SPEED            = 0xC000,
1393         PREG17_DUPLEX           = 0x2000,
1394         PREG17_SPDRSV           = 0x0800,
1395         PREG17_LNKUP            = 0x0400,
1396         PREG17_MDI              = 0x0040,
1397 };
1398
1399 enum jme_phy_reg17_vals {
1400         PREG17_SPEED_10M        = 0x0000,
1401         PREG17_SPEED_100M       = 0x4000,
1402         PREG17_SPEED_1000M      = 0x8000,
1403 };
1404
1405 #define BMSR_ANCOMP               0x0020
1406
1407 /*
1408  * Workaround
1409  */
1410 static inline int is_buggy250(unsigned short device, u8 chiprev)
1411 {
1412         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1413 }
1414
1415 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1416 {
1417         return chip_main_rev >= 5;
1418 }
1419
1420 /*
1421  * Function prototypes
1422  */
1423 static int jme_set_settings(struct net_device *netdev,
1424                                 struct ethtool_cmd *ecmd);
1425 static void jme_set_unicastaddr(struct net_device *netdev);
1426 static void jme_set_multi(struct net_device *netdev);
1427
1428 #endif
1429