Import jme 1.0.6-backport source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME        "jme"
28 #define DRV_VERSION     "1.0.6-jmmod"
29 #define PFX             DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
33
34 /*
35  * Message related definitions
36  */
37 #define JME_DEF_MSG_ENABLE \
38         (NETIF_MSG_PROBE | \
39         NETIF_MSG_LINK | \
40         NETIF_MSG_RX_ERR | \
41         NETIF_MSG_TX_ERR | \
42         NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45         printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...)                                      \
49         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
50 #else
51 #define tx_dbg(priv, fmt, args...)                                      \
52 do {                                                                    \
53         if (0)                                                          \
54                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
55 } while (0)
56 #endif
57
58 #include <linux/version.h>
59 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
60 #define jme_msg(msglvl, type, priv, fmt, args...) \
61         if (netif_msg_##type(priv)) \
62                 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
63
64 #define msg_probe(priv, fmt, args...) \
65         jme_msg(KERN_INFO, probe, priv, fmt, ## args)
66
67 #define msg_link(priv, fmt, args...) \
68         jme_msg(KERN_INFO, link, priv, fmt, ## args)
69
70 #define msg_intr(priv, fmt, args...) \
71         jme_msg(KERN_INFO, intr, priv, fmt, ## args)
72
73 #define msg_rx_err(priv, fmt, args...) \
74         jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
75
76 #define msg_rx_status(priv, fmt, args...) \
77         jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
78
79 #define msg_tx_err(priv, fmt, args...) \
80         jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
81
82 #define msg_tx_done(priv, fmt, args...) \
83         jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
84
85 #define msg_tx_queued(priv, fmt, args...) \
86         jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
87
88 #define msg_hw(priv, fmt, args...) \
89         jme_msg(KERN_ERR, hw, priv, fmt, ## args)
90 #endif
91
92 /*
93  * Extra PCI Configuration space interface
94  */
95 #define PCI_DCSR_MRRS           0x59
96 #define PCI_DCSR_MRRS_MASK      0x70
97
98 enum pci_dcsr_mrrs_vals {
99         MRRS_128B       = 0x00,
100         MRRS_256B       = 0x10,
101         MRRS_512B       = 0x20,
102         MRRS_1024B      = 0x30,
103         MRRS_2048B      = 0x40,
104         MRRS_4096B      = 0x50,
105 };
106
107 #define PCI_SPI                 0xB0
108
109 enum pci_spi_bits {
110         SPI_EN          = 0x10,
111         SPI_MISO        = 0x08,
112         SPI_MOSI        = 0x04,
113         SPI_SCLK        = 0x02,
114         SPI_CS          = 0x01,
115 };
116
117 struct jme_spi_op {
118         void __user *uwbuf;
119         void __user *urbuf;
120         __u8    wn;     /* Number of write actions */
121         __u8    rn;     /* Number of read actions */
122         __u8    bitn;   /* Number of bits per action */
123         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
124         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
125
126         /* Internal use only */
127         u8      *kwbuf;
128         u8      *krbuf;
129         u8      sr;
130         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
131 };
132
133 enum jme_spi_op_bits {
134         SPI_MODE_CPHA   = 0x01,
135         SPI_MODE_CPOL   = 0x02,
136         SPI_MODE_DUP    = 0x80,
137 };
138
139 #define HALF_US 500     /* 500 ns */
140 #define JMESPIIOCTL     SIOCDEVPRIVATE
141
142 /*
143  * Dynamic(adaptive)/Static PCC values
144  */
145 enum dynamic_pcc_values {
146         PCC_OFF         = 0,
147         PCC_P1          = 1,
148         PCC_P2          = 2,
149         PCC_P3          = 3,
150
151         PCC_OFF_TO      = 0,
152         PCC_P1_TO       = 1,
153         PCC_P2_TO       = 64,
154         PCC_P3_TO       = 128,
155
156         PCC_OFF_CNT     = 0,
157         PCC_P1_CNT      = 1,
158         PCC_P2_CNT      = 16,
159         PCC_P3_CNT      = 32,
160 };
161 struct dynpcc_info {
162         unsigned long   last_bytes;
163         unsigned long   last_pkts;
164         unsigned long   intr_cnt;
165         unsigned char   cur;
166         unsigned char   attempt;
167         unsigned char   cnt;
168 };
169 #define PCC_INTERVAL_US 100000
170 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
171 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
172 #define PCC_P2_THRESHOLD 800
173 #define PCC_INTR_THRESHOLD 800
174 #define PCC_TX_TO 1000
175 #define PCC_TX_CNT 8
176
177 /*
178  * TX/RX Descriptors
179  *
180  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
181  */
182 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
183 #define TX_DESC_SIZE            16
184 #define TX_RING_NR              8
185 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
186
187 struct txdesc {
188         union {
189                 __u8    all[16];
190                 __le32  dw[4];
191                 struct {
192                         /* DW0 */
193                         __le16  vlan;
194                         __u8    rsv1;
195                         __u8    flags;
196
197                         /* DW1 */
198                         __le16  datalen;
199                         __le16  mss;
200
201                         /* DW2 */
202                         __le16  pktsize;
203                         __le16  rsv2;
204
205                         /* DW3 */
206                         __le32  bufaddr;
207                 } desc1;
208                 struct {
209                         /* DW0 */
210                         __le16  rsv1;
211                         __u8    rsv2;
212                         __u8    flags;
213
214                         /* DW1 */
215                         __le16  datalen;
216                         __le16  rsv3;
217
218                         /* DW2 */
219                         __le32  bufaddrh;
220
221                         /* DW3 */
222                         __le32  bufaddrl;
223                 } desc2;
224                 struct {
225                         /* DW0 */
226                         __u8    ehdrsz;
227                         __u8    rsv1;
228                         __u8    rsv2;
229                         __u8    flags;
230
231                         /* DW1 */
232                         __le16  trycnt;
233                         __le16  segcnt;
234
235                         /* DW2 */
236                         __le16  pktsz;
237                         __le16  rsv3;
238
239                         /* DW3 */
240                         __le32  bufaddrl;
241                 } descwb;
242         };
243 };
244
245 enum jme_txdesc_flags_bits {
246         TXFLAG_OWN      = 0x80,
247         TXFLAG_INT      = 0x40,
248         TXFLAG_64BIT    = 0x20,
249         TXFLAG_TCPCS    = 0x10,
250         TXFLAG_UDPCS    = 0x08,
251         TXFLAG_IPCS     = 0x04,
252         TXFLAG_LSEN     = 0x02,
253         TXFLAG_TAGON    = 0x01,
254 };
255
256 #define TXDESC_MSS_SHIFT        2
257 enum jme_txwbdesc_flags_bits {
258         TXWBFLAG_OWN    = 0x80,
259         TXWBFLAG_INT    = 0x40,
260         TXWBFLAG_TMOUT  = 0x20,
261         TXWBFLAG_TRYOUT = 0x10,
262         TXWBFLAG_COL    = 0x08,
263
264         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
265                           TXWBFLAG_TRYOUT |
266                           TXWBFLAG_COL,
267 };
268
269 #define RX_DESC_SIZE            16
270 #define RX_RING_NR              4
271 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
272 #define RX_BUF_DMA_ALIGN        8
273 #define RX_PREPAD_SIZE          10
274 #define ETH_CRC_LEN             2
275 #define RX_VLANHDR_LEN          2
276 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
277                                 ETH_HLEN + \
278                                 ETH_CRC_LEN + \
279                                 RX_VLANHDR_LEN + \
280                                 RX_BUF_DMA_ALIGN)
281
282 struct rxdesc {
283         union {
284                 __u8    all[16];
285                 __le32  dw[4];
286                 struct {
287                         /* DW0 */
288                         __le16  rsv2;
289                         __u8    rsv1;
290                         __u8    flags;
291
292                         /* DW1 */
293                         __le16  datalen;
294                         __le16  wbcpl;
295
296                         /* DW2 */
297                         __le32  bufaddrh;
298
299                         /* DW3 */
300                         __le32  bufaddrl;
301                 } desc1;
302                 struct {
303                         /* DW0 */
304                         __le16  vlan;
305                         __le16  flags;
306
307                         /* DW1 */
308                         __le16  framesize;
309                         __u8    errstat;
310                         __u8    desccnt;
311
312                         /* DW2 */
313                         __le32  rsshash;
314
315                         /* DW3 */
316                         __u8    hashfun;
317                         __u8    hashtype;
318                         __le16  resrv;
319                 } descwb;
320         };
321 };
322
323 enum jme_rxdesc_flags_bits {
324         RXFLAG_OWN      = 0x80,
325         RXFLAG_INT      = 0x40,
326         RXFLAG_64BIT    = 0x20,
327 };
328
329 enum jme_rxwbdesc_flags_bits {
330         RXWBFLAG_OWN            = 0x8000,
331         RXWBFLAG_INT            = 0x4000,
332         RXWBFLAG_MF             = 0x2000,
333         RXWBFLAG_64BIT          = 0x2000,
334         RXWBFLAG_TCPON          = 0x1000,
335         RXWBFLAG_UDPON          = 0x0800,
336         RXWBFLAG_IPCS           = 0x0400,
337         RXWBFLAG_TCPCS          = 0x0200,
338         RXWBFLAG_UDPCS          = 0x0100,
339         RXWBFLAG_TAGON          = 0x0080,
340         RXWBFLAG_IPV4           = 0x0040,
341         RXWBFLAG_IPV6           = 0x0020,
342         RXWBFLAG_PAUSE          = 0x0010,
343         RXWBFLAG_MAGIC          = 0x0008,
344         RXWBFLAG_WAKEUP         = 0x0004,
345         RXWBFLAG_DEST           = 0x0003,
346         RXWBFLAG_DEST_UNI       = 0x0001,
347         RXWBFLAG_DEST_MUL       = 0x0002,
348         RXWBFLAG_DEST_BRO       = 0x0003,
349 };
350
351 enum jme_rxwbdesc_desccnt_mask {
352         RXWBDCNT_WBCPL  = 0x80,
353         RXWBDCNT_DCNT   = 0x7F,
354 };
355
356 enum jme_rxwbdesc_errstat_bits {
357         RXWBERR_LIMIT   = 0x80,
358         RXWBERR_MIIER   = 0x40,
359         RXWBERR_NIBON   = 0x20,
360         RXWBERR_COLON   = 0x10,
361         RXWBERR_ABORT   = 0x08,
362         RXWBERR_SHORT   = 0x04,
363         RXWBERR_OVERUN  = 0x02,
364         RXWBERR_CRCERR  = 0x01,
365         RXWBERR_ALLERR  = 0xFF,
366 };
367
368 /*
369  * Buffer information corresponding to ring descriptors.
370  */
371 struct jme_buffer_info {
372         struct sk_buff *skb;
373         dma_addr_t mapping;
374         int len;
375         int nr_desc;
376         unsigned long start_xmit;
377 };
378
379 /*
380  * The structure holding buffer information and ring descriptors all together.
381  */
382 struct jme_ring {
383         void *alloc;            /* pointer to allocated memory */
384         void *desc;             /* pointer to ring memory  */
385         dma_addr_t dmaalloc;    /* phys address of ring alloc */
386         dma_addr_t dma;         /* phys address for ring dma */
387
388         /* Buffer information corresponding to each descriptor */
389         struct jme_buffer_info *bufinf;
390
391         int next_to_use;
392         atomic_t next_to_clean;
393         atomic_t nr_free;
394 };
395
396 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
397 #define false 0
398 #define true 0
399 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
400 #define PCI_VENDOR_ID_JMICRON           0x197B
401 #endif
402
403 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
404 #define PCI_VDEVICE(vendor, device)             \
405         PCI_VENDOR_ID_##vendor, (device),       \
406         PCI_ANY_ID, PCI_ANY_ID, 0, 0
407 #endif
408
409 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
410 #define NET_STAT(priv) priv->stats
411 #define NETDEV_GET_STATS(netdev, fun_ptr) \
412         netdev->get_stats = fun_ptr
413 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
414 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
415 {
416         return skb->nh.iph;
417 }
418
419 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
420 {
421         return skb->nh.ipv6h;
422 }
423
424 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
425 {
426         return skb->h.th;
427 }
428 #else
429 #define NET_STAT(priv) (priv->dev->stats)
430 #define NETDEV_GET_STATS(netdev, fun_ptr)
431 #define DECLARE_NET_DEVICE_STATS
432 #endif
433
434 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
435 #define DECLARE_NAPI_STRUCT
436 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
437         dev->poll = pollfn; \
438         dev->weight = q;
439 #define JME_NAPI_HOLDER(holder) struct net_device *holder
440 #define JME_NAPI_WEIGHT(w) int *w
441 #define JME_NAPI_WEIGHT_VAL(w) *w
442 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
443 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
444 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
445 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
446 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
447 #define JME_RX_SCHEDULE_PREP(priv) \
448         netif_rx_schedule_prep(priv->dev)
449 #define JME_RX_SCHEDULE(priv) \
450         __netif_rx_schedule(priv->dev);
451 #else
452 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
453 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
454         netif_napi_add(dev, napis, pollfn, q);
455 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
456 #define JME_NAPI_WEIGHT(w) int w
457 #define JME_NAPI_WEIGHT_VAL(w) w
458 #define JME_NAPI_WEIGHT_SET(w, r)
459 #define DECLARE_NETDEV
460 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
461 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
462 #define JME_NAPI_DISABLE(priv) \
463         if (!napi_disable_pending(&priv->napi)) \
464                 napi_disable(&priv->napi);
465 #define JME_RX_SCHEDULE_PREP(priv) \
466         napi_schedule_prep(&priv->napi)
467 #define JME_RX_SCHEDULE(priv) \
468         __napi_schedule(&priv->napi);
469 #endif
470
471 /*
472  * Jmac Adapter Private data
473  */
474 struct jme_adapter {
475         struct pci_dev          *pdev;
476         struct net_device       *dev;
477         void __iomem            *regs;
478         struct mii_if_info      mii_if;
479         struct jme_ring         rxring[RX_RING_NR];
480         struct jme_ring         txring[TX_RING_NR];
481         spinlock_t              phy_lock;
482         spinlock_t              macaddr_lock;
483         spinlock_t              rxmcs_lock;
484         spinlock_t              vlgrp_lock;
485         struct tasklet_struct   rxempty_task;
486         struct tasklet_struct   rxclean_task;
487         struct tasklet_struct   txclean_task;
488         struct tasklet_struct   linkch_task;
489         struct tasklet_struct   pcc_task;
490         unsigned long           flags;
491         u32                     reg_txcs;
492         u32                     reg_txpfc;
493         u32                     reg_rxcs;
494         u32                     reg_rxmcs;
495         u32                     reg_ghc;
496         u32                     reg_pmcs;
497         u32                     phylink;
498         u32                     tx_ring_size;
499         u32                     tx_ring_mask;
500         u32                     tx_wake_threshold;
501         u32                     rx_ring_size;
502         u32                     rx_ring_mask;
503         u8                      mrrs;
504         unsigned int            fpgaver;
505         unsigned int            chiprev;
506         u8                      rev;
507         u32                     msg_enable;
508         struct ethtool_cmd      old_ecmd;
509         unsigned int            old_mtu;
510         struct vlan_group       *vlgrp;
511         struct dynpcc_info      dpi;
512         atomic_t                intr_sem;
513         atomic_t                link_changing;
514         atomic_t                tx_cleaning;
515         atomic_t                rx_cleaning;
516         atomic_t                rx_empty;
517         int                     (*jme_rx)(struct sk_buff *skb);
518         int                     (*jme_vlan_rx)(struct sk_buff *skb,
519                                           struct vlan_group *grp,
520                                           unsigned short vlan_tag);
521         DECLARE_NAPI_STRUCT
522         DECLARE_NET_DEVICE_STATS
523 };
524
525 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
526 static struct net_device_stats *
527 jme_get_stats(struct net_device *netdev)
528 {
529         struct jme_adapter *jme = netdev_priv(netdev);
530         return &jme->stats;
531 }
532 #endif
533
534 enum jme_flags_bits {
535         JME_FLAG_MSI            = 1,
536         JME_FLAG_SSET           = 2,
537         JME_FLAG_TXCSUM         = 3,
538         JME_FLAG_TSO            = 4,
539         JME_FLAG_POLL           = 5,
540         JME_FLAG_SHUTDOWN       = 6,
541 };
542
543 #define TX_TIMEOUT              (5 * HZ)
544 #define JME_REG_LEN             0x500
545 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
546
547 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
548 static inline struct jme_adapter*
549 jme_napi_priv(struct net_device *holder)
550 {
551         struct jme_adapter *jme;
552         jme = netdev_priv(holder);
553         return jme;
554 }
555 #else
556 static inline struct jme_adapter*
557 jme_napi_priv(struct napi_struct *napi)
558 {
559         struct jme_adapter *jme;
560         jme = container_of(napi, struct jme_adapter, napi);
561         return jme;
562 }
563 #endif
564
565 /*
566  * MMaped I/O Resters
567  */
568 enum jme_iomap_offsets {
569         JME_MAC         = 0x0000,
570         JME_PHY         = 0x0400,
571         JME_MISC        = 0x0800,
572         JME_RSS         = 0x0C00,
573 };
574
575 enum jme_iomap_lens {
576         JME_MAC_LEN     = 0x80,
577         JME_PHY_LEN     = 0x58,
578         JME_MISC_LEN    = 0x98,
579         JME_RSS_LEN     = 0xFF,
580 };
581
582 enum jme_iomap_regs {
583         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
584         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
585         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
586         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
587         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
588         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
589         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
590         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
591
592         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
593         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
594         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
595         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
596         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
597         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
598         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
599         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
600         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
601         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
602         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
603         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
604
605         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
606         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
607         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
608
609
610         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
611         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
612         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
613         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
614
615
616         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
617         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
618         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
619         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
620         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
621         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
622         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
623         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
624         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
625         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
626         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
627         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
628         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
629         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
630         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
631         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
632 };
633
634 /*
635  * TX Control/Status Bits
636  */
637 enum jme_txcs_bits {
638         TXCS_QUEUE7S    = 0x00008000,
639         TXCS_QUEUE6S    = 0x00004000,
640         TXCS_QUEUE5S    = 0x00002000,
641         TXCS_QUEUE4S    = 0x00001000,
642         TXCS_QUEUE3S    = 0x00000800,
643         TXCS_QUEUE2S    = 0x00000400,
644         TXCS_QUEUE1S    = 0x00000200,
645         TXCS_QUEUE0S    = 0x00000100,
646         TXCS_FIFOTH     = 0x000000C0,
647         TXCS_DMASIZE    = 0x00000030,
648         TXCS_BURST      = 0x00000004,
649         TXCS_ENABLE     = 0x00000001,
650 };
651
652 enum jme_txcs_value {
653         TXCS_FIFOTH_16QW        = 0x000000C0,
654         TXCS_FIFOTH_12QW        = 0x00000080,
655         TXCS_FIFOTH_8QW         = 0x00000040,
656         TXCS_FIFOTH_4QW         = 0x00000000,
657
658         TXCS_DMASIZE_64B        = 0x00000000,
659         TXCS_DMASIZE_128B       = 0x00000010,
660         TXCS_DMASIZE_256B       = 0x00000020,
661         TXCS_DMASIZE_512B       = 0x00000030,
662
663         TXCS_SELECT_QUEUE0      = 0x00000000,
664         TXCS_SELECT_QUEUE1      = 0x00010000,
665         TXCS_SELECT_QUEUE2      = 0x00020000,
666         TXCS_SELECT_QUEUE3      = 0x00030000,
667         TXCS_SELECT_QUEUE4      = 0x00040000,
668         TXCS_SELECT_QUEUE5      = 0x00050000,
669         TXCS_SELECT_QUEUE6      = 0x00060000,
670         TXCS_SELECT_QUEUE7      = 0x00070000,
671
672         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
673                                   TXCS_BURST,
674 };
675
676 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
677
678 /*
679  * TX MAC Control/Status Bits
680  */
681 enum jme_txmcs_bit_masks {
682         TXMCS_IFG2              = 0xC0000000,
683         TXMCS_IFG1              = 0x30000000,
684         TXMCS_TTHOLD            = 0x00000300,
685         TXMCS_FBURST            = 0x00000080,
686         TXMCS_CARRIEREXT        = 0x00000040,
687         TXMCS_DEFER             = 0x00000020,
688         TXMCS_BACKOFF           = 0x00000010,
689         TXMCS_CARRIERSENSE      = 0x00000008,
690         TXMCS_COLLISION         = 0x00000004,
691         TXMCS_CRC               = 0x00000002,
692         TXMCS_PADDING           = 0x00000001,
693 };
694
695 enum jme_txmcs_values {
696         TXMCS_IFG2_6_4          = 0x00000000,
697         TXMCS_IFG2_8_5          = 0x40000000,
698         TXMCS_IFG2_10_6         = 0x80000000,
699         TXMCS_IFG2_12_7         = 0xC0000000,
700
701         TXMCS_IFG1_8_4          = 0x00000000,
702         TXMCS_IFG1_12_6         = 0x10000000,
703         TXMCS_IFG1_16_8         = 0x20000000,
704         TXMCS_IFG1_20_10        = 0x30000000,
705
706         TXMCS_TTHOLD_1_8        = 0x00000000,
707         TXMCS_TTHOLD_1_4        = 0x00000100,
708         TXMCS_TTHOLD_1_2        = 0x00000200,
709         TXMCS_TTHOLD_FULL       = 0x00000300,
710
711         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
712                                   TXMCS_IFG1_16_8 |
713                                   TXMCS_TTHOLD_FULL |
714                                   TXMCS_DEFER |
715                                   TXMCS_CRC |
716                                   TXMCS_PADDING,
717 };
718
719 enum jme_txpfc_bits_masks {
720         TXPFC_VLAN_TAG          = 0xFFFF0000,
721         TXPFC_VLAN_EN           = 0x00008000,
722         TXPFC_PF_EN             = 0x00000001,
723 };
724
725 enum jme_txtrhd_bits_masks {
726         TXTRHD_TXPEN            = 0x80000000,
727         TXTRHD_TXP              = 0x7FFFFF00,
728         TXTRHD_TXREN            = 0x00000080,
729         TXTRHD_TXRL             = 0x0000007F,
730 };
731
732 enum jme_txtrhd_shifts {
733         TXTRHD_TXP_SHIFT        = 8,
734         TXTRHD_TXRL_SHIFT       = 0,
735 };
736
737 /*
738  * RX Control/Status Bits
739  */
740 enum jme_rxcs_bit_masks {
741         /* FIFO full threshold for transmitting Tx Pause Packet */
742         RXCS_FIFOTHTP   = 0x30000000,
743         /* FIFO threshold for processing next packet */
744         RXCS_FIFOTHNP   = 0x0C000000,
745         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
746         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
747         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
748         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
749         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
750         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
751         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
752         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
753         RXCS_QST        = 0x00000004, /* Receive queue start */
754         RXCS_SUSPEND    = 0x00000002,
755         RXCS_ENABLE     = 0x00000001,
756 };
757
758 enum jme_rxcs_values {
759         RXCS_FIFOTHTP_16T       = 0x00000000,
760         RXCS_FIFOTHTP_32T       = 0x10000000,
761         RXCS_FIFOTHTP_64T       = 0x20000000,
762         RXCS_FIFOTHTP_128T      = 0x30000000,
763
764         RXCS_FIFOTHNP_16QW      = 0x00000000,
765         RXCS_FIFOTHNP_32QW      = 0x04000000,
766         RXCS_FIFOTHNP_64QW      = 0x08000000,
767         RXCS_FIFOTHNP_128QW     = 0x0C000000,
768
769         RXCS_DMAREQSZ_16B       = 0x00000000,
770         RXCS_DMAREQSZ_32B       = 0x01000000,
771         RXCS_DMAREQSZ_64B       = 0x02000000,
772         RXCS_DMAREQSZ_128B      = 0x03000000,
773
774         RXCS_QUEUESEL_Q0        = 0x00000000,
775         RXCS_QUEUESEL_Q1        = 0x00010000,
776         RXCS_QUEUESEL_Q2        = 0x00020000,
777         RXCS_QUEUESEL_Q3        = 0x00030000,
778
779         RXCS_RETRYGAP_256ns     = 0x00000000,
780         RXCS_RETRYGAP_512ns     = 0x00001000,
781         RXCS_RETRYGAP_1024ns    = 0x00002000,
782         RXCS_RETRYGAP_2048ns    = 0x00003000,
783         RXCS_RETRYGAP_4096ns    = 0x00004000,
784         RXCS_RETRYGAP_8192ns    = 0x00005000,
785         RXCS_RETRYGAP_16384ns   = 0x00006000,
786         RXCS_RETRYGAP_32768ns   = 0x00007000,
787
788         RXCS_RETRYCNT_0         = 0x00000000,
789         RXCS_RETRYCNT_4         = 0x00000100,
790         RXCS_RETRYCNT_8         = 0x00000200,
791         RXCS_RETRYCNT_12        = 0x00000300,
792         RXCS_RETRYCNT_16        = 0x00000400,
793         RXCS_RETRYCNT_20        = 0x00000500,
794         RXCS_RETRYCNT_24        = 0x00000600,
795         RXCS_RETRYCNT_28        = 0x00000700,
796         RXCS_RETRYCNT_32        = 0x00000800,
797         RXCS_RETRYCNT_36        = 0x00000900,
798         RXCS_RETRYCNT_40        = 0x00000A00,
799         RXCS_RETRYCNT_44        = 0x00000B00,
800         RXCS_RETRYCNT_48        = 0x00000C00,
801         RXCS_RETRYCNT_52        = 0x00000D00,
802         RXCS_RETRYCNT_56        = 0x00000E00,
803         RXCS_RETRYCNT_60        = 0x00000F00,
804
805         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
806                                   RXCS_FIFOTHNP_128QW |
807                                   RXCS_DMAREQSZ_128B |
808                                   RXCS_RETRYGAP_256ns |
809                                   RXCS_RETRYCNT_32,
810 };
811
812 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
813
814 /*
815  * RX MAC Control/Status Bits
816  */
817 enum jme_rxmcs_bits {
818         RXMCS_ALLFRAME          = 0x00000800,
819         RXMCS_BRDFRAME          = 0x00000400,
820         RXMCS_MULFRAME          = 0x00000200,
821         RXMCS_UNIFRAME          = 0x00000100,
822         RXMCS_ALLMULFRAME       = 0x00000080,
823         RXMCS_MULFILTERED       = 0x00000040,
824         RXMCS_RXCOLLDEC         = 0x00000020,
825         RXMCS_FLOWCTRL          = 0x00000008,
826         RXMCS_VTAGRM            = 0x00000004,
827         RXMCS_PREPAD            = 0x00000002,
828         RXMCS_CHECKSUM          = 0x00000001,
829
830         RXMCS_DEFAULT           = RXMCS_VTAGRM |
831                                   RXMCS_PREPAD |
832                                   RXMCS_FLOWCTRL |
833                                   RXMCS_CHECKSUM,
834 };
835
836 /*
837  * Wakeup Frame setup interface registers
838  */
839 #define WAKEUP_FRAME_NR 8
840 #define WAKEUP_FRAME_MASK_DWNR  4
841
842 enum jme_wfoi_bit_masks {
843         WFOI_MASK_SEL           = 0x00000070,
844         WFOI_CRC_SEL            = 0x00000008,
845         WFOI_FRAME_SEL          = 0x00000007,
846 };
847
848 enum jme_wfoi_shifts {
849         WFOI_MASK_SHIFT         = 4,
850 };
851
852 /*
853  * SMI Related definitions
854  */
855 enum jme_smi_bit_mask {
856         SMI_DATA_MASK           = 0xFFFF0000,
857         SMI_REG_ADDR_MASK       = 0x0000F800,
858         SMI_PHY_ADDR_MASK       = 0x000007C0,
859         SMI_OP_WRITE            = 0x00000020,
860         /* Set to 1, after req done it'll be cleared to 0 */
861         SMI_OP_REQ              = 0x00000010,
862         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
863         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
864         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
865         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
866 };
867
868 enum jme_smi_bit_shift {
869         SMI_DATA_SHIFT          = 16,
870         SMI_REG_ADDR_SHIFT      = 11,
871         SMI_PHY_ADDR_SHIFT      = 6,
872 };
873
874 static inline u32 smi_reg_addr(int x)
875 {
876         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
877 }
878
879 static inline u32 smi_phy_addr(int x)
880 {
881         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
882 }
883
884 #define JME_PHY_TIMEOUT 100 /* 100 msec */
885 #define JME_PHY_REG_NR 32
886
887 /*
888  * Global Host Control
889  */
890 enum jme_ghc_bit_mask {
891         GHC_SWRST               = 0x40000000,
892         GHC_DPX                 = 0x00000040,
893         GHC_SPEED               = 0x00000030,
894         GHC_LINK_POLL           = 0x00000001,
895 };
896
897 enum jme_ghc_speed_val {
898         GHC_SPEED_10M           = 0x00000010,
899         GHC_SPEED_100M          = 0x00000020,
900         GHC_SPEED_1000M         = 0x00000030,
901 };
902
903 enum jme_ghc_to_clk {
904         GHC_TO_CLK_OFF          = 0x00000000,
905         GHC_TO_CLK_GPHY         = 0x00400000,
906         GHC_TO_CLK_PCIE         = 0x00800000,
907         GHC_TO_CLK_INVALID      = 0x00C00000,
908 };
909
910 enum jme_ghc_txmac_clk {
911         GHC_TXMAC_CLK_OFF       = 0x00000000,
912         GHC_TXMAC_CLK_GPHY      = 0x00100000,
913         GHC_TXMAC_CLK_PCIE      = 0x00200000,
914         GHC_TXMAC_CLK_INVALID   = 0x00300000,
915 };
916
917 /*
918  * Power management control and status register
919  */
920 enum jme_pmcs_bit_masks {
921         PMCS_WF7DET     = 0x80000000,
922         PMCS_WF6DET     = 0x40000000,
923         PMCS_WF5DET     = 0x20000000,
924         PMCS_WF4DET     = 0x10000000,
925         PMCS_WF3DET     = 0x08000000,
926         PMCS_WF2DET     = 0x04000000,
927         PMCS_WF1DET     = 0x02000000,
928         PMCS_WF0DET     = 0x01000000,
929         PMCS_LFDET      = 0x00040000,
930         PMCS_LRDET      = 0x00020000,
931         PMCS_MFDET      = 0x00010000,
932         PMCS_WF7EN      = 0x00008000,
933         PMCS_WF6EN      = 0x00004000,
934         PMCS_WF5EN      = 0x00002000,
935         PMCS_WF4EN      = 0x00001000,
936         PMCS_WF3EN      = 0x00000800,
937         PMCS_WF2EN      = 0x00000400,
938         PMCS_WF1EN      = 0x00000200,
939         PMCS_WF0EN      = 0x00000100,
940         PMCS_LFEN       = 0x00000004,
941         PMCS_LREN       = 0x00000002,
942         PMCS_MFEN       = 0x00000001,
943 };
944
945 /*
946  * Giga PHY Status Registers
947  */
948 enum jme_phy_link_bit_mask {
949         PHY_LINK_SPEED_MASK             = 0x0000C000,
950         PHY_LINK_DUPLEX                 = 0x00002000,
951         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
952         PHY_LINK_UP                     = 0x00000400,
953         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
954         PHY_LINK_MDI_STAT               = 0x00000040,
955 };
956
957 enum jme_phy_link_speed_val {
958         PHY_LINK_SPEED_10M              = 0x00000000,
959         PHY_LINK_SPEED_100M             = 0x00004000,
960         PHY_LINK_SPEED_1000M            = 0x00008000,
961 };
962
963 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
964
965 /*
966  * SMB Control and Status
967  */
968 enum jme_smbcsr_bit_mask {
969         SMBCSR_CNACK    = 0x00020000,
970         SMBCSR_RELOAD   = 0x00010000,
971         SMBCSR_EEPROMD  = 0x00000020,
972         SMBCSR_INITDONE = 0x00000010,
973         SMBCSR_BUSY     = 0x0000000F,
974 };
975
976 enum jme_smbintf_bit_mask {
977         SMBINTF_HWDATR  = 0xFF000000,
978         SMBINTF_HWDATW  = 0x00FF0000,
979         SMBINTF_HWADDR  = 0x0000FF00,
980         SMBINTF_HWRWN   = 0x00000020,
981         SMBINTF_HWCMD   = 0x00000010,
982         SMBINTF_FASTM   = 0x00000008,
983         SMBINTF_GPIOSCL = 0x00000004,
984         SMBINTF_GPIOSDA = 0x00000002,
985         SMBINTF_GPIOEN  = 0x00000001,
986 };
987
988 enum jme_smbintf_vals {
989         SMBINTF_HWRWN_READ      = 0x00000020,
990         SMBINTF_HWRWN_WRITE     = 0x00000000,
991 };
992
993 enum jme_smbintf_shifts {
994         SMBINTF_HWDATR_SHIFT    = 24,
995         SMBINTF_HWDATW_SHIFT    = 16,
996         SMBINTF_HWADDR_SHIFT    = 8,
997 };
998
999 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1000 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1001 #define JME_SMB_LEN 256
1002 #define JME_EEPROM_MAGIC 0x250
1003
1004 /*
1005  * Timer Control/Status Register
1006  */
1007 enum jme_tmcsr_bit_masks {
1008         TMCSR_SWIT      = 0x80000000,
1009         TMCSR_EN        = 0x01000000,
1010         TMCSR_CNT       = 0x00FFFFFF,
1011 };
1012
1013 /*
1014  * General Purpose REG-0
1015  */
1016 enum jme_gpreg0_masks {
1017         GPREG0_DISSH            = 0xFF000000,
1018         GPREG0_PCIRLMT          = 0x00300000,
1019         GPREG0_PCCNOMUTCLR      = 0x00040000,
1020         GPREG0_LNKINTPOLL       = 0x00001000,
1021         GPREG0_PCCTMR           = 0x00000300,
1022         GPREG0_PHYADDR          = 0x0000001F,
1023 };
1024
1025 enum jme_gpreg0_vals {
1026         GPREG0_DISSH_DW7        = 0x80000000,
1027         GPREG0_DISSH_DW6        = 0x40000000,
1028         GPREG0_DISSH_DW5        = 0x20000000,
1029         GPREG0_DISSH_DW4        = 0x10000000,
1030         GPREG0_DISSH_DW3        = 0x08000000,
1031         GPREG0_DISSH_DW2        = 0x04000000,
1032         GPREG0_DISSH_DW1        = 0x02000000,
1033         GPREG0_DISSH_DW0        = 0x01000000,
1034         GPREG0_DISSH_ALL        = 0xFF000000,
1035
1036         GPREG0_PCIRLMT_8        = 0x00000000,
1037         GPREG0_PCIRLMT_6        = 0x00100000,
1038         GPREG0_PCIRLMT_5        = 0x00200000,
1039         GPREG0_PCIRLMT_4        = 0x00300000,
1040
1041         GPREG0_PCCTMR_16ns      = 0x00000000,
1042         GPREG0_PCCTMR_256ns     = 0x00000100,
1043         GPREG0_PCCTMR_1us       = 0x00000200,
1044         GPREG0_PCCTMR_1ms       = 0x00000300,
1045
1046         GPREG0_PHYADDR_1        = 0x00000001,
1047
1048         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
1049                                   GPREG0_PCCTMR_1us |
1050                                   GPREG0_PHYADDR_1,
1051 };
1052
1053 /*
1054  * General Purpose REG-1
1055  * Note: All theses bits defined here are for
1056  *       Chip mode revision 0x11 only
1057  */
1058 enum jme_gpreg1_masks {
1059         GPREG1_INTRDELAYUNIT    = 0x00000018,
1060         GPREG1_INTRDELAYENABLE  = 0x00000007,
1061 };
1062
1063 enum jme_gpreg1_vals {
1064         GPREG1_RSSPATCH         = 0x00000040,
1065         GPREG1_HALFMODEPATCH    = 0x00000020,
1066
1067         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1068         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1069         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1070         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1071
1072         GPREG1_INTDLYEN_1U      = 0x00000001,
1073         GPREG1_INTDLYEN_2U      = 0x00000002,
1074         GPREG1_INTDLYEN_3U      = 0x00000003,
1075         GPREG1_INTDLYEN_4U      = 0x00000004,
1076         GPREG1_INTDLYEN_5U      = 0x00000005,
1077         GPREG1_INTDLYEN_6U      = 0x00000006,
1078         GPREG1_INTDLYEN_7U      = 0x00000007,
1079
1080         GPREG1_DEFAULT          = 0x00000000,
1081 };
1082
1083 /*
1084  * Interrupt Status Bits
1085  */
1086 enum jme_interrupt_bits {
1087         INTR_SWINTR     = 0x80000000,
1088         INTR_TMINTR     = 0x40000000,
1089         INTR_LINKCH     = 0x20000000,
1090         INTR_PAUSERCV   = 0x10000000,
1091         INTR_MAGICRCV   = 0x08000000,
1092         INTR_WAKERCV    = 0x04000000,
1093         INTR_PCCRX0TO   = 0x02000000,
1094         INTR_PCCRX1TO   = 0x01000000,
1095         INTR_PCCRX2TO   = 0x00800000,
1096         INTR_PCCRX3TO   = 0x00400000,
1097         INTR_PCCTXTO    = 0x00200000,
1098         INTR_PCCRX0     = 0x00100000,
1099         INTR_PCCRX1     = 0x00080000,
1100         INTR_PCCRX2     = 0x00040000,
1101         INTR_PCCRX3     = 0x00020000,
1102         INTR_PCCTX      = 0x00010000,
1103         INTR_RX3EMP     = 0x00008000,
1104         INTR_RX2EMP     = 0x00004000,
1105         INTR_RX1EMP     = 0x00002000,
1106         INTR_RX0EMP     = 0x00001000,
1107         INTR_RX3        = 0x00000800,
1108         INTR_RX2        = 0x00000400,
1109         INTR_RX1        = 0x00000200,
1110         INTR_RX0        = 0x00000100,
1111         INTR_TX7        = 0x00000080,
1112         INTR_TX6        = 0x00000040,
1113         INTR_TX5        = 0x00000020,
1114         INTR_TX4        = 0x00000010,
1115         INTR_TX3        = 0x00000008,
1116         INTR_TX2        = 0x00000004,
1117         INTR_TX1        = 0x00000002,
1118         INTR_TX0        = 0x00000001,
1119 };
1120
1121 static const u32 INTR_ENABLE = INTR_SWINTR |
1122                                  INTR_TMINTR |
1123                                  INTR_LINKCH |
1124                                  INTR_PCCRX0TO |
1125                                  INTR_PCCRX0 |
1126                                  INTR_PCCTXTO |
1127                                  INTR_PCCTX |
1128                                  INTR_RX0EMP;
1129
1130 /*
1131  * PCC Control Registers
1132  */
1133 enum jme_pccrx_masks {
1134         PCCRXTO_MASK    = 0xFFFF0000,
1135         PCCRX_MASK      = 0x0000FF00,
1136 };
1137
1138 enum jme_pcctx_masks {
1139         PCCTXTO_MASK    = 0xFFFF0000,
1140         PCCTX_MASK      = 0x0000FF00,
1141         PCCTX_QS_MASK   = 0x000000FF,
1142 };
1143
1144 enum jme_pccrx_shifts {
1145         PCCRXTO_SHIFT   = 16,
1146         PCCRX_SHIFT     = 8,
1147 };
1148
1149 enum jme_pcctx_shifts {
1150         PCCTXTO_SHIFT   = 16,
1151         PCCTX_SHIFT     = 8,
1152 };
1153
1154 enum jme_pcctx_bits {
1155         PCCTXQ0_EN      = 0x00000001,
1156         PCCTXQ1_EN      = 0x00000002,
1157         PCCTXQ2_EN      = 0x00000004,
1158         PCCTXQ3_EN      = 0x00000008,
1159         PCCTXQ4_EN      = 0x00000010,
1160         PCCTXQ5_EN      = 0x00000020,
1161         PCCTXQ6_EN      = 0x00000040,
1162         PCCTXQ7_EN      = 0x00000080,
1163 };
1164
1165 /*
1166  * Chip Mode Register
1167  */
1168 enum jme_chipmode_bit_masks {
1169         CM_FPGAVER_MASK         = 0xFFFF0000,
1170         CM_CHIPREV_MASK         = 0x0000FF00,
1171         CM_CHIPMODE_MASK        = 0x0000000F,
1172 };
1173
1174 enum jme_chipmode_shifts {
1175         CM_FPGAVER_SHIFT        = 16,
1176         CM_CHIPREV_SHIFT        = 8,
1177 };
1178
1179 /*
1180  * Aggressive Power Mode Control
1181  */
1182 enum jme_apmc_bits {
1183         JME_APMC_PCIE_SD_EN     = 0x40000000,
1184         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1185         JME_APMC_EPIEN          = 0x04000000,
1186         JME_APMC_EPIEN_CTRL     = 0x03000000,
1187 };
1188
1189 enum jme_apmc_values {
1190         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1191         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1192 };
1193
1194 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1195
1196 #ifdef REG_DEBUG
1197 static char *MAC_REG_NAME[] = {
1198         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1199         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1200         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1201         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1202         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1203         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1204         "JME_PMCS"};
1205
1206 static char *PE_REG_NAME[] = {
1207         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1208         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1209         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1210         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1211         "JME_SMBCSR",   "JME_SMBINTF"};
1212
1213 static char *MISC_REG_NAME[] = {
1214         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1215         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1216         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1217         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1218         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1219         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1220         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1221         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1222         "JME_PCCSRX0"};
1223
1224 static inline void reg_dbg(const struct jme_adapter *jme,
1225                 const char *msg, u32 val, u32 reg)
1226 {
1227         const char *regname;
1228         switch (reg & 0xF00) {
1229         case 0x000:
1230                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1231                 break;
1232         case 0x400:
1233                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1234                 break;
1235         case 0x800:
1236                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1237                 break;
1238         default:
1239                 regname = PE_REG_NAME[0];
1240         }
1241         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1242                         msg, val, regname);
1243 }
1244 #else
1245 static inline void reg_dbg(const struct jme_adapter *jme,
1246                 const char *msg, u32 val, u32 reg) {}
1247 #endif
1248
1249 /*
1250  * Read/Write MMaped I/O Registers
1251  */
1252 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1253 {
1254         return readl(jme->regs + reg);
1255 }
1256
1257 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1258 {
1259         reg_dbg(jme, "REG WRITE", val, reg);
1260         writel(val, jme->regs + reg);
1261         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1262 }
1263
1264 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1265 {
1266         /*
1267          * Read after write should cause flush
1268          */
1269         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1270         writel(val, jme->regs + reg);
1271         readl(jme->regs + reg);
1272         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1273 }
1274
1275 /*
1276  * PHY Regs
1277  */
1278 enum jme_phy_reg17_bit_masks {
1279         PREG17_SPEED            = 0xC000,
1280         PREG17_DUPLEX           = 0x2000,
1281         PREG17_SPDRSV           = 0x0800,
1282         PREG17_LNKUP            = 0x0400,
1283         PREG17_MDI              = 0x0040,
1284 };
1285
1286 enum jme_phy_reg17_vals {
1287         PREG17_SPEED_10M        = 0x0000,
1288         PREG17_SPEED_100M       = 0x4000,
1289         PREG17_SPEED_1000M      = 0x8000,
1290 };
1291
1292 #define BMSR_ANCOMP               0x0020
1293
1294 /*
1295  * Workaround
1296  */
1297 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1298 {
1299         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1300 }
1301
1302 /*
1303  * Function prototypes
1304  */
1305 static int jme_set_settings(struct net_device *netdev,
1306                                 struct ethtool_cmd *ecmd);
1307 static void jme_set_multi(struct net_device *netdev);
1308
1309 #endif