Import jme 1.0.2-backport source
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/version.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/mii.h>
32 #include <linux/crc32.h>
33 #include <linux/delay.h>
34 #include <linux/spinlock.h>
35 #include <linux/in.h>
36 #include <linux/ip.h>
37 #include <linux/ipv6.h>
38 #include <linux/tcp.h>
39 #include <linux/udp.h>
40 #include <linux/if_vlan.h>
41 #include "jme.h"
42
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53         "Do not use external plug signal for pseudo hot-plug.");
54
55 static int
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
57 {
58         struct jme_adapter *jme = netdev_priv(netdev);
59         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61 read_again:
62         jwrite32(jme, JME_SMI, SMI_OP_REQ |
63                                 smi_phy_addr(phy) |
64                                 smi_reg_addr(reg));
65
66         wmb();
67         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68                 udelay(20);
69                 val = jread32(jme, JME_SMI);
70                 if ((val & SMI_OP_REQ) == 0)
71                         break;
72         }
73
74         if (i == 0) {
75                 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76                 return 0;
77         }
78
79         if (again--)
80                 goto read_again;
81
82         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83 }
84
85 static void
86 jme_mdio_write(struct net_device *netdev,
87                                 int phy, int reg, int val)
88 {
89         struct jme_adapter *jme = netdev_priv(netdev);
90         int i;
91
92         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94                 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96         wmb();
97         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98                 udelay(20);
99                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100                         break;
101         }
102
103         if (i == 0)
104                 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106         return;
107 }
108
109 static inline void
110 jme_reset_phy_processor(struct jme_adapter *jme)
111 {
112         u32 val;
113
114         jme_mdio_write(jme->dev,
115                         jme->mii_if.phy_id,
116                         MII_ADVERTISE, ADVERTISE_ALL |
117                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120                 jme_mdio_write(jme->dev,
121                                 jme->mii_if.phy_id,
122                                 MII_CTRL1000,
123                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125         val = jme_mdio_read(jme->dev,
126                                 jme->mii_if.phy_id,
127                                 MII_BMCR);
128
129         jme_mdio_write(jme->dev,
130                         jme->mii_if.phy_id,
131                         MII_BMCR, val | BMCR_RESET);
132
133         return;
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138                 u32 *mask, u32 crc, int fnr)
139 {
140         int i;
141
142         /*
143          * Setup CRC pattern
144          */
145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146         wmb();
147         jwrite32(jme, JME_WFODP, crc);
148         wmb();
149
150         /*
151          * Setup Mask
152          */
153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154                 jwrite32(jme, JME_WFOI,
155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156                                 (fnr & WFOI_FRAME_SEL));
157                 wmb();
158                 jwrite32(jme, JME_WFODP, mask[i]);
159                 wmb();
160         }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166         u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167         u32 crc = 0xCDCDCDCD;
168         u32 gpreg0;
169         int i;
170
171         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172         udelay(2);
173         jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177         jwrite32(jme, JME_RXQDC, 0x00000000);
178         jwrite32(jme, JME_RXNDA, 0x00000000);
179         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181         jwrite32(jme, JME_TXQDC, 0x00000000);
182         jwrite32(jme, JME_TXNDA, 0x00000000);
183
184         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187                 jme_setup_wakeup_frame(jme, mask, crc, i);
188         if (jme->fpgaver)
189                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190         else
191                 gpreg0 = GPREG0_DEFAULT;
192         jwrite32(jme, JME_GPREG0, gpreg0);
193         jwrite32(jme, JME_GPREG1, 0);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200         jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207         pci_set_power_state(jme->pdev, PCI_D0);
208         pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214         u32 val;
215         int i;
216
217         val = jread32(jme, JME_SMBCSR);
218
219         if (val & SMBCSR_EEPROMD) {
220                 val |= SMBCSR_CNACK;
221                 jwrite32(jme, JME_SMBCSR, val);
222                 val |= SMBCSR_RELOAD;
223                 jwrite32(jme, JME_SMBCSR, val);
224                 mdelay(12);
225
226                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227                         mdelay(1);
228                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229                                 break;
230                 }
231
232                 if (i == 0) {
233                         jeprintk(jme->pdev, "eeprom reload timeout\n");
234                         return -EIO;
235                 }
236         }
237
238         return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244         struct jme_adapter *jme = netdev_priv(netdev);
245         unsigned char macaddr[6];
246         u32 val;
247
248         spin_lock_bh(&jme->macaddr_lock);
249         val = jread32(jme, JME_RXUMA_LO);
250         macaddr[0] = (val >>  0) & 0xFF;
251         macaddr[1] = (val >>  8) & 0xFF;
252         macaddr[2] = (val >> 16) & 0xFF;
253         macaddr[3] = (val >> 24) & 0xFF;
254         val = jread32(jme, JME_RXUMA_HI);
255         macaddr[4] = (val >>  0) & 0xFF;
256         macaddr[5] = (val >>  8) & 0xFF;
257         memcpy(netdev->dev_addr, macaddr, 6);
258         spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264         switch (p) {
265         case PCC_OFF:
266                 jwrite32(jme, JME_PCCRX0,
267                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269                 break;
270         case PCC_P1:
271                 jwrite32(jme, JME_PCCRX0,
272                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274                 break;
275         case PCC_P2:
276                 jwrite32(jme, JME_PCCRX0,
277                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279                 break;
280         case PCC_P3:
281                 jwrite32(jme, JME_PCCRX0,
282                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284                 break;
285         default:
286                 break;
287         }
288         wmb();
289
290         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291                 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297         register struct dynpcc_info *dpi = &(jme->dpi);
298
299         jme_set_rx_pcc(jme, PCC_P1);
300         dpi->cur                = PCC_P1;
301         dpi->attempt            = PCC_P1;
302         dpi->cnt                = 0;
303
304         jwrite32(jme, JME_PCCTX,
305                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307                         PCCTXQ0_EN
308                 );
309
310         /*
311          * Enable Interrupts
312          */
313         jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319         /*
320          * Disable Interrupts
321          */
322         jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static inline void
326 jme_enable_shadow(struct jme_adapter *jme)
327 {
328         jwrite32(jme,
329                  JME_SHBA_LO,
330                  ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
331 }
332
333 static inline void
334 jme_disable_shadow(struct jme_adapter *jme)
335 {
336         jwrite32(jme, JME_SHBA_LO, 0x0);
337 }
338
339 static u32
340 jme_linkstat_from_phy(struct jme_adapter *jme)
341 {
342         u32 phylink, bmsr;
343
344         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346         if (bmsr & BMSR_ANCOMP)
347                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349         return phylink;
350 }
351
352 static inline void
353 jme_set_phyfifoa(struct jme_adapter *jme)
354 {
355         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356 }
357
358 static inline void
359 jme_set_phyfifob(struct jme_adapter *jme)
360 {
361         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362 }
363
364 static int
365 jme_check_link(struct net_device *netdev, int testonly)
366 {
367         struct jme_adapter *jme = netdev_priv(netdev);
368         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
369         char linkmsg[64];
370         int rc = 0;
371
372         linkmsg[0] = '\0';
373
374         if (jme->fpgaver)
375                 phylink = jme_linkstat_from_phy(jme);
376         else
377                 phylink = jread32(jme, JME_PHY_LINK);
378
379         if (phylink & PHY_LINK_UP) {
380                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
381                         /*
382                          * If we did not enable AN
383                          * Speed/Duplex Info should be obtained from SMI
384                          */
385                         phylink = PHY_LINK_UP;
386
387                         bmcr = jme_mdio_read(jme->dev,
388                                                 jme->mii_if.phy_id,
389                                                 MII_BMCR);
390
391                         phylink |= ((bmcr & BMCR_SPEED1000) &&
392                                         (bmcr & BMCR_SPEED100) == 0) ?
393                                         PHY_LINK_SPEED_1000M :
394                                         (bmcr & BMCR_SPEED100) ?
395                                         PHY_LINK_SPEED_100M :
396                                         PHY_LINK_SPEED_10M;
397
398                         phylink |= (bmcr & BMCR_FULLDPLX) ?
399                                          PHY_LINK_DUPLEX : 0;
400
401                         strcat(linkmsg, "Forced: ");
402                 } else {
403                         /*
404                          * Keep polling for speed/duplex resolve complete
405                          */
406                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
407                                 --cnt) {
408
409                                 udelay(1);
410
411                                 if (jme->fpgaver)
412                                         phylink = jme_linkstat_from_phy(jme);
413                                 else
414                                         phylink = jread32(jme, JME_PHY_LINK);
415                         }
416                         if (!cnt)
417                                 jeprintk(jme->pdev,
418                                         "Waiting speed resolve timeout.\n");
419
420                         strcat(linkmsg, "ANed: ");
421                 }
422
423                 if (jme->phylink == phylink) {
424                         rc = 1;
425                         goto out;
426                 }
427                 if (testonly)
428                         goto out;
429
430                 jme->phylink = phylink;
431
432                 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
433                                         GHC_SPEED_100M |
434                                         GHC_SPEED_1000M |
435                                         GHC_DPX);
436                 switch (phylink & PHY_LINK_SPEED_MASK) {
437                 case PHY_LINK_SPEED_10M:
438                         ghc |= GHC_SPEED_10M;
439                         strcat(linkmsg, "10 Mbps, ");
440                         if (is_buggy250(jme->pdev->device, jme->chiprev))
441                                 jme_set_phyfifoa(jme);
442                         break;
443                 case PHY_LINK_SPEED_100M:
444                         ghc |= GHC_SPEED_100M;
445                         strcat(linkmsg, "100 Mbps, ");
446                         if (is_buggy250(jme->pdev->device, jme->chiprev))
447                                 jme_set_phyfifob(jme);
448                         break;
449                 case PHY_LINK_SPEED_1000M:
450                         ghc |= GHC_SPEED_1000M;
451                         strcat(linkmsg, "1000 Mbps, ");
452                         if (is_buggy250(jme->pdev->device, jme->chiprev))
453                                 jme_set_phyfifoa(jme);
454                         break;
455                 default:
456                         break;
457                 }
458                 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
459
460                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
461                                         "Full-Duplex, " :
462                                         "Half-Duplex, ");
463
464                 if (phylink & PHY_LINK_MDI_STAT)
465                         strcat(linkmsg, "MDI-X");
466                 else
467                         strcat(linkmsg, "MDI");
468
469                 if (phylink & PHY_LINK_DUPLEX) {
470                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
471                 } else {
472                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
473                                                 TXMCS_BACKOFF |
474                                                 TXMCS_CARRIERSENSE |
475                                                 TXMCS_COLLISION);
476                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
477                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
478                                 TXTRHD_TXREN |
479                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
480                 }
481
482                 jme->reg_ghc = ghc;
483                 jwrite32(jme, JME_GHC, ghc);
484
485                 msg_link(jme, "Link is up at %s.\n", linkmsg);
486                 netif_carrier_on(netdev);
487         } else {
488                 if (testonly)
489                         goto out;
490
491                 msg_link(jme, "Link is down.\n");
492                 jme->phylink = 0;
493                 netif_carrier_off(netdev);
494         }
495
496 out:
497         return rc;
498 }
499
500 static int
501 jme_setup_tx_resources(struct jme_adapter *jme)
502 {
503         struct jme_ring *txring = &(jme->txring[0]);
504
505         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
506                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
507                                    &(txring->dmaalloc),
508                                    GFP_ATOMIC);
509
510         if (!txring->alloc) {
511                 txring->desc = NULL;
512                 txring->dmaalloc = 0;
513                 txring->dma = 0;
514                 return -ENOMEM;
515         }
516
517         /*
518          * 16 Bytes align
519          */
520         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
521                                                 RING_DESC_ALIGN);
522         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
523         txring->next_to_use     = 0;
524         atomic_set(&txring->next_to_clean, 0);
525         atomic_set(&txring->nr_free, jme->tx_ring_size);
526
527         /*
528          * Initialize Transmit Descriptors
529          */
530         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
531         memset(txring->bufinf, 0,
532                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
533
534         return 0;
535 }
536
537 static void
538 jme_free_tx_resources(struct jme_adapter *jme)
539 {
540         int i;
541         struct jme_ring *txring = &(jme->txring[0]);
542         struct jme_buffer_info *txbi = txring->bufinf;
543
544         if (txring->alloc) {
545                 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
546                         txbi = txring->bufinf + i;
547                         if (txbi->skb) {
548                                 dev_kfree_skb(txbi->skb);
549                                 txbi->skb = NULL;
550                         }
551                         txbi->mapping           = 0;
552                         txbi->len               = 0;
553                         txbi->nr_desc           = 0;
554                         txbi->start_xmit        = 0;
555                 }
556
557                 dma_free_coherent(&(jme->pdev->dev),
558                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
559                                   txring->alloc,
560                                   txring->dmaalloc);
561
562                 txring->alloc           = NULL;
563                 txring->desc            = NULL;
564                 txring->dmaalloc        = 0;
565                 txring->dma             = 0;
566         }
567         txring->next_to_use     = 0;
568         atomic_set(&txring->next_to_clean, 0);
569         atomic_set(&txring->nr_free, 0);
570
571 }
572
573 static inline void
574 jme_enable_tx_engine(struct jme_adapter *jme)
575 {
576         /*
577          * Select Queue 0
578          */
579         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
580         wmb();
581
582         /*
583          * Setup TX Queue 0 DMA Bass Address
584          */
585         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
586         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
587         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
588
589         /*
590          * Setup TX Descptor Count
591          */
592         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
593
594         /*
595          * Enable TX Engine
596          */
597         wmb();
598         jwrite32(jme, JME_TXCS, jme->reg_txcs |
599                                 TXCS_SELECT_QUEUE0 |
600                                 TXCS_ENABLE);
601
602 }
603
604 static inline void
605 jme_restart_tx_engine(struct jme_adapter *jme)
606 {
607         /*
608          * Restart TX Engine
609          */
610         jwrite32(jme, JME_TXCS, jme->reg_txcs |
611                                 TXCS_SELECT_QUEUE0 |
612                                 TXCS_ENABLE);
613 }
614
615 static inline void
616 jme_disable_tx_engine(struct jme_adapter *jme)
617 {
618         int i;
619         u32 val;
620
621         /*
622          * Disable TX Engine
623          */
624         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
625         wmb();
626
627         val = jread32(jme, JME_TXCS);
628         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
629                 mdelay(1);
630                 val = jread32(jme, JME_TXCS);
631                 rmb();
632         }
633
634         if (!i)
635                 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
636 }
637
638 static void
639 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
640 {
641         struct jme_ring *rxring = jme->rxring;
642         register struct rxdesc *rxdesc = rxring->desc;
643         struct jme_buffer_info *rxbi = rxring->bufinf;
644         rxdesc += i;
645         rxbi += i;
646
647         rxdesc->dw[0] = 0;
648         rxdesc->dw[1] = 0;
649         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
650         rxdesc->desc1.bufaddrl  = cpu_to_le32(
651                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
652         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
653         if (jme->dev->features & NETIF_F_HIGHDMA)
654                 rxdesc->desc1.flags = RXFLAG_64BIT;
655         wmb();
656         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
657 }
658
659 static int
660 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
661 {
662         struct jme_ring *rxring = &(jme->rxring[0]);
663         struct jme_buffer_info *rxbi = rxring->bufinf + i;
664         struct sk_buff *skb;
665
666         skb = netdev_alloc_skb(jme->dev,
667                 jme->dev->mtu + RX_EXTRA_LEN);
668         if (unlikely(!skb))
669                 return -ENOMEM;
670
671         rxbi->skb = skb;
672         rxbi->len = skb_tailroom(skb);
673         rxbi->mapping = pci_map_page(jme->pdev,
674                                         virt_to_page(skb->data),
675                                         offset_in_page(skb->data),
676                                         rxbi->len,
677                                         PCI_DMA_FROMDEVICE);
678
679         return 0;
680 }
681
682 static void
683 jme_free_rx_buf(struct jme_adapter *jme, int i)
684 {
685         struct jme_ring *rxring = &(jme->rxring[0]);
686         struct jme_buffer_info *rxbi = rxring->bufinf;
687         rxbi += i;
688
689         if (rxbi->skb) {
690                 pci_unmap_page(jme->pdev,
691                                  rxbi->mapping,
692                                  rxbi->len,
693                                  PCI_DMA_FROMDEVICE);
694                 dev_kfree_skb(rxbi->skb);
695                 rxbi->skb = NULL;
696                 rxbi->mapping = 0;
697                 rxbi->len = 0;
698         }
699 }
700
701 static void
702 jme_free_rx_resources(struct jme_adapter *jme)
703 {
704         int i;
705         struct jme_ring *rxring = &(jme->rxring[0]);
706
707         if (rxring->alloc) {
708                 for (i = 0 ; i < jme->rx_ring_size ; ++i)
709                         jme_free_rx_buf(jme, i);
710
711                 dma_free_coherent(&(jme->pdev->dev),
712                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
713                                   rxring->alloc,
714                                   rxring->dmaalloc);
715                 rxring->alloc    = NULL;
716                 rxring->desc     = NULL;
717                 rxring->dmaalloc = 0;
718                 rxring->dma      = 0;
719         }
720         rxring->next_to_use   = 0;
721         atomic_set(&rxring->next_to_clean, 0);
722 }
723
724 static int
725 jme_setup_rx_resources(struct jme_adapter *jme)
726 {
727         int i;
728         struct jme_ring *rxring = &(jme->rxring[0]);
729
730         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
731                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
732                                    &(rxring->dmaalloc),
733                                    GFP_ATOMIC);
734         if (!rxring->alloc) {
735                 rxring->desc = NULL;
736                 rxring->dmaalloc = 0;
737                 rxring->dma = 0;
738                 return -ENOMEM;
739         }
740
741         /*
742          * 16 Bytes align
743          */
744         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
745                                                 RING_DESC_ALIGN);
746         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
747         rxring->next_to_use     = 0;
748         atomic_set(&rxring->next_to_clean, 0);
749
750         /*
751          * Initiallize Receive Descriptors
752          */
753         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
754                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
755                         jme_free_rx_resources(jme);
756                         return -ENOMEM;
757                 }
758
759                 jme_set_clean_rxdesc(jme, i);
760         }
761
762         return 0;
763 }
764
765 static inline void
766 jme_enable_rx_engine(struct jme_adapter *jme)
767 {
768         /*
769          * Select Queue 0
770          */
771         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
772                                 RXCS_QUEUESEL_Q0);
773         wmb();
774
775         /*
776          * Setup RX DMA Bass Address
777          */
778         jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
779         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
780         jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
781
782         /*
783          * Setup RX Descriptor Count
784          */
785         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
786
787         /*
788          * Setup Unicast Filter
789          */
790         jme_set_multi(jme->dev);
791
792         /*
793          * Enable RX Engine
794          */
795         wmb();
796         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
797                                 RXCS_QUEUESEL_Q0 |
798                                 RXCS_ENABLE |
799                                 RXCS_QST);
800 }
801
802 static inline void
803 jme_restart_rx_engine(struct jme_adapter *jme)
804 {
805         /*
806          * Start RX Engine
807          */
808         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
809                                 RXCS_QUEUESEL_Q0 |
810                                 RXCS_ENABLE |
811                                 RXCS_QST);
812 }
813
814 static inline void
815 jme_disable_rx_engine(struct jme_adapter *jme)
816 {
817         int i;
818         u32 val;
819
820         /*
821          * Disable RX Engine
822          */
823         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
824         wmb();
825
826         val = jread32(jme, JME_RXCS);
827         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
828                 mdelay(1);
829                 val = jread32(jme, JME_RXCS);
830                 rmb();
831         }
832
833         if (!i)
834                 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
835
836 }
837
838 static int
839 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
840 {
841         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
842                 return false;
843
844         if (unlikely(!(flags & RXWBFLAG_MF) &&
845         (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
846                 msg_rx_err(jme, "TCP Checksum error.\n");
847                 goto out_sumerr;
848         }
849
850         if (unlikely(!(flags & RXWBFLAG_MF) &&
851         (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
852                 msg_rx_err(jme, "UDP Checksum error.\n");
853                 goto out_sumerr;
854         }
855
856         if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
857                 msg_rx_err(jme, "IPv4 Checksum error.\n");
858                 goto out_sumerr;
859         }
860
861         return true;
862
863 out_sumerr:
864         return false;
865 }
866
867 static void
868 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
869 {
870         struct jme_ring *rxring = &(jme->rxring[0]);
871         struct rxdesc *rxdesc = rxring->desc;
872         struct jme_buffer_info *rxbi = rxring->bufinf;
873         struct sk_buff *skb;
874         int framesize;
875
876         rxdesc += idx;
877         rxbi += idx;
878
879         skb = rxbi->skb;
880         pci_dma_sync_single_for_cpu(jme->pdev,
881                                         rxbi->mapping,
882                                         rxbi->len,
883                                         PCI_DMA_FROMDEVICE);
884
885         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
886                 pci_dma_sync_single_for_device(jme->pdev,
887                                                 rxbi->mapping,
888                                                 rxbi->len,
889                                                 PCI_DMA_FROMDEVICE);
890
891                 ++(NET_STAT(jme).rx_dropped);
892         } else {
893                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
894                                 - RX_PREPAD_SIZE;
895
896                 skb_reserve(skb, RX_PREPAD_SIZE);
897                 skb_put(skb, framesize);
898                 skb->protocol = eth_type_trans(skb, jme->dev);
899
900                 if (jme_rxsum_ok(jme, rxdesc->descwb.flags))
901                         skb->ip_summed = CHECKSUM_UNNECESSARY;
902                 else
903                         skb->ip_summed = CHECKSUM_NONE;
904
905                 if (rxdesc->descwb.flags & RXWBFLAG_TAGON) {
906                         if (jme->vlgrp) {
907                                 jme->jme_vlan_rx(skb, jme->vlgrp,
908                                         le32_to_cpu(rxdesc->descwb.vlan));
909                                 NET_STAT(jme).rx_bytes += 4;
910                         }
911                 } else {
912                         jme->jme_rx(skb);
913                 }
914
915                 if ((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
916                                 RXWBFLAG_DEST_MUL)
917                         ++(NET_STAT(jme).multicast);
918
919                 jme->dev->last_rx = jiffies;
920                 NET_STAT(jme).rx_bytes += framesize;
921                 ++(NET_STAT(jme).rx_packets);
922         }
923
924         jme_set_clean_rxdesc(jme, idx);
925
926 }
927
928 static int
929 jme_process_receive(struct jme_adapter *jme, int limit)
930 {
931         struct jme_ring *rxring = &(jme->rxring[0]);
932         struct rxdesc *rxdesc = rxring->desc;
933         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
934
935         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
936                 goto out_inc;
937
938         if (unlikely(atomic_read(&jme->link_changing) != 1))
939                 goto out_inc;
940
941         if (unlikely(!netif_carrier_ok(jme->dev)))
942                 goto out_inc;
943
944         i = atomic_read(&rxring->next_to_clean);
945         while (limit-- > 0) {
946                 rxdesc = rxring->desc;
947                 rxdesc += i;
948
949                 if ((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
950                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
951                         goto out;
952
953                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
954
955                 if (unlikely(desccnt > 1 ||
956                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
957
958                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
959                                 ++(NET_STAT(jme).rx_crc_errors);
960                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
961                                 ++(NET_STAT(jme).rx_fifo_errors);
962                         else
963                                 ++(NET_STAT(jme).rx_errors);
964
965                         if (desccnt > 1)
966                                 limit -= desccnt - 1;
967
968                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
969                                 jme_set_clean_rxdesc(jme, j);
970                                 j = (j + 1) & (mask);
971                         }
972
973                 } else {
974                         jme_alloc_and_feed_skb(jme, i);
975                 }
976
977                 i = (i + desccnt) & (mask);
978         }
979
980 out:
981         atomic_set(&rxring->next_to_clean, i);
982
983 out_inc:
984         atomic_inc(&jme->rx_cleaning);
985
986         return limit > 0 ? limit : 0;
987
988 }
989
990 static void
991 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
992 {
993         if (likely(atmp == dpi->cur)) {
994                 dpi->cnt = 0;
995                 return;
996         }
997
998         if (dpi->attempt == atmp) {
999                 ++(dpi->cnt);
1000         } else {
1001                 dpi->attempt = atmp;
1002                 dpi->cnt = 0;
1003         }
1004
1005 }
1006
1007 static void
1008 jme_dynamic_pcc(struct jme_adapter *jme)
1009 {
1010         register struct dynpcc_info *dpi = &(jme->dpi);
1011
1012         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1013                 jme_attempt_pcc(dpi, PCC_P3);
1014         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1015         || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1016                 jme_attempt_pcc(dpi, PCC_P2);
1017         else
1018                 jme_attempt_pcc(dpi, PCC_P1);
1019
1020         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1021                 if (dpi->attempt < dpi->cur)
1022                         tasklet_schedule(&jme->rxclean_task);
1023                 jme_set_rx_pcc(jme, dpi->attempt);
1024                 dpi->cur = dpi->attempt;
1025                 dpi->cnt = 0;
1026         }
1027 }
1028
1029 static void
1030 jme_start_pcc_timer(struct jme_adapter *jme)
1031 {
1032         struct dynpcc_info *dpi = &(jme->dpi);
1033         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1034         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1035         dpi->intr_cnt           = 0;
1036         jwrite32(jme, JME_TMCSR,
1037                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1038 }
1039
1040 static inline void
1041 jme_stop_pcc_timer(struct jme_adapter *jme)
1042 {
1043         jwrite32(jme, JME_TMCSR, 0);
1044 }
1045
1046 static void
1047 jme_shutdown_nic(struct jme_adapter *jme)
1048 {
1049         u32 phylink;
1050
1051         phylink = jme_linkstat_from_phy(jme);
1052
1053         if (!(phylink & PHY_LINK_UP)) {
1054                 /*
1055                  * Disable all interrupt before issue timer
1056                  */
1057                 jme_stop_irq(jme);
1058                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1059         }
1060 }
1061
1062 static void
1063 jme_pcc_tasklet(unsigned long arg)
1064 {
1065         struct jme_adapter *jme = (struct jme_adapter *)arg;
1066         struct net_device *netdev = jme->dev;
1067
1068         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1069                 jme_shutdown_nic(jme);
1070                 return;
1071         }
1072
1073         if (unlikely(!netif_carrier_ok(netdev) ||
1074                 (atomic_read(&jme->link_changing) != 1)
1075         )) {
1076                 jme_stop_pcc_timer(jme);
1077                 return;
1078         }
1079
1080         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1081                 jme_dynamic_pcc(jme);
1082
1083         jme_start_pcc_timer(jme);
1084 }
1085
1086 static inline void
1087 jme_polling_mode(struct jme_adapter *jme)
1088 {
1089         jme_set_rx_pcc(jme, PCC_OFF);
1090 }
1091
1092 static inline void
1093 jme_interrupt_mode(struct jme_adapter *jme)
1094 {
1095         jme_set_rx_pcc(jme, PCC_P1);
1096 }
1097
1098 static inline int
1099 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1100 {
1101         u32 apmc;
1102         apmc = jread32(jme, JME_APMC);
1103         return apmc & JME_APMC_PSEUDO_HP_EN;
1104 }
1105
1106 static void
1107 jme_start_shutdown_timer(struct jme_adapter *jme)
1108 {
1109         u32 apmc;
1110
1111         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1112         apmc &= ~JME_APMC_EPIEN_CTRL;
1113         if (!no_extplug) {
1114                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1115                 wmb();
1116         }
1117         jwrite32f(jme, JME_APMC, apmc);
1118
1119         jwrite32f(jme, JME_TIMER2, 0);
1120         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1121         jwrite32(jme, JME_TMCSR,
1122                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1123 }
1124
1125 static void
1126 jme_stop_shutdown_timer(struct jme_adapter *jme)
1127 {
1128         u32 apmc;
1129
1130         jwrite32f(jme, JME_TMCSR, 0);
1131         jwrite32f(jme, JME_TIMER2, 0);
1132         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1133
1134         apmc = jread32(jme, JME_APMC);
1135         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1136         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1137         wmb();
1138         jwrite32f(jme, JME_APMC, apmc);
1139 }
1140
1141 static void
1142 jme_link_change_tasklet(unsigned long arg)
1143 {
1144         struct jme_adapter *jme = (struct jme_adapter *)arg;
1145         struct net_device *netdev = jme->dev;
1146         int rc;
1147
1148         while (!atomic_dec_and_test(&jme->link_changing)) {
1149                 atomic_inc(&jme->link_changing);
1150                 msg_intr(jme, "Get link change lock failed.\n");
1151                 while (atomic_read(&jme->link_changing) != 1)
1152                         msg_intr(jme, "Waiting link change lock.\n");
1153         }
1154
1155         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1156                 goto out;
1157
1158         jme->old_mtu = netdev->mtu;
1159         netif_stop_queue(netdev);
1160         if (jme_pseudo_hotplug_enabled(jme))
1161                 jme_stop_shutdown_timer(jme);
1162
1163         jme_stop_pcc_timer(jme);
1164         tasklet_disable(&jme->txclean_task);
1165         tasklet_disable(&jme->rxclean_task);
1166         tasklet_disable(&jme->rxempty_task);
1167
1168         if (netif_carrier_ok(netdev)) {
1169                 jme_reset_ghc_speed(jme);
1170                 jme_disable_rx_engine(jme);
1171                 jme_disable_tx_engine(jme);
1172                 jme_reset_mac_processor(jme);
1173                 jme_free_rx_resources(jme);
1174                 jme_free_tx_resources(jme);
1175
1176                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1177                         jme_polling_mode(jme);
1178
1179                 netif_carrier_off(netdev);
1180         }
1181
1182         jme_check_link(netdev, 0);
1183         if (netif_carrier_ok(netdev)) {
1184                 rc = jme_setup_rx_resources(jme);
1185                 if (rc) {
1186                         jeprintk(jme->pdev, "Allocating resources for RX error"
1187                                 ", Device STOPPED!\n");
1188                         goto out_enable_tasklet;
1189                 }
1190
1191                 rc = jme_setup_tx_resources(jme);
1192                 if (rc) {
1193                         jeprintk(jme->pdev, "Allocating resources for TX error"
1194                                 ", Device STOPPED!\n");
1195                         goto err_out_free_rx_resources;
1196                 }
1197
1198                 jme_enable_rx_engine(jme);
1199                 jme_enable_tx_engine(jme);
1200
1201                 netif_start_queue(netdev);
1202
1203                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1204                         jme_interrupt_mode(jme);
1205
1206                 jme_start_pcc_timer(jme);
1207         } else if (jme_pseudo_hotplug_enabled(jme)) {
1208                 jme_start_shutdown_timer(jme);
1209         }
1210
1211         goto out_enable_tasklet;
1212
1213 err_out_free_rx_resources:
1214         jme_free_rx_resources(jme);
1215 out_enable_tasklet:
1216         tasklet_enable(&jme->txclean_task);
1217         tasklet_hi_enable(&jme->rxclean_task);
1218         tasklet_hi_enable(&jme->rxempty_task);
1219 out:
1220         atomic_inc(&jme->link_changing);
1221 }
1222
1223 static void
1224 jme_rx_clean_tasklet(unsigned long arg)
1225 {
1226         struct jme_adapter *jme = (struct jme_adapter *)arg;
1227         struct dynpcc_info *dpi = &(jme->dpi);
1228
1229         jme_process_receive(jme, jme->rx_ring_size);
1230         ++(dpi->intr_cnt);
1231
1232 }
1233
1234 static int
1235 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1236 {
1237         struct jme_adapter *jme = jme_napi_priv(holder);
1238         struct net_device *netdev = jme->dev;
1239         int rest;
1240
1241         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1242
1243         while (atomic_read(&jme->rx_empty) > 0) {
1244                 atomic_dec(&jme->rx_empty);
1245                 ++(NET_STAT(jme).rx_dropped);
1246                 jme_restart_rx_engine(jme);
1247         }
1248         atomic_inc(&jme->rx_empty);
1249
1250         if (rest) {
1251                 JME_RX_COMPLETE(netdev, holder);
1252                 jme_interrupt_mode(jme);
1253         }
1254
1255         JME_NAPI_WEIGHT_SET(budget, rest);
1256         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1257 }
1258
1259 static void
1260 jme_rx_empty_tasklet(unsigned long arg)
1261 {
1262         struct jme_adapter *jme = (struct jme_adapter *)arg;
1263
1264         if (unlikely(atomic_read(&jme->link_changing) != 1))
1265                 return;
1266
1267         if (unlikely(!netif_carrier_ok(jme->dev)))
1268                 return;
1269
1270         msg_rx_status(jme, "RX Queue Full!\n");
1271
1272         jme_rx_clean_tasklet(arg);
1273
1274         while (atomic_read(&jme->rx_empty) > 0) {
1275                 atomic_dec(&jme->rx_empty);
1276                 ++(NET_STAT(jme).rx_dropped);
1277                 jme_restart_rx_engine(jme);
1278         }
1279         atomic_inc(&jme->rx_empty);
1280 }
1281
1282 static void
1283 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1284 {
1285         struct jme_ring *txring = jme->txring;
1286
1287         smp_wmb();
1288         if (unlikely(netif_queue_stopped(jme->dev) &&
1289         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1290                 msg_tx_done(jme, "TX Queue Waked.\n");
1291                 netif_wake_queue(jme->dev);
1292         }
1293
1294 }
1295
1296 static void
1297 jme_tx_clean_tasklet(unsigned long arg)
1298 {
1299         struct jme_adapter *jme = (struct jme_adapter *)arg;
1300         struct jme_ring *txring = &(jme->txring[0]);
1301         struct txdesc *txdesc = txring->desc;
1302         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1303         int i, j, cnt = 0, max, err, mask;
1304
1305         tx_dbg(jme, "Into txclean.\n");
1306
1307         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1308                 goto out;
1309
1310         if (unlikely(atomic_read(&jme->link_changing) != 1))
1311                 goto out;
1312
1313         if (unlikely(!netif_carrier_ok(jme->dev)))
1314                 goto out;
1315
1316         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1317         mask = jme->tx_ring_mask;
1318
1319         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1320
1321                 ctxbi = txbi + i;
1322
1323                 if (likely(ctxbi->skb &&
1324                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1325
1326                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1327                                         i, ctxbi->nr_desc, jiffies);
1328
1329                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1330
1331                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1332                                 ttxbi = txbi + ((i + j) & (mask));
1333                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1334
1335                                 pci_unmap_page(jme->pdev,
1336                                                  ttxbi->mapping,
1337                                                  ttxbi->len,
1338                                                  PCI_DMA_TODEVICE);
1339
1340                                 ttxbi->mapping = 0;
1341                                 ttxbi->len = 0;
1342                         }
1343
1344                         dev_kfree_skb(ctxbi->skb);
1345
1346                         cnt += ctxbi->nr_desc;
1347
1348                         if (unlikely(err)) {
1349                                 ++(NET_STAT(jme).tx_carrier_errors);
1350                         } else {
1351                                 ++(NET_STAT(jme).tx_packets);
1352                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1353                         }
1354
1355                         ctxbi->skb = NULL;
1356                         ctxbi->len = 0;
1357                         ctxbi->start_xmit = 0;
1358
1359                 } else {
1360                         break;
1361                 }
1362
1363                 i = (i + ctxbi->nr_desc) & mask;
1364
1365                 ctxbi->nr_desc = 0;
1366         }
1367
1368         tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1369         atomic_set(&txring->next_to_clean, i);
1370         atomic_add(cnt, &txring->nr_free);
1371
1372         jme_wake_queue_if_stopped(jme);
1373
1374 out:
1375         atomic_inc(&jme->tx_cleaning);
1376 }
1377
1378 static void
1379 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1380 {
1381         /*
1382          * Disable interrupt
1383          */
1384         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1385
1386         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1387                 /*
1388                  * Link change event is critical
1389                  * all other events are ignored
1390                  */
1391                 jwrite32(jme, JME_IEVE, intrstat);
1392                 tasklet_schedule(&jme->linkch_task);
1393                 goto out_reenable;
1394         }
1395
1396         if (intrstat & INTR_TMINTR) {
1397                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1398                 tasklet_schedule(&jme->pcc_task);
1399         }
1400
1401         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1402                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1403                 tasklet_schedule(&jme->txclean_task);
1404         }
1405
1406         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1407                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1408                                                      INTR_PCCRX0 |
1409                                                      INTR_RX0EMP)) |
1410                                         INTR_RX0);
1411         }
1412
1413         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1414                 if (intrstat & INTR_RX0EMP)
1415                         atomic_inc(&jme->rx_empty);
1416
1417                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1418                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1419                                 jme_polling_mode(jme);
1420                                 JME_RX_SCHEDULE(jme);
1421                         }
1422                 }
1423         } else {
1424                 if (intrstat & INTR_RX0EMP) {
1425                         atomic_inc(&jme->rx_empty);
1426                         tasklet_hi_schedule(&jme->rxempty_task);
1427                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1428                         tasklet_hi_schedule(&jme->rxclean_task);
1429                 }
1430         }
1431
1432 out_reenable:
1433         /*
1434          * Re-enable interrupt
1435          */
1436         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1437 }
1438
1439 static irqreturn_t
1440 jme_intr(int irq, void *dev_id)
1441 {
1442         struct net_device *netdev = dev_id;
1443         struct jme_adapter *jme = netdev_priv(netdev);
1444         u32 intrstat;
1445
1446         intrstat = jread32(jme, JME_IEVE);
1447
1448         /*
1449          * Check if it's really an interrupt for us
1450          */
1451         if (unlikely(intrstat == 0))
1452                 return IRQ_NONE;
1453
1454         /*
1455          * Check if the device still exist
1456          */
1457         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1458                 return IRQ_NONE;
1459
1460         jme_intr_msi(jme, intrstat);
1461
1462         return IRQ_HANDLED;
1463 }
1464
1465 static irqreturn_t
1466 jme_msi(int irq, void *dev_id)
1467 {
1468         struct net_device *netdev = dev_id;
1469         struct jme_adapter *jme = netdev_priv(netdev);
1470         u32 intrstat;
1471
1472         pci_dma_sync_single_for_cpu(jme->pdev,
1473                                     jme->shadow_dma,
1474                                     sizeof(u32) * SHADOW_REG_NR,
1475                                     PCI_DMA_FROMDEVICE);
1476         intrstat = jme->shadow_regs[SHADOW_IEVE];
1477         jme->shadow_regs[SHADOW_IEVE] = 0;
1478
1479         jme_intr_msi(jme, intrstat);
1480
1481         return IRQ_HANDLED;
1482 }
1483
1484 static void
1485 jme_reset_link(struct jme_adapter *jme)
1486 {
1487         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1488 }
1489
1490 static void
1491 jme_restart_an(struct jme_adapter *jme)
1492 {
1493         u32 bmcr;
1494
1495         spin_lock_bh(&jme->phy_lock);
1496         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1497         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1498         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1499         spin_unlock_bh(&jme->phy_lock);
1500 }
1501
1502 static int
1503 jme_request_irq(struct jme_adapter *jme)
1504 {
1505         int rc;
1506         struct net_device *netdev = jme->dev;
1507         irq_handler_t handler = jme_intr;
1508         int irq_flags = IRQF_SHARED;
1509
1510         if (!pci_enable_msi(jme->pdev)) {
1511                 set_bit(JME_FLAG_MSI, &jme->flags);
1512                 handler = jme_msi;
1513                 irq_flags = 0;
1514         }
1515
1516         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1517                           netdev);
1518         if (rc) {
1519                 jeprintk(jme->pdev,
1520                         "Unable to request %s interrupt (return: %d)\n",
1521                         test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1522                         rc);
1523
1524                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1525                         pci_disable_msi(jme->pdev);
1526                         clear_bit(JME_FLAG_MSI, &jme->flags);
1527                 }
1528         } else {
1529                 netdev->irq = jme->pdev->irq;
1530         }
1531
1532         return rc;
1533 }
1534
1535 static void
1536 jme_free_irq(struct jme_adapter *jme)
1537 {
1538         free_irq(jme->pdev->irq, jme->dev);
1539         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1540                 pci_disable_msi(jme->pdev);
1541                 clear_bit(JME_FLAG_MSI, &jme->flags);
1542                 jme->dev->irq = jme->pdev->irq;
1543         }
1544 }
1545
1546 static int
1547 jme_open(struct net_device *netdev)
1548 {
1549         struct jme_adapter *jme = netdev_priv(netdev);
1550         int rc;
1551
1552         jme_clear_pm(jme);
1553         JME_NAPI_ENABLE(jme);
1554
1555         tasklet_enable(&jme->txclean_task);
1556         tasklet_hi_enable(&jme->rxclean_task);
1557         tasklet_hi_enable(&jme->rxempty_task);
1558
1559         rc = jme_request_irq(jme);
1560         if (rc)
1561                 goto err_out;
1562
1563         jme_enable_shadow(jme);
1564         jme_start_irq(jme);
1565
1566         if (test_bit(JME_FLAG_SSET, &jme->flags))
1567                 jme_set_settings(netdev, &jme->old_ecmd);
1568         else
1569                 jme_reset_phy_processor(jme);
1570
1571         jme_reset_link(jme);
1572
1573         return 0;
1574
1575 err_out:
1576         netif_stop_queue(netdev);
1577         netif_carrier_off(netdev);
1578         return rc;
1579 }
1580
1581 static void
1582 jme_set_100m_half(struct jme_adapter *jme)
1583 {
1584         u32 bmcr, tmp;
1585
1586         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1587         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1588                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1589         tmp |= BMCR_SPEED100;
1590
1591         if (bmcr != tmp)
1592                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1593
1594         if (jme->fpgaver)
1595                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1596         else
1597                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1598 }
1599
1600 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1601 static void
1602 jme_wait_link(struct jme_adapter *jme)
1603 {
1604         u32 phylink, to = JME_WAIT_LINK_TIME;
1605
1606         mdelay(1000);
1607         phylink = jme_linkstat_from_phy(jme);
1608         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1609                 mdelay(10);
1610                 phylink = jme_linkstat_from_phy(jme);
1611         }
1612 }
1613
1614 static inline void
1615 jme_phy_off(struct jme_adapter *jme)
1616 {
1617         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1618 }
1619
1620 static int
1621 jme_close(struct net_device *netdev)
1622 {
1623         struct jme_adapter *jme = netdev_priv(netdev);
1624
1625         netif_stop_queue(netdev);
1626         netif_carrier_off(netdev);
1627
1628         jme_stop_irq(jme);
1629         jme_disable_shadow(jme);
1630         jme_free_irq(jme);
1631
1632         JME_NAPI_DISABLE(jme);
1633
1634         tasklet_kill(&jme->linkch_task);
1635         tasklet_kill(&jme->txclean_task);
1636         tasklet_kill(&jme->rxclean_task);
1637         tasklet_kill(&jme->rxempty_task);
1638
1639         jme_reset_ghc_speed(jme);
1640         jme_disable_rx_engine(jme);
1641         jme_disable_tx_engine(jme);
1642         jme_reset_mac_processor(jme);
1643         jme_free_rx_resources(jme);
1644         jme_free_tx_resources(jme);
1645         jme->phylink = 0;
1646         jme_phy_off(jme);
1647
1648         return 0;
1649 }
1650
1651 static int
1652 jme_alloc_txdesc(struct jme_adapter *jme,
1653                         struct sk_buff *skb)
1654 {
1655         struct jme_ring *txring = jme->txring;
1656         int idx, nr_alloc, mask = jme->tx_ring_mask;
1657
1658         idx = txring->next_to_use;
1659         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1660
1661         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1662                 return -1;
1663
1664         atomic_sub(nr_alloc, &txring->nr_free);
1665
1666         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1667
1668         return idx;
1669 }
1670
1671 static void
1672 jme_fill_tx_map(struct pci_dev *pdev,
1673                 struct txdesc *txdesc,
1674                 struct jme_buffer_info *txbi,
1675                 struct page *page,
1676                 u32 page_offset,
1677                 u32 len,
1678                 u8 hidma)
1679 {
1680         dma_addr_t dmaaddr;
1681
1682         dmaaddr = pci_map_page(pdev,
1683                                 page,
1684                                 page_offset,
1685                                 len,
1686                                 PCI_DMA_TODEVICE);
1687
1688         pci_dma_sync_single_for_device(pdev,
1689                                        dmaaddr,
1690                                        len,
1691                                        PCI_DMA_TODEVICE);
1692
1693         txdesc->dw[0] = 0;
1694         txdesc->dw[1] = 0;
1695         txdesc->desc2.flags     = TXFLAG_OWN;
1696         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1697         txdesc->desc2.datalen   = cpu_to_le16(len);
1698         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1699         txdesc->desc2.bufaddrl  = cpu_to_le32(
1700                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1701
1702         txbi->mapping = dmaaddr;
1703         txbi->len = len;
1704 }
1705
1706 static void
1707 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1708 {
1709         struct jme_ring *txring = jme->txring;
1710         struct txdesc *txdesc = txring->desc, *ctxdesc;
1711         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1712         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1713         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1714         int mask = jme->tx_ring_mask;
1715         struct skb_frag_struct *frag;
1716         u32 len;
1717
1718         for (i = 0 ; i < nr_frags ; ++i) {
1719                 frag = &skb_shinfo(skb)->frags[i];
1720                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1721                 ctxbi = txbi + ((idx + i + 2) & (mask));
1722
1723                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1724                                  frag->page_offset, frag->size, hidma);
1725         }
1726
1727         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1728         ctxdesc = txdesc + ((idx + 1) & (mask));
1729         ctxbi = txbi + ((idx + 1) & (mask));
1730         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1731                         offset_in_page(skb->data), len, hidma);
1732
1733 }
1734
1735 static int
1736 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1737 {
1738         if (unlikely(skb_shinfo(skb)->gso_size &&
1739                         skb_header_cloned(skb) &&
1740                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1741                 dev_kfree_skb(skb);
1742                 return -1;
1743         }
1744
1745         return 0;
1746 }
1747
1748 static int
1749 jme_tx_tso(struct sk_buff *skb,
1750                 u16 *mss, u8 *flags)
1751 {
1752         *mss = skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT;
1753         if (*mss) {
1754                 *flags |= TXFLAG_LSEN;
1755
1756                 if (skb->protocol == htons(ETH_P_IP)) {
1757                         struct iphdr *iph = ip_hdr(skb);
1758
1759                         iph->check = 0;
1760                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1761                                                                 iph->daddr, 0,
1762                                                                 IPPROTO_TCP,
1763                                                                 0);
1764                 } else {
1765                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1766
1767                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1768                                                                 &ip6h->daddr, 0,
1769                                                                 IPPROTO_TCP,
1770                                                                 0);
1771                 }
1772
1773                 return 0;
1774         }
1775
1776         return 1;
1777 }
1778
1779 static void
1780 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1781 {
1782         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1783                 u8 ip_proto;
1784
1785                 switch (skb->protocol) {
1786                 case htons(ETH_P_IP):
1787                         ip_proto = ip_hdr(skb)->protocol;
1788                         break;
1789                 case htons(ETH_P_IPV6):
1790                         ip_proto = ipv6_hdr(skb)->nexthdr;
1791                         break;
1792                 default:
1793                         ip_proto = 0;
1794                         break;
1795                 }
1796
1797                 switch (ip_proto) {
1798                 case IPPROTO_TCP:
1799                         *flags |= TXFLAG_TCPCS;
1800                         break;
1801                 case IPPROTO_UDP:
1802                         *flags |= TXFLAG_UDPCS;
1803                         break;
1804                 default:
1805                         msg_tx_err(jme, "Error upper layer protocol.\n");
1806                         break;
1807                 }
1808         }
1809 }
1810
1811 static inline void
1812 jme_tx_vlan(struct sk_buff *skb, u16 *vlan, u8 *flags)
1813 {
1814         if (vlan_tx_tag_present(skb)) {
1815                 *flags |= TXFLAG_TAGON;
1816                 *vlan = vlan_tx_tag_get(skb);
1817         }
1818 }
1819
1820 static int
1821 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1822 {
1823         struct jme_ring *txring = jme->txring;
1824         struct txdesc *txdesc;
1825         struct jme_buffer_info *txbi;
1826         u8 flags;
1827
1828         txdesc = (struct txdesc *)txring->desc + idx;
1829         txbi = txring->bufinf + idx;
1830
1831         txdesc->dw[0] = 0;
1832         txdesc->dw[1] = 0;
1833         txdesc->dw[2] = 0;
1834         txdesc->dw[3] = 0;
1835         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1836         /*
1837          * Set OWN bit at final.
1838          * When kernel transmit faster than NIC.
1839          * And NIC trying to send this descriptor before we tell
1840          * it to start sending this TX queue.
1841          * Other fields are already filled correctly.
1842          */
1843         wmb();
1844         flags = TXFLAG_OWN | TXFLAG_INT;
1845         /*
1846          * Set checksum flags while not tso
1847          */
1848         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1849                 jme_tx_csum(jme, skb, &flags);
1850         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1851         txdesc->desc1.flags = flags;
1852         /*
1853          * Set tx buffer info after telling NIC to send
1854          * For better tx_clean timing
1855          */
1856         wmb();
1857         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1858         txbi->skb = skb;
1859         txbi->len = skb->len;
1860         txbi->start_xmit = jiffies;
1861         if (!txbi->start_xmit)
1862                 txbi->start_xmit = (0UL-1);
1863
1864         return 0;
1865 }
1866
1867 static void
1868 jme_stop_queue_if_full(struct jme_adapter *jme)
1869 {
1870         struct jme_ring *txring = jme->txring;
1871         struct jme_buffer_info *txbi = txring->bufinf;
1872         int idx = atomic_read(&txring->next_to_clean);
1873
1874         txbi += idx;
1875
1876         smp_wmb();
1877         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1878                 netif_stop_queue(jme->dev);
1879                 msg_tx_queued(jme, "TX Queue Paused.\n");
1880                 smp_wmb();
1881                 if (atomic_read(&txring->nr_free)
1882                         >= (jme->tx_wake_threshold)) {
1883                         netif_wake_queue(jme->dev);
1884                         msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1885                 }
1886         }
1887
1888         if (unlikely(txbi->start_xmit &&
1889                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1890                         txbi->skb)) {
1891                 netif_stop_queue(jme->dev);
1892                 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1893         }
1894 }
1895
1896 /*
1897  * This function is already protected by netif_tx_lock()
1898  */
1899
1900 static int
1901 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1902 {
1903         struct jme_adapter *jme = netdev_priv(netdev);
1904         int idx;
1905
1906         if (unlikely(jme_expand_header(jme, skb))) {
1907                 ++(NET_STAT(jme).tx_dropped);
1908                 return NETDEV_TX_OK;
1909         }
1910
1911         idx = jme_alloc_txdesc(jme, skb);
1912
1913         if (unlikely(idx < 0)) {
1914                 netif_stop_queue(netdev);
1915                 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1916
1917                 return NETDEV_TX_BUSY;
1918         }
1919
1920         jme_map_tx_skb(jme, skb, idx);
1921         jme_fill_first_tx_desc(jme, skb, idx);
1922
1923         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1924                                 TXCS_SELECT_QUEUE0 |
1925                                 TXCS_QUEUE0S |
1926                                 TXCS_ENABLE);
1927         netdev->trans_start = jiffies;
1928
1929         tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1930                         skb_shinfo(skb)->nr_frags + 2,
1931                         jiffies);
1932         jme_stop_queue_if_full(jme);
1933
1934         return NETDEV_TX_OK;
1935 }
1936
1937 static int
1938 jme_set_macaddr(struct net_device *netdev, void *p)
1939 {
1940         struct jme_adapter *jme = netdev_priv(netdev);
1941         struct sockaddr *addr = p;
1942         u32 val;
1943
1944         if (netif_running(netdev))
1945                 return -EBUSY;
1946
1947         spin_lock_bh(&jme->macaddr_lock);
1948         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1949
1950         val = (addr->sa_data[3] & 0xff) << 24 |
1951               (addr->sa_data[2] & 0xff) << 16 |
1952               (addr->sa_data[1] & 0xff) <<  8 |
1953               (addr->sa_data[0] & 0xff);
1954         jwrite32(jme, JME_RXUMA_LO, val);
1955         val = (addr->sa_data[5] & 0xff) << 8 |
1956               (addr->sa_data[4] & 0xff);
1957         jwrite32(jme, JME_RXUMA_HI, val);
1958         spin_unlock_bh(&jme->macaddr_lock);
1959
1960         return 0;
1961 }
1962
1963 static void
1964 jme_set_multi(struct net_device *netdev)
1965 {
1966         struct jme_adapter *jme = netdev_priv(netdev);
1967         u32 mc_hash[2] = {};
1968         int i;
1969
1970         spin_lock_bh(&jme->rxmcs_lock);
1971
1972         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1973
1974         if (netdev->flags & IFF_PROMISC) {
1975                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1976         } else if (netdev->flags & IFF_ALLMULTI) {
1977                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1978         } else if (netdev->flags & IFF_MULTICAST) {
1979                 struct dev_mc_list *mclist;
1980                 int bit_nr;
1981
1982                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1983                 for (i = 0, mclist = netdev->mc_list;
1984                         mclist && i < netdev->mc_count;
1985                         ++i, mclist = mclist->next) {
1986
1987                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1988                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1989                 }
1990
1991                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1992                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1993         }
1994
1995         wmb();
1996         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1997
1998         spin_unlock_bh(&jme->rxmcs_lock);
1999 }
2000
2001 static int
2002 jme_change_mtu(struct net_device *netdev, int new_mtu)
2003 {
2004         struct jme_adapter *jme = netdev_priv(netdev);
2005
2006         if (new_mtu == jme->old_mtu)
2007                 return 0;
2008
2009         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2010                 ((new_mtu) < IPV6_MIN_MTU))
2011                 return -EINVAL;
2012
2013         if (new_mtu > 4000) {
2014                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2015                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2016                 jme_restart_rx_engine(jme);
2017         } else {
2018                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2019                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2020                 jme_restart_rx_engine(jme);
2021         }
2022
2023         if (new_mtu > 1900) {
2024                 netdev->features &= ~(NETIF_F_HW_CSUM |
2025                                 NETIF_F_TSO |
2026                                 NETIF_F_TSO6);
2027         } else {
2028                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2029                         netdev->features |= NETIF_F_HW_CSUM;
2030                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2031                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2032         }
2033
2034         netdev->mtu = new_mtu;
2035         jme_reset_link(jme);
2036
2037         return 0;
2038 }
2039
2040 static void
2041 jme_tx_timeout(struct net_device *netdev)
2042 {
2043         struct jme_adapter *jme = netdev_priv(netdev);
2044
2045         jme->phylink = 0;
2046         jme_reset_phy_processor(jme);
2047         if (test_bit(JME_FLAG_SSET, &jme->flags))
2048                 jme_set_settings(netdev, &jme->old_ecmd);
2049
2050         /*
2051          * Force to Reset the link again
2052          */
2053         jme_reset_link(jme);
2054 }
2055
2056 static void
2057 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2058 {
2059         struct jme_adapter *jme = netdev_priv(netdev);
2060
2061         jme->vlgrp = grp;
2062 }
2063
2064 static void
2065 jme_get_drvinfo(struct net_device *netdev,
2066                      struct ethtool_drvinfo *info)
2067 {
2068         struct jme_adapter *jme = netdev_priv(netdev);
2069
2070         strcpy(info->driver, DRV_NAME);
2071         strcpy(info->version, DRV_VERSION);
2072         strcpy(info->bus_info, pci_name(jme->pdev));
2073 }
2074
2075 static int
2076 jme_get_regs_len(struct net_device *netdev)
2077 {
2078         return JME_REG_LEN;
2079 }
2080
2081 static void
2082 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2083 {
2084         int i;
2085
2086         for (i = 0 ; i < len ; i += 4)
2087                 p[i >> 2] = jread32(jme, reg + i);
2088 }
2089
2090 static void
2091 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2092 {
2093         int i;
2094         u16 *p16 = (u16 *)p;
2095
2096         for (i = 0 ; i < reg_nr ; ++i)
2097                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2098 }
2099
2100 static void
2101 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2102 {
2103         struct jme_adapter *jme = netdev_priv(netdev);
2104         u32 *p32 = (u32 *)p;
2105
2106         memset(p, 0xFF, JME_REG_LEN);
2107
2108         regs->version = 1;
2109         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2110
2111         p32 += 0x100 >> 2;
2112         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2113
2114         p32 += 0x100 >> 2;
2115         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2116
2117         p32 += 0x100 >> 2;
2118         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2119
2120         p32 += 0x100 >> 2;
2121         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2122 }
2123
2124 static int
2125 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2126 {
2127         struct jme_adapter *jme = netdev_priv(netdev);
2128
2129         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2130         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2131
2132         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2133                 ecmd->use_adaptive_rx_coalesce = false;
2134                 ecmd->rx_coalesce_usecs = 0;
2135                 ecmd->rx_max_coalesced_frames = 0;
2136                 return 0;
2137         }
2138
2139         ecmd->use_adaptive_rx_coalesce = true;
2140
2141         switch (jme->dpi.cur) {
2142         case PCC_P1:
2143                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2144                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2145                 break;
2146         case PCC_P2:
2147                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2148                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2149                 break;
2150         case PCC_P3:
2151                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2152                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2153                 break;
2154         default:
2155                 break;
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int
2162 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2163 {
2164         struct jme_adapter *jme = netdev_priv(netdev);
2165         struct dynpcc_info *dpi = &(jme->dpi);
2166
2167         if (netif_running(netdev))
2168                 return -EBUSY;
2169
2170         if (ecmd->use_adaptive_rx_coalesce
2171         && test_bit(JME_FLAG_POLL, &jme->flags)) {
2172                 clear_bit(JME_FLAG_POLL, &jme->flags);
2173                 jme->jme_rx = netif_rx;
2174                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2175                 dpi->cur                = PCC_P1;
2176                 dpi->attempt            = PCC_P1;
2177                 dpi->cnt                = 0;
2178                 jme_set_rx_pcc(jme, PCC_P1);
2179                 jme_interrupt_mode(jme);
2180         } else if (!(ecmd->use_adaptive_rx_coalesce)
2181         && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2182                 set_bit(JME_FLAG_POLL, &jme->flags);
2183                 jme->jme_rx = netif_receive_skb;
2184                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2185                 jme_interrupt_mode(jme);
2186         }
2187
2188         return 0;
2189 }
2190
2191 static void
2192 jme_get_pauseparam(struct net_device *netdev,
2193                         struct ethtool_pauseparam *ecmd)
2194 {
2195         struct jme_adapter *jme = netdev_priv(netdev);
2196         u32 val;
2197
2198         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2199         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2200
2201         spin_lock_bh(&jme->phy_lock);
2202         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2203         spin_unlock_bh(&jme->phy_lock);
2204
2205         ecmd->autoneg =
2206                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2207 }
2208
2209 static int
2210 jme_set_pauseparam(struct net_device *netdev,
2211                         struct ethtool_pauseparam *ecmd)
2212 {
2213         struct jme_adapter *jme = netdev_priv(netdev);
2214         u32 val;
2215
2216         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2217                 (ecmd->tx_pause != 0)) {
2218
2219                 if (ecmd->tx_pause)
2220                         jme->reg_txpfc |= TXPFC_PF_EN;
2221                 else
2222                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2223
2224                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2225         }
2226
2227         spin_lock_bh(&jme->rxmcs_lock);
2228         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2229                 (ecmd->rx_pause != 0)) {
2230
2231                 if (ecmd->rx_pause)
2232                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2233                 else
2234                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2235
2236                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2237         }
2238         spin_unlock_bh(&jme->rxmcs_lock);
2239
2240         spin_lock_bh(&jme->phy_lock);
2241         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2242         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2243                 (ecmd->autoneg != 0)) {
2244
2245                 if (ecmd->autoneg)
2246                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2247                 else
2248                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2249
2250                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2251                                 MII_ADVERTISE, val);
2252         }
2253         spin_unlock_bh(&jme->phy_lock);
2254
2255         return 0;
2256 }
2257
2258 static void
2259 jme_get_wol(struct net_device *netdev,
2260                 struct ethtool_wolinfo *wol)
2261 {
2262         struct jme_adapter *jme = netdev_priv(netdev);
2263
2264         wol->supported = WAKE_MAGIC | WAKE_PHY;
2265
2266         wol->wolopts = 0;
2267
2268         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2269                 wol->wolopts |= WAKE_PHY;
2270
2271         if (jme->reg_pmcs & PMCS_MFEN)
2272                 wol->wolopts |= WAKE_MAGIC;
2273
2274 }
2275
2276 static int
2277 jme_set_wol(struct net_device *netdev,
2278                 struct ethtool_wolinfo *wol)
2279 {
2280         struct jme_adapter *jme = netdev_priv(netdev);
2281
2282         if (wol->wolopts & (WAKE_MAGICSECURE |
2283                                 WAKE_UCAST |
2284                                 WAKE_MCAST |
2285                                 WAKE_BCAST |
2286                                 WAKE_ARP))
2287                 return -EOPNOTSUPP;
2288
2289         jme->reg_pmcs = 0;
2290
2291         if (wol->wolopts & WAKE_PHY)
2292                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2293
2294         if (wol->wolopts & WAKE_MAGIC)
2295                 jme->reg_pmcs |= PMCS_MFEN;
2296
2297         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2298
2299         return 0;
2300 }
2301
2302 static int
2303 jme_get_settings(struct net_device *netdev,
2304                      struct ethtool_cmd *ecmd)
2305 {
2306         struct jme_adapter *jme = netdev_priv(netdev);
2307         int rc;
2308
2309         spin_lock_bh(&jme->phy_lock);
2310         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2311         spin_unlock_bh(&jme->phy_lock);
2312         return rc;
2313 }
2314
2315 static int
2316 jme_set_settings(struct net_device *netdev,
2317                      struct ethtool_cmd *ecmd)
2318 {
2319         struct jme_adapter *jme = netdev_priv(netdev);
2320         int rc, fdc = 0;
2321
2322         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2323                 return -EINVAL;
2324
2325         if (jme->mii_if.force_media &&
2326         ecmd->autoneg != AUTONEG_ENABLE &&
2327         (jme->mii_if.full_duplex != ecmd->duplex))
2328                 fdc = 1;
2329
2330         spin_lock_bh(&jme->phy_lock);
2331         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2332         spin_unlock_bh(&jme->phy_lock);
2333
2334         if (!rc && fdc)
2335                 jme_reset_link(jme);
2336
2337         if (!rc) {
2338                 set_bit(JME_FLAG_SSET, &jme->flags);
2339                 jme->old_ecmd = *ecmd;
2340         }
2341
2342         return rc;
2343 }
2344
2345 static u32
2346 jme_get_link(struct net_device *netdev)
2347 {
2348         struct jme_adapter *jme = netdev_priv(netdev);
2349         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2350 }
2351
2352 static u32
2353 jme_get_msglevel(struct net_device *netdev)
2354 {
2355         struct jme_adapter *jme = netdev_priv(netdev);
2356         return jme->msg_enable;
2357 }
2358
2359 static void
2360 jme_set_msglevel(struct net_device *netdev, u32 value)
2361 {
2362         struct jme_adapter *jme = netdev_priv(netdev);
2363         jme->msg_enable = value;
2364 }
2365
2366 static u32
2367 jme_get_rx_csum(struct net_device *netdev)
2368 {
2369         struct jme_adapter *jme = netdev_priv(netdev);
2370         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2371 }
2372
2373 static int
2374 jme_set_rx_csum(struct net_device *netdev, u32 on)
2375 {
2376         struct jme_adapter *jme = netdev_priv(netdev);
2377
2378         spin_lock_bh(&jme->rxmcs_lock);
2379         if (on)
2380                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2381         else
2382                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2383         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2384         spin_unlock_bh(&jme->rxmcs_lock);
2385
2386         return 0;
2387 }
2388
2389 static int
2390 jme_set_tx_csum(struct net_device *netdev, u32 on)
2391 {
2392         struct jme_adapter *jme = netdev_priv(netdev);
2393
2394         if (on) {
2395                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2396                 if (netdev->mtu <= 1900)
2397                         netdev->features |= NETIF_F_HW_CSUM;
2398         } else {
2399                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2400                 netdev->features &= ~NETIF_F_HW_CSUM;
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int
2407 jme_set_tso(struct net_device *netdev, u32 on)
2408 {
2409         struct jme_adapter *jme = netdev_priv(netdev);
2410
2411         if (on) {
2412                 set_bit(JME_FLAG_TSO, &jme->flags);
2413                 if (netdev->mtu <= 1900)
2414                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2415         } else {
2416                 clear_bit(JME_FLAG_TSO, &jme->flags);
2417                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2418         }
2419
2420         return 0;
2421 }
2422
2423 static int
2424 jme_nway_reset(struct net_device *netdev)
2425 {
2426         struct jme_adapter *jme = netdev_priv(netdev);
2427         jme_restart_an(jme);
2428         return 0;
2429 }
2430
2431 static u8
2432 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2433 {
2434         u32 val;
2435         int to;
2436
2437         val = jread32(jme, JME_SMBCSR);
2438         to = JME_SMB_BUSY_TIMEOUT;
2439         while ((val & SMBCSR_BUSY) && --to) {
2440                 msleep(1);
2441                 val = jread32(jme, JME_SMBCSR);
2442         }
2443         if (!to) {
2444                 msg_hw(jme, "SMB Bus Busy.\n");
2445                 return 0xFF;
2446         }
2447
2448         jwrite32(jme, JME_SMBINTF,
2449                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2450                 SMBINTF_HWRWN_READ |
2451                 SMBINTF_HWCMD);
2452
2453         val = jread32(jme, JME_SMBINTF);
2454         to = JME_SMB_BUSY_TIMEOUT;
2455         while ((val & SMBINTF_HWCMD) && --to) {
2456                 msleep(1);
2457                 val = jread32(jme, JME_SMBINTF);
2458         }
2459         if (!to) {
2460                 msg_hw(jme, "SMB Bus Busy.\n");
2461                 return 0xFF;
2462         }
2463
2464         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2465 }
2466
2467 static void
2468 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2469 {
2470         u32 val;
2471         int to;
2472
2473         val = jread32(jme, JME_SMBCSR);
2474         to = JME_SMB_BUSY_TIMEOUT;
2475         while ((val & SMBCSR_BUSY) && --to) {
2476                 msleep(1);
2477                 val = jread32(jme, JME_SMBCSR);
2478         }
2479         if (!to) {
2480                 msg_hw(jme, "SMB Bus Busy.\n");
2481                 return;
2482         }
2483
2484         jwrite32(jme, JME_SMBINTF,
2485                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2486                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2487                 SMBINTF_HWRWN_WRITE |
2488                 SMBINTF_HWCMD);
2489
2490         val = jread32(jme, JME_SMBINTF);
2491         to = JME_SMB_BUSY_TIMEOUT;
2492         while ((val & SMBINTF_HWCMD) && --to) {
2493                 msleep(1);
2494                 val = jread32(jme, JME_SMBINTF);
2495         }
2496         if (!to) {
2497                 msg_hw(jme, "SMB Bus Busy.\n");
2498                 return;
2499         }
2500
2501         mdelay(2);
2502 }
2503
2504 static int
2505 jme_get_eeprom_len(struct net_device *netdev)
2506 {
2507         struct jme_adapter *jme = netdev_priv(netdev);
2508         u32 val;
2509         val = jread32(jme, JME_SMBCSR);
2510         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2511 }
2512
2513 static int
2514 jme_get_eeprom(struct net_device *netdev,
2515                 struct ethtool_eeprom *eeprom, u8 *data)
2516 {
2517         struct jme_adapter *jme = netdev_priv(netdev);
2518         int i, offset = eeprom->offset, len = eeprom->len;
2519
2520         /*
2521          * ethtool will check the boundary for us
2522          */
2523         eeprom->magic = JME_EEPROM_MAGIC;
2524         for (i = 0 ; i < len ; ++i)
2525                 data[i] = jme_smb_read(jme, i + offset);
2526
2527         return 0;
2528 }
2529
2530 static int
2531 jme_set_eeprom(struct net_device *netdev,
2532                 struct ethtool_eeprom *eeprom, u8 *data)
2533 {
2534         struct jme_adapter *jme = netdev_priv(netdev);
2535         int i, offset = eeprom->offset, len = eeprom->len;
2536
2537         if (eeprom->magic != JME_EEPROM_MAGIC)
2538                 return -EINVAL;
2539
2540         /*
2541          * ethtool will check the boundary for us
2542          */
2543         for (i = 0 ; i < len ; ++i)
2544                 jme_smb_write(jme, i + offset, data[i]);
2545
2546         return 0;
2547 }
2548
2549 static const struct ethtool_ops jme_ethtool_ops = {
2550         .get_drvinfo            = jme_get_drvinfo,
2551         .get_regs_len           = jme_get_regs_len,
2552         .get_regs               = jme_get_regs,
2553         .get_coalesce           = jme_get_coalesce,
2554         .set_coalesce           = jme_set_coalesce,
2555         .get_pauseparam         = jme_get_pauseparam,
2556         .set_pauseparam         = jme_set_pauseparam,
2557         .get_wol                = jme_get_wol,
2558         .set_wol                = jme_set_wol,
2559         .get_settings           = jme_get_settings,
2560         .set_settings           = jme_set_settings,
2561         .get_link               = jme_get_link,
2562         .get_msglevel           = jme_get_msglevel,
2563         .set_msglevel           = jme_set_msglevel,
2564         .get_rx_csum            = jme_get_rx_csum,
2565         .set_rx_csum            = jme_set_rx_csum,
2566         .set_tx_csum            = jme_set_tx_csum,
2567         .set_tso                = jme_set_tso,
2568         .set_sg                 = ethtool_op_set_sg,
2569         .nway_reset             = jme_nway_reset,
2570         .get_eeprom_len         = jme_get_eeprom_len,
2571         .get_eeprom             = jme_get_eeprom,
2572         .set_eeprom             = jme_set_eeprom,
2573 };
2574
2575 static int
2576 jme_pci_dma64(struct pci_dev *pdev)
2577 {
2578         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2579                 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2580                         return 1;
2581
2582         if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2583                 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2584                         return 1;
2585
2586         if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2587                 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2588                         return 0;
2589
2590         return -1;
2591 }
2592
2593 static inline void
2594 jme_phy_init(struct jme_adapter *jme)
2595 {
2596         u16 reg26;
2597
2598         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2599         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2600 }
2601
2602 static inline void
2603 jme_check_hw_ver(struct jme_adapter *jme)
2604 {
2605         u32 chipmode;
2606
2607         chipmode = jread32(jme, JME_CHIPMODE);
2608
2609         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2610         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2611 }
2612
2613 static int __devinit
2614 jme_init_one(struct pci_dev *pdev,
2615              const struct pci_device_id *ent)
2616 {
2617         int rc = 0, using_dac, i;
2618         struct net_device *netdev;
2619         struct jme_adapter *jme;
2620         u16 bmcr, bmsr;
2621         u32 apmc;
2622
2623         /*
2624          * set up PCI device basics
2625          */
2626         rc = pci_enable_device(pdev);
2627         if (rc) {
2628                 jeprintk(pdev, "Cannot enable PCI device.\n");
2629                 goto err_out;
2630         }
2631
2632         using_dac = jme_pci_dma64(pdev);
2633         if (using_dac < 0) {
2634                 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2635                 rc = -EIO;
2636                 goto err_out_disable_pdev;
2637         }
2638
2639         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2640                 jeprintk(pdev, "No PCI resource region found.\n");
2641                 rc = -ENOMEM;
2642                 goto err_out_disable_pdev;
2643         }
2644
2645         rc = pci_request_regions(pdev, DRV_NAME);
2646         if (rc) {
2647                 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2648                 goto err_out_disable_pdev;
2649         }
2650
2651         pci_set_master(pdev);
2652
2653         /*
2654          * alloc and init net device
2655          */
2656         netdev = alloc_etherdev(sizeof(*jme));
2657         if (!netdev) {
2658                 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2659                 rc = -ENOMEM;
2660                 goto err_out_release_regions;
2661         }
2662         netdev->open                    = jme_open;
2663         netdev->stop                    = jme_close;
2664         netdev->hard_start_xmit         = jme_start_xmit;
2665         netdev->set_mac_address         = jme_set_macaddr;
2666         netdev->set_multicast_list      = jme_set_multi;
2667         netdev->change_mtu              = jme_change_mtu;
2668         netdev->ethtool_ops             = &jme_ethtool_ops;
2669         netdev->tx_timeout              = jme_tx_timeout;
2670         netdev->watchdog_timeo          = TX_TIMEOUT;
2671         netdev->vlan_rx_register        = jme_vlan_rx_register;
2672         NETDEV_GET_STATS(netdev, &jme_get_stats);
2673         netdev->features                =       NETIF_F_HW_CSUM |
2674                                                 NETIF_F_SG |
2675                                                 NETIF_F_TSO |
2676                                                 NETIF_F_TSO6 |
2677                                                 NETIF_F_HW_VLAN_TX |
2678                                                 NETIF_F_HW_VLAN_RX;
2679         if (using_dac)
2680                 netdev->features        |=      NETIF_F_HIGHDMA;
2681
2682         SET_NETDEV_DEV(netdev, &pdev->dev);
2683         pci_set_drvdata(pdev, netdev);
2684
2685         /*
2686          * init adapter info
2687          */
2688         jme = netdev_priv(netdev);
2689         jme->pdev = pdev;
2690         jme->dev = netdev;
2691         jme->jme_rx = netif_rx;
2692         jme->jme_vlan_rx = vlan_hwaccel_rx;
2693         jme->old_mtu = netdev->mtu = 1500;
2694         jme->phylink = 0;
2695         jme->tx_ring_size = 1 << 10;
2696         jme->tx_ring_mask = jme->tx_ring_size - 1;
2697         jme->tx_wake_threshold = 1 << 9;
2698         jme->rx_ring_size = 1 << 9;
2699         jme->rx_ring_mask = jme->rx_ring_size - 1;
2700         jme->msg_enable = JME_DEF_MSG_ENABLE;
2701         jme->regs = ioremap(pci_resource_start(pdev, 0),
2702                              pci_resource_len(pdev, 0));
2703         if (!(jme->regs)) {
2704                 jeprintk(pdev, "Mapping PCI resource region error.\n");
2705                 rc = -ENOMEM;
2706                 goto err_out_free_netdev;
2707         }
2708         jme->shadow_regs = pci_alloc_consistent(pdev,
2709                                                 sizeof(u32) * SHADOW_REG_NR,
2710                                                 &(jme->shadow_dma));
2711         if (!(jme->shadow_regs)) {
2712                 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2713                 rc = -ENOMEM;
2714                 goto err_out_unmap;
2715         }
2716
2717         if (no_pseudohp) {
2718                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2719                 jwrite32(jme, JME_APMC, apmc);
2720         } else if (force_pseudohp) {
2721                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2722                 jwrite32(jme, JME_APMC, apmc);
2723         }
2724
2725         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2726
2727         spin_lock_init(&jme->phy_lock);
2728         spin_lock_init(&jme->macaddr_lock);
2729         spin_lock_init(&jme->rxmcs_lock);
2730
2731         atomic_set(&jme->link_changing, 1);
2732         atomic_set(&jme->rx_cleaning, 1);
2733         atomic_set(&jme->tx_cleaning, 1);
2734         atomic_set(&jme->rx_empty, 1);
2735
2736         tasklet_init(&jme->pcc_task,
2737                      &jme_pcc_tasklet,
2738                      (unsigned long) jme);
2739         tasklet_init(&jme->linkch_task,
2740                      &jme_link_change_tasklet,
2741                      (unsigned long) jme);
2742         tasklet_init(&jme->txclean_task,
2743                      &jme_tx_clean_tasklet,
2744                      (unsigned long) jme);
2745         tasklet_init(&jme->rxclean_task,
2746                      &jme_rx_clean_tasklet,
2747                      (unsigned long) jme);
2748         tasklet_init(&jme->rxempty_task,
2749                      &jme_rx_empty_tasklet,
2750                      (unsigned long) jme);
2751         tasklet_disable_nosync(&jme->txclean_task);
2752         tasklet_disable_nosync(&jme->rxclean_task);
2753         tasklet_disable_nosync(&jme->rxempty_task);
2754         jme->dpi.cur = PCC_P1;
2755
2756         jme->reg_ghc = 0;
2757         jme->reg_rxcs = RXCS_DEFAULT;
2758         jme->reg_rxmcs = RXMCS_DEFAULT;
2759         jme->reg_txpfc = 0;
2760         jme->reg_pmcs = PMCS_MFEN;
2761         set_bit(JME_FLAG_TXCSUM, &jme->flags);
2762         set_bit(JME_FLAG_TSO, &jme->flags);
2763
2764         /*
2765          * Get Max Read Req Size from PCI Config Space
2766          */
2767         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2768         jme->mrrs &= PCI_DCSR_MRRS_MASK;
2769         switch (jme->mrrs) {
2770         case MRRS_128B:
2771                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2772                 break;
2773         case MRRS_256B:
2774                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2775                 break;
2776         default:
2777                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2778                 break;
2779         };
2780
2781         /*
2782          * Must check before reset_mac_processor
2783          */
2784         jme_check_hw_ver(jme);
2785         jme->mii_if.dev = netdev;
2786         if (jme->fpgaver) {
2787                 jme->mii_if.phy_id = 0;
2788                 for (i = 1 ; i < 32 ; ++i) {
2789                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2790                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2791                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2792                                 jme->mii_if.phy_id = i;
2793                                 break;
2794                         }
2795                 }
2796
2797                 if (!jme->mii_if.phy_id) {
2798                         rc = -EIO;
2799                         jeprintk(pdev, "Can not find phy_id.\n");
2800                          goto err_out_free_shadow;
2801                 }
2802
2803                 jme->reg_ghc |= GHC_LINK_POLL;
2804         } else {
2805                 jme->mii_if.phy_id = 1;
2806         }
2807         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2808                 jme->mii_if.supports_gmii = true;
2809         else
2810                 jme->mii_if.supports_gmii = false;
2811         jme->mii_if.mdio_read = jme_mdio_read;
2812         jme->mii_if.mdio_write = jme_mdio_write;
2813
2814         jme_clear_pm(jme);
2815         jme_set_phyfifoa(jme);
2816         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2817         if (!jme->fpgaver)
2818                 jme_phy_init(jme);
2819         jme_phy_off(jme);
2820
2821         /*
2822          * Reset MAC processor and reload EEPROM for MAC Address
2823          */
2824         jme_reset_mac_processor(jme);
2825         rc = jme_reload_eeprom(jme);
2826         if (rc) {
2827                 jeprintk(pdev,
2828                         "Reload eeprom for reading MAC Address error.\n");
2829                 goto err_out_free_shadow;
2830         }
2831         jme_load_macaddr(netdev);
2832
2833         /*
2834          * Tell stack that we are not ready to work until open()
2835          */
2836         netif_carrier_off(netdev);
2837         netif_stop_queue(netdev);
2838
2839         /*
2840          * Register netdev
2841          */
2842         rc = register_netdev(netdev);
2843         if (rc) {
2844                 jeprintk(pdev, "Cannot register net device.\n");
2845                 goto err_out_free_shadow;
2846         }
2847
2848         msg_probe(jme,
2849                 "JMC250 gigabit%s ver:%x rev:%x "
2850                 "macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
2851                 (jme->fpgaver != 0) ? " (FPGA)" : "",
2852                 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2853                 jme->rev,
2854                 netdev->dev_addr[0],
2855                 netdev->dev_addr[1],
2856                 netdev->dev_addr[2],
2857                 netdev->dev_addr[3],
2858                 netdev->dev_addr[4],
2859                 netdev->dev_addr[5]);
2860
2861         return 0;
2862
2863 err_out_free_shadow:
2864         pci_free_consistent(pdev,
2865                             sizeof(u32) * SHADOW_REG_NR,
2866                             jme->shadow_regs,
2867                             jme->shadow_dma);
2868 err_out_unmap:
2869         iounmap(jme->regs);
2870 err_out_free_netdev:
2871         pci_set_drvdata(pdev, NULL);
2872         free_netdev(netdev);
2873 err_out_release_regions:
2874         pci_release_regions(pdev);
2875 err_out_disable_pdev:
2876         pci_disable_device(pdev);
2877 err_out:
2878         return rc;
2879 }
2880
2881 static void __devexit
2882 jme_remove_one(struct pci_dev *pdev)
2883 {
2884         struct net_device *netdev = pci_get_drvdata(pdev);
2885         struct jme_adapter *jme = netdev_priv(netdev);
2886
2887         unregister_netdev(netdev);
2888         pci_free_consistent(pdev,
2889                             sizeof(u32) * SHADOW_REG_NR,
2890                             jme->shadow_regs,
2891                             jme->shadow_dma);
2892         iounmap(jme->regs);
2893         pci_set_drvdata(pdev, NULL);
2894         free_netdev(netdev);
2895         pci_release_regions(pdev);
2896         pci_disable_device(pdev);
2897
2898 }
2899
2900 static int
2901 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2902 {
2903         struct net_device *netdev = pci_get_drvdata(pdev);
2904         struct jme_adapter *jme = netdev_priv(netdev);
2905
2906         atomic_dec(&jme->link_changing);
2907
2908         netif_device_detach(netdev);
2909         netif_stop_queue(netdev);
2910         jme_stop_irq(jme);
2911
2912         tasklet_disable(&jme->txclean_task);
2913         tasklet_disable(&jme->rxclean_task);
2914         tasklet_disable(&jme->rxempty_task);
2915
2916         jme_disable_shadow(jme);
2917
2918         if (netif_carrier_ok(netdev)) {
2919                 if (test_bit(JME_FLAG_POLL, &jme->flags))
2920                         jme_polling_mode(jme);
2921
2922                 jme_stop_pcc_timer(jme);
2923                 jme_reset_ghc_speed(jme);
2924                 jme_disable_rx_engine(jme);
2925                 jme_disable_tx_engine(jme);
2926                 jme_reset_mac_processor(jme);
2927                 jme_free_rx_resources(jme);
2928                 jme_free_tx_resources(jme);
2929                 netif_carrier_off(netdev);
2930                 jme->phylink = 0;
2931         }
2932
2933         tasklet_enable(&jme->txclean_task);
2934         tasklet_hi_enable(&jme->rxclean_task);
2935         tasklet_hi_enable(&jme->rxempty_task);
2936
2937         pci_save_state(pdev);
2938         if (jme->reg_pmcs) {
2939                 jme_set_100m_half(jme);
2940
2941                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2942                         jme_wait_link(jme);
2943
2944                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2945
2946                 pci_enable_wake(pdev, PCI_D3cold, true);
2947         } else {
2948                 jme_phy_off(jme);
2949         }
2950         pci_set_power_state(pdev, PCI_D3cold);
2951
2952         return 0;
2953 }
2954
2955 static int
2956 jme_resume(struct pci_dev *pdev)
2957 {
2958         struct net_device *netdev = pci_get_drvdata(pdev);
2959         struct jme_adapter *jme = netdev_priv(netdev);
2960
2961         jme_clear_pm(jme);
2962         pci_restore_state(pdev);
2963
2964         if (test_bit(JME_FLAG_SSET, &jme->flags))
2965                 jme_set_settings(netdev, &jme->old_ecmd);
2966         else
2967                 jme_reset_phy_processor(jme);
2968
2969         jme_enable_shadow(jme);
2970         jme_start_irq(jme);
2971         netif_device_attach(netdev);
2972
2973         atomic_inc(&jme->link_changing);
2974
2975         jme_reset_link(jme);
2976
2977         return 0;
2978 }
2979
2980 static struct pci_device_id jme_pci_tbl[] = {
2981         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2982         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
2983         { }
2984 };
2985
2986 static struct pci_driver jme_driver = {
2987         .name           = DRV_NAME,
2988         .id_table       = jme_pci_tbl,
2989         .probe          = jme_init_one,
2990         .remove         = __devexit_p(jme_remove_one),
2991 #ifdef CONFIG_PM
2992         .suspend        = jme_suspend,
2993         .resume         = jme_resume,
2994 #endif /* CONFIG_PM */
2995 };
2996
2997 static int __init
2998 jme_init_module(void)
2999 {
3000         printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3001                "driver version %s\n", DRV_VERSION);
3002         return pci_register_driver(&jme_driver);
3003 }
3004
3005 static void __exit
3006 jme_cleanup_module(void)
3007 {
3008         pci_unregister_driver(&jme_driver);
3009 }
3010
3011 module_init(jme_init_module);
3012 module_exit(jme_cleanup_module);
3013
3014 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3015 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3016 MODULE_LICENSE("GPL");
3017 MODULE_VERSION(DRV_VERSION);
3018 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3019