2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57 "Do not use external plug signal for pseudo hot-plug.");
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
66 jwrite32(jme, JME_SMI, SMI_OP_REQ |
71 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
73 val = jread32(jme, JME_SMI);
74 if ((val & SMI_OP_REQ) == 0)
79 pr_err("phy(%d) read timeout : %d\n", phy, reg);
86 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90 jme_mdio_write(struct net_device *netdev,
91 int phy, int reg, int val)
93 struct jme_adapter *jme = netdev_priv(netdev);
96 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98 smi_phy_addr(phy) | smi_reg_addr(reg));
101 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
103 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112 jme_reset_phy_processor(struct jme_adapter *jme)
116 jme_mdio_write(jme->dev,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
121 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122 jme_mdio_write(jme->dev,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
127 val = jme_mdio_read(jme->dev,
131 jme_mdio_write(jme->dev,
133 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 const u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_mac_rxclk_off(struct jme_adapter *jme)
166 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
171 jme_mac_rxclk_on(struct jme_adapter *jme)
173 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
178 jme_mac_txclk_off(struct jme_adapter *jme)
180 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181 jwrite32f(jme, JME_GHC, jme->reg_ghc);
185 jme_mac_txclk_on(struct jme_adapter *jme)
187 u32 speed = jme->reg_ghc & GHC_SPEED;
188 if (speed == GHC_SPEED_1000M)
189 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
191 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192 jwrite32f(jme, JME_GHC, jme->reg_ghc);
196 jme_reset_ghc_speed(struct jme_adapter *jme)
198 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203 jme_reset_250A2_workaround(struct jme_adapter *jme)
205 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
207 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
211 jme_assert_ghc_reset(struct jme_adapter *jme)
213 jme->reg_ghc |= GHC_SWRST;
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218 jme_clear_ghc_reset(struct jme_adapter *jme)
220 jme->reg_ghc &= ~GHC_SWRST;
221 jwrite32f(jme, JME_GHC, jme->reg_ghc);
225 jme_reset_mac_processor(struct jme_adapter *jme)
227 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
228 u32 crc = 0xCDCDCDCD;
232 jme_reset_ghc_speed(jme);
233 jme_reset_250A2_workaround(jme);
235 jme_mac_rxclk_on(jme);
236 jme_mac_txclk_on(jme);
238 jme_assert_ghc_reset(jme);
240 jme_mac_rxclk_off(jme);
241 jme_mac_txclk_off(jme);
243 jme_clear_ghc_reset(jme);
245 jme_mac_rxclk_on(jme);
246 jme_mac_txclk_on(jme);
248 jme_mac_rxclk_off(jme);
249 jme_mac_txclk_off(jme);
251 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253 jwrite32(jme, JME_RXQDC, 0x00000000);
254 jwrite32(jme, JME_RXNDA, 0x00000000);
255 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257 jwrite32(jme, JME_TXQDC, 0x00000000);
258 jwrite32(jme, JME_TXNDA, 0x00000000);
260 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263 jme_setup_wakeup_frame(jme, mask, crc, i);
265 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
267 gpreg0 = GPREG0_DEFAULT;
268 jwrite32(jme, JME_GPREG0, gpreg0);
272 jme_clear_pm(struct jme_adapter *jme)
274 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
275 pci_set_power_state(jme->pdev, PCI_D0);
276 pci_enable_wake(jme->pdev, PCI_D0, false);
280 jme_reload_eeprom(struct jme_adapter *jme)
285 val = jread32(jme, JME_SMBCSR);
287 if (val & SMBCSR_EEPROMD) {
289 jwrite32(jme, JME_SMBCSR, val);
290 val |= SMBCSR_RELOAD;
291 jwrite32(jme, JME_SMBCSR, val);
294 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
296 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
301 pr_err("eeprom reload timeout\n");
310 jme_load_macaddr(struct net_device *netdev)
312 struct jme_adapter *jme = netdev_priv(netdev);
313 unsigned char macaddr[6];
316 spin_lock_bh(&jme->macaddr_lock);
317 val = jread32(jme, JME_RXUMA_LO);
318 macaddr[0] = (val >> 0) & 0xFF;
319 macaddr[1] = (val >> 8) & 0xFF;
320 macaddr[2] = (val >> 16) & 0xFF;
321 macaddr[3] = (val >> 24) & 0xFF;
322 val = jread32(jme, JME_RXUMA_HI);
323 macaddr[4] = (val >> 0) & 0xFF;
324 macaddr[5] = (val >> 8) & 0xFF;
325 memcpy(netdev->dev_addr, macaddr, 6);
326 spin_unlock_bh(&jme->macaddr_lock);
330 jme_set_rx_pcc(struct jme_adapter *jme, int p)
334 jwrite32(jme, JME_PCCRX0,
335 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
336 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
339 jwrite32(jme, JME_PCCRX0,
340 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
341 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
344 jwrite32(jme, JME_PCCRX0,
345 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
346 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
349 jwrite32(jme, JME_PCCRX0,
350 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
351 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
359 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
363 jme_start_irq(struct jme_adapter *jme)
365 register struct dynpcc_info *dpi = &(jme->dpi);
367 jme_set_rx_pcc(jme, PCC_P1);
369 dpi->attempt = PCC_P1;
372 jwrite32(jme, JME_PCCTX,
373 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
374 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
381 jwrite32(jme, JME_IENS, INTR_ENABLE);
385 jme_stop_irq(struct jme_adapter *jme)
390 jwrite32f(jme, JME_IENC, INTR_ENABLE);
394 jme_linkstat_from_phy(struct jme_adapter *jme)
398 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
399 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
400 if (bmsr & BMSR_ANCOMP)
401 phylink |= PHY_LINK_AUTONEG_COMPLETE;
407 jme_set_phyfifo_5level(struct jme_adapter *jme)
409 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
413 jme_set_phyfifo_8level(struct jme_adapter *jme)
415 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
419 jme_check_link(struct net_device *netdev, int testonly)
421 struct jme_adapter *jme = netdev_priv(netdev);
422 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
429 phylink = jme_linkstat_from_phy(jme);
431 phylink = jread32(jme, JME_PHY_LINK);
433 if (phylink & PHY_LINK_UP) {
434 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
436 * If we did not enable AN
437 * Speed/Duplex Info should be obtained from SMI
439 phylink = PHY_LINK_UP;
441 bmcr = jme_mdio_read(jme->dev,
445 phylink |= ((bmcr & BMCR_SPEED1000) &&
446 (bmcr & BMCR_SPEED100) == 0) ?
447 PHY_LINK_SPEED_1000M :
448 (bmcr & BMCR_SPEED100) ?
449 PHY_LINK_SPEED_100M :
452 phylink |= (bmcr & BMCR_FULLDPLX) ?
455 strcat(linkmsg, "Forced: ");
458 * Keep polling for speed/duplex resolve complete
460 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
466 phylink = jme_linkstat_from_phy(jme);
468 phylink = jread32(jme, JME_PHY_LINK);
471 pr_err("Waiting speed resolve timeout\n");
473 strcat(linkmsg, "ANed: ");
476 if (jme->phylink == phylink) {
483 jme->phylink = phylink;
486 * The speed/duplex setting of jme->reg_ghc already cleared
487 * by jme_reset_mac_processor()
489 switch (phylink & PHY_LINK_SPEED_MASK) {
490 case PHY_LINK_SPEED_10M:
491 jme->reg_ghc |= GHC_SPEED_10M;
492 strcat(linkmsg, "10 Mbps, ");
494 case PHY_LINK_SPEED_100M:
495 jme->reg_ghc |= GHC_SPEED_100M;
496 strcat(linkmsg, "100 Mbps, ");
498 case PHY_LINK_SPEED_1000M:
499 jme->reg_ghc |= GHC_SPEED_1000M;
500 strcat(linkmsg, "1000 Mbps, ");
506 if (phylink & PHY_LINK_DUPLEX) {
507 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
508 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
509 jme->reg_ghc |= GHC_DPX;
511 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
515 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
518 jwrite32(jme, JME_GHC, jme->reg_ghc);
520 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
521 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
523 if (!(phylink & PHY_LINK_DUPLEX))
524 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
525 switch (phylink & PHY_LINK_SPEED_MASK) {
526 case PHY_LINK_SPEED_10M:
527 jme_set_phyfifo_8level(jme);
528 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
530 case PHY_LINK_SPEED_100M:
531 jme_set_phyfifo_5level(jme);
532 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
534 case PHY_LINK_SPEED_1000M:
535 jme_set_phyfifo_8level(jme);
541 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
543 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
546 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
549 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
550 netif_carrier_on(netdev);
555 netif_info(jme, link, jme->dev, "Link is down\n");
557 netif_carrier_off(netdev);
565 jme_setup_tx_resources(struct jme_adapter *jme)
567 struct jme_ring *txring = &(jme->txring[0]);
569 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
570 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
580 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
582 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
583 txring->next_to_use = 0;
584 atomic_set(&txring->next_to_clean, 0);
585 atomic_set(&txring->nr_free, jme->tx_ring_size);
587 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
588 jme->tx_ring_size, GFP_ATOMIC);
589 if (unlikely(!(txring->bufinf)))
590 goto err_free_txring;
593 * Initialize Transmit Descriptors
595 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
596 memset(txring->bufinf, 0,
597 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
602 dma_free_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
609 txring->dmaalloc = 0;
611 txring->bufinf = NULL;
617 jme_free_tx_resources(struct jme_adapter *jme)
620 struct jme_ring *txring = &(jme->txring[0]);
621 struct jme_buffer_info *txbi;
624 if (txring->bufinf) {
625 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
626 txbi = txring->bufinf + i;
628 dev_kfree_skb(txbi->skb);
634 txbi->start_xmit = 0;
636 kfree(txring->bufinf);
639 dma_free_coherent(&(jme->pdev->dev),
640 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
644 txring->alloc = NULL;
646 txring->dmaalloc = 0;
648 txring->bufinf = NULL;
650 txring->next_to_use = 0;
651 atomic_set(&txring->next_to_clean, 0);
652 atomic_set(&txring->nr_free, 0);
656 jme_enable_tx_engine(struct jme_adapter *jme)
661 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
665 * Setup TX Queue 0 DMA Bass Address
667 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
669 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
672 * Setup TX Descptor Count
674 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
680 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
685 * Start clock for TX MAC Processor
687 jme_mac_txclk_on(jme);
691 jme_restart_tx_engine(struct jme_adapter *jme)
696 jwrite32(jme, JME_TXCS, jme->reg_txcs |
702 jme_disable_tx_engine(struct jme_adapter *jme)
710 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
713 val = jread32(jme, JME_TXCS);
714 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
716 val = jread32(jme, JME_TXCS);
721 pr_err("Disable TX engine timeout\n");
724 * Stop clock for TX MAC Processor
726 jme_mac_txclk_off(jme);
730 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
732 struct jme_ring *rxring = &(jme->rxring[0]);
733 register struct rxdesc *rxdesc = rxring->desc;
734 struct jme_buffer_info *rxbi = rxring->bufinf;
740 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
741 rxdesc->desc1.bufaddrl = cpu_to_le32(
742 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
743 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
744 if (jme->dev->features & NETIF_F_HIGHDMA)
745 rxdesc->desc1.flags = RXFLAG_64BIT;
747 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
751 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
753 struct jme_ring *rxring = &(jme->rxring[0]);
754 struct jme_buffer_info *rxbi = rxring->bufinf + i;
757 skb = netdev_alloc_skb(jme->dev,
758 jme->dev->mtu + RX_EXTRA_LEN);
763 rxbi->len = skb_tailroom(skb);
764 rxbi->mapping = pci_map_page(jme->pdev,
765 virt_to_page(skb->data),
766 offset_in_page(skb->data),
774 jme_free_rx_buf(struct jme_adapter *jme, int i)
776 struct jme_ring *rxring = &(jme->rxring[0]);
777 struct jme_buffer_info *rxbi = rxring->bufinf;
781 pci_unmap_page(jme->pdev,
785 dev_kfree_skb(rxbi->skb);
793 jme_free_rx_resources(struct jme_adapter *jme)
796 struct jme_ring *rxring = &(jme->rxring[0]);
799 if (rxring->bufinf) {
800 for (i = 0 ; i < jme->rx_ring_size ; ++i)
801 jme_free_rx_buf(jme, i);
802 kfree(rxring->bufinf);
805 dma_free_coherent(&(jme->pdev->dev),
806 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
809 rxring->alloc = NULL;
811 rxring->dmaalloc = 0;
813 rxring->bufinf = NULL;
815 rxring->next_to_use = 0;
816 atomic_set(&rxring->next_to_clean, 0);
820 jme_setup_rx_resources(struct jme_adapter *jme)
823 struct jme_ring *rxring = &(jme->rxring[0]);
825 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
826 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
835 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
837 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
838 rxring->next_to_use = 0;
839 atomic_set(&rxring->next_to_clean, 0);
841 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
842 jme->rx_ring_size, GFP_ATOMIC);
843 if (unlikely(!(rxring->bufinf)))
844 goto err_free_rxring;
847 * Initiallize Receive Descriptors
849 memset(rxring->bufinf, 0,
850 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
851 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
852 if (unlikely(jme_make_new_rx_buf(jme, i))) {
853 jme_free_rx_resources(jme);
857 jme_set_clean_rxdesc(jme, i);
863 dma_free_coherent(&(jme->pdev->dev),
864 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
869 rxring->dmaalloc = 0;
871 rxring->bufinf = NULL;
877 jme_enable_rx_engine(struct jme_adapter *jme)
882 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
887 * Setup RX DMA Bass Address
889 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
890 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
891 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
894 * Setup RX Descriptor Count
896 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
899 * Setup Unicast Filter
901 jme_set_unicastaddr(jme->dev);
902 jme_set_multi(jme->dev);
908 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
914 * Start clock for RX MAC Processor
916 jme_mac_rxclk_on(jme);
920 jme_restart_rx_engine(struct jme_adapter *jme)
925 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
932 jme_disable_rx_engine(struct jme_adapter *jme)
940 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
943 val = jread32(jme, JME_RXCS);
944 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
946 val = jread32(jme, JME_RXCS);
951 pr_err("Disable RX engine timeout\n");
954 * Stop clock for RX MAC Processor
956 jme_mac_rxclk_off(jme);
960 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
962 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
965 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
966 == RXWBFLAG_TCPON)) {
967 if (flags & RXWBFLAG_IPV4)
968 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
972 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
973 == RXWBFLAG_UDPON)) {
974 if (flags & RXWBFLAG_IPV4)
975 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
979 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
981 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
989 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
991 struct jme_ring *rxring = &(jme->rxring[0]);
992 struct rxdesc *rxdesc = rxring->desc;
993 struct jme_buffer_info *rxbi = rxring->bufinf;
1001 pci_dma_sync_single_for_cpu(jme->pdev,
1004 PCI_DMA_FROMDEVICE);
1006 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1007 pci_dma_sync_single_for_device(jme->pdev,
1010 PCI_DMA_FROMDEVICE);
1012 ++(NET_STAT(jme).rx_dropped);
1014 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1017 skb_reserve(skb, RX_PREPAD_SIZE);
1018 skb_put(skb, framesize);
1019 skb->protocol = eth_type_trans(skb, jme->dev);
1021 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
1022 skb->ip_summed = CHECKSUM_UNNECESSARY;
1024 skb_checksum_none_assert(skb);
1026 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1028 jme->jme_vlan_rx(skb, jme->vlgrp,
1029 le16_to_cpu(rxdesc->descwb.vlan));
1030 NET_STAT(jme).rx_bytes += 4;
1038 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1039 cpu_to_le16(RXWBFLAG_DEST_MUL))
1040 ++(NET_STAT(jme).multicast);
1042 NET_STAT(jme).rx_bytes += framesize;
1043 ++(NET_STAT(jme).rx_packets);
1046 jme_set_clean_rxdesc(jme, idx);
1051 jme_process_receive(struct jme_adapter *jme, int limit)
1053 struct jme_ring *rxring = &(jme->rxring[0]);
1054 struct rxdesc *rxdesc = rxring->desc;
1055 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1057 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1060 if (unlikely(atomic_read(&jme->link_changing) != 1))
1063 if (unlikely(!netif_carrier_ok(jme->dev)))
1066 i = atomic_read(&rxring->next_to_clean);
1068 rxdesc = rxring->desc;
1071 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1072 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1077 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1079 if (unlikely(desccnt > 1 ||
1080 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1082 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1083 ++(NET_STAT(jme).rx_crc_errors);
1084 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1085 ++(NET_STAT(jme).rx_fifo_errors);
1087 ++(NET_STAT(jme).rx_errors);
1090 limit -= desccnt - 1;
1092 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1093 jme_set_clean_rxdesc(jme, j);
1094 j = (j + 1) & (mask);
1098 jme_alloc_and_feed_skb(jme, i);
1101 i = (i + desccnt) & (mask);
1105 atomic_set(&rxring->next_to_clean, i);
1108 atomic_inc(&jme->rx_cleaning);
1110 return limit > 0 ? limit : 0;
1115 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1117 if (likely(atmp == dpi->cur)) {
1122 if (dpi->attempt == atmp) {
1125 dpi->attempt = atmp;
1132 jme_dynamic_pcc(struct jme_adapter *jme)
1134 register struct dynpcc_info *dpi = &(jme->dpi);
1136 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1137 jme_attempt_pcc(dpi, PCC_P3);
1138 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1139 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1140 jme_attempt_pcc(dpi, PCC_P2);
1142 jme_attempt_pcc(dpi, PCC_P1);
1144 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1145 if (dpi->attempt < dpi->cur)
1146 tasklet_schedule(&jme->rxclean_task);
1147 jme_set_rx_pcc(jme, dpi->attempt);
1148 dpi->cur = dpi->attempt;
1154 jme_start_pcc_timer(struct jme_adapter *jme)
1156 struct dynpcc_info *dpi = &(jme->dpi);
1157 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1158 dpi->last_pkts = NET_STAT(jme).rx_packets;
1160 jwrite32(jme, JME_TMCSR,
1161 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1165 jme_stop_pcc_timer(struct jme_adapter *jme)
1167 jwrite32(jme, JME_TMCSR, 0);
1171 jme_shutdown_nic(struct jme_adapter *jme)
1175 phylink = jme_linkstat_from_phy(jme);
1177 if (!(phylink & PHY_LINK_UP)) {
1179 * Disable all interrupt before issue timer
1182 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1187 jme_pcc_tasklet(unsigned long arg)
1189 struct jme_adapter *jme = (struct jme_adapter *)arg;
1190 struct net_device *netdev = jme->dev;
1192 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1193 jme_shutdown_nic(jme);
1197 if (unlikely(!netif_carrier_ok(netdev) ||
1198 (atomic_read(&jme->link_changing) != 1)
1200 jme_stop_pcc_timer(jme);
1204 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1205 jme_dynamic_pcc(jme);
1207 jme_start_pcc_timer(jme);
1211 jme_polling_mode(struct jme_adapter *jme)
1213 jme_set_rx_pcc(jme, PCC_OFF);
1217 jme_interrupt_mode(struct jme_adapter *jme)
1219 jme_set_rx_pcc(jme, PCC_P1);
1223 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1226 apmc = jread32(jme, JME_APMC);
1227 return apmc & JME_APMC_PSEUDO_HP_EN;
1231 jme_start_shutdown_timer(struct jme_adapter *jme)
1235 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1236 apmc &= ~JME_APMC_EPIEN_CTRL;
1238 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1241 jwrite32f(jme, JME_APMC, apmc);
1243 jwrite32f(jme, JME_TIMER2, 0);
1244 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1245 jwrite32(jme, JME_TMCSR,
1246 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1250 jme_stop_shutdown_timer(struct jme_adapter *jme)
1254 jwrite32f(jme, JME_TMCSR, 0);
1255 jwrite32f(jme, JME_TIMER2, 0);
1256 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1258 apmc = jread32(jme, JME_APMC);
1259 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1260 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1262 jwrite32f(jme, JME_APMC, apmc);
1266 jme_link_change_tasklet(unsigned long arg)
1268 struct jme_adapter *jme = (struct jme_adapter *)arg;
1269 struct net_device *netdev = jme->dev;
1272 while (!atomic_dec_and_test(&jme->link_changing)) {
1273 atomic_inc(&jme->link_changing);
1274 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1275 while (atomic_read(&jme->link_changing) != 1)
1276 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1279 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1282 jme->old_mtu = netdev->mtu;
1283 netif_stop_queue(netdev);
1284 if (jme_pseudo_hotplug_enabled(jme))
1285 jme_stop_shutdown_timer(jme);
1287 jme_stop_pcc_timer(jme);
1288 tasklet_disable(&jme->txclean_task);
1289 tasklet_disable(&jme->rxclean_task);
1290 tasklet_disable(&jme->rxempty_task);
1292 if (netif_carrier_ok(netdev)) {
1293 jme_disable_rx_engine(jme);
1294 jme_disable_tx_engine(jme);
1295 jme_reset_mac_processor(jme);
1296 jme_free_rx_resources(jme);
1297 jme_free_tx_resources(jme);
1299 if (test_bit(JME_FLAG_POLL, &jme->flags))
1300 jme_polling_mode(jme);
1302 netif_carrier_off(netdev);
1305 jme_check_link(netdev, 0);
1306 if (netif_carrier_ok(netdev)) {
1307 rc = jme_setup_rx_resources(jme);
1309 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1310 goto out_enable_tasklet;
1313 rc = jme_setup_tx_resources(jme);
1315 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1316 goto err_out_free_rx_resources;
1319 jme_enable_rx_engine(jme);
1320 jme_enable_tx_engine(jme);
1322 netif_start_queue(netdev);
1324 if (test_bit(JME_FLAG_POLL, &jme->flags))
1325 jme_interrupt_mode(jme);
1327 jme_start_pcc_timer(jme);
1328 } else if (jme_pseudo_hotplug_enabled(jme)) {
1329 jme_start_shutdown_timer(jme);
1332 goto out_enable_tasklet;
1334 err_out_free_rx_resources:
1335 jme_free_rx_resources(jme);
1337 tasklet_enable(&jme->txclean_task);
1338 tasklet_hi_enable(&jme->rxclean_task);
1339 tasklet_hi_enable(&jme->rxempty_task);
1341 atomic_inc(&jme->link_changing);
1345 jme_rx_clean_tasklet(unsigned long arg)
1347 struct jme_adapter *jme = (struct jme_adapter *)arg;
1348 struct dynpcc_info *dpi = &(jme->dpi);
1350 jme_process_receive(jme, jme->rx_ring_size);
1356 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1358 struct jme_adapter *jme = jme_napi_priv(holder);
1361 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1363 while (atomic_read(&jme->rx_empty) > 0) {
1364 atomic_dec(&jme->rx_empty);
1365 ++(NET_STAT(jme).rx_dropped);
1366 jme_restart_rx_engine(jme);
1368 atomic_inc(&jme->rx_empty);
1371 JME_RX_COMPLETE(netdev, holder);
1372 jme_interrupt_mode(jme);
1375 JME_NAPI_WEIGHT_SET(budget, rest);
1376 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1380 jme_rx_empty_tasklet(unsigned long arg)
1382 struct jme_adapter *jme = (struct jme_adapter *)arg;
1384 if (unlikely(atomic_read(&jme->link_changing) != 1))
1387 if (unlikely(!netif_carrier_ok(jme->dev)))
1390 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1392 jme_rx_clean_tasklet(arg);
1394 while (atomic_read(&jme->rx_empty) > 0) {
1395 atomic_dec(&jme->rx_empty);
1396 ++(NET_STAT(jme).rx_dropped);
1397 jme_restart_rx_engine(jme);
1399 atomic_inc(&jme->rx_empty);
1403 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1405 struct jme_ring *txring = &(jme->txring[0]);
1408 if (unlikely(netif_queue_stopped(jme->dev) &&
1409 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1410 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1411 netif_wake_queue(jme->dev);
1417 jme_tx_clean_tasklet(unsigned long arg)
1419 struct jme_adapter *jme = (struct jme_adapter *)arg;
1420 struct jme_ring *txring = &(jme->txring[0]);
1421 struct txdesc *txdesc = txring->desc;
1422 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1423 int i, j, cnt = 0, max, err, mask;
1425 tx_dbg(jme, "Into txclean\n");
1427 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1430 if (unlikely(atomic_read(&jme->link_changing) != 1))
1433 if (unlikely(!netif_carrier_ok(jme->dev)))
1436 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1437 mask = jme->tx_ring_mask;
1439 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1443 if (likely(ctxbi->skb &&
1444 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1446 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1447 i, ctxbi->nr_desc, jiffies);
1449 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1451 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1452 ttxbi = txbi + ((i + j) & (mask));
1453 txdesc[(i + j) & (mask)].dw[0] = 0;
1455 pci_unmap_page(jme->pdev,
1464 dev_kfree_skb(ctxbi->skb);
1466 cnt += ctxbi->nr_desc;
1468 if (unlikely(err)) {
1469 ++(NET_STAT(jme).tx_carrier_errors);
1471 ++(NET_STAT(jme).tx_packets);
1472 NET_STAT(jme).tx_bytes += ctxbi->len;
1477 ctxbi->start_xmit = 0;
1483 i = (i + ctxbi->nr_desc) & mask;
1488 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1489 atomic_set(&txring->next_to_clean, i);
1490 atomic_add(cnt, &txring->nr_free);
1492 jme_wake_queue_if_stopped(jme);
1495 atomic_inc(&jme->tx_cleaning);
1499 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1504 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1506 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1508 * Link change event is critical
1509 * all other events are ignored
1511 jwrite32(jme, JME_IEVE, intrstat);
1512 tasklet_schedule(&jme->linkch_task);
1516 if (intrstat & INTR_TMINTR) {
1517 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1518 tasklet_schedule(&jme->pcc_task);
1521 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1522 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1523 tasklet_schedule(&jme->txclean_task);
1526 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1527 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1533 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1534 if (intrstat & INTR_RX0EMP)
1535 atomic_inc(&jme->rx_empty);
1537 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1538 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1539 jme_polling_mode(jme);
1540 JME_RX_SCHEDULE(jme);
1544 if (intrstat & INTR_RX0EMP) {
1545 atomic_inc(&jme->rx_empty);
1546 tasklet_hi_schedule(&jme->rxempty_task);
1547 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1548 tasklet_hi_schedule(&jme->rxclean_task);
1554 * Re-enable interrupt
1556 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1560 jme_intr(int irq, void *dev_id)
1562 struct net_device *netdev = dev_id;
1563 struct jme_adapter *jme = netdev_priv(netdev);
1566 intrstat = jread32(jme, JME_IEVE);
1569 * Check if it's really an interrupt for us
1571 if (unlikely((intrstat & INTR_ENABLE) == 0))
1575 * Check if the device still exist
1577 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1580 jme_intr_msi(jme, intrstat);
1586 jme_msi(int irq, void *dev_id)
1588 struct net_device *netdev = dev_id;
1589 struct jme_adapter *jme = netdev_priv(netdev);
1592 intrstat = jread32(jme, JME_IEVE);
1594 jme_intr_msi(jme, intrstat);
1600 jme_reset_link(struct jme_adapter *jme)
1602 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1606 jme_restart_an(struct jme_adapter *jme)
1610 spin_lock_bh(&jme->phy_lock);
1611 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1612 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1613 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1614 spin_unlock_bh(&jme->phy_lock);
1618 jme_request_irq(struct jme_adapter *jme)
1621 struct net_device *netdev = jme->dev;
1622 irq_handler_t handler = jme_intr;
1623 int irq_flags = IRQF_SHARED;
1625 if (!pci_enable_msi(jme->pdev)) {
1626 set_bit(JME_FLAG_MSI, &jme->flags);
1631 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1635 "Unable to request %s interrupt (return: %d)\n",
1636 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1639 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1640 pci_disable_msi(jme->pdev);
1641 clear_bit(JME_FLAG_MSI, &jme->flags);
1644 netdev->irq = jme->pdev->irq;
1651 jme_free_irq(struct jme_adapter *jme)
1653 free_irq(jme->pdev->irq, jme->dev);
1654 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1655 pci_disable_msi(jme->pdev);
1656 clear_bit(JME_FLAG_MSI, &jme->flags);
1657 jme->dev->irq = jme->pdev->irq;
1662 jme_new_phy_on(struct jme_adapter *jme)
1666 reg = jread32(jme, JME_PHY_PWR);
1667 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1668 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1669 jwrite32(jme, JME_PHY_PWR, reg);
1671 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1672 reg &= ~PE1_GPREG0_PBG;
1673 reg |= PE1_GPREG0_ENBG;
1674 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1678 jme_new_phy_off(struct jme_adapter *jme)
1682 reg = jread32(jme, JME_PHY_PWR);
1683 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1684 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1685 jwrite32(jme, JME_PHY_PWR, reg);
1687 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1688 reg &= ~PE1_GPREG0_PBG;
1689 reg |= PE1_GPREG0_PDD3COLD;
1690 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1694 jme_phy_on(struct jme_adapter *jme)
1698 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1699 bmcr &= ~BMCR_PDOWN;
1700 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1702 if (new_phy_power_ctrl(jme->chip_main_rev))
1703 jme_new_phy_on(jme);
1707 jme_phy_off(struct jme_adapter *jme)
1711 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1713 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1715 if (new_phy_power_ctrl(jme->chip_main_rev))
1716 jme_new_phy_off(jme);
1720 jme_open(struct net_device *netdev)
1722 struct jme_adapter *jme = netdev_priv(netdev);
1726 JME_NAPI_ENABLE(jme);
1728 tasklet_enable(&jme->linkch_task);
1729 tasklet_enable(&jme->txclean_task);
1730 tasklet_hi_enable(&jme->rxclean_task);
1731 tasklet_hi_enable(&jme->rxempty_task);
1733 rc = jme_request_irq(jme);
1740 if (test_bit(JME_FLAG_SSET, &jme->flags))
1741 jme_set_settings(netdev, &jme->old_ecmd);
1743 jme_reset_phy_processor(jme);
1745 jme_reset_link(jme);
1750 netif_stop_queue(netdev);
1751 netif_carrier_off(netdev);
1756 jme_set_100m_half(struct jme_adapter *jme)
1761 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1762 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1763 BMCR_SPEED1000 | BMCR_FULLDPLX);
1764 tmp |= BMCR_SPEED100;
1767 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1770 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1772 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1775 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1777 jme_wait_link(struct jme_adapter *jme)
1779 u32 phylink, to = JME_WAIT_LINK_TIME;
1782 phylink = jme_linkstat_from_phy(jme);
1783 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1785 phylink = jme_linkstat_from_phy(jme);
1790 jme_powersave_phy(struct jme_adapter *jme)
1792 if (jme->reg_pmcs) {
1793 jme_set_100m_half(jme);
1795 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1798 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1805 jme_close(struct net_device *netdev)
1807 struct jme_adapter *jme = netdev_priv(netdev);
1809 netif_stop_queue(netdev);
1810 netif_carrier_off(netdev);
1815 JME_NAPI_DISABLE(jme);
1817 tasklet_disable(&jme->linkch_task);
1818 tasklet_disable(&jme->txclean_task);
1819 tasklet_disable(&jme->rxclean_task);
1820 tasklet_disable(&jme->rxempty_task);
1822 jme_disable_rx_engine(jme);
1823 jme_disable_tx_engine(jme);
1824 jme_reset_mac_processor(jme);
1825 jme_free_rx_resources(jme);
1826 jme_free_tx_resources(jme);
1834 jme_alloc_txdesc(struct jme_adapter *jme,
1835 struct sk_buff *skb)
1837 struct jme_ring *txring = &(jme->txring[0]);
1838 int idx, nr_alloc, mask = jme->tx_ring_mask;
1840 idx = txring->next_to_use;
1841 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1843 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1846 atomic_sub(nr_alloc, &txring->nr_free);
1848 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1854 jme_fill_tx_map(struct pci_dev *pdev,
1855 struct txdesc *txdesc,
1856 struct jme_buffer_info *txbi,
1864 dmaaddr = pci_map_page(pdev,
1870 pci_dma_sync_single_for_device(pdev,
1877 txdesc->desc2.flags = TXFLAG_OWN;
1878 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1879 txdesc->desc2.datalen = cpu_to_le16(len);
1880 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1881 txdesc->desc2.bufaddrl = cpu_to_le32(
1882 (__u64)dmaaddr & 0xFFFFFFFFUL);
1884 txbi->mapping = dmaaddr;
1889 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1891 struct jme_ring *txring = &(jme->txring[0]);
1892 struct txdesc *txdesc = txring->desc, *ctxdesc;
1893 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1894 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1895 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1896 int mask = jme->tx_ring_mask;
1897 struct skb_frag_struct *frag;
1900 for (i = 0 ; i < nr_frags ; ++i) {
1901 frag = &skb_shinfo(skb)->frags[i];
1902 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1903 ctxbi = txbi + ((idx + i + 2) & (mask));
1905 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1906 frag->page_offset, frag->size, hidma);
1909 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1910 ctxdesc = txdesc + ((idx + 1) & (mask));
1911 ctxbi = txbi + ((idx + 1) & (mask));
1912 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1913 offset_in_page(skb->data), len, hidma);
1918 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1920 if (unlikely(skb_shinfo(skb)->gso_size &&
1921 skb_header_cloned(skb) &&
1922 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1931 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1933 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1935 *flags |= TXFLAG_LSEN;
1937 if (skb->protocol == htons(ETH_P_IP)) {
1938 struct iphdr *iph = ip_hdr(skb);
1941 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1946 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1948 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1961 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1963 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1966 switch (skb->protocol) {
1967 case htons(ETH_P_IP):
1968 ip_proto = ip_hdr(skb)->protocol;
1970 case htons(ETH_P_IPV6):
1971 ip_proto = ipv6_hdr(skb)->nexthdr;
1980 *flags |= TXFLAG_TCPCS;
1983 *flags |= TXFLAG_UDPCS;
1986 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1993 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1995 if (vlan_tx_tag_present(skb)) {
1996 *flags |= TXFLAG_TAGON;
1997 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2002 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2004 struct jme_ring *txring = &(jme->txring[0]);
2005 struct txdesc *txdesc;
2006 struct jme_buffer_info *txbi;
2009 txdesc = (struct txdesc *)txring->desc + idx;
2010 txbi = txring->bufinf + idx;
2016 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2018 * Set OWN bit at final.
2019 * When kernel transmit faster than NIC.
2020 * And NIC trying to send this descriptor before we tell
2021 * it to start sending this TX queue.
2022 * Other fields are already filled correctly.
2025 flags = TXFLAG_OWN | TXFLAG_INT;
2027 * Set checksum flags while not tso
2029 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2030 jme_tx_csum(jme, skb, &flags);
2031 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2032 jme_map_tx_skb(jme, skb, idx);
2033 txdesc->desc1.flags = flags;
2035 * Set tx buffer info after telling NIC to send
2036 * For better tx_clean timing
2039 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2041 txbi->len = skb->len;
2042 txbi->start_xmit = jiffies;
2043 if (!txbi->start_xmit)
2044 txbi->start_xmit = (0UL-1);
2050 jme_stop_queue_if_full(struct jme_adapter *jme)
2052 struct jme_ring *txring = &(jme->txring[0]);
2053 struct jme_buffer_info *txbi = txring->bufinf;
2054 int idx = atomic_read(&txring->next_to_clean);
2059 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2060 netif_stop_queue(jme->dev);
2061 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2063 if (atomic_read(&txring->nr_free)
2064 >= (jme->tx_wake_threshold)) {
2065 netif_wake_queue(jme->dev);
2066 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2070 if (unlikely(txbi->start_xmit &&
2071 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2073 netif_stop_queue(jme->dev);
2074 netif_info(jme, tx_queued, jme->dev,
2075 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2080 * This function is already protected by netif_tx_lock()
2084 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2086 struct jme_adapter *jme = netdev_priv(netdev);
2089 if (unlikely(jme_expand_header(jme, skb))) {
2090 ++(NET_STAT(jme).tx_dropped);
2091 return NETDEV_TX_OK;
2094 idx = jme_alloc_txdesc(jme, skb);
2096 if (unlikely(idx < 0)) {
2097 netif_stop_queue(netdev);
2098 netif_err(jme, tx_err, jme->dev,
2099 "BUG! Tx ring full when queue awake!\n");
2101 return NETDEV_TX_BUSY;
2104 jme_fill_tx_desc(jme, skb, idx);
2106 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2107 TXCS_SELECT_QUEUE0 |
2111 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2112 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2113 jme_stop_queue_if_full(jme);
2115 return NETDEV_TX_OK;
2119 jme_set_unicastaddr(struct net_device *netdev)
2121 struct jme_adapter *jme = netdev_priv(netdev);
2124 val = (netdev->dev_addr[3] & 0xff) << 24 |
2125 (netdev->dev_addr[2] & 0xff) << 16 |
2126 (netdev->dev_addr[1] & 0xff) << 8 |
2127 (netdev->dev_addr[0] & 0xff);
2128 jwrite32(jme, JME_RXUMA_LO, val);
2129 val = (netdev->dev_addr[5] & 0xff) << 8 |
2130 (netdev->dev_addr[4] & 0xff);
2131 jwrite32(jme, JME_RXUMA_HI, val);
2135 jme_set_macaddr(struct net_device *netdev, void *p)
2137 struct jme_adapter *jme = netdev_priv(netdev);
2138 struct sockaddr *addr = p;
2140 if (netif_running(netdev))
2143 spin_lock_bh(&jme->macaddr_lock);
2144 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2145 jme_set_unicastaddr(netdev);
2146 spin_unlock_bh(&jme->macaddr_lock);
2152 jme_set_multi(struct net_device *netdev)
2154 struct jme_adapter *jme = netdev_priv(netdev);
2155 u32 mc_hash[2] = {};
2157 spin_lock_bh(&jme->rxmcs_lock);
2159 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2161 if (netdev->flags & IFF_PROMISC) {
2162 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2163 } else if (netdev->flags & IFF_ALLMULTI) {
2164 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2165 } else if (netdev->flags & IFF_MULTICAST) {
2166 struct netdev_hw_addr *ha;
2169 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2170 netdev_for_each_mc_addr(ha, netdev) {
2171 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2172 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2175 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2176 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2180 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2182 spin_unlock_bh(&jme->rxmcs_lock);
2186 jme_change_mtu(struct net_device *netdev, int new_mtu)
2188 struct jme_adapter *jme = netdev_priv(netdev);
2190 if (new_mtu == jme->old_mtu)
2193 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2194 ((new_mtu) < IPV6_MIN_MTU))
2197 if (new_mtu > 4000) {
2198 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2199 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2200 jme_restart_rx_engine(jme);
2202 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2203 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2204 jme_restart_rx_engine(jme);
2207 if (new_mtu > 1900) {
2208 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2209 NETIF_F_TSO | NETIF_F_TSO6);
2211 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2212 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2213 if (test_bit(JME_FLAG_TSO, &jme->flags))
2214 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2217 netdev->mtu = new_mtu;
2218 jme_reset_link(jme);
2224 jme_tx_timeout(struct net_device *netdev)
2226 struct jme_adapter *jme = netdev_priv(netdev);
2229 jme_reset_phy_processor(jme);
2230 if (test_bit(JME_FLAG_SSET, &jme->flags))
2231 jme_set_settings(netdev, &jme->old_ecmd);
2234 * Force to Reset the link again
2236 jme_reset_link(jme);
2239 static inline void jme_pause_rx(struct jme_adapter *jme)
2241 atomic_dec(&jme->link_changing);
2243 jme_set_rx_pcc(jme, PCC_OFF);
2244 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2245 JME_NAPI_DISABLE(jme);
2247 tasklet_disable(&jme->rxclean_task);
2248 tasklet_disable(&jme->rxempty_task);
2252 static inline void jme_resume_rx(struct jme_adapter *jme)
2254 struct dynpcc_info *dpi = &(jme->dpi);
2256 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2257 JME_NAPI_ENABLE(jme);
2259 tasklet_hi_enable(&jme->rxclean_task);
2260 tasklet_hi_enable(&jme->rxempty_task);
2263 dpi->attempt = PCC_P1;
2265 jme_set_rx_pcc(jme, PCC_P1);
2267 atomic_inc(&jme->link_changing);
2271 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2273 struct jme_adapter *jme = netdev_priv(netdev);
2281 jme_get_drvinfo(struct net_device *netdev,
2282 struct ethtool_drvinfo *info)
2284 struct jme_adapter *jme = netdev_priv(netdev);
2286 strcpy(info->driver, DRV_NAME);
2287 strcpy(info->version, DRV_VERSION);
2288 strcpy(info->bus_info, pci_name(jme->pdev));
2292 jme_get_regs_len(struct net_device *netdev)
2298 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2302 for (i = 0 ; i < len ; i += 4)
2303 p[i >> 2] = jread32(jme, reg + i);
2307 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2310 u16 *p16 = (u16 *)p;
2312 for (i = 0 ; i < reg_nr ; ++i)
2313 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2317 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2319 struct jme_adapter *jme = netdev_priv(netdev);
2320 u32 *p32 = (u32 *)p;
2322 memset(p, 0xFF, JME_REG_LEN);
2325 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2328 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2331 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2334 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2337 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2341 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2343 struct jme_adapter *jme = netdev_priv(netdev);
2345 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2346 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2348 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2349 ecmd->use_adaptive_rx_coalesce = false;
2350 ecmd->rx_coalesce_usecs = 0;
2351 ecmd->rx_max_coalesced_frames = 0;
2355 ecmd->use_adaptive_rx_coalesce = true;
2357 switch (jme->dpi.cur) {
2359 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2360 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2363 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2364 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2367 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2368 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2378 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2380 struct jme_adapter *jme = netdev_priv(netdev);
2381 struct dynpcc_info *dpi = &(jme->dpi);
2383 if (netif_running(netdev))
2386 if (ecmd->use_adaptive_rx_coalesce &&
2387 test_bit(JME_FLAG_POLL, &jme->flags)) {
2388 clear_bit(JME_FLAG_POLL, &jme->flags);
2389 jme->jme_rx = netif_rx;
2390 jme->jme_vlan_rx = vlan_hwaccel_rx;
2392 dpi->attempt = PCC_P1;
2394 jme_set_rx_pcc(jme, PCC_P1);
2395 jme_interrupt_mode(jme);
2396 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2397 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2398 set_bit(JME_FLAG_POLL, &jme->flags);
2399 jme->jme_rx = netif_receive_skb;
2400 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2401 jme_interrupt_mode(jme);
2408 jme_get_pauseparam(struct net_device *netdev,
2409 struct ethtool_pauseparam *ecmd)
2411 struct jme_adapter *jme = netdev_priv(netdev);
2414 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2415 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2417 spin_lock_bh(&jme->phy_lock);
2418 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2419 spin_unlock_bh(&jme->phy_lock);
2422 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2426 jme_set_pauseparam(struct net_device *netdev,
2427 struct ethtool_pauseparam *ecmd)
2429 struct jme_adapter *jme = netdev_priv(netdev);
2432 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2433 (ecmd->tx_pause != 0)) {
2436 jme->reg_txpfc |= TXPFC_PF_EN;
2438 jme->reg_txpfc &= ~TXPFC_PF_EN;
2440 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2443 spin_lock_bh(&jme->rxmcs_lock);
2444 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2445 (ecmd->rx_pause != 0)) {
2448 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2450 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2452 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2454 spin_unlock_bh(&jme->rxmcs_lock);
2456 spin_lock_bh(&jme->phy_lock);
2457 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2458 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2459 (ecmd->autoneg != 0)) {
2462 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2464 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2466 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2467 MII_ADVERTISE, val);
2469 spin_unlock_bh(&jme->phy_lock);
2475 jme_get_wol(struct net_device *netdev,
2476 struct ethtool_wolinfo *wol)
2478 struct jme_adapter *jme = netdev_priv(netdev);
2480 wol->supported = WAKE_MAGIC | WAKE_PHY;
2484 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2485 wol->wolopts |= WAKE_PHY;
2487 if (jme->reg_pmcs & PMCS_MFEN)
2488 wol->wolopts |= WAKE_MAGIC;
2493 jme_set_wol(struct net_device *netdev,
2494 struct ethtool_wolinfo *wol)
2496 struct jme_adapter *jme = netdev_priv(netdev);
2498 if (wol->wolopts & (WAKE_MAGICSECURE |
2507 if (wol->wolopts & WAKE_PHY)
2508 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2510 if (wol->wolopts & WAKE_MAGIC)
2511 jme->reg_pmcs |= PMCS_MFEN;
2513 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2519 jme_get_settings(struct net_device *netdev,
2520 struct ethtool_cmd *ecmd)
2522 struct jme_adapter *jme = netdev_priv(netdev);
2525 spin_lock_bh(&jme->phy_lock);
2526 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2527 spin_unlock_bh(&jme->phy_lock);
2532 jme_set_settings(struct net_device *netdev,
2533 struct ethtool_cmd *ecmd)
2535 struct jme_adapter *jme = netdev_priv(netdev);
2538 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2542 * Check If user changed duplex only while force_media.
2543 * Hardware would not generate link change interrupt.
2545 if (jme->mii_if.force_media &&
2546 ecmd->autoneg != AUTONEG_ENABLE &&
2547 (jme->mii_if.full_duplex != ecmd->duplex))
2550 spin_lock_bh(&jme->phy_lock);
2551 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2552 spin_unlock_bh(&jme->phy_lock);
2556 jme_reset_link(jme);
2557 jme->old_ecmd = *ecmd;
2558 set_bit(JME_FLAG_SSET, &jme->flags);
2565 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2568 struct jme_adapter *jme = netdev_priv(netdev);
2569 struct mii_ioctl_data *mii_data = if_mii(rq);
2570 unsigned int duplex_chg;
2572 if (cmd == SIOCSMIIREG) {
2573 u16 val = mii_data->val_in;
2574 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2575 (val & BMCR_SPEED1000))
2579 spin_lock_bh(&jme->phy_lock);
2580 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2581 spin_unlock_bh(&jme->phy_lock);
2583 if (!rc && (cmd == SIOCSMIIREG)) {
2585 jme_reset_link(jme);
2586 jme_get_settings(netdev, &jme->old_ecmd);
2587 set_bit(JME_FLAG_SSET, &jme->flags);
2594 jme_get_link(struct net_device *netdev)
2596 struct jme_adapter *jme = netdev_priv(netdev);
2597 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2601 jme_get_msglevel(struct net_device *netdev)
2603 struct jme_adapter *jme = netdev_priv(netdev);
2604 return jme->msg_enable;
2608 jme_set_msglevel(struct net_device *netdev, u32 value)
2610 struct jme_adapter *jme = netdev_priv(netdev);
2611 jme->msg_enable = value;
2615 jme_get_rx_csum(struct net_device *netdev)
2617 struct jme_adapter *jme = netdev_priv(netdev);
2618 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2622 jme_set_rx_csum(struct net_device *netdev, u32 on)
2624 struct jme_adapter *jme = netdev_priv(netdev);
2626 spin_lock_bh(&jme->rxmcs_lock);
2628 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2630 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2631 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2632 spin_unlock_bh(&jme->rxmcs_lock);
2638 jme_set_tx_csum(struct net_device *netdev, u32 on)
2640 struct jme_adapter *jme = netdev_priv(netdev);
2643 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2644 if (netdev->mtu <= 1900)
2646 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2648 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2650 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2657 jme_set_tso(struct net_device *netdev, u32 on)
2659 struct jme_adapter *jme = netdev_priv(netdev);
2662 set_bit(JME_FLAG_TSO, &jme->flags);
2663 if (netdev->mtu <= 1900)
2664 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2666 clear_bit(JME_FLAG_TSO, &jme->flags);
2667 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2674 jme_nway_reset(struct net_device *netdev)
2676 struct jme_adapter *jme = netdev_priv(netdev);
2677 jme_restart_an(jme);
2682 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2687 val = jread32(jme, JME_SMBCSR);
2688 to = JME_SMB_BUSY_TIMEOUT;
2689 while ((val & SMBCSR_BUSY) && --to) {
2691 val = jread32(jme, JME_SMBCSR);
2694 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2698 jwrite32(jme, JME_SMBINTF,
2699 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2700 SMBINTF_HWRWN_READ |
2703 val = jread32(jme, JME_SMBINTF);
2704 to = JME_SMB_BUSY_TIMEOUT;
2705 while ((val & SMBINTF_HWCMD) && --to) {
2707 val = jread32(jme, JME_SMBINTF);
2710 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2714 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2718 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2723 val = jread32(jme, JME_SMBCSR);
2724 to = JME_SMB_BUSY_TIMEOUT;
2725 while ((val & SMBCSR_BUSY) && --to) {
2727 val = jread32(jme, JME_SMBCSR);
2730 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2734 jwrite32(jme, JME_SMBINTF,
2735 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2736 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2737 SMBINTF_HWRWN_WRITE |
2740 val = jread32(jme, JME_SMBINTF);
2741 to = JME_SMB_BUSY_TIMEOUT;
2742 while ((val & SMBINTF_HWCMD) && --to) {
2744 val = jread32(jme, JME_SMBINTF);
2747 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2755 jme_get_eeprom_len(struct net_device *netdev)
2757 struct jme_adapter *jme = netdev_priv(netdev);
2759 val = jread32(jme, JME_SMBCSR);
2760 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2764 jme_get_eeprom(struct net_device *netdev,
2765 struct ethtool_eeprom *eeprom, u8 *data)
2767 struct jme_adapter *jme = netdev_priv(netdev);
2768 int i, offset = eeprom->offset, len = eeprom->len;
2771 * ethtool will check the boundary for us
2773 eeprom->magic = JME_EEPROM_MAGIC;
2774 for (i = 0 ; i < len ; ++i)
2775 data[i] = jme_smb_read(jme, i + offset);
2781 jme_set_eeprom(struct net_device *netdev,
2782 struct ethtool_eeprom *eeprom, u8 *data)
2784 struct jme_adapter *jme = netdev_priv(netdev);
2785 int i, offset = eeprom->offset, len = eeprom->len;
2787 if (eeprom->magic != JME_EEPROM_MAGIC)
2791 * ethtool will check the boundary for us
2793 for (i = 0 ; i < len ; ++i)
2794 jme_smb_write(jme, i + offset, data[i]);
2799 static const struct ethtool_ops jme_ethtool_ops = {
2800 .get_drvinfo = jme_get_drvinfo,
2801 .get_regs_len = jme_get_regs_len,
2802 .get_regs = jme_get_regs,
2803 .get_coalesce = jme_get_coalesce,
2804 .set_coalesce = jme_set_coalesce,
2805 .get_pauseparam = jme_get_pauseparam,
2806 .set_pauseparam = jme_set_pauseparam,
2807 .get_wol = jme_get_wol,
2808 .set_wol = jme_set_wol,
2809 .get_settings = jme_get_settings,
2810 .set_settings = jme_set_settings,
2811 .get_link = jme_get_link,
2812 .get_msglevel = jme_get_msglevel,
2813 .set_msglevel = jme_set_msglevel,
2814 .get_rx_csum = jme_get_rx_csum,
2815 .set_rx_csum = jme_set_rx_csum,
2816 .set_tx_csum = jme_set_tx_csum,
2817 .set_tso = jme_set_tso,
2818 .set_sg = ethtool_op_set_sg,
2819 .nway_reset = jme_nway_reset,
2820 .get_eeprom_len = jme_get_eeprom_len,
2821 .get_eeprom = jme_get_eeprom,
2822 .set_eeprom = jme_set_eeprom,
2826 jme_pci_dma64(struct pci_dev *pdev)
2828 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2829 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2830 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2833 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2834 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2835 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2838 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2839 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2846 jme_phy_init(struct jme_adapter *jme)
2850 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2851 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2855 jme_check_hw_ver(struct jme_adapter *jme)
2859 chipmode = jread32(jme, JME_CHIPMODE);
2861 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2862 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2863 jme->chip_main_rev = jme->chiprev & 0xF;
2864 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2867 static const struct net_device_ops jme_netdev_ops = {
2868 .ndo_open = jme_open,
2869 .ndo_stop = jme_close,
2870 .ndo_validate_addr = eth_validate_addr,
2871 .ndo_do_ioctl = jme_ioctl,
2872 .ndo_start_xmit = jme_start_xmit,
2873 .ndo_set_mac_address = jme_set_macaddr,
2874 .ndo_set_multicast_list = jme_set_multi,
2875 .ndo_change_mtu = jme_change_mtu,
2876 .ndo_tx_timeout = jme_tx_timeout,
2877 .ndo_vlan_rx_register = jme_vlan_rx_register,
2880 static int __devinit
2881 jme_init_one(struct pci_dev *pdev,
2882 const struct pci_device_id *ent)
2884 int rc = 0, using_dac, i;
2885 struct net_device *netdev;
2886 struct jme_adapter *jme;
2891 * set up PCI device basics
2893 rc = pci_enable_device(pdev);
2895 pr_err("Cannot enable PCI device\n");
2899 using_dac = jme_pci_dma64(pdev);
2900 if (using_dac < 0) {
2901 pr_err("Cannot set PCI DMA Mask\n");
2903 goto err_out_disable_pdev;
2906 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2907 pr_err("No PCI resource region found\n");
2909 goto err_out_disable_pdev;
2912 rc = pci_request_regions(pdev, DRV_NAME);
2914 pr_err("Cannot obtain PCI resource region\n");
2915 goto err_out_disable_pdev;
2918 pci_set_master(pdev);
2921 * alloc and init net device
2923 netdev = alloc_etherdev(sizeof(*jme));
2925 pr_err("Cannot allocate netdev structure\n");
2927 goto err_out_release_regions;
2929 netdev->netdev_ops = &jme_netdev_ops;
2930 netdev->ethtool_ops = &jme_ethtool_ops;
2931 netdev->watchdog_timeo = TX_TIMEOUT;
2932 netdev->features = NETIF_F_IP_CSUM |
2937 NETIF_F_HW_VLAN_TX |
2940 netdev->features |= NETIF_F_HIGHDMA;
2942 SET_NETDEV_DEV(netdev, &pdev->dev);
2943 pci_set_drvdata(pdev, netdev);
2948 jme = netdev_priv(netdev);
2951 jme->jme_rx = netif_rx;
2952 jme->jme_vlan_rx = vlan_hwaccel_rx;
2953 jme->old_mtu = netdev->mtu = 1500;
2955 jme->tx_ring_size = 1 << 10;
2956 jme->tx_ring_mask = jme->tx_ring_size - 1;
2957 jme->tx_wake_threshold = 1 << 9;
2958 jme->rx_ring_size = 1 << 9;
2959 jme->rx_ring_mask = jme->rx_ring_size - 1;
2960 jme->msg_enable = JME_DEF_MSG_ENABLE;
2961 jme->regs = ioremap(pci_resource_start(pdev, 0),
2962 pci_resource_len(pdev, 0));
2964 pr_err("Mapping PCI resource region error\n");
2966 goto err_out_free_netdev;
2970 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2971 jwrite32(jme, JME_APMC, apmc);
2972 } else if (force_pseudohp) {
2973 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2974 jwrite32(jme, JME_APMC, apmc);
2977 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2979 spin_lock_init(&jme->phy_lock);
2980 spin_lock_init(&jme->macaddr_lock);
2981 spin_lock_init(&jme->rxmcs_lock);
2983 atomic_set(&jme->link_changing, 1);
2984 atomic_set(&jme->rx_cleaning, 1);
2985 atomic_set(&jme->tx_cleaning, 1);
2986 atomic_set(&jme->rx_empty, 1);
2988 tasklet_init(&jme->pcc_task,
2990 (unsigned long) jme);
2991 tasklet_init(&jme->linkch_task,
2992 jme_link_change_tasklet,
2993 (unsigned long) jme);
2994 tasklet_init(&jme->txclean_task,
2995 jme_tx_clean_tasklet,
2996 (unsigned long) jme);
2997 tasklet_init(&jme->rxclean_task,
2998 jme_rx_clean_tasklet,
2999 (unsigned long) jme);
3000 tasklet_init(&jme->rxempty_task,
3001 jme_rx_empty_tasklet,
3002 (unsigned long) jme);
3003 tasklet_disable_nosync(&jme->linkch_task);
3004 tasklet_disable_nosync(&jme->txclean_task);
3005 tasklet_disable_nosync(&jme->rxclean_task);
3006 tasklet_disable_nosync(&jme->rxempty_task);
3007 jme->dpi.cur = PCC_P1;
3010 jme->reg_rxcs = RXCS_DEFAULT;
3011 jme->reg_rxmcs = RXMCS_DEFAULT;
3013 jme->reg_pmcs = PMCS_MFEN;
3014 jme->reg_gpreg1 = GPREG1_DEFAULT;
3015 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3016 set_bit(JME_FLAG_TSO, &jme->flags);
3019 * Get Max Read Req Size from PCI Config Space
3021 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3022 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3023 switch (jme->mrrs) {
3025 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3028 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3031 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3036 * Must check before reset_mac_processor
3038 jme_check_hw_ver(jme);
3039 jme->mii_if.dev = netdev;
3041 jme->mii_if.phy_id = 0;
3042 for (i = 1 ; i < 32 ; ++i) {
3043 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3044 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3045 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3046 jme->mii_if.phy_id = i;
3051 if (!jme->mii_if.phy_id) {
3053 pr_err("Can not find phy_id\n");
3057 jme->reg_ghc |= GHC_LINK_POLL;
3059 jme->mii_if.phy_id = 1;
3061 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3062 jme->mii_if.supports_gmii = true;
3064 jme->mii_if.supports_gmii = false;
3065 jme->mii_if.phy_id_mask = 0x1F;
3066 jme->mii_if.reg_num_mask = 0x1F;
3067 jme->mii_if.mdio_read = jme_mdio_read;
3068 jme->mii_if.mdio_write = jme_mdio_write;
3071 jme_set_phyfifo_5level(jme);
3072 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3078 * Reset MAC processor and reload EEPROM for MAC Address
3080 jme_reset_mac_processor(jme);
3081 rc = jme_reload_eeprom(jme);
3083 pr_err("Reload eeprom for reading MAC Address error\n");
3086 jme_load_macaddr(netdev);
3089 * Tell stack that we are not ready to work until open()
3091 netif_carrier_off(netdev);
3093 rc = register_netdev(netdev);
3095 pr_err("Cannot register net device\n");
3099 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3100 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3101 "JMC250 Gigabit Ethernet" :
3102 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3103 "JMC260 Fast Ethernet" : "Unknown",
3104 (jme->fpgaver != 0) ? " (FPGA)" : "",
3105 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3106 jme->pcirev, netdev->dev_addr);
3112 err_out_free_netdev:
3113 pci_set_drvdata(pdev, NULL);
3114 free_netdev(netdev);
3115 err_out_release_regions:
3116 pci_release_regions(pdev);
3117 err_out_disable_pdev:
3118 pci_disable_device(pdev);
3123 static void __devexit
3124 jme_remove_one(struct pci_dev *pdev)
3126 struct net_device *netdev = pci_get_drvdata(pdev);
3127 struct jme_adapter *jme = netdev_priv(netdev);
3129 unregister_netdev(netdev);
3131 pci_set_drvdata(pdev, NULL);
3132 free_netdev(netdev);
3133 pci_release_regions(pdev);
3134 pci_disable_device(pdev);
3139 jme_shutdown(struct pci_dev *pdev)
3141 struct net_device *netdev = pci_get_drvdata(pdev);
3142 struct jme_adapter *jme = netdev_priv(netdev);
3144 jme_powersave_phy(jme);
3145 pci_pme_active(pdev, true);
3150 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3152 struct net_device *netdev = pci_get_drvdata(pdev);
3153 struct jme_adapter *jme = netdev_priv(netdev);
3155 atomic_dec(&jme->link_changing);
3157 netif_device_detach(netdev);
3158 netif_stop_queue(netdev);
3161 tasklet_disable(&jme->txclean_task);
3162 tasklet_disable(&jme->rxclean_task);
3163 tasklet_disable(&jme->rxempty_task);
3165 if (netif_carrier_ok(netdev)) {
3166 if (test_bit(JME_FLAG_POLL, &jme->flags))
3167 jme_polling_mode(jme);
3169 jme_stop_pcc_timer(jme);
3170 jme_disable_rx_engine(jme);
3171 jme_disable_tx_engine(jme);
3172 jme_reset_mac_processor(jme);
3173 jme_free_rx_resources(jme);
3174 jme_free_tx_resources(jme);
3175 netif_carrier_off(netdev);
3179 tasklet_enable(&jme->txclean_task);
3180 tasklet_hi_enable(&jme->rxclean_task);
3181 tasklet_hi_enable(&jme->rxempty_task);
3183 pci_save_state(pdev);
3184 jme_powersave_phy(jme);
3185 pci_enable_wake(jme->pdev, PCI_D3hot, true);
3186 pci_set_power_state(pdev, PCI_D3hot);
3192 jme_resume(struct pci_dev *pdev)
3194 struct net_device *netdev = pci_get_drvdata(pdev);
3195 struct jme_adapter *jme = netdev_priv(netdev);
3198 pci_restore_state(pdev);
3201 if (test_bit(JME_FLAG_SSET, &jme->flags))
3202 jme_set_settings(netdev, &jme->old_ecmd);
3204 jme_reset_phy_processor(jme);
3207 netif_device_attach(netdev);
3209 atomic_inc(&jme->link_changing);
3211 jme_reset_link(jme);
3217 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3218 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3219 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3223 static struct pci_driver jme_driver = {
3225 .id_table = jme_pci_tbl,
3226 .probe = jme_init_one,
3227 .remove = __devexit_p(jme_remove_one),
3229 .suspend = jme_suspend,
3230 .resume = jme_resume,
3231 #endif /* CONFIG_PM */
3232 .shutdown = jme_shutdown,
3236 jme_init_module(void)
3238 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3239 return pci_register_driver(&jme_driver);
3243 jme_cleanup_module(void)
3245 pci_unregister_driver(&jme_driver);
3248 module_init(jme_init_module);
3249 module_exit(jme_cleanup_module);
3251 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3252 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3253 MODULE_LICENSE("GPL");
3254 MODULE_VERSION(DRV_VERSION);
3255 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);