2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
63 jme_mdio_read(struct net_device *netdev, int phy, int reg)
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
93 jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
96 struct jme_adapter *jme = netdev_priv(netdev);
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
115 jme_reset_phy_processor(struct jme_adapter *jme)
119 jme_mdio_write(jme->dev,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
130 val = jme_mdio_read(jme->dev,
134 jme_mdio_write(jme->dev,
136 MII_BMCR, val | BMCR_RESET);
140 jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
150 jwrite32(jme, JME_WFODP, crc);
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
161 jwrite32(jme, JME_WFODP, mask[i]);
167 jme_mac_rxclk_off(struct jme_adapter *jme)
169 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
170 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
174 jme_mac_rxclk_on(struct jme_adapter *jme)
176 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
177 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
181 jme_mac_txclk_off(struct jme_adapter *jme)
183 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
184 jwrite32f(jme, JME_GHC, jme->reg_ghc);
188 jme_mac_txclk_on(struct jme_adapter *jme)
190 u32 speed = jme->reg_ghc & GHC_SPEED;
191 if (speed == GHC_SPEED_1000M)
192 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
194 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
195 jwrite32f(jme, JME_GHC, jme->reg_ghc);
199 jme_reset_ghc_speed(struct jme_adapter *jme)
201 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
206 jme_reset_250A2_workaround(struct jme_adapter *jme)
208 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
210 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
214 jme_assert_ghc_reset(struct jme_adapter *jme)
216 jme->reg_ghc |= GHC_SWRST;
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
221 jme_clear_ghc_reset(struct jme_adapter *jme)
223 jme->reg_ghc &= ~GHC_SWRST;
224 jwrite32f(jme, JME_GHC, jme->reg_ghc);
228 jme_reset_mac_processor(struct jme_adapter *jme)
230 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
231 u32 crc = 0xCDCDCDCD;
235 jme_reset_ghc_speed(jme);
236 jme_reset_250A2_workaround(jme);
238 jme_mac_rxclk_on(jme);
239 jme_mac_txclk_on(jme);
241 jme_assert_ghc_reset(jme);
243 jme_mac_rxclk_off(jme);
244 jme_mac_txclk_off(jme);
246 jme_clear_ghc_reset(jme);
248 jme_mac_rxclk_on(jme);
249 jme_mac_txclk_on(jme);
251 jme_mac_rxclk_off(jme);
252 jme_mac_txclk_off(jme);
254 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
255 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
256 jwrite32(jme, JME_RXQDC, 0x00000000);
257 jwrite32(jme, JME_RXNDA, 0x00000000);
258 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
259 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
260 jwrite32(jme, JME_TXQDC, 0x00000000);
261 jwrite32(jme, JME_TXNDA, 0x00000000);
263 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
264 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
265 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
266 jme_setup_wakeup_frame(jme, mask, crc, i);
268 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
270 gpreg0 = GPREG0_DEFAULT;
271 jwrite32(jme, JME_GPREG0, gpreg0);
275 jme_clear_pm(struct jme_adapter *jme)
277 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
278 pci_set_power_state(jme->pdev, PCI_D0);
279 pci_enable_wake(jme->pdev, PCI_D0, false);
283 jme_reload_eeprom(struct jme_adapter *jme)
288 val = jread32(jme, JME_SMBCSR);
290 if (val & SMBCSR_EEPROMD) {
292 jwrite32(jme, JME_SMBCSR, val);
293 val |= SMBCSR_RELOAD;
294 jwrite32(jme, JME_SMBCSR, val);
297 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
299 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
304 pr_err("eeprom reload timeout\n");
313 jme_load_macaddr(struct net_device *netdev)
315 struct jme_adapter *jme = netdev_priv(netdev);
316 unsigned char macaddr[6];
319 spin_lock_bh(&jme->macaddr_lock);
320 val = jread32(jme, JME_RXUMA_LO);
321 macaddr[0] = (val >> 0) & 0xFF;
322 macaddr[1] = (val >> 8) & 0xFF;
323 macaddr[2] = (val >> 16) & 0xFF;
324 macaddr[3] = (val >> 24) & 0xFF;
325 val = jread32(jme, JME_RXUMA_HI);
326 macaddr[4] = (val >> 0) & 0xFF;
327 macaddr[5] = (val >> 8) & 0xFF;
328 memcpy(netdev->dev_addr, macaddr, 6);
329 spin_unlock_bh(&jme->macaddr_lock);
333 jme_set_rx_pcc(struct jme_adapter *jme, int p)
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
352 jwrite32(jme, JME_PCCRX0,
353 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
354 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
361 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
362 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
366 jme_start_irq(struct jme_adapter *jme)
368 register struct dynpcc_info *dpi = &(jme->dpi);
370 jme_set_rx_pcc(jme, PCC_P1);
372 dpi->attempt = PCC_P1;
375 jwrite32(jme, JME_PCCTX,
376 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
377 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
384 jwrite32(jme, JME_IENS, INTR_ENABLE);
388 jme_stop_irq(struct jme_adapter *jme)
393 jwrite32f(jme, JME_IENC, INTR_ENABLE);
397 jme_linkstat_from_phy(struct jme_adapter *jme)
401 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
402 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
403 if (bmsr & BMSR_ANCOMP)
404 phylink |= PHY_LINK_AUTONEG_COMPLETE;
410 jme_set_phyfifo_5level(struct jme_adapter *jme)
412 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
416 jme_set_phyfifo_8level(struct jme_adapter *jme)
418 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
422 jme_check_link(struct net_device *netdev, int testonly)
424 struct jme_adapter *jme = netdev_priv(netdev);
425 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
432 phylink = jme_linkstat_from_phy(jme);
434 phylink = jread32(jme, JME_PHY_LINK);
436 if (phylink & PHY_LINK_UP) {
437 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
439 * If we did not enable AN
440 * Speed/Duplex Info should be obtained from SMI
442 phylink = PHY_LINK_UP;
444 bmcr = jme_mdio_read(jme->dev,
448 phylink |= ((bmcr & BMCR_SPEED1000) &&
449 (bmcr & BMCR_SPEED100) == 0) ?
450 PHY_LINK_SPEED_1000M :
451 (bmcr & BMCR_SPEED100) ?
452 PHY_LINK_SPEED_100M :
455 phylink |= (bmcr & BMCR_FULLDPLX) ?
458 strcat(linkmsg, "Forced: ");
461 * Keep polling for speed/duplex resolve complete
463 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
469 phylink = jme_linkstat_from_phy(jme);
471 phylink = jread32(jme, JME_PHY_LINK);
474 pr_err("Waiting speed resolve timeout\n");
476 strcat(linkmsg, "ANed: ");
479 if (jme->phylink == phylink) {
486 jme->phylink = phylink;
489 * The speed/duplex setting of jme->reg_ghc already cleared
490 * by jme_reset_mac_processor()
492 switch (phylink & PHY_LINK_SPEED_MASK) {
493 case PHY_LINK_SPEED_10M:
494 jme->reg_ghc |= GHC_SPEED_10M;
495 strcat(linkmsg, "10 Mbps, ");
497 case PHY_LINK_SPEED_100M:
498 jme->reg_ghc |= GHC_SPEED_100M;
499 strcat(linkmsg, "100 Mbps, ");
501 case PHY_LINK_SPEED_1000M:
502 jme->reg_ghc |= GHC_SPEED_1000M;
503 strcat(linkmsg, "1000 Mbps, ");
509 if (phylink & PHY_LINK_DUPLEX) {
510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
511 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
512 jme->reg_ghc |= GHC_DPX;
514 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
518 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
521 jwrite32(jme, JME_GHC, jme->reg_ghc);
523 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
524 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
526 if (!(phylink & PHY_LINK_DUPLEX))
527 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
528 switch (phylink & PHY_LINK_SPEED_MASK) {
529 case PHY_LINK_SPEED_10M:
530 jme_set_phyfifo_8level(jme);
531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
533 case PHY_LINK_SPEED_100M:
534 jme_set_phyfifo_5level(jme);
535 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
537 case PHY_LINK_SPEED_1000M:
538 jme_set_phyfifo_8level(jme);
544 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
546 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
549 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
552 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
553 netif_carrier_on(netdev);
558 netif_info(jme, link, jme->dev, "Link is down\n");
560 netif_carrier_off(netdev);
568 jme_setup_tx_resources(struct jme_adapter *jme)
570 struct jme_ring *txring = &(jme->txring[0]);
572 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
583 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
585 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, jme->tx_ring_size);
590 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
591 jme->tx_ring_size, GFP_ATOMIC);
592 if (unlikely(!(txring->bufinf)))
593 goto err_free_txring;
596 * Initialize Transmit Descriptors
598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
599 memset(txring->bufinf, 0,
600 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
612 txring->dmaalloc = 0;
614 txring->bufinf = NULL;
620 jme_free_tx_resources(struct jme_adapter *jme)
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
631 dev_kfree_skb(txbi->skb);
637 txbi->start_xmit = 0;
639 kfree(txring->bufinf);
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
647 txring->alloc = NULL;
649 txring->dmaalloc = 0;
651 txring->bufinf = NULL;
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
659 jme_enable_tx_engine(struct jme_adapter *jme)
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
668 * Setup TX Queue 0 DMA Bass Address
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
675 * Setup TX Descptor Count
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
688 * Start clock for TX MAC Processor
690 jme_mac_txclk_on(jme);
694 jme_restart_tx_engine(struct jme_adapter *jme)
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
705 jme_disable_tx_engine(struct jme_adapter *jme)
713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
716 val = jread32(jme, JME_TXCS);
717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
719 val = jread32(jme, JME_TXCS);
724 pr_err("Disable TX engine timeout\n");
727 * Stop clock for TX MAC Processor
729 jme_mac_txclk_off(jme);
733 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
735 struct jme_ring *rxring = &(jme->rxring[0]);
736 register struct rxdesc *rxdesc = rxring->desc;
737 struct jme_buffer_info *rxbi = rxring->bufinf;
743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
747 if (jme->dev->features & NETIF_F_HIGHDMA)
748 rxdesc->desc1.flags = RXFLAG_64BIT;
750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
754 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
756 struct jme_ring *rxring = &(jme->rxring[0]);
757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
760 skb = netdev_alloc_skb(jme->dev,
761 jme->dev->mtu + RX_EXTRA_LEN);
764 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
769 rxbi->len = skb_tailroom(skb);
770 rxbi->mapping = pci_map_page(jme->pdev,
771 virt_to_page(skb->data),
772 offset_in_page(skb->data),
780 jme_free_rx_buf(struct jme_adapter *jme, int i)
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
787 pci_unmap_page(jme->pdev,
791 dev_kfree_skb(rxbi->skb);
799 jme_free_rx_resources(struct jme_adapter *jme)
802 struct jme_ring *rxring = &(jme->rxring[0]);
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
811 dma_free_coherent(&(jme->pdev->dev),
812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
815 rxring->alloc = NULL;
817 rxring->dmaalloc = 0;
819 rxring->bufinf = NULL;
821 rxring->next_to_use = 0;
822 atomic_set(&rxring->next_to_clean, 0);
826 jme_setup_rx_resources(struct jme_adapter *jme)
829 struct jme_ring *rxring = &(jme->rxring[0]);
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
844 rxring->next_to_use = 0;
845 atomic_set(&rxring->next_to_clean, 0);
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
853 * Initiallize Receive Descriptors
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
859 jme_free_rx_resources(jme);
863 jme_set_clean_rxdesc(jme, i);
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
875 rxring->dmaalloc = 0;
877 rxring->bufinf = NULL;
883 jme_enable_rx_engine(struct jme_adapter *jme)
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
893 * Setup RX DMA Bass Address
895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
900 * Setup RX Descriptor Count
902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
905 * Setup Unicast Filter
907 jme_set_unicastaddr(jme->dev);
908 jme_set_multi(jme->dev);
914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
920 * Start clock for RX MAC Processor
922 jme_mac_rxclk_on(jme);
926 jme_restart_rx_engine(struct jme_adapter *jme)
931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
938 jme_disable_rx_engine(struct jme_adapter *jme)
946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
949 val = jread32(jme, JME_RXCS);
950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
952 val = jread32(jme, JME_RXCS);
957 pr_err("Disable RX engine timeout\n");
960 * Stop clock for RX MAC Processor
962 jme_mac_rxclk_off(jme);
966 jme_udpsum(struct sk_buff *skb)
970 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
972 if (skb->protocol != htons(ETH_P_IP))
974 skb_set_network_header(skb, ETH_HLEN);
975 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
976 (skb->len < (ETH_HLEN +
977 (ip_hdr(skb)->ihl << 2) +
978 sizeof(struct udphdr)))) {
979 skb_reset_network_header(skb);
982 skb_set_transport_header(skb,
983 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
984 csum = udp_hdr(skb)->check;
985 skb_reset_transport_header(skb);
986 skb_reset_network_header(skb);
992 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
994 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
997 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
998 == RXWBFLAG_TCPON)) {
999 if (flags & RXWBFLAG_IPV4)
1000 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1004 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1005 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1006 if (flags & RXWBFLAG_IPV4)
1007 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1011 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1012 == RXWBFLAG_IPV4)) {
1013 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1021 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1023 struct jme_ring *rxring = &(jme->rxring[0]);
1024 struct rxdesc *rxdesc = rxring->desc;
1025 struct jme_buffer_info *rxbi = rxring->bufinf;
1026 struct sk_buff *skb;
1033 pci_dma_sync_single_for_cpu(jme->pdev,
1036 PCI_DMA_FROMDEVICE);
1038 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1039 pci_dma_sync_single_for_device(jme->pdev,
1042 PCI_DMA_FROMDEVICE);
1044 ++(NET_STAT(jme).rx_dropped);
1046 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1049 skb_reserve(skb, RX_PREPAD_SIZE);
1050 skb_put(skb, framesize);
1051 skb->protocol = eth_type_trans(skb, jme->dev);
1053 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1054 skb->ip_summed = CHECKSUM_UNNECESSARY;
1056 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1057 skb->ip_summed = CHECKSUM_NONE;
1059 skb_checksum_none_assert(skb);
1062 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1064 jme->jme_vlan_rx(skb, jme->vlgrp,
1065 le16_to_cpu(rxdesc->descwb.vlan));
1066 NET_STAT(jme).rx_bytes += 4;
1074 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1075 cpu_to_le16(RXWBFLAG_DEST_MUL))
1076 ++(NET_STAT(jme).multicast);
1078 NET_STAT(jme).rx_bytes += framesize;
1079 ++(NET_STAT(jme).rx_packets);
1082 jme_set_clean_rxdesc(jme, idx);
1087 jme_process_receive(struct jme_adapter *jme, int limit)
1089 struct jme_ring *rxring = &(jme->rxring[0]);
1090 struct rxdesc *rxdesc = rxring->desc;
1091 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1093 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1096 if (unlikely(atomic_read(&jme->link_changing) != 1))
1099 if (unlikely(!netif_carrier_ok(jme->dev)))
1102 i = atomic_read(&rxring->next_to_clean);
1104 rxdesc = rxring->desc;
1107 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1108 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1113 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1115 if (unlikely(desccnt > 1 ||
1116 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1118 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1119 ++(NET_STAT(jme).rx_crc_errors);
1120 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1121 ++(NET_STAT(jme).rx_fifo_errors);
1123 ++(NET_STAT(jme).rx_errors);
1126 limit -= desccnt - 1;
1128 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1129 jme_set_clean_rxdesc(jme, j);
1130 j = (j + 1) & (mask);
1134 jme_alloc_and_feed_skb(jme, i);
1137 i = (i + desccnt) & (mask);
1141 atomic_set(&rxring->next_to_clean, i);
1144 atomic_inc(&jme->rx_cleaning);
1146 return limit > 0 ? limit : 0;
1151 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1153 if (likely(atmp == dpi->cur)) {
1158 if (dpi->attempt == atmp) {
1161 dpi->attempt = atmp;
1168 jme_dynamic_pcc(struct jme_adapter *jme)
1170 register struct dynpcc_info *dpi = &(jme->dpi);
1172 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1173 jme_attempt_pcc(dpi, PCC_P3);
1174 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1175 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1176 jme_attempt_pcc(dpi, PCC_P2);
1178 jme_attempt_pcc(dpi, PCC_P1);
1180 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1181 if (dpi->attempt < dpi->cur)
1182 tasklet_schedule(&jme->rxclean_task);
1183 jme_set_rx_pcc(jme, dpi->attempt);
1184 dpi->cur = dpi->attempt;
1190 jme_start_pcc_timer(struct jme_adapter *jme)
1192 struct dynpcc_info *dpi = &(jme->dpi);
1193 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1194 dpi->last_pkts = NET_STAT(jme).rx_packets;
1196 jwrite32(jme, JME_TMCSR,
1197 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1201 jme_stop_pcc_timer(struct jme_adapter *jme)
1203 jwrite32(jme, JME_TMCSR, 0);
1207 jme_shutdown_nic(struct jme_adapter *jme)
1211 phylink = jme_linkstat_from_phy(jme);
1213 if (!(phylink & PHY_LINK_UP)) {
1215 * Disable all interrupt before issue timer
1218 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1223 jme_pcc_tasklet(unsigned long arg)
1225 struct jme_adapter *jme = (struct jme_adapter *)arg;
1226 struct net_device *netdev = jme->dev;
1228 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1229 jme_shutdown_nic(jme);
1233 if (unlikely(!netif_carrier_ok(netdev) ||
1234 (atomic_read(&jme->link_changing) != 1)
1236 jme_stop_pcc_timer(jme);
1240 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1241 jme_dynamic_pcc(jme);
1243 jme_start_pcc_timer(jme);
1247 jme_polling_mode(struct jme_adapter *jme)
1249 jme_set_rx_pcc(jme, PCC_OFF);
1253 jme_interrupt_mode(struct jme_adapter *jme)
1255 jme_set_rx_pcc(jme, PCC_P1);
1259 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1262 apmc = jread32(jme, JME_APMC);
1263 return apmc & JME_APMC_PSEUDO_HP_EN;
1267 jme_start_shutdown_timer(struct jme_adapter *jme)
1271 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1272 apmc &= ~JME_APMC_EPIEN_CTRL;
1274 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1277 jwrite32f(jme, JME_APMC, apmc);
1279 jwrite32f(jme, JME_TIMER2, 0);
1280 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1281 jwrite32(jme, JME_TMCSR,
1282 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1286 jme_stop_shutdown_timer(struct jme_adapter *jme)
1290 jwrite32f(jme, JME_TMCSR, 0);
1291 jwrite32f(jme, JME_TIMER2, 0);
1292 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1294 apmc = jread32(jme, JME_APMC);
1295 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1296 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1298 jwrite32f(jme, JME_APMC, apmc);
1302 jme_link_change_tasklet(unsigned long arg)
1304 struct jme_adapter *jme = (struct jme_adapter *)arg;
1305 struct net_device *netdev = jme->dev;
1308 while (!atomic_dec_and_test(&jme->link_changing)) {
1309 atomic_inc(&jme->link_changing);
1310 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1311 while (atomic_read(&jme->link_changing) != 1)
1312 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1315 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1318 jme->old_mtu = netdev->mtu;
1319 netif_stop_queue(netdev);
1320 if (jme_pseudo_hotplug_enabled(jme))
1321 jme_stop_shutdown_timer(jme);
1323 jme_stop_pcc_timer(jme);
1324 tasklet_disable(&jme->txclean_task);
1325 tasklet_disable(&jme->rxclean_task);
1326 tasklet_disable(&jme->rxempty_task);
1328 if (netif_carrier_ok(netdev)) {
1329 jme_disable_rx_engine(jme);
1330 jme_disable_tx_engine(jme);
1331 jme_reset_mac_processor(jme);
1332 jme_free_rx_resources(jme);
1333 jme_free_tx_resources(jme);
1335 if (test_bit(JME_FLAG_POLL, &jme->flags))
1336 jme_polling_mode(jme);
1338 netif_carrier_off(netdev);
1341 jme_check_link(netdev, 0);
1342 if (netif_carrier_ok(netdev)) {
1343 rc = jme_setup_rx_resources(jme);
1345 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1346 goto out_enable_tasklet;
1349 rc = jme_setup_tx_resources(jme);
1351 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1352 goto err_out_free_rx_resources;
1355 jme_enable_rx_engine(jme);
1356 jme_enable_tx_engine(jme);
1358 netif_start_queue(netdev);
1360 if (test_bit(JME_FLAG_POLL, &jme->flags))
1361 jme_interrupt_mode(jme);
1363 jme_start_pcc_timer(jme);
1364 } else if (jme_pseudo_hotplug_enabled(jme)) {
1365 jme_start_shutdown_timer(jme);
1368 goto out_enable_tasklet;
1370 err_out_free_rx_resources:
1371 jme_free_rx_resources(jme);
1373 tasklet_enable(&jme->txclean_task);
1374 tasklet_hi_enable(&jme->rxclean_task);
1375 tasklet_hi_enable(&jme->rxempty_task);
1377 atomic_inc(&jme->link_changing);
1381 jme_rx_clean_tasklet(unsigned long arg)
1383 struct jme_adapter *jme = (struct jme_adapter *)arg;
1384 struct dynpcc_info *dpi = &(jme->dpi);
1386 jme_process_receive(jme, jme->rx_ring_size);
1392 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1394 struct jme_adapter *jme = jme_napi_priv(holder);
1398 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1400 while (atomic_read(&jme->rx_empty) > 0) {
1401 atomic_dec(&jme->rx_empty);
1402 ++(NET_STAT(jme).rx_dropped);
1403 jme_restart_rx_engine(jme);
1405 atomic_inc(&jme->rx_empty);
1408 JME_RX_COMPLETE(netdev, holder);
1409 jme_interrupt_mode(jme);
1412 JME_NAPI_WEIGHT_SET(budget, rest);
1413 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1417 jme_rx_empty_tasklet(unsigned long arg)
1419 struct jme_adapter *jme = (struct jme_adapter *)arg;
1421 if (unlikely(atomic_read(&jme->link_changing) != 1))
1424 if (unlikely(!netif_carrier_ok(jme->dev)))
1427 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1429 jme_rx_clean_tasklet(arg);
1431 while (atomic_read(&jme->rx_empty) > 0) {
1432 atomic_dec(&jme->rx_empty);
1433 ++(NET_STAT(jme).rx_dropped);
1434 jme_restart_rx_engine(jme);
1436 atomic_inc(&jme->rx_empty);
1440 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1442 struct jme_ring *txring = &(jme->txring[0]);
1445 if (unlikely(netif_queue_stopped(jme->dev) &&
1446 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1447 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1448 netif_wake_queue(jme->dev);
1454 jme_tx_clean_tasklet(unsigned long arg)
1456 struct jme_adapter *jme = (struct jme_adapter *)arg;
1457 struct jme_ring *txring = &(jme->txring[0]);
1458 struct txdesc *txdesc = txring->desc;
1459 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1460 int i, j, cnt = 0, max, err, mask;
1462 tx_dbg(jme, "Into txclean\n");
1464 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1467 if (unlikely(atomic_read(&jme->link_changing) != 1))
1470 if (unlikely(!netif_carrier_ok(jme->dev)))
1473 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1474 mask = jme->tx_ring_mask;
1476 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1480 if (likely(ctxbi->skb &&
1481 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1483 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1484 i, ctxbi->nr_desc, jiffies);
1486 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1488 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1489 ttxbi = txbi + ((i + j) & (mask));
1490 txdesc[(i + j) & (mask)].dw[0] = 0;
1492 pci_unmap_page(jme->pdev,
1501 dev_kfree_skb(ctxbi->skb);
1503 cnt += ctxbi->nr_desc;
1505 if (unlikely(err)) {
1506 ++(NET_STAT(jme).tx_carrier_errors);
1508 ++(NET_STAT(jme).tx_packets);
1509 NET_STAT(jme).tx_bytes += ctxbi->len;
1514 ctxbi->start_xmit = 0;
1520 i = (i + ctxbi->nr_desc) & mask;
1525 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1526 atomic_set(&txring->next_to_clean, i);
1527 atomic_add(cnt, &txring->nr_free);
1529 jme_wake_queue_if_stopped(jme);
1532 atomic_inc(&jme->tx_cleaning);
1536 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1541 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1543 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1545 * Link change event is critical
1546 * all other events are ignored
1548 jwrite32(jme, JME_IEVE, intrstat);
1549 tasklet_schedule(&jme->linkch_task);
1553 if (intrstat & INTR_TMINTR) {
1554 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1555 tasklet_schedule(&jme->pcc_task);
1558 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1559 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1560 tasklet_schedule(&jme->txclean_task);
1563 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1564 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1570 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1571 if (intrstat & INTR_RX0EMP)
1572 atomic_inc(&jme->rx_empty);
1574 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1575 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1576 jme_polling_mode(jme);
1577 JME_RX_SCHEDULE(jme);
1581 if (intrstat & INTR_RX0EMP) {
1582 atomic_inc(&jme->rx_empty);
1583 tasklet_hi_schedule(&jme->rxempty_task);
1584 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1585 tasklet_hi_schedule(&jme->rxclean_task);
1591 * Re-enable interrupt
1593 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1596 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1598 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1601 jme_intr(int irq, void *dev_id)
1604 struct net_device *netdev = dev_id;
1605 struct jme_adapter *jme = netdev_priv(netdev);
1608 intrstat = jread32(jme, JME_IEVE);
1611 * Check if it's really an interrupt for us
1613 if (unlikely((intrstat & INTR_ENABLE) == 0))
1617 * Check if the device still exist
1619 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1622 jme_intr_msi(jme, intrstat);
1627 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1629 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1632 jme_msi(int irq, void *dev_id)
1635 struct net_device *netdev = dev_id;
1636 struct jme_adapter *jme = netdev_priv(netdev);
1639 intrstat = jread32(jme, JME_IEVE);
1641 jme_intr_msi(jme, intrstat);
1647 jme_reset_link(struct jme_adapter *jme)
1649 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1653 jme_restart_an(struct jme_adapter *jme)
1657 spin_lock_bh(&jme->phy_lock);
1658 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1659 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1660 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1661 spin_unlock_bh(&jme->phy_lock);
1665 jme_request_irq(struct jme_adapter *jme)
1668 struct net_device *netdev = jme->dev;
1669 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1670 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1671 int irq_flags = SA_SHIRQ;
1673 irq_handler_t handler = jme_intr;
1674 int irq_flags = IRQF_SHARED;
1677 if (!pci_enable_msi(jme->pdev)) {
1678 set_bit(JME_FLAG_MSI, &jme->flags);
1683 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1687 "Unable to request %s interrupt (return: %d)\n",
1688 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1691 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1692 pci_disable_msi(jme->pdev);
1693 clear_bit(JME_FLAG_MSI, &jme->flags);
1696 netdev->irq = jme->pdev->irq;
1703 jme_free_irq(struct jme_adapter *jme)
1705 free_irq(jme->pdev->irq, jme->dev);
1706 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1707 pci_disable_msi(jme->pdev);
1708 clear_bit(JME_FLAG_MSI, &jme->flags);
1709 jme->dev->irq = jme->pdev->irq;
1714 jme_new_phy_on(struct jme_adapter *jme)
1718 reg = jread32(jme, JME_PHY_PWR);
1719 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1720 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1721 jwrite32(jme, JME_PHY_PWR, reg);
1723 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1724 reg &= ~PE1_GPREG0_PBG;
1725 reg |= PE1_GPREG0_ENBG;
1726 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1730 jme_new_phy_off(struct jme_adapter *jme)
1734 reg = jread32(jme, JME_PHY_PWR);
1735 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1736 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1737 jwrite32(jme, JME_PHY_PWR, reg);
1739 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1740 reg &= ~PE1_GPREG0_PBG;
1741 reg |= PE1_GPREG0_PDD3COLD;
1742 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1746 jme_phy_on(struct jme_adapter *jme)
1750 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1751 bmcr &= ~BMCR_PDOWN;
1752 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1754 if (new_phy_power_ctrl(jme->chip_main_rev))
1755 jme_new_phy_on(jme);
1759 jme_phy_off(struct jme_adapter *jme)
1763 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1765 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1767 if (new_phy_power_ctrl(jme->chip_main_rev))
1768 jme_new_phy_off(jme);
1772 jme_open(struct net_device *netdev)
1774 struct jme_adapter *jme = netdev_priv(netdev);
1778 JME_NAPI_ENABLE(jme);
1780 tasklet_enable(&jme->linkch_task);
1781 tasklet_enable(&jme->txclean_task);
1782 tasklet_hi_enable(&jme->rxclean_task);
1783 tasklet_hi_enable(&jme->rxempty_task);
1785 rc = jme_request_irq(jme);
1792 if (test_bit(JME_FLAG_SSET, &jme->flags))
1793 jme_set_settings(netdev, &jme->old_ecmd);
1795 jme_reset_phy_processor(jme);
1797 jme_reset_link(jme);
1802 netif_stop_queue(netdev);
1803 netif_carrier_off(netdev);
1808 jme_set_100m_half(struct jme_adapter *jme)
1813 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1814 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1815 BMCR_SPEED1000 | BMCR_FULLDPLX);
1816 tmp |= BMCR_SPEED100;
1819 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1822 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1824 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1827 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1829 jme_wait_link(struct jme_adapter *jme)
1831 u32 phylink, to = JME_WAIT_LINK_TIME;
1834 phylink = jme_linkstat_from_phy(jme);
1835 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1837 phylink = jme_linkstat_from_phy(jme);
1842 jme_powersave_phy(struct jme_adapter *jme)
1844 if (jme->reg_pmcs) {
1845 jme_set_100m_half(jme);
1847 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1850 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1857 jme_close(struct net_device *netdev)
1859 struct jme_adapter *jme = netdev_priv(netdev);
1861 netif_stop_queue(netdev);
1862 netif_carrier_off(netdev);
1867 JME_NAPI_DISABLE(jme);
1869 tasklet_disable(&jme->linkch_task);
1870 tasklet_disable(&jme->txclean_task);
1871 tasklet_disable(&jme->rxclean_task);
1872 tasklet_disable(&jme->rxempty_task);
1874 jme_disable_rx_engine(jme);
1875 jme_disable_tx_engine(jme);
1876 jme_reset_mac_processor(jme);
1877 jme_free_rx_resources(jme);
1878 jme_free_tx_resources(jme);
1886 jme_alloc_txdesc(struct jme_adapter *jme,
1887 struct sk_buff *skb)
1889 struct jme_ring *txring = &(jme->txring[0]);
1890 int idx, nr_alloc, mask = jme->tx_ring_mask;
1892 idx = txring->next_to_use;
1893 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1895 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1898 atomic_sub(nr_alloc, &txring->nr_free);
1900 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1906 jme_fill_tx_map(struct pci_dev *pdev,
1907 struct txdesc *txdesc,
1908 struct jme_buffer_info *txbi,
1916 dmaaddr = pci_map_page(pdev,
1922 pci_dma_sync_single_for_device(pdev,
1929 txdesc->desc2.flags = TXFLAG_OWN;
1930 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1931 txdesc->desc2.datalen = cpu_to_le16(len);
1932 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1933 txdesc->desc2.bufaddrl = cpu_to_le32(
1934 (__u64)dmaaddr & 0xFFFFFFFFUL);
1936 txbi->mapping = dmaaddr;
1941 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1943 struct jme_ring *txring = &(jme->txring[0]);
1944 struct txdesc *txdesc = txring->desc, *ctxdesc;
1945 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1946 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1947 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1948 int mask = jme->tx_ring_mask;
1949 struct skb_frag_struct *frag;
1952 for (i = 0 ; i < nr_frags ; ++i) {
1953 frag = &skb_shinfo(skb)->frags[i];
1954 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1955 ctxbi = txbi + ((idx + i + 2) & (mask));
1957 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1958 frag->page_offset, frag->size, hidma);
1961 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1962 ctxdesc = txdesc + ((idx + 1) & (mask));
1963 ctxbi = txbi + ((idx + 1) & (mask));
1964 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1965 offset_in_page(skb->data), len, hidma);
1970 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1973 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1974 skb_shinfo(skb)->tso_size
1976 skb_shinfo(skb)->gso_size
1978 && skb_header_cloned(skb) &&
1979 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1988 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1990 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1991 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1993 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1996 *flags |= TXFLAG_LSEN;
1998 if (skb->protocol == htons(ETH_P_IP)) {
1999 struct iphdr *iph = ip_hdr(skb);
2002 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2007 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2009 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2022 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2024 #ifdef CHECKSUM_PARTIAL
2025 if (skb->ip_summed == CHECKSUM_PARTIAL)
2027 if (skb->ip_summed == CHECKSUM_HW)
2032 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2033 if (skb->protocol == htons(ETH_P_IP))
2034 ip_proto = ip_hdr(skb)->protocol;
2035 else if (skb->protocol == htons(ETH_P_IPV6))
2036 ip_proto = ipv6_hdr(skb)->nexthdr;
2040 switch (skb->protocol) {
2041 case htons(ETH_P_IP):
2042 ip_proto = ip_hdr(skb)->protocol;
2044 case htons(ETH_P_IPV6):
2045 ip_proto = ipv6_hdr(skb)->nexthdr;
2055 *flags |= TXFLAG_TCPCS;
2058 *flags |= TXFLAG_UDPCS;
2061 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2068 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2070 if (vlan_tx_tag_present(skb)) {
2071 *flags |= TXFLAG_TAGON;
2072 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2077 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2079 struct jme_ring *txring = &(jme->txring[0]);
2080 struct txdesc *txdesc;
2081 struct jme_buffer_info *txbi;
2084 txdesc = (struct txdesc *)txring->desc + idx;
2085 txbi = txring->bufinf + idx;
2091 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2093 * Set OWN bit at final.
2094 * When kernel transmit faster than NIC.
2095 * And NIC trying to send this descriptor before we tell
2096 * it to start sending this TX queue.
2097 * Other fields are already filled correctly.
2100 flags = TXFLAG_OWN | TXFLAG_INT;
2102 * Set checksum flags while not tso
2104 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2105 jme_tx_csum(jme, skb, &flags);
2106 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2107 jme_map_tx_skb(jme, skb, idx);
2108 txdesc->desc1.flags = flags;
2110 * Set tx buffer info after telling NIC to send
2111 * For better tx_clean timing
2114 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2116 txbi->len = skb->len;
2117 txbi->start_xmit = jiffies;
2118 if (!txbi->start_xmit)
2119 txbi->start_xmit = (0UL-1);
2125 jme_stop_queue_if_full(struct jme_adapter *jme)
2127 struct jme_ring *txring = &(jme->txring[0]);
2128 struct jme_buffer_info *txbi = txring->bufinf;
2129 int idx = atomic_read(&txring->next_to_clean);
2134 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2135 netif_stop_queue(jme->dev);
2136 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2138 if (atomic_read(&txring->nr_free)
2139 >= (jme->tx_wake_threshold)) {
2140 netif_wake_queue(jme->dev);
2141 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2145 if (unlikely(txbi->start_xmit &&
2146 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2148 netif_stop_queue(jme->dev);
2149 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2154 * This function is already protected by netif_tx_lock()
2157 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2162 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2164 struct jme_adapter *jme = netdev_priv(netdev);
2167 if (unlikely(jme_expand_header(jme, skb))) {
2168 ++(NET_STAT(jme).tx_dropped);
2169 return NETDEV_TX_OK;
2172 idx = jme_alloc_txdesc(jme, skb);
2174 if (unlikely(idx < 0)) {
2175 netif_stop_queue(netdev);
2176 netif_err(jme, tx_err, jme->dev,
2177 "BUG! Tx ring full when queue awake!\n");
2179 return NETDEV_TX_BUSY;
2182 jme_fill_tx_desc(jme, skb, idx);
2184 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2185 TXCS_SELECT_QUEUE0 |
2188 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2189 netdev->trans_start = jiffies;
2192 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2193 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2194 jme_stop_queue_if_full(jme);
2196 return NETDEV_TX_OK;
2200 jme_set_unicastaddr(struct net_device *netdev)
2202 struct jme_adapter *jme = netdev_priv(netdev);
2205 val = (netdev->dev_addr[3] & 0xff) << 24 |
2206 (netdev->dev_addr[2] & 0xff) << 16 |
2207 (netdev->dev_addr[1] & 0xff) << 8 |
2208 (netdev->dev_addr[0] & 0xff);
2209 jwrite32(jme, JME_RXUMA_LO, val);
2210 val = (netdev->dev_addr[5] & 0xff) << 8 |
2211 (netdev->dev_addr[4] & 0xff);
2212 jwrite32(jme, JME_RXUMA_HI, val);
2216 jme_set_macaddr(struct net_device *netdev, void *p)
2218 struct jme_adapter *jme = netdev_priv(netdev);
2219 struct sockaddr *addr = p;
2221 if (netif_running(netdev))
2224 spin_lock_bh(&jme->macaddr_lock);
2225 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2226 jme_set_unicastaddr(netdev);
2227 spin_unlock_bh(&jme->macaddr_lock);
2233 jme_set_multi(struct net_device *netdev)
2235 struct jme_adapter *jme = netdev_priv(netdev);
2236 u32 mc_hash[2] = {};
2237 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2241 spin_lock_bh(&jme->rxmcs_lock);
2243 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2245 if (netdev->flags & IFF_PROMISC) {
2246 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2247 } else if (netdev->flags & IFF_ALLMULTI) {
2248 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2249 } else if (netdev->flags & IFF_MULTICAST) {
2250 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2251 struct dev_mc_list *mclist;
2253 struct netdev_hw_addr *ha;
2257 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2258 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2259 for (i = 0, mclist = netdev->mc_list;
2260 mclist && i < netdev->mc_count;
2261 ++i, mclist = mclist->next) {
2262 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2263 netdev_for_each_mc_addr(mclist, netdev) {
2265 netdev_for_each_mc_addr(ha, netdev) {
2267 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2268 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2270 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2272 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2275 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2276 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2280 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2282 spin_unlock_bh(&jme->rxmcs_lock);
2286 jme_change_mtu(struct net_device *netdev, int new_mtu)
2288 struct jme_adapter *jme = netdev_priv(netdev);
2290 if (new_mtu == jme->old_mtu)
2293 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2294 ((new_mtu) < IPV6_MIN_MTU))
2297 if (new_mtu > 4000) {
2298 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2299 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2300 jme_restart_rx_engine(jme);
2302 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2303 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2304 jme_restart_rx_engine(jme);
2307 if (new_mtu > 1900) {
2308 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2309 NETIF_F_TSO | NETIF_F_TSO6);
2311 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2312 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2313 if (test_bit(JME_FLAG_TSO, &jme->flags))
2314 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2317 netdev->mtu = new_mtu;
2318 jme_reset_link(jme);
2324 jme_tx_timeout(struct net_device *netdev)
2326 struct jme_adapter *jme = netdev_priv(netdev);
2329 jme_reset_phy_processor(jme);
2330 if (test_bit(JME_FLAG_SSET, &jme->flags))
2331 jme_set_settings(netdev, &jme->old_ecmd);
2334 * Force to Reset the link again
2336 jme_reset_link(jme);
2339 static inline void jme_pause_rx(struct jme_adapter *jme)
2341 atomic_dec(&jme->link_changing);
2343 jme_set_rx_pcc(jme, PCC_OFF);
2344 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2345 JME_NAPI_DISABLE(jme);
2347 tasklet_disable(&jme->rxclean_task);
2348 tasklet_disable(&jme->rxempty_task);
2352 static inline void jme_resume_rx(struct jme_adapter *jme)
2354 struct dynpcc_info *dpi = &(jme->dpi);
2356 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2357 JME_NAPI_ENABLE(jme);
2359 tasklet_hi_enable(&jme->rxclean_task);
2360 tasklet_hi_enable(&jme->rxempty_task);
2363 dpi->attempt = PCC_P1;
2365 jme_set_rx_pcc(jme, PCC_P1);
2367 atomic_inc(&jme->link_changing);
2371 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2373 struct jme_adapter *jme = netdev_priv(netdev);
2380 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2382 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2384 struct jme_adapter *jme = netdev_priv(netdev);
2388 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2389 jme->vlgrp->vlan_devices[vid] = NULL;
2391 vlan_group_set_device(jme->vlgrp, vid, NULL);
2399 jme_get_drvinfo(struct net_device *netdev,
2400 struct ethtool_drvinfo *info)
2402 struct jme_adapter *jme = netdev_priv(netdev);
2404 strcpy(info->driver, DRV_NAME);
2405 strcpy(info->version, DRV_VERSION);
2406 strcpy(info->bus_info, pci_name(jme->pdev));
2410 jme_get_regs_len(struct net_device *netdev)
2416 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2420 for (i = 0 ; i < len ; i += 4)
2421 p[i >> 2] = jread32(jme, reg + i);
2425 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2428 u16 *p16 = (u16 *)p;
2430 for (i = 0 ; i < reg_nr ; ++i)
2431 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2435 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2437 struct jme_adapter *jme = netdev_priv(netdev);
2438 u32 *p32 = (u32 *)p;
2440 memset(p, 0xFF, JME_REG_LEN);
2443 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2446 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2449 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2452 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2455 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2459 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2461 struct jme_adapter *jme = netdev_priv(netdev);
2463 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2464 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2466 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2467 ecmd->use_adaptive_rx_coalesce = false;
2468 ecmd->rx_coalesce_usecs = 0;
2469 ecmd->rx_max_coalesced_frames = 0;
2473 ecmd->use_adaptive_rx_coalesce = true;
2475 switch (jme->dpi.cur) {
2477 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2478 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2481 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2482 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2485 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2486 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2496 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499 struct dynpcc_info *dpi = &(jme->dpi);
2501 if (netif_running(netdev))
2504 if (ecmd->use_adaptive_rx_coalesce &&
2505 test_bit(JME_FLAG_POLL, &jme->flags)) {
2506 clear_bit(JME_FLAG_POLL, &jme->flags);
2507 jme->jme_rx = netif_rx;
2508 jme->jme_vlan_rx = vlan_hwaccel_rx;
2510 dpi->attempt = PCC_P1;
2512 jme_set_rx_pcc(jme, PCC_P1);
2513 jme_interrupt_mode(jme);
2514 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2515 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2516 set_bit(JME_FLAG_POLL, &jme->flags);
2517 jme->jme_rx = netif_receive_skb;
2518 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2519 jme_interrupt_mode(jme);
2526 jme_get_pauseparam(struct net_device *netdev,
2527 struct ethtool_pauseparam *ecmd)
2529 struct jme_adapter *jme = netdev_priv(netdev);
2532 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2533 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2535 spin_lock_bh(&jme->phy_lock);
2536 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2537 spin_unlock_bh(&jme->phy_lock);
2540 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2544 jme_set_pauseparam(struct net_device *netdev,
2545 struct ethtool_pauseparam *ecmd)
2547 struct jme_adapter *jme = netdev_priv(netdev);
2550 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2551 (ecmd->tx_pause != 0)) {
2554 jme->reg_txpfc |= TXPFC_PF_EN;
2556 jme->reg_txpfc &= ~TXPFC_PF_EN;
2558 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2561 spin_lock_bh(&jme->rxmcs_lock);
2562 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2563 (ecmd->rx_pause != 0)) {
2566 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2568 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2570 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2572 spin_unlock_bh(&jme->rxmcs_lock);
2574 spin_lock_bh(&jme->phy_lock);
2575 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2576 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2577 (ecmd->autoneg != 0)) {
2580 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2582 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2584 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2585 MII_ADVERTISE, val);
2587 spin_unlock_bh(&jme->phy_lock);
2593 jme_get_wol(struct net_device *netdev,
2594 struct ethtool_wolinfo *wol)
2596 struct jme_adapter *jme = netdev_priv(netdev);
2598 wol->supported = WAKE_MAGIC | WAKE_PHY;
2602 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2603 wol->wolopts |= WAKE_PHY;
2605 if (jme->reg_pmcs & PMCS_MFEN)
2606 wol->wolopts |= WAKE_MAGIC;
2611 jme_set_wol(struct net_device *netdev,
2612 struct ethtool_wolinfo *wol)
2614 struct jme_adapter *jme = netdev_priv(netdev);
2616 if (wol->wolopts & (WAKE_MAGICSECURE |
2625 if (wol->wolopts & WAKE_PHY)
2626 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2628 if (wol->wolopts & WAKE_MAGIC)
2629 jme->reg_pmcs |= PMCS_MFEN;
2631 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2637 jme_get_settings(struct net_device *netdev,
2638 struct ethtool_cmd *ecmd)
2640 struct jme_adapter *jme = netdev_priv(netdev);
2643 spin_lock_bh(&jme->phy_lock);
2644 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2645 spin_unlock_bh(&jme->phy_lock);
2650 jme_set_settings(struct net_device *netdev,
2651 struct ethtool_cmd *ecmd)
2653 struct jme_adapter *jme = netdev_priv(netdev);
2656 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2660 * Check If user changed duplex only while force_media.
2661 * Hardware would not generate link change interrupt.
2663 if (jme->mii_if.force_media &&
2664 ecmd->autoneg != AUTONEG_ENABLE &&
2665 (jme->mii_if.full_duplex != ecmd->duplex))
2668 spin_lock_bh(&jme->phy_lock);
2669 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2670 spin_unlock_bh(&jme->phy_lock);
2674 jme_reset_link(jme);
2675 jme->old_ecmd = *ecmd;
2676 set_bit(JME_FLAG_SSET, &jme->flags);
2683 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2686 struct jme_adapter *jme = netdev_priv(netdev);
2687 struct mii_ioctl_data *mii_data = if_mii(rq);
2688 unsigned int duplex_chg;
2690 if (cmd == SIOCSMIIREG) {
2691 u16 val = mii_data->val_in;
2692 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2693 (val & BMCR_SPEED1000))
2697 spin_lock_bh(&jme->phy_lock);
2698 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2699 spin_unlock_bh(&jme->phy_lock);
2701 if (!rc && (cmd == SIOCSMIIREG)) {
2703 jme_reset_link(jme);
2704 jme_get_settings(netdev, &jme->old_ecmd);
2705 set_bit(JME_FLAG_SSET, &jme->flags);
2712 jme_get_link(struct net_device *netdev)
2714 struct jme_adapter *jme = netdev_priv(netdev);
2715 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2719 jme_get_msglevel(struct net_device *netdev)
2721 struct jme_adapter *jme = netdev_priv(netdev);
2722 return jme->msg_enable;
2726 jme_set_msglevel(struct net_device *netdev, u32 value)
2728 struct jme_adapter *jme = netdev_priv(netdev);
2729 jme->msg_enable = value;
2733 jme_get_rx_csum(struct net_device *netdev)
2735 struct jme_adapter *jme = netdev_priv(netdev);
2736 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2740 jme_set_rx_csum(struct net_device *netdev, u32 on)
2742 struct jme_adapter *jme = netdev_priv(netdev);
2744 spin_lock_bh(&jme->rxmcs_lock);
2746 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2748 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2749 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2750 spin_unlock_bh(&jme->rxmcs_lock);
2756 jme_set_tx_csum(struct net_device *netdev, u32 on)
2758 struct jme_adapter *jme = netdev_priv(netdev);
2761 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2762 if (netdev->mtu <= 1900)
2764 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2766 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2768 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2775 jme_set_tso(struct net_device *netdev, u32 on)
2777 struct jme_adapter *jme = netdev_priv(netdev);
2780 set_bit(JME_FLAG_TSO, &jme->flags);
2781 if (netdev->mtu <= 1900)
2782 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2784 clear_bit(JME_FLAG_TSO, &jme->flags);
2785 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2792 jme_nway_reset(struct net_device *netdev)
2794 struct jme_adapter *jme = netdev_priv(netdev);
2795 jme_restart_an(jme);
2800 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2805 val = jread32(jme, JME_SMBCSR);
2806 to = JME_SMB_BUSY_TIMEOUT;
2807 while ((val & SMBCSR_BUSY) && --to) {
2809 val = jread32(jme, JME_SMBCSR);
2812 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2816 jwrite32(jme, JME_SMBINTF,
2817 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2818 SMBINTF_HWRWN_READ |
2821 val = jread32(jme, JME_SMBINTF);
2822 to = JME_SMB_BUSY_TIMEOUT;
2823 while ((val & SMBINTF_HWCMD) && --to) {
2825 val = jread32(jme, JME_SMBINTF);
2828 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2832 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2836 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2841 val = jread32(jme, JME_SMBCSR);
2842 to = JME_SMB_BUSY_TIMEOUT;
2843 while ((val & SMBCSR_BUSY) && --to) {
2845 val = jread32(jme, JME_SMBCSR);
2848 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2852 jwrite32(jme, JME_SMBINTF,
2853 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2854 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2855 SMBINTF_HWRWN_WRITE |
2858 val = jread32(jme, JME_SMBINTF);
2859 to = JME_SMB_BUSY_TIMEOUT;
2860 while ((val & SMBINTF_HWCMD) && --to) {
2862 val = jread32(jme, JME_SMBINTF);
2865 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2873 jme_get_eeprom_len(struct net_device *netdev)
2875 struct jme_adapter *jme = netdev_priv(netdev);
2877 val = jread32(jme, JME_SMBCSR);
2878 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2882 jme_get_eeprom(struct net_device *netdev,
2883 struct ethtool_eeprom *eeprom, u8 *data)
2885 struct jme_adapter *jme = netdev_priv(netdev);
2886 int i, offset = eeprom->offset, len = eeprom->len;
2889 * ethtool will check the boundary for us
2891 eeprom->magic = JME_EEPROM_MAGIC;
2892 for (i = 0 ; i < len ; ++i)
2893 data[i] = jme_smb_read(jme, i + offset);
2899 jme_set_eeprom(struct net_device *netdev,
2900 struct ethtool_eeprom *eeprom, u8 *data)
2902 struct jme_adapter *jme = netdev_priv(netdev);
2903 int i, offset = eeprom->offset, len = eeprom->len;
2905 if (eeprom->magic != JME_EEPROM_MAGIC)
2909 * ethtool will check the boundary for us
2911 for (i = 0 ; i < len ; ++i)
2912 jme_smb_write(jme, i + offset, data[i]);
2917 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2918 static struct ethtool_ops jme_ethtool_ops = {
2920 static const struct ethtool_ops jme_ethtool_ops = {
2922 .get_drvinfo = jme_get_drvinfo,
2923 .get_regs_len = jme_get_regs_len,
2924 .get_regs = jme_get_regs,
2925 .get_coalesce = jme_get_coalesce,
2926 .set_coalesce = jme_set_coalesce,
2927 .get_pauseparam = jme_get_pauseparam,
2928 .set_pauseparam = jme_set_pauseparam,
2929 .get_wol = jme_get_wol,
2930 .set_wol = jme_set_wol,
2931 .get_settings = jme_get_settings,
2932 .set_settings = jme_set_settings,
2933 .get_link = jme_get_link,
2934 .get_msglevel = jme_get_msglevel,
2935 .set_msglevel = jme_set_msglevel,
2936 .get_rx_csum = jme_get_rx_csum,
2937 .set_rx_csum = jme_set_rx_csum,
2938 .set_tx_csum = jme_set_tx_csum,
2939 .set_tso = jme_set_tso,
2940 .set_sg = ethtool_op_set_sg,
2941 .nway_reset = jme_nway_reset,
2942 .get_eeprom_len = jme_get_eeprom_len,
2943 .get_eeprom = jme_get_eeprom,
2944 .set_eeprom = jme_set_eeprom,
2948 jme_pci_dma64(struct pci_dev *pdev)
2950 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2951 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2952 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2954 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2957 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2958 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2960 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2964 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2965 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2966 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2968 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2971 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2972 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2974 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2978 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2979 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2980 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2982 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2983 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2991 jme_phy_init(struct jme_adapter *jme)
2995 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2996 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3000 jme_check_hw_ver(struct jme_adapter *jme)
3004 chipmode = jread32(jme, JME_CHIPMODE);
3006 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3007 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3008 jme->chip_main_rev = jme->chiprev & 0xF;
3009 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3012 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3013 static const struct net_device_ops jme_netdev_ops = {
3014 .ndo_open = jme_open,
3015 .ndo_stop = jme_close,
3016 .ndo_validate_addr = eth_validate_addr,
3017 .ndo_do_ioctl = jme_ioctl,
3018 .ndo_start_xmit = jme_start_xmit,
3019 .ndo_set_mac_address = jme_set_macaddr,
3020 .ndo_set_multicast_list = jme_set_multi,
3021 .ndo_change_mtu = jme_change_mtu,
3022 .ndo_tx_timeout = jme_tx_timeout,
3023 .ndo_vlan_rx_register = jme_vlan_rx_register,
3027 static int __devinit
3028 jme_init_one(struct pci_dev *pdev,
3029 const struct pci_device_id *ent)
3031 int rc = 0, using_dac, i;
3032 struct net_device *netdev;
3033 struct jme_adapter *jme;
3038 * set up PCI device basics
3040 rc = pci_enable_device(pdev);
3042 pr_err("Cannot enable PCI device\n");
3046 using_dac = jme_pci_dma64(pdev);
3047 if (using_dac < 0) {
3048 pr_err("Cannot set PCI DMA Mask\n");
3050 goto err_out_disable_pdev;
3053 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3054 pr_err("No PCI resource region found\n");
3056 goto err_out_disable_pdev;
3059 rc = pci_request_regions(pdev, DRV_NAME);
3061 pr_err("Cannot obtain PCI resource region\n");
3062 goto err_out_disable_pdev;
3065 pci_set_master(pdev);
3068 * alloc and init net device
3070 netdev = alloc_etherdev(sizeof(*jme));
3072 pr_err("Cannot allocate netdev structure\n");
3074 goto err_out_release_regions;
3076 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3077 netdev->netdev_ops = &jme_netdev_ops;
3079 netdev->open = jme_open;
3080 netdev->stop = jme_close;
3081 netdev->do_ioctl = jme_ioctl;
3082 netdev->hard_start_xmit = jme_start_xmit;
3083 netdev->set_mac_address = jme_set_macaddr;
3084 netdev->set_multicast_list = jme_set_multi;
3085 netdev->change_mtu = jme_change_mtu;
3086 netdev->tx_timeout = jme_tx_timeout;
3087 netdev->vlan_rx_register = jme_vlan_rx_register;
3088 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3089 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3091 NETDEV_GET_STATS(netdev, &jme_get_stats);
3093 netdev->ethtool_ops = &jme_ethtool_ops;
3094 netdev->watchdog_timeo = TX_TIMEOUT;
3095 netdev->features = NETIF_F_IP_CSUM |
3100 NETIF_F_HW_VLAN_TX |
3103 netdev->features |= NETIF_F_HIGHDMA;
3105 SET_NETDEV_DEV(netdev, &pdev->dev);
3106 pci_set_drvdata(pdev, netdev);
3111 jme = netdev_priv(netdev);
3114 jme->jme_rx = netif_rx;
3115 jme->jme_vlan_rx = vlan_hwaccel_rx;
3116 jme->old_mtu = netdev->mtu = 1500;
3118 jme->tx_ring_size = 1 << 10;
3119 jme->tx_ring_mask = jme->tx_ring_size - 1;
3120 jme->tx_wake_threshold = 1 << 9;
3121 jme->rx_ring_size = 1 << 9;
3122 jme->rx_ring_mask = jme->rx_ring_size - 1;
3123 jme->msg_enable = JME_DEF_MSG_ENABLE;
3124 jme->regs = ioremap(pci_resource_start(pdev, 0),
3125 pci_resource_len(pdev, 0));
3127 pr_err("Mapping PCI resource region error\n");
3129 goto err_out_free_netdev;
3133 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3134 jwrite32(jme, JME_APMC, apmc);
3135 } else if (force_pseudohp) {
3136 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3137 jwrite32(jme, JME_APMC, apmc);
3140 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3142 spin_lock_init(&jme->phy_lock);
3143 spin_lock_init(&jme->macaddr_lock);
3144 spin_lock_init(&jme->rxmcs_lock);
3146 atomic_set(&jme->link_changing, 1);
3147 atomic_set(&jme->rx_cleaning, 1);
3148 atomic_set(&jme->tx_cleaning, 1);
3149 atomic_set(&jme->rx_empty, 1);
3151 tasklet_init(&jme->pcc_task,
3153 (unsigned long) jme);
3154 tasklet_init(&jme->linkch_task,
3155 jme_link_change_tasklet,
3156 (unsigned long) jme);
3157 tasklet_init(&jme->txclean_task,
3158 jme_tx_clean_tasklet,
3159 (unsigned long) jme);
3160 tasklet_init(&jme->rxclean_task,
3161 jme_rx_clean_tasklet,
3162 (unsigned long) jme);
3163 tasklet_init(&jme->rxempty_task,
3164 jme_rx_empty_tasklet,
3165 (unsigned long) jme);
3166 tasklet_disable_nosync(&jme->linkch_task);
3167 tasklet_disable_nosync(&jme->txclean_task);
3168 tasklet_disable_nosync(&jme->rxclean_task);
3169 tasklet_disable_nosync(&jme->rxempty_task);
3170 jme->dpi.cur = PCC_P1;
3173 jme->reg_rxcs = RXCS_DEFAULT;
3174 jme->reg_rxmcs = RXMCS_DEFAULT;
3176 jme->reg_pmcs = PMCS_MFEN;
3177 jme->reg_gpreg1 = GPREG1_DEFAULT;
3178 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3179 set_bit(JME_FLAG_TSO, &jme->flags);
3182 * Get Max Read Req Size from PCI Config Space
3184 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3185 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3186 switch (jme->mrrs) {
3188 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3191 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3194 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3199 * Must check before reset_mac_processor
3201 jme_check_hw_ver(jme);
3202 jme->mii_if.dev = netdev;
3204 jme->mii_if.phy_id = 0;
3205 for (i = 1 ; i < 32 ; ++i) {
3206 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3207 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3208 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3209 jme->mii_if.phy_id = i;
3214 if (!jme->mii_if.phy_id) {
3216 pr_err("Can not find phy_id\n");
3220 jme->reg_ghc |= GHC_LINK_POLL;
3222 jme->mii_if.phy_id = 1;
3224 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3225 jme->mii_if.supports_gmii = true;
3227 jme->mii_if.supports_gmii = false;
3228 jme->mii_if.phy_id_mask = 0x1F;
3229 jme->mii_if.reg_num_mask = 0x1F;
3230 jme->mii_if.mdio_read = jme_mdio_read;
3231 jme->mii_if.mdio_write = jme_mdio_write;
3234 jme_set_phyfifo_5level(jme);
3235 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3236 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3238 jme->pcirev = pdev->revision;
3245 * Reset MAC processor and reload EEPROM for MAC Address
3247 jme_reset_mac_processor(jme);
3248 rc = jme_reload_eeprom(jme);
3250 pr_err("Reload eeprom for reading MAC Address error\n");
3253 jme_load_macaddr(netdev);
3256 * Tell stack that we are not ready to work until open()
3258 netif_carrier_off(netdev);
3260 rc = register_netdev(netdev);
3262 pr_err("Cannot register net device\n");
3266 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3267 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3268 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3269 "JMC250 Gigabit Ethernet" :
3270 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3271 "JMC260 Fast Ethernet" : "Unknown",
3272 (jme->fpgaver != 0) ? " (FPGA)" : "",
3273 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3275 netdev->dev_addr[0],
3276 netdev->dev_addr[1],
3277 netdev->dev_addr[2],
3278 netdev->dev_addr[3],
3279 netdev->dev_addr[4],
3280 netdev->dev_addr[5]);
3286 err_out_free_netdev:
3287 pci_set_drvdata(pdev, NULL);
3288 free_netdev(netdev);
3289 err_out_release_regions:
3290 pci_release_regions(pdev);
3291 err_out_disable_pdev:
3292 pci_disable_device(pdev);
3297 static void __devexit
3298 jme_remove_one(struct pci_dev *pdev)
3300 struct net_device *netdev = pci_get_drvdata(pdev);
3301 struct jme_adapter *jme = netdev_priv(netdev);
3303 unregister_netdev(netdev);
3305 pci_set_drvdata(pdev, NULL);
3306 free_netdev(netdev);
3307 pci_release_regions(pdev);
3308 pci_disable_device(pdev);
3313 jme_shutdown(struct pci_dev *pdev)
3315 struct net_device *netdev = pci_get_drvdata(pdev);
3316 struct jme_adapter *jme = netdev_priv(netdev);
3318 jme_powersave_phy(jme);
3319 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3320 pci_enable_wake(pdev, PCI_D3hot, true);
3322 pci_pme_active(pdev, true);
3328 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3330 struct net_device *netdev = pci_get_drvdata(pdev);
3331 struct jme_adapter *jme = netdev_priv(netdev);
3333 atomic_dec(&jme->link_changing);
3335 netif_device_detach(netdev);
3336 netif_stop_queue(netdev);
3339 tasklet_disable(&jme->txclean_task);
3340 tasklet_disable(&jme->rxclean_task);
3341 tasklet_disable(&jme->rxempty_task);
3343 if (netif_carrier_ok(netdev)) {
3344 if (test_bit(JME_FLAG_POLL, &jme->flags))
3345 jme_polling_mode(jme);
3347 jme_stop_pcc_timer(jme);
3348 jme_disable_rx_engine(jme);
3349 jme_disable_tx_engine(jme);
3350 jme_reset_mac_processor(jme);
3351 jme_free_rx_resources(jme);
3352 jme_free_tx_resources(jme);
3353 netif_carrier_off(netdev);
3357 tasklet_enable(&jme->txclean_task);
3358 tasklet_hi_enable(&jme->rxclean_task);
3359 tasklet_hi_enable(&jme->rxempty_task);
3361 pci_save_state(pdev);
3362 jme_powersave_phy(jme);
3363 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3364 pci_enable_wake(pdev, PCI_D3hot, true);
3366 pci_pme_active(pdev, true);
3368 pci_set_power_state(pdev, PCI_D3hot);
3374 jme_resume(struct pci_dev *pdev)
3376 struct net_device *netdev = pci_get_drvdata(pdev);
3377 struct jme_adapter *jme = netdev_priv(netdev);
3380 pci_restore_state(pdev);
3383 if (test_bit(JME_FLAG_SSET, &jme->flags))
3384 jme_set_settings(netdev, &jme->old_ecmd);
3386 jme_reset_phy_processor(jme);
3389 netif_device_attach(netdev);
3391 atomic_inc(&jme->link_changing);
3393 jme_reset_link(jme);
3399 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3400 static struct pci_device_id jme_pci_tbl[] = {
3402 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3404 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3405 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3409 static struct pci_driver jme_driver = {
3411 .id_table = jme_pci_tbl,
3412 .probe = jme_init_one,
3413 .remove = __devexit_p(jme_remove_one),
3415 .suspend = jme_suspend,
3416 .resume = jme_resume,
3417 #endif /* CONFIG_PM */
3418 .shutdown = jme_shutdown,
3422 jme_init_module(void)
3424 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3425 return pci_register_driver(&jme_driver);
3429 jme_cleanup_module(void)
3431 pci_unregister_driver(&jme_driver);
3434 module_init(jme_init_module);
3435 module_exit(jme_cleanup_module);
3437 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3438 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3439 MODULE_LICENSE("GPL");
3440 MODULE_VERSION(DRV_VERSION);
3441 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);