2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * - Decode register dump for ethtool.
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
48 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
49 static struct net_device_stats *
50 jme_get_stats(struct net_device *netdev)
52 struct jme_adapter *jme = netdev_priv(netdev);
58 jme_mdio_read(struct net_device *netdev, int phy, int reg)
60 struct jme_adapter *jme = netdev_priv(netdev);
61 int i, val, again = (reg == MII_BMSR)?1:0;
64 jwrite32(jme, JME_SMI, SMI_OP_REQ |
69 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
71 val = jread32(jme, JME_SMI);
72 if ((val & SMI_OP_REQ) == 0)
77 jeprintk("jme", "phy(%d) read timeout : %d\n", phy, reg);
84 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
88 jme_mdio_write(struct net_device *netdev,
89 int phy, int reg, int val)
91 struct jme_adapter *jme = netdev_priv(netdev);
94 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
95 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
96 smi_phy_addr(phy) | smi_reg_addr(reg));
99 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
101 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
106 jeprintk("jme", "phy(%d) write timeout : %d\n", phy, reg);
111 __always_inline static void
112 jme_reset_phy_processor(struct jme_adapter *jme)
116 jme_mdio_write(jme->dev,
118 MII_ADVERTISE, ADVERTISE_ALL |
119 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
121 if(jme->pdev->device == JME_GE_DEVICE)
122 jme_mdio_write(jme->dev,
125 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
127 val = jme_mdio_read(jme->dev,
131 jme_mdio_write(jme->dev,
133 MII_BMCR, val | BMCR_RESET);
139 jme_setup_wakeup_frame(struct jme_adapter *jme,
140 __u32 *mask, __u32 crc, int fnr)
147 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 jwrite32(jme, JME_WFODP, crc);
155 for(i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
156 jwrite32(jme, JME_WFOI,
157 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
158 (fnr & WFOI_FRAME_SEL));
160 jwrite32(jme, JME_WFODP, mask[i]);
165 __always_inline static void
166 jme_reset_mac_processor(struct jme_adapter *jme)
168 __u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0,0,0,0};
169 __u32 crc = 0xCDCDCDCD;
173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
175 jwrite32(jme, JME_GHC, jme->reg_ghc);
176 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
177 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
178 for(i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
179 jme_setup_wakeup_frame(jme, mask, crc, i);
181 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
183 gpreg0 = GPREG0_DEFAULT;
184 jwrite32(jme, JME_GPREG0, gpreg0);
185 jwrite32(jme, JME_GPREG1, 0);
188 __always_inline static void
189 jme_clear_pm(struct jme_adapter *jme)
191 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
192 pci_set_power_state(jme->pdev, PCI_D0);
193 pci_enable_wake(jme->pdev, PCI_D0, false);
197 jme_reload_eeprom(struct jme_adapter *jme)
202 val = jread32(jme, JME_SMBCSR);
204 if(val & SMBCSR_EEPROMD)
207 jwrite32(jme, JME_SMBCSR, val);
208 val |= SMBCSR_RELOAD;
209 jwrite32(jme, JME_SMBCSR, val);
212 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i)
215 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
220 jeprintk("jme", "eeprom reload timeout\n");
229 jme_load_macaddr(struct net_device *netdev)
231 struct jme_adapter *jme = netdev_priv(netdev);
232 unsigned char macaddr[6];
235 spin_lock(&jme->macaddr_lock);
236 val = jread32(jme, JME_RXUMA_LO);
237 macaddr[0] = (val >> 0) & 0xFF;
238 macaddr[1] = (val >> 8) & 0xFF;
239 macaddr[2] = (val >> 16) & 0xFF;
240 macaddr[3] = (val >> 24) & 0xFF;
241 val = jread32(jme, JME_RXUMA_HI);
242 macaddr[4] = (val >> 0) & 0xFF;
243 macaddr[5] = (val >> 8) & 0xFF;
244 memcpy(netdev->dev_addr, macaddr, 6);
245 spin_unlock(&jme->macaddr_lock);
248 __always_inline static void
249 jme_set_rx_pcc(struct jme_adapter *jme, int p)
253 jwrite32(jme, JME_PCCRX0,
254 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
255 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
258 jwrite32(jme, JME_PCCRX0,
259 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
260 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
277 if(!(jme->flags & JME_FLAG_POLL))
278 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
282 jme_start_irq(struct jme_adapter *jme)
284 register struct dynpcc_info *dpi = &(jme->dpi);
286 jme_set_rx_pcc(jme, PCC_P1);
288 dpi->attempt = PCC_P1;
291 jwrite32(jme, JME_PCCTX,
292 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
293 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
300 jwrite32(jme, JME_IENS, INTR_ENABLE);
303 __always_inline static void
304 jme_stop_irq(struct jme_adapter *jme)
309 jwrite32(jme, JME_IENC, INTR_ENABLE);
313 __always_inline static void
314 jme_enable_shadow(struct jme_adapter *jme)
318 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
321 __always_inline static void
322 jme_disable_shadow(struct jme_adapter *jme)
324 jwrite32(jme, JME_SHBA_LO, 0x0);
328 jme_linkstat_from_phy(struct jme_adapter *jme)
332 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
333 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
334 if(bmsr & BMSR_ANCOMP)
335 phylink |= PHY_LINK_AUTONEG_COMPLETE;
341 jme_check_link(struct net_device *netdev, int testonly)
343 struct jme_adapter *jme = netdev_priv(netdev);
344 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
351 phylink = jme_linkstat_from_phy(jme);
353 phylink = jread32(jme, JME_PHY_LINK);
355 if (phylink & PHY_LINK_UP) {
356 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
358 * If we did not enable AN
359 * Speed/Duplex Info should be obtained from SMI
361 phylink = PHY_LINK_UP;
363 bmcr = jme_mdio_read(jme->dev,
368 phylink |= ((bmcr & BMCR_SPEED1000) &&
369 (bmcr & BMCR_SPEED100) == 0) ?
370 PHY_LINK_SPEED_1000M :
371 (bmcr & BMCR_SPEED100) ?
372 PHY_LINK_SPEED_100M :
375 phylink |= (bmcr & BMCR_FULLDPLX) ?
378 strcat(linkmsg, "Forced: ");
382 * Keep polling for speed/duplex resolve complete
384 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
390 phylink = jme_linkstat_from_phy(jme);
392 phylink = jread32(jme, JME_PHY_LINK);
396 jeprintk(netdev->name,
397 "Waiting speed resolve timeout.\n");
399 strcat(linkmsg, "ANed: ");
402 if(jme->phylink == phylink) {
409 jme->phylink = phylink;
411 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
415 switch(phylink & PHY_LINK_SPEED_MASK) {
416 case PHY_LINK_SPEED_10M:
417 ghc |= GHC_SPEED_10M;
418 strcat(linkmsg, "10 Mbps, ");
420 case PHY_LINK_SPEED_100M:
421 ghc |= GHC_SPEED_100M;
422 strcat(linkmsg, "100 Mbps, ");
424 case PHY_LINK_SPEED_1000M:
425 ghc |= GHC_SPEED_1000M;
426 strcat(linkmsg, "1000 Mbps, ");
431 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
433 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
437 if(phylink & PHY_LINK_MDI_STAT)
438 strcat(linkmsg, "MDI-X");
440 strcat(linkmsg, "MDI");
442 if(phylink & PHY_LINK_DUPLEX)
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
456 jwrite32(jme, JME_GHC, ghc);
458 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
459 netif_carrier_on(netdev);
465 jprintk(netdev->name, "Link is down.\n");
467 netif_carrier_off(netdev);
475 jme_setup_tx_resources(struct jme_adapter *jme)
477 struct jme_ring *txring = &(jme->txring[0]);
479 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
480 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
486 txring->dmaalloc = 0;
494 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
496 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
497 txring->next_to_use = 0;
498 atomic_set(&txring->next_to_clean, 0);
499 atomic_set(&txring->nr_free, jme->tx_ring_size);
502 * Initialize Transmit Descriptors
504 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
505 memset(txring->bufinf, 0,
506 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
512 jme_free_tx_resources(struct jme_adapter *jme)
515 struct jme_ring *txring = &(jme->txring[0]);
516 struct jme_buffer_info *txbi = txring->bufinf;
519 for(i = 0 ; i < jme->tx_ring_size ; ++i) {
520 txbi = txring->bufinf + i;
522 dev_kfree_skb(txbi->skb);
528 txbi->start_xmit = 0;
531 dma_free_coherent(&(jme->pdev->dev),
532 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
536 txring->alloc = NULL;
538 txring->dmaalloc = 0;
541 txring->next_to_use = 0;
542 atomic_set(&txring->next_to_clean, 0);
543 atomic_set(&txring->nr_free, 0);
547 __always_inline static void
548 jme_enable_tx_engine(struct jme_adapter *jme)
553 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
556 * Setup TX Queue 0 DMA Bass Address
558 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
559 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
560 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
563 * Setup TX Descptor Count
565 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
571 jwrite32(jme, JME_TXCS, jme->reg_txcs |
577 __always_inline static void
578 jme_restart_tx_engine(struct jme_adapter *jme)
583 jwrite32(jme, JME_TXCS, jme->reg_txcs |
588 __always_inline static void
589 jme_disable_tx_engine(struct jme_adapter *jme)
597 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
599 val = jread32(jme, JME_TXCS);
600 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
603 val = jread32(jme, JME_TXCS);
607 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
608 jme_reset_mac_processor(jme);
615 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
617 struct jme_ring *rxring = jme->rxring;
618 register volatile struct rxdesc* rxdesc = rxring->desc;
619 struct jme_buffer_info *rxbi = rxring->bufinf;
625 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
626 rxdesc->desc1.bufaddrl = cpu_to_le32(
627 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
628 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
629 if(jme->dev->features & NETIF_F_HIGHDMA)
630 rxdesc->desc1.flags = RXFLAG_64BIT;
632 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
636 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
638 struct jme_ring *rxring = &(jme->rxring[0]);
639 struct jme_buffer_info *rxbi = rxring->bufinf + i;
640 unsigned long offset;
643 skb = netdev_alloc_skb(jme->dev,
644 jme->dev->mtu + RX_EXTRA_LEN);
649 (unsigned long)(skb->data)
650 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
651 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
654 rxbi->len = skb_tailroom(skb);
655 rxbi->mapping = pci_map_page(jme->pdev,
656 virt_to_page(skb->data),
657 offset_in_page(skb->data),
665 jme_free_rx_buf(struct jme_adapter *jme, int i)
667 struct jme_ring *rxring = &(jme->rxring[0]);
668 struct jme_buffer_info *rxbi = rxring->bufinf;
672 pci_unmap_page(jme->pdev,
676 dev_kfree_skb(rxbi->skb);
684 jme_free_rx_resources(struct jme_adapter *jme)
687 struct jme_ring *rxring = &(jme->rxring[0]);
690 for(i = 0 ; i < jme->rx_ring_size ; ++i)
691 jme_free_rx_buf(jme, i);
693 dma_free_coherent(&(jme->pdev->dev),
694 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
697 rxring->alloc = NULL;
699 rxring->dmaalloc = 0;
702 rxring->next_to_use = 0;
703 atomic_set(&rxring->next_to_clean, 0);
707 jme_setup_rx_resources(struct jme_adapter *jme)
710 struct jme_ring *rxring = &(jme->rxring[0]);
712 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
713 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
718 rxring->dmaalloc = 0;
726 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
728 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
729 rxring->next_to_use = 0;
730 atomic_set(&rxring->next_to_clean, 0);
733 * Initiallize Receive Descriptors
735 for(i = 0 ; i < jme->rx_ring_size ; ++i) {
736 if(unlikely(jme_make_new_rx_buf(jme, i))) {
737 jme_free_rx_resources(jme);
741 jme_set_clean_rxdesc(jme, i);
747 __always_inline static void
748 jme_enable_rx_engine(struct jme_adapter *jme)
751 * Setup RX DMA Bass Address
753 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
754 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
755 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
758 * Setup RX Descriptor Count
760 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
763 * Setup Unicast Filter
765 jme_set_multi(jme->dev);
771 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
777 __always_inline static void
778 jme_restart_rx_engine(struct jme_adapter *jme)
783 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
790 __always_inline static void
791 jme_disable_rx_engine(struct jme_adapter *jme)
799 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
801 val = jread32(jme, JME_RXCS);
802 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
805 val = jread32(jme, JME_RXCS);
809 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
814 jme_rxsum_ok(struct jme_adapter *jme, __u16 flags)
816 if(!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
819 if(unlikely((flags & RXWBFLAG_TCPON) &&
820 !(flags & RXWBFLAG_TCPCS))) {
821 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
825 if(unlikely((flags & RXWBFLAG_UDPON) &&
826 !(flags & RXWBFLAG_UDPCS))) {
827 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
831 if(unlikely((flags & RXWBFLAG_IPV4) &&
832 !(flags & RXWBFLAG_IPCS))) {
833 csum_dbg(jme->dev->name, "IPv4 Checksum error.\n");
840 csum_dbg(jme->dev->name, "%s%s%s%s\n",
841 (flags & RXWBFLAG_IPV4)?"IPv4 ":"",
842 (flags & RXWBFLAG_IPV6)?"IPv6 ":"",
843 (flags & RXWBFLAG_UDPON)?"UDP ":"",
844 (flags & RXWBFLAG_TCPON)?"TCP":"");
849 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
851 struct jme_ring *rxring = &(jme->rxring[0]);
852 volatile struct rxdesc *rxdesc = rxring->desc;
853 struct jme_buffer_info *rxbi = rxring->bufinf;
861 pci_dma_sync_single_for_cpu(jme->pdev,
866 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
867 pci_dma_sync_single_for_device(jme->pdev,
872 ++(NET_STAT(jme).rx_dropped);
875 framesize = le16_to_cpu(rxdesc->descwb.framesize)
878 skb_reserve(skb, RX_PREPAD_SIZE);
879 skb_put(skb, framesize);
880 skb->protocol = eth_type_trans(skb, jme->dev);
882 if(jme_rxsum_ok(jme, rxdesc->descwb.flags))
883 skb->ip_summed = CHECKSUM_UNNECESSARY;
885 skb->ip_summed = CHECKSUM_NONE;
888 if(rxdesc->descwb.flags & RXWBFLAG_TAGON) {
889 vlan_dbg(jme->dev->name, "VLAN: %04x\n",
890 rxdesc->descwb.vlan);
892 vlan_dbg(jme->dev->name,
893 "VLAN Passed to kernel.\n");
894 jme->jme_vlan_rx(skb, jme->vlgrp,
895 le32_to_cpu(rxdesc->descwb.vlan));
896 NET_STAT(jme).rx_bytes += 4;
903 if((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
905 ++(NET_STAT(jme).multicast);
907 jme->dev->last_rx = jiffies;
908 NET_STAT(jme).rx_bytes += framesize;
909 ++(NET_STAT(jme).rx_packets);
912 jme_set_clean_rxdesc(jme, idx);
919 jme_process_receive(struct jme_adapter *jme, int limit)
921 struct jme_ring *rxring = &(jme->rxring[0]);
922 volatile struct rxdesc *rxdesc = rxring->desc;
923 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
925 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
928 if(unlikely(atomic_read(&jme->link_changing) != 1))
931 if(unlikely(!netif_carrier_ok(jme->dev)))
934 i = atomic_read(&rxring->next_to_clean);
937 rxdesc = rxring->desc;
940 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
941 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
944 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
946 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
948 if(unlikely(desccnt > 1 ||
949 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
951 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
952 ++(NET_STAT(jme).rx_crc_errors);
953 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
954 ++(NET_STAT(jme).rx_fifo_errors);
956 ++(NET_STAT(jme).rx_errors);
959 rx_dbg(jme->dev->name,
960 "RX: More than one(%d) descriptor, "
962 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
963 limit -= desccnt - 1;
966 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
967 jme_set_clean_rxdesc(jme, j);
968 j = (j + 1) & (mask);
973 jme_alloc_and_feed_skb(jme, i);
976 i = (i + desccnt) & (mask);
981 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
982 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
983 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
986 atomic_set(&rxring->next_to_clean, i);
989 atomic_inc(&jme->rx_cleaning);
991 return limit > 0 ? limit : 0;
996 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
998 if(likely(atmp == dpi->cur)) {
1003 if(dpi->attempt == atmp) {
1007 dpi->attempt = atmp;
1014 jme_dynamic_pcc(struct jme_adapter *jme)
1016 register struct dynpcc_info *dpi = &(jme->dpi);
1018 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1019 jme_attempt_pcc(dpi, PCC_P3);
1020 else if((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1021 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1022 jme_attempt_pcc(dpi, PCC_P2);
1024 jme_attempt_pcc(dpi, PCC_P1);
1026 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1027 jme_set_rx_pcc(jme, dpi->attempt);
1028 dpi->cur = dpi->attempt;
1034 jme_start_pcc_timer(struct jme_adapter *jme)
1036 struct dynpcc_info *dpi = &(jme->dpi);
1037 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1038 dpi->last_pkts = NET_STAT(jme).rx_packets;
1040 jwrite32(jme, JME_TMCSR,
1041 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1044 __always_inline static void
1045 jme_stop_pcc_timer(struct jme_adapter *jme)
1047 jwrite32(jme, JME_TMCSR, 0);
1051 jme_pcc_tasklet(unsigned long arg)
1053 struct jme_adapter *jme = (struct jme_adapter*)arg;
1054 struct net_device *netdev = jme->dev;
1057 if(unlikely(!netif_carrier_ok(netdev) ||
1058 (atomic_read(&jme->link_changing) != 1)
1060 jme_stop_pcc_timer(jme);
1064 if(!(jme->flags & JME_FLAG_POLL))
1065 jme_dynamic_pcc(jme);
1067 jme_start_pcc_timer(jme);
1070 __always_inline static void
1071 jme_polling_mode(struct jme_adapter *jme)
1073 jme_set_rx_pcc(jme, PCC_OFF);
1076 __always_inline static void
1077 jme_interrupt_mode(struct jme_adapter *jme)
1079 jme_set_rx_pcc(jme, PCC_P1);
1083 jme_link_change_tasklet(unsigned long arg)
1085 struct jme_adapter *jme = (struct jme_adapter*)arg;
1086 struct net_device *netdev = jme->dev;
1087 int timeout = WAIT_TASKLET_TIMEOUT;
1090 if(!atomic_dec_and_test(&jme->link_changing))
1093 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1096 jme->old_mtu = netdev->mtu;
1097 netif_stop_queue(netdev);
1099 while(--timeout > 0 &&
1101 atomic_read(&jme->rx_cleaning) != 1 ||
1102 atomic_read(&jme->tx_cleaning) != 1
1108 if(netif_carrier_ok(netdev)) {
1109 jme_stop_pcc_timer(jme);
1110 jme_reset_mac_processor(jme);
1111 jme_free_rx_resources(jme);
1112 jme_free_tx_resources(jme);
1114 if(jme->flags & JME_FLAG_POLL)
1115 jme_polling_mode(jme);
1118 jme_check_link(netdev, 0);
1119 if(netif_carrier_ok(netdev)) {
1120 rc = jme_setup_rx_resources(jme);
1122 jeprintk(netdev->name,
1123 "Allocating resources for RX error"
1124 ", Device STOPPED!\n");
1129 rc = jme_setup_tx_resources(jme);
1131 jeprintk(netdev->name,
1132 "Allocating resources for TX error"
1133 ", Device STOPPED!\n");
1134 goto err_out_free_rx_resources;
1137 jme_enable_rx_engine(jme);
1138 jme_enable_tx_engine(jme);
1140 netif_start_queue(netdev);
1142 if(jme->flags & JME_FLAG_POLL)
1143 jme_interrupt_mode(jme);
1145 jme_start_pcc_timer(jme);
1150 err_out_free_rx_resources:
1151 jme_free_rx_resources(jme);
1153 atomic_inc(&jme->link_changing);
1157 jme_rx_clean_tasklet(unsigned long arg)
1159 struct jme_adapter *jme = (struct jme_adapter*)arg;
1160 struct dynpcc_info *dpi = &(jme->dpi);
1162 jme_process_receive(jme, jme->rx_ring_size);
1168 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1170 struct jme_adapter *jme = jme_napi_priv(holder);
1171 struct net_device *netdev = jme->dev;
1174 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1176 while(atomic_read(&jme->rx_empty) > 0) {
1177 atomic_dec(&jme->rx_empty);
1178 ++(NET_STAT(jme).rx_dropped);
1179 jme_restart_rx_engine(jme);
1181 atomic_inc(&jme->rx_empty);
1184 JME_RX_COMPLETE(netdev, holder);
1185 jme_interrupt_mode(jme);
1188 JME_NAPI_WEIGHT_SET(budget, rest);
1189 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1193 jme_rx_empty_tasklet(unsigned long arg)
1195 struct jme_adapter *jme = (struct jme_adapter*)arg;
1197 if(unlikely(atomic_read(&jme->link_changing) != 1))
1200 if(unlikely(!netif_carrier_ok(jme->dev)))
1203 queue_dbg(jme->dev->name, "RX Queue Full!\n");
1205 jme_rx_clean_tasklet(arg);
1207 while(atomic_read(&jme->rx_empty) > 0) {
1208 atomic_dec(&jme->rx_empty);
1209 ++(NET_STAT(jme).rx_dropped);
1210 jme_restart_rx_engine(jme);
1212 atomic_inc(&jme->rx_empty);
1216 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1218 struct jme_ring *txring = jme->txring;
1221 if(unlikely(netif_queue_stopped(jme->dev) &&
1222 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1224 queue_dbg(jme->dev->name, "TX Queue Waked.\n");
1225 netif_wake_queue(jme->dev);
1232 jme_tx_clean_tasklet(unsigned long arg)
1234 struct jme_adapter *jme = (struct jme_adapter*)arg;
1235 struct jme_ring *txring = &(jme->txring[0]);
1236 volatile struct txdesc *txdesc = txring->desc;
1237 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1238 int i, j, cnt = 0, max, err, mask;
1240 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1243 if(unlikely(atomic_read(&jme->link_changing) != 1))
1246 if(unlikely(!netif_carrier_ok(jme->dev)))
1249 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1250 mask = jme->tx_ring_mask;
1252 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1254 for(i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1258 if(likely(ctxbi->skb &&
1259 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1261 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1263 tx_dbg(jme->dev->name,
1264 "Tx Tasklet: Clean %d+%d\n",
1267 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1268 ttxbi = txbi + ((i + j) & (mask));
1269 txdesc[(i + j) & (mask)].dw[0] = 0;
1271 pci_unmap_page(jme->pdev,
1280 dev_kfree_skb(ctxbi->skb);
1282 cnt += ctxbi->nr_desc;
1285 ++(NET_STAT(jme).tx_carrier_errors);
1287 ++(NET_STAT(jme).tx_packets);
1288 NET_STAT(jme).tx_bytes += ctxbi->len;
1293 ctxbi->start_xmit = 0;
1297 tx_dbg(jme->dev->name,
1299 " Stopped due to no skb.\n");
1301 tx_dbg(jme->dev->name,
1303 "Stopped due to not done.\n");
1307 i = (i + ctxbi->nr_desc) & mask;
1312 tx_dbg(jme->dev->name,
1313 "Tx Tasklet: Stop %d Jiffies %lu\n",
1316 atomic_set(&txring->next_to_clean, i);
1317 atomic_add(cnt, &txring->nr_free);
1319 jme_wake_queue_if_stopped(jme);
1322 atomic_inc(&jme->tx_cleaning);
1326 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1331 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1333 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1335 * Link change event is critical
1336 * all other events are ignored
1338 jwrite32(jme, JME_IEVE, intrstat);
1339 tasklet_schedule(&jme->linkch_task);
1343 if(intrstat & INTR_TMINTR) {
1344 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1345 tasklet_schedule(&jme->pcc_task);
1348 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1349 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1350 tasklet_schedule(&jme->txclean_task);
1353 if((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1354 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1360 if(jme->flags & JME_FLAG_POLL) {
1361 if(intrstat & INTR_RX0EMP)
1362 atomic_inc(&jme->rx_empty);
1364 if((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1365 if(likely(JME_RX_SCHEDULE_PREP(jme))) {
1366 jme_polling_mode(jme);
1367 JME_RX_SCHEDULE(jme);
1372 if(intrstat & INTR_RX0EMP) {
1373 atomic_inc(&jme->rx_empty);
1374 tasklet_schedule(&jme->rxempty_task);
1376 else if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1377 tasklet_schedule(&jme->rxclean_task);
1382 * Re-enable interrupt
1384 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1390 jme_intr(int irq, void *dev_id)
1392 struct net_device *netdev = dev_id;
1393 struct jme_adapter *jme = netdev_priv(netdev);
1396 intrstat = jread32(jme, JME_IEVE);
1399 * Check if it's really an interrupt for us
1401 if(unlikely(intrstat == 0))
1405 * Check if the device still exist
1407 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1410 jme_intr_msi(jme, intrstat);
1416 jme_msi(int irq, void *dev_id)
1418 struct net_device *netdev = dev_id;
1419 struct jme_adapter *jme = netdev_priv(netdev);
1422 pci_dma_sync_single_for_cpu(jme->pdev,
1424 sizeof(__u32) * SHADOW_REG_NR,
1425 PCI_DMA_FROMDEVICE);
1426 intrstat = jme->shadow_regs[SHADOW_IEVE];
1427 jme->shadow_regs[SHADOW_IEVE] = 0;
1429 jme_intr_msi(jme, intrstat);
1436 jme_reset_link(struct jme_adapter *jme)
1438 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1442 jme_restart_an(struct jme_adapter *jme)
1445 unsigned long flags;
1447 spin_lock_irqsave(&jme->phy_lock, flags);
1448 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1449 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1450 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1451 spin_unlock_irqrestore(&jme->phy_lock, flags);
1455 jme_request_irq(struct jme_adapter *jme)
1458 struct net_device *netdev = jme->dev;
1459 irq_handler_t handler = jme_intr;
1460 int irq_flags = IRQF_SHARED;
1462 if (!pci_enable_msi(jme->pdev)) {
1463 jme->flags |= JME_FLAG_MSI;
1468 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1471 jeprintk(netdev->name,
1472 "Unable to request %s interrupt (return: %d)\n",
1473 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
1475 if(jme->flags & JME_FLAG_MSI) {
1476 pci_disable_msi(jme->pdev);
1477 jme->flags &= ~JME_FLAG_MSI;
1481 netdev->irq = jme->pdev->irq;
1488 jme_free_irq(struct jme_adapter *jme)
1490 free_irq(jme->pdev->irq, jme->dev);
1491 if (jme->flags & JME_FLAG_MSI) {
1492 pci_disable_msi(jme->pdev);
1493 jme->flags &= ~JME_FLAG_MSI;
1494 jme->dev->irq = jme->pdev->irq;
1499 jme_open(struct net_device *netdev)
1501 struct jme_adapter *jme = netdev_priv(netdev);
1502 int rc, timeout = 10;
1507 atomic_read(&jme->link_changing) != 1 ||
1508 atomic_read(&jme->rx_cleaning) != 1 ||
1509 atomic_read(&jme->tx_cleaning) != 1
1520 jme_reset_mac_processor(jme);
1521 JME_NAPI_ENABLE(jme);
1523 rc = jme_request_irq(jme);
1527 jme_enable_shadow(jme);
1530 if(jme->flags & JME_FLAG_SSET)
1531 jme_set_settings(netdev, &jme->old_ecmd);
1533 jme_reset_phy_processor(jme);
1535 jme_reset_link(jme);
1540 netif_stop_queue(netdev);
1541 netif_carrier_off(netdev);
1546 jme_set_100m_half(struct jme_adapter *jme)
1550 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1551 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1552 BMCR_SPEED1000 | BMCR_FULLDPLX);
1553 tmp |= BMCR_SPEED100;
1556 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1559 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1561 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1564 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1566 jme_wait_link(struct jme_adapter *jme)
1568 __u32 phylink, to = JME_WAIT_LINK_TIME;
1571 phylink = jme_linkstat_from_phy(jme);
1572 while(!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1574 phylink = jme_linkstat_from_phy(jme);
1579 jme_phy_off(struct jme_adapter *jme)
1581 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1586 jme_close(struct net_device *netdev)
1588 struct jme_adapter *jme = netdev_priv(netdev);
1590 netif_stop_queue(netdev);
1591 netif_carrier_off(netdev);
1594 jme_disable_shadow(jme);
1597 JME_NAPI_DISABLE(jme);
1599 tasklet_kill(&jme->linkch_task);
1600 tasklet_kill(&jme->txclean_task);
1601 tasklet_kill(&jme->rxclean_task);
1602 tasklet_kill(&jme->rxempty_task);
1604 jme_reset_mac_processor(jme);
1605 jme_free_rx_resources(jme);
1606 jme_free_tx_resources(jme);
1614 jme_alloc_txdesc(struct jme_adapter *jme,
1615 struct sk_buff *skb)
1617 struct jme_ring *txring = jme->txring;
1618 int idx, nr_alloc, mask = jme->tx_ring_mask;
1620 idx = txring->next_to_use;
1621 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1623 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1626 atomic_sub(nr_alloc, &txring->nr_free);
1628 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1634 jme_fill_tx_map(struct pci_dev *pdev,
1635 volatile struct txdesc *txdesc,
1636 struct jme_buffer_info *txbi,
1644 dmaaddr = pci_map_page(pdev,
1650 pci_dma_sync_single_for_device(pdev,
1657 txdesc->desc2.flags = TXFLAG_OWN;
1658 txdesc->desc2.flags |= (hidma)?TXFLAG_64BIT:0;
1659 txdesc->desc2.datalen = cpu_to_le16(len);
1660 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1661 txdesc->desc2.bufaddrl = cpu_to_le32(
1662 (__u64)dmaaddr & 0xFFFFFFFFUL);
1664 txbi->mapping = dmaaddr;
1669 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1671 struct jme_ring *txring = jme->txring;
1672 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
1673 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1674 __u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1675 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1676 int mask = jme->tx_ring_mask;
1677 struct skb_frag_struct *frag;
1680 for(i = 0 ; i < nr_frags ; ++i) {
1681 frag = &skb_shinfo(skb)->frags[i];
1682 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1683 ctxbi = txbi + ((idx + i + 2) & (mask));
1685 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1686 frag->page_offset, frag->size, hidma);
1689 len = skb_is_nonlinear(skb)?skb_headlen(skb):skb->len;
1690 ctxdesc = txdesc + ((idx + 1) & (mask));
1691 ctxbi = txbi + ((idx + 1) & (mask));
1692 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1693 offset_in_page(skb->data), len, hidma);
1698 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1700 if(unlikely(skb_shinfo(skb)->gso_size &&
1701 skb_header_cloned(skb) &&
1702 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1711 jme_tx_tso(struct sk_buff *skb,
1712 volatile __u16 *mss, __u8 *flags)
1714 if((*mss = (skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT))) {
1715 *flags |= TXFLAG_LSEN;
1717 if(skb->protocol == __constant_htons(ETH_P_IP)) {
1718 struct iphdr *iph = ip_hdr(skb);
1721 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1727 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1729 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1742 jme_tx_csum(struct sk_buff *skb, __u8 *flags)
1744 if(skb->ip_summed == CHECKSUM_PARTIAL) {
1747 switch (skb->protocol) {
1748 case __constant_htons(ETH_P_IP):
1749 ip_proto = ip_hdr(skb)->protocol;
1751 case __constant_htons(ETH_P_IPV6):
1752 ip_proto = ipv6_hdr(skb)->nexthdr;
1761 *flags |= TXFLAG_TCPCS;
1764 *flags |= TXFLAG_UDPCS;
1767 jeprintk("jme", "Error upper layer protocol.\n");
1773 __always_inline static void
1774 jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
1776 if(vlan_tx_tag_present(skb)) {
1777 vlan_dbg("jme", "Tag found!(%04x)\n", vlan_tx_tag_get(skb));
1778 *flags |= TXFLAG_TAGON;
1779 *vlan = vlan_tx_tag_get(skb);
1784 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1786 struct jme_ring *txring = jme->txring;
1787 volatile struct txdesc *txdesc;
1788 struct jme_buffer_info *txbi;
1791 txdesc = (volatile struct txdesc*)txring->desc + idx;
1792 txbi = txring->bufinf + idx;
1798 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1800 * Set OWN bit at final.
1801 * When kernel transmit faster than NIC.
1802 * And NIC trying to send this descriptor before we tell
1803 * it to start sending this TX queue.
1804 * Other fields are already filled correctly.
1807 flags = TXFLAG_OWN | TXFLAG_INT;
1808 //Set checksum flags while not tso
1809 if(jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1810 jme_tx_csum(skb, &flags);
1811 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1812 txdesc->desc1.flags = flags;
1814 * Set tx buffer info after telling NIC to send
1815 * For better tx_clean timing
1818 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1820 txbi->len = skb->len;
1821 if(!(txbi->start_xmit = jiffies))
1822 txbi->start_xmit = (0UL-1);
1828 jme_stop_queue_if_full(struct jme_adapter *jme)
1830 struct jme_ring *txring = jme->txring;
1831 struct jme_buffer_info *txbi = txring->bufinf;
1833 txbi += atomic_read(&txring->next_to_clean);
1836 if(unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1837 netif_stop_queue(jme->dev);
1838 queue_dbg(jme->dev->name, "TX Queue Paused.\n");
1840 if (atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold)) {
1841 netif_wake_queue(jme->dev);
1842 queue_dbg(jme->dev->name, "TX Queue Fast Waked.\n");
1846 if(unlikely( txbi->start_xmit &&
1847 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1849 netif_stop_queue(jme->dev);
1850 queue_dbg(jme->dev->name, "TX Queue Stopped @(%lu).\n", jiffies);
1855 * This function is already protected by netif_tx_lock()
1858 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1860 struct jme_adapter *jme = netdev_priv(netdev);
1863 if(skb_shinfo(skb)->nr_frags) {
1864 tx_dbg(netdev->name, "Frags: %d Headlen: %d Len: %d MSS: %d Sum:%d\n",
1865 skb_shinfo(skb)->nr_frags,
1868 skb_shinfo(skb)->gso_size,
1872 if(unlikely(jme_expand_header(jme, skb))) {
1873 ++(NET_STAT(jme).tx_dropped);
1874 return NETDEV_TX_OK;
1877 idx = jme_alloc_txdesc(jme, skb);
1879 if(unlikely(idx<0)) {
1880 netif_stop_queue(netdev);
1881 jeprintk(netdev->name,
1882 "BUG! Tx ring full when queue awake!\n");
1884 return NETDEV_TX_BUSY;
1887 jme_map_tx_skb(jme, skb, idx);
1888 jme_fill_first_tx_desc(jme, skb, idx);
1890 tx_dbg(jme->dev->name, "Xmit: %d+%d @(%lu)\n",
1891 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1893 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1894 TXCS_SELECT_QUEUE0 |
1897 netdev->trans_start = jiffies;
1899 jme_stop_queue_if_full(jme);
1901 return NETDEV_TX_OK;
1905 jme_set_macaddr(struct net_device *netdev, void *p)
1907 struct jme_adapter *jme = netdev_priv(netdev);
1908 struct sockaddr *addr = p;
1911 if(netif_running(netdev))
1914 spin_lock(&jme->macaddr_lock);
1915 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1917 val = (addr->sa_data[3] & 0xff) << 24 |
1918 (addr->sa_data[2] & 0xff) << 16 |
1919 (addr->sa_data[1] & 0xff) << 8 |
1920 (addr->sa_data[0] & 0xff);
1921 jwrite32(jme, JME_RXUMA_LO, val);
1922 val = (addr->sa_data[5] & 0xff) << 8 |
1923 (addr->sa_data[4] & 0xff);
1924 jwrite32(jme, JME_RXUMA_HI, val);
1925 spin_unlock(&jme->macaddr_lock);
1931 jme_set_multi(struct net_device *netdev)
1933 struct jme_adapter *jme = netdev_priv(netdev);
1934 u32 mc_hash[2] = {};
1936 unsigned long flags;
1938 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1940 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1942 if (netdev->flags & IFF_PROMISC) {
1943 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1945 else if (netdev->flags & IFF_ALLMULTI) {
1946 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1948 else if(netdev->flags & IFF_MULTICAST) {
1949 struct dev_mc_list *mclist;
1952 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1953 for (i = 0, mclist = netdev->mc_list;
1954 mclist && i < netdev->mc_count;
1955 ++i, mclist = mclist->next) {
1957 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1958 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1961 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1962 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1966 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1968 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1972 jme_change_mtu(struct net_device *netdev, int new_mtu)
1974 struct jme_adapter *jme = netdev_priv(netdev);
1976 if(new_mtu == jme->old_mtu)
1979 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1980 ((new_mtu) < IPV6_MIN_MTU))
1983 if(new_mtu > 4000) {
1984 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1985 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1986 jme_restart_rx_engine(jme);
1989 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1990 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1991 jme_restart_rx_engine(jme);
1994 if(new_mtu > 1900) {
1995 netdev->features &= ~(NETIF_F_HW_CSUM |
2000 if(jme->flags & JME_FLAG_TXCSUM)
2001 netdev->features |= NETIF_F_HW_CSUM;
2002 if(jme->flags & JME_FLAG_TSO)
2003 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2006 netdev->mtu = new_mtu;
2007 jme_reset_link(jme);
2013 jme_tx_timeout(struct net_device *netdev)
2015 struct jme_adapter *jme = netdev_priv(netdev);
2018 jme_reset_phy_processor(jme);
2019 if(jme->flags & JME_FLAG_SSET)
2020 jme_set_settings(netdev, &jme->old_ecmd);
2023 * Force to Reset the link again
2025 jme_reset_link(jme);
2029 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2031 struct jme_adapter *jme = netdev_priv(netdev);
2037 jme_get_drvinfo(struct net_device *netdev,
2038 struct ethtool_drvinfo *info)
2040 struct jme_adapter *jme = netdev_priv(netdev);
2042 strcpy(info->driver, DRV_NAME);
2043 strcpy(info->version, DRV_VERSION);
2044 strcpy(info->bus_info, pci_name(jme->pdev));
2048 jme_get_regs_len(struct net_device *netdev)
2054 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
2058 for(i = 0 ; i < len ; i += 4)
2059 p[i >> 2] = jread32(jme, reg + i);
2063 mdio_memcpy(struct jme_adapter *jme, __u32 *p, int reg_nr)
2066 __u16 *p16 = (__u16*)p;
2068 for(i = 0 ; i < reg_nr ; ++i)
2069 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2073 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2075 struct jme_adapter *jme = netdev_priv(netdev);
2076 __u32 *p32 = (__u32*)p;
2078 memset(p, 0xFF, JME_REG_LEN);
2081 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2084 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2087 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2090 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2093 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2097 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2099 struct jme_adapter *jme = netdev_priv(netdev);
2101 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2102 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2104 if(jme->flags & JME_FLAG_POLL) {
2105 ecmd->use_adaptive_rx_coalesce = false;
2106 ecmd->rx_coalesce_usecs = 0;
2107 ecmd->rx_max_coalesced_frames = 0;
2111 ecmd->use_adaptive_rx_coalesce = true;
2113 switch(jme->dpi.cur) {
2115 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2116 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2119 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2120 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2123 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2124 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2134 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2136 struct jme_adapter *jme = netdev_priv(netdev);
2137 struct dynpcc_info *dpi = &(jme->dpi);
2139 if(netif_running(netdev))
2142 if(ecmd->use_adaptive_rx_coalesce
2143 && (jme->flags & JME_FLAG_POLL)) {
2144 jme->flags &= ~JME_FLAG_POLL;
2145 jme->jme_rx = netif_rx;
2146 jme->jme_vlan_rx = vlan_hwaccel_rx;
2148 dpi->attempt = PCC_P1;
2150 jme_set_rx_pcc(jme, PCC_P1);
2151 jme_interrupt_mode(jme);
2153 else if(!(ecmd->use_adaptive_rx_coalesce)
2154 && !(jme->flags & JME_FLAG_POLL)) {
2155 jme->flags |= JME_FLAG_POLL;
2156 jme->jme_rx = netif_receive_skb;
2157 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2158 jme_interrupt_mode(jme);
2165 jme_get_pauseparam(struct net_device *netdev,
2166 struct ethtool_pauseparam *ecmd)
2168 struct jme_adapter *jme = netdev_priv(netdev);
2169 unsigned long flags;
2172 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2173 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2175 spin_lock_irqsave(&jme->phy_lock, flags);
2176 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2177 spin_unlock_irqrestore(&jme->phy_lock, flags);
2180 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2184 jme_set_pauseparam(struct net_device *netdev,
2185 struct ethtool_pauseparam *ecmd)
2187 struct jme_adapter *jme = netdev_priv(netdev);
2188 unsigned long flags;
2191 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
2192 (ecmd->tx_pause != 0)) {
2195 jme->reg_txpfc |= TXPFC_PF_EN;
2197 jme->reg_txpfc &= ~TXPFC_PF_EN;
2199 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2202 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2203 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
2204 (ecmd->rx_pause != 0)) {
2207 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2209 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2211 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2213 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2215 spin_lock_irqsave(&jme->phy_lock, flags);
2216 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2217 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
2218 (ecmd->autoneg != 0)) {
2221 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2223 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2225 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2226 MII_ADVERTISE, val);
2228 spin_unlock_irqrestore(&jme->phy_lock, flags);
2234 jme_get_wol(struct net_device *netdev,
2235 struct ethtool_wolinfo *wol)
2237 struct jme_adapter *jme = netdev_priv(netdev);
2239 wol->supported = WAKE_MAGIC | WAKE_PHY;
2243 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2244 wol->wolopts |= WAKE_PHY;
2246 if(jme->reg_pmcs & PMCS_MFEN)
2247 wol->wolopts |= WAKE_MAGIC;
2252 jme_set_wol(struct net_device *netdev,
2253 struct ethtool_wolinfo *wol)
2255 struct jme_adapter *jme = netdev_priv(netdev);
2257 if(wol->wolopts & (WAKE_MAGICSECURE |
2266 if(wol->wolopts & WAKE_PHY)
2267 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2269 if(wol->wolopts & WAKE_MAGIC)
2270 jme->reg_pmcs |= PMCS_MFEN;
2277 jme_get_settings(struct net_device *netdev,
2278 struct ethtool_cmd *ecmd)
2280 struct jme_adapter *jme = netdev_priv(netdev);
2282 unsigned long flags;
2284 spin_lock_irqsave(&jme->phy_lock, flags);
2285 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2286 spin_unlock_irqrestore(&jme->phy_lock, flags);
2291 jme_set_settings(struct net_device *netdev,
2292 struct ethtool_cmd *ecmd)
2294 struct jme_adapter *jme = netdev_priv(netdev);
2296 unsigned long flags;
2298 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2301 if(jme->mii_if.force_media &&
2302 ecmd->autoneg != AUTONEG_ENABLE &&
2303 (jme->mii_if.full_duplex != ecmd->duplex))
2306 spin_lock_irqsave(&jme->phy_lock, flags);
2307 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2308 spin_unlock_irqrestore(&jme->phy_lock, flags);
2311 jme_reset_link(jme);
2314 jme->flags |= JME_FLAG_SSET;
2315 jme->old_ecmd = *ecmd;
2322 jme_get_link(struct net_device *netdev)
2324 struct jme_adapter *jme = netdev_priv(netdev);
2325 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2329 jme_get_rx_csum(struct net_device *netdev)
2331 struct jme_adapter *jme = netdev_priv(netdev);
2333 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2337 jme_set_rx_csum(struct net_device *netdev, u32 on)
2339 struct jme_adapter *jme = netdev_priv(netdev);
2340 unsigned long flags;
2342 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2344 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2346 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2347 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2348 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2354 jme_set_tx_csum(struct net_device *netdev, u32 on)
2356 struct jme_adapter *jme = netdev_priv(netdev);
2359 jme->flags |= JME_FLAG_TXCSUM;
2360 if(netdev->mtu <= 1900)
2361 netdev->features |= NETIF_F_HW_CSUM;
2364 jme->flags &= ~JME_FLAG_TXCSUM;
2365 netdev->features &= ~NETIF_F_HW_CSUM;
2372 jme_set_tso(struct net_device *netdev, u32 on)
2374 struct jme_adapter *jme = netdev_priv(netdev);
2377 jme->flags |= JME_FLAG_TSO;
2378 if(netdev->mtu <= 1900)
2379 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2382 jme->flags &= ~JME_FLAG_TSO;
2383 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2390 jme_nway_reset(struct net_device *netdev)
2392 struct jme_adapter *jme = netdev_priv(netdev);
2393 jme_restart_an(jme);
2398 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2403 val = jread32(jme, JME_SMBCSR);
2404 to = JME_SMB_BUSY_TIMEOUT;
2405 while((val & SMBCSR_BUSY) && --to) {
2407 val = jread32(jme, JME_SMBCSR);
2410 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2414 jwrite32(jme, JME_SMBINTF,
2415 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2416 SMBINTF_HWRWN_READ |
2419 val = jread32(jme, JME_SMBINTF);
2420 to = JME_SMB_BUSY_TIMEOUT;
2421 while((val & SMBINTF_HWCMD) && --to) {
2423 val = jread32(jme, JME_SMBINTF);
2426 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2430 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2434 jme_smb_write(struct jme_adapter *jme, unsigned int addr, __u8 data)
2439 val = jread32(jme, JME_SMBCSR);
2440 to = JME_SMB_BUSY_TIMEOUT;
2441 while((val & SMBCSR_BUSY) && --to) {
2443 val = jread32(jme, JME_SMBCSR);
2446 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2450 jwrite32(jme, JME_SMBINTF,
2451 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2452 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2453 SMBINTF_HWRWN_WRITE |
2456 val = jread32(jme, JME_SMBINTF);
2457 to = JME_SMB_BUSY_TIMEOUT;
2458 while((val & SMBINTF_HWCMD) && --to) {
2460 val = jread32(jme, JME_SMBINTF);
2463 jeprintk(jme->dev->name, "SMB Bus Busy.\n");
2471 jme_get_eeprom_len(struct net_device *netdev)
2473 struct jme_adapter *jme = netdev_priv(netdev);
2475 val = jread32(jme, JME_SMBCSR);
2476 return (val & SMBCSR_EEPROMD)?JME_SMB_LEN:0;
2480 jme_get_eeprom(struct net_device *netdev,
2481 struct ethtool_eeprom *eeprom, u8 *data)
2483 struct jme_adapter *jme = netdev_priv(netdev);
2484 int i, offset = eeprom->offset, len = eeprom->len;
2487 * ethtool will check the boundary for us
2489 eeprom->magic = JME_EEPROM_MAGIC;
2490 for(i = 0 ; i < len ; ++i)
2491 data[i] = jme_smb_read(jme, i + offset);
2497 jme_set_eeprom(struct net_device *netdev,
2498 struct ethtool_eeprom *eeprom, u8 *data)
2500 struct jme_adapter *jme = netdev_priv(netdev);
2501 int i, offset = eeprom->offset, len = eeprom->len;
2503 if (eeprom->magic != JME_EEPROM_MAGIC)
2507 * ethtool will check the boundary for us
2509 for(i = 0 ; i < len ; ++i)
2510 jme_smb_write(jme, i + offset, data[i]);
2515 static const struct ethtool_ops jme_ethtool_ops = {
2516 .get_drvinfo = jme_get_drvinfo,
2517 .get_regs_len = jme_get_regs_len,
2518 .get_regs = jme_get_regs,
2519 .get_coalesce = jme_get_coalesce,
2520 .set_coalesce = jme_set_coalesce,
2521 .get_pauseparam = jme_get_pauseparam,
2522 .set_pauseparam = jme_set_pauseparam,
2523 .get_wol = jme_get_wol,
2524 .set_wol = jme_set_wol,
2525 .get_settings = jme_get_settings,
2526 .set_settings = jme_set_settings,
2527 .get_link = jme_get_link,
2528 .get_rx_csum = jme_get_rx_csum,
2529 .set_rx_csum = jme_set_rx_csum,
2530 .set_tx_csum = jme_set_tx_csum,
2531 .set_tso = jme_set_tso,
2532 .set_sg = ethtool_op_set_sg,
2533 .nway_reset = jme_nway_reset,
2534 .get_eeprom_len = jme_get_eeprom_len,
2535 .get_eeprom = jme_get_eeprom,
2536 .set_eeprom = jme_set_eeprom,
2540 jme_pci_dma64(struct pci_dev *pdev)
2542 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2543 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2544 dprintk("jme", "64Bit DMA Selected.\n");
2548 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2549 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2550 dprintk("jme", "40Bit DMA Selected.\n");
2554 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2555 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2556 dprintk("jme", "32Bit DMA Selected.\n");
2563 __always_inline static void
2564 jme_phy_init(struct jme_adapter *jme)
2568 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2569 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2572 __always_inline static void
2573 jme_set_gmii(struct jme_adapter *jme)
2575 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
2579 jme_check_hw_ver(struct jme_adapter *jme)
2583 chipmode = jread32(jme, JME_CHIPMODE);
2585 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2586 jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
2589 static int __devinit
2590 jme_init_one(struct pci_dev *pdev,
2591 const struct pci_device_id *ent)
2593 int rc = 0, using_dac, i;
2594 struct net_device *netdev;
2595 struct jme_adapter *jme;
2599 * set up PCI device basics
2601 rc = pci_enable_device(pdev);
2603 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2607 using_dac = jme_pci_dma64(pdev);
2609 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2611 goto err_out_disable_pdev;
2614 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2615 printk(KERN_ERR PFX "No PCI resource region found.\n");
2617 goto err_out_disable_pdev;
2620 rc = pci_request_regions(pdev, DRV_NAME);
2622 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2623 goto err_out_disable_pdev;
2626 pci_set_master(pdev);
2629 * alloc and init net device
2631 netdev = alloc_etherdev(sizeof(*jme));
2633 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
2635 goto err_out_release_regions;
2637 netdev->open = jme_open;
2638 netdev->stop = jme_close;
2639 netdev->hard_start_xmit = jme_start_xmit;
2640 netdev->set_mac_address = jme_set_macaddr;
2641 netdev->set_multicast_list = jme_set_multi;
2642 netdev->change_mtu = jme_change_mtu;
2643 netdev->ethtool_ops = &jme_ethtool_ops;
2644 netdev->tx_timeout = jme_tx_timeout;
2645 netdev->watchdog_timeo = TX_TIMEOUT;
2646 netdev->vlan_rx_register = jme_vlan_rx_register;
2647 NETDEV_GET_STATS(netdev, &jme_get_stats);
2648 netdev->features = NETIF_F_HW_CSUM |
2652 NETIF_F_HW_VLAN_TX |
2655 netdev->features |= NETIF_F_HIGHDMA;
2657 SET_NETDEV_DEV(netdev, &pdev->dev);
2658 pci_set_drvdata(pdev, netdev);
2663 jme = netdev_priv(netdev);
2666 jme->jme_rx = netif_rx;
2667 jme->jme_vlan_rx = vlan_hwaccel_rx;
2668 jme->old_mtu = netdev->mtu = 1500;
2670 jme->tx_ring_size = 1 << 10;
2671 jme->tx_ring_mask = jme->tx_ring_size - 1;
2672 jme->tx_wake_threshold = 1 << 9;
2673 jme->rx_ring_size = 1 << 9;
2674 jme->rx_ring_mask = jme->rx_ring_size - 1;
2675 jme->regs = ioremap(pci_resource_start(pdev, 0),
2676 pci_resource_len(pdev, 0));
2678 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
2680 goto err_out_free_netdev;
2682 jme->shadow_regs = pci_alloc_consistent(pdev,
2683 sizeof(__u32) * SHADOW_REG_NR,
2684 &(jme->shadow_dma));
2685 if (!(jme->shadow_regs)) {
2686 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
2691 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2693 spin_lock_init(&jme->phy_lock);
2694 spin_lock_init(&jme->macaddr_lock);
2695 spin_lock_init(&jme->rxmcs_lock);
2697 atomic_set(&jme->link_changing, 1);
2698 atomic_set(&jme->rx_cleaning, 1);
2699 atomic_set(&jme->tx_cleaning, 1);
2700 atomic_set(&jme->rx_empty, 1);
2702 tasklet_init(&jme->pcc_task,
2704 (unsigned long) jme);
2705 tasklet_init(&jme->linkch_task,
2706 &jme_link_change_tasklet,
2707 (unsigned long) jme);
2708 tasklet_init(&jme->txclean_task,
2709 &jme_tx_clean_tasklet,
2710 (unsigned long) jme);
2711 tasklet_init(&jme->rxclean_task,
2712 &jme_rx_clean_tasklet,
2713 (unsigned long) jme);
2714 tasklet_init(&jme->rxempty_task,
2715 &jme_rx_empty_tasklet,
2716 (unsigned long) jme);
2717 jme->dpi.cur = PCC_P1;
2719 if(pdev->device == JME_GE_DEVICE)
2720 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2722 jme->reg_ghc = GHC_DPX | GHC_SPEED_100M;
2723 jme->reg_rxcs = RXCS_DEFAULT;
2724 jme->reg_rxmcs = RXMCS_DEFAULT;
2726 jme->reg_pmcs = PMCS_MFEN;
2727 jme->flags = JME_FLAG_TXCSUM | JME_FLAG_TSO;
2730 * Get Max Read Req Size from PCI Config Space
2732 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2735 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2738 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2741 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2747 * Must check before reset_mac_processor
2749 jme_check_hw_ver(jme);
2750 jme->mii_if.dev = netdev;
2752 jme->mii_if.phy_id = 0;
2753 for(i = 1 ; i < 32 ; ++i) {
2754 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2755 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2756 if(bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2757 jme->mii_if.phy_id = i;
2762 if(!jme->mii_if.phy_id) {
2764 printk(KERN_ERR PFX "Can not find phy_id.\n");
2765 goto err_out_free_shadow;
2768 jme->reg_ghc |= GHC_LINK_POLL;
2771 jme->mii_if.phy_id = 1;
2773 if(pdev->device == JME_GE_DEVICE)
2774 jme->mii_if.supports_gmii = true;
2776 jme->mii_if.supports_gmii = false;
2777 jme->mii_if.mdio_read = jme_mdio_read;
2778 jme->mii_if.mdio_write = jme_mdio_write;
2788 * Reset MAC processor and reload EEPROM for MAC Address
2790 jme_reset_mac_processor(jme);
2791 rc = jme_reload_eeprom(jme);
2794 "Reload eeprom for reading MAC Address error.\n");
2795 goto err_out_free_shadow;
2797 jme_load_macaddr(netdev);
2801 * Tell stack that we are not ready to work until open()
2803 netif_carrier_off(netdev);
2804 netif_stop_queue(netdev);
2809 rc = register_netdev(netdev);
2811 printk(KERN_ERR PFX "Cannot register net device.\n");
2812 goto err_out_free_shadow;
2815 jprintk(netdev->name,
2816 "JMC250 gigabit%s ver:%u eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2817 (jme->fpgaver != 0)?" (FPGA)":"",
2818 (jme->fpgaver != 0)?jme->fpgaver:jme->chipver,
2819 netdev->dev_addr[0],
2820 netdev->dev_addr[1],
2821 netdev->dev_addr[2],
2822 netdev->dev_addr[3],
2823 netdev->dev_addr[4],
2824 netdev->dev_addr[5]);
2828 err_out_free_shadow:
2829 pci_free_consistent(pdev,
2830 sizeof(__u32) * SHADOW_REG_NR,
2835 err_out_free_netdev:
2836 pci_set_drvdata(pdev, NULL);
2837 free_netdev(netdev);
2838 err_out_release_regions:
2839 pci_release_regions(pdev);
2840 err_out_disable_pdev:
2841 pci_disable_device(pdev);
2846 static void __devexit
2847 jme_remove_one(struct pci_dev *pdev)
2849 struct net_device *netdev = pci_get_drvdata(pdev);
2850 struct jme_adapter *jme = netdev_priv(netdev);
2852 unregister_netdev(netdev);
2853 pci_free_consistent(pdev,
2854 sizeof(__u32) * SHADOW_REG_NR,
2858 pci_set_drvdata(pdev, NULL);
2859 free_netdev(netdev);
2860 pci_release_regions(pdev);
2861 pci_disable_device(pdev);
2866 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2868 struct net_device *netdev = pci_get_drvdata(pdev);
2869 struct jme_adapter *jme = netdev_priv(netdev);
2872 atomic_dec(&jme->link_changing);
2874 netif_device_detach(netdev);
2875 netif_stop_queue(netdev);
2877 //jme_free_irq(jme);
2879 while(--timeout > 0 &&
2881 atomic_read(&jme->rx_cleaning) != 1 ||
2882 atomic_read(&jme->tx_cleaning) != 1
2887 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2890 jme_disable_shadow(jme);
2892 if(netif_carrier_ok(netdev)) {
2893 if(jme->flags & JME_FLAG_POLL)
2894 jme_polling_mode(jme);
2896 jme_stop_pcc_timer(jme);
2897 jme_reset_mac_processor(jme);
2898 jme_free_rx_resources(jme);
2899 jme_free_tx_resources(jme);
2900 netif_carrier_off(netdev);
2905 pci_save_state(pdev);
2907 jme_set_100m_half(jme);
2909 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2912 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2913 pci_enable_wake(pdev, PCI_D1, true);
2914 pci_enable_wake(pdev, PCI_D3hot, true);
2915 pci_enable_wake(pdev, PCI_D3cold, true);
2919 pci_enable_wake(pdev, PCI_D1, false);
2920 pci_enable_wake(pdev, PCI_D3hot, false);
2921 pci_enable_wake(pdev, PCI_D3cold, false);
2923 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2929 jme_resume(struct pci_dev *pdev)
2931 struct net_device *netdev = pci_get_drvdata(pdev);
2932 struct jme_adapter *jme = netdev_priv(netdev);
2935 pci_restore_state(pdev);
2937 if(jme->flags & JME_FLAG_SSET)
2938 jme_set_settings(netdev, &jme->old_ecmd);
2940 jme_reset_phy_processor(jme);
2942 jme_reset_mac_processor(jme);
2943 jme_enable_shadow(jme);
2944 //jme_request_irq(jme);
2946 netif_device_attach(netdev);
2948 atomic_inc(&jme->link_changing);
2950 jme_reset_link(jme);
2955 static struct pci_device_id jme_pci_tbl[] = {
2956 { PCI_VDEVICE(JMICRON, JME_GE_DEVICE) },
2957 { PCI_VDEVICE(JMICRON, JME_FE_DEVICE) },
2961 static struct pci_driver jme_driver = {
2963 .id_table = jme_pci_tbl,
2964 .probe = jme_init_one,
2965 .remove = __devexit_p(jme_remove_one),
2967 .suspend = jme_suspend,
2968 .resume = jme_resume,
2969 #endif /* CONFIG_PM */
2973 jme_init_module(void)
2975 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2976 "driver version %s\n", DRV_VERSION);
2977 return pci_register_driver(&jme_driver);
2981 jme_cleanup_module(void)
2983 pci_unregister_driver(&jme_driver);
2986 module_init(jme_init_module);
2987 module_exit(jme_cleanup_module);
2989 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2990 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2991 MODULE_LICENSE("GPL");
2992 MODULE_VERSION(DRV_VERSION);
2993 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);