2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
62 #ifndef JME_NEW_PM_API
64 jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
72 pci_pme_active(jme->pdev, enable);
78 jme_mdio_read(struct net_device *netdev, int phy, int reg)
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
108 jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
111 struct jme_adapter *jme = netdev_priv(netdev);
114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
130 jme_reset_phy_processor(struct jme_adapter *jme)
134 jme_mdio_write(jme->dev,
136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
140 jme_mdio_write(jme->dev,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
145 val = jme_mdio_read(jme->dev,
149 jme_mdio_write(jme->dev,
151 MII_BMCR, val | BMCR_RESET);
155 jme_setup_wakeup_frame(struct jme_adapter *jme,
156 const u32 *mask, u32 crc, int fnr)
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
165 jwrite32(jme, JME_WFODP, crc);
171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
176 jwrite32(jme, JME_WFODP, mask[i]);
182 jme_mac_rxclk_off(struct jme_adapter *jme)
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
189 jme_mac_rxclk_on(struct jme_adapter *jme)
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
196 jme_mac_txclk_off(struct jme_adapter *jme)
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203 jme_mac_txclk_on(struct jme_adapter *jme)
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
214 jme_reset_ghc_speed(struct jme_adapter *jme)
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
221 jme_reset_250A2_workaround(struct jme_adapter *jme)
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
229 jme_assert_ghc_reset(struct jme_adapter *jme)
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
236 jme_clear_ghc_reset(struct jme_adapter *jme)
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
243 jme_reset_mac_processor(struct jme_adapter *jme)
245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
246 u32 crc = 0xCDCDCDCD;
250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
256 jme_assert_ghc_reset(jme);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
261 jme_clear_ghc_reset(jme);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
281 jme_setup_wakeup_frame(jme, mask, crc, i);
283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
290 jme_clear_pm(struct jme_adapter *jme)
292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
296 jme_reload_eeprom(struct jme_adapter *jme)
301 val = jread32(jme, JME_SMBCSR);
303 if (val & SMBCSR_EEPROMD) {
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
317 pr_err("eeprom reload timeout\n");
326 jme_load_macaddr(struct net_device *netdev)
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
332 spin_lock_bh(&jme->macaddr_lock);
333 val = jread32(jme, JME_RXUMA_LO);
334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
338 val = jread32(jme, JME_RXUMA_HI);
339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
346 jme_set_rx_pcc(struct jme_adapter *jme, int p)
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
379 jme_start_irq(struct jme_adapter *jme)
381 register struct dynpcc_info *dpi = &(jme->dpi);
383 jme_set_rx_pcc(jme, PCC_P1);
385 dpi->attempt = PCC_P1;
388 jwrite32(jme, JME_PCCTX,
389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
401 jme_stop_irq(struct jme_adapter *jme)
406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
410 jme_linkstat_from_phy(struct jme_adapter *jme)
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
416 if (bmsr & BMSR_ANCOMP)
417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
423 jme_set_phyfifo_5level(struct jme_adapter *jme)
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
429 jme_set_phyfifo_8level(struct jme_adapter *jme)
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
435 jme_check_link(struct net_device *netdev, int testonly)
437 struct jme_adapter *jme = netdev_priv(netdev);
438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
445 phylink = jme_linkstat_from_phy(jme);
447 phylink = jread32(jme, JME_PHY_LINK);
449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
455 phylink = PHY_LINK_UP;
457 bmcr = jme_mdio_read(jme->dev,
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
471 strcat(linkmsg, "Forced: ");
474 * Keep polling for speed/duplex resolve complete
476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
482 phylink = jme_linkstat_from_phy(jme);
484 phylink = jread32(jme, JME_PHY_LINK);
487 pr_err("Waiting speed resolve timeout\n");
489 strcat(linkmsg, "ANed: ");
492 if (jme->phylink == phylink) {
499 jme->phylink = phylink;
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
507 jme->reg_ghc |= GHC_SPEED_10M;
508 strcat(linkmsg, "10 Mbps, ");
510 case PHY_LINK_SPEED_100M:
511 jme->reg_ghc |= GHC_SPEED_100M;
512 strcat(linkmsg, "100 Mbps, ");
514 case PHY_LINK_SPEED_1000M:
515 jme->reg_ghc |= GHC_SPEED_1000M;
516 strcat(linkmsg, "1000 Mbps, ");
522 if (phylink & PHY_LINK_DUPLEX) {
523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
525 jme->reg_ghc |= GHC_DPX;
527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
534 jwrite32(jme, JME_GHC, jme->reg_ghc);
536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
539 if (!(phylink & PHY_LINK_DUPLEX))
540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
543 jme_set_phyfifo_8level(jme);
544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
546 case PHY_LINK_SPEED_100M:
547 jme_set_phyfifo_5level(jme);
548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
550 case PHY_LINK_SPEED_1000M:
551 jme_set_phyfifo_8level(jme);
557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
566 netif_carrier_on(netdev);
571 netif_info(jme, link, jme->dev, "Link is down\n");
573 netif_carrier_off(netdev);
581 jme_setup_tx_resources(struct jme_adapter *jme)
583 struct jme_ring *txring = &(jme->txring[0]);
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
599 txring->next_to_use = 0;
600 atomic_set(&txring->next_to_clean, 0);
601 atomic_set(&txring->nr_free, jme->tx_ring_size);
603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
609 * Initialize Transmit Descriptors
611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
612 memset(txring->bufinf, 0,
613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
625 txring->dmaalloc = 0;
627 txring->bufinf = NULL;
633 jme_free_tx_resources(struct jme_adapter *jme)
636 struct jme_ring *txring = &(jme->txring[0]);
637 struct jme_buffer_info *txbi;
640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
644 dev_kfree_skb(txbi->skb);
650 txbi->start_xmit = 0;
652 kfree(txring->bufinf);
655 dma_free_coherent(&(jme->pdev->dev),
656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
660 txring->alloc = NULL;
662 txring->dmaalloc = 0;
664 txring->bufinf = NULL;
666 txring->next_to_use = 0;
667 atomic_set(&txring->next_to_clean, 0);
668 atomic_set(&txring->nr_free, 0);
672 jme_enable_tx_engine(struct jme_adapter *jme)
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
681 * Setup TX Queue 0 DMA Bass Address
683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
688 * Setup TX Descptor Count
690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
701 * Start clock for TX MAC Processor
703 jme_mac_txclk_on(jme);
707 jme_restart_tx_engine(struct jme_adapter *jme)
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
718 jme_disable_tx_engine(struct jme_adapter *jme)
726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
729 val = jread32(jme, JME_TXCS);
730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
732 val = jread32(jme, JME_TXCS);
737 pr_err("Disable TX engine timeout\n");
740 * Stop clock for TX MAC Processor
742 jme_mac_txclk_off(jme);
746 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
748 struct jme_ring *rxring = &(jme->rxring[0]);
749 register struct rxdesc *rxdesc = rxring->desc;
750 struct jme_buffer_info *rxbi = rxring->bufinf;
756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
760 if (jme->dev->features & NETIF_F_HIGHDMA)
761 rxdesc->desc1.flags = RXFLAG_64BIT;
763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
767 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
769 struct jme_ring *rxring = &(jme->rxring[0]);
770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
773 skb = netdev_alloc_skb(jme->dev,
774 jme->dev->mtu + RX_EXTRA_LEN);
777 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
782 rxbi->len = skb_tailroom(skb);
783 rxbi->mapping = pci_map_page(jme->pdev,
784 virt_to_page(skb->data),
785 offset_in_page(skb->data),
793 jme_free_rx_buf(struct jme_adapter *jme, int i)
795 struct jme_ring *rxring = &(jme->rxring[0]);
796 struct jme_buffer_info *rxbi = rxring->bufinf;
800 pci_unmap_page(jme->pdev,
804 dev_kfree_skb(rxbi->skb);
812 jme_free_rx_resources(struct jme_adapter *jme)
815 struct jme_ring *rxring = &(jme->rxring[0]);
818 if (rxring->bufinf) {
819 for (i = 0 ; i < jme->rx_ring_size ; ++i)
820 jme_free_rx_buf(jme, i);
821 kfree(rxring->bufinf);
824 dma_free_coherent(&(jme->pdev->dev),
825 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
828 rxring->alloc = NULL;
830 rxring->dmaalloc = 0;
832 rxring->bufinf = NULL;
834 rxring->next_to_use = 0;
835 atomic_set(&rxring->next_to_clean, 0);
839 jme_setup_rx_resources(struct jme_adapter *jme)
842 struct jme_ring *rxring = &(jme->rxring[0]);
844 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
856 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
857 rxring->next_to_use = 0;
858 atomic_set(&rxring->next_to_clean, 0);
860 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
861 jme->rx_ring_size, GFP_ATOMIC);
862 if (unlikely(!(rxring->bufinf)))
863 goto err_free_rxring;
866 * Initiallize Receive Descriptors
868 memset(rxring->bufinf, 0,
869 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
870 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
871 if (unlikely(jme_make_new_rx_buf(jme, i))) {
872 jme_free_rx_resources(jme);
876 jme_set_clean_rxdesc(jme, i);
882 dma_free_coherent(&(jme->pdev->dev),
883 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
888 rxring->dmaalloc = 0;
890 rxring->bufinf = NULL;
896 jme_enable_rx_engine(struct jme_adapter *jme)
901 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
906 * Setup RX DMA Bass Address
908 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
909 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
910 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
913 * Setup RX Descriptor Count
915 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
918 * Setup Unicast Filter
920 jme_set_unicastaddr(jme->dev);
921 jme_set_multi(jme->dev);
927 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
933 * Start clock for RX MAC Processor
935 jme_mac_rxclk_on(jme);
939 jme_restart_rx_engine(struct jme_adapter *jme)
944 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
951 jme_disable_rx_engine(struct jme_adapter *jme)
959 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
962 val = jread32(jme, JME_RXCS);
963 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
965 val = jread32(jme, JME_RXCS);
970 pr_err("Disable RX engine timeout\n");
973 * Stop clock for RX MAC Processor
975 jme_mac_rxclk_off(jme);
979 jme_udpsum(struct sk_buff *skb)
982 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
988 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
990 if (skb->protocol != htons(ETH_P_IP))
992 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
993 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
994 iphlen = (iph->ihl << 2);
995 if ((iph->protocol != IPPROTO_UDP) ||
996 (skb->len < (iphlen + sizeof(struct udphdr)))) {
997 skb_push(skb, ETH_HLEN);
1000 udph = (struct udphdr *)skb_pull(skb, iphlen);
1002 skb_push(skb, iphlen);
1003 skb_push(skb, ETH_HLEN);
1005 skb_set_network_header(skb, ETH_HLEN);
1006 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1007 (skb->len < (ETH_HLEN +
1008 (ip_hdr(skb)->ihl << 2) +
1009 sizeof(struct udphdr)))) {
1010 skb_reset_network_header(skb);
1013 skb_set_transport_header(skb,
1014 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1015 csum = udp_hdr(skb)->check;
1016 skb_reset_transport_header(skb);
1017 skb_reset_network_header(skb);
1024 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1026 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1029 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1030 == RXWBFLAG_TCPON)) {
1031 if (flags & RXWBFLAG_IPV4)
1032 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1036 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1037 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1038 if (flags & RXWBFLAG_IPV4)
1039 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1043 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1044 == RXWBFLAG_IPV4)) {
1045 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1053 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1055 struct jme_ring *rxring = &(jme->rxring[0]);
1056 struct rxdesc *rxdesc = rxring->desc;
1057 struct jme_buffer_info *rxbi = rxring->bufinf;
1058 struct sk_buff *skb;
1065 pci_dma_sync_single_for_cpu(jme->pdev,
1068 PCI_DMA_FROMDEVICE);
1070 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1071 pci_dma_sync_single_for_device(jme->pdev,
1074 PCI_DMA_FROMDEVICE);
1076 ++(NET_STAT(jme).rx_dropped);
1078 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1081 skb_reserve(skb, RX_PREPAD_SIZE);
1082 skb_put(skb, framesize);
1083 skb->protocol = eth_type_trans(skb, jme->dev);
1085 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1086 skb->ip_summed = CHECKSUM_UNNECESSARY;
1088 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1089 skb->ip_summed = CHECKSUM_NONE;
1091 skb_checksum_none_assert(skb);
1094 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1096 jme->jme_vlan_rx(skb, jme->vlgrp,
1097 le16_to_cpu(rxdesc->descwb.vlan));
1098 NET_STAT(jme).rx_bytes += 4;
1106 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1107 cpu_to_le16(RXWBFLAG_DEST_MUL))
1108 ++(NET_STAT(jme).multicast);
1110 NET_STAT(jme).rx_bytes += framesize;
1111 ++(NET_STAT(jme).rx_packets);
1114 jme_set_clean_rxdesc(jme, idx);
1119 jme_process_receive(struct jme_adapter *jme, int limit)
1121 struct jme_ring *rxring = &(jme->rxring[0]);
1122 struct rxdesc *rxdesc = rxring->desc;
1123 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1125 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1128 if (unlikely(atomic_read(&jme->link_changing) != 1))
1131 if (unlikely(!netif_carrier_ok(jme->dev)))
1134 i = atomic_read(&rxring->next_to_clean);
1136 rxdesc = rxring->desc;
1139 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1140 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1145 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1147 if (unlikely(desccnt > 1 ||
1148 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1150 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1151 ++(NET_STAT(jme).rx_crc_errors);
1152 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1153 ++(NET_STAT(jme).rx_fifo_errors);
1155 ++(NET_STAT(jme).rx_errors);
1158 limit -= desccnt - 1;
1160 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1161 jme_set_clean_rxdesc(jme, j);
1162 j = (j + 1) & (mask);
1166 jme_alloc_and_feed_skb(jme, i);
1169 i = (i + desccnt) & (mask);
1173 atomic_set(&rxring->next_to_clean, i);
1176 atomic_inc(&jme->rx_cleaning);
1178 return limit > 0 ? limit : 0;
1183 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1185 if (likely(atmp == dpi->cur)) {
1190 if (dpi->attempt == atmp) {
1193 dpi->attempt = atmp;
1200 jme_dynamic_pcc(struct jme_adapter *jme)
1202 register struct dynpcc_info *dpi = &(jme->dpi);
1204 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1205 jme_attempt_pcc(dpi, PCC_P3);
1206 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1207 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1208 jme_attempt_pcc(dpi, PCC_P2);
1210 jme_attempt_pcc(dpi, PCC_P1);
1212 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1213 if (dpi->attempt < dpi->cur)
1214 tasklet_schedule(&jme->rxclean_task);
1215 jme_set_rx_pcc(jme, dpi->attempt);
1216 dpi->cur = dpi->attempt;
1222 jme_start_pcc_timer(struct jme_adapter *jme)
1224 struct dynpcc_info *dpi = &(jme->dpi);
1225 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1226 dpi->last_pkts = NET_STAT(jme).rx_packets;
1228 jwrite32(jme, JME_TMCSR,
1229 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1233 jme_stop_pcc_timer(struct jme_adapter *jme)
1235 jwrite32(jme, JME_TMCSR, 0);
1239 jme_shutdown_nic(struct jme_adapter *jme)
1243 phylink = jme_linkstat_from_phy(jme);
1245 if (!(phylink & PHY_LINK_UP)) {
1247 * Disable all interrupt before issue timer
1250 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1255 jme_pcc_tasklet(unsigned long arg)
1257 struct jme_adapter *jme = (struct jme_adapter *)arg;
1258 struct net_device *netdev = jme->dev;
1260 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1261 jme_shutdown_nic(jme);
1265 if (unlikely(!netif_carrier_ok(netdev) ||
1266 (atomic_read(&jme->link_changing) != 1)
1268 jme_stop_pcc_timer(jme);
1272 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1273 jme_dynamic_pcc(jme);
1275 jme_start_pcc_timer(jme);
1279 jme_polling_mode(struct jme_adapter *jme)
1281 jme_set_rx_pcc(jme, PCC_OFF);
1285 jme_interrupt_mode(struct jme_adapter *jme)
1287 jme_set_rx_pcc(jme, PCC_P1);
1291 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1294 apmc = jread32(jme, JME_APMC);
1295 return apmc & JME_APMC_PSEUDO_HP_EN;
1299 jme_start_shutdown_timer(struct jme_adapter *jme)
1303 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1304 apmc &= ~JME_APMC_EPIEN_CTRL;
1306 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1309 jwrite32f(jme, JME_APMC, apmc);
1311 jwrite32f(jme, JME_TIMER2, 0);
1312 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1313 jwrite32(jme, JME_TMCSR,
1314 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1318 jme_stop_shutdown_timer(struct jme_adapter *jme)
1322 jwrite32f(jme, JME_TMCSR, 0);
1323 jwrite32f(jme, JME_TIMER2, 0);
1324 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1326 apmc = jread32(jme, JME_APMC);
1327 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1328 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1330 jwrite32f(jme, JME_APMC, apmc);
1334 jme_link_change_tasklet(unsigned long arg)
1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
1337 struct net_device *netdev = jme->dev;
1340 while (!atomic_dec_and_test(&jme->link_changing)) {
1341 atomic_inc(&jme->link_changing);
1342 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1343 while (atomic_read(&jme->link_changing) != 1)
1344 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1347 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1350 jme->old_mtu = netdev->mtu;
1351 netif_stop_queue(netdev);
1352 if (jme_pseudo_hotplug_enabled(jme))
1353 jme_stop_shutdown_timer(jme);
1355 jme_stop_pcc_timer(jme);
1356 tasklet_disable(&jme->txclean_task);
1357 tasklet_disable(&jme->rxclean_task);
1358 tasklet_disable(&jme->rxempty_task);
1360 if (netif_carrier_ok(netdev)) {
1361 jme_disable_rx_engine(jme);
1362 jme_disable_tx_engine(jme);
1363 jme_reset_mac_processor(jme);
1364 jme_free_rx_resources(jme);
1365 jme_free_tx_resources(jme);
1367 if (test_bit(JME_FLAG_POLL, &jme->flags))
1368 jme_polling_mode(jme);
1370 netif_carrier_off(netdev);
1373 jme_check_link(netdev, 0);
1374 if (netif_carrier_ok(netdev)) {
1375 rc = jme_setup_rx_resources(jme);
1377 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1378 goto out_enable_tasklet;
1381 rc = jme_setup_tx_resources(jme);
1383 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1384 goto err_out_free_rx_resources;
1387 jme_enable_rx_engine(jme);
1388 jme_enable_tx_engine(jme);
1390 netif_start_queue(netdev);
1392 if (test_bit(JME_FLAG_POLL, &jme->flags))
1393 jme_interrupt_mode(jme);
1395 jme_start_pcc_timer(jme);
1396 } else if (jme_pseudo_hotplug_enabled(jme)) {
1397 jme_start_shutdown_timer(jme);
1400 goto out_enable_tasklet;
1402 err_out_free_rx_resources:
1403 jme_free_rx_resources(jme);
1405 tasklet_enable(&jme->txclean_task);
1406 tasklet_hi_enable(&jme->rxclean_task);
1407 tasklet_hi_enable(&jme->rxempty_task);
1409 atomic_inc(&jme->link_changing);
1413 jme_rx_clean_tasklet(unsigned long arg)
1415 struct jme_adapter *jme = (struct jme_adapter *)arg;
1416 struct dynpcc_info *dpi = &(jme->dpi);
1418 jme_process_receive(jme, jme->rx_ring_size);
1424 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1426 struct jme_adapter *jme = jme_napi_priv(holder);
1430 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1432 while (atomic_read(&jme->rx_empty) > 0) {
1433 atomic_dec(&jme->rx_empty);
1434 ++(NET_STAT(jme).rx_dropped);
1435 jme_restart_rx_engine(jme);
1437 atomic_inc(&jme->rx_empty);
1440 JME_RX_COMPLETE(netdev, holder);
1441 jme_interrupt_mode(jme);
1444 JME_NAPI_WEIGHT_SET(budget, rest);
1445 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1449 jme_rx_empty_tasklet(unsigned long arg)
1451 struct jme_adapter *jme = (struct jme_adapter *)arg;
1453 if (unlikely(atomic_read(&jme->link_changing) != 1))
1456 if (unlikely(!netif_carrier_ok(jme->dev)))
1459 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1461 jme_rx_clean_tasklet(arg);
1463 while (atomic_read(&jme->rx_empty) > 0) {
1464 atomic_dec(&jme->rx_empty);
1465 ++(NET_STAT(jme).rx_dropped);
1466 jme_restart_rx_engine(jme);
1468 atomic_inc(&jme->rx_empty);
1472 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1474 struct jme_ring *txring = &(jme->txring[0]);
1477 if (unlikely(netif_queue_stopped(jme->dev) &&
1478 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1479 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1480 netif_wake_queue(jme->dev);
1486 jme_tx_clean_tasklet(unsigned long arg)
1488 struct jme_adapter *jme = (struct jme_adapter *)arg;
1489 struct jme_ring *txring = &(jme->txring[0]);
1490 struct txdesc *txdesc = txring->desc;
1491 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1492 int i, j, cnt = 0, max, err, mask;
1494 tx_dbg(jme, "Into txclean\n");
1496 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1499 if (unlikely(atomic_read(&jme->link_changing) != 1))
1502 if (unlikely(!netif_carrier_ok(jme->dev)))
1505 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1506 mask = jme->tx_ring_mask;
1508 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1512 if (likely(ctxbi->skb &&
1513 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1515 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1516 i, ctxbi->nr_desc, jiffies);
1518 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1520 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1521 ttxbi = txbi + ((i + j) & (mask));
1522 txdesc[(i + j) & (mask)].dw[0] = 0;
1524 pci_unmap_page(jme->pdev,
1533 dev_kfree_skb(ctxbi->skb);
1535 cnt += ctxbi->nr_desc;
1537 if (unlikely(err)) {
1538 ++(NET_STAT(jme).tx_carrier_errors);
1540 ++(NET_STAT(jme).tx_packets);
1541 NET_STAT(jme).tx_bytes += ctxbi->len;
1546 ctxbi->start_xmit = 0;
1552 i = (i + ctxbi->nr_desc) & mask;
1557 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1558 atomic_set(&txring->next_to_clean, i);
1559 atomic_add(cnt, &txring->nr_free);
1561 jme_wake_queue_if_stopped(jme);
1564 atomic_inc(&jme->tx_cleaning);
1568 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1573 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1575 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1577 * Link change event is critical
1578 * all other events are ignored
1580 jwrite32(jme, JME_IEVE, intrstat);
1581 tasklet_schedule(&jme->linkch_task);
1585 if (intrstat & INTR_TMINTR) {
1586 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1587 tasklet_schedule(&jme->pcc_task);
1590 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1591 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1592 tasklet_schedule(&jme->txclean_task);
1595 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1596 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1602 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1603 if (intrstat & INTR_RX0EMP)
1604 atomic_inc(&jme->rx_empty);
1606 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1607 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1608 jme_polling_mode(jme);
1609 JME_RX_SCHEDULE(jme);
1613 if (intrstat & INTR_RX0EMP) {
1614 atomic_inc(&jme->rx_empty);
1615 tasklet_hi_schedule(&jme->rxempty_task);
1616 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1617 tasklet_hi_schedule(&jme->rxclean_task);
1623 * Re-enable interrupt
1625 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1628 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1630 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1633 jme_intr(int irq, void *dev_id)
1636 struct net_device *netdev = dev_id;
1637 struct jme_adapter *jme = netdev_priv(netdev);
1640 intrstat = jread32(jme, JME_IEVE);
1643 * Check if it's really an interrupt for us
1645 if (unlikely((intrstat & INTR_ENABLE) == 0))
1649 * Check if the device still exist
1651 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1654 jme_intr_msi(jme, intrstat);
1659 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1661 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1664 jme_msi(int irq, void *dev_id)
1667 struct net_device *netdev = dev_id;
1668 struct jme_adapter *jme = netdev_priv(netdev);
1671 intrstat = jread32(jme, JME_IEVE);
1673 jme_intr_msi(jme, intrstat);
1679 jme_reset_link(struct jme_adapter *jme)
1681 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1685 jme_restart_an(struct jme_adapter *jme)
1689 spin_lock_bh(&jme->phy_lock);
1690 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1691 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1692 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1693 spin_unlock_bh(&jme->phy_lock);
1697 jme_request_irq(struct jme_adapter *jme)
1700 struct net_device *netdev = jme->dev;
1701 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1702 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1703 int irq_flags = SA_SHIRQ;
1705 irq_handler_t handler = jme_intr;
1706 int irq_flags = IRQF_SHARED;
1709 if (!pci_enable_msi(jme->pdev)) {
1710 set_bit(JME_FLAG_MSI, &jme->flags);
1715 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1719 "Unable to request %s interrupt (return: %d)\n",
1720 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1723 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1724 pci_disable_msi(jme->pdev);
1725 clear_bit(JME_FLAG_MSI, &jme->flags);
1728 netdev->irq = jme->pdev->irq;
1735 jme_free_irq(struct jme_adapter *jme)
1737 free_irq(jme->pdev->irq, jme->dev);
1738 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1739 pci_disable_msi(jme->pdev);
1740 clear_bit(JME_FLAG_MSI, &jme->flags);
1741 jme->dev->irq = jme->pdev->irq;
1746 jme_new_phy_on(struct jme_adapter *jme)
1750 reg = jread32(jme, JME_PHY_PWR);
1751 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1752 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1753 jwrite32(jme, JME_PHY_PWR, reg);
1755 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1756 reg &= ~PE1_GPREG0_PBG;
1757 reg |= PE1_GPREG0_ENBG;
1758 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1762 jme_new_phy_off(struct jme_adapter *jme)
1766 reg = jread32(jme, JME_PHY_PWR);
1767 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1768 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1769 jwrite32(jme, JME_PHY_PWR, reg);
1771 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1772 reg &= ~PE1_GPREG0_PBG;
1773 reg |= PE1_GPREG0_PDD3COLD;
1774 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1778 jme_phy_on(struct jme_adapter *jme)
1782 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1783 bmcr &= ~BMCR_PDOWN;
1784 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1786 if (new_phy_power_ctrl(jme->chip_main_rev))
1787 jme_new_phy_on(jme);
1791 jme_phy_off(struct jme_adapter *jme)
1795 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1797 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1799 if (new_phy_power_ctrl(jme->chip_main_rev))
1800 jme_new_phy_off(jme);
1804 jme_open(struct net_device *netdev)
1806 struct jme_adapter *jme = netdev_priv(netdev);
1810 JME_NAPI_ENABLE(jme);
1812 tasklet_enable(&jme->linkch_task);
1813 tasklet_enable(&jme->txclean_task);
1814 tasklet_hi_enable(&jme->rxclean_task);
1815 tasklet_hi_enable(&jme->rxempty_task);
1817 rc = jme_request_irq(jme);
1824 if (test_bit(JME_FLAG_SSET, &jme->flags))
1825 jme_set_settings(netdev, &jme->old_ecmd);
1827 jme_reset_phy_processor(jme);
1829 jme_reset_link(jme);
1834 netif_stop_queue(netdev);
1835 netif_carrier_off(netdev);
1840 jme_set_100m_half(struct jme_adapter *jme)
1845 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1846 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1847 BMCR_SPEED1000 | BMCR_FULLDPLX);
1848 tmp |= BMCR_SPEED100;
1851 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1854 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1856 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1859 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1861 jme_wait_link(struct jme_adapter *jme)
1863 u32 phylink, to = JME_WAIT_LINK_TIME;
1866 phylink = jme_linkstat_from_phy(jme);
1867 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1869 phylink = jme_linkstat_from_phy(jme);
1874 jme_powersave_phy(struct jme_adapter *jme)
1876 if (jme->reg_pmcs) {
1877 jme_set_100m_half(jme);
1878 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1887 jme_close(struct net_device *netdev)
1889 struct jme_adapter *jme = netdev_priv(netdev);
1891 netif_stop_queue(netdev);
1892 netif_carrier_off(netdev);
1897 JME_NAPI_DISABLE(jme);
1899 tasklet_disable(&jme->linkch_task);
1900 tasklet_disable(&jme->txclean_task);
1901 tasklet_disable(&jme->rxclean_task);
1902 tasklet_disable(&jme->rxempty_task);
1904 jme_disable_rx_engine(jme);
1905 jme_disable_tx_engine(jme);
1906 jme_reset_mac_processor(jme);
1907 jme_free_rx_resources(jme);
1908 jme_free_tx_resources(jme);
1916 jme_alloc_txdesc(struct jme_adapter *jme,
1917 struct sk_buff *skb)
1919 struct jme_ring *txring = &(jme->txring[0]);
1920 int idx, nr_alloc, mask = jme->tx_ring_mask;
1922 idx = txring->next_to_use;
1923 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1925 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1928 atomic_sub(nr_alloc, &txring->nr_free);
1930 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1936 jme_fill_tx_map(struct pci_dev *pdev,
1937 struct txdesc *txdesc,
1938 struct jme_buffer_info *txbi,
1946 dmaaddr = pci_map_page(pdev,
1952 pci_dma_sync_single_for_device(pdev,
1959 txdesc->desc2.flags = TXFLAG_OWN;
1960 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1961 txdesc->desc2.datalen = cpu_to_le16(len);
1962 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1963 txdesc->desc2.bufaddrl = cpu_to_le32(
1964 (__u64)dmaaddr & 0xFFFFFFFFUL);
1966 txbi->mapping = dmaaddr;
1971 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1973 struct jme_ring *txring = &(jme->txring[0]);
1974 struct txdesc *txdesc = txring->desc, *ctxdesc;
1975 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1976 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1977 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1978 int mask = jme->tx_ring_mask;
1979 struct skb_frag_struct *frag;
1982 for (i = 0 ; i < nr_frags ; ++i) {
1983 frag = &skb_shinfo(skb)->frags[i];
1984 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1985 ctxbi = txbi + ((idx + i + 2) & (mask));
1987 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1988 frag->page_offset, frag->size, hidma);
1991 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1992 ctxdesc = txdesc + ((idx + 1) & (mask));
1993 ctxbi = txbi + ((idx + 1) & (mask));
1994 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1995 offset_in_page(skb->data), len, hidma);
2000 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2003 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2004 skb_shinfo(skb)->tso_size
2006 skb_shinfo(skb)->gso_size
2008 && skb_header_cloned(skb) &&
2009 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2018 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2020 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2021 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2023 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2026 *flags |= TXFLAG_LSEN;
2028 if (skb->protocol == htons(ETH_P_IP)) {
2029 struct iphdr *iph = ip_hdr(skb);
2032 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2037 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2039 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2052 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2054 #ifdef CHECKSUM_PARTIAL
2055 if (skb->ip_summed == CHECKSUM_PARTIAL)
2057 if (skb->ip_summed == CHECKSUM_HW)
2062 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2063 if (skb->protocol == htons(ETH_P_IP))
2064 ip_proto = ip_hdr(skb)->protocol;
2065 else if (skb->protocol == htons(ETH_P_IPV6))
2066 ip_proto = ipv6_hdr(skb)->nexthdr;
2070 switch (skb->protocol) {
2071 case htons(ETH_P_IP):
2072 ip_proto = ip_hdr(skb)->protocol;
2074 case htons(ETH_P_IPV6):
2075 ip_proto = ipv6_hdr(skb)->nexthdr;
2085 *flags |= TXFLAG_TCPCS;
2088 *flags |= TXFLAG_UDPCS;
2091 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2098 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2100 if (vlan_tx_tag_present(skb)) {
2101 *flags |= TXFLAG_TAGON;
2102 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2107 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2109 struct jme_ring *txring = &(jme->txring[0]);
2110 struct txdesc *txdesc;
2111 struct jme_buffer_info *txbi;
2114 txdesc = (struct txdesc *)txring->desc + idx;
2115 txbi = txring->bufinf + idx;
2121 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2123 * Set OWN bit at final.
2124 * When kernel transmit faster than NIC.
2125 * And NIC trying to send this descriptor before we tell
2126 * it to start sending this TX queue.
2127 * Other fields are already filled correctly.
2130 flags = TXFLAG_OWN | TXFLAG_INT;
2132 * Set checksum flags while not tso
2134 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2135 jme_tx_csum(jme, skb, &flags);
2136 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2137 jme_map_tx_skb(jme, skb, idx);
2138 txdesc->desc1.flags = flags;
2140 * Set tx buffer info after telling NIC to send
2141 * For better tx_clean timing
2144 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2146 txbi->len = skb->len;
2147 txbi->start_xmit = jiffies;
2148 if (!txbi->start_xmit)
2149 txbi->start_xmit = (0UL-1);
2155 jme_stop_queue_if_full(struct jme_adapter *jme)
2157 struct jme_ring *txring = &(jme->txring[0]);
2158 struct jme_buffer_info *txbi = txring->bufinf;
2159 int idx = atomic_read(&txring->next_to_clean);
2164 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2165 netif_stop_queue(jme->dev);
2166 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2168 if (atomic_read(&txring->nr_free)
2169 >= (jme->tx_wake_threshold)) {
2170 netif_wake_queue(jme->dev);
2171 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2175 if (unlikely(txbi->start_xmit &&
2176 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2178 netif_stop_queue(jme->dev);
2179 netif_info(jme, tx_queued, jme->dev,
2180 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2185 * This function is already protected by netif_tx_lock()
2188 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2193 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2195 struct jme_adapter *jme = netdev_priv(netdev);
2198 if (unlikely(jme_expand_header(jme, skb))) {
2199 ++(NET_STAT(jme).tx_dropped);
2200 return NETDEV_TX_OK;
2203 idx = jme_alloc_txdesc(jme, skb);
2205 if (unlikely(idx < 0)) {
2206 netif_stop_queue(netdev);
2207 netif_err(jme, tx_err, jme->dev,
2208 "BUG! Tx ring full when queue awake!\n");
2210 return NETDEV_TX_BUSY;
2213 jme_fill_tx_desc(jme, skb, idx);
2215 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2216 TXCS_SELECT_QUEUE0 |
2219 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2220 netdev->trans_start = jiffies;
2223 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2224 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2225 jme_stop_queue_if_full(jme);
2227 return NETDEV_TX_OK;
2231 jme_set_unicastaddr(struct net_device *netdev)
2233 struct jme_adapter *jme = netdev_priv(netdev);
2236 val = (netdev->dev_addr[3] & 0xff) << 24 |
2237 (netdev->dev_addr[2] & 0xff) << 16 |
2238 (netdev->dev_addr[1] & 0xff) << 8 |
2239 (netdev->dev_addr[0] & 0xff);
2240 jwrite32(jme, JME_RXUMA_LO, val);
2241 val = (netdev->dev_addr[5] & 0xff) << 8 |
2242 (netdev->dev_addr[4] & 0xff);
2243 jwrite32(jme, JME_RXUMA_HI, val);
2247 jme_set_macaddr(struct net_device *netdev, void *p)
2249 struct jme_adapter *jme = netdev_priv(netdev);
2250 struct sockaddr *addr = p;
2252 if (netif_running(netdev))
2255 spin_lock_bh(&jme->macaddr_lock);
2256 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2257 jme_set_unicastaddr(netdev);
2258 spin_unlock_bh(&jme->macaddr_lock);
2264 jme_set_multi(struct net_device *netdev)
2266 struct jme_adapter *jme = netdev_priv(netdev);
2267 u32 mc_hash[2] = {};
2268 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2272 spin_lock_bh(&jme->rxmcs_lock);
2274 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2276 if (netdev->flags & IFF_PROMISC) {
2277 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2278 } else if (netdev->flags & IFF_ALLMULTI) {
2279 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2280 } else if (netdev->flags & IFF_MULTICAST) {
2281 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2282 struct dev_mc_list *mclist;
2284 struct netdev_hw_addr *ha;
2288 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2289 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2290 for (i = 0, mclist = netdev->mc_list;
2291 mclist && i < netdev->mc_count;
2292 ++i, mclist = mclist->next) {
2293 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2294 netdev_for_each_mc_addr(mclist, netdev) {
2296 netdev_for_each_mc_addr(ha, netdev) {
2298 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2299 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2301 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2303 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2306 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2307 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2311 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2313 spin_unlock_bh(&jme->rxmcs_lock);
2317 jme_change_mtu(struct net_device *netdev, int new_mtu)
2319 struct jme_adapter *jme = netdev_priv(netdev);
2321 if (new_mtu == jme->old_mtu)
2324 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2325 ((new_mtu) < IPV6_MIN_MTU))
2328 if (new_mtu > 4000) {
2329 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2330 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2331 jme_restart_rx_engine(jme);
2333 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2334 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2335 jme_restart_rx_engine(jme);
2338 if (new_mtu > 1900) {
2339 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2340 NETIF_F_TSO | NETIF_F_TSO6);
2342 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2343 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2344 if (test_bit(JME_FLAG_TSO, &jme->flags))
2345 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2348 netdev->mtu = new_mtu;
2349 jme_reset_link(jme);
2355 jme_tx_timeout(struct net_device *netdev)
2357 struct jme_adapter *jme = netdev_priv(netdev);
2360 jme_reset_phy_processor(jme);
2361 if (test_bit(JME_FLAG_SSET, &jme->flags))
2362 jme_set_settings(netdev, &jme->old_ecmd);
2365 * Force to Reset the link again
2367 jme_reset_link(jme);
2370 static inline void jme_pause_rx(struct jme_adapter *jme)
2372 atomic_dec(&jme->link_changing);
2374 jme_set_rx_pcc(jme, PCC_OFF);
2375 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2376 JME_NAPI_DISABLE(jme);
2378 tasklet_disable(&jme->rxclean_task);
2379 tasklet_disable(&jme->rxempty_task);
2383 static inline void jme_resume_rx(struct jme_adapter *jme)
2385 struct dynpcc_info *dpi = &(jme->dpi);
2387 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2388 JME_NAPI_ENABLE(jme);
2390 tasklet_hi_enable(&jme->rxclean_task);
2391 tasklet_hi_enable(&jme->rxempty_task);
2394 dpi->attempt = PCC_P1;
2396 jme_set_rx_pcc(jme, PCC_P1);
2398 atomic_inc(&jme->link_changing);
2402 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2404 struct jme_adapter *jme = netdev_priv(netdev);
2411 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2413 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2415 struct jme_adapter *jme = netdev_priv(netdev);
2419 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2420 jme->vlgrp->vlan_devices[vid] = NULL;
2422 vlan_group_set_device(jme->vlgrp, vid, NULL);
2430 jme_get_drvinfo(struct net_device *netdev,
2431 struct ethtool_drvinfo *info)
2433 struct jme_adapter *jme = netdev_priv(netdev);
2435 strcpy(info->driver, DRV_NAME);
2436 strcpy(info->version, DRV_VERSION);
2437 strcpy(info->bus_info, pci_name(jme->pdev));
2441 jme_get_regs_len(struct net_device *netdev)
2447 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2451 for (i = 0 ; i < len ; i += 4)
2452 p[i >> 2] = jread32(jme, reg + i);
2456 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2459 u16 *p16 = (u16 *)p;
2461 for (i = 0 ; i < reg_nr ; ++i)
2462 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2466 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2468 struct jme_adapter *jme = netdev_priv(netdev);
2469 u32 *p32 = (u32 *)p;
2471 memset(p, 0xFF, JME_REG_LEN);
2474 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2477 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2480 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2483 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2486 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2490 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2492 struct jme_adapter *jme = netdev_priv(netdev);
2494 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2495 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2497 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2498 ecmd->use_adaptive_rx_coalesce = false;
2499 ecmd->rx_coalesce_usecs = 0;
2500 ecmd->rx_max_coalesced_frames = 0;
2504 ecmd->use_adaptive_rx_coalesce = true;
2506 switch (jme->dpi.cur) {
2508 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2509 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2512 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2513 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2516 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2517 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2527 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2529 struct jme_adapter *jme = netdev_priv(netdev);
2530 struct dynpcc_info *dpi = &(jme->dpi);
2532 if (netif_running(netdev))
2535 if (ecmd->use_adaptive_rx_coalesce &&
2536 test_bit(JME_FLAG_POLL, &jme->flags)) {
2537 clear_bit(JME_FLAG_POLL, &jme->flags);
2538 jme->jme_rx = netif_rx;
2539 jme->jme_vlan_rx = vlan_hwaccel_rx;
2541 dpi->attempt = PCC_P1;
2543 jme_set_rx_pcc(jme, PCC_P1);
2544 jme_interrupt_mode(jme);
2545 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2546 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2547 set_bit(JME_FLAG_POLL, &jme->flags);
2548 jme->jme_rx = netif_receive_skb;
2549 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2550 jme_interrupt_mode(jme);
2557 jme_get_pauseparam(struct net_device *netdev,
2558 struct ethtool_pauseparam *ecmd)
2560 struct jme_adapter *jme = netdev_priv(netdev);
2563 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2564 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2566 spin_lock_bh(&jme->phy_lock);
2567 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2568 spin_unlock_bh(&jme->phy_lock);
2571 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2575 jme_set_pauseparam(struct net_device *netdev,
2576 struct ethtool_pauseparam *ecmd)
2578 struct jme_adapter *jme = netdev_priv(netdev);
2581 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2582 (ecmd->tx_pause != 0)) {
2585 jme->reg_txpfc |= TXPFC_PF_EN;
2587 jme->reg_txpfc &= ~TXPFC_PF_EN;
2589 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2592 spin_lock_bh(&jme->rxmcs_lock);
2593 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2594 (ecmd->rx_pause != 0)) {
2597 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2599 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2601 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2603 spin_unlock_bh(&jme->rxmcs_lock);
2605 spin_lock_bh(&jme->phy_lock);
2606 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2607 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2608 (ecmd->autoneg != 0)) {
2611 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2613 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2615 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2616 MII_ADVERTISE, val);
2618 spin_unlock_bh(&jme->phy_lock);
2624 jme_get_wol(struct net_device *netdev,
2625 struct ethtool_wolinfo *wol)
2627 struct jme_adapter *jme = netdev_priv(netdev);
2629 wol->supported = WAKE_MAGIC | WAKE_PHY;
2633 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2634 wol->wolopts |= WAKE_PHY;
2636 if (jme->reg_pmcs & PMCS_MFEN)
2637 wol->wolopts |= WAKE_MAGIC;
2642 jme_set_wol(struct net_device *netdev,
2643 struct ethtool_wolinfo *wol)
2645 struct jme_adapter *jme = netdev_priv(netdev);
2647 if (wol->wolopts & (WAKE_MAGICSECURE |
2656 if (wol->wolopts & WAKE_PHY)
2657 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2659 if (wol->wolopts & WAKE_MAGIC)
2660 jme->reg_pmcs |= PMCS_MFEN;
2662 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2663 #ifndef JME_NEW_PM_API
2664 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2666 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2667 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2674 jme_get_settings(struct net_device *netdev,
2675 struct ethtool_cmd *ecmd)
2677 struct jme_adapter *jme = netdev_priv(netdev);
2680 spin_lock_bh(&jme->phy_lock);
2681 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2682 spin_unlock_bh(&jme->phy_lock);
2687 jme_set_settings(struct net_device *netdev,
2688 struct ethtool_cmd *ecmd)
2690 struct jme_adapter *jme = netdev_priv(netdev);
2693 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2694 && ecmd->autoneg != AUTONEG_ENABLE)
2698 * Check If user changed duplex only while force_media.
2699 * Hardware would not generate link change interrupt.
2701 if (jme->mii_if.force_media &&
2702 ecmd->autoneg != AUTONEG_ENABLE &&
2703 (jme->mii_if.full_duplex != ecmd->duplex))
2706 spin_lock_bh(&jme->phy_lock);
2707 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2708 spin_unlock_bh(&jme->phy_lock);
2712 jme_reset_link(jme);
2713 jme->old_ecmd = *ecmd;
2714 set_bit(JME_FLAG_SSET, &jme->flags);
2721 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2724 struct jme_adapter *jme = netdev_priv(netdev);
2725 struct mii_ioctl_data *mii_data = if_mii(rq);
2726 unsigned int duplex_chg;
2728 if (cmd == SIOCSMIIREG) {
2729 u16 val = mii_data->val_in;
2730 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2731 (val & BMCR_SPEED1000))
2735 spin_lock_bh(&jme->phy_lock);
2736 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2737 spin_unlock_bh(&jme->phy_lock);
2739 if (!rc && (cmd == SIOCSMIIREG)) {
2741 jme_reset_link(jme);
2742 jme_get_settings(netdev, &jme->old_ecmd);
2743 set_bit(JME_FLAG_SSET, &jme->flags);
2750 jme_get_link(struct net_device *netdev)
2752 struct jme_adapter *jme = netdev_priv(netdev);
2753 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2757 jme_get_msglevel(struct net_device *netdev)
2759 struct jme_adapter *jme = netdev_priv(netdev);
2760 return jme->msg_enable;
2764 jme_set_msglevel(struct net_device *netdev, u32 value)
2766 struct jme_adapter *jme = netdev_priv(netdev);
2767 jme->msg_enable = value;
2771 jme_get_rx_csum(struct net_device *netdev)
2773 struct jme_adapter *jme = netdev_priv(netdev);
2774 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2778 jme_set_rx_csum(struct net_device *netdev, u32 on)
2780 struct jme_adapter *jme = netdev_priv(netdev);
2782 spin_lock_bh(&jme->rxmcs_lock);
2784 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2786 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2787 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2788 spin_unlock_bh(&jme->rxmcs_lock);
2794 jme_set_tx_csum(struct net_device *netdev, u32 on)
2796 struct jme_adapter *jme = netdev_priv(netdev);
2799 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2800 if (netdev->mtu <= 1900)
2802 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2804 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2806 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2813 jme_set_tso(struct net_device *netdev, u32 on)
2815 struct jme_adapter *jme = netdev_priv(netdev);
2818 set_bit(JME_FLAG_TSO, &jme->flags);
2819 if (netdev->mtu <= 1900)
2820 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2822 clear_bit(JME_FLAG_TSO, &jme->flags);
2823 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2830 jme_nway_reset(struct net_device *netdev)
2832 struct jme_adapter *jme = netdev_priv(netdev);
2833 jme_restart_an(jme);
2838 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2843 val = jread32(jme, JME_SMBCSR);
2844 to = JME_SMB_BUSY_TIMEOUT;
2845 while ((val & SMBCSR_BUSY) && --to) {
2847 val = jread32(jme, JME_SMBCSR);
2850 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2854 jwrite32(jme, JME_SMBINTF,
2855 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2856 SMBINTF_HWRWN_READ |
2859 val = jread32(jme, JME_SMBINTF);
2860 to = JME_SMB_BUSY_TIMEOUT;
2861 while ((val & SMBINTF_HWCMD) && --to) {
2863 val = jread32(jme, JME_SMBINTF);
2866 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2870 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2874 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2879 val = jread32(jme, JME_SMBCSR);
2880 to = JME_SMB_BUSY_TIMEOUT;
2881 while ((val & SMBCSR_BUSY) && --to) {
2883 val = jread32(jme, JME_SMBCSR);
2886 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2890 jwrite32(jme, JME_SMBINTF,
2891 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2892 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2893 SMBINTF_HWRWN_WRITE |
2896 val = jread32(jme, JME_SMBINTF);
2897 to = JME_SMB_BUSY_TIMEOUT;
2898 while ((val & SMBINTF_HWCMD) && --to) {
2900 val = jread32(jme, JME_SMBINTF);
2903 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2911 jme_get_eeprom_len(struct net_device *netdev)
2913 struct jme_adapter *jme = netdev_priv(netdev);
2915 val = jread32(jme, JME_SMBCSR);
2916 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2920 jme_get_eeprom(struct net_device *netdev,
2921 struct ethtool_eeprom *eeprom, u8 *data)
2923 struct jme_adapter *jme = netdev_priv(netdev);
2924 int i, offset = eeprom->offset, len = eeprom->len;
2927 * ethtool will check the boundary for us
2929 eeprom->magic = JME_EEPROM_MAGIC;
2930 for (i = 0 ; i < len ; ++i)
2931 data[i] = jme_smb_read(jme, i + offset);
2937 jme_set_eeprom(struct net_device *netdev,
2938 struct ethtool_eeprom *eeprom, u8 *data)
2940 struct jme_adapter *jme = netdev_priv(netdev);
2941 int i, offset = eeprom->offset, len = eeprom->len;
2943 if (eeprom->magic != JME_EEPROM_MAGIC)
2947 * ethtool will check the boundary for us
2949 for (i = 0 ; i < len ; ++i)
2950 jme_smb_write(jme, i + offset, data[i]);
2955 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2956 static struct ethtool_ops jme_ethtool_ops = {
2958 static const struct ethtool_ops jme_ethtool_ops = {
2960 .get_drvinfo = jme_get_drvinfo,
2961 .get_regs_len = jme_get_regs_len,
2962 .get_regs = jme_get_regs,
2963 .get_coalesce = jme_get_coalesce,
2964 .set_coalesce = jme_set_coalesce,
2965 .get_pauseparam = jme_get_pauseparam,
2966 .set_pauseparam = jme_set_pauseparam,
2967 .get_wol = jme_get_wol,
2968 .set_wol = jme_set_wol,
2969 .get_settings = jme_get_settings,
2970 .set_settings = jme_set_settings,
2971 .get_link = jme_get_link,
2972 .get_msglevel = jme_get_msglevel,
2973 .set_msglevel = jme_set_msglevel,
2974 .get_rx_csum = jme_get_rx_csum,
2975 .set_rx_csum = jme_set_rx_csum,
2976 .set_tx_csum = jme_set_tx_csum,
2977 .set_tso = jme_set_tso,
2978 .set_sg = ethtool_op_set_sg,
2979 .nway_reset = jme_nway_reset,
2980 .get_eeprom_len = jme_get_eeprom_len,
2981 .get_eeprom = jme_get_eeprom,
2982 .set_eeprom = jme_set_eeprom,
2986 jme_pci_dma64(struct pci_dev *pdev)
2988 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2989 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2990 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2992 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2995 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2996 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2998 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3002 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3003 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3004 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3006 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3009 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3010 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3012 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3016 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3017 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3018 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3020 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3021 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3029 jme_phy_init(struct jme_adapter *jme)
3033 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3034 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3038 jme_check_hw_ver(struct jme_adapter *jme)
3042 chipmode = jread32(jme, JME_CHIPMODE);
3044 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3045 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3046 jme->chip_main_rev = jme->chiprev & 0xF;
3047 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3050 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051 static const struct net_device_ops jme_netdev_ops = {
3052 .ndo_open = jme_open,
3053 .ndo_stop = jme_close,
3054 .ndo_validate_addr = eth_validate_addr,
3055 .ndo_do_ioctl = jme_ioctl,
3056 .ndo_start_xmit = jme_start_xmit,
3057 .ndo_set_mac_address = jme_set_macaddr,
3058 .ndo_set_multicast_list = jme_set_multi,
3059 .ndo_change_mtu = jme_change_mtu,
3060 .ndo_tx_timeout = jme_tx_timeout,
3061 .ndo_vlan_rx_register = jme_vlan_rx_register,
3065 static int __devinit
3066 jme_init_one(struct pci_dev *pdev,
3067 const struct pci_device_id *ent)
3069 int rc = 0, using_dac, i;
3070 struct net_device *netdev;
3071 struct jme_adapter *jme;
3076 * set up PCI device basics
3078 rc = pci_enable_device(pdev);
3080 pr_err("Cannot enable PCI device\n");
3084 using_dac = jme_pci_dma64(pdev);
3085 if (using_dac < 0) {
3086 pr_err("Cannot set PCI DMA Mask\n");
3088 goto err_out_disable_pdev;
3091 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3092 pr_err("No PCI resource region found\n");
3094 goto err_out_disable_pdev;
3097 rc = pci_request_regions(pdev, DRV_NAME);
3099 pr_err("Cannot obtain PCI resource region\n");
3100 goto err_out_disable_pdev;
3103 pci_set_master(pdev);
3106 * alloc and init net device
3108 netdev = alloc_etherdev(sizeof(*jme));
3110 pr_err("Cannot allocate netdev structure\n");
3112 goto err_out_release_regions;
3114 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3115 netdev->netdev_ops = &jme_netdev_ops;
3117 netdev->open = jme_open;
3118 netdev->stop = jme_close;
3119 netdev->do_ioctl = jme_ioctl;
3120 netdev->hard_start_xmit = jme_start_xmit;
3121 netdev->set_mac_address = jme_set_macaddr;
3122 netdev->set_multicast_list = jme_set_multi;
3123 netdev->change_mtu = jme_change_mtu;
3124 netdev->tx_timeout = jme_tx_timeout;
3125 netdev->vlan_rx_register = jme_vlan_rx_register;
3126 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3127 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3129 NETDEV_GET_STATS(netdev, &jme_get_stats);
3131 netdev->ethtool_ops = &jme_ethtool_ops;
3132 netdev->watchdog_timeo = TX_TIMEOUT;
3133 netdev->features = NETIF_F_IP_CSUM |
3138 NETIF_F_HW_VLAN_TX |
3141 netdev->features |= NETIF_F_HIGHDMA;
3143 SET_NETDEV_DEV(netdev, &pdev->dev);
3144 pci_set_drvdata(pdev, netdev);
3149 jme = netdev_priv(netdev);
3152 jme->jme_rx = netif_rx;
3153 jme->jme_vlan_rx = vlan_hwaccel_rx;
3154 jme->old_mtu = netdev->mtu = 1500;
3156 jme->tx_ring_size = 1 << 10;
3157 jme->tx_ring_mask = jme->tx_ring_size - 1;
3158 jme->tx_wake_threshold = 1 << 9;
3159 jme->rx_ring_size = 1 << 9;
3160 jme->rx_ring_mask = jme->rx_ring_size - 1;
3161 jme->msg_enable = JME_DEF_MSG_ENABLE;
3162 jme->regs = ioremap(pci_resource_start(pdev, 0),
3163 pci_resource_len(pdev, 0));
3165 pr_err("Mapping PCI resource region error\n");
3167 goto err_out_free_netdev;
3171 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3172 jwrite32(jme, JME_APMC, apmc);
3173 } else if (force_pseudohp) {
3174 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3175 jwrite32(jme, JME_APMC, apmc);
3178 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3180 spin_lock_init(&jme->phy_lock);
3181 spin_lock_init(&jme->macaddr_lock);
3182 spin_lock_init(&jme->rxmcs_lock);
3184 atomic_set(&jme->link_changing, 1);
3185 atomic_set(&jme->rx_cleaning, 1);
3186 atomic_set(&jme->tx_cleaning, 1);
3187 atomic_set(&jme->rx_empty, 1);
3189 tasklet_init(&jme->pcc_task,
3191 (unsigned long) jme);
3192 tasklet_init(&jme->linkch_task,
3193 jme_link_change_tasklet,
3194 (unsigned long) jme);
3195 tasklet_init(&jme->txclean_task,
3196 jme_tx_clean_tasklet,
3197 (unsigned long) jme);
3198 tasklet_init(&jme->rxclean_task,
3199 jme_rx_clean_tasklet,
3200 (unsigned long) jme);
3201 tasklet_init(&jme->rxempty_task,
3202 jme_rx_empty_tasklet,
3203 (unsigned long) jme);
3204 tasklet_disable_nosync(&jme->linkch_task);
3205 tasklet_disable_nosync(&jme->txclean_task);
3206 tasklet_disable_nosync(&jme->rxclean_task);
3207 tasklet_disable_nosync(&jme->rxempty_task);
3208 jme->dpi.cur = PCC_P1;
3211 jme->reg_rxcs = RXCS_DEFAULT;
3212 jme->reg_rxmcs = RXMCS_DEFAULT;
3214 jme->reg_pmcs = PMCS_MFEN;
3215 jme->reg_gpreg1 = GPREG1_DEFAULT;
3216 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3217 set_bit(JME_FLAG_TSO, &jme->flags);
3220 * Get Max Read Req Size from PCI Config Space
3222 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3223 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3224 switch (jme->mrrs) {
3226 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3229 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3232 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3237 * Must check before reset_mac_processor
3239 jme_check_hw_ver(jme);
3240 jme->mii_if.dev = netdev;
3242 jme->mii_if.phy_id = 0;
3243 for (i = 1 ; i < 32 ; ++i) {
3244 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3245 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3246 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3247 jme->mii_if.phy_id = i;
3252 if (!jme->mii_if.phy_id) {
3254 pr_err("Can not find phy_id\n");
3258 jme->reg_ghc |= GHC_LINK_POLL;
3260 jme->mii_if.phy_id = 1;
3262 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3263 jme->mii_if.supports_gmii = true;
3265 jme->mii_if.supports_gmii = false;
3266 jme->mii_if.phy_id_mask = 0x1F;
3267 jme->mii_if.reg_num_mask = 0x1F;
3268 jme->mii_if.mdio_read = jme_mdio_read;
3269 jme->mii_if.mdio_write = jme_mdio_write;
3272 pci_set_power_state(jme->pdev, PCI_D0);
3273 #ifndef JME_NEW_PM_API
3274 jme_pci_wakeup_enable(jme, true);
3276 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3277 device_set_wakeup_enable(&pdev->dev, true);
3280 jme_set_phyfifo_5level(jme);
3281 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3282 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3284 jme->pcirev = pdev->revision;
3291 * Reset MAC processor and reload EEPROM for MAC Address
3293 jme_reset_mac_processor(jme);
3294 rc = jme_reload_eeprom(jme);
3296 pr_err("Reload eeprom for reading MAC Address error\n");
3299 jme_load_macaddr(netdev);
3302 * Tell stack that we are not ready to work until open()
3304 netif_carrier_off(netdev);
3306 rc = register_netdev(netdev);
3308 pr_err("Cannot register net device\n");
3312 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3313 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3314 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3315 "JMC250 Gigabit Ethernet" :
3316 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3317 "JMC260 Fast Ethernet" : "Unknown",
3318 (jme->fpgaver != 0) ? " (FPGA)" : "",
3319 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3321 netdev->dev_addr[0],
3322 netdev->dev_addr[1],
3323 netdev->dev_addr[2],
3324 netdev->dev_addr[3],
3325 netdev->dev_addr[4],
3326 netdev->dev_addr[5]);
3332 err_out_free_netdev:
3333 pci_set_drvdata(pdev, NULL);
3334 free_netdev(netdev);
3335 err_out_release_regions:
3336 pci_release_regions(pdev);
3337 err_out_disable_pdev:
3338 pci_disable_device(pdev);
3343 static void __devexit
3344 jme_remove_one(struct pci_dev *pdev)
3346 struct net_device *netdev = pci_get_drvdata(pdev);
3347 struct jme_adapter *jme = netdev_priv(netdev);
3349 unregister_netdev(netdev);
3351 pci_set_drvdata(pdev, NULL);
3352 free_netdev(netdev);
3353 pci_release_regions(pdev);
3354 pci_disable_device(pdev);
3359 jme_shutdown(struct pci_dev *pdev)
3361 struct net_device *netdev = pci_get_drvdata(pdev);
3362 struct jme_adapter *jme = netdev_priv(netdev);
3364 jme_powersave_phy(jme);
3365 #ifndef JME_NEW_PM_API
3366 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3368 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3369 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
3373 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3378 #ifdef CONFIG_PM_SLEEP
3385 #ifdef JME_NEW_PM_API
3386 jme_suspend(struct device *dev)
3388 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3391 #ifdef JME_NEW_PM_API
3392 struct pci_dev *pdev = to_pci_dev(dev);
3394 struct net_device *netdev = pci_get_drvdata(pdev);
3395 struct jme_adapter *jme = netdev_priv(netdev);
3397 atomic_dec(&jme->link_changing);
3399 netif_device_detach(netdev);
3400 netif_stop_queue(netdev);
3403 tasklet_disable(&jme->txclean_task);
3404 tasklet_disable(&jme->rxclean_task);
3405 tasklet_disable(&jme->rxempty_task);
3407 if (netif_carrier_ok(netdev)) {
3408 if (test_bit(JME_FLAG_POLL, &jme->flags))
3409 jme_polling_mode(jme);
3411 jme_stop_pcc_timer(jme);
3412 jme_disable_rx_engine(jme);
3413 jme_disable_tx_engine(jme);
3414 jme_reset_mac_processor(jme);
3415 jme_free_rx_resources(jme);
3416 jme_free_tx_resources(jme);
3417 netif_carrier_off(netdev);
3421 tasklet_enable(&jme->txclean_task);
3422 tasklet_hi_enable(&jme->rxclean_task);
3423 tasklet_hi_enable(&jme->rxempty_task);
3425 jme_powersave_phy(jme);
3426 #ifndef JME_NEW_PM_API
3427 pci_save_state(pdev);
3428 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3429 pci_set_power_state(pdev, PCI_D3hot);
3436 #ifdef JME_NEW_PM_API
3437 jme_resume(struct device *dev)
3439 jme_resume(struct pci_dev *pdev)
3442 #ifdef JME_NEW_PM_API
3443 struct pci_dev *pdev = to_pci_dev(dev);
3445 struct net_device *netdev = pci_get_drvdata(pdev);
3446 struct jme_adapter *jme = netdev_priv(netdev);
3449 #ifndef JME_NEW_PM_API
3450 pci_set_power_state(pdev, PCI_D0);
3451 pci_restore_state(pdev);
3455 if (test_bit(JME_FLAG_SSET, &jme->flags))
3456 jme_set_settings(netdev, &jme->old_ecmd);
3458 jme_reset_phy_processor(jme);
3461 netif_device_attach(netdev);
3463 atomic_inc(&jme->link_changing);
3465 jme_reset_link(jme);
3470 #ifdef JME_NEW_PM_API
3471 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3472 #define JME_PM_OPS (&jme_pm_ops)
3477 #ifdef JME_NEW_PM_API
3478 #define JME_PM_OPS NULL
3482 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3483 static struct pci_device_id jme_pci_tbl[] = {
3485 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3487 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3488 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3492 static struct pci_driver jme_driver = {
3494 .id_table = jme_pci_tbl,
3495 .probe = jme_init_one,
3496 .remove = __devexit_p(jme_remove_one),
3497 .shutdown = jme_shutdown,
3498 #ifndef JME_NEW_PM_API
3499 .suspend = jme_suspend,
3500 .resume = jme_resume
3502 .driver.pm = JME_PM_OPS,
3507 jme_init_module(void)
3509 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3510 return pci_register_driver(&jme_driver);
3514 jme_cleanup_module(void)
3516 pci_unregister_driver(&jme_driver);
3519 module_init(jme_init_module);
3520 module_exit(jme_cleanup_module);
3522 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3523 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3524 MODULE_LICENSE("GPL");
3525 MODULE_VERSION(DRV_VERSION);
3526 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);