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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67
68read_again:
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
72
73 wmb();
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 udelay(20);
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
78 break;
79 }
80
81 if (i == 0) {
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
83 return 0;
84 }
85
86 if (again--)
87 goto read_again;
88
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90}
91
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
102
103 wmb();
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 break;
108 }
109
110 if (i == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112}
113
114static inline void
115jme_reset_phy_processor(struct jme_adapter *jme)
116{
117 u32 val;
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
129
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
137}
138
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
165
166static inline void
167jme_mac_rxclk_off(struct jme_adapter *jme)
168{
169 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
170 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
171}
172
173static inline void
174jme_mac_rxclk_on(struct jme_adapter *jme)
175{
176 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
177 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
178}
179
180static inline void
181jme_mac_txclk_off(struct jme_adapter *jme)
182{
183 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
184 jwrite32f(jme, JME_GHC, jme->reg_ghc);
185}
186
187static inline void
188jme_mac_txclk_on(struct jme_adapter *jme)
189{
190 u32 speed = jme->reg_ghc & GHC_SPEED;
191 if (speed == GHC_SPEED_1000M)
192 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
193 else
194 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
195 jwrite32f(jme, JME_GHC, jme->reg_ghc);
196}
197
198static inline void
199jme_reset_ghc_speed(struct jme_adapter *jme)
200{
201 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
202 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
206jme_reset_250A2_workaround(struct jme_adapter *jme)
207{
208 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
209 GPREG1_RSSPATCH);
210 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
211}
212
213static inline void
214jme_assert_ghc_reset(struct jme_adapter *jme)
215{
216 jme->reg_ghc |= GHC_SWRST;
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_clear_ghc_reset(struct jme_adapter *jme)
222{
223 jme->reg_ghc &= ~GHC_SWRST;
224 jwrite32f(jme, JME_GHC, jme->reg_ghc);
225}
226
227static inline void
228jme_reset_mac_processor(struct jme_adapter *jme)
229{
230 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
231 u32 crc = 0xCDCDCDCD;
232 u32 gpreg0;
233 int i;
234
235 jme_reset_ghc_speed(jme);
236 jme_reset_250A2_workaround(jme);
237
238 jme_mac_rxclk_on(jme);
239 jme_mac_txclk_on(jme);
240 udelay(1);
241 jme_assert_ghc_reset(jme);
242 udelay(1);
243 jme_mac_rxclk_off(jme);
244 jme_mac_txclk_off(jme);
245 udelay(1);
246 jme_clear_ghc_reset(jme);
247 udelay(1);
248 jme_mac_rxclk_on(jme);
249 jme_mac_txclk_on(jme);
250 udelay(1);
251 jme_mac_rxclk_off(jme);
252 jme_mac_txclk_off(jme);
253
254 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
255 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
256 jwrite32(jme, JME_RXQDC, 0x00000000);
257 jwrite32(jme, JME_RXNDA, 0x00000000);
258 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
259 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
260 jwrite32(jme, JME_TXQDC, 0x00000000);
261 jwrite32(jme, JME_TXNDA, 0x00000000);
262
263 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
264 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
265 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
266 jme_setup_wakeup_frame(jme, mask, crc, i);
267 if (jme->fpgaver)
268 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
269 else
270 gpreg0 = GPREG0_DEFAULT;
271 jwrite32(jme, JME_GPREG0, gpreg0);
272}
273
274static inline void
275jme_clear_pm(struct jme_adapter *jme)
276{
277 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
278 pci_set_power_state(jme->pdev, PCI_D0);
279 pci_enable_wake(jme->pdev, PCI_D0, false);
280}
281
282static int
283jme_reload_eeprom(struct jme_adapter *jme)
284{
285 u32 val;
286 int i;
287
288 val = jread32(jme, JME_SMBCSR);
289
290 if (val & SMBCSR_EEPROMD) {
291 val |= SMBCSR_CNACK;
292 jwrite32(jme, JME_SMBCSR, val);
293 val |= SMBCSR_RELOAD;
294 jwrite32(jme, JME_SMBCSR, val);
295 mdelay(12);
296
297 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
298 mdelay(1);
299 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
300 break;
301 }
302
303 if (i == 0) {
304 pr_err("eeprom reload timeout\n");
305 return -EIO;
306 }
307 }
308
309 return 0;
310}
311
312static void
313jme_load_macaddr(struct net_device *netdev)
314{
315 struct jme_adapter *jme = netdev_priv(netdev);
316 unsigned char macaddr[6];
317 u32 val;
318
319 spin_lock_bh(&jme->macaddr_lock);
320 val = jread32(jme, JME_RXUMA_LO);
321 macaddr[0] = (val >> 0) & 0xFF;
322 macaddr[1] = (val >> 8) & 0xFF;
323 macaddr[2] = (val >> 16) & 0xFF;
324 macaddr[3] = (val >> 24) & 0xFF;
325 val = jread32(jme, JME_RXUMA_HI);
326 macaddr[4] = (val >> 0) & 0xFF;
327 macaddr[5] = (val >> 8) & 0xFF;
328 memcpy(netdev->dev_addr, macaddr, 6);
329 spin_unlock_bh(&jme->macaddr_lock);
330}
331
332static inline void
333jme_set_rx_pcc(struct jme_adapter *jme, int p)
334{
335 switch (p) {
336 case PCC_OFF:
337 jwrite32(jme, JME_PCCRX0,
338 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340 break;
341 case PCC_P1:
342 jwrite32(jme, JME_PCCRX0,
343 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345 break;
346 case PCC_P2:
347 jwrite32(jme, JME_PCCRX0,
348 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350 break;
351 case PCC_P3:
352 jwrite32(jme, JME_PCCRX0,
353 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
354 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
355 break;
356 default:
357 break;
358 }
359 wmb();
360
361 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
362 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
363}
364
365static void
366jme_start_irq(struct jme_adapter *jme)
367{
368 register struct dynpcc_info *dpi = &(jme->dpi);
369
370 jme_set_rx_pcc(jme, PCC_P1);
371 dpi->cur = PCC_P1;
372 dpi->attempt = PCC_P1;
373 dpi->cnt = 0;
374
375 jwrite32(jme, JME_PCCTX,
376 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
377 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
378 PCCTXQ0_EN
379 );
380
381 /*
382 * Enable Interrupts
383 */
384 jwrite32(jme, JME_IENS, INTR_ENABLE);
385}
386
387static inline void
388jme_stop_irq(struct jme_adapter *jme)
389{
390 /*
391 * Disable Interrupts
392 */
393 jwrite32f(jme, JME_IENC, INTR_ENABLE);
394}
395
396static u32
397jme_linkstat_from_phy(struct jme_adapter *jme)
398{
399 u32 phylink, bmsr;
400
401 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
402 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
403 if (bmsr & BMSR_ANCOMP)
404 phylink |= PHY_LINK_AUTONEG_COMPLETE;
405
406 return phylink;
407}
408
409static inline void
410jme_set_phyfifo_5level(struct jme_adapter *jme)
411{
412 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
413}
414
415static inline void
416jme_set_phyfifo_8level(struct jme_adapter *jme)
417{
418 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
419}
420
421static int
422jme_check_link(struct net_device *netdev, int testonly)
423{
424 struct jme_adapter *jme = netdev_priv(netdev);
425 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
426 char linkmsg[64];
427 int rc = 0;
428
429 linkmsg[0] = '\0';
430
431 if (jme->fpgaver)
432 phylink = jme_linkstat_from_phy(jme);
433 else
434 phylink = jread32(jme, JME_PHY_LINK);
435
436 if (phylink & PHY_LINK_UP) {
437 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
438 /*
439 * If we did not enable AN
440 * Speed/Duplex Info should be obtained from SMI
441 */
442 phylink = PHY_LINK_UP;
443
444 bmcr = jme_mdio_read(jme->dev,
445 jme->mii_if.phy_id,
446 MII_BMCR);
447
448 phylink |= ((bmcr & BMCR_SPEED1000) &&
449 (bmcr & BMCR_SPEED100) == 0) ?
450 PHY_LINK_SPEED_1000M :
451 (bmcr & BMCR_SPEED100) ?
452 PHY_LINK_SPEED_100M :
453 PHY_LINK_SPEED_10M;
454
455 phylink |= (bmcr & BMCR_FULLDPLX) ?
456 PHY_LINK_DUPLEX : 0;
457
458 strcat(linkmsg, "Forced: ");
459 } else {
460 /*
461 * Keep polling for speed/duplex resolve complete
462 */
463 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
464 --cnt) {
465
466 udelay(1);
467
468 if (jme->fpgaver)
469 phylink = jme_linkstat_from_phy(jme);
470 else
471 phylink = jread32(jme, JME_PHY_LINK);
472 }
473 if (!cnt)
474 pr_err("Waiting speed resolve timeout\n");
475
476 strcat(linkmsg, "ANed: ");
477 }
478
479 if (jme->phylink == phylink) {
480 rc = 1;
481 goto out;
482 }
483 if (testonly)
484 goto out;
485
486 jme->phylink = phylink;
487
488 /*
489 * The speed/duplex setting of jme->reg_ghc already cleared
490 * by jme_reset_mac_processor()
491 */
492 switch (phylink & PHY_LINK_SPEED_MASK) {
493 case PHY_LINK_SPEED_10M:
494 jme->reg_ghc |= GHC_SPEED_10M;
495 strcat(linkmsg, "10 Mbps, ");
496 break;
497 case PHY_LINK_SPEED_100M:
498 jme->reg_ghc |= GHC_SPEED_100M;
499 strcat(linkmsg, "100 Mbps, ");
500 break;
501 case PHY_LINK_SPEED_1000M:
502 jme->reg_ghc |= GHC_SPEED_1000M;
503 strcat(linkmsg, "1000 Mbps, ");
504 break;
505 default:
506 break;
507 }
508
509 if (phylink & PHY_LINK_DUPLEX) {
510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
511 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
512 jme->reg_ghc |= GHC_DPX;
513 } else {
514 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
515 TXMCS_BACKOFF |
516 TXMCS_CARRIERSENSE |
517 TXMCS_COLLISION);
518 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
519 }
520
521 jwrite32(jme, JME_GHC, jme->reg_ghc);
522
523 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
524 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
525 GPREG1_RSSPATCH);
526 if (!(phylink & PHY_LINK_DUPLEX))
527 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
528 switch (phylink & PHY_LINK_SPEED_MASK) {
529 case PHY_LINK_SPEED_10M:
530 jme_set_phyfifo_8level(jme);
531 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
532 break;
533 case PHY_LINK_SPEED_100M:
534 jme_set_phyfifo_5level(jme);
535 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
536 break;
537 case PHY_LINK_SPEED_1000M:
538 jme_set_phyfifo_8level(jme);
539 break;
540 default:
541 break;
542 }
543 }
544 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
545
546 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
547 "Full-Duplex, " :
548 "Half-Duplex, ");
549 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
550 "MDI-X" :
551 "MDI");
552 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
553 netif_carrier_on(netdev);
554 } else {
555 if (testonly)
556 goto out;
557
558 netif_info(jme, link, jme->dev, "Link is down\n");
559 jme->phylink = 0;
560 netif_carrier_off(netdev);
561 }
562
563out:
564 return rc;
565}
566
567static int
568jme_setup_tx_resources(struct jme_adapter *jme)
569{
570 struct jme_ring *txring = &(jme->txring[0]);
571
572 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 &(txring->dmaalloc),
575 GFP_ATOMIC);
576
577 if (!txring->alloc)
578 goto err_set_null;
579
580 /*
581 * 16 Bytes align
582 */
583 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
584 RING_DESC_ALIGN);
585 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
586 txring->next_to_use = 0;
587 atomic_set(&txring->next_to_clean, 0);
588 atomic_set(&txring->nr_free, jme->tx_ring_size);
589
590 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
591 jme->tx_ring_size, GFP_ATOMIC);
592 if (unlikely(!(txring->bufinf)))
593 goto err_free_txring;
594
595 /*
596 * Initialize Transmit Descriptors
597 */
598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
599 memset(txring->bufinf, 0,
600 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
601
602 return 0;
603
604err_free_txring:
605 dma_free_coherent(&(jme->pdev->dev),
606 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
607 txring->alloc,
608 txring->dmaalloc);
609
610err_set_null:
611 txring->desc = NULL;
612 txring->dmaalloc = 0;
613 txring->dma = 0;
614 txring->bufinf = NULL;
615
616 return -ENOMEM;
617}
618
619static void
620jme_free_tx_resources(struct jme_adapter *jme)
621{
622 int i;
623 struct jme_ring *txring = &(jme->txring[0]);
624 struct jme_buffer_info *txbi;
625
626 if (txring->alloc) {
627 if (txring->bufinf) {
628 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
629 txbi = txring->bufinf + i;
630 if (txbi->skb) {
631 dev_kfree_skb(txbi->skb);
632 txbi->skb = NULL;
633 }
634 txbi->mapping = 0;
635 txbi->len = 0;
636 txbi->nr_desc = 0;
637 txbi->start_xmit = 0;
638 }
639 kfree(txring->bufinf);
640 }
641
642 dma_free_coherent(&(jme->pdev->dev),
643 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
644 txring->alloc,
645 txring->dmaalloc);
646
647 txring->alloc = NULL;
648 txring->desc = NULL;
649 txring->dmaalloc = 0;
650 txring->dma = 0;
651 txring->bufinf = NULL;
652 }
653 txring->next_to_use = 0;
654 atomic_set(&txring->next_to_clean, 0);
655 atomic_set(&txring->nr_free, 0);
656}
657
658static inline void
659jme_enable_tx_engine(struct jme_adapter *jme)
660{
661 /*
662 * Select Queue 0
663 */
664 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
665 wmb();
666
667 /*
668 * Setup TX Queue 0 DMA Bass Address
669 */
670 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
671 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
672 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
673
674 /*
675 * Setup TX Descptor Count
676 */
677 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
678
679 /*
680 * Enable TX Engine
681 */
682 wmb();
683 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
686
687 /*
688 * Start clock for TX MAC Processor
689 */
690 jme_mac_txclk_on(jme);
691}
692
693static inline void
694jme_restart_tx_engine(struct jme_adapter *jme)
695{
696 /*
697 * Restart TX Engine
698 */
699 jwrite32(jme, JME_TXCS, jme->reg_txcs |
700 TXCS_SELECT_QUEUE0 |
701 TXCS_ENABLE);
702}
703
704static inline void
705jme_disable_tx_engine(struct jme_adapter *jme)
706{
707 int i;
708 u32 val;
709
710 /*
711 * Disable TX Engine
712 */
713 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
714 wmb();
715
716 val = jread32(jme, JME_TXCS);
717 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
718 mdelay(1);
719 val = jread32(jme, JME_TXCS);
720 rmb();
721 }
722
723 if (!i)
724 pr_err("Disable TX engine timeout\n");
725
726 /*
727 * Stop clock for TX MAC Processor
728 */
729 jme_mac_txclk_off(jme);
730}
731
732static void
733jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
734{
735 struct jme_ring *rxring = &(jme->rxring[0]);
736 register struct rxdesc *rxdesc = rxring->desc;
737 struct jme_buffer_info *rxbi = rxring->bufinf;
738 rxdesc += i;
739 rxbi += i;
740
741 rxdesc->dw[0] = 0;
742 rxdesc->dw[1] = 0;
743 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
744 rxdesc->desc1.bufaddrl = cpu_to_le32(
745 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
746 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
747 if (jme->dev->features & NETIF_F_HIGHDMA)
748 rxdesc->desc1.flags = RXFLAG_64BIT;
749 wmb();
750 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
751}
752
753static int
754jme_make_new_rx_buf(struct jme_adapter *jme, int i)
755{
756 struct jme_ring *rxring = &(jme->rxring[0]);
757 struct jme_buffer_info *rxbi = rxring->bufinf + i;
758 struct sk_buff *skb;
759
760 skb = netdev_alloc_skb(jme->dev,
761 jme->dev->mtu + RX_EXTRA_LEN);
762 if (unlikely(!skb))
763 return -ENOMEM;
764#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
765 skb->dev = jme->dev;
766#endif
767
768 rxbi->skb = skb;
769 rxbi->len = skb_tailroom(skb);
770 rxbi->mapping = pci_map_page(jme->pdev,
771 virt_to_page(skb->data),
772 offset_in_page(skb->data),
773 rxbi->len,
774 PCI_DMA_FROMDEVICE);
775
776 return 0;
777}
778
779static void
780jme_free_rx_buf(struct jme_adapter *jme, int i)
781{
782 struct jme_ring *rxring = &(jme->rxring[0]);
783 struct jme_buffer_info *rxbi = rxring->bufinf;
784 rxbi += i;
785
786 if (rxbi->skb) {
787 pci_unmap_page(jme->pdev,
788 rxbi->mapping,
789 rxbi->len,
790 PCI_DMA_FROMDEVICE);
791 dev_kfree_skb(rxbi->skb);
792 rxbi->skb = NULL;
793 rxbi->mapping = 0;
794 rxbi->len = 0;
795 }
796}
797
798static void
799jme_free_rx_resources(struct jme_adapter *jme)
800{
801 int i;
802 struct jme_ring *rxring = &(jme->rxring[0]);
803
804 if (rxring->alloc) {
805 if (rxring->bufinf) {
806 for (i = 0 ; i < jme->rx_ring_size ; ++i)
807 jme_free_rx_buf(jme, i);
808 kfree(rxring->bufinf);
809 }
810
811 dma_free_coherent(&(jme->pdev->dev),
812 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
813 rxring->alloc,
814 rxring->dmaalloc);
815 rxring->alloc = NULL;
816 rxring->desc = NULL;
817 rxring->dmaalloc = 0;
818 rxring->dma = 0;
819 rxring->bufinf = NULL;
820 }
821 rxring->next_to_use = 0;
822 atomic_set(&rxring->next_to_clean, 0);
823}
824
825static int
826jme_setup_rx_resources(struct jme_adapter *jme)
827{
828 int i;
829 struct jme_ring *rxring = &(jme->rxring[0]);
830
831 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
832 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833 &(rxring->dmaalloc),
834 GFP_ATOMIC);
835 if (!rxring->alloc)
836 goto err_set_null;
837
838 /*
839 * 16 Bytes align
840 */
841 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
842 RING_DESC_ALIGN);
843 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
844 rxring->next_to_use = 0;
845 atomic_set(&rxring->next_to_clean, 0);
846
847 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
848 jme->rx_ring_size, GFP_ATOMIC);
849 if (unlikely(!(rxring->bufinf)))
850 goto err_free_rxring;
851
852 /*
853 * Initiallize Receive Descriptors
854 */
855 memset(rxring->bufinf, 0,
856 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
857 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858 if (unlikely(jme_make_new_rx_buf(jme, i))) {
859 jme_free_rx_resources(jme);
860 return -ENOMEM;
861 }
862
863 jme_set_clean_rxdesc(jme, i);
864 }
865
866 return 0;
867
868err_free_rxring:
869 dma_free_coherent(&(jme->pdev->dev),
870 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->alloc,
872 rxring->dmaalloc);
873err_set_null:
874 rxring->desc = NULL;
875 rxring->dmaalloc = 0;
876 rxring->dma = 0;
877 rxring->bufinf = NULL;
878
879 return -ENOMEM;
880}
881
882static inline void
883jme_enable_rx_engine(struct jme_adapter *jme)
884{
885 /*
886 * Select Queue 0
887 */
888 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889 RXCS_QUEUESEL_Q0);
890 wmb();
891
892 /*
893 * Setup RX DMA Bass Address
894 */
895 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
896 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
897 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
898
899 /*
900 * Setup RX Descriptor Count
901 */
902 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
903
904 /*
905 * Setup Unicast Filter
906 */
907 jme_set_unicastaddr(jme->dev);
908 jme_set_multi(jme->dev);
909
910 /*
911 * Enable RX Engine
912 */
913 wmb();
914 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
915 RXCS_QUEUESEL_Q0 |
916 RXCS_ENABLE |
917 RXCS_QST);
918
919 /*
920 * Start clock for RX MAC Processor
921 */
922 jme_mac_rxclk_on(jme);
923}
924
925static inline void
926jme_restart_rx_engine(struct jme_adapter *jme)
927{
928 /*
929 * Start RX Engine
930 */
931 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
932 RXCS_QUEUESEL_Q0 |
933 RXCS_ENABLE |
934 RXCS_QST);
935}
936
937static inline void
938jme_disable_rx_engine(struct jme_adapter *jme)
939{
940 int i;
941 u32 val;
942
943 /*
944 * Disable RX Engine
945 */
946 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
947 wmb();
948
949 val = jread32(jme, JME_RXCS);
950 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
951 mdelay(1);
952 val = jread32(jme, JME_RXCS);
953 rmb();
954 }
955
956 if (!i)
957 pr_err("Disable RX engine timeout\n");
958
959 /*
960 * Stop clock for RX MAC Processor
961 */
962 jme_mac_rxclk_off(jme);
963}
964
965static int
966jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
967{
968 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
969 return false;
970
971 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
972 == RXWBFLAG_TCPON)) {
973 if (flags & RXWBFLAG_IPV4)
974 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
975 return false;
976 }
977
978 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
979 == RXWBFLAG_UDPON)) {
980 if (flags & RXWBFLAG_IPV4)
981 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
982 return false;
983 }
984
985 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
986 == RXWBFLAG_IPV4)) {
987 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
988 return false;
989 }
990
991 return true;
992}
993
994static void
995jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
996{
997 struct jme_ring *rxring = &(jme->rxring[0]);
998 struct rxdesc *rxdesc = rxring->desc;
999 struct jme_buffer_info *rxbi = rxring->bufinf;
1000 struct sk_buff *skb;
1001 int framesize;
1002
1003 rxdesc += idx;
1004 rxbi += idx;
1005
1006 skb = rxbi->skb;
1007 pci_dma_sync_single_for_cpu(jme->pdev,
1008 rxbi->mapping,
1009 rxbi->len,
1010 PCI_DMA_FROMDEVICE);
1011
1012 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1013 pci_dma_sync_single_for_device(jme->pdev,
1014 rxbi->mapping,
1015 rxbi->len,
1016 PCI_DMA_FROMDEVICE);
1017
1018 ++(NET_STAT(jme).rx_dropped);
1019 } else {
1020 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1021 - RX_PREPAD_SIZE;
1022
1023 skb_reserve(skb, RX_PREPAD_SIZE);
1024 skb_put(skb, framesize);
1025 skb->protocol = eth_type_trans(skb, jme->dev);
1026
1027 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
1028 skb->ip_summed = CHECKSUM_UNNECESSARY;
1029 else
1030#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1031 skb->ip_summed = CHECKSUM_NONE;
1032#else
1033 skb_checksum_none_assert(skb);
1034#endif
1035
1036 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1037 if (jme->vlgrp) {
1038 jme->jme_vlan_rx(skb, jme->vlgrp,
1039 le16_to_cpu(rxdesc->descwb.vlan));
1040 NET_STAT(jme).rx_bytes += 4;
1041 } else {
1042 dev_kfree_skb(skb);
1043 }
1044 } else {
1045 jme->jme_rx(skb);
1046 }
1047
1048 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1049 cpu_to_le16(RXWBFLAG_DEST_MUL))
1050 ++(NET_STAT(jme).multicast);
1051
1052 NET_STAT(jme).rx_bytes += framesize;
1053 ++(NET_STAT(jme).rx_packets);
1054 }
1055
1056 jme_set_clean_rxdesc(jme, idx);
1057
1058}
1059
1060static int
1061jme_process_receive(struct jme_adapter *jme, int limit)
1062{
1063 struct jme_ring *rxring = &(jme->rxring[0]);
1064 struct rxdesc *rxdesc = rxring->desc;
1065 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1066
1067 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1068 goto out_inc;
1069
1070 if (unlikely(atomic_read(&jme->link_changing) != 1))
1071 goto out_inc;
1072
1073 if (unlikely(!netif_carrier_ok(jme->dev)))
1074 goto out_inc;
1075
1076 i = atomic_read(&rxring->next_to_clean);
1077 while (limit > 0) {
1078 rxdesc = rxring->desc;
1079 rxdesc += i;
1080
1081 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1082 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1083 goto out;
1084 --limit;
1085
1086 rmb();
1087 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1088
1089 if (unlikely(desccnt > 1 ||
1090 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1091
1092 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1093 ++(NET_STAT(jme).rx_crc_errors);
1094 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1095 ++(NET_STAT(jme).rx_fifo_errors);
1096 else
1097 ++(NET_STAT(jme).rx_errors);
1098
1099 if (desccnt > 1)
1100 limit -= desccnt - 1;
1101
1102 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1103 jme_set_clean_rxdesc(jme, j);
1104 j = (j + 1) & (mask);
1105 }
1106
1107 } else {
1108 jme_alloc_and_feed_skb(jme, i);
1109 }
1110
1111 i = (i + desccnt) & (mask);
1112 }
1113
1114out:
1115 atomic_set(&rxring->next_to_clean, i);
1116
1117out_inc:
1118 atomic_inc(&jme->rx_cleaning);
1119
1120 return limit > 0 ? limit : 0;
1121
1122}
1123
1124static void
1125jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1126{
1127 if (likely(atmp == dpi->cur)) {
1128 dpi->cnt = 0;
1129 return;
1130 }
1131
1132 if (dpi->attempt == atmp) {
1133 ++(dpi->cnt);
1134 } else {
1135 dpi->attempt = atmp;
1136 dpi->cnt = 0;
1137 }
1138
1139}
1140
1141static void
1142jme_dynamic_pcc(struct jme_adapter *jme)
1143{
1144 register struct dynpcc_info *dpi = &(jme->dpi);
1145
1146 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1147 jme_attempt_pcc(dpi, PCC_P3);
1148 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1149 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1150 jme_attempt_pcc(dpi, PCC_P2);
1151 else
1152 jme_attempt_pcc(dpi, PCC_P1);
1153
1154 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1155 if (dpi->attempt < dpi->cur)
1156 tasklet_schedule(&jme->rxclean_task);
1157 jme_set_rx_pcc(jme, dpi->attempt);
1158 dpi->cur = dpi->attempt;
1159 dpi->cnt = 0;
1160 }
1161}
1162
1163static void
1164jme_start_pcc_timer(struct jme_adapter *jme)
1165{
1166 struct dynpcc_info *dpi = &(jme->dpi);
1167 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1168 dpi->last_pkts = NET_STAT(jme).rx_packets;
1169 dpi->intr_cnt = 0;
1170 jwrite32(jme, JME_TMCSR,
1171 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1172}
1173
1174static inline void
1175jme_stop_pcc_timer(struct jme_adapter *jme)
1176{
1177 jwrite32(jme, JME_TMCSR, 0);
1178}
1179
1180static void
1181jme_shutdown_nic(struct jme_adapter *jme)
1182{
1183 u32 phylink;
1184
1185 phylink = jme_linkstat_from_phy(jme);
1186
1187 if (!(phylink & PHY_LINK_UP)) {
1188 /*
1189 * Disable all interrupt before issue timer
1190 */
1191 jme_stop_irq(jme);
1192 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1193 }
1194}
1195
1196static void
1197jme_pcc_tasklet(unsigned long arg)
1198{
1199 struct jme_adapter *jme = (struct jme_adapter *)arg;
1200 struct net_device *netdev = jme->dev;
1201
1202 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1203 jme_shutdown_nic(jme);
1204 return;
1205 }
1206
1207 if (unlikely(!netif_carrier_ok(netdev) ||
1208 (atomic_read(&jme->link_changing) != 1)
1209 )) {
1210 jme_stop_pcc_timer(jme);
1211 return;
1212 }
1213
1214 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1215 jme_dynamic_pcc(jme);
1216
1217 jme_start_pcc_timer(jme);
1218}
1219
1220static inline void
1221jme_polling_mode(struct jme_adapter *jme)
1222{
1223 jme_set_rx_pcc(jme, PCC_OFF);
1224}
1225
1226static inline void
1227jme_interrupt_mode(struct jme_adapter *jme)
1228{
1229 jme_set_rx_pcc(jme, PCC_P1);
1230}
1231
1232static inline int
1233jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1234{
1235 u32 apmc;
1236 apmc = jread32(jme, JME_APMC);
1237 return apmc & JME_APMC_PSEUDO_HP_EN;
1238}
1239
1240static void
1241jme_start_shutdown_timer(struct jme_adapter *jme)
1242{
1243 u32 apmc;
1244
1245 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1246 apmc &= ~JME_APMC_EPIEN_CTRL;
1247 if (!no_extplug) {
1248 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1249 wmb();
1250 }
1251 jwrite32f(jme, JME_APMC, apmc);
1252
1253 jwrite32f(jme, JME_TIMER2, 0);
1254 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1255 jwrite32(jme, JME_TMCSR,
1256 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1257}
1258
1259static void
1260jme_stop_shutdown_timer(struct jme_adapter *jme)
1261{
1262 u32 apmc;
1263
1264 jwrite32f(jme, JME_TMCSR, 0);
1265 jwrite32f(jme, JME_TIMER2, 0);
1266 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1267
1268 apmc = jread32(jme, JME_APMC);
1269 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1270 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1271 wmb();
1272 jwrite32f(jme, JME_APMC, apmc);
1273}
1274
1275static void
1276jme_link_change_tasklet(unsigned long arg)
1277{
1278 struct jme_adapter *jme = (struct jme_adapter *)arg;
1279 struct net_device *netdev = jme->dev;
1280 int rc;
1281
1282 while (!atomic_dec_and_test(&jme->link_changing)) {
1283 atomic_inc(&jme->link_changing);
1284 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1285 while (atomic_read(&jme->link_changing) != 1)
1286 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1287 }
1288
1289 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1290 goto out;
1291
1292 jme->old_mtu = netdev->mtu;
1293 netif_stop_queue(netdev);
1294 if (jme_pseudo_hotplug_enabled(jme))
1295 jme_stop_shutdown_timer(jme);
1296
1297 jme_stop_pcc_timer(jme);
1298 tasklet_disable(&jme->txclean_task);
1299 tasklet_disable(&jme->rxclean_task);
1300 tasklet_disable(&jme->rxempty_task);
1301
1302 if (netif_carrier_ok(netdev)) {
1303 jme_disable_rx_engine(jme);
1304 jme_disable_tx_engine(jme);
1305 jme_reset_mac_processor(jme);
1306 jme_free_rx_resources(jme);
1307 jme_free_tx_resources(jme);
1308
1309 if (test_bit(JME_FLAG_POLL, &jme->flags))
1310 jme_polling_mode(jme);
1311
1312 netif_carrier_off(netdev);
1313 }
1314
1315 jme_check_link(netdev, 0);
1316 if (netif_carrier_ok(netdev)) {
1317 rc = jme_setup_rx_resources(jme);
1318 if (rc) {
1319 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1320 goto out_enable_tasklet;
1321 }
1322
1323 rc = jme_setup_tx_resources(jme);
1324 if (rc) {
1325 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1326 goto err_out_free_rx_resources;
1327 }
1328
1329 jme_enable_rx_engine(jme);
1330 jme_enable_tx_engine(jme);
1331
1332 netif_start_queue(netdev);
1333
1334 if (test_bit(JME_FLAG_POLL, &jme->flags))
1335 jme_interrupt_mode(jme);
1336
1337 jme_start_pcc_timer(jme);
1338 } else if (jme_pseudo_hotplug_enabled(jme)) {
1339 jme_start_shutdown_timer(jme);
1340 }
1341
1342 goto out_enable_tasklet;
1343
1344err_out_free_rx_resources:
1345 jme_free_rx_resources(jme);
1346out_enable_tasklet:
1347 tasklet_enable(&jme->txclean_task);
1348 tasklet_hi_enable(&jme->rxclean_task);
1349 tasklet_hi_enable(&jme->rxempty_task);
1350out:
1351 atomic_inc(&jme->link_changing);
1352}
1353
1354static void
1355jme_rx_clean_tasklet(unsigned long arg)
1356{
1357 struct jme_adapter *jme = (struct jme_adapter *)arg;
1358 struct dynpcc_info *dpi = &(jme->dpi);
1359
1360 jme_process_receive(jme, jme->rx_ring_size);
1361 ++(dpi->intr_cnt);
1362
1363}
1364
1365static int
1366jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1367{
1368 struct jme_adapter *jme = jme_napi_priv(holder);
1369 DECLARE_NETDEV
1370 int rest;
1371
1372 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1373
1374 while (atomic_read(&jme->rx_empty) > 0) {
1375 atomic_dec(&jme->rx_empty);
1376 ++(NET_STAT(jme).rx_dropped);
1377 jme_restart_rx_engine(jme);
1378 }
1379 atomic_inc(&jme->rx_empty);
1380
1381 if (rest) {
1382 JME_RX_COMPLETE(netdev, holder);
1383 jme_interrupt_mode(jme);
1384 }
1385
1386 JME_NAPI_WEIGHT_SET(budget, rest);
1387 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1388}
1389
1390static void
1391jme_rx_empty_tasklet(unsigned long arg)
1392{
1393 struct jme_adapter *jme = (struct jme_adapter *)arg;
1394
1395 if (unlikely(atomic_read(&jme->link_changing) != 1))
1396 return;
1397
1398 if (unlikely(!netif_carrier_ok(jme->dev)))
1399 return;
1400
1401 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1402
1403 jme_rx_clean_tasklet(arg);
1404
1405 while (atomic_read(&jme->rx_empty) > 0) {
1406 atomic_dec(&jme->rx_empty);
1407 ++(NET_STAT(jme).rx_dropped);
1408 jme_restart_rx_engine(jme);
1409 }
1410 atomic_inc(&jme->rx_empty);
1411}
1412
1413static void
1414jme_wake_queue_if_stopped(struct jme_adapter *jme)
1415{
1416 struct jme_ring *txring = &(jme->txring[0]);
1417
1418 smp_wmb();
1419 if (unlikely(netif_queue_stopped(jme->dev) &&
1420 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1421 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1422 netif_wake_queue(jme->dev);
1423 }
1424
1425}
1426
1427static void
1428jme_tx_clean_tasklet(unsigned long arg)
1429{
1430 struct jme_adapter *jme = (struct jme_adapter *)arg;
1431 struct jme_ring *txring = &(jme->txring[0]);
1432 struct txdesc *txdesc = txring->desc;
1433 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1434 int i, j, cnt = 0, max, err, mask;
1435
1436 tx_dbg(jme, "Into txclean\n");
1437
1438 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1439 goto out;
1440
1441 if (unlikely(atomic_read(&jme->link_changing) != 1))
1442 goto out;
1443
1444 if (unlikely(!netif_carrier_ok(jme->dev)))
1445 goto out;
1446
1447 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1448 mask = jme->tx_ring_mask;
1449
1450 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1451
1452 ctxbi = txbi + i;
1453
1454 if (likely(ctxbi->skb &&
1455 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1456
1457 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1458 i, ctxbi->nr_desc, jiffies);
1459
1460 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1461
1462 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1463 ttxbi = txbi + ((i + j) & (mask));
1464 txdesc[(i + j) & (mask)].dw[0] = 0;
1465
1466 pci_unmap_page(jme->pdev,
1467 ttxbi->mapping,
1468 ttxbi->len,
1469 PCI_DMA_TODEVICE);
1470
1471 ttxbi->mapping = 0;
1472 ttxbi->len = 0;
1473 }
1474
1475 dev_kfree_skb(ctxbi->skb);
1476
1477 cnt += ctxbi->nr_desc;
1478
1479 if (unlikely(err)) {
1480 ++(NET_STAT(jme).tx_carrier_errors);
1481 } else {
1482 ++(NET_STAT(jme).tx_packets);
1483 NET_STAT(jme).tx_bytes += ctxbi->len;
1484 }
1485
1486 ctxbi->skb = NULL;
1487 ctxbi->len = 0;
1488 ctxbi->start_xmit = 0;
1489
1490 } else {
1491 break;
1492 }
1493
1494 i = (i + ctxbi->nr_desc) & mask;
1495
1496 ctxbi->nr_desc = 0;
1497 }
1498
1499 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1500 atomic_set(&txring->next_to_clean, i);
1501 atomic_add(cnt, &txring->nr_free);
1502
1503 jme_wake_queue_if_stopped(jme);
1504
1505out:
1506 atomic_inc(&jme->tx_cleaning);
1507}
1508
1509static void
1510jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1511{
1512 /*
1513 * Disable interrupt
1514 */
1515 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1516
1517 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1518 /*
1519 * Link change event is critical
1520 * all other events are ignored
1521 */
1522 jwrite32(jme, JME_IEVE, intrstat);
1523 tasklet_schedule(&jme->linkch_task);
1524 goto out_reenable;
1525 }
1526
1527 if (intrstat & INTR_TMINTR) {
1528 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1529 tasklet_schedule(&jme->pcc_task);
1530 }
1531
1532 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1533 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1534 tasklet_schedule(&jme->txclean_task);
1535 }
1536
1537 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1538 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1539 INTR_PCCRX0 |
1540 INTR_RX0EMP)) |
1541 INTR_RX0);
1542 }
1543
1544 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1545 if (intrstat & INTR_RX0EMP)
1546 atomic_inc(&jme->rx_empty);
1547
1548 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1549 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1550 jme_polling_mode(jme);
1551 JME_RX_SCHEDULE(jme);
1552 }
1553 }
1554 } else {
1555 if (intrstat & INTR_RX0EMP) {
1556 atomic_inc(&jme->rx_empty);
1557 tasklet_hi_schedule(&jme->rxempty_task);
1558 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1559 tasklet_hi_schedule(&jme->rxclean_task);
1560 }
1561 }
1562
1563out_reenable:
1564 /*
1565 * Re-enable interrupt
1566 */
1567 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1568}
1569
1570#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1571static irqreturn_t
1572jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1573#else
1574static irqreturn_t
1575jme_intr(int irq, void *dev_id)
1576#endif
1577{
1578 struct net_device *netdev = dev_id;
1579 struct jme_adapter *jme = netdev_priv(netdev);
1580 u32 intrstat;
1581
1582 intrstat = jread32(jme, JME_IEVE);
1583
1584 /*
1585 * Check if it's really an interrupt for us
1586 */
1587 if (unlikely((intrstat & INTR_ENABLE) == 0))
1588 return IRQ_NONE;
1589
1590 /*
1591 * Check if the device still exist
1592 */
1593 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1594 return IRQ_NONE;
1595
1596 jme_intr_msi(jme, intrstat);
1597
1598 return IRQ_HANDLED;
1599}
1600
1601#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1602static irqreturn_t
1603jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1604#else
1605static irqreturn_t
1606jme_msi(int irq, void *dev_id)
1607#endif
1608{
1609 struct net_device *netdev = dev_id;
1610 struct jme_adapter *jme = netdev_priv(netdev);
1611 u32 intrstat;
1612
1613 intrstat = jread32(jme, JME_IEVE);
1614
1615 jme_intr_msi(jme, intrstat);
1616
1617 return IRQ_HANDLED;
1618}
1619
1620static void
1621jme_reset_link(struct jme_adapter *jme)
1622{
1623 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1624}
1625
1626static void
1627jme_restart_an(struct jme_adapter *jme)
1628{
1629 u32 bmcr;
1630
1631 spin_lock_bh(&jme->phy_lock);
1632 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1633 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1634 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1635 spin_unlock_bh(&jme->phy_lock);
1636}
1637
1638static int
1639jme_request_irq(struct jme_adapter *jme)
1640{
1641 int rc;
1642 struct net_device *netdev = jme->dev;
1643#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1644 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1645 int irq_flags = SA_SHIRQ;
1646#else
1647 irq_handler_t handler = jme_intr;
1648 int irq_flags = IRQF_SHARED;
1649#endif
1650
1651 if (!pci_enable_msi(jme->pdev)) {
1652 set_bit(JME_FLAG_MSI, &jme->flags);
1653 handler = jme_msi;
1654 irq_flags = 0;
1655 }
1656
1657 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1658 netdev);
1659 if (rc) {
1660 netdev_err(netdev,
1661 "Unable to request %s interrupt (return: %d)\n",
1662 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1663 rc);
1664
1665 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1666 pci_disable_msi(jme->pdev);
1667 clear_bit(JME_FLAG_MSI, &jme->flags);
1668 }
1669 } else {
1670 netdev->irq = jme->pdev->irq;
1671 }
1672
1673 return rc;
1674}
1675
1676static void
1677jme_free_irq(struct jme_adapter *jme)
1678{
1679 free_irq(jme->pdev->irq, jme->dev);
1680 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1681 pci_disable_msi(jme->pdev);
1682 clear_bit(JME_FLAG_MSI, &jme->flags);
1683 jme->dev->irq = jme->pdev->irq;
1684 }
1685}
1686
1687static inline void
1688jme_new_phy_on(struct jme_adapter *jme)
1689{
1690 u32 reg;
1691
1692 reg = jread32(jme, JME_PHY_PWR);
1693 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1694 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1695 jwrite32(jme, JME_PHY_PWR, reg);
1696
1697 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1698 reg &= ~PE1_GPREG0_PBG;
1699 reg |= PE1_GPREG0_ENBG;
1700 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1701}
1702
1703static inline void
1704jme_new_phy_off(struct jme_adapter *jme)
1705{
1706 u32 reg;
1707
1708 reg = jread32(jme, JME_PHY_PWR);
1709 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1710 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1711 jwrite32(jme, JME_PHY_PWR, reg);
1712
1713 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1714 reg &= ~PE1_GPREG0_PBG;
1715 reg |= PE1_GPREG0_PDD3COLD;
1716 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1717}
1718
1719static inline void
1720jme_phy_on(struct jme_adapter *jme)
1721{
1722 u32 bmcr;
1723
1724 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1725 bmcr &= ~BMCR_PDOWN;
1726 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1727
1728 if (new_phy_power_ctrl(jme->chip_main_rev))
1729 jme_new_phy_on(jme);
1730}
1731
1732static inline void
1733jme_phy_off(struct jme_adapter *jme)
1734{
1735 u32 bmcr;
1736
1737 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1738 bmcr |= BMCR_PDOWN;
1739 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1740
1741 if (new_phy_power_ctrl(jme->chip_main_rev))
1742 jme_new_phy_off(jme);
1743}
1744
1745static int
1746jme_open(struct net_device *netdev)
1747{
1748 struct jme_adapter *jme = netdev_priv(netdev);
1749 int rc;
1750
1751 jme_clear_pm(jme);
1752 JME_NAPI_ENABLE(jme);
1753
1754 tasklet_enable(&jme->linkch_task);
1755 tasklet_enable(&jme->txclean_task);
1756 tasklet_hi_enable(&jme->rxclean_task);
1757 tasklet_hi_enable(&jme->rxempty_task);
1758
1759 rc = jme_request_irq(jme);
1760 if (rc)
1761 goto err_out;
1762
1763 jme_start_irq(jme);
1764
1765 jme_phy_on(jme);
1766 if (test_bit(JME_FLAG_SSET, &jme->flags))
1767 jme_set_settings(netdev, &jme->old_ecmd);
1768 else
1769 jme_reset_phy_processor(jme);
1770
1771 jme_reset_link(jme);
1772
1773 return 0;
1774
1775err_out:
1776 netif_stop_queue(netdev);
1777 netif_carrier_off(netdev);
1778 return rc;
1779}
1780
1781static void
1782jme_set_100m_half(struct jme_adapter *jme)
1783{
1784 u32 bmcr, tmp;
1785
1786 jme_phy_on(jme);
1787 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1788 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1789 BMCR_SPEED1000 | BMCR_FULLDPLX);
1790 tmp |= BMCR_SPEED100;
1791
1792 if (bmcr != tmp)
1793 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1794
1795 if (jme->fpgaver)
1796 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1797 else
1798 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1799}
1800
1801#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1802static void
1803jme_wait_link(struct jme_adapter *jme)
1804{
1805 u32 phylink, to = JME_WAIT_LINK_TIME;
1806
1807 mdelay(1000);
1808 phylink = jme_linkstat_from_phy(jme);
1809 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1810 mdelay(10);
1811 phylink = jme_linkstat_from_phy(jme);
1812 }
1813}
1814
1815static void
1816jme_powersave_phy(struct jme_adapter *jme)
1817{
1818 if (jme->reg_pmcs) {
1819 jme_set_100m_half(jme);
1820
1821 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1822 jme_wait_link(jme);
1823
1824 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1825 } else {
1826 jme_phy_off(jme);
1827 }
1828}
1829
1830static int
1831jme_close(struct net_device *netdev)
1832{
1833 struct jme_adapter *jme = netdev_priv(netdev);
1834
1835 netif_stop_queue(netdev);
1836 netif_carrier_off(netdev);
1837
1838 jme_stop_irq(jme);
1839 jme_free_irq(jme);
1840
1841 JME_NAPI_DISABLE(jme);
1842
1843 tasklet_disable(&jme->linkch_task);
1844 tasklet_disable(&jme->txclean_task);
1845 tasklet_disable(&jme->rxclean_task);
1846 tasklet_disable(&jme->rxempty_task);
1847
1848 jme_disable_rx_engine(jme);
1849 jme_disable_tx_engine(jme);
1850 jme_reset_mac_processor(jme);
1851 jme_free_rx_resources(jme);
1852 jme_free_tx_resources(jme);
1853 jme->phylink = 0;
1854 jme_phy_off(jme);
1855
1856 return 0;
1857}
1858
1859static int
1860jme_alloc_txdesc(struct jme_adapter *jme,
1861 struct sk_buff *skb)
1862{
1863 struct jme_ring *txring = &(jme->txring[0]);
1864 int idx, nr_alloc, mask = jme->tx_ring_mask;
1865
1866 idx = txring->next_to_use;
1867 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1868
1869 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1870 return -1;
1871
1872 atomic_sub(nr_alloc, &txring->nr_free);
1873
1874 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1875
1876 return idx;
1877}
1878
1879static void
1880jme_fill_tx_map(struct pci_dev *pdev,
1881 struct txdesc *txdesc,
1882 struct jme_buffer_info *txbi,
1883 struct page *page,
1884 u32 page_offset,
1885 u32 len,
1886 u8 hidma)
1887{
1888 dma_addr_t dmaaddr;
1889
1890 dmaaddr = pci_map_page(pdev,
1891 page,
1892 page_offset,
1893 len,
1894 PCI_DMA_TODEVICE);
1895
1896 pci_dma_sync_single_for_device(pdev,
1897 dmaaddr,
1898 len,
1899 PCI_DMA_TODEVICE);
1900
1901 txdesc->dw[0] = 0;
1902 txdesc->dw[1] = 0;
1903 txdesc->desc2.flags = TXFLAG_OWN;
1904 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1905 txdesc->desc2.datalen = cpu_to_le16(len);
1906 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1907 txdesc->desc2.bufaddrl = cpu_to_le32(
1908 (__u64)dmaaddr & 0xFFFFFFFFUL);
1909
1910 txbi->mapping = dmaaddr;
1911 txbi->len = len;
1912}
1913
1914static void
1915jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1916{
1917 struct jme_ring *txring = &(jme->txring[0]);
1918 struct txdesc *txdesc = txring->desc, *ctxdesc;
1919 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1920 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1921 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1922 int mask = jme->tx_ring_mask;
1923 struct skb_frag_struct *frag;
1924 u32 len;
1925
1926 for (i = 0 ; i < nr_frags ; ++i) {
1927 frag = &skb_shinfo(skb)->frags[i];
1928 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1929 ctxbi = txbi + ((idx + i + 2) & (mask));
1930
1931 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1932 frag->page_offset, frag->size, hidma);
1933 }
1934
1935 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1936 ctxdesc = txdesc + ((idx + 1) & (mask));
1937 ctxbi = txbi + ((idx + 1) & (mask));
1938 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1939 offset_in_page(skb->data), len, hidma);
1940
1941}
1942
1943static int
1944jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1945{
1946 if (unlikely(
1947#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1948 skb_shinfo(skb)->tso_size
1949#else
1950 skb_shinfo(skb)->gso_size
1951#endif
1952 && skb_header_cloned(skb) &&
1953 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1954 dev_kfree_skb(skb);
1955 return -1;
1956 }
1957
1958 return 0;
1959}
1960
1961static int
1962jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1963{
1964#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1965 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1966#else
1967 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1968#endif
1969 if (*mss) {
1970 *flags |= TXFLAG_LSEN;
1971
1972 if (skb->protocol == htons(ETH_P_IP)) {
1973 struct iphdr *iph = ip_hdr(skb);
1974
1975 iph->check = 0;
1976 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1977 iph->daddr, 0,
1978 IPPROTO_TCP,
1979 0);
1980 } else {
1981 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1982
1983 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1984 &ip6h->daddr, 0,
1985 IPPROTO_TCP,
1986 0);
1987 }
1988
1989 return 0;
1990 }
1991
1992 return 1;
1993}
1994
1995static void
1996jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1997{
1998#ifdef CHECKSUM_PARTIAL
1999 if (skb->ip_summed == CHECKSUM_PARTIAL)
2000#else
2001 if (skb->ip_summed == CHECKSUM_HW)
2002#endif
2003 {
2004 u8 ip_proto;
2005
2006#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2007 if (skb->protocol == htons(ETH_P_IP))
2008 ip_proto = ip_hdr(skb)->protocol;
2009 else if (skb->protocol == htons(ETH_P_IPV6))
2010 ip_proto = ipv6_hdr(skb)->nexthdr;
2011 else
2012 ip_proto = 0;
2013#else
2014 switch (skb->protocol) {
2015 case htons(ETH_P_IP):
2016 ip_proto = ip_hdr(skb)->protocol;
2017 break;
2018 case htons(ETH_P_IPV6):
2019 ip_proto = ipv6_hdr(skb)->nexthdr;
2020 break;
2021 default:
2022 ip_proto = 0;
2023 break;
2024 }
2025#endif
2026
2027 switch (ip_proto) {
2028 case IPPROTO_TCP:
2029 *flags |= TXFLAG_TCPCS;
2030 break;
2031 case IPPROTO_UDP:
2032 *flags |= TXFLAG_UDPCS;
2033 break;
2034 default:
2035 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2036 break;
2037 }
2038 }
2039}
2040
2041static inline void
2042jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2043{
2044 if (vlan_tx_tag_present(skb)) {
2045 *flags |= TXFLAG_TAGON;
2046 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2047 }
2048}
2049
2050static int
2051jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2052{
2053 struct jme_ring *txring = &(jme->txring[0]);
2054 struct txdesc *txdesc;
2055 struct jme_buffer_info *txbi;
2056 u8 flags;
2057
2058 txdesc = (struct txdesc *)txring->desc + idx;
2059 txbi = txring->bufinf + idx;
2060
2061 txdesc->dw[0] = 0;
2062 txdesc->dw[1] = 0;
2063 txdesc->dw[2] = 0;
2064 txdesc->dw[3] = 0;
2065 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2066 /*
2067 * Set OWN bit at final.
2068 * When kernel transmit faster than NIC.
2069 * And NIC trying to send this descriptor before we tell
2070 * it to start sending this TX queue.
2071 * Other fields are already filled correctly.
2072 */
2073 wmb();
2074 flags = TXFLAG_OWN | TXFLAG_INT;
2075 /*
2076 * Set checksum flags while not tso
2077 */
2078 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2079 jme_tx_csum(jme, skb, &flags);
2080 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2081 jme_map_tx_skb(jme, skb, idx);
2082 txdesc->desc1.flags = flags;
2083 /*
2084 * Set tx buffer info after telling NIC to send
2085 * For better tx_clean timing
2086 */
2087 wmb();
2088 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2089 txbi->skb = skb;
2090 txbi->len = skb->len;
2091 txbi->start_xmit = jiffies;
2092 if (!txbi->start_xmit)
2093 txbi->start_xmit = (0UL-1);
2094
2095 return 0;
2096}
2097
2098static void
2099jme_stop_queue_if_full(struct jme_adapter *jme)
2100{
2101 struct jme_ring *txring = &(jme->txring[0]);
2102 struct jme_buffer_info *txbi = txring->bufinf;
2103 int idx = atomic_read(&txring->next_to_clean);
2104
2105 txbi += idx;
2106
2107 smp_wmb();
2108 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2109 netif_stop_queue(jme->dev);
2110 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2111 smp_wmb();
2112 if (atomic_read(&txring->nr_free)
2113 >= (jme->tx_wake_threshold)) {
2114 netif_wake_queue(jme->dev);
2115 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2116 }
2117 }
2118
2119 if (unlikely(txbi->start_xmit &&
2120 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2121 txbi->skb)) {
2122 netif_stop_queue(jme->dev);
2123 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2124 }
2125}
2126
2127/*
2128 * This function is already protected by netif_tx_lock()
2129 */
2130
2131#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2132static int
2133#else
2134static netdev_tx_t
2135#endif
2136jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2137{
2138 struct jme_adapter *jme = netdev_priv(netdev);
2139 int idx;
2140
2141 if (unlikely(jme_expand_header(jme, skb))) {
2142 ++(NET_STAT(jme).tx_dropped);
2143 return NETDEV_TX_OK;
2144 }
2145
2146 idx = jme_alloc_txdesc(jme, skb);
2147
2148 if (unlikely(idx < 0)) {
2149 netif_stop_queue(netdev);
2150 netif_err(jme, tx_err, jme->dev,
2151 "BUG! Tx ring full when queue awake!\n");
2152
2153 return NETDEV_TX_BUSY;
2154 }
2155
2156 jme_fill_tx_desc(jme, skb, idx);
2157
2158 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2159 TXCS_SELECT_QUEUE0 |
2160 TXCS_QUEUE0S |
2161 TXCS_ENABLE);
2162#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2163 netdev->trans_start = jiffies;
2164#endif
2165
2166 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2167 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2168 jme_stop_queue_if_full(jme);
2169
2170 return NETDEV_TX_OK;
2171}
2172
2173static void
2174jme_set_unicastaddr(struct net_device *netdev)
2175{
2176 struct jme_adapter *jme = netdev_priv(netdev);
2177 u32 val;
2178
2179 val = (netdev->dev_addr[3] & 0xff) << 24 |
2180 (netdev->dev_addr[2] & 0xff) << 16 |
2181 (netdev->dev_addr[1] & 0xff) << 8 |
2182 (netdev->dev_addr[0] & 0xff);
2183 jwrite32(jme, JME_RXUMA_LO, val);
2184 val = (netdev->dev_addr[5] & 0xff) << 8 |
2185 (netdev->dev_addr[4] & 0xff);
2186 jwrite32(jme, JME_RXUMA_HI, val);
2187}
2188
2189static int
2190jme_set_macaddr(struct net_device *netdev, void *p)
2191{
2192 struct jme_adapter *jme = netdev_priv(netdev);
2193 struct sockaddr *addr = p;
2194
2195 if (netif_running(netdev))
2196 return -EBUSY;
2197
2198 spin_lock_bh(&jme->macaddr_lock);
2199 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2200 jme_set_unicastaddr(netdev);
2201 spin_unlock_bh(&jme->macaddr_lock);
2202
2203 return 0;
2204}
2205
2206static void
2207jme_set_multi(struct net_device *netdev)
2208{
2209 struct jme_adapter *jme = netdev_priv(netdev);
2210 u32 mc_hash[2] = {};
2211#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2212 int i;
2213#endif
2214
2215 spin_lock_bh(&jme->rxmcs_lock);
2216
2217 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2218
2219 if (netdev->flags & IFF_PROMISC) {
2220 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2221 } else if (netdev->flags & IFF_ALLMULTI) {
2222 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2223 } else if (netdev->flags & IFF_MULTICAST) {
2224#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2225 struct dev_mc_list *mclist;
2226#else
2227 struct netdev_hw_addr *ha;
2228#endif
2229 int bit_nr;
2230
2231 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2232#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2233 for (i = 0, mclist = netdev->mc_list;
2234 mclist && i < netdev->mc_count;
2235 ++i, mclist = mclist->next) {
2236#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2237 netdev_for_each_mc_addr(mclist, netdev) {
2238#else
2239 netdev_for_each_mc_addr(ha, netdev) {
2240#endif
2241#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2242 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2243#else
2244 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2245#endif
2246 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2247 }
2248
2249 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2250 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2251 }
2252
2253 wmb();
2254 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2255
2256 spin_unlock_bh(&jme->rxmcs_lock);
2257}
2258
2259static int
2260jme_change_mtu(struct net_device *netdev, int new_mtu)
2261{
2262 struct jme_adapter *jme = netdev_priv(netdev);
2263
2264 if (new_mtu == jme->old_mtu)
2265 return 0;
2266
2267 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2268 ((new_mtu) < IPV6_MIN_MTU))
2269 return -EINVAL;
2270
2271 if (new_mtu > 4000) {
2272 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2273 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2274 jme_restart_rx_engine(jme);
2275 } else {
2276 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2277 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2278 jme_restart_rx_engine(jme);
2279 }
2280
2281 if (new_mtu > 1900) {
2282 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2283 NETIF_F_TSO | NETIF_F_TSO6);
2284 } else {
2285 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2286 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2287 if (test_bit(JME_FLAG_TSO, &jme->flags))
2288 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2289 }
2290
2291 netdev->mtu = new_mtu;
2292 jme_reset_link(jme);
2293
2294 return 0;
2295}
2296
2297static void
2298jme_tx_timeout(struct net_device *netdev)
2299{
2300 struct jme_adapter *jme = netdev_priv(netdev);
2301
2302 jme->phylink = 0;
2303 jme_reset_phy_processor(jme);
2304 if (test_bit(JME_FLAG_SSET, &jme->flags))
2305 jme_set_settings(netdev, &jme->old_ecmd);
2306
2307 /*
2308 * Force to Reset the link again
2309 */
2310 jme_reset_link(jme);
2311}
2312
2313static inline void jme_pause_rx(struct jme_adapter *jme)
2314{
2315 atomic_dec(&jme->link_changing);
2316
2317 jme_set_rx_pcc(jme, PCC_OFF);
2318 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2319 JME_NAPI_DISABLE(jme);
2320 } else {
2321 tasklet_disable(&jme->rxclean_task);
2322 tasklet_disable(&jme->rxempty_task);
2323 }
2324}
2325
2326static inline void jme_resume_rx(struct jme_adapter *jme)
2327{
2328 struct dynpcc_info *dpi = &(jme->dpi);
2329
2330 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2331 JME_NAPI_ENABLE(jme);
2332 } else {
2333 tasklet_hi_enable(&jme->rxclean_task);
2334 tasklet_hi_enable(&jme->rxempty_task);
2335 }
2336 dpi->cur = PCC_P1;
2337 dpi->attempt = PCC_P1;
2338 dpi->cnt = 0;
2339 jme_set_rx_pcc(jme, PCC_P1);
2340
2341 atomic_inc(&jme->link_changing);
2342}
2343
2344static void
2345jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2346{
2347 struct jme_adapter *jme = netdev_priv(netdev);
2348
2349 jme_pause_rx(jme);
2350 jme->vlgrp = grp;
2351 jme_resume_rx(jme);
2352}
2353
2354#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2355static void
2356jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2357{
2358 struct jme_adapter *jme = netdev_priv(netdev);
2359
2360 if(jme->vlgrp) {
2361 jme_pause_rx(jme);
2362#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2363 jme->vlgrp->vlan_devices[vid] = NULL;
2364#else
2365 vlan_group_set_device(jme->vlgrp, vid, NULL);
2366#endif
2367 jme_resume_rx(jme);
2368 }
2369}
2370#endif
2371
2372static void
2373jme_get_drvinfo(struct net_device *netdev,
2374 struct ethtool_drvinfo *info)
2375{
2376 struct jme_adapter *jme = netdev_priv(netdev);
2377
2378 strcpy(info->driver, DRV_NAME);
2379 strcpy(info->version, DRV_VERSION);
2380 strcpy(info->bus_info, pci_name(jme->pdev));
2381}
2382
2383static int
2384jme_get_regs_len(struct net_device *netdev)
2385{
2386 return JME_REG_LEN;
2387}
2388
2389static void
2390mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2391{
2392 int i;
2393
2394 for (i = 0 ; i < len ; i += 4)
2395 p[i >> 2] = jread32(jme, reg + i);
2396}
2397
2398static void
2399mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2400{
2401 int i;
2402 u16 *p16 = (u16 *)p;
2403
2404 for (i = 0 ; i < reg_nr ; ++i)
2405 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2406}
2407
2408static void
2409jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2410{
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412 u32 *p32 = (u32 *)p;
2413
2414 memset(p, 0xFF, JME_REG_LEN);
2415
2416 regs->version = 1;
2417 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2418
2419 p32 += 0x100 >> 2;
2420 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2421
2422 p32 += 0x100 >> 2;
2423 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2424
2425 p32 += 0x100 >> 2;
2426 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2427
2428 p32 += 0x100 >> 2;
2429 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2430}
2431
2432static int
2433jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2434{
2435 struct jme_adapter *jme = netdev_priv(netdev);
2436
2437 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2438 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2439
2440 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2441 ecmd->use_adaptive_rx_coalesce = false;
2442 ecmd->rx_coalesce_usecs = 0;
2443 ecmd->rx_max_coalesced_frames = 0;
2444 return 0;
2445 }
2446
2447 ecmd->use_adaptive_rx_coalesce = true;
2448
2449 switch (jme->dpi.cur) {
2450 case PCC_P1:
2451 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2452 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2453 break;
2454 case PCC_P2:
2455 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2456 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2457 break;
2458 case PCC_P3:
2459 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2460 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2461 break;
2462 default:
2463 break;
2464 }
2465
2466 return 0;
2467}
2468
2469static int
2470jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2471{
2472 struct jme_adapter *jme = netdev_priv(netdev);
2473 struct dynpcc_info *dpi = &(jme->dpi);
2474
2475 if (netif_running(netdev))
2476 return -EBUSY;
2477
2478 if (ecmd->use_adaptive_rx_coalesce &&
2479 test_bit(JME_FLAG_POLL, &jme->flags)) {
2480 clear_bit(JME_FLAG_POLL, &jme->flags);
2481 jme->jme_rx = netif_rx;
2482 jme->jme_vlan_rx = vlan_hwaccel_rx;
2483 dpi->cur = PCC_P1;
2484 dpi->attempt = PCC_P1;
2485 dpi->cnt = 0;
2486 jme_set_rx_pcc(jme, PCC_P1);
2487 jme_interrupt_mode(jme);
2488 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2489 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2490 set_bit(JME_FLAG_POLL, &jme->flags);
2491 jme->jme_rx = netif_receive_skb;
2492 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2493 jme_interrupt_mode(jme);
2494 }
2495
2496 return 0;
2497}
2498
2499static void
2500jme_get_pauseparam(struct net_device *netdev,
2501 struct ethtool_pauseparam *ecmd)
2502{
2503 struct jme_adapter *jme = netdev_priv(netdev);
2504 u32 val;
2505
2506 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2507 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2508
2509 spin_lock_bh(&jme->phy_lock);
2510 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2511 spin_unlock_bh(&jme->phy_lock);
2512
2513 ecmd->autoneg =
2514 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2515}
2516
2517static int
2518jme_set_pauseparam(struct net_device *netdev,
2519 struct ethtool_pauseparam *ecmd)
2520{
2521 struct jme_adapter *jme = netdev_priv(netdev);
2522 u32 val;
2523
2524 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2525 (ecmd->tx_pause != 0)) {
2526
2527 if (ecmd->tx_pause)
2528 jme->reg_txpfc |= TXPFC_PF_EN;
2529 else
2530 jme->reg_txpfc &= ~TXPFC_PF_EN;
2531
2532 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2533 }
2534
2535 spin_lock_bh(&jme->rxmcs_lock);
2536 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2537 (ecmd->rx_pause != 0)) {
2538
2539 if (ecmd->rx_pause)
2540 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2541 else
2542 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2543
2544 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2545 }
2546 spin_unlock_bh(&jme->rxmcs_lock);
2547
2548 spin_lock_bh(&jme->phy_lock);
2549 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2550 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2551 (ecmd->autoneg != 0)) {
2552
2553 if (ecmd->autoneg)
2554 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2555 else
2556 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2557
2558 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2559 MII_ADVERTISE, val);
2560 }
2561 spin_unlock_bh(&jme->phy_lock);
2562
2563 return 0;
2564}
2565
2566static void
2567jme_get_wol(struct net_device *netdev,
2568 struct ethtool_wolinfo *wol)
2569{
2570 struct jme_adapter *jme = netdev_priv(netdev);
2571
2572 wol->supported = WAKE_MAGIC | WAKE_PHY;
2573
2574 wol->wolopts = 0;
2575
2576 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2577 wol->wolopts |= WAKE_PHY;
2578
2579 if (jme->reg_pmcs & PMCS_MFEN)
2580 wol->wolopts |= WAKE_MAGIC;
2581
2582}
2583
2584static int
2585jme_set_wol(struct net_device *netdev,
2586 struct ethtool_wolinfo *wol)
2587{
2588 struct jme_adapter *jme = netdev_priv(netdev);
2589
2590 if (wol->wolopts & (WAKE_MAGICSECURE |
2591 WAKE_UCAST |
2592 WAKE_MCAST |
2593 WAKE_BCAST |
2594 WAKE_ARP))
2595 return -EOPNOTSUPP;
2596
2597 jme->reg_pmcs = 0;
2598
2599 if (wol->wolopts & WAKE_PHY)
2600 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2601
2602 if (wol->wolopts & WAKE_MAGIC)
2603 jme->reg_pmcs |= PMCS_MFEN;
2604
2605 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2606
2607 return 0;
2608}
2609
2610static int
2611jme_get_settings(struct net_device *netdev,
2612 struct ethtool_cmd *ecmd)
2613{
2614 struct jme_adapter *jme = netdev_priv(netdev);
2615 int rc;
2616
2617 spin_lock_bh(&jme->phy_lock);
2618 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2619 spin_unlock_bh(&jme->phy_lock);
2620 return rc;
2621}
2622
2623static int
2624jme_set_settings(struct net_device *netdev,
2625 struct ethtool_cmd *ecmd)
2626{
2627 struct jme_adapter *jme = netdev_priv(netdev);
2628 int rc, fdc = 0;
2629
2630 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2631 return -EINVAL;
2632
2633 /*
2634 * Check If user changed duplex only while force_media.
2635 * Hardware would not generate link change interrupt.
2636 */
2637 if (jme->mii_if.force_media &&
2638 ecmd->autoneg != AUTONEG_ENABLE &&
2639 (jme->mii_if.full_duplex != ecmd->duplex))
2640 fdc = 1;
2641
2642 spin_lock_bh(&jme->phy_lock);
2643 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2644 spin_unlock_bh(&jme->phy_lock);
2645
2646 if (!rc) {
2647 if (fdc)
2648 jme_reset_link(jme);
2649 jme->old_ecmd = *ecmd;
2650 set_bit(JME_FLAG_SSET, &jme->flags);
2651 }
2652
2653 return rc;
2654}
2655
2656static int
2657jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2658{
2659 int rc;
2660 struct jme_adapter *jme = netdev_priv(netdev);
2661 struct mii_ioctl_data *mii_data = if_mii(rq);
2662 unsigned int duplex_chg;
2663
2664 if (cmd == SIOCSMIIREG) {
2665 u16 val = mii_data->val_in;
2666 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2667 (val & BMCR_SPEED1000))
2668 return -EINVAL;
2669 }
2670
2671 spin_lock_bh(&jme->phy_lock);
2672 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2673 spin_unlock_bh(&jme->phy_lock);
2674
2675 if (!rc && (cmd == SIOCSMIIREG)) {
2676 if (duplex_chg)
2677 jme_reset_link(jme);
2678 jme_get_settings(netdev, &jme->old_ecmd);
2679 set_bit(JME_FLAG_SSET, &jme->flags);
2680 }
2681
2682 return rc;
2683}
2684
2685static u32
2686jme_get_link(struct net_device *netdev)
2687{
2688 struct jme_adapter *jme = netdev_priv(netdev);
2689 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2690}
2691
2692static u32
2693jme_get_msglevel(struct net_device *netdev)
2694{
2695 struct jme_adapter *jme = netdev_priv(netdev);
2696 return jme->msg_enable;
2697}
2698
2699static void
2700jme_set_msglevel(struct net_device *netdev, u32 value)
2701{
2702 struct jme_adapter *jme = netdev_priv(netdev);
2703 jme->msg_enable = value;
2704}
2705
2706static u32
2707jme_get_rx_csum(struct net_device *netdev)
2708{
2709 struct jme_adapter *jme = netdev_priv(netdev);
2710 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2711}
2712
2713static int
2714jme_set_rx_csum(struct net_device *netdev, u32 on)
2715{
2716 struct jme_adapter *jme = netdev_priv(netdev);
2717
2718 spin_lock_bh(&jme->rxmcs_lock);
2719 if (on)
2720 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2721 else
2722 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2723 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2724 spin_unlock_bh(&jme->rxmcs_lock);
2725
2726 return 0;
2727}
2728
2729static int
2730jme_set_tx_csum(struct net_device *netdev, u32 on)
2731{
2732 struct jme_adapter *jme = netdev_priv(netdev);
2733
2734 if (on) {
2735 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2736 if (netdev->mtu <= 1900)
2737 netdev->features |=
2738 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2739 } else {
2740 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2741 netdev->features &=
2742 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2743 }
2744
2745 return 0;
2746}
2747
2748static int
2749jme_set_tso(struct net_device *netdev, u32 on)
2750{
2751 struct jme_adapter *jme = netdev_priv(netdev);
2752
2753 if (on) {
2754 set_bit(JME_FLAG_TSO, &jme->flags);
2755 if (netdev->mtu <= 1900)
2756 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2757 } else {
2758 clear_bit(JME_FLAG_TSO, &jme->flags);
2759 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2760 }
2761
2762 return 0;
2763}
2764
2765static int
2766jme_nway_reset(struct net_device *netdev)
2767{
2768 struct jme_adapter *jme = netdev_priv(netdev);
2769 jme_restart_an(jme);
2770 return 0;
2771}
2772
2773static u8
2774jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2775{
2776 u32 val;
2777 int to;
2778
2779 val = jread32(jme, JME_SMBCSR);
2780 to = JME_SMB_BUSY_TIMEOUT;
2781 while ((val & SMBCSR_BUSY) && --to) {
2782 msleep(1);
2783 val = jread32(jme, JME_SMBCSR);
2784 }
2785 if (!to) {
2786 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2787 return 0xFF;
2788 }
2789
2790 jwrite32(jme, JME_SMBINTF,
2791 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2792 SMBINTF_HWRWN_READ |
2793 SMBINTF_HWCMD);
2794
2795 val = jread32(jme, JME_SMBINTF);
2796 to = JME_SMB_BUSY_TIMEOUT;
2797 while ((val & SMBINTF_HWCMD) && --to) {
2798 msleep(1);
2799 val = jread32(jme, JME_SMBINTF);
2800 }
2801 if (!to) {
2802 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2803 return 0xFF;
2804 }
2805
2806 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2807}
2808
2809static void
2810jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2811{
2812 u32 val;
2813 int to;
2814
2815 val = jread32(jme, JME_SMBCSR);
2816 to = JME_SMB_BUSY_TIMEOUT;
2817 while ((val & SMBCSR_BUSY) && --to) {
2818 msleep(1);
2819 val = jread32(jme, JME_SMBCSR);
2820 }
2821 if (!to) {
2822 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2823 return;
2824 }
2825
2826 jwrite32(jme, JME_SMBINTF,
2827 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2828 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2829 SMBINTF_HWRWN_WRITE |
2830 SMBINTF_HWCMD);
2831
2832 val = jread32(jme, JME_SMBINTF);
2833 to = JME_SMB_BUSY_TIMEOUT;
2834 while ((val & SMBINTF_HWCMD) && --to) {
2835 msleep(1);
2836 val = jread32(jme, JME_SMBINTF);
2837 }
2838 if (!to) {
2839 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2840 return;
2841 }
2842
2843 mdelay(2);
2844}
2845
2846static int
2847jme_get_eeprom_len(struct net_device *netdev)
2848{
2849 struct jme_adapter *jme = netdev_priv(netdev);
2850 u32 val;
2851 val = jread32(jme, JME_SMBCSR);
2852 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2853}
2854
2855static int
2856jme_get_eeprom(struct net_device *netdev,
2857 struct ethtool_eeprom *eeprom, u8 *data)
2858{
2859 struct jme_adapter *jme = netdev_priv(netdev);
2860 int i, offset = eeprom->offset, len = eeprom->len;
2861
2862 /*
2863 * ethtool will check the boundary for us
2864 */
2865 eeprom->magic = JME_EEPROM_MAGIC;
2866 for (i = 0 ; i < len ; ++i)
2867 data[i] = jme_smb_read(jme, i + offset);
2868
2869 return 0;
2870}
2871
2872static int
2873jme_set_eeprom(struct net_device *netdev,
2874 struct ethtool_eeprom *eeprom, u8 *data)
2875{
2876 struct jme_adapter *jme = netdev_priv(netdev);
2877 int i, offset = eeprom->offset, len = eeprom->len;
2878
2879 if (eeprom->magic != JME_EEPROM_MAGIC)
2880 return -EINVAL;
2881
2882 /*
2883 * ethtool will check the boundary for us
2884 */
2885 for (i = 0 ; i < len ; ++i)
2886 jme_smb_write(jme, i + offset, data[i]);
2887
2888 return 0;
2889}
2890
2891#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2892static struct ethtool_ops jme_ethtool_ops = {
2893#else
2894static const struct ethtool_ops jme_ethtool_ops = {
2895#endif
2896 .get_drvinfo = jme_get_drvinfo,
2897 .get_regs_len = jme_get_regs_len,
2898 .get_regs = jme_get_regs,
2899 .get_coalesce = jme_get_coalesce,
2900 .set_coalesce = jme_set_coalesce,
2901 .get_pauseparam = jme_get_pauseparam,
2902 .set_pauseparam = jme_set_pauseparam,
2903 .get_wol = jme_get_wol,
2904 .set_wol = jme_set_wol,
2905 .get_settings = jme_get_settings,
2906 .set_settings = jme_set_settings,
2907 .get_link = jme_get_link,
2908 .get_msglevel = jme_get_msglevel,
2909 .set_msglevel = jme_set_msglevel,
2910 .get_rx_csum = jme_get_rx_csum,
2911 .set_rx_csum = jme_set_rx_csum,
2912 .set_tx_csum = jme_set_tx_csum,
2913 .set_tso = jme_set_tso,
2914 .set_sg = ethtool_op_set_sg,
2915 .nway_reset = jme_nway_reset,
2916 .get_eeprom_len = jme_get_eeprom_len,
2917 .get_eeprom = jme_get_eeprom,
2918 .set_eeprom = jme_set_eeprom,
2919};
2920
2921static int
2922jme_pci_dma64(struct pci_dev *pdev)
2923{
2924 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2925#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2926 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2927#else
2928 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2929#endif
2930 )
2931#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2932 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2933#else
2934 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2935#endif
2936 return 1;
2937
2938 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2939#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2940 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2941#else
2942 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2943#endif
2944 )
2945#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2946 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2947#else
2948 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2949#endif
2950 return 1;
2951
2952#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2953 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2954 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2955#else
2956 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2957 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2958#endif
2959 return 0;
2960
2961 return -1;
2962}
2963
2964static inline void
2965jme_phy_init(struct jme_adapter *jme)
2966{
2967 u16 reg26;
2968
2969 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2970 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2971}
2972
2973static inline void
2974jme_check_hw_ver(struct jme_adapter *jme)
2975{
2976 u32 chipmode;
2977
2978 chipmode = jread32(jme, JME_CHIPMODE);
2979
2980 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2981 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2982 jme->chip_main_rev = jme->chiprev & 0xF;
2983 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2984}
2985
2986#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2987static const struct net_device_ops jme_netdev_ops = {
2988 .ndo_open = jme_open,
2989 .ndo_stop = jme_close,
2990 .ndo_validate_addr = eth_validate_addr,
2991 .ndo_do_ioctl = jme_ioctl,
2992 .ndo_start_xmit = jme_start_xmit,
2993 .ndo_set_mac_address = jme_set_macaddr,
2994 .ndo_set_multicast_list = jme_set_multi,
2995 .ndo_change_mtu = jme_change_mtu,
2996 .ndo_tx_timeout = jme_tx_timeout,
2997 .ndo_vlan_rx_register = jme_vlan_rx_register,
2998};
2999#endif
3000
3001static int __devinit
3002jme_init_one(struct pci_dev *pdev,
3003 const struct pci_device_id *ent)
3004{
3005 int rc = 0, using_dac, i;
3006 struct net_device *netdev;
3007 struct jme_adapter *jme;
3008 u16 bmcr, bmsr;
3009 u32 apmc;
3010
3011 /*
3012 * set up PCI device basics
3013 */
3014 rc = pci_enable_device(pdev);
3015 if (rc) {
3016 pr_err("Cannot enable PCI device\n");
3017 goto err_out;
3018 }
3019
3020 using_dac = jme_pci_dma64(pdev);
3021 if (using_dac < 0) {
3022 pr_err("Cannot set PCI DMA Mask\n");
3023 rc = -EIO;
3024 goto err_out_disable_pdev;
3025 }
3026
3027 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3028 pr_err("No PCI resource region found\n");
3029 rc = -ENOMEM;
3030 goto err_out_disable_pdev;
3031 }
3032
3033 rc = pci_request_regions(pdev, DRV_NAME);
3034 if (rc) {
3035 pr_err("Cannot obtain PCI resource region\n");
3036 goto err_out_disable_pdev;
3037 }
3038
3039 pci_set_master(pdev);
3040
3041 /*
3042 * alloc and init net device
3043 */
3044 netdev = alloc_etherdev(sizeof(*jme));
3045 if (!netdev) {
3046 pr_err("Cannot allocate netdev structure\n");
3047 rc = -ENOMEM;
3048 goto err_out_release_regions;
3049 }
3050#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051 netdev->netdev_ops = &jme_netdev_ops;
3052#else
3053 netdev->open = jme_open;
3054 netdev->stop = jme_close;
3055 netdev->do_ioctl = jme_ioctl;
3056 netdev->hard_start_xmit = jme_start_xmit;
3057 netdev->set_mac_address = jme_set_macaddr;
3058 netdev->set_multicast_list = jme_set_multi;
3059 netdev->change_mtu = jme_change_mtu;
3060 netdev->tx_timeout = jme_tx_timeout;
3061 netdev->vlan_rx_register = jme_vlan_rx_register;
3062#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3063 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3064#endif
3065 NETDEV_GET_STATS(netdev, &jme_get_stats);
3066#endif
3067 netdev->ethtool_ops = &jme_ethtool_ops;
3068 netdev->watchdog_timeo = TX_TIMEOUT;
3069 netdev->features = NETIF_F_IP_CSUM |
3070 NETIF_F_IPV6_CSUM |
3071 NETIF_F_SG |
3072 NETIF_F_TSO |
3073 NETIF_F_TSO6 |
3074 NETIF_F_HW_VLAN_TX |
3075 NETIF_F_HW_VLAN_RX;
3076 if (using_dac)
3077 netdev->features |= NETIF_F_HIGHDMA;
3078
3079 SET_NETDEV_DEV(netdev, &pdev->dev);
3080 pci_set_drvdata(pdev, netdev);
3081
3082 /*
3083 * init adapter info
3084 */
3085 jme = netdev_priv(netdev);
3086 jme->pdev = pdev;
3087 jme->dev = netdev;
3088 jme->jme_rx = netif_rx;
3089 jme->jme_vlan_rx = vlan_hwaccel_rx;
3090 jme->old_mtu = netdev->mtu = 1500;
3091 jme->phylink = 0;
3092 jme->tx_ring_size = 1 << 10;
3093 jme->tx_ring_mask = jme->tx_ring_size - 1;
3094 jme->tx_wake_threshold = 1 << 9;
3095 jme->rx_ring_size = 1 << 9;
3096 jme->rx_ring_mask = jme->rx_ring_size - 1;
3097 jme->msg_enable = JME_DEF_MSG_ENABLE;
3098 jme->regs = ioremap(pci_resource_start(pdev, 0),
3099 pci_resource_len(pdev, 0));
3100 if (!(jme->regs)) {
3101 pr_err("Mapping PCI resource region error\n");
3102 rc = -ENOMEM;
3103 goto err_out_free_netdev;
3104 }
3105
3106 if (no_pseudohp) {
3107 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3108 jwrite32(jme, JME_APMC, apmc);
3109 } else if (force_pseudohp) {
3110 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3111 jwrite32(jme, JME_APMC, apmc);
3112 }
3113
3114 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3115
3116 spin_lock_init(&jme->phy_lock);
3117 spin_lock_init(&jme->macaddr_lock);
3118 spin_lock_init(&jme->rxmcs_lock);
3119
3120 atomic_set(&jme->link_changing, 1);
3121 atomic_set(&jme->rx_cleaning, 1);
3122 atomic_set(&jme->tx_cleaning, 1);
3123 atomic_set(&jme->rx_empty, 1);
3124
3125 tasklet_init(&jme->pcc_task,
3126 jme_pcc_tasklet,
3127 (unsigned long) jme);
3128 tasklet_init(&jme->linkch_task,
3129 jme_link_change_tasklet,
3130 (unsigned long) jme);
3131 tasklet_init(&jme->txclean_task,
3132 jme_tx_clean_tasklet,
3133 (unsigned long) jme);
3134 tasklet_init(&jme->rxclean_task,
3135 jme_rx_clean_tasklet,
3136 (unsigned long) jme);
3137 tasklet_init(&jme->rxempty_task,
3138 jme_rx_empty_tasklet,
3139 (unsigned long) jme);
3140 tasklet_disable_nosync(&jme->linkch_task);
3141 tasklet_disable_nosync(&jme->txclean_task);
3142 tasklet_disable_nosync(&jme->rxclean_task);
3143 tasklet_disable_nosync(&jme->rxempty_task);
3144 jme->dpi.cur = PCC_P1;
3145
3146 jme->reg_ghc = 0;
3147 jme->reg_rxcs = RXCS_DEFAULT;
3148 jme->reg_rxmcs = RXMCS_DEFAULT;
3149 jme->reg_txpfc = 0;
3150 jme->reg_pmcs = PMCS_MFEN;
3151 jme->reg_gpreg1 = GPREG1_DEFAULT;
3152 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3153 set_bit(JME_FLAG_TSO, &jme->flags);
3154
3155 /*
3156 * Get Max Read Req Size from PCI Config Space
3157 */
3158 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3159 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3160 switch (jme->mrrs) {
3161 case MRRS_128B:
3162 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3163 break;
3164 case MRRS_256B:
3165 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3166 break;
3167 default:
3168 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3169 break;
3170 }
3171
3172 /*
3173 * Must check before reset_mac_processor
3174 */
3175 jme_check_hw_ver(jme);
3176 jme->mii_if.dev = netdev;
3177 if (jme->fpgaver) {
3178 jme->mii_if.phy_id = 0;
3179 for (i = 1 ; i < 32 ; ++i) {
3180 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3181 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3182 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3183 jme->mii_if.phy_id = i;
3184 break;
3185 }
3186 }
3187
3188 if (!jme->mii_if.phy_id) {
3189 rc = -EIO;
3190 pr_err("Can not find phy_id\n");
3191 goto err_out_unmap;
3192 }
3193
3194 jme->reg_ghc |= GHC_LINK_POLL;
3195 } else {
3196 jme->mii_if.phy_id = 1;
3197 }
3198 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3199 jme->mii_if.supports_gmii = true;
3200 else
3201 jme->mii_if.supports_gmii = false;
3202 jme->mii_if.phy_id_mask = 0x1F;
3203 jme->mii_if.reg_num_mask = 0x1F;
3204 jme->mii_if.mdio_read = jme_mdio_read;
3205 jme->mii_if.mdio_write = jme_mdio_write;
3206
3207 jme_clear_pm(jme);
3208 jme_set_phyfifo_5level(jme);
3209 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3210 if (!jme->fpgaver)
3211 jme_phy_init(jme);
3212 jme_phy_off(jme);
3213
3214 /*
3215 * Reset MAC processor and reload EEPROM for MAC Address
3216 */
3217 jme_reset_mac_processor(jme);
3218 rc = jme_reload_eeprom(jme);
3219 if (rc) {
3220 pr_err("Reload eeprom for reading MAC Address error\n");
3221 goto err_out_unmap;
3222 }
3223 jme_load_macaddr(netdev);
3224
3225 /*
3226 * Tell stack that we are not ready to work until open()
3227 */
3228 netif_carrier_off(netdev);
3229
3230 rc = register_netdev(netdev);
3231 if (rc) {
3232 pr_err("Cannot register net device\n");
3233 goto err_out_unmap;
3234 }
3235
3236 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3237 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3238 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3239 "JMC250 Gigabit Ethernet" :
3240 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3241 "JMC260 Fast Ethernet" : "Unknown",
3242 (jme->fpgaver != 0) ? " (FPGA)" : "",
3243 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3244 jme->pcirev,
3245 netdev->dev_addr[0],
3246 netdev->dev_addr[1],
3247 netdev->dev_addr[2],
3248 netdev->dev_addr[3],
3249 netdev->dev_addr[4],
3250 netdev->dev_addr[5]);
3251
3252 return 0;
3253
3254err_out_unmap:
3255 iounmap(jme->regs);
3256err_out_free_netdev:
3257 pci_set_drvdata(pdev, NULL);
3258 free_netdev(netdev);
3259err_out_release_regions:
3260 pci_release_regions(pdev);
3261err_out_disable_pdev:
3262 pci_disable_device(pdev);
3263err_out:
3264 return rc;
3265}
3266
3267static void __devexit
3268jme_remove_one(struct pci_dev *pdev)
3269{
3270 struct net_device *netdev = pci_get_drvdata(pdev);
3271 struct jme_adapter *jme = netdev_priv(netdev);
3272
3273 unregister_netdev(netdev);
3274 iounmap(jme->regs);
3275 pci_set_drvdata(pdev, NULL);
3276 free_netdev(netdev);
3277 pci_release_regions(pdev);
3278 pci_disable_device(pdev);
3279
3280}
3281
3282static void
3283jme_shutdown(struct pci_dev *pdev)
3284{
3285 struct net_device *netdev = pci_get_drvdata(pdev);
3286 struct jme_adapter *jme = netdev_priv(netdev);
3287
3288 jme_powersave_phy(jme);
3289#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3290 pci_enable_wake(pdev, PCI_D3hot, true);
3291#else
3292 pci_pme_active(pdev, true);
3293#endif
3294}
3295
3296#ifdef CONFIG_PM
3297static int
3298jme_suspend(struct pci_dev *pdev, pm_message_t state)
3299{
3300 struct net_device *netdev = pci_get_drvdata(pdev);
3301 struct jme_adapter *jme = netdev_priv(netdev);
3302
3303 atomic_dec(&jme->link_changing);
3304
3305 netif_device_detach(netdev);
3306 netif_stop_queue(netdev);
3307 jme_stop_irq(jme);
3308
3309 tasklet_disable(&jme->txclean_task);
3310 tasklet_disable(&jme->rxclean_task);
3311 tasklet_disable(&jme->rxempty_task);
3312
3313 if (netif_carrier_ok(netdev)) {
3314 if (test_bit(JME_FLAG_POLL, &jme->flags))
3315 jme_polling_mode(jme);
3316
3317 jme_stop_pcc_timer(jme);
3318 jme_disable_rx_engine(jme);
3319 jme_disable_tx_engine(jme);
3320 jme_reset_mac_processor(jme);
3321 jme_free_rx_resources(jme);
3322 jme_free_tx_resources(jme);
3323 netif_carrier_off(netdev);
3324 jme->phylink = 0;
3325 }
3326
3327 tasklet_enable(&jme->txclean_task);
3328 tasklet_hi_enable(&jme->rxclean_task);
3329 tasklet_hi_enable(&jme->rxempty_task);
3330
3331 pci_save_state(pdev);
3332 jme_powersave_phy(jme);
3333#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3334 pci_enable_wake(pdev, PCI_D3hot, true);
3335#else
3336 pci_pme_active(pdev, true);
3337#endif
3338 pci_set_power_state(pdev, PCI_D3hot);
3339
3340 return 0;
3341}
3342
3343static int
3344jme_resume(struct pci_dev *pdev)
3345{
3346 struct net_device *netdev = pci_get_drvdata(pdev);
3347 struct jme_adapter *jme = netdev_priv(netdev);
3348
3349 jme_clear_pm(jme);
3350 pci_restore_state(pdev);
3351
3352 jme_phy_on(jme);
3353 if (test_bit(JME_FLAG_SSET, &jme->flags))
3354 jme_set_settings(netdev, &jme->old_ecmd);
3355 else
3356 jme_reset_phy_processor(jme);
3357
3358 jme_start_irq(jme);
3359 netif_device_attach(netdev);
3360
3361 atomic_inc(&jme->link_changing);
3362
3363 jme_reset_link(jme);
3364
3365 return 0;
3366}
3367#endif
3368
3369#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3370static struct pci_device_id jme_pci_tbl[] = {
3371#else
3372static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3373#endif
3374 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3375 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3376 { }
3377};
3378
3379static struct pci_driver jme_driver = {
3380 .name = DRV_NAME,
3381 .id_table = jme_pci_tbl,
3382 .probe = jme_init_one,
3383 .remove = __devexit_p(jme_remove_one),
3384#ifdef CONFIG_PM
3385 .suspend = jme_suspend,
3386 .resume = jme_resume,
3387#endif /* CONFIG_PM */
3388 .shutdown = jme_shutdown,
3389};
3390
3391static int __init
3392jme_init_module(void)
3393{
3394 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3395 return pci_register_driver(&jme_driver);
3396}
3397
3398static void __exit
3399jme_cleanup_module(void)
3400{
3401 pci_unregister_driver(&jme_driver);
3402}
3403
3404module_init(jme_init_module);
3405module_exit(jme_cleanup_module);
3406
3407MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3408MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3409MODULE_LICENSE("GPL");
3410MODULE_VERSION(DRV_VERSION);
3411MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3412
JMicron Ethernet Linux driver