2 * Routines to indentify caches on Intel CPU.
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
18 #include <asm/processor.h>
19 #include <linux/smp.h>
30 unsigned char descriptor;
35 #define MB(x) ((x) * 1024)
37 /* All the cache descriptor types we care about (no TLB or
38 trace cache entries) */
40 static const struct _cache_table __cpuinitconst cache_table[] =
42 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
43 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
44 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
45 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
46 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
48 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
49 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
50 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
51 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
52 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
53 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
54 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
55 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
56 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
57 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
58 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
59 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
60 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
62 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
63 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
64 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
65 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
66 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
67 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
68 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
69 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
70 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
71 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
72 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
73 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
74 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
75 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
76 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
78 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
79 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
80 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
81 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
82 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
83 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
84 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
85 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
86 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
87 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
88 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
89 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
90 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
91 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
92 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
93 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
94 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
95 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
96 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
97 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
98 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
99 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
100 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
101 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
102 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
103 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
104 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
105 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
106 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
107 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
108 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
109 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
110 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
119 CACHE_TYPE_UNIFIED = 3
122 union _cpuid4_leaf_eax {
124 enum _cache_type type:5;
125 unsigned int level:3;
126 unsigned int is_self_initializing:1;
127 unsigned int is_fully_associative:1;
128 unsigned int reserved:4;
129 unsigned int num_threads_sharing:12;
130 unsigned int num_cores_on_die:6;
135 union _cpuid4_leaf_ebx {
137 unsigned int coherency_line_size:12;
138 unsigned int physical_line_partition:10;
139 unsigned int ways_of_associativity:10;
144 union _cpuid4_leaf_ecx {
146 unsigned int number_of_sets:32;
151 struct _cpuid4_info {
152 union _cpuid4_leaf_eax eax;
153 union _cpuid4_leaf_ebx ebx;
154 union _cpuid4_leaf_ecx ecx;
157 unsigned int l3_indices;
158 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
161 /* subset of above _cpuid4_info w/o shared_cpu_map */
162 struct _cpuid4_info_regs {
163 union _cpuid4_leaf_eax eax;
164 union _cpuid4_leaf_ebx ebx;
165 union _cpuid4_leaf_ecx ecx;
168 unsigned int l3_indices;
171 unsigned short num_cache_leaves;
173 /* AMD doesn't have CPUID4. Emulate it here to report the same
174 information to the user. This makes some assumptions about the machine:
175 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
177 In theory the TLBs could be reported as fake type (they are in "dummy").
181 unsigned line_size:8;
182 unsigned lines_per_tag:8;
184 unsigned size_in_kb:8;
191 unsigned line_size:8;
192 unsigned lines_per_tag:4;
194 unsigned size_in_kb:16;
201 unsigned line_size:8;
202 unsigned lines_per_tag:4;
205 unsigned size_encoded:14;
210 static const unsigned short __cpuinitconst assocs[] = {
221 [0xf] = 0xffff /* fully associative - no way to show this currently */
224 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
225 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
227 static void __cpuinit
228 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
229 union _cpuid4_leaf_ebx *ebx,
230 union _cpuid4_leaf_ecx *ecx)
233 unsigned line_size, lines_per_tag, assoc, size_in_kb;
234 union l1_cache l1i, l1d;
237 union l1_cache *l1 = &l1d;
243 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
244 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
252 assoc = assocs[l1->assoc];
253 line_size = l1->line_size;
254 lines_per_tag = l1->lines_per_tag;
255 size_in_kb = l1->size_in_kb;
260 assoc = assocs[l2.assoc];
261 line_size = l2.line_size;
262 lines_per_tag = l2.lines_per_tag;
263 /* cpu_data has errata corrections for K7 applied */
264 size_in_kb = current_cpu_data.x86_cache_size;
269 assoc = assocs[l3.assoc];
270 line_size = l3.line_size;
271 lines_per_tag = l3.lines_per_tag;
272 size_in_kb = l3.size_encoded * 512;
273 if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
274 size_in_kb = size_in_kb >> 1;
282 eax->split.is_self_initializing = 1;
283 eax->split.type = types[leaf];
284 eax->split.level = levels[leaf];
285 eax->split.num_threads_sharing = 0;
286 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
290 eax->split.is_fully_associative = 1;
291 ebx->split.coherency_line_size = line_size - 1;
292 ebx->split.ways_of_associativity = assoc - 1;
293 ebx->split.physical_line_partition = lines_per_tag - 1;
294 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
295 (ebx->split.ways_of_associativity + 1) - 1;
299 struct attribute attr;
300 ssize_t (*show)(struct _cpuid4_info *, char *);
301 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
304 #ifdef CONFIG_CPU_SUP_AMD
305 static unsigned int __cpuinit amd_calc_l3_indices(void)
308 * We're called over smp_call_function_single() and therefore
309 * are on the correct cpu.
311 int cpu = smp_processor_id();
312 int node = cpu_to_node(cpu);
313 struct pci_dev *dev = node_to_k8_nb_misc(node);
314 unsigned int sc0, sc1, sc2, sc3;
317 pci_read_config_dword(dev, 0x1C4, &val);
319 /* calculate subcache sizes */
320 sc0 = !(val & BIT(0));
321 sc1 = !(val & BIT(4));
322 sc2 = !(val & BIT(8)) + !(val & BIT(9));
323 sc3 = !(val & BIT(12)) + !(val & BIT(13));
325 return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
328 static void __cpuinit
329 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
331 if (boot_cpu_data.x86 != 0x10)
337 /* see errata #382 and #388 */
338 if (boot_cpu_data.x86_model < 0x8)
341 if ((boot_cpu_data.x86_model == 0x8 ||
342 boot_cpu_data.x86_model == 0x9)
344 boot_cpu_data.x86_mask < 0x1)
347 this_leaf->can_disable = true;
348 this_leaf->l3_indices = amd_calc_l3_indices();
351 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
354 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
355 int node = amd_get_nb_id(cpu);
356 struct pci_dev *dev = node_to_k8_nb_misc(node);
357 unsigned int reg = 0;
359 if (!this_leaf->can_disable)
365 pci_read_config_dword(dev, 0x1BC + index * 4, ®);
366 return sprintf(buf, "0x%08x\n", reg);
369 #define SHOW_CACHE_DISABLE(index) \
371 show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
373 return show_cache_disable(this_leaf, buf, index); \
375 SHOW_CACHE_DISABLE(0)
376 SHOW_CACHE_DISABLE(1)
378 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
379 const char *buf, size_t count, unsigned int index)
381 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
382 int node = amd_get_nb_id(cpu);
383 struct pci_dev *dev = node_to_k8_nb_misc(node);
384 unsigned long val = 0;
386 #define SUBCACHE_MASK (3UL << 20)
387 #define SUBCACHE_INDEX 0xfff
389 if (!this_leaf->can_disable)
392 if (!capable(CAP_SYS_ADMIN))
398 if (strict_strtoul(buf, 10, &val) < 0)
401 /* do not allow writes outside of allowed bits */
402 if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
403 ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
407 pci_write_config_dword(dev, 0x1BC + index * 4, val);
409 * We need to WBINVD on a core on the node containing the L3 cache which
410 * indices we disable therefore a simple wbinvd() is not sufficient.
413 pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
417 #define STORE_CACHE_DISABLE(index) \
419 store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
420 const char *buf, size_t count) \
422 return store_cache_disable(this_leaf, buf, count, index); \
424 STORE_CACHE_DISABLE(0)
425 STORE_CACHE_DISABLE(1)
427 static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
428 show_cache_disable_0, store_cache_disable_0);
429 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
430 show_cache_disable_1, store_cache_disable_1);
432 #else /* CONFIG_CPU_SUP_AMD */
433 static void __cpuinit
434 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
437 #endif /* CONFIG_CPU_SUP_AMD */
440 __cpuinit cpuid4_cache_lookup_regs(int index,
441 struct _cpuid4_info_regs *this_leaf)
443 union _cpuid4_leaf_eax eax;
444 union _cpuid4_leaf_ebx ebx;
445 union _cpuid4_leaf_ecx ecx;
448 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
449 amd_cpuid4(index, &eax, &ebx, &ecx);
450 amd_check_l3_disable(index, this_leaf);
452 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
455 if (eax.split.type == CACHE_TYPE_NULL)
456 return -EIO; /* better error ? */
458 this_leaf->eax = eax;
459 this_leaf->ebx = ebx;
460 this_leaf->ecx = ecx;
461 this_leaf->size = (ecx.split.number_of_sets + 1) *
462 (ebx.split.coherency_line_size + 1) *
463 (ebx.split.physical_line_partition + 1) *
464 (ebx.split.ways_of_associativity + 1);
468 static int __cpuinit find_num_cache_leaves(void)
470 unsigned int eax, ebx, ecx, edx;
471 union _cpuid4_leaf_eax cache_eax;
476 /* Do cpuid(4) loop to find out num_cache_leaves */
477 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
478 cache_eax.full = eax;
479 } while (cache_eax.split.type != CACHE_TYPE_NULL);
483 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
486 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
487 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
488 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
489 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
491 unsigned int cpu = c->cpu_index;
494 if (c->cpuid_level > 3) {
495 static int is_initialized;
497 if (is_initialized == 0) {
498 /* Init num_cache_leaves from boot CPU */
499 num_cache_leaves = find_num_cache_leaves();
504 * Whenever possible use cpuid(4), deterministic cache
505 * parameters cpuid leaf to find the cache details
507 for (i = 0; i < num_cache_leaves; i++) {
508 struct _cpuid4_info_regs this_leaf;
511 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
513 switch (this_leaf.eax.split.level) {
515 if (this_leaf.eax.split.type ==
517 new_l1d = this_leaf.size/1024;
518 else if (this_leaf.eax.split.type ==
520 new_l1i = this_leaf.size/1024;
523 new_l2 = this_leaf.size/1024;
524 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
525 index_msb = get_count_order(num_threads_sharing);
526 l2_id = c->apicid >> index_msb;
529 new_l3 = this_leaf.size/1024;
530 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
531 index_msb = get_count_order(
532 num_threads_sharing);
533 l3_id = c->apicid >> index_msb;
542 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
545 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
546 /* supports eax=2 call */
548 unsigned int regs[4];
549 unsigned char *dp = (unsigned char *)regs;
552 if (num_cache_leaves != 0 && c->x86 == 15)
555 /* Number of times to iterate */
556 n = cpuid_eax(2) & 0xFF;
558 for (i = 0 ; i < n ; i++) {
559 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
561 /* If bit 31 is set, this is an unknown format */
562 for (j = 0 ; j < 3 ; j++)
563 if (regs[j] & (1 << 31))
566 /* Byte 0 is level count, not a descriptor */
567 for (j = 1 ; j < 16 ; j++) {
568 unsigned char des = dp[j];
571 /* look up this descriptor in the table */
572 while (cache_table[k].descriptor != 0) {
573 if (cache_table[k].descriptor == des) {
574 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
576 switch (cache_table[k].cache_type) {
578 l1i += cache_table[k].size;
581 l1d += cache_table[k].size;
584 l2 += cache_table[k].size;
587 l3 += cache_table[k].size;
590 trace += cache_table[k].size;
612 per_cpu(cpu_llc_id, cpu) = l2_id;
619 per_cpu(cpu_llc_id, cpu) = l3_id;
623 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
630 /* pointer to _cpuid4_info array (for each cache leaf) */
631 static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
632 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
635 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
637 struct _cpuid4_info *this_leaf, *sibling_leaf;
638 unsigned long num_threads_sharing;
639 int index_msb, i, sibling;
640 struct cpuinfo_x86 *c = &cpu_data(cpu);
642 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
643 for_each_cpu(i, c->llc_shared_map) {
644 if (!per_cpu(ici_cpuid4_info, i))
646 this_leaf = CPUID4_INFO_IDX(i, index);
647 for_each_cpu(sibling, c->llc_shared_map) {
648 if (!cpu_online(sibling))
650 set_bit(sibling, this_leaf->shared_cpu_map);
655 this_leaf = CPUID4_INFO_IDX(cpu, index);
656 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
658 if (num_threads_sharing == 1)
659 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
661 index_msb = get_count_order(num_threads_sharing);
663 for_each_online_cpu(i) {
664 if (cpu_data(i).apicid >> index_msb ==
665 c->apicid >> index_msb) {
667 to_cpumask(this_leaf->shared_cpu_map));
668 if (i != cpu && per_cpu(ici_cpuid4_info, i)) {
670 CPUID4_INFO_IDX(i, index);
671 cpumask_set_cpu(cpu, to_cpumask(
672 sibling_leaf->shared_cpu_map));
678 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
680 struct _cpuid4_info *this_leaf, *sibling_leaf;
683 this_leaf = CPUID4_INFO_IDX(cpu, index);
684 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
685 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
686 cpumask_clear_cpu(cpu,
687 to_cpumask(sibling_leaf->shared_cpu_map));
691 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
695 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
700 static void __cpuinit free_cache_attributes(unsigned int cpu)
704 for (i = 0; i < num_cache_leaves; i++)
705 cache_remove_shared_cpu_map(cpu, i);
707 kfree(per_cpu(ici_cpuid4_info, cpu));
708 per_cpu(ici_cpuid4_info, cpu) = NULL;
712 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
714 struct _cpuid4_info_regs *leaf_regs =
715 (struct _cpuid4_info_regs *)this_leaf;
717 return cpuid4_cache_lookup_regs(index, leaf_regs);
720 static void __cpuinit get_cpu_leaves(void *_retval)
722 int j, *retval = _retval, cpu = smp_processor_id();
724 /* Do cpuid and store the results */
725 for (j = 0; j < num_cache_leaves; j++) {
726 struct _cpuid4_info *this_leaf;
727 this_leaf = CPUID4_INFO_IDX(cpu, j);
728 *retval = cpuid4_cache_lookup(j, this_leaf);
729 if (unlikely(*retval < 0)) {
732 for (i = 0; i < j; i++)
733 cache_remove_shared_cpu_map(cpu, i);
736 cache_shared_cpu_map_setup(cpu, j);
740 static int __cpuinit detect_cache_attributes(unsigned int cpu)
744 if (num_cache_leaves == 0)
747 per_cpu(ici_cpuid4_info, cpu) = kzalloc(
748 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
749 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
752 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
754 kfree(per_cpu(ici_cpuid4_info, cpu));
755 per_cpu(ici_cpuid4_info, cpu) = NULL;
761 #include <linux/kobject.h>
762 #include <linux/sysfs.h>
764 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
766 /* pointer to kobject for cpuX/cache */
767 static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
769 struct _index_kobject {
772 unsigned short index;
775 /* pointer to array of kobjects for cpuX/cache/indexY */
776 static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
777 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
779 #define show_one_plus(file_name, object, val) \
780 static ssize_t show_##file_name \
781 (struct _cpuid4_info *this_leaf, char *buf) \
783 return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
786 show_one_plus(level, eax.split.level, 0);
787 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
788 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
789 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
790 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
792 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
794 return sprintf(buf, "%luK\n", this_leaf->size / 1024);
797 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
800 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
804 const struct cpumask *mask;
806 mask = to_cpumask(this_leaf->shared_cpu_map);
808 cpulist_scnprintf(buf, len-2, mask) :
809 cpumask_scnprintf(buf, len-2, mask);
816 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
818 return show_shared_cpu_map_func(leaf, 0, buf);
821 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
823 return show_shared_cpu_map_func(leaf, 1, buf);
826 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
828 switch (this_leaf->eax.split.type) {
829 case CACHE_TYPE_DATA:
830 return sprintf(buf, "Data\n");
831 case CACHE_TYPE_INST:
832 return sprintf(buf, "Instruction\n");
833 case CACHE_TYPE_UNIFIED:
834 return sprintf(buf, "Unified\n");
836 return sprintf(buf, "Unknown\n");
840 #define to_object(k) container_of(k, struct _index_kobject, kobj)
841 #define to_attr(a) container_of(a, struct _cache_attr, attr)
843 #define define_one_ro(_name) \
844 static struct _cache_attr _name = \
845 __ATTR(_name, 0444, show_##_name, NULL)
847 define_one_ro(level);
849 define_one_ro(coherency_line_size);
850 define_one_ro(physical_line_partition);
851 define_one_ro(ways_of_associativity);
852 define_one_ro(number_of_sets);
854 define_one_ro(shared_cpu_map);
855 define_one_ro(shared_cpu_list);
857 #define DEFAULT_SYSFS_CACHE_ATTRS \
860 &coherency_line_size.attr, \
861 &physical_line_partition.attr, \
862 &ways_of_associativity.attr, \
863 &number_of_sets.attr, \
865 &shared_cpu_map.attr, \
866 &shared_cpu_list.attr
868 static struct attribute *default_attrs[] = {
869 DEFAULT_SYSFS_CACHE_ATTRS,
873 static struct attribute *default_l3_attrs[] = {
874 DEFAULT_SYSFS_CACHE_ATTRS,
875 #ifdef CONFIG_CPU_SUP_AMD
876 &cache_disable_0.attr,
877 &cache_disable_1.attr,
882 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
884 struct _cache_attr *fattr = to_attr(attr);
885 struct _index_kobject *this_leaf = to_object(kobj);
889 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
895 static ssize_t store(struct kobject *kobj, struct attribute *attr,
896 const char *buf, size_t count)
898 struct _cache_attr *fattr = to_attr(attr);
899 struct _index_kobject *this_leaf = to_object(kobj);
903 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
909 static const struct sysfs_ops sysfs_ops = {
914 static struct kobj_type ktype_cache = {
915 .sysfs_ops = &sysfs_ops,
916 .default_attrs = default_attrs,
919 static struct kobj_type ktype_percpu_entry = {
920 .sysfs_ops = &sysfs_ops,
923 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
925 kfree(per_cpu(ici_cache_kobject, cpu));
926 kfree(per_cpu(ici_index_kobject, cpu));
927 per_cpu(ici_cache_kobject, cpu) = NULL;
928 per_cpu(ici_index_kobject, cpu) = NULL;
929 free_cache_attributes(cpu);
932 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
936 if (num_cache_leaves == 0)
939 err = detect_cache_attributes(cpu);
943 /* Allocate all required memory */
944 per_cpu(ici_cache_kobject, cpu) =
945 kzalloc(sizeof(struct kobject), GFP_KERNEL);
946 if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
949 per_cpu(ici_index_kobject, cpu) = kzalloc(
950 sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
951 if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
957 cpuid4_cache_sysfs_exit(cpu);
961 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
963 /* Add/Remove cache interface for CPU device */
964 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
966 unsigned int cpu = sys_dev->id;
968 struct _index_kobject *this_object;
969 struct _cpuid4_info *this_leaf;
972 retval = cpuid4_cache_sysfs_init(cpu);
973 if (unlikely(retval < 0))
976 retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
978 &sys_dev->kobj, "%s", "cache");
980 cpuid4_cache_sysfs_exit(cpu);
984 for (i = 0; i < num_cache_leaves; i++) {
985 this_object = INDEX_KOBJECT_PTR(cpu, i);
986 this_object->cpu = cpu;
987 this_object->index = i;
989 this_leaf = CPUID4_INFO_IDX(cpu, i);
991 if (this_leaf->can_disable)
992 ktype_cache.default_attrs = default_l3_attrs;
994 ktype_cache.default_attrs = default_attrs;
996 retval = kobject_init_and_add(&(this_object->kobj),
998 per_cpu(ici_cache_kobject, cpu),
1000 if (unlikely(retval)) {
1001 for (j = 0; j < i; j++)
1002 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
1003 kobject_put(per_cpu(ici_cache_kobject, cpu));
1004 cpuid4_cache_sysfs_exit(cpu);
1007 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
1009 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
1011 kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
1015 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
1017 unsigned int cpu = sys_dev->id;
1020 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
1022 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
1024 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
1026 for (i = 0; i < num_cache_leaves; i++)
1027 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
1028 kobject_put(per_cpu(ici_cache_kobject, cpu));
1029 cpuid4_cache_sysfs_exit(cpu);
1032 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
1033 unsigned long action, void *hcpu)
1035 unsigned int cpu = (unsigned long)hcpu;
1036 struct sys_device *sys_dev;
1038 sys_dev = get_cpu_sysdev(cpu);
1041 case CPU_ONLINE_FROZEN:
1042 cache_add_dev(sys_dev);
1045 case CPU_DEAD_FROZEN:
1046 cache_remove_dev(sys_dev);
1052 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
1053 .notifier_call = cacheinfo_cpu_callback,
1056 static int __cpuinit cache_sysfs_init(void)
1060 if (num_cache_leaves == 0)
1063 for_each_online_cpu(i) {
1065 struct sys_device *sys_dev = get_cpu_sysdev(i);
1067 err = cache_add_dev(sys_dev);
1071 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
1075 device_initcall(cache_sysfs_init);