arch/arm/mach-omap1/clock.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.c
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *
   7  *  Modified to use omap shared clock framework by
   8  *  Tony Lindgren <tony@atomide.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21
  22 #include <asm/mach-types.h>
  23 #include <asm/clkdev.h>
  24
  25 #include <plat/cpu.h>
  26 #include <plat/usb.h>
  27 #include <plat/clock.h>
  28 #include <plat/sram.h>
  29
  30 static const struct clkops clkops_generic;
  31 static const struct clkops clkops_uart;
  32 static const struct clkops clkops_dspck;
  33
  34 #include "clock.h"
  35
  36 static int clk_omap1_dummy_enable(struct clk *clk)
  37 {
  38         return 0;
  39 }
  40
  41 static void clk_omap1_dummy_disable(struct clk *clk)
  42 {
  43 }
  44
  45 static const struct clkops clkops_dummy = {
  46         .enable = clk_omap1_dummy_enable,
  47         .disable = clk_omap1_dummy_disable,
  48 };
  49
  50 static struct clk dummy_ck = {
  51         .name   = "dummy",
  52         .ops    = &clkops_dummy,
  53         .flags  = RATE_FIXED,
  54 };
  55
  56 struct omap_clk {
  57         u32             cpu;
  58         struct clk_lookup lk;
  59 };
  60
  61 #define CLK(dev, con, ck, cp)           \
  62         {                               \
  63                  .cpu = cp,             \
  64                 .lk = {                 \
  65                         .dev_id = dev,  \
  66                         .con_id = con,  \
  67                         .clk = ck,      \
  68                 },                      \
  69         }
  70
  71 #define CK_310  (1 << 0)
  72 #define CK_7XX  (1 << 1)
  73 #define CK_1510 (1 << 2)
  74 #define CK_16XX (1 << 3)
  75
  76 static struct omap_clk omap_clks[] = {
  77         /* non-ULPD clocks */
  78         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
  79         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
  80         /* CK_GEN1 clocks */
  81         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
  82         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
  83         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
  84         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
  85         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
  86         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
  87         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
  88         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
  89         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
  90         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
  91         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
  92         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
  93         /* CK_GEN2 clocks */
  94         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
  95         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
  96         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
  97         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
  98         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
  99         /* CK_GEN3 clocks */
 100         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 101         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 102         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 103         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 104         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 105         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 106         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 107         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
 108         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 109         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 110         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 111         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 112         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 113         /* ULPD clocks */
 114         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 115         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 116         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 117         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 118         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 119         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 120         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 121         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 122         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 123         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 124         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 125         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 126         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 127         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 128         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 129         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 130         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 131         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 132         /* Virtual clocks */
 133         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 134         CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
 135         CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
 136         CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
 137         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 138         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 139         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 140         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 141         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 142         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 143         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 144         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 145         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 146         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 147 };
 148
 149 static int omap1_clk_enable_generic(struct clk * clk);
 150 static int omap1_clk_enable(struct clk *clk);
 151 static void omap1_clk_disable_generic(struct clk * clk);
 152 static void omap1_clk_disable(struct clk *clk);
 153
 154 __u32 arm_idlect1_mask;
 155
 156 /*-------------------------------------------------------------------------
 157  * Omap1 specific clock functions
 158  *-------------------------------------------------------------------------*/
 159
 160 static unsigned long omap1_watchdog_recalc(struct clk *clk)
 161 {
 162         return clk->parent->rate / 14;
 163 }
 164
 165 static unsigned long omap1_uart_recalc(struct clk *clk)
 166 {
 167         unsigned int val = __raw_readl(clk->enable_reg);
 168         return val & clk->enable_bit ? 48000000 : 12000000;
 169 }
 170
 171 static unsigned long omap1_sossi_recalc(struct clk *clk)
 172 {
 173         u32 div = omap_readl(MOD_CONF_CTRL_1);
 174
 175         div = (div >> 17) & 0x7;
 176         div++;
 177
 178         return clk->parent->rate / div;
 179 }
 180
 181 static int omap1_clk_enable_dsp_domain(struct clk *clk)
 182 {
 183         int retval;
 184
 185         retval = omap1_clk_enable(&api_ck.clk);
 186         if (!retval) {
 187                 retval = omap1_clk_enable_generic(clk);
 188                 omap1_clk_disable(&api_ck.clk);
 189         }
 190
 191         return retval;
 192 }
 193
 194 static void omap1_clk_disable_dsp_domain(struct clk *clk)
 195 {
 196         if (omap1_clk_enable(&api_ck.clk) == 0) {
 197                 omap1_clk_disable_generic(clk);
 198                 omap1_clk_disable(&api_ck.clk);
 199         }
 200 }
 201
 202 static const struct clkops clkops_dspck = {
 203         .enable         = &omap1_clk_enable_dsp_domain,
 204         .disable        = &omap1_clk_disable_dsp_domain,
 205 };
 206
 207 static int omap1_clk_enable_uart_functional(struct clk *clk)
 208 {
 209         int ret;
 210         struct uart_clk *uclk;
 211
 212         ret = omap1_clk_enable_generic(clk);
 213         if (ret == 0) {
 214                 /* Set smart idle acknowledgement mode */
 215                 uclk = (struct uart_clk *)clk;
 216                 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
 217                             uclk->sysc_addr);
 218         }
 219
 220         return ret;
 221 }
 222
 223 static void omap1_clk_disable_uart_functional(struct clk *clk)
 224 {
 225         struct uart_clk *uclk;
 226
 227         /* Set force idle acknowledgement mode */
 228         uclk = (struct uart_clk *)clk;
 229         omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
 230
 231         omap1_clk_disable_generic(clk);
 232 }
 233
 234 static const struct clkops clkops_uart = {
 235         .enable         = &omap1_clk_enable_uart_functional,
 236         .disable        = &omap1_clk_disable_uart_functional,
 237 };
 238
 239 static void omap1_clk_allow_idle(struct clk *clk)
 240 {
 241         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 242
 243         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 244                 return;
 245
 246         if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
 247                 arm_idlect1_mask |= 1 << iclk->idlect_shift;
 248 }
 249
 250 static void omap1_clk_deny_idle(struct clk *clk)
 251 {
 252         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
 253
 254         if (!(clk->flags & CLOCK_IDLE_CONTROL))
 255                 return;
 256
 257         if (iclk->no_idle_count++ == 0)
 258                 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
 259 }
 260
 261 static __u16 verify_ckctl_value(__u16 newval)
 262 {
 263         /* This function checks for following limitations set
 264          * by the hardware (all conditions must be true):
 265          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 266          * ARM_CK >= TC_CK
 267          * DSP_CK >= TC_CK
 268          * DSPMMU_CK >= TC_CK
 269          *
 270          * In addition following rules are enforced:
 271          * LCD_CK <= TC_CK
 272          * ARMPER_CK <= TC_CK
 273          *
 274          * However, maximum frequencies are not checked for!
 275          */
 276         __u8 per_exp;
 277         __u8 lcd_exp;
 278         __u8 arm_exp;
 279         __u8 dsp_exp;
 280         __u8 tc_exp;
 281         __u8 dspmmu_exp;
 282
 283         per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
 284         lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
 285         arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
 286         dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
 287         tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
 288         dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
 289
 290         if (dspmmu_exp < dsp_exp)
 291                 dspmmu_exp = dsp_exp;
 292         if (dspmmu_exp > dsp_exp+1)
 293                 dspmmu_exp = dsp_exp+1;
 294         if (tc_exp < arm_exp)
 295                 tc_exp = arm_exp;
 296         if (tc_exp < dspmmu_exp)
 297                 tc_exp = dspmmu_exp;
 298         if (tc_exp > lcd_exp)
 299                 lcd_exp = tc_exp;
 300         if (tc_exp > per_exp)
 301                 per_exp = tc_exp;
 302
 303         newval &= 0xf000;
 304         newval |= per_exp << CKCTL_PERDIV_OFFSET;
 305         newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
 306         newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
 307         newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
 308         newval |= tc_exp << CKCTL_TCDIV_OFFSET;
 309         newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
 310
 311         return newval;
 312 }
 313
 314 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
 315 {
 316         /* Note: If target frequency is too low, this function will return 4,
 317          * which is invalid value. Caller must check for this value and act
 318          * accordingly.
 319          *
 320          * Note: This function does not check for following limitations set
 321          * by the hardware (all conditions must be true):
 322          * DSPMMU_CK == DSP_CK  or  DSPMMU_CK == DSP_CK/2
 323          * ARM_CK >= TC_CK
 324          * DSP_CK >= TC_CK
 325          * DSPMMU_CK >= TC_CK
 326          */
 327         unsigned long realrate;
 328         struct clk * parent;
 329         unsigned  dsor_exp;
 330
 331         parent = clk->parent;
 332         if (unlikely(parent == NULL))
 333                 return -EIO;
 334
 335         realrate = parent->rate;
 336         for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
 337                 if (realrate <= rate)
 338                         break;
 339
 340                 realrate /= 2;
 341         }
 342
 343         return dsor_exp;
 344 }
 345
 346 static unsigned long omap1_ckctl_recalc(struct clk *clk)
 347 {
 348         /* Calculate divisor encoded as 2-bit exponent */
 349         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
 350
 351         return clk->parent->rate / dsor;
 352 }
 353
 354 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 355 {
 356         int dsor;
 357
 358         /* Calculate divisor encoded as 2-bit exponent
 359          *
 360          * The clock control bits are in DSP domain,
 361          * so api_ck is needed for access.
 362          * Note that DSP_CKCTL virt addr = phys addr, so
 363          * we must use __raw_readw() instead of omap_readw().
 364          */
 365         omap1_clk_enable(&api_ck.clk);
 366         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
 367         omap1_clk_disable(&api_ck.clk);
 368
 369         return clk->parent->rate / dsor;
 370 }
 371
 372 /* MPU virtual clock functions */
 373 static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 374 {
 375         /* Find the highest supported frequency <= rate and switch to it */
 376         struct mpu_rate * ptr;
 377
 378         if (clk != &virtual_ck_mpu)
 379                 return -EINVAL;
 380
 381         for (ptr = rate_table; ptr->rate; ptr++) {
 382                 if (ptr->xtal != ck_ref.rate)
 383                         continue;
 384
 385                 /* DPLL1 cannot be reprogrammed without risking system crash */
 386                 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
 387                         continue;
 388
 389                 /* Can check only after xtal frequency check */
 390                 if (ptr->rate <= rate)
 391                         break;
 392         }
 393
 394         if (!ptr->rate)
 395                 return -EINVAL;
 396
 397         /*
 398          * In most cases we should not need to reprogram DPLL.
 399          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 400          * (on 730, bit 13 must always be 1)
 401          */
 402         if (cpu_is_omap7xx())
 403                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 404         else
 405                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 406
 407         ck_dpll1.rate = ptr->pll_rate;
 408         return 0;
 409 }
 410
 411 static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 412 {
 413         int dsor_exp;
 414         u16 regval;
 415
 416         dsor_exp = calc_dsor_exp(clk, rate);
 417         if (dsor_exp > 3)
 418                 dsor_exp = -EINVAL;
 419         if (dsor_exp < 0)
 420                 return dsor_exp;
 421
 422         regval = __raw_readw(DSP_CKCTL);
 423         regval &= ~(3 << clk->rate_offset);
 424         regval |= dsor_exp << clk->rate_offset;
 425         __raw_writew(regval, DSP_CKCTL);
 426         clk->rate = clk->parent->rate / (1 << dsor_exp);
 427
 428         return 0;
 429 }
 430
 431 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 432 {
 433         int dsor_exp = calc_dsor_exp(clk, rate);
 434         if (dsor_exp < 0)
 435                 return dsor_exp;
 436         if (dsor_exp > 3)
 437                 dsor_exp = 3;
 438         return clk->parent->rate / (1 << dsor_exp);
 439 }
 440
 441 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 442 {
 443         int dsor_exp;
 444         u16 regval;
 445
 446         dsor_exp = calc_dsor_exp(clk, rate);
 447         if (dsor_exp > 3)
 448                 dsor_exp = -EINVAL;
 449         if (dsor_exp < 0)
 450                 return dsor_exp;
 451
 452         regval = omap_readw(ARM_CKCTL);
 453         regval &= ~(3 << clk->rate_offset);
 454         regval |= dsor_exp << clk->rate_offset;
 455         regval = verify_ckctl_value(regval);
 456         omap_writew(regval, ARM_CKCTL);
 457         clk->rate = clk->parent->rate / (1 << dsor_exp);
 458         return 0;
 459 }
 460
 461 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
 462 {
 463         /* Find the highest supported frequency <= rate */
 464         struct mpu_rate * ptr;
 465         long  highest_rate;
 466
 467         if (clk != &virtual_ck_mpu)
 468                 return -EINVAL;
 469
 470         highest_rate = -EINVAL;
 471
 472         for (ptr = rate_table; ptr->rate; ptr++) {
 473                 if (ptr->xtal != ck_ref.rate)
 474                         continue;
 475
 476                 highest_rate = ptr->rate;
 477
 478                 /* Can check only after xtal frequency check */
 479                 if (ptr->rate <= rate)
 480                         break;
 481         }
 482
 483         return highest_rate;
 484 }
 485
 486 static unsigned calc_ext_dsor(unsigned long rate)
 487 {
 488         unsigned dsor;
 489
 490         /* MCLK and BCLK divisor selection is not linear:
 491          * freq = 96MHz / dsor
 492          *
 493          * RATIO_SEL range: dsor <-> RATIO_SEL
 494          * 0..6: (RATIO_SEL+2) <-> (dsor-2)
 495          * 6..48:  (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
 496          * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
 497          * can not be used.
 498          */
 499         for (dsor = 2; dsor < 96; ++dsor) {
 500                 if ((dsor & 1) && dsor > 8)
 501                         continue;
 502                 if (rate >= 96000000 / dsor)
 503                         break;
 504         }
 505         return dsor;
 506 }
 507
 508 /* Only needed on 1510 */
 509 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 510 {
 511         unsigned int val;
 512
 513         val = __raw_readl(clk->enable_reg);
 514         if (rate == 12000000)
 515                 val &= ~(1 << clk->enable_bit);
 516         else if (rate == 48000000)
 517                 val |= (1 << clk->enable_bit);
 518         else
 519                 return -EINVAL;
 520         __raw_writel(val, clk->enable_reg);
 521         clk->rate = rate;
 522
 523         return 0;
 524 }
 525
 526 /* External clock (MCLK & BCLK) functions */
 527 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
 528 {
 529         unsigned dsor;
 530         __u16 ratio_bits;
 531
 532         dsor = calc_ext_dsor(rate);
 533         clk->rate = 96000000 / dsor;
 534         if (dsor > 8)
 535                 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
 536         else
 537                 ratio_bits = (dsor - 2) << 2;
 538
 539         ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
 540         __raw_writew(ratio_bits, clk->enable_reg);
 541
 542         return 0;
 543 }
 544
 545 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 546 {
 547         u32 l;
 548         int div;
 549         unsigned long p_rate;
 550
 551         p_rate = clk->parent->rate;
 552         /* Round towards slower frequency */
 553         div = (p_rate + rate - 1) / rate;
 554         div--;
 555         if (div < 0 || div > 7)
 556                 return -EINVAL;
 557
 558         l = omap_readl(MOD_CONF_CTRL_1);
 559         l &= ~(7 << 17);
 560         l |= div << 17;
 561         omap_writel(l, MOD_CONF_CTRL_1);
 562
 563         clk->rate = p_rate / (div + 1);
 564
 565         return 0;
 566 }
 567
 568 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
 569 {
 570         return 96000000 / calc_ext_dsor(rate);
 571 }
 572
 573 static void omap1_init_ext_clk(struct clk * clk)
 574 {
 575         unsigned dsor;
 576         __u16 ratio_bits;
 577
 578         /* Determine current rate and ensure clock is based on 96MHz APLL */
 579         ratio_bits = __raw_readw(clk->enable_reg) & ~1;
 580         __raw_writew(ratio_bits, clk->enable_reg);
 581
 582         ratio_bits = (ratio_bits & 0xfc) >> 2;
 583         if (ratio_bits > 6)
 584                 dsor = (ratio_bits - 6) * 2 + 8;
 585         else
 586                 dsor = ratio_bits + 2;
 587
 588         clk-> rate = 96000000 / dsor;
 589 }
 590
 591 static int omap1_clk_enable(struct clk *clk)
 592 {
 593         int ret = 0;
 594
 595         if (clk->usecount++ == 0) {
 596                 if (clk->parent) {
 597                         ret = omap1_clk_enable(clk->parent);
 598                         if (ret)
 599                                 goto err;
 600
 601                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 602                                 omap1_clk_deny_idle(clk->parent);
 603                 }
 604
 605                 ret = clk->ops->enable(clk);
 606                 if (ret) {
 607                         if (clk->parent)
 608                                 omap1_clk_disable(clk->parent);
 609                         goto err;
 610                 }
 611         }
 612         return ret;
 613
 614 err:
 615         clk->usecount--;
 616         return ret;
 617 }
 618
 619 static void omap1_clk_disable(struct clk *clk)
 620 {
 621         if (clk->usecount > 0 && !(--clk->usecount)) {
 622                 clk->ops->disable(clk);
 623                 if (likely(clk->parent)) {
 624                         omap1_clk_disable(clk->parent);
 625                         if (clk->flags & CLOCK_NO_IDLE_PARENT)
 626                                 omap1_clk_allow_idle(clk->parent);
 627                 }
 628         }
 629 }
 630
 631 static int omap1_clk_enable_generic(struct clk *clk)
 632 {
 633         __u16 regval16;
 634         __u32 regval32;
 635
 636         if (unlikely(clk->enable_reg == NULL)) {
 637                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
 638                        clk->name);
 639                 return -EINVAL;
 640         }
 641
 642         if (clk->flags & ENABLE_REG_32BIT) {
 643                 regval32 = __raw_readl(clk->enable_reg);
 644                 regval32 |= (1 << clk->enable_bit);
 645                 __raw_writel(regval32, clk->enable_reg);
 646         } else {
 647                 regval16 = __raw_readw(clk->enable_reg);
 648                 regval16 |= (1 << clk->enable_bit);
 649                 __raw_writew(regval16, clk->enable_reg);
 650         }
 651
 652         return 0;
 653 }
 654
 655 static void omap1_clk_disable_generic(struct clk *clk)
 656 {
 657         __u16 regval16;
 658         __u32 regval32;
 659
 660         if (clk->enable_reg == NULL)
 661                 return;
 662
 663         if (clk->flags & ENABLE_REG_32BIT) {
 664                 regval32 = __raw_readl(clk->enable_reg);
 665                 regval32 &= ~(1 << clk->enable_bit);
 666                 __raw_writel(regval32, clk->enable_reg);
 667         } else {
 668                 regval16 = __raw_readw(clk->enable_reg);
 669                 regval16 &= ~(1 << clk->enable_bit);
 670                 __raw_writew(regval16, clk->enable_reg);
 671         }
 672 }
 673
 674 static const struct clkops clkops_generic = {
 675         .enable         = &omap1_clk_enable_generic,
 676         .disable        = &omap1_clk_disable_generic,
 677 };
 678
 679 static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 680 {
 681         if (clk->flags & RATE_FIXED)
 682                 return clk->rate;
 683
 684         if (clk->round_rate != NULL)
 685                 return clk->round_rate(clk, rate);
 686
 687         return clk->rate;
 688 }
 689
 690 static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 691 {
 692         int  ret = -EINVAL;
 693
 694         if (clk->set_rate)
 695                 ret = clk->set_rate(clk, rate);
 696         return ret;
 697 }
 698
 699 /*-------------------------------------------------------------------------
 700  * Omap1 clock reset and init functions
 701  *-------------------------------------------------------------------------*/
 702
 703 #ifdef CONFIG_OMAP_RESET_CLOCKS
 704
 705 static void __init omap1_clk_disable_unused(struct clk *clk)
 706 {
 707         __u32 regval32;
 708
 709         /* Clocks in the DSP domain need api_ck. Just assume bootloader
 710          * has not enabled any DSP clocks */
 711         if (clk->enable_reg == DSP_IDLECT2) {
 712                 printk(KERN_INFO "Skipping reset check for DSP domain "
 713                        "clock \"%s\"\n", clk->name);
 714                 return;
 715         }
 716
 717         /* Is the clock already disabled? */
 718         if (clk->flags & ENABLE_REG_32BIT)
 719                 regval32 = __raw_readl(clk->enable_reg);
 720         else
 721                 regval32 = __raw_readw(clk->enable_reg);
 722
 723         if ((regval32 & (1 << clk->enable_bit)) == 0)
 724                 return;
 725
 726         /* FIXME: This clock seems to be necessary but no-one
 727          * has asked for its activation. */
 728         if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
 729             || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
 730             || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
 731                 ) {
 732                 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
 733                        clk->name);
 734                 return;
 735         }
 736
 737         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
 738         clk->ops->disable(clk);
 739         printk(" done\n");
 740 }
 741
 742 #else
 743 #define omap1_clk_disable_unused        NULL
 744 #endif
 745
 746 static struct clk_functions omap1_clk_functions = {
 747         .clk_enable             = omap1_clk_enable,
 748         .clk_disable            = omap1_clk_disable,
 749         .clk_round_rate         = omap1_clk_round_rate,
 750         .clk_set_rate           = omap1_clk_set_rate,
 751         .clk_disable_unused     = omap1_clk_disable_unused,
 752 };
 753
 754 int __init omap1_clk_init(void)
 755 {
 756         struct omap_clk *c;
 757         const struct omap_clock_config *info;
 758         int crystal_type = 0; /* Default 12 MHz */
 759         u32 reg, cpu_mask;
 760
 761 #ifdef CONFIG_DEBUG_LL
 762         /* Resets some clocks that may be left on from bootloader,
 763          * but leaves serial clocks on.
 764          */
 765         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 766 #endif
 767
 768         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 769         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 770         omap_writew(reg, SOFT_REQ_REG);
 771         if (!cpu_is_omap15xx())
 772                 omap_writew(0, SOFT_REQ_REG2);
 773
 774         clk_init(&omap1_clk_functions);
 775
 776         /* By default all idlect1 clocks are allowed to idle */
 777         arm_idlect1_mask = ~0;
 778
 779         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 780                 clk_preinit(c->lk.clk);
 781
 782         cpu_mask = 0;
 783         if (cpu_is_omap16xx())
 784                 cpu_mask |= CK_16XX;
 785         if (cpu_is_omap1510())
 786                 cpu_mask |= CK_1510;
 787         if (cpu_is_omap7xx())
 788                 cpu_mask |= CK_7XX;
 789         if (cpu_is_omap310())
 790                 cpu_mask |= CK_310;
 791
 792         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 793                 if (c->cpu & cpu_mask) {
 794                         clkdev_add(&c->lk);
 795                         clk_register(c->lk.clk);
 796                 }
 797
 798         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 799         if (info != NULL) {
 800                 if (!cpu_is_omap15xx())
 801                         crystal_type = info->system_clock_type;
 802         }
 803
 804 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 805         ck_ref.rate = 13000000;
 806 #elif defined(CONFIG_ARCH_OMAP16XX)
 807         if (crystal_type == 2)
 808                 ck_ref.rate = 19200000;
 809 #endif
 810
 811         printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
 812                omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 813                omap_readw(ARM_CKCTL));
 814
 815         /* We want to be in syncronous scalable mode */
 816         omap_writew(0x1000, ARM_SYSST);
 817
 818 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
 819         /* Use values set by bootloader. Determine PLL rate and recalculate
 820          * dependent clocks as if kernel had changed PLL or divisors.
 821          */
 822         {
 823                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 824
 825                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 826                 if (pll_ctl_val & 0x10) {
 827                         /* PLL enabled, apply multiplier and divisor */
 828                         if (pll_ctl_val & 0xf80)
 829                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 830                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 831                 } else {
 832                         /* PLL disabled, apply bypass divisor */
 833                         switch (pll_ctl_val & 0xc) {
 834                         case 0:
 835                                 break;
 836                         case 0x4:
 837                                 ck_dpll1.rate /= 2;
 838                                 break;
 839                         default:
 840                                 ck_dpll1.rate /= 4;
 841                                 break;
 842                         }
 843                 }
 844         }
 845 #else
 846         /* Find the highest supported frequency and enable it */
 847         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 848                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 849                 /* Guess sane values (60MHz) */
 850                 omap_writew(0x2290, DPLL_CTL);
 851                 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 852                 ck_dpll1.rate = 60000000;
 853         }
 854 #endif
 855         propagate_rate(&ck_dpll1);
 856         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 857         propagate_rate(&ck_ref);
 858         printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
 859                 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 860                ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 861                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 862                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 863
 864 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 865         /* Select slicer output as OMAP input clock */
 866         omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 867 #endif
 868
 869         /* Amstrad Delta wants BCLK high when inactive */
 870         if (machine_is_ams_delta())
 871                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 872                                 (1 << SDW_MCLK_INV_BIT),
 873                                 ULPD_CLOCK_CTRL);
 874
 875         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 876         /* (on 730, bit 13 must not be cleared) */
 877         if (cpu_is_omap7xx())
 878                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 879         else
 880                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 881
 882         /* Put DSP/MPUI into reset until needed */
 883         omap_writew(0, ARM_RSTCT1);
 884         omap_writew(1, ARM_RSTCT2);
 885         omap_writew(0x400, ARM_IDLECT1);
 886
 887         /*
 888          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 889          * of the ARM_IDLECT2 register must be set to zero. The power-on
 890          * default value of this bit is one.
 891          */
 892         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 893
 894         /*
 895          * Only enable those clocks we will need, let the drivers
 896          * enable other clocks as necessary
 897          */
 898         clk_enable(&armper_ck.clk);
 899         clk_enable(&armxor_ck.clk);
 900         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 901
 902         if (cpu_is_omap15xx())
 903                 clk_enable(&arm_gpio_ck);
 904
 905         return 0;
 906 }