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[TG3]: Add indirect register method for 5703 behind ICH
[net-next-2.6.git] / drivers / net / tg3.c
CommitLineData
1da177e4
LT		 1/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
49cabf49
MC		 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
1da177e4
LT		 16 */
17
18#include <linux/config.h>
19
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/ioport.h>
29#include <linux/pci.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/skbuff.h>
33#include <linux/ethtool.h>
34#include <linux/mii.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/workqueue.h>
39
40#include <net/checksum.h>
41
42#include <asm/system.h>
43#include <asm/io.h>
44#include <asm/byteorder.h>
45#include <asm/uaccess.h>
46
47#ifdef CONFIG_SPARC64
48#include <asm/idprom.h>
49#include <asm/oplib.h>
50#include <asm/pbm.h>
51#endif
52
53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define TG3_VLAN_TAG_USED 1
55#else
56#define TG3_VLAN_TAG_USED 0
57#endif
58
59#ifdef NETIF_F_TSO
60#define TG3_TSO_SUPPORT 1
61#else
62#define TG3_TSO_SUPPORT 0
63#endif
64
65#include "tg3.h"
66
67#define DRV_MODULE_NAME "tg3"
68#define PFX DRV_MODULE_NAME ": "
d4ef1608
MC		 69#define DRV_MODULE_VERSION "3.37"
70#define DRV_MODULE_RELDATE "August 25, 2005"
1da177e4
LT		 71
72#define TG3_DEF_MAC_MODE 0
73#define TG3_DEF_RX_MODE 0
74#define TG3_DEF_TX_MODE 0
75#define TG3_DEF_MSG_ENABLE \
76 (NETIF_MSG_DRV | \
77 NETIF_MSG_PROBE | \
78 NETIF_MSG_LINK | \
79 NETIF_MSG_TIMER | \
80 NETIF_MSG_IFDOWN | \
81 NETIF_MSG_IFUP | \
82 NETIF_MSG_RX_ERR | \
83 NETIF_MSG_TX_ERR)
84
85/* length of time before we decide the hardware is borked,
86 * and dev->tx_timeout() should be called to fix the problem
87 */
88#define TG3_TX_TIMEOUT (5 * HZ)
89
90/* hardware minimum and maximum for a single frame's data payload */
91#define TG3_MIN_MTU 60
92#define TG3_MAX_MTU(tp) \
0f893dc6 93 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
1da177e4
LT		 94
95/* These numbers seem to be hard coded in the NIC firmware somehow.
96 * You can't change the ring sizes, but you can change where you place
97 * them in the NIC onboard memory.
98 */
99#define TG3_RX_RING_SIZE 512
100#define TG3_DEF_RX_RING_PENDING 200
101#define TG3_RX_JUMBO_RING_SIZE 256
102#define TG3_DEF_RX_JUMBO_RING_PENDING 100
103
104/* Do not place this n-ring entries value into the tp struct itself,
105 * we really want to expose these constants to GCC so that modulo et
106 * al. operations are done with shifts and masks instead of with
107 * hw multiply/modulo instructions. Another solution would be to
108 * replace things like '% foo' with '& (foo - 1)'.
109 */
110#define TG3_RX_RCB_RING_SIZE(tp) \
111 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
112
113#define TG3_TX_RING_SIZE 512
114#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
115
116#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_RING_SIZE)
118#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_JUMBO_RING_SIZE)
120#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RCB_RING_SIZE(tp))
122#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
123 TG3_TX_RING_SIZE)
124#define TX_RING_GAP(TP) \
125 (TG3_TX_RING_SIZE - (TP)->tx_pending)
126#define TX_BUFFS_AVAIL(TP) \
127 (((TP)->tx_cons <= (TP)->tx_prod) ? \
128 (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod : \
129 (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
130#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
131
132#define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
133#define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
134
135/* minimum number of free TX descriptors required to wake up TX process */
136#define TG3_TX_WAKEUP_THRESH (TG3_TX_RING_SIZE / 4)
137
138/* number of ETHTOOL_GSTATS u64's */
139#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
140
4cafd3f5
MC		 141#define TG3_NUM_TEST 6
142
1da177e4
LT		 143static char version[] __devinitdata =
144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
145
146MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
147MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_MODULE_VERSION);
150
151static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
152module_param(tg3_debug, int, 0);
153MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
154
155static struct pci_device_id tg3_pci_tbl[] = {
156 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
158 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
160 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
162 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
164 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
166 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
168 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
170 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
172 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
174 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
176 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
178 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
180 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
182 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
184 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
186 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
188 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
190 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
192 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
194 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
196 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
198 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
200 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
202 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
206 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
208 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
210 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
6e9017a7 214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
af2bcd97 215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
d8659255
XVP		 216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
4cf78e4f
MC		 224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
230 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
232 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
234 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
236 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
238 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
240 { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
242 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
244 { 0, }
245};
246
247MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
248
249static struct {
250 const char string[ETH_GSTRING_LEN];
251} ethtool_stats_keys[TG3_NUM_STATS] = {
252 { "rx_octets" },
253 { "rx_fragments" },
254 { "rx_ucast_packets" },
255 { "rx_mcast_packets" },
256 { "rx_bcast_packets" },
257 { "rx_fcs_errors" },
258 { "rx_align_errors" },
259 { "rx_xon_pause_rcvd" },
260 { "rx_xoff_pause_rcvd" },
261 { "rx_mac_ctrl_rcvd" },
262 { "rx_xoff_entered" },
263 { "rx_frame_too_long_errors" },
264 { "rx_jabbers" },
265 { "rx_undersize_packets" },
266 { "rx_in_length_errors" },
267 { "rx_out_length_errors" },
268 { "rx_64_or_less_octet_packets" },
269 { "rx_65_to_127_octet_packets" },
270 { "rx_128_to_255_octet_packets" },
271 { "rx_256_to_511_octet_packets" },
272 { "rx_512_to_1023_octet_packets" },
273 { "rx_1024_to_1522_octet_packets" },
274 { "rx_1523_to_2047_octet_packets" },
275 { "rx_2048_to_4095_octet_packets" },
276 { "rx_4096_to_8191_octet_packets" },
277 { "rx_8192_to_9022_octet_packets" },
278
279 { "tx_octets" },
280 { "tx_collisions" },
281
282 { "tx_xon_sent" },
283 { "tx_xoff_sent" },
284 { "tx_flow_control" },
285 { "tx_mac_errors" },
286 { "tx_single_collisions" },
287 { "tx_mult_collisions" },
288 { "tx_deferred" },
289 { "tx_excessive_collisions" },
290 { "tx_late_collisions" },
291 { "tx_collide_2times" },
292 { "tx_collide_3times" },
293 { "tx_collide_4times" },
294 { "tx_collide_5times" },
295 { "tx_collide_6times" },
296 { "tx_collide_7times" },
297 { "tx_collide_8times" },
298 { "tx_collide_9times" },
299 { "tx_collide_10times" },
300 { "tx_collide_11times" },
301 { "tx_collide_12times" },
302 { "tx_collide_13times" },
303 { "tx_collide_14times" },
304 { "tx_collide_15times" },
305 { "tx_ucast_packets" },
306 { "tx_mcast_packets" },
307 { "tx_bcast_packets" },
308 { "tx_carrier_sense_errors" },
309 { "tx_discards" },
310 { "tx_errors" },
311
312 { "dma_writeq_full" },
313 { "dma_write_prioq_full" },
314 { "rxbds_empty" },
315 { "rx_discards" },
316 { "rx_errors" },
317 { "rx_threshold_hit" },
318
319 { "dma_readq_full" },
320 { "dma_read_prioq_full" },
321 { "tx_comp_queue_full" },
322
323 { "ring_set_send_prod_index" },
324 { "ring_status_update" },
325 { "nic_irqs" },
326 { "nic_avoided_irqs" },
327 { "nic_tx_threshold_hit" }
328};
329
4cafd3f5
MC		 330static struct {
331 const char string[ETH_GSTRING_LEN];
332} ethtool_test_keys[TG3_NUM_TEST] = {
333 { "nvram test (online) " },
334 { "link test (online) " },
335 { "register test (offline)" },
336 { "memory test (offline)" },
337 { "loopback test (offline)" },
338 { "interrupt test (offline)" },
339};
340
1da177e4
LT		 341static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
342{
6892914f
MC		 343 unsigned long flags;
344
345 spin_lock_irqsave(&tp->indirect_lock, flags);
1ee582d8
MC		 346 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
347 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
6892914f 348 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1ee582d8
MC		 349}
350
351static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
352{
353 writel(val, tp->regs + off);
354 readl(tp->regs + off);
1da177e4
LT		 355}
356
6892914f 357static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
1da177e4 358{
6892914f
MC		 359 unsigned long flags;
360 u32 val;
361
362 spin_lock_irqsave(&tp->indirect_lock, flags);
363 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
364 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
365 spin_unlock_irqrestore(&tp->indirect_lock, flags);
366 return val;
367}
368
369static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
370{
371 unsigned long flags;
372
373 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
374 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
375 TG3_64BIT_REG_LOW, val);
376 return;
377 }
378 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
379 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
380 TG3_64BIT_REG_LOW, val);
381 return;
1da177e4 382 }
6892914f
MC		 383
384 spin_lock_irqsave(&tp->indirect_lock, flags);
385 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
386 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
387 spin_unlock_irqrestore(&tp->indirect_lock, flags);
388
389 /* In indirect mode when disabling interrupts, we also need
390 * to clear the interrupt bit in the GRC local ctrl register.
391 */
392 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
393 (val == 0x1)) {
394 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
395 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
396 }
397}
398
399static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
400{
401 unsigned long flags;
402 u32 val;
403
404 spin_lock_irqsave(&tp->indirect_lock, flags);
405 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
406 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
407 spin_unlock_irqrestore(&tp->indirect_lock, flags);
408 return val;
409}
410
411static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
412{
413 tp->write32(tp, off, val);
414 if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
415 !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
416 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
417 tp->read32(tp, off); /* flush */
1da177e4
LT		 418}
419
09ee929c
MC		 420static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
421{
422 tp->write32_mbox(tp, off, val);
6892914f
MC		 423 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
424 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
425 tp->read32_mbox(tp, off);
09ee929c
MC		 426}
427
20094930 428static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
1da177e4
LT		 429{
430 void __iomem *mbox = tp->regs + off;
431 writel(val, mbox);
432 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
433 writel(val, mbox);
434 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
435 readl(mbox);
436}
437
20094930
MC		 438static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
439{
440 writel(val, tp->regs + off);
441}
1da177e4 442
20094930
MC		 443static u32 tg3_read32(struct tg3 *tp, u32 off)
444{
445 return (readl(tp->regs + off));
446}
447
448#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
09ee929c 449#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
20094930
MC		 450#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
451#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
09ee929c 452#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
20094930
MC		 453
454#define tw32(reg,val) tp->write32(tp, reg, val)
1da177e4 455#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val))
20094930 456#define tr32(reg) tp->read32(tp, reg)
1da177e4
LT		 457
458static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
459{
6892914f
MC		 460 unsigned long flags;
461
462 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
464 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
465
466 /* Always leave this as zero. */
467 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 468 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 469}
470
471static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
472{
6892914f
MC		 473 unsigned long flags;
474
475 spin_lock_irqsave(&tp->indirect_lock, flags);
1da177e4
LT		 476 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
477 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
478
479 /* Always leave this as zero. */
480 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
6892914f 481 spin_unlock_irqrestore(&tp->indirect_lock, flags);
1da177e4
LT		 482}
483
484static void tg3_disable_ints(struct tg3 *tp)
485{
486 tw32(TG3PCI_MISC_HOST_CTRL,
487 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c 488 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
1da177e4
LT		 489}
490
491static inline void tg3_cond_int(struct tg3 *tp)
492{
493 if (tp->hw_status->status & SD_STATUS_UPDATED)
494 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
495}
496
497static void tg3_enable_ints(struct tg3 *tp)
498{
bbe832c0
MC		 499 tp->irq_sync = 0;
500 wmb();
501
1da177e4
LT		 502 tw32(TG3PCI_MISC_HOST_CTRL,
503 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
09ee929c
MC		 504 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
505 (tp->last_tag << 24));
1da177e4
LT		 506 tg3_cond_int(tp);
507}
508
04237ddd
MC		 509static inline unsigned int tg3_has_work(struct tg3 *tp)
510{
511 struct tg3_hw_status *sblk = tp->hw_status;
512 unsigned int work_exists = 0;
513
514 /* check for phy events */
515 if (!(tp->tg3_flags &
516 (TG3_FLAG_USE_LINKCHG_REG |
517 TG3_FLAG_POLL_SERDES))) {
518 if (sblk->status & SD_STATUS_LINK_CHG)
519 work_exists = 1;
520 }
521 /* check for RX/TX work to do */
522 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
523 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
524 work_exists = 1;
525
526 return work_exists;
527}
528
1da177e4 529/* tg3_restart_ints
04237ddd
MC		 530 * similar to tg3_enable_ints, but it accurately determines whether there
531 * is new work pending and can return without flushing the PIO write
532 * which reenables interrupts
1da177e4
LT		 533 */
534static void tg3_restart_ints(struct tg3 *tp)
535{
536 tw32(TG3PCI_MISC_HOST_CTRL,
537 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
fac9b83e
DM		 538 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
539 tp->last_tag << 24);
1da177e4
LT		 540 mmiowb();
541
fac9b83e
DM		 542 /* When doing tagged status, this work check is unnecessary.
543 * The last_tag we write above tells the chip which piece of
544 * work we've completed.
545 */
546 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
547 tg3_has_work(tp))
04237ddd
MC		 548 tw32(HOSTCC_MODE, tp->coalesce_mode |
549 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
1da177e4
LT		 550}
551
552static inline void tg3_netif_stop(struct tg3 *tp)
553{
bbe832c0 554 tp->dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 555 netif_poll_disable(tp->dev);
556 netif_tx_disable(tp->dev);
557}
558
559static inline void tg3_netif_start(struct tg3 *tp)
560{
561 netif_wake_queue(tp->dev);
562 /* NOTE: unconditional netif_wake_queue is only appropriate
563 * so long as all callers are assured to have free tx slots
564 * (such as after tg3_init_hw)
565 */
566 netif_poll_enable(tp->dev);
f47c11ee
DM		 567 tp->hw_status->status |= SD_STATUS_UPDATED;
568 tg3_enable_ints(tp);
1da177e4
LT		 569}
570
571static void tg3_switch_clocks(struct tg3 *tp)
572{
573 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
574 u32 orig_clock_ctrl;
575
4cf78e4f
MC		 576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
577 return;
578
1da177e4
LT		 579 orig_clock_ctrl = clock_ctrl;
580 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
581 CLOCK_CTRL_CLKRUN_OENABLE |
582 0x1f);
583 tp->pci_clock_ctrl = clock_ctrl;
584
585 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
586 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
587 tw32_f(TG3PCI_CLOCK_CTRL,
588 clock_ctrl | CLOCK_CTRL_625_CORE);
589 udelay(40);
590 }
591 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
592 tw32_f(TG3PCI_CLOCK_CTRL,
593 clock_ctrl |
594 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
595 udelay(40);
596 tw32_f(TG3PCI_CLOCK_CTRL,
597 clock_ctrl | (CLOCK_CTRL_ALTCLK));
598 udelay(40);
599 }
600 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
601 udelay(40);
602}
603
604#define PHY_BUSY_LOOPS 5000
605
606static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
607{
608 u32 frame_val;
609 unsigned int loops;
610 int ret;
611
612 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
613 tw32_f(MAC_MI_MODE,
614 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
615 udelay(80);
616 }
617
618 *val = 0x0;
619
620 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
621 MI_COM_PHY_ADDR_MASK);
622 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
623 MI_COM_REG_ADDR_MASK);
624 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
625
626 tw32_f(MAC_MI_COM, frame_val);
627
628 loops = PHY_BUSY_LOOPS;
629 while (loops != 0) {
630 udelay(10);
631 frame_val = tr32(MAC_MI_COM);
632
633 if ((frame_val & MI_COM_BUSY) == 0) {
634 udelay(5);
635 frame_val = tr32(MAC_MI_COM);
636 break;
637 }
638 loops -= 1;
639 }
640
641 ret = -EBUSY;
642 if (loops != 0) {
643 *val = frame_val & MI_COM_DATA_MASK;
644 ret = 0;
645 }
646
647 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
648 tw32_f(MAC_MI_MODE, tp->mi_mode);
649 udelay(80);
650 }
651
652 return ret;
653}
654
655static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
656{
657 u32 frame_val;
658 unsigned int loops;
659 int ret;
660
661 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
662 tw32_f(MAC_MI_MODE,
663 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
664 udelay(80);
665 }
666
667 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
668 MI_COM_PHY_ADDR_MASK);
669 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
670 MI_COM_REG_ADDR_MASK);
671 frame_val |= (val & MI_COM_DATA_MASK);
672 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
673
674 tw32_f(MAC_MI_COM, frame_val);
675
676 loops = PHY_BUSY_LOOPS;
677 while (loops != 0) {
678 udelay(10);
679 frame_val = tr32(MAC_MI_COM);
680 if ((frame_val & MI_COM_BUSY) == 0) {
681 udelay(5);
682 frame_val = tr32(MAC_MI_COM);
683 break;
684 }
685 loops -= 1;
686 }
687
688 ret = -EBUSY;
689 if (loops != 0)
690 ret = 0;
691
692 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
693 tw32_f(MAC_MI_MODE, tp->mi_mode);
694 udelay(80);
695 }
696
697 return ret;
698}
699
700static void tg3_phy_set_wirespeed(struct tg3 *tp)
701{
702 u32 val;
703
704 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
705 return;
706
707 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
708 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
709 tg3_writephy(tp, MII_TG3_AUX_CTRL,
710 (val | (1 << 15) | (1 << 4)));
711}
712
713static int tg3_bmcr_reset(struct tg3 *tp)
714{
715 u32 phy_control;
716 int limit, err;
717
718 /* OK, reset it, and poll the BMCR_RESET bit until it
719 * clears or we time out.
720 */
721 phy_control = BMCR_RESET;
722 err = tg3_writephy(tp, MII_BMCR, phy_control);
723 if (err != 0)
724 return -EBUSY;
725
726 limit = 5000;
727 while (limit--) {
728 err = tg3_readphy(tp, MII_BMCR, &phy_control);
729 if (err != 0)
730 return -EBUSY;
731
732 if ((phy_control & BMCR_RESET) == 0) {
733 udelay(40);
734 break;
735 }
736 udelay(10);
737 }
738 if (limit <= 0)
739 return -EBUSY;
740
741 return 0;
742}
743
744static int tg3_wait_macro_done(struct tg3 *tp)
745{
746 int limit = 100;
747
748 while (limit--) {
749 u32 tmp32;
750
751 if (!tg3_readphy(tp, 0x16, &tmp32)) {
752 if ((tmp32 & 0x1000) == 0)
753 break;
754 }
755 }
756 if (limit <= 0)
757 return -EBUSY;
758
759 return 0;
760}
761
762static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
763{
764 static const u32 test_pat[4][6] = {
765 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
766 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
767 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
768 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
769 };
770 int chan;
771
772 for (chan = 0; chan < 4; chan++) {
773 int i;
774
775 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
776 (chan * 0x2000) | 0x0200);
777 tg3_writephy(tp, 0x16, 0x0002);
778
779 for (i = 0; i < 6; i++)
780 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
781 test_pat[chan][i]);
782
783 tg3_writephy(tp, 0x16, 0x0202);
784 if (tg3_wait_macro_done(tp)) {
785 *resetp = 1;
786 return -EBUSY;
787 }
788
789 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
790 (chan * 0x2000) | 0x0200);
791 tg3_writephy(tp, 0x16, 0x0082);
792 if (tg3_wait_macro_done(tp)) {
793 *resetp = 1;
794 return -EBUSY;
795 }
796
797 tg3_writephy(tp, 0x16, 0x0802);
798 if (tg3_wait_macro_done(tp)) {
799 *resetp = 1;
800 return -EBUSY;
801 }
802
803 for (i = 0; i < 6; i += 2) {
804 u32 low, high;
805
806 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
807 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
808 tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812 low &= 0x7fff;
813 high &= 0x000f;
814 if (low != test_pat[chan][i] ||
815 high != test_pat[chan][i+1]) {
816 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
817 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
818 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
819
820 return -EBUSY;
821 }
822 }
823 }
824
825 return 0;
826}
827
828static int tg3_phy_reset_chanpat(struct tg3 *tp)
829{
830 int chan;
831
832 for (chan = 0; chan < 4; chan++) {
833 int i;
834
835 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
836 (chan * 0x2000) | 0x0200);
837 tg3_writephy(tp, 0x16, 0x0002);
838 for (i = 0; i < 6; i++)
839 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
840 tg3_writephy(tp, 0x16, 0x0202);
841 if (tg3_wait_macro_done(tp))
842 return -EBUSY;
843 }
844
845 return 0;
846}
847
848static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
849{
850 u32 reg32, phy9_orig;
851 int retries, do_phy_reset, err;
852
853 retries = 10;
854 do_phy_reset = 1;
855 do {
856 if (do_phy_reset) {
857 err = tg3_bmcr_reset(tp);
858 if (err)
859 return err;
860 do_phy_reset = 0;
861 }
862
863 /* Disable transmitter and interrupt. */
864 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
865 continue;
866
867 reg32 |= 0x3000;
868 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
869
870 /* Set full-duplex, 1000 mbps. */
871 tg3_writephy(tp, MII_BMCR,
872 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
873
874 /* Set to master mode. */
875 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
876 continue;
877
878 tg3_writephy(tp, MII_TG3_CTRL,
879 (MII_TG3_CTRL_AS_MASTER |
880 MII_TG3_CTRL_ENABLE_AS_MASTER));
881
882 /* Enable SM_DSP_CLOCK and 6dB. */
883 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
884
885 /* Block the PHY control access. */
886 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
887 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
888
889 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
890 if (!err)
891 break;
892 } while (--retries);
893
894 err = tg3_phy_reset_chanpat(tp);
895 if (err)
896 return err;
897
898 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
899 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
900
901 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
902 tg3_writephy(tp, 0x16, 0x0000);
903
904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
906 /* Set Extended packet length bit for jumbo frames */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
908 }
909 else {
910 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
911 }
912
913 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
914
915 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
916 reg32 &= ~0x3000;
917 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
918 } else if (!err)
919 err = -EBUSY;
920
921 return err;
922}
923
924/* This will reset the tigon3 PHY if there is no valid
925 * link unless the FORCE argument is non-zero.
926 */
927static int tg3_phy_reset(struct tg3 *tp)
928{
929 u32 phy_status;
930 int err;
931
932 err = tg3_readphy(tp, MII_BMSR, &phy_status);
933 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
934 if (err != 0)
935 return -EBUSY;
936
937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
940 err = tg3_phy_reset_5703_4_5(tp);
941 if (err)
942 return err;
943 goto out;
944 }
945
946 err = tg3_bmcr_reset(tp);
947 if (err)
948 return err;
949
950out:
951 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
952 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
953 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
954 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
955 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
958 }
959 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
960 tg3_writephy(tp, 0x1c, 0x8d68);
961 tg3_writephy(tp, 0x1c, 0x8d68);
962 }
963 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
964 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
965 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
966 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
967 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
968 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
969 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
970 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
972 }
973 /* Set Extended packet length bit (bit 14) on all chips that */
974 /* support jumbo frames */
975 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
976 /* Cannot do read-modify-write on 5401 */
977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
0f893dc6 978 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 979 u32 phy_reg;
980
981 /* Set bit 14 with read-modify-write to preserve other bits */
982 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
983 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
984 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
985 }
986
987 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
988 * jumbo frames transmission.
989 */
0f893dc6 990 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1da177e4
LT		 991 u32 phy_reg;
992
993 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
994 tg3_writephy(tp, MII_TG3_EXT_CTRL,
995 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
996 }
997
998 tg3_phy_set_wirespeed(tp);
999 return 0;
1000}
1001
1002static void tg3_frob_aux_power(struct tg3 *tp)
1003{
1004 struct tg3 *tp_peer = tp;
1005
1006 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1007 return;
1008
1009 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1010 tp_peer = pci_get_drvdata(tp->pdev_peer);
1011 if (!tp_peer)
1012 BUG();
1013 }
1014
1015
1016 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1017 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
1018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1020 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1021 (GRC_LCLCTRL_GPIO_OE0 |
1022 GRC_LCLCTRL_GPIO_OE1 |
1023 GRC_LCLCTRL_GPIO_OE2 |
1024 GRC_LCLCTRL_GPIO_OUTPUT0 |
1025 GRC_LCLCTRL_GPIO_OUTPUT1));
1026 udelay(100);
1027 } else {
1028 u32 no_gpio2;
1029 u32 grc_local_ctrl;
1030
1031 if (tp_peer != tp &&
1032 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1033 return;
1034
1035 /* On 5753 and variants, GPIO2 cannot be used. */
1036 no_gpio2 = tp->nic_sram_data_cfg &
1037 NIC_SRAM_DATA_CFG_NO_GPIO2;
1038
1039 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1040 GRC_LCLCTRL_GPIO_OE1 |
1041 GRC_LCLCTRL_GPIO_OE2 |
1042 GRC_LCLCTRL_GPIO_OUTPUT1 |
1043 GRC_LCLCTRL_GPIO_OUTPUT2;
1044 if (no_gpio2) {
1045 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1046 GRC_LCLCTRL_GPIO_OUTPUT2);
1047 }
1048 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1049 grc_local_ctrl);
1050 udelay(100);
1051
1052 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1053
1054 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1055 grc_local_ctrl);
1056 udelay(100);
1057
1058 if (!no_gpio2) {
1059 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1060 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1061 grc_local_ctrl);
1062 udelay(100);
1063 }
1064 }
1065 } else {
1066 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1067 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1068 if (tp_peer != tp &&
1069 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1070 return;
1071
1072 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1073 (GRC_LCLCTRL_GPIO_OE1 |
1074 GRC_LCLCTRL_GPIO_OUTPUT1));
1075 udelay(100);
1076
1077 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1078 (GRC_LCLCTRL_GPIO_OE1));
1079 udelay(100);
1080
1081 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1082 (GRC_LCLCTRL_GPIO_OE1 |
1083 GRC_LCLCTRL_GPIO_OUTPUT1));
1084 udelay(100);
1085 }
1086 }
1087}
1088
1089static int tg3_setup_phy(struct tg3 *, int);
1090
1091#define RESET_KIND_SHUTDOWN 0
1092#define RESET_KIND_INIT 1
1093#define RESET_KIND_SUSPEND 2
1094
1095static void tg3_write_sig_post_reset(struct tg3 *, int);
1096static int tg3_halt_cpu(struct tg3 *, u32);
1097
1098static int tg3_set_power_state(struct tg3 *tp, int state)
1099{
1100 u32 misc_host_ctrl;
1101 u16 power_control, power_caps;
1102 int pm = tp->pm_cap;
1103
1104 /* Make sure register accesses (indirect or otherwise)
1105 * will function correctly.
1106 */
1107 pci_write_config_dword(tp->pdev,
1108 TG3PCI_MISC_HOST_CTRL,
1109 tp->misc_host_ctrl);
1110
1111 pci_read_config_word(tp->pdev,
1112 pm + PCI_PM_CTRL,
1113 &power_control);
1114 power_control |= PCI_PM_CTRL_PME_STATUS;
1115 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1116 switch (state) {
1117 case 0:
1118 power_control |= 0;
1119 pci_write_config_word(tp->pdev,
1120 pm + PCI_PM_CTRL,
1121 power_control);
8c6bda1a
MC		 1122 udelay(100); /* Delay after power state change */
1123
1124 /* Switch out of Vaux if it is not a LOM */
1125 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1126 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1127 udelay(100);
1128 }
1da177e4
LT		 1129
1130 return 0;
1131
1132 case 1:
1133 power_control |= 1;
1134 break;
1135
1136 case 2:
1137 power_control |= 2;
1138 break;
1139
1140 case 3:
1141 power_control |= 3;
1142 break;
1143
1144 default:
1145 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1146 "requested.\n",
1147 tp->dev->name, state);
1148 return -EINVAL;
1149 };
1150
1151 power_control |= PCI_PM_CTRL_PME_ENABLE;
1152
1153 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1154 tw32(TG3PCI_MISC_HOST_CTRL,
1155 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1156
1157 if (tp->link_config.phy_is_low_power == 0) {
1158 tp->link_config.phy_is_low_power = 1;
1159 tp->link_config.orig_speed = tp->link_config.speed;
1160 tp->link_config.orig_duplex = tp->link_config.duplex;
1161 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1162 }
1163
747e8f8b 1164 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1da177e4
LT		 1165 tp->link_config.speed = SPEED_10;
1166 tp->link_config.duplex = DUPLEX_HALF;
1167 tp->link_config.autoneg = AUTONEG_ENABLE;
1168 tg3_setup_phy(tp, 0);
1169 }
1170
1171 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1172
1173 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1174 u32 mac_mode;
1175
1176 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1177 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1178 udelay(40);
1179
1180 mac_mode = MAC_MODE_PORT_MODE_MII;
1181
1182 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1183 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1184 mac_mode |= MAC_MODE_LINK_POLARITY;
1185 } else {
1186 mac_mode = MAC_MODE_PORT_MODE_TBI;
1187 }
1188
cbf46853 1189 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1da177e4
LT		 1190 tw32(MAC_LED_CTRL, tp->led_ctrl);
1191
1192 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1193 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1194 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1195
1196 tw32_f(MAC_MODE, mac_mode);
1197 udelay(100);
1198
1199 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1200 udelay(10);
1201 }
1202
1203 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1204 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1206 u32 base_val;
1207
1208 base_val = tp->pci_clock_ctrl;
1209 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1210 CLOCK_CTRL_TXCLK_DISABLE);
1211
1212 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1213 CLOCK_CTRL_ALTCLK |
1214 CLOCK_CTRL_PWRDOWN_PLL133);
1215 udelay(40);
4cf78e4f
MC		 1216 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1217 /* do nothing */
85e94ced 1218 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1da177e4
LT		 1219 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1220 u32 newbits1, newbits2;
1221
1222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1224 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1225 CLOCK_CTRL_TXCLK_DISABLE |
1226 CLOCK_CTRL_ALTCLK);
1227 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1228 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1229 newbits1 = CLOCK_CTRL_625_CORE;
1230 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1231 } else {
1232 newbits1 = CLOCK_CTRL_ALTCLK;
1233 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1234 }
1235
1236 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1237 udelay(40);
1238
1239 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1240 udelay(40);
1241
1242 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1243 u32 newbits3;
1244
1245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1247 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1248 CLOCK_CTRL_TXCLK_DISABLE |
1249 CLOCK_CTRL_44MHZ_CORE);
1250 } else {
1251 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1252 }
1253
1254 tw32_f(TG3PCI_CLOCK_CTRL,
1255 tp->pci_clock_ctrl | newbits3);
1256 udelay(40);
1257 }
1258 }
1259
1260 tg3_frob_aux_power(tp);
1261
1262 /* Workaround for unstable PLL clock */
1263 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1264 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1265 u32 val = tr32(0x7d00);
1266
1267 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1268 tw32(0x7d00, val);
1269 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1270 tg3_halt_cpu(tp, RX_CPU_BASE);
1271 }
1272
1273 /* Finally, set the new power state. */
1274 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
8c6bda1a 1275 udelay(100); /* Delay after power state change */
1da177e4
LT		 1276
1277 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1278
1279 return 0;
1280}
1281
1282static void tg3_link_report(struct tg3 *tp)
1283{
1284 if (!netif_carrier_ok(tp->dev)) {
1285 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1286 } else {
1287 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1288 tp->dev->name,
1289 (tp->link_config.active_speed == SPEED_1000 ?
1290 1000 :
1291 (tp->link_config.active_speed == SPEED_100 ?
1292 100 : 10)),
1293 (tp->link_config.active_duplex == DUPLEX_FULL ?
1294 "full" : "half"));
1295
1296 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1297 "%s for RX.\n",
1298 tp->dev->name,
1299 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1300 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1301 }
1302}
1303
1304static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1305{
1306 u32 new_tg3_flags = 0;
1307 u32 old_rx_mode = tp->rx_mode;
1308 u32 old_tx_mode = tp->tx_mode;
1309
1310 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
747e8f8b
MC		 1311
1312 /* Convert 1000BaseX flow control bits to 1000BaseT
1313 * bits before resolving flow control.
1314 */
1315 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1316 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1317 ADVERTISE_PAUSE_ASYM);
1318 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1319
1320 if (local_adv & ADVERTISE_1000XPAUSE)
1321 local_adv |= ADVERTISE_PAUSE_CAP;
1322 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1323 local_adv |= ADVERTISE_PAUSE_ASYM;
1324 if (remote_adv & LPA_1000XPAUSE)
1325 remote_adv |= LPA_PAUSE_CAP;
1326 if (remote_adv & LPA_1000XPAUSE_ASYM)
1327 remote_adv |= LPA_PAUSE_ASYM;
1328 }
1329
1da177e4
LT		 1330 if (local_adv & ADVERTISE_PAUSE_CAP) {
1331 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1332 if (remote_adv & LPA_PAUSE_CAP)
1333 new_tg3_flags |=
1334 (TG3_FLAG_RX_PAUSE |
1335 TG3_FLAG_TX_PAUSE);
1336 else if (remote_adv & LPA_PAUSE_ASYM)
1337 new_tg3_flags |=
1338 (TG3_FLAG_RX_PAUSE);
1339 } else {
1340 if (remote_adv & LPA_PAUSE_CAP)
1341 new_tg3_flags |=
1342 (TG3_FLAG_RX_PAUSE |
1343 TG3_FLAG_TX_PAUSE);
1344 }
1345 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1346 if ((remote_adv & LPA_PAUSE_CAP) &&
1347 (remote_adv & LPA_PAUSE_ASYM))
1348 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1349 }
1350
1351 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1352 tp->tg3_flags |= new_tg3_flags;
1353 } else {
1354 new_tg3_flags = tp->tg3_flags;
1355 }
1356
1357 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1358 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1359 else
1360 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1361
1362 if (old_rx_mode != tp->rx_mode) {
1363 tw32_f(MAC_RX_MODE, tp->rx_mode);
1364 }
1365
1366 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1367 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1368 else
1369 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1370
1371 if (old_tx_mode != tp->tx_mode) {
1372 tw32_f(MAC_TX_MODE, tp->tx_mode);
1373 }
1374}
1375
1376static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1377{
1378 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1379 case MII_TG3_AUX_STAT_10HALF:
1380 *speed = SPEED_10;
1381 *duplex = DUPLEX_HALF;
1382 break;
1383
1384 case MII_TG3_AUX_STAT_10FULL:
1385 *speed = SPEED_10;
1386 *duplex = DUPLEX_FULL;
1387 break;
1388
1389 case MII_TG3_AUX_STAT_100HALF:
1390 *speed = SPEED_100;
1391 *duplex = DUPLEX_HALF;
1392 break;
1393
1394 case MII_TG3_AUX_STAT_100FULL:
1395 *speed = SPEED_100;
1396 *duplex = DUPLEX_FULL;
1397 break;
1398
1399 case MII_TG3_AUX_STAT_1000HALF:
1400 *speed = SPEED_1000;
1401 *duplex = DUPLEX_HALF;
1402 break;
1403
1404 case MII_TG3_AUX_STAT_1000FULL:
1405 *speed = SPEED_1000;
1406 *duplex = DUPLEX_FULL;
1407 break;
1408
1409 default:
1410 *speed = SPEED_INVALID;
1411 *duplex = DUPLEX_INVALID;
1412 break;
1413 };
1414}
1415
1416static void tg3_phy_copper_begin(struct tg3 *tp)
1417{
1418 u32 new_adv;
1419 int i;
1420
1421 if (tp->link_config.phy_is_low_power) {
1422 /* Entering low power mode. Disable gigabit and
1423 * 100baseT advertisements.
1424 */
1425 tg3_writephy(tp, MII_TG3_CTRL, 0);
1426
1427 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1428 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1429 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1430 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1431
1432 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1433 } else if (tp->link_config.speed == SPEED_INVALID) {
1434 tp->link_config.advertising =
1435 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1436 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1437 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1438 ADVERTISED_Autoneg | ADVERTISED_MII);
1439
1440 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1441 tp->link_config.advertising &=
1442 ~(ADVERTISED_1000baseT_Half |
1443 ADVERTISED_1000baseT_Full);
1444
1445 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1446 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1447 new_adv |= ADVERTISE_10HALF;
1448 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1449 new_adv |= ADVERTISE_10FULL;
1450 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1451 new_adv |= ADVERTISE_100HALF;
1452 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1453 new_adv |= ADVERTISE_100FULL;
1454 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1455
1456 if (tp->link_config.advertising &
1457 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1458 new_adv = 0;
1459 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1460 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1461 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1462 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1463 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1464 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1465 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1466 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1467 MII_TG3_CTRL_ENABLE_AS_MASTER);
1468 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1469 } else {
1470 tg3_writephy(tp, MII_TG3_CTRL, 0);
1471 }
1472 } else {
1473 /* Asking for a specific link mode. */
1474 if (tp->link_config.speed == SPEED_1000) {
1475 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1476 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1477
1478 if (tp->link_config.duplex == DUPLEX_FULL)
1479 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1480 else
1481 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1482 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1483 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1484 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1485 MII_TG3_CTRL_ENABLE_AS_MASTER);
1486 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1487 } else {
1488 tg3_writephy(tp, MII_TG3_CTRL, 0);
1489
1490 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1491 if (tp->link_config.speed == SPEED_100) {
1492 if (tp->link_config.duplex == DUPLEX_FULL)
1493 new_adv |= ADVERTISE_100FULL;
1494 else
1495 new_adv |= ADVERTISE_100HALF;
1496 } else {
1497 if (tp->link_config.duplex == DUPLEX_FULL)
1498 new_adv |= ADVERTISE_10FULL;
1499 else
1500 new_adv |= ADVERTISE_10HALF;
1501 }
1502 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1503 }
1504 }
1505
1506 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1507 tp->link_config.speed != SPEED_INVALID) {
1508 u32 bmcr, orig_bmcr;
1509
1510 tp->link_config.active_speed = tp->link_config.speed;
1511 tp->link_config.active_duplex = tp->link_config.duplex;
1512
1513 bmcr = 0;
1514 switch (tp->link_config.speed) {
1515 default:
1516 case SPEED_10:
1517 break;
1518
1519 case SPEED_100:
1520 bmcr |= BMCR_SPEED100;
1521 break;
1522
1523 case SPEED_1000:
1524 bmcr |= TG3_BMCR_SPEED1000;
1525 break;
1526 };
1527
1528 if (tp->link_config.duplex == DUPLEX_FULL)
1529 bmcr |= BMCR_FULLDPLX;
1530
1531 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1532 (bmcr != orig_bmcr)) {
1533 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1534 for (i = 0; i < 1500; i++) {
1535 u32 tmp;
1536
1537 udelay(10);
1538 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1539 tg3_readphy(tp, MII_BMSR, &tmp))
1540 continue;
1541 if (!(tmp & BMSR_LSTATUS)) {
1542 udelay(40);
1543 break;
1544 }
1545 }
1546 tg3_writephy(tp, MII_BMCR, bmcr);
1547 udelay(40);
1548 }
1549 } else {
1550 tg3_writephy(tp, MII_BMCR,
1551 BMCR_ANENABLE | BMCR_ANRESTART);
1552 }
1553}
1554
1555static int tg3_init_5401phy_dsp(struct tg3 *tp)
1556{
1557 int err;
1558
1559 /* Turn off tap power management. */
1560 /* Set Extended packet length bit */
1561 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1562
1563 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1564 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1565
1566 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1567 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1568
1569 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1570 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1571
1572 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1573 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1574
1575 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1576 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1577
1578 udelay(40);
1579
1580 return err;
1581}
1582
1583static int tg3_copper_is_advertising_all(struct tg3 *tp)
1584{
1585 u32 adv_reg, all_mask;
1586
1587 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1588 return 0;
1589
1590 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1591 ADVERTISE_100HALF | ADVERTISE_100FULL);
1592 if ((adv_reg & all_mask) != all_mask)
1593 return 0;
1594 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1595 u32 tg3_ctrl;
1596
1597 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1598 return 0;
1599
1600 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1601 MII_TG3_CTRL_ADV_1000_FULL);
1602 if ((tg3_ctrl & all_mask) != all_mask)
1603 return 0;
1604 }
1605 return 1;
1606}
1607
1608static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1609{
1610 int current_link_up;
1611 u32 bmsr, dummy;
1612 u16 current_speed;
1613 u8 current_duplex;
1614 int i, err;
1615
1616 tw32(MAC_EVENT, 0);
1617
1618 tw32_f(MAC_STATUS,
1619 (MAC_STATUS_SYNC_CHANGED |
1620 MAC_STATUS_CFG_CHANGED |
1621 MAC_STATUS_MI_COMPLETION |
1622 MAC_STATUS_LNKSTATE_CHANGED));
1623 udelay(40);
1624
1625 tp->mi_mode = MAC_MI_MODE_BASE;
1626 tw32_f(MAC_MI_MODE, tp->mi_mode);
1627 udelay(80);
1628
1629 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1630
1631 /* Some third-party PHYs need to be reset on link going
1632 * down.
1633 */
1634 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1637 netif_carrier_ok(tp->dev)) {
1638 tg3_readphy(tp, MII_BMSR, &bmsr);
1639 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1640 !(bmsr & BMSR_LSTATUS))
1641 force_reset = 1;
1642 }
1643 if (force_reset)
1644 tg3_phy_reset(tp);
1645
1646 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1647 tg3_readphy(tp, MII_BMSR, &bmsr);
1648 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1649 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1650 bmsr = 0;
1651
1652 if (!(bmsr & BMSR_LSTATUS)) {
1653 err = tg3_init_5401phy_dsp(tp);
1654 if (err)
1655 return err;
1656
1657 tg3_readphy(tp, MII_BMSR, &bmsr);
1658 for (i = 0; i < 1000; i++) {
1659 udelay(10);
1660 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1661 (bmsr & BMSR_LSTATUS)) {
1662 udelay(40);
1663 break;
1664 }
1665 }
1666
1667 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1668 !(bmsr & BMSR_LSTATUS) &&
1669 tp->link_config.active_speed == SPEED_1000) {
1670 err = tg3_phy_reset(tp);
1671 if (!err)
1672 err = tg3_init_5401phy_dsp(tp);
1673 if (err)
1674 return err;
1675 }
1676 }
1677 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1678 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1679 /* 5701 {A0,B0} CRC bug workaround */
1680 tg3_writephy(tp, 0x15, 0x0a75);
1681 tg3_writephy(tp, 0x1c, 0x8c68);
1682 tg3_writephy(tp, 0x1c, 0x8d68);
1683 tg3_writephy(tp, 0x1c, 0x8c68);
1684 }
1685
1686 /* Clear pending interrupts... */
1687 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1688 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1689
1690 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1691 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1692 else
1693 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1694
1695 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1696 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1697 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1698 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1699 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1700 else
1701 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1702 }
1703
1704 current_link_up = 0;
1705 current_speed = SPEED_INVALID;
1706 current_duplex = DUPLEX_INVALID;
1707
1708 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1709 u32 val;
1710
1711 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1712 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1713 if (!(val & (1 << 10))) {
1714 val |= (1 << 10);
1715 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1716 goto relink;
1717 }
1718 }
1719
1720 bmsr = 0;
1721 for (i = 0; i < 100; i++) {
1722 tg3_readphy(tp, MII_BMSR, &bmsr);
1723 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1724 (bmsr & BMSR_LSTATUS))
1725 break;
1726 udelay(40);
1727 }
1728
1729 if (bmsr & BMSR_LSTATUS) {
1730 u32 aux_stat, bmcr;
1731
1732 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1733 for (i = 0; i < 2000; i++) {
1734 udelay(10);
1735 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1736 aux_stat)
1737 break;
1738 }
1739
1740 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1741 &current_speed,
1742 &current_duplex);
1743
1744 bmcr = 0;
1745 for (i = 0; i < 200; i++) {
1746 tg3_readphy(tp, MII_BMCR, &bmcr);
1747 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1748 continue;
1749 if (bmcr && bmcr != 0x7fff)
1750 break;
1751 udelay(10);
1752 }
1753
1754 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1755 if (bmcr & BMCR_ANENABLE) {
1756 current_link_up = 1;
1757
1758 /* Force autoneg restart if we are exiting
1759 * low power mode.
1760 */
1761 if (!tg3_copper_is_advertising_all(tp))
1762 current_link_up = 0;
1763 } else {
1764 current_link_up = 0;
1765 }
1766 } else {
1767 if (!(bmcr & BMCR_ANENABLE) &&
1768 tp->link_config.speed == current_speed &&
1769 tp->link_config.duplex == current_duplex) {
1770 current_link_up = 1;
1771 } else {
1772 current_link_up = 0;
1773 }
1774 }
1775
1776 tp->link_config.active_speed = current_speed;
1777 tp->link_config.active_duplex = current_duplex;
1778 }
1779
1780 if (current_link_up == 1 &&
1781 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1782 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1783 u32 local_adv, remote_adv;
1784
1785 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1786 local_adv = 0;
1787 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1788
1789 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1790 remote_adv = 0;
1791
1792 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1793
1794 /* If we are not advertising full pause capability,
1795 * something is wrong. Bring the link down and reconfigure.
1796 */
1797 if (local_adv != ADVERTISE_PAUSE_CAP) {
1798 current_link_up = 0;
1799 } else {
1800 tg3_setup_flow_control(tp, local_adv, remote_adv);
1801 }
1802 }
1803relink:
1804 if (current_link_up == 0) {
1805 u32 tmp;
1806
1807 tg3_phy_copper_begin(tp);
1808
1809 tg3_readphy(tp, MII_BMSR, &tmp);
1810 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1811 (tmp & BMSR_LSTATUS))
1812 current_link_up = 1;
1813 }
1814
1815 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1816 if (current_link_up == 1) {
1817 if (tp->link_config.active_speed == SPEED_100 ||
1818 tp->link_config.active_speed == SPEED_10)
1819 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1820 else
1821 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1822 } else
1823 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1824
1825 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1826 if (tp->link_config.active_duplex == DUPLEX_HALF)
1827 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1828
1829 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1830 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1831 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1832 (current_link_up == 1 &&
1833 tp->link_config.active_speed == SPEED_10))
1834 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1835 } else {
1836 if (current_link_up == 1)
1837 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1838 }
1839
1840 /* ??? Without this setting Netgear GA302T PHY does not
1841 * ??? send/receive packets...
1842 */
1843 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1844 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1845 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1846 tw32_f(MAC_MI_MODE, tp->mi_mode);
1847 udelay(80);
1848 }
1849
1850 tw32_f(MAC_MODE, tp->mac_mode);
1851 udelay(40);
1852
1853 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1854 /* Polled via timer. */
1855 tw32_f(MAC_EVENT, 0);
1856 } else {
1857 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1858 }
1859 udelay(40);
1860
1861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1862 current_link_up == 1 &&
1863 tp->link_config.active_speed == SPEED_1000 &&
1864 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1865 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1866 udelay(120);
1867 tw32_f(MAC_STATUS,
1868 (MAC_STATUS_SYNC_CHANGED |
1869 MAC_STATUS_CFG_CHANGED));
1870 udelay(40);
1871 tg3_write_mem(tp,
1872 NIC_SRAM_FIRMWARE_MBOX,
1873 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1874 }
1875
1876 if (current_link_up != netif_carrier_ok(tp->dev)) {
1877 if (current_link_up)
1878 netif_carrier_on(tp->dev);
1879 else
1880 netif_carrier_off(tp->dev);
1881 tg3_link_report(tp);
1882 }
1883
1884 return 0;
1885}
1886
1887struct tg3_fiber_aneginfo {
1888 int state;
1889#define ANEG_STATE_UNKNOWN 0
1890#define ANEG_STATE_AN_ENABLE 1
1891#define ANEG_STATE_RESTART_INIT 2
1892#define ANEG_STATE_RESTART 3
1893#define ANEG_STATE_DISABLE_LINK_OK 4
1894#define ANEG_STATE_ABILITY_DETECT_INIT 5
1895#define ANEG_STATE_ABILITY_DETECT 6
1896#define ANEG_STATE_ACK_DETECT_INIT 7
1897#define ANEG_STATE_ACK_DETECT 8
1898#define ANEG_STATE_COMPLETE_ACK_INIT 9
1899#define ANEG_STATE_COMPLETE_ACK 10
1900#define ANEG_STATE_IDLE_DETECT_INIT 11
1901#define ANEG_STATE_IDLE_DETECT 12
1902#define ANEG_STATE_LINK_OK 13
1903#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1904#define ANEG_STATE_NEXT_PAGE_WAIT 15
1905
1906 u32 flags;
1907#define MR_AN_ENABLE 0x00000001
1908#define MR_RESTART_AN 0x00000002
1909#define MR_AN_COMPLETE 0x00000004
1910#define MR_PAGE_RX 0x00000008
1911#define MR_NP_LOADED 0x00000010
1912#define MR_TOGGLE_TX 0x00000020
1913#define MR_LP_ADV_FULL_DUPLEX 0x00000040
1914#define MR_LP_ADV_HALF_DUPLEX 0x00000080
1915#define MR_LP_ADV_SYM_PAUSE 0x00000100
1916#define MR_LP_ADV_ASYM_PAUSE 0x00000200
1917#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1918#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1919#define MR_LP_ADV_NEXT_PAGE 0x00001000
1920#define MR_TOGGLE_RX 0x00002000
1921#define MR_NP_RX 0x00004000
1922
1923#define MR_LINK_OK 0x80000000
1924
1925 unsigned long link_time, cur_time;
1926
1927 u32 ability_match_cfg;
1928 int ability_match_count;
1929
1930 char ability_match, idle_match, ack_match;
1931
1932 u32 txconfig, rxconfig;
1933#define ANEG_CFG_NP 0x00000080
1934#define ANEG_CFG_ACK 0x00000040
1935#define ANEG_CFG_RF2 0x00000020
1936#define ANEG_CFG_RF1 0x00000010
1937#define ANEG_CFG_PS2 0x00000001
1938#define ANEG_CFG_PS1 0x00008000
1939#define ANEG_CFG_HD 0x00004000
1940#define ANEG_CFG_FD 0x00002000
1941#define ANEG_CFG_INVAL 0x00001f06
1942
1943};
1944#define ANEG_OK 0
1945#define ANEG_DONE 1
1946#define ANEG_TIMER_ENAB 2
1947#define ANEG_FAILED -1
1948
1949#define ANEG_STATE_SETTLE_TIME 10000
1950
1951static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1952 struct tg3_fiber_aneginfo *ap)
1953{
1954 unsigned long delta;
1955 u32 rx_cfg_reg;
1956 int ret;
1957
1958 if (ap->state == ANEG_STATE_UNKNOWN) {
1959 ap->rxconfig = 0;
1960 ap->link_time = 0;
1961 ap->cur_time = 0;
1962 ap->ability_match_cfg = 0;
1963 ap->ability_match_count = 0;
1964 ap->ability_match = 0;
1965 ap->idle_match = 0;
1966 ap->ack_match = 0;
1967 }
1968 ap->cur_time++;
1969
1970 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1971 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1972
1973 if (rx_cfg_reg != ap->ability_match_cfg) {
1974 ap->ability_match_cfg = rx_cfg_reg;
1975 ap->ability_match = 0;
1976 ap->ability_match_count = 0;
1977 } else {
1978 if (++ap->ability_match_count > 1) {
1979 ap->ability_match = 1;
1980 ap->ability_match_cfg = rx_cfg_reg;
1981 }
1982 }
1983 if (rx_cfg_reg & ANEG_CFG_ACK)
1984 ap->ack_match = 1;
1985 else
1986 ap->ack_match = 0;
1987
1988 ap->idle_match = 0;
1989 } else {
1990 ap->idle_match = 1;
1991 ap->ability_match_cfg = 0;
1992 ap->ability_match_count = 0;
1993 ap->ability_match = 0;
1994 ap->ack_match = 0;
1995
1996 rx_cfg_reg = 0;
1997 }
1998
1999 ap->rxconfig = rx_cfg_reg;
2000 ret = ANEG_OK;
2001
2002 switch(ap->state) {
2003 case ANEG_STATE_UNKNOWN:
2004 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2005 ap->state = ANEG_STATE_AN_ENABLE;
2006
2007 /* fallthru */
2008 case ANEG_STATE_AN_ENABLE:
2009 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2010 if (ap->flags & MR_AN_ENABLE) {
2011 ap->link_time = 0;
2012 ap->cur_time = 0;
2013 ap->ability_match_cfg = 0;
2014 ap->ability_match_count = 0;
2015 ap->ability_match = 0;
2016 ap->idle_match = 0;
2017 ap->ack_match = 0;
2018
2019 ap->state = ANEG_STATE_RESTART_INIT;
2020 } else {
2021 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2022 }
2023 break;
2024
2025 case ANEG_STATE_RESTART_INIT:
2026 ap->link_time = ap->cur_time;
2027 ap->flags &= ~(MR_NP_LOADED);
2028 ap->txconfig = 0;
2029 tw32(MAC_TX_AUTO_NEG, 0);
2030 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2031 tw32_f(MAC_MODE, tp->mac_mode);
2032 udelay(40);
2033
2034 ret = ANEG_TIMER_ENAB;
2035 ap->state = ANEG_STATE_RESTART;
2036
2037 /* fallthru */
2038 case ANEG_STATE_RESTART:
2039 delta = ap->cur_time - ap->link_time;
2040 if (delta > ANEG_STATE_SETTLE_TIME) {
2041 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2042 } else {
2043 ret = ANEG_TIMER_ENAB;
2044 }
2045 break;
2046
2047 case ANEG_STATE_DISABLE_LINK_OK:
2048 ret = ANEG_DONE;
2049 break;
2050
2051 case ANEG_STATE_ABILITY_DETECT_INIT:
2052 ap->flags &= ~(MR_TOGGLE_TX);
2053 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2054 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2055 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2056 tw32_f(MAC_MODE, tp->mac_mode);
2057 udelay(40);
2058
2059 ap->state = ANEG_STATE_ABILITY_DETECT;
2060 break;
2061
2062 case ANEG_STATE_ABILITY_DETECT:
2063 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2064 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2065 }
2066 break;
2067
2068 case ANEG_STATE_ACK_DETECT_INIT:
2069 ap->txconfig |= ANEG_CFG_ACK;
2070 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2071 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2072 tw32_f(MAC_MODE, tp->mac_mode);
2073 udelay(40);
2074
2075 ap->state = ANEG_STATE_ACK_DETECT;
2076
2077 /* fallthru */
2078 case ANEG_STATE_ACK_DETECT:
2079 if (ap->ack_match != 0) {
2080 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2081 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2082 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2083 } else {
2084 ap->state = ANEG_STATE_AN_ENABLE;
2085 }
2086 } else if (ap->ability_match != 0 &&
2087 ap->rxconfig == 0) {
2088 ap->state = ANEG_STATE_AN_ENABLE;
2089 }
2090 break;
2091
2092 case ANEG_STATE_COMPLETE_ACK_INIT:
2093 if (ap->rxconfig & ANEG_CFG_INVAL) {
2094 ret = ANEG_FAILED;
2095 break;
2096 }
2097 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2098 MR_LP_ADV_HALF_DUPLEX |
2099 MR_LP_ADV_SYM_PAUSE |
2100 MR_LP_ADV_ASYM_PAUSE |
2101 MR_LP_ADV_REMOTE_FAULT1 |
2102 MR_LP_ADV_REMOTE_FAULT2 |
2103 MR_LP_ADV_NEXT_PAGE |
2104 MR_TOGGLE_RX |
2105 MR_NP_RX);
2106 if (ap->rxconfig & ANEG_CFG_FD)
2107 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2108 if (ap->rxconfig & ANEG_CFG_HD)
2109 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2110 if (ap->rxconfig & ANEG_CFG_PS1)
2111 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2112 if (ap->rxconfig & ANEG_CFG_PS2)
2113 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2114 if (ap->rxconfig & ANEG_CFG_RF1)
2115 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2116 if (ap->rxconfig & ANEG_CFG_RF2)
2117 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2118 if (ap->rxconfig & ANEG_CFG_NP)
2119 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2120
2121 ap->link_time = ap->cur_time;
2122
2123 ap->flags ^= (MR_TOGGLE_TX);
2124 if (ap->rxconfig & 0x0008)
2125 ap->flags |= MR_TOGGLE_RX;
2126 if (ap->rxconfig & ANEG_CFG_NP)
2127 ap->flags |= MR_NP_RX;
2128 ap->flags |= MR_PAGE_RX;
2129
2130 ap->state = ANEG_STATE_COMPLETE_ACK;
2131 ret = ANEG_TIMER_ENAB;
2132 break;
2133
2134 case ANEG_STATE_COMPLETE_ACK:
2135 if (ap->ability_match != 0 &&
2136 ap->rxconfig == 0) {
2137 ap->state = ANEG_STATE_AN_ENABLE;
2138 break;
2139 }
2140 delta = ap->cur_time - ap->link_time;
2141 if (delta > ANEG_STATE_SETTLE_TIME) {
2142 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2143 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2144 } else {
2145 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2146 !(ap->flags & MR_NP_RX)) {
2147 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2148 } else {
2149 ret = ANEG_FAILED;
2150 }
2151 }
2152 }
2153 break;
2154
2155 case ANEG_STATE_IDLE_DETECT_INIT:
2156 ap->link_time = ap->cur_time;
2157 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2158 tw32_f(MAC_MODE, tp->mac_mode);
2159 udelay(40);
2160
2161 ap->state = ANEG_STATE_IDLE_DETECT;
2162 ret = ANEG_TIMER_ENAB;
2163 break;
2164
2165 case ANEG_STATE_IDLE_DETECT:
2166 if (ap->ability_match != 0 &&
2167 ap->rxconfig == 0) {
2168 ap->state = ANEG_STATE_AN_ENABLE;
2169 break;
2170 }
2171 delta = ap->cur_time - ap->link_time;
2172 if (delta > ANEG_STATE_SETTLE_TIME) {
2173 /* XXX another gem from the Broadcom driver :( */
2174 ap->state = ANEG_STATE_LINK_OK;
2175 }
2176 break;
2177
2178 case ANEG_STATE_LINK_OK:
2179 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2180 ret = ANEG_DONE;
2181 break;
2182
2183 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2184 /* ??? unimplemented */
2185 break;
2186
2187 case ANEG_STATE_NEXT_PAGE_WAIT:
2188 /* ??? unimplemented */
2189 break;
2190
2191 default:
2192 ret = ANEG_FAILED;
2193 break;
2194 };
2195
2196 return ret;
2197}
2198
2199static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2200{
2201 int res = 0;
2202 struct tg3_fiber_aneginfo aninfo;
2203 int status = ANEG_FAILED;
2204 unsigned int tick;
2205 u32 tmp;
2206
2207 tw32_f(MAC_TX_AUTO_NEG, 0);
2208
2209 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2210 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2211 udelay(40);
2212
2213 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2214 udelay(40);
2215
2216 memset(&aninfo, 0, sizeof(aninfo));
2217 aninfo.flags |= MR_AN_ENABLE;
2218 aninfo.state = ANEG_STATE_UNKNOWN;
2219 aninfo.cur_time = 0;
2220 tick = 0;
2221 while (++tick < 195000) {
2222 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2223 if (status == ANEG_DONE || status == ANEG_FAILED)
2224 break;
2225
2226 udelay(1);
2227 }
2228
2229 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2230 tw32_f(MAC_MODE, tp->mac_mode);
2231 udelay(40);
2232
2233 *flags = aninfo.flags;
2234
2235 if (status == ANEG_DONE &&
2236 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2237 MR_LP_ADV_FULL_DUPLEX)))
2238 res = 1;
2239
2240 return res;
2241}
2242
2243static void tg3_init_bcm8002(struct tg3 *tp)
2244{
2245 u32 mac_status = tr32(MAC_STATUS);
2246 int i;
2247
2248 /* Reset when initting first time or we have a link. */
2249 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2250 !(mac_status & MAC_STATUS_PCS_SYNCED))
2251 return;
2252
2253 /* Set PLL lock range. */
2254 tg3_writephy(tp, 0x16, 0x8007);
2255
2256 /* SW reset */
2257 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2258
2259 /* Wait for reset to complete. */
2260 /* XXX schedule_timeout() ... */
2261 for (i = 0; i < 500; i++)
2262 udelay(10);
2263
2264 /* Config mode; select PMA/Ch 1 regs. */
2265 tg3_writephy(tp, 0x10, 0x8411);
2266
2267 /* Enable auto-lock and comdet, select txclk for tx. */
2268 tg3_writephy(tp, 0x11, 0x0a10);
2269
2270 tg3_writephy(tp, 0x18, 0x00a0);
2271 tg3_writephy(tp, 0x16, 0x41ff);
2272
2273 /* Assert and deassert POR. */
2274 tg3_writephy(tp, 0x13, 0x0400);
2275 udelay(40);
2276 tg3_writephy(tp, 0x13, 0x0000);
2277
2278 tg3_writephy(tp, 0x11, 0x0a50);
2279 udelay(40);
2280 tg3_writephy(tp, 0x11, 0x0a10);
2281
2282 /* Wait for signal to stabilize */
2283 /* XXX schedule_timeout() ... */
2284 for (i = 0; i < 15000; i++)
2285 udelay(10);
2286
2287 /* Deselect the channel register so we can read the PHYID
2288 * later.
2289 */
2290 tg3_writephy(tp, 0x10, 0x8011);
2291}
2292
2293static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2294{
2295 u32 sg_dig_ctrl, sg_dig_status;
2296 u32 serdes_cfg, expected_sg_dig_ctrl;
2297 int workaround, port_a;
2298 int current_link_up;
2299
2300 serdes_cfg = 0;
2301 expected_sg_dig_ctrl = 0;
2302 workaround = 0;
2303 port_a = 1;
2304 current_link_up = 0;
2305
2306 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2307 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2308 workaround = 1;
2309 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2310 port_a = 0;
2311
2312 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2313 /* preserve bits 20-23 for voltage regulator */
2314 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2315 }
2316
2317 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2318
2319 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2320 if (sg_dig_ctrl & (1 << 31)) {
2321 if (workaround) {
2322 u32 val = serdes_cfg;
2323
2324 if (port_a)
2325 val |= 0xc010000;
2326 else
2327 val |= 0x4010000;
2328 tw32_f(MAC_SERDES_CFG, val);
2329 }
2330 tw32_f(SG_DIG_CTRL, 0x01388400);
2331 }
2332 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2333 tg3_setup_flow_control(tp, 0, 0);
2334 current_link_up = 1;
2335 }
2336 goto out;
2337 }
2338
2339 /* Want auto-negotiation. */
2340 expected_sg_dig_ctrl = 0x81388400;
2341
2342 /* Pause capability */
2343 expected_sg_dig_ctrl |= (1 << 11);
2344
2345 /* Asymettric pause */
2346 expected_sg_dig_ctrl |= (1 << 12);
2347
2348 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2349 if (workaround)
2350 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2351 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2352 udelay(5);
2353 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2354
2355 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2356 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2357 MAC_STATUS_SIGNAL_DET)) {
2358 int i;
2359
2360 /* Giver time to negotiate (~200ms) */
2361 for (i = 0; i < 40000; i++) {
2362 sg_dig_status = tr32(SG_DIG_STATUS);
2363 if (sg_dig_status & (0x3))
2364 break;
2365 udelay(5);
2366 }
2367 mac_status = tr32(MAC_STATUS);
2368
2369 if ((sg_dig_status & (1 << 1)) &&
2370 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2371 u32 local_adv, remote_adv;
2372
2373 local_adv = ADVERTISE_PAUSE_CAP;
2374 remote_adv = 0;
2375 if (sg_dig_status & (1 << 19))
2376 remote_adv |= LPA_PAUSE_CAP;
2377 if (sg_dig_status & (1 << 20))
2378 remote_adv |= LPA_PAUSE_ASYM;
2379
2380 tg3_setup_flow_control(tp, local_adv, remote_adv);
2381 current_link_up = 1;
2382 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2383 } else if (!(sg_dig_status & (1 << 1))) {
2384 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2385 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2386 else {
2387 if (workaround) {
2388 u32 val = serdes_cfg;
2389
2390 if (port_a)
2391 val |= 0xc010000;
2392 else
2393 val |= 0x4010000;
2394
2395 tw32_f(MAC_SERDES_CFG, val);
2396 }
2397
2398 tw32_f(SG_DIG_CTRL, 0x01388400);
2399 udelay(40);
2400
2401 /* Link parallel detection - link is up */
2402 /* only if we have PCS_SYNC and not */
2403 /* receiving config code words */
2404 mac_status = tr32(MAC_STATUS);
2405 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2406 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2407 tg3_setup_flow_control(tp, 0, 0);
2408 current_link_up = 1;
2409 }
2410 }
2411 }
2412 }
2413
2414out:
2415 return current_link_up;
2416}
2417
2418static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2419{
2420 int current_link_up = 0;
2421
2422 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2423 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2424 goto out;
2425 }
2426
2427 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2428 u32 flags;
2429 int i;
2430
2431 if (fiber_autoneg(tp, &flags)) {
2432 u32 local_adv, remote_adv;
2433
2434 local_adv = ADVERTISE_PAUSE_CAP;
2435 remote_adv = 0;
2436 if (flags & MR_LP_ADV_SYM_PAUSE)
2437 remote_adv |= LPA_PAUSE_CAP;
2438 if (flags & MR_LP_ADV_ASYM_PAUSE)
2439 remote_adv |= LPA_PAUSE_ASYM;
2440
2441 tg3_setup_flow_control(tp, local_adv, remote_adv);
2442
2443 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2444 current_link_up = 1;
2445 }
2446 for (i = 0; i < 30; i++) {
2447 udelay(20);
2448 tw32_f(MAC_STATUS,
2449 (MAC_STATUS_SYNC_CHANGED |
2450 MAC_STATUS_CFG_CHANGED));
2451 udelay(40);
2452 if ((tr32(MAC_STATUS) &
2453 (MAC_STATUS_SYNC_CHANGED |
2454 MAC_STATUS_CFG_CHANGED)) == 0)
2455 break;
2456 }
2457
2458 mac_status = tr32(MAC_STATUS);
2459 if (current_link_up == 0 &&
2460 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2461 !(mac_status & MAC_STATUS_RCVD_CFG))
2462 current_link_up = 1;
2463 } else {
2464 /* Forcing 1000FD link up. */
2465 current_link_up = 1;
2466 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2467
2468 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2469 udelay(40);
2470 }
2471
2472out:
2473 return current_link_up;
2474}
2475
2476static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2477{
2478 u32 orig_pause_cfg;
2479 u16 orig_active_speed;
2480 u8 orig_active_duplex;
2481 u32 mac_status;
2482 int current_link_up;
2483 int i;
2484
2485 orig_pause_cfg =
2486 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2487 TG3_FLAG_TX_PAUSE));
2488 orig_active_speed = tp->link_config.active_speed;
2489 orig_active_duplex = tp->link_config.active_duplex;
2490
2491 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2492 netif_carrier_ok(tp->dev) &&
2493 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2494 mac_status = tr32(MAC_STATUS);
2495 mac_status &= (MAC_STATUS_PCS_SYNCED |
2496 MAC_STATUS_SIGNAL_DET |
2497 MAC_STATUS_CFG_CHANGED |
2498 MAC_STATUS_RCVD_CFG);
2499 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2500 MAC_STATUS_SIGNAL_DET)) {
2501 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2502 MAC_STATUS_CFG_CHANGED));
2503 return 0;
2504 }
2505 }
2506
2507 tw32_f(MAC_TX_AUTO_NEG, 0);
2508
2509 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2510 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2511 tw32_f(MAC_MODE, tp->mac_mode);
2512 udelay(40);
2513
2514 if (tp->phy_id == PHY_ID_BCM8002)
2515 tg3_init_bcm8002(tp);
2516
2517 /* Enable link change event even when serdes polling. */
2518 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2519 udelay(40);
2520
2521 current_link_up = 0;
2522 mac_status = tr32(MAC_STATUS);
2523
2524 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2525 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2526 else
2527 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2528
2529 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2530 tw32_f(MAC_MODE, tp->mac_mode);
2531 udelay(40);
2532
2533 tp->hw_status->status =
2534 (SD_STATUS_UPDATED |
2535 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2536
2537 for (i = 0; i < 100; i++) {
2538 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2539 MAC_STATUS_CFG_CHANGED));
2540 udelay(5);
2541 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2542 MAC_STATUS_CFG_CHANGED)) == 0)
2543 break;
2544 }
2545
2546 mac_status = tr32(MAC_STATUS);
2547 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2548 current_link_up = 0;
2549 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2550 tw32_f(MAC_MODE, (tp->mac_mode |
2551 MAC_MODE_SEND_CONFIGS));
2552 udelay(1);
2553 tw32_f(MAC_MODE, tp->mac_mode);
2554 }
2555 }
2556
2557 if (current_link_up == 1) {
2558 tp->link_config.active_speed = SPEED_1000;
2559 tp->link_config.active_duplex = DUPLEX_FULL;
2560 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2561 LED_CTRL_LNKLED_OVERRIDE |
2562 LED_CTRL_1000MBPS_ON));
2563 } else {
2564 tp->link_config.active_speed = SPEED_INVALID;
2565 tp->link_config.active_duplex = DUPLEX_INVALID;
2566 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2567 LED_CTRL_LNKLED_OVERRIDE |
2568 LED_CTRL_TRAFFIC_OVERRIDE));
2569 }
2570
2571 if (current_link_up != netif_carrier_ok(tp->dev)) {
2572 if (current_link_up)
2573 netif_carrier_on(tp->dev);
2574 else
2575 netif_carrier_off(tp->dev);
2576 tg3_link_report(tp);
2577 } else {
2578 u32 now_pause_cfg =
2579 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2580 TG3_FLAG_TX_PAUSE);
2581 if (orig_pause_cfg != now_pause_cfg ||
2582 orig_active_speed != tp->link_config.active_speed ||
2583 orig_active_duplex != tp->link_config.active_duplex)
2584 tg3_link_report(tp);
2585 }
2586
2587 return 0;
2588}
2589
747e8f8b
MC		 2590static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2591{
2592 int current_link_up, err = 0;
2593 u32 bmsr, bmcr;
2594 u16 current_speed;
2595 u8 current_duplex;
2596
2597 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2598 tw32_f(MAC_MODE, tp->mac_mode);
2599 udelay(40);
2600
2601 tw32(MAC_EVENT, 0);
2602
2603 tw32_f(MAC_STATUS,
2604 (MAC_STATUS_SYNC_CHANGED |
2605 MAC_STATUS_CFG_CHANGED |
2606 MAC_STATUS_MI_COMPLETION |
2607 MAC_STATUS_LNKSTATE_CHANGED));
2608 udelay(40);
2609
2610 if (force_reset)
2611 tg3_phy_reset(tp);
2612
2613 current_link_up = 0;
2614 current_speed = SPEED_INVALID;
2615 current_duplex = DUPLEX_INVALID;
2616
2617 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2618 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2619
2620 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2621
2622 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2623 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2624 /* do nothing, just check for link up at the end */
2625 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2626 u32 adv, new_adv;
2627
2628 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2629 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2630 ADVERTISE_1000XPAUSE |
2631 ADVERTISE_1000XPSE_ASYM |
2632 ADVERTISE_SLCT);
2633
2634 /* Always advertise symmetric PAUSE just like copper */
2635 new_adv |= ADVERTISE_1000XPAUSE;
2636
2637 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2638 new_adv |= ADVERTISE_1000XHALF;
2639 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2640 new_adv |= ADVERTISE_1000XFULL;
2641
2642 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2643 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2644 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2645 tg3_writephy(tp, MII_BMCR, bmcr);
2646
2647 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2648 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2649 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2650
2651 return err;
2652 }
2653 } else {
2654 u32 new_bmcr;
2655
2656 bmcr &= ~BMCR_SPEED1000;
2657 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2658
2659 if (tp->link_config.duplex == DUPLEX_FULL)
2660 new_bmcr |= BMCR_FULLDPLX;
2661
2662 if (new_bmcr != bmcr) {
2663 /* BMCR_SPEED1000 is a reserved bit that needs
2664 * to be set on write.
2665 */
2666 new_bmcr |= BMCR_SPEED1000;
2667
2668 /* Force a linkdown */
2669 if (netif_carrier_ok(tp->dev)) {
2670 u32 adv;
2671
2672 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2673 adv &= ~(ADVERTISE_1000XFULL |
2674 ADVERTISE_1000XHALF |
2675 ADVERTISE_SLCT);
2676 tg3_writephy(tp, MII_ADVERTISE, adv);
2677 tg3_writephy(tp, MII_BMCR, bmcr |
2678 BMCR_ANRESTART |
2679 BMCR_ANENABLE);
2680 udelay(10);
2681 netif_carrier_off(tp->dev);
2682 }
2683 tg3_writephy(tp, MII_BMCR, new_bmcr);
2684 bmcr = new_bmcr;
2685 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2686 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2687 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2688 }
2689 }
2690
2691 if (bmsr & BMSR_LSTATUS) {
2692 current_speed = SPEED_1000;
2693 current_link_up = 1;
2694 if (bmcr & BMCR_FULLDPLX)
2695 current_duplex = DUPLEX_FULL;
2696 else
2697 current_duplex = DUPLEX_HALF;
2698
2699 if (bmcr & BMCR_ANENABLE) {
2700 u32 local_adv, remote_adv, common;
2701
2702 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2703 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2704 common = local_adv & remote_adv;
2705 if (common & (ADVERTISE_1000XHALF |
2706 ADVERTISE_1000XFULL)) {
2707 if (common & ADVERTISE_1000XFULL)
2708 current_duplex = DUPLEX_FULL;
2709 else
2710 current_duplex = DUPLEX_HALF;
2711
2712 tg3_setup_flow_control(tp, local_adv,
2713 remote_adv);
2714 }
2715 else
2716 current_link_up = 0;
2717 }
2718 }
2719
2720 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2721 if (tp->link_config.active_duplex == DUPLEX_HALF)
2722 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2723
2724 tw32_f(MAC_MODE, tp->mac_mode);
2725 udelay(40);
2726
2727 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2728
2729 tp->link_config.active_speed = current_speed;
2730 tp->link_config.active_duplex = current_duplex;
2731
2732 if (current_link_up != netif_carrier_ok(tp->dev)) {
2733 if (current_link_up)
2734 netif_carrier_on(tp->dev);
2735 else {
2736 netif_carrier_off(tp->dev);
2737 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2738 }
2739 tg3_link_report(tp);
2740 }
2741 return err;
2742}
2743
2744static void tg3_serdes_parallel_detect(struct tg3 *tp)
2745{
2746 if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2747 /* Give autoneg time to complete. */
2748 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2749 return;
2750 }
2751 if (!netif_carrier_ok(tp->dev) &&
2752 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2753 u32 bmcr;
2754
2755 tg3_readphy(tp, MII_BMCR, &bmcr);
2756 if (bmcr & BMCR_ANENABLE) {
2757 u32 phy1, phy2;
2758
2759 /* Select shadow register 0x1f */
2760 tg3_writephy(tp, 0x1c, 0x7c00);
2761 tg3_readphy(tp, 0x1c, &phy1);
2762
2763 /* Select expansion interrupt status register */
2764 tg3_writephy(tp, 0x17, 0x0f01);
2765 tg3_readphy(tp, 0x15, &phy2);
2766 tg3_readphy(tp, 0x15, &phy2);
2767
2768 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2769 /* We have signal detect and not receiving
2770 * config code words, link is up by parallel
2771 * detection.
2772 */
2773
2774 bmcr &= ~BMCR_ANENABLE;
2775 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2776 tg3_writephy(tp, MII_BMCR, bmcr);
2777 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2778 }
2779 }
2780 }
2781 else if (netif_carrier_ok(tp->dev) &&
2782 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2783 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2784 u32 phy2;
2785
2786 /* Select expansion interrupt status register */
2787 tg3_writephy(tp, 0x17, 0x0f01);
2788 tg3_readphy(tp, 0x15, &phy2);
2789 if (phy2 & 0x20) {
2790 u32 bmcr;
2791
2792 /* Config code words received, turn on autoneg. */
2793 tg3_readphy(tp, MII_BMCR, &bmcr);
2794 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2795
2796 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2797
2798 }
2799 }
2800}
2801
1da177e4
LT		 2802static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2803{
2804 int err;
2805
2806 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2807 err = tg3_setup_fiber_phy(tp, force_reset);
747e8f8b
MC		 2808 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2809 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1da177e4
LT		 2810 } else {
2811 err = tg3_setup_copper_phy(tp, force_reset);
2812 }
2813
2814 if (tp->link_config.active_speed == SPEED_1000 &&
2815 tp->link_config.active_duplex == DUPLEX_HALF)
2816 tw32(MAC_TX_LENGTHS,
2817 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2818 (6 << TX_LENGTHS_IPG_SHIFT) |
2819 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2820 else
2821 tw32(MAC_TX_LENGTHS,
2822 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2823 (6 << TX_LENGTHS_IPG_SHIFT) |
2824 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2825
2826 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2827 if (netif_carrier_ok(tp->dev)) {
2828 tw32(HOSTCC_STAT_COAL_TICKS,
15f9850d 2829 tp->coal.stats_block_coalesce_usecs);
1da177e4
LT		 2830 } else {
2831 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2832 }
2833 }
2834
2835 return err;
2836}
2837
2838/* Tigon3 never reports partial packet sends. So we do not
2839 * need special logic to handle SKBs that have not had all
2840 * of their frags sent yet, like SunGEM does.
2841 */
2842static void tg3_tx(struct tg3 *tp)
2843{
2844 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2845 u32 sw_idx = tp->tx_cons;
2846
2847 while (sw_idx != hw_idx) {
2848 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2849 struct sk_buff *skb = ri->skb;
2850 int i;
2851
2852 if (unlikely(skb == NULL))
2853 BUG();
2854
2855 pci_unmap_single(tp->pdev,
2856 pci_unmap_addr(ri, mapping),
2857 skb_headlen(skb),
2858 PCI_DMA_TODEVICE);
2859
2860 ri->skb = NULL;
2861
2862 sw_idx = NEXT_TX(sw_idx);
2863
2864 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2865 if (unlikely(sw_idx == hw_idx))
2866 BUG();
2867
2868 ri = &tp->tx_buffers[sw_idx];
2869 if (unlikely(ri->skb != NULL))
2870 BUG();
2871
2872 pci_unmap_page(tp->pdev,
2873 pci_unmap_addr(ri, mapping),
2874 skb_shinfo(skb)->frags[i].size,
2875 PCI_DMA_TODEVICE);
2876
2877 sw_idx = NEXT_TX(sw_idx);
2878 }
2879
f47c11ee 2880 dev_kfree_skb(skb);
1da177e4
LT		 2881 }
2882
2883 tp->tx_cons = sw_idx;
2884
2885 if (netif_queue_stopped(tp->dev) &&
2886 (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2887 netif_wake_queue(tp->dev);
2888}
2889
2890/* Returns size of skb allocated or < 0 on error.
2891 *
2892 * We only need to fill in the address because the other members
2893 * of the RX descriptor are invariant, see tg3_init_rings.
2894 *
2895 * Note the purposeful assymetry of cpu vs. chip accesses. For
2896 * posting buffers we only dirty the first cache line of the RX
2897 * descriptor (containing the address). Whereas for the RX status
2898 * buffers the cpu only reads the last cacheline of the RX descriptor
2899 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2900 */
2901static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2902 int src_idx, u32 dest_idx_unmasked)
2903{
2904 struct tg3_rx_buffer_desc *desc;
2905 struct ring_info *map, *src_map;
2906 struct sk_buff *skb;
2907 dma_addr_t mapping;
2908 int skb_size, dest_idx;
2909
2910 src_map = NULL;
2911 switch (opaque_key) {
2912 case RXD_OPAQUE_RING_STD:
2913 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2914 desc = &tp->rx_std[dest_idx];
2915 map = &tp->rx_std_buffers[dest_idx];
2916 if (src_idx >= 0)
2917 src_map = &tp->rx_std_buffers[src_idx];
7e72aad4 2918 skb_size = tp->rx_pkt_buf_sz;
1da177e4
LT		 2919 break;
2920
2921 case RXD_OPAQUE_RING_JUMBO:
2922 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2923 desc = &tp->rx_jumbo[dest_idx];
2924 map = &tp->rx_jumbo_buffers[dest_idx];
2925 if (src_idx >= 0)
2926 src_map = &tp->rx_jumbo_buffers[src_idx];
2927 skb_size = RX_JUMBO_PKT_BUF_SZ;
2928 break;
2929
2930 default:
2931 return -EINVAL;
2932 };
2933
2934 /* Do not overwrite any of the map or rp information
2935 * until we are sure we can commit to a new buffer.
2936 *
2937 * Callers depend upon this behavior and assume that
2938 * we leave everything unchanged if we fail.
2939 */
2940 skb = dev_alloc_skb(skb_size);
2941 if (skb == NULL)
2942 return -ENOMEM;
2943
2944 skb->dev = tp->dev;
2945 skb_reserve(skb, tp->rx_offset);
2946
2947 mapping = pci_map_single(tp->pdev, skb->data,
2948 skb_size - tp->rx_offset,
2949 PCI_DMA_FROMDEVICE);
2950
2951 map->skb = skb;
2952 pci_unmap_addr_set(map, mapping, mapping);
2953
2954 if (src_map != NULL)
2955 src_map->skb = NULL;
2956
2957 desc->addr_hi = ((u64)mapping >> 32);
2958 desc->addr_lo = ((u64)mapping & 0xffffffff);
2959
2960 return skb_size;
2961}
2962
2963/* We only need to move over in the address because the other
2964 * members of the RX descriptor are invariant. See notes above
2965 * tg3_alloc_rx_skb for full details.
2966 */
2967static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2968 int src_idx, u32 dest_idx_unmasked)
2969{
2970 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2971 struct ring_info *src_map, *dest_map;
2972 int dest_idx;
2973
2974 switch (opaque_key) {
2975 case RXD_OPAQUE_RING_STD:
2976 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2977 dest_desc = &tp->rx_std[dest_idx];
2978 dest_map = &tp->rx_std_buffers[dest_idx];
2979 src_desc = &tp->rx_std[src_idx];
2980 src_map = &tp->rx_std_buffers[src_idx];
2981 break;
2982
2983 case RXD_OPAQUE_RING_JUMBO:
2984 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2985 dest_desc = &tp->rx_jumbo[dest_idx];
2986 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2987 src_desc = &tp->rx_jumbo[src_idx];
2988 src_map = &tp->rx_jumbo_buffers[src_idx];
2989 break;
2990
2991 default:
2992 return;
2993 };
2994
2995 dest_map->skb = src_map->skb;
2996 pci_unmap_addr_set(dest_map, mapping,
2997 pci_unmap_addr(src_map, mapping));
2998 dest_desc->addr_hi = src_desc->addr_hi;
2999 dest_desc->addr_lo = src_desc->addr_lo;
3000
3001 src_map->skb = NULL;
3002}
3003
3004#if TG3_VLAN_TAG_USED
3005static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3006{
3007 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3008}
3009#endif
3010
3011/* The RX ring scheme is composed of multiple rings which post fresh
3012 * buffers to the chip, and one special ring the chip uses to report
3013 * status back to the host.
3014 *
3015 * The special ring reports the status of received packets to the
3016 * host. The chip does not write into the original descriptor the
3017 * RX buffer was obtained from. The chip simply takes the original
3018 * descriptor as provided by the host, updates the status and length
3019 * field, then writes this into the next status ring entry.
3020 *
3021 * Each ring the host uses to post buffers to the chip is described
3022 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3023 * it is first placed into the on-chip ram. When the packet's length
3024 * is known, it walks down the TG3_BDINFO entries to select the ring.
3025 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3026 * which is within the range of the new packet's length is chosen.
3027 *
3028 * The "separate ring for rx status" scheme may sound queer, but it makes
3029 * sense from a cache coherency perspective. If only the host writes
3030 * to the buffer post rings, and only the chip writes to the rx status
3031 * rings, then cache lines never move beyond shared-modified state.
3032 * If both the host and chip were to write into the same ring, cache line
3033 * eviction could occur since both entities want it in an exclusive state.
3034 */
3035static int tg3_rx(struct tg3 *tp, int budget)
3036{
3037 u32 work_mask;
483ba50b
MC		 3038 u32 sw_idx = tp->rx_rcb_ptr;
3039 u16 hw_idx;
1da177e4
LT		 3040 int received;
3041
3042 hw_idx = tp->hw_status->idx[0].rx_producer;
3043 /*
3044 * We need to order the read of hw_idx and the read of
3045 * the opaque cookie.
3046 */
3047 rmb();
1da177e4
LT		 3048 work_mask = 0;
3049 received = 0;
3050 while (sw_idx != hw_idx && budget > 0) {
3051 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3052 unsigned int len;
3053 struct sk_buff *skb;
3054 dma_addr_t dma_addr;
3055 u32 opaque_key, desc_idx, *post_ptr;
3056
3057 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3058 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3059 if (opaque_key == RXD_OPAQUE_RING_STD) {
3060 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3061 mapping);
3062 skb = tp->rx_std_buffers[desc_idx].skb;
3063 post_ptr = &tp->rx_std_ptr;
3064 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3065 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3066 mapping);
3067 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3068 post_ptr = &tp->rx_jumbo_ptr;
3069 }
3070 else {
3071 goto next_pkt_nopost;
3072 }
3073
3074 work_mask |= opaque_key;
3075
3076 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3077 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3078 drop_it:
3079 tg3_recycle_rx(tp, opaque_key,
3080 desc_idx, *post_ptr);
3081 drop_it_no_recycle:
3082 /* Other statistics kept track of by card. */
3083 tp->net_stats.rx_dropped++;
3084 goto next_pkt;
3085 }
3086
3087 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3088
3089 if (len > RX_COPY_THRESHOLD
3090 && tp->rx_offset == 2
3091 /* rx_offset != 2 iff this is a 5701 card running
3092 * in PCI-X mode [see tg3_get_invariants()] */
3093 ) {
3094 int skb_size;
3095
3096 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3097 desc_idx, *post_ptr);
3098 if (skb_size < 0)
3099 goto drop_it;
3100
3101 pci_unmap_single(tp->pdev, dma_addr,
3102 skb_size - tp->rx_offset,
3103 PCI_DMA_FROMDEVICE);
3104
3105 skb_put(skb, len);
3106 } else {
3107 struct sk_buff *copy_skb;
3108
3109 tg3_recycle_rx(tp, opaque_key,
3110 desc_idx, *post_ptr);
3111
3112 copy_skb = dev_alloc_skb(len + 2);
3113 if (copy_skb == NULL)
3114 goto drop_it_no_recycle;
3115
3116 copy_skb->dev = tp->dev;
3117 skb_reserve(copy_skb, 2);
3118 skb_put(copy_skb, len);
3119 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3120 memcpy(copy_skb->data, skb->data, len);
3121 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3122
3123 /* We'll reuse the original ring buffer. */
3124 skb = copy_skb;
3125 }
3126
3127 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3128 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3129 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3130 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3131 skb->ip_summed = CHECKSUM_UNNECESSARY;
3132 else
3133 skb->ip_summed = CHECKSUM_NONE;
3134
3135 skb->protocol = eth_type_trans(skb, tp->dev);
3136#if TG3_VLAN_TAG_USED
3137 if (tp->vlgrp != NULL &&
3138 desc->type_flags & RXD_FLAG_VLAN) {
3139 tg3_vlan_rx(tp, skb,
3140 desc->err_vlan & RXD_VLAN_MASK);
3141 } else
3142#endif
3143 netif_receive_skb(skb);
3144
3145 tp->dev->last_rx = jiffies;
3146 received++;
3147 budget--;
3148
3149next_pkt:
3150 (*post_ptr)++;
3151next_pkt_nopost:
483ba50b
MC		 3152 sw_idx++;
3153 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
52f6d697
MC		 3154
3155 /* Refresh hw_idx to see if there is new work */
3156 if (sw_idx == hw_idx) {
3157 hw_idx = tp->hw_status->idx[0].rx_producer;
3158 rmb();
3159 }
1da177e4
LT		 3160 }
3161
3162 /* ACK the status ring. */
483ba50b
MC		 3163 tp->rx_rcb_ptr = sw_idx;
3164 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
1da177e4
LT		 3165
3166 /* Refill RX ring(s). */
3167 if (work_mask & RXD_OPAQUE_RING_STD) {
3168 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3169 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3170 sw_idx);
3171 }
3172 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3173 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3174 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3175 sw_idx);
3176 }
3177 mmiowb();
3178
3179 return received;
3180}
3181
3182static int tg3_poll(struct net_device *netdev, int *budget)
3183{
3184 struct tg3 *tp = netdev_priv(netdev);
3185 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3186 int done;
3187
1da177e4
LT		 3188 /* handle link change and other phy events */
3189 if (!(tp->tg3_flags &
3190 (TG3_FLAG_USE_LINKCHG_REG |
3191 TG3_FLAG_POLL_SERDES))) {
3192 if (sblk->status & SD_STATUS_LINK_CHG) {
3193 sblk->status = SD_STATUS_UPDATED |
3194 (sblk->status & ~SD_STATUS_LINK_CHG);
f47c11ee 3195 spin_lock(&tp->lock);
1da177e4 3196 tg3_setup_phy(tp, 0);
f47c11ee 3197 spin_unlock(&tp->lock);
1da177e4
LT		 3198 }
3199 }
3200
3201 /* run TX completion thread */
3202 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3203 spin_lock(&tp->tx_lock);
3204 tg3_tx(tp);
3205 spin_unlock(&tp->tx_lock);
3206 }
3207
1da177e4
LT		 3208 /* run RX thread, within the bounds set by NAPI.
3209 * All RX "locking" is done by ensuring outside
3210 * code synchronizes with dev->poll()
3211 */
1da177e4
LT		 3212 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3213 int orig_budget = *budget;
3214 int work_done;
3215
3216 if (orig_budget > netdev->quota)
3217 orig_budget = netdev->quota;
3218
3219 work_done = tg3_rx(tp, orig_budget);
3220
3221 *budget -= work_done;
3222 netdev->quota -= work_done;
1da177e4
LT		 3223 }
3224
f7383c22
DM		 3225 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
3226 tp->last_tag = sblk->status_tag;
3227 rmb();
cd024c8b 3228 sblk->status &= ~SD_STATUS_UPDATED;
f7383c22 3229
1da177e4 3230 /* if no more work, tell net stack and NIC we're done */
f7383c22 3231 done = !tg3_has_work(tp);
1da177e4 3232 if (done) {
f47c11ee
DM		 3233 spin_lock(&tp->lock);
3234 netif_rx_complete(netdev);
1da177e4 3235 tg3_restart_ints(tp);
f47c11ee 3236 spin_unlock(&tp->lock);
1da177e4
LT		 3237 }
3238
3239 return (done ? 0 : 1);
3240}
3241
f47c11ee
DM		 3242static void tg3_irq_quiesce(struct tg3 *tp)
3243{
3244 BUG_ON(tp->irq_sync);
3245
3246 tp->irq_sync = 1;
3247 smp_mb();
3248
3249 synchronize_irq(tp->pdev->irq);
3250}
3251
3252static inline int tg3_irq_sync(struct tg3 *tp)
3253{
3254 return tp->irq_sync;
3255}
3256
3257/* Fully shutdown all tg3 driver activity elsewhere in the system.
3258 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3259 * with as well. Most of the time, this is not necessary except when
3260 * shutting down the device.
3261 */
3262static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3263{
3264 if (irq_sync)
3265 tg3_irq_quiesce(tp);
3266 spin_lock_bh(&tp->lock);
3267 spin_lock(&tp->tx_lock);
3268}
3269
3270static inline void tg3_full_unlock(struct tg3 *tp)
3271{
3272 spin_unlock(&tp->tx_lock);
3273 spin_unlock_bh(&tp->lock);
3274}
3275
88b06bc2
MC		 3276/* MSI ISR - No need to check for interrupt sharing and no need to
3277 * flush status block and interrupt mailbox. PCI ordering rules
3278 * guarantee that MSI will arrive after the status block.
3279 */
3280static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3281{
3282 struct net_device *dev = dev_id;
3283 struct tg3 *tp = netdev_priv(dev);
3284 struct tg3_hw_status *sblk = tp->hw_status;
88b06bc2
MC		 3285
3286 /*
fac9b83e 3287 * Writing any value to intr-mbox-0 clears PCI INTA# and
88b06bc2 3288 * chip-internal interrupt pending events.
fac9b83e 3289 * Writing non-zero to intr-mbox-0 additional tells the
88b06bc2
MC		 3290 * NIC to stop sending us irqs, engaging "in-intr-handler"
3291 * event coalescing.
3292 */
3293 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
fac9b83e 3294 tp->last_tag = sblk->status_tag;
cd024c8b 3295 rmb();
f47c11ee
DM		 3296 if (tg3_irq_sync(tp))
3297 goto out;
88b06bc2 3298 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 3299 if (likely(tg3_has_work(tp)))
88b06bc2
MC		 3300 netif_rx_schedule(dev); /* schedule NAPI poll */
3301 else {
fac9b83e 3302 /* No work, re-enable interrupts. */
88b06bc2 3303 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3304 tp->last_tag << 24);
88b06bc2 3305 }
f47c11ee 3306out:
88b06bc2
MC		 3307 return IRQ_RETVAL(1);
3308}
3309
1da177e4
LT		 3310static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3311{
3312 struct net_device *dev = dev_id;
3313 struct tg3 *tp = netdev_priv(dev);
3314 struct tg3_hw_status *sblk = tp->hw_status;
1da177e4
LT		 3315 unsigned int handled = 1;
3316
1da177e4
LT		 3317 /* In INTx mode, it is possible for the interrupt to arrive at
3318 * the CPU before the status block posted prior to the interrupt.
3319 * Reading the PCI State register will confirm whether the
3320 * interrupt is ours and will flush the status block.
3321 */
3322 if ((sblk->status & SD_STATUS_UPDATED) ||
3323 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3324 /*
fac9b83e 3325 * Writing any value to intr-mbox-0 clears PCI INTA# and
1da177e4 3326 * chip-internal interrupt pending events.
fac9b83e 3327 * Writing non-zero to intr-mbox-0 additional tells the
1da177e4
LT		 3328 * NIC to stop sending us irqs, engaging "in-intr-handler"
3329 * event coalescing.
3330 */
3331 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3332 0x00000001);
f47c11ee
DM		 3333 if (tg3_irq_sync(tp))
3334 goto out;
fac9b83e
DM		 3335 sblk->status &= ~SD_STATUS_UPDATED;
3336 if (likely(tg3_has_work(tp)))
3337 netif_rx_schedule(dev); /* schedule NAPI poll */
3338 else {
3339 /* No work, shared interrupt perhaps? re-enable
3340 * interrupts, and flush that PCI write
3341 */
09ee929c 3342 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
fac9b83e 3343 0x00000000);
fac9b83e
DM		 3344 }
3345 } else { /* shared interrupt */
3346 handled = 0;
3347 }
f47c11ee 3348out:
fac9b83e
DM		 3349 return IRQ_RETVAL(handled);
3350}
3351
3352static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3353{
3354 struct net_device *dev = dev_id;
3355 struct tg3 *tp = netdev_priv(dev);
3356 struct tg3_hw_status *sblk = tp->hw_status;
fac9b83e
DM		 3357 unsigned int handled = 1;
3358
fac9b83e
DM		 3359 /* In INTx mode, it is possible for the interrupt to arrive at
3360 * the CPU before the status block posted prior to the interrupt.
3361 * Reading the PCI State register will confirm whether the
3362 * interrupt is ours and will flush the status block.
3363 */
3364 if ((sblk->status & SD_STATUS_UPDATED) ||
3365 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
1da177e4 3366 /*
fac9b83e
DM		 3367 * writing any value to intr-mbox-0 clears PCI INTA# and
3368 * chip-internal interrupt pending events.
3369 * writing non-zero to intr-mbox-0 additional tells the
3370 * NIC to stop sending us irqs, engaging "in-intr-handler"
3371 * event coalescing.
1da177e4 3372 */
fac9b83e
DM		 3373 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3374 0x00000001);
3375 tp->last_tag = sblk->status_tag;
cd024c8b 3376 rmb();
f47c11ee
DM		 3377 if (tg3_irq_sync(tp))
3378 goto out;
1da177e4 3379 sblk->status &= ~SD_STATUS_UPDATED;
04237ddd 3380 if (likely(tg3_has_work(tp)))
1da177e4
LT		 3381 netif_rx_schedule(dev); /* schedule NAPI poll */
3382 else {
3383 /* no work, shared interrupt perhaps? re-enable
3384 * interrupts, and flush that PCI write
3385 */
09ee929c
MC		 3386 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3387 tp->last_tag << 24);
1da177e4
LT		 3388 }
3389 } else { /* shared interrupt */
3390 handled = 0;
3391 }
f47c11ee 3392out:
1da177e4
LT		 3393 return IRQ_RETVAL(handled);
3394}
3395
7938109f
MC		 3396/* ISR for interrupt test */
3397static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3398 struct pt_regs *regs)
3399{
3400 struct net_device *dev = dev_id;
3401 struct tg3 *tp = netdev_priv(dev);
3402 struct tg3_hw_status *sblk = tp->hw_status;
3403
3404 if (sblk->status & SD_STATUS_UPDATED) {
3405 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3406 0x00000001);
3407 return IRQ_RETVAL(1);
3408 }
3409 return IRQ_RETVAL(0);
3410}
3411
1da177e4 3412static int tg3_init_hw(struct tg3 *);
944d980e 3413static int tg3_halt(struct tg3 *, int, int);
1da177e4
LT		 3414
3415#ifdef CONFIG_NET_POLL_CONTROLLER
3416static void tg3_poll_controller(struct net_device *dev)
3417{
88b06bc2
MC		 3418 struct tg3 *tp = netdev_priv(dev);
3419
3420 tg3_interrupt(tp->pdev->irq, dev, NULL);
1da177e4
LT		 3421}
3422#endif
3423
3424static void tg3_reset_task(void *_data)
3425{
3426 struct tg3 *tp = _data;
3427 unsigned int restart_timer;
3428
3429 tg3_netif_stop(tp);
3430
f47c11ee 3431 tg3_full_lock(tp, 1);
1da177e4
LT		 3432
3433 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3434 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3435
944d980e 3436 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
1da177e4
LT		 3437 tg3_init_hw(tp);
3438
3439 tg3_netif_start(tp);
3440
f47c11ee 3441 tg3_full_unlock(tp);
1da177e4
LT		 3442
3443 if (restart_timer)
3444 mod_timer(&tp->timer, jiffies + 1);
3445}
3446
3447static void tg3_tx_timeout(struct net_device *dev)
3448{
3449 struct tg3 *tp = netdev_priv(dev);
3450
3451 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3452 dev->name);
3453
3454 schedule_work(&tp->reset_task);
3455}
3456
3457static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3458
3459static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3460 u32 guilty_entry, int guilty_len,
3461 u32 last_plus_one, u32 *start, u32 mss)
3462{
3463 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3464 dma_addr_t new_addr;
3465 u32 entry = *start;
3466 int i;
3467
3468 if (!new_skb) {
3469 dev_kfree_skb(skb);
3470 return -1;
3471 }
3472
3473 /* New SKB is guaranteed to be linear. */
3474 entry = *start;
3475 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3476 PCI_DMA_TODEVICE);
3477 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3478 (skb->ip_summed == CHECKSUM_HW) ?
3479 TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3480 *start = NEXT_TX(entry);
3481
3482 /* Now clean up the sw ring entries. */
3483 i = 0;
3484 while (entry != last_plus_one) {
3485 int len;
3486
3487 if (i == 0)
3488 len = skb_headlen(skb);
3489 else
3490 len = skb_shinfo(skb)->frags[i-1].size;
3491 pci_unmap_single(tp->pdev,
3492 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3493 len, PCI_DMA_TODEVICE);
3494 if (i == 0) {
3495 tp->tx_buffers[entry].skb = new_skb;
3496 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3497 } else {
3498 tp->tx_buffers[entry].skb = NULL;
3499 }
3500 entry = NEXT_TX(entry);
3501 i++;
3502 }
3503
3504 dev_kfree_skb(skb);
3505
3506 return 0;
3507}
3508
3509static void tg3_set_txd(struct tg3 *tp, int entry,
3510 dma_addr_t mapping, int len, u32 flags,
3511 u32 mss_and_is_end)
3512{
3513 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3514 int is_end = (mss_and_is_end & 0x1);
3515 u32 mss = (mss_and_is_end >> 1);
3516 u32 vlan_tag = 0;
3517
3518 if (is_end)
3519 flags |= TXD_FLAG_END;
3520 if (flags & TXD_FLAG_VLAN) {
3521 vlan_tag = flags >> 16;
3522 flags &= 0xffff;
3523 }
3524 vlan_tag |= (mss << TXD_MSS_SHIFT);
3525
3526 txd->addr_hi = ((u64) mapping >> 32);
3527 txd->addr_lo = ((u64) mapping & 0xffffffff);
3528 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3529 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3530}
3531
3532static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3533{
3534 u32 base = (u32) mapping & 0xffffffff;
3535
3536 return ((base > 0xffffdcc0) &&
3537 (base + len + 8 < base));
3538}
3539
3540static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3541{
3542 struct tg3 *tp = netdev_priv(dev);
3543 dma_addr_t mapping;
3544 unsigned int i;
3545 u32 len, entry, base_flags, mss;
3546 int would_hit_hwbug;
1da177e4
LT		 3547
3548 len = skb_headlen(skb);
3549
3550 /* No BH disabling for tx_lock here. We are running in BH disabled
3551 * context and TX reclaim runs via tp->poll inside of a software
f47c11ee
DM		 3552 * interrupt. Furthermore, IRQ processing runs lockless so we have
3553 * no IRQ context deadlocks to worry about either. Rejoice!
1da177e4 3554 */
f47c11ee 3555 if (!spin_trylock(&tp->tx_lock))
1da177e4 3556 return NETDEV_TX_LOCKED;
1da177e4
LT		 3557
3558 /* This is a hard error, log it. */
3559 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3560 netif_stop_queue(dev);
f47c11ee 3561 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3562 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3563 dev->name);
3564 return NETDEV_TX_BUSY;
3565 }
3566
3567 entry = tp->tx_prod;
3568 base_flags = 0;
3569 if (skb->ip_summed == CHECKSUM_HW)
3570 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3571#if TG3_TSO_SUPPORT != 0
3572 mss = 0;
3573 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3574 (mss = skb_shinfo(skb)->tso_size) != 0) {
3575 int tcp_opt_len, ip_tcp_len;
3576
3577 if (skb_header_cloned(skb) &&
3578 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3579 dev_kfree_skb(skb);
3580 goto out_unlock;
3581 }
3582
3583 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3584 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3585
3586 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3587 TXD_FLAG_CPU_POST_DMA);
3588
3589 skb->nh.iph->check = 0;
3590 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3591 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3592 skb->h.th->check = 0;
3593 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3594 }
3595 else {
3596 skb->h.th->check =
3597 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3598 skb->nh.iph->daddr,
3599 0, IPPROTO_TCP, 0);
3600 }
3601
3602 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3603 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3604 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3605 int tsflags;
3606
3607 tsflags = ((skb->nh.iph->ihl - 5) +
3608 (tcp_opt_len >> 2));
3609 mss |= (tsflags << 11);
3610 }
3611 } else {
3612 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3613 int tsflags;
3614
3615 tsflags = ((skb->nh.iph->ihl - 5) +
3616 (tcp_opt_len >> 2));
3617 base_flags |= tsflags << 12;
3618 }
3619 }
3620 }
3621#else
3622 mss = 0;
3623#endif
3624#if TG3_VLAN_TAG_USED
3625 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3626 base_flags |= (TXD_FLAG_VLAN |
3627 (vlan_tx_tag_get(skb) << 16));
3628#endif
3629
3630 /* Queue skb data, a.k.a. the main skb fragment. */
3631 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3632
3633 tp->tx_buffers[entry].skb = skb;
3634 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3635
3636 would_hit_hwbug = 0;
3637
3638 if (tg3_4g_overflow_test(mapping, len))
3639 would_hit_hwbug = entry + 1;
3640
3641 tg3_set_txd(tp, entry, mapping, len, base_flags,
3642 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3643
3644 entry = NEXT_TX(entry);
3645
3646 /* Now loop through additional data fragments, and queue them. */
3647 if (skb_shinfo(skb)->nr_frags > 0) {
3648 unsigned int i, last;
3649
3650 last = skb_shinfo(skb)->nr_frags - 1;
3651 for (i = 0; i <= last; i++) {
3652 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3653
3654 len = frag->size;
3655 mapping = pci_map_page(tp->pdev,
3656 frag->page,
3657 frag->page_offset,
3658 len, PCI_DMA_TODEVICE);
3659
3660 tp->tx_buffers[entry].skb = NULL;
3661 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3662
3663 if (tg3_4g_overflow_test(mapping, len)) {
3664 /* Only one should match. */
3665 if (would_hit_hwbug)
3666 BUG();
3667 would_hit_hwbug = entry + 1;
3668 }
3669
3670 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3671 tg3_set_txd(tp, entry, mapping, len,
3672 base_flags, (i == last)|(mss << 1));
3673 else
3674 tg3_set_txd(tp, entry, mapping, len,
3675 base_flags, (i == last));
3676
3677 entry = NEXT_TX(entry);
3678 }
3679 }
3680
3681 if (would_hit_hwbug) {
3682 u32 last_plus_one = entry;
3683 u32 start;
3684 unsigned int len = 0;
3685
3686 would_hit_hwbug -= 1;
3687 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3688 entry &= (TG3_TX_RING_SIZE - 1);
3689 start = entry;
3690 i = 0;
3691 while (entry != last_plus_one) {
3692 if (i == 0)
3693 len = skb_headlen(skb);
3694 else
3695 len = skb_shinfo(skb)->frags[i-1].size;
3696
3697 if (entry == would_hit_hwbug)
3698 break;
3699
3700 i++;
3701 entry = NEXT_TX(entry);
3702
3703 }
3704
3705 /* If the workaround fails due to memory/mapping
3706 * failure, silently drop this packet.
3707 */
3708 if (tigon3_4gb_hwbug_workaround(tp, skb,
3709 entry, len,
3710 last_plus_one,
3711 &start, mss))
3712 goto out_unlock;
3713
3714 entry = start;
3715 }
3716
3717 /* Packets are ready, update Tx producer idx local and on card. */
3718 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3719
3720 tp->tx_prod = entry;
3721 if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3722 netif_stop_queue(dev);
3723
3724out_unlock:
3725 mmiowb();
f47c11ee 3726 spin_unlock(&tp->tx_lock);
1da177e4
LT		 3727
3728 dev->trans_start = jiffies;
3729
3730 return NETDEV_TX_OK;
3731}
3732
3733static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3734 int new_mtu)
3735{
3736 dev->mtu = new_mtu;
3737
ef7f5ec0
MC		 3738 if (new_mtu > ETH_DATA_LEN) {
3739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
3740 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3741 ethtool_op_set_tso(dev, 0);
3742 }
3743 else
3744 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3745 } else {
3746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
3747 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
0f893dc6 3748 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
ef7f5ec0 3749 }
1da177e4
LT		 3750}
3751
3752static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3753{
3754 struct tg3 *tp = netdev_priv(dev);
3755
3756 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3757 return -EINVAL;
3758
3759 if (!netif_running(dev)) {
3760 /* We'll just catch it later when the
3761 * device is up'd.
3762 */
3763 tg3_set_mtu(dev, tp, new_mtu);
3764 return 0;
3765 }
3766
3767 tg3_netif_stop(tp);
f47c11ee
DM		 3768
3769 tg3_full_lock(tp, 1);
1da177e4 3770
944d980e 3771 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 3772
3773 tg3_set_mtu(dev, tp, new_mtu);
3774
3775 tg3_init_hw(tp);
3776
3777 tg3_netif_start(tp);
3778
f47c11ee 3779 tg3_full_unlock(tp);
1da177e4
LT		 3780
3781 return 0;
3782}
3783
3784/* Free up pending packets in all rx/tx rings.
3785 *
3786 * The chip has been shut down and the driver detached from
3787 * the networking, so no interrupts or new tx packets will
3788 * end up in the driver. tp->{tx,}lock is not held and we are not
3789 * in an interrupt context and thus may sleep.
3790 */
3791static void tg3_free_rings(struct tg3 *tp)
3792{
3793 struct ring_info *rxp;
3794 int i;
3795
3796 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3797 rxp = &tp->rx_std_buffers[i];
3798
3799 if (rxp->skb == NULL)
3800 continue;
3801 pci_unmap_single(tp->pdev,
3802 pci_unmap_addr(rxp, mapping),
7e72aad4 3803 tp->rx_pkt_buf_sz - tp->rx_offset,
1da177e4
LT		 3804 PCI_DMA_FROMDEVICE);
3805 dev_kfree_skb_any(rxp->skb);
3806 rxp->skb = NULL;
3807 }
3808
3809 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3810 rxp = &tp->rx_jumbo_buffers[i];
3811
3812 if (rxp->skb == NULL)
3813 continue;
3814 pci_unmap_single(tp->pdev,
3815 pci_unmap_addr(rxp, mapping),
3816 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3817 PCI_DMA_FROMDEVICE);
3818 dev_kfree_skb_any(rxp->skb);
3819 rxp->skb = NULL;
3820 }
3821
3822 for (i = 0; i < TG3_TX_RING_SIZE; ) {
3823 struct tx_ring_info *txp;
3824 struct sk_buff *skb;
3825 int j;
3826
3827 txp = &tp->tx_buffers[i];
3828 skb = txp->skb;
3829
3830 if (skb == NULL) {
3831 i++;
3832 continue;
3833 }
3834
3835 pci_unmap_single(tp->pdev,
3836 pci_unmap_addr(txp, mapping),
3837 skb_headlen(skb),
3838 PCI_DMA_TODEVICE);
3839 txp->skb = NULL;
3840
3841 i++;
3842
3843 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3844 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3845 pci_unmap_page(tp->pdev,
3846 pci_unmap_addr(txp, mapping),
3847 skb_shinfo(skb)->frags[j].size,
3848 PCI_DMA_TODEVICE);
3849 i++;
3850 }
3851
3852 dev_kfree_skb_any(skb);
3853 }
3854}
3855
3856/* Initialize tx/rx rings for packet processing.
3857 *
3858 * The chip has been shut down and the driver detached from
3859 * the networking, so no interrupts or new tx packets will
3860 * end up in the driver. tp->{tx,}lock are held and thus
3861 * we may not sleep.
3862 */
3863static void tg3_init_rings(struct tg3 *tp)
3864{
3865 u32 i;
3866
3867 /* Free up all the SKBs. */
3868 tg3_free_rings(tp);
3869
3870 /* Zero out all descriptors. */
3871 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3872 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3873 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3874 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3875
7e72aad4
MC		 3876 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3877 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) &&
3878 (tp->dev->mtu > ETH_DATA_LEN))
3879 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3880
1da177e4
LT		 3881 /* Initialize invariants of the rings, we only set this
3882 * stuff once. This works because the card does not
3883 * write into the rx buffer posting rings.
3884 */
3885 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3886 struct tg3_rx_buffer_desc *rxd;
3887
3888 rxd = &tp->rx_std[i];
7e72aad4 3889 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
1da177e4
LT		 3890 << RXD_LEN_SHIFT;
3891 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3892 rxd->opaque = (RXD_OPAQUE_RING_STD |
3893 (i << RXD_OPAQUE_INDEX_SHIFT));
3894 }
3895
0f893dc6 3896 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3897 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3898 struct tg3_rx_buffer_desc *rxd;
3899
3900 rxd = &tp->rx_jumbo[i];
3901 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3902 << RXD_LEN_SHIFT;
3903 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3904 RXD_FLAG_JUMBO;
3905 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3906 (i << RXD_OPAQUE_INDEX_SHIFT));
3907 }
3908 }
3909
3910 /* Now allocate fresh SKBs for each rx ring. */
3911 for (i = 0; i < tp->rx_pending; i++) {
3912 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3913 -1, i) < 0)
3914 break;
3915 }
3916
0f893dc6 3917 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 3918 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3919 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3920 -1, i) < 0)
3921 break;
3922 }
3923 }
3924}
3925
3926/*
3927 * Must not be invoked with interrupt sources disabled and
3928 * the hardware shutdown down.
3929 */
3930static void tg3_free_consistent(struct tg3 *tp)
3931{
3932 if (tp->rx_std_buffers) {
3933 kfree(tp->rx_std_buffers);
3934 tp->rx_std_buffers = NULL;
3935 }
3936 if (tp->rx_std) {
3937 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3938 tp->rx_std, tp->rx_std_mapping);
3939 tp->rx_std = NULL;
3940 }
3941 if (tp->rx_jumbo) {
3942 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3943 tp->rx_jumbo, tp->rx_jumbo_mapping);
3944 tp->rx_jumbo = NULL;
3945 }
3946 if (tp->rx_rcb) {
3947 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3948 tp->rx_rcb, tp->rx_rcb_mapping);
3949 tp->rx_rcb = NULL;
3950 }
3951 if (tp->tx_ring) {
3952 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3953 tp->tx_ring, tp->tx_desc_mapping);
3954 tp->tx_ring = NULL;
3955 }
3956 if (tp->hw_status) {
3957 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3958 tp->hw_status, tp->status_mapping);
3959 tp->hw_status = NULL;
3960 }
3961 if (tp->hw_stats) {
3962 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3963 tp->hw_stats, tp->stats_mapping);
3964 tp->hw_stats = NULL;
3965 }
3966}
3967
3968/*
3969 * Must not be invoked with interrupt sources disabled and
3970 * the hardware shutdown down. Can sleep.
3971 */
3972static int tg3_alloc_consistent(struct tg3 *tp)
3973{
3974 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3975 (TG3_RX_RING_SIZE +
3976 TG3_RX_JUMBO_RING_SIZE)) +
3977 (sizeof(struct tx_ring_info) *
3978 TG3_TX_RING_SIZE),
3979 GFP_KERNEL);
3980 if (!tp->rx_std_buffers)
3981 return -ENOMEM;
3982
3983 memset(tp->rx_std_buffers, 0,
3984 (sizeof(struct ring_info) *
3985 (TG3_RX_RING_SIZE +
3986 TG3_RX_JUMBO_RING_SIZE)) +
3987 (sizeof(struct tx_ring_info) *
3988 TG3_TX_RING_SIZE));
3989
3990 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3991 tp->tx_buffers = (struct tx_ring_info *)
3992 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3993
3994 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3995 &tp->rx_std_mapping);
3996 if (!tp->rx_std)
3997 goto err_out;
3998
3999 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4000 &tp->rx_jumbo_mapping);
4001
4002 if (!tp->rx_jumbo)
4003 goto err_out;
4004
4005 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4006 &tp->rx_rcb_mapping);
4007 if (!tp->rx_rcb)
4008 goto err_out;
4009
4010 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4011 &tp->tx_desc_mapping);
4012 if (!tp->tx_ring)
4013 goto err_out;
4014
4015 tp->hw_status = pci_alloc_consistent(tp->pdev,
4016 TG3_HW_STATUS_SIZE,
4017 &tp->status_mapping);
4018 if (!tp->hw_status)
4019 goto err_out;
4020
4021 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4022 sizeof(struct tg3_hw_stats),
4023 &tp->stats_mapping);
4024 if (!tp->hw_stats)
4025 goto err_out;
4026
4027 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4028 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4029
4030 return 0;
4031
4032err_out:
4033 tg3_free_consistent(tp);
4034 return -ENOMEM;
4035}
4036
4037#define MAX_WAIT_CNT 1000
4038
4039/* To stop a block, clear the enable bit and poll till it
4040 * clears. tp->lock is held.
4041 */
b3b7d6be 4042static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
1da177e4
LT		 4043{
4044 unsigned int i;
4045 u32 val;
4046
4047 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4048 switch (ofs) {
4049 case RCVLSC_MODE:
4050 case DMAC_MODE:
4051 case MBFREE_MODE:
4052 case BUFMGR_MODE:
4053 case MEMARB_MODE:
4054 /* We can't enable/disable these bits of the
4055 * 5705/5750, just say success.
4056 */
4057 return 0;
4058
4059 default:
4060 break;
4061 };
4062 }
4063
4064 val = tr32(ofs);
4065 val &= ~enable_bit;
4066 tw32_f(ofs, val);
4067
4068 for (i = 0; i < MAX_WAIT_CNT; i++) {
4069 udelay(100);
4070 val = tr32(ofs);
4071 if ((val & enable_bit) == 0)
4072 break;
4073 }
4074
b3b7d6be 4075 if (i == MAX_WAIT_CNT && !silent) {
1da177e4
LT		 4076 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4077 "ofs=%lx enable_bit=%x\n",
4078 ofs, enable_bit);
4079 return -ENODEV;
4080 }
4081
4082 return 0;
4083}
4084
4085/* tp->lock is held. */
b3b7d6be 4086static int tg3_abort_hw(struct tg3 *tp, int silent)
1da177e4
LT		 4087{
4088 int i, err;
4089
4090 tg3_disable_ints(tp);
4091
4092 tp->rx_mode &= ~RX_MODE_ENABLE;
4093 tw32_f(MAC_RX_MODE, tp->rx_mode);
4094 udelay(10);
4095
b3b7d6be
DM		 4096 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4097 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4098 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4099 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4100 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4101 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4102
4103 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4104 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4105 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4106 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4107 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4108 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4109 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
1da177e4
LT		 4110
4111 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4112 tw32_f(MAC_MODE, tp->mac_mode);
4113 udelay(40);
4114
4115 tp->tx_mode &= ~TX_MODE_ENABLE;
4116 tw32_f(MAC_TX_MODE, tp->tx_mode);
4117
4118 for (i = 0; i < MAX_WAIT_CNT; i++) {
4119 udelay(100);
4120 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4121 break;
4122 }
4123 if (i >= MAX_WAIT_CNT) {
4124 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4125 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4126 tp->dev->name, tr32(MAC_TX_MODE));
e6de8ad1 4127 err |= -ENODEV;
1da177e4
LT		 4128 }
4129
e6de8ad1 4130 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
b3b7d6be
DM		 4131 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4132 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
1da177e4
LT		 4133
4134 tw32(FTQ_RESET, 0xffffffff);
4135 tw32(FTQ_RESET, 0x00000000);
4136
b3b7d6be
DM		 4137 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4138 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
1da177e4
LT		 4139
4140 if (tp->hw_status)
4141 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4142 if (tp->hw_stats)
4143 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4144
1da177e4
LT		 4145 return err;
4146}
4147
4148/* tp->lock is held. */
4149static int tg3_nvram_lock(struct tg3 *tp)
4150{
4151 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4152 int i;
4153
4154 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4155 for (i = 0; i < 8000; i++) {
4156 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4157 break;
4158 udelay(20);
4159 }
4160 if (i == 8000)
4161 return -ENODEV;
4162 }
4163 return 0;
4164}
4165
4166/* tp->lock is held. */
4167static void tg3_nvram_unlock(struct tg3 *tp)
4168{
4169 if (tp->tg3_flags & TG3_FLAG_NVRAM)
4170 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4171}
4172
e6af301b
MC		 4173/* tp->lock is held. */
4174static void tg3_enable_nvram_access(struct tg3 *tp)
4175{
4176 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4177 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4178 u32 nvaccess = tr32(NVRAM_ACCESS);
4179
4180 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4181 }
4182}
4183
4184/* tp->lock is held. */
4185static void tg3_disable_nvram_access(struct tg3 *tp)
4186{
4187 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4188 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4189 u32 nvaccess = tr32(NVRAM_ACCESS);
4190
4191 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4192 }
4193}
4194
1da177e4
LT		 4195/* tp->lock is held. */
4196static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4197{
4198 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4199 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4200 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4201
4202 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4203 switch (kind) {
4204 case RESET_KIND_INIT:
4205 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4206 DRV_STATE_START);
4207 break;
4208
4209 case RESET_KIND_SHUTDOWN:
4210 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4211 DRV_STATE_UNLOAD);
4212 break;
4213
4214 case RESET_KIND_SUSPEND:
4215 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4216 DRV_STATE_SUSPEND);
4217 break;
4218
4219 default:
4220 break;
4221 };
4222 }
4223}
4224
4225/* tp->lock is held. */
4226static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4227{
4228 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4229 switch (kind) {
4230 case RESET_KIND_INIT:
4231 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4232 DRV_STATE_START_DONE);
4233 break;
4234
4235 case RESET_KIND_SHUTDOWN:
4236 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4237 DRV_STATE_UNLOAD_DONE);
4238 break;
4239
4240 default:
4241 break;
4242 };
4243 }
4244}
4245
4246/* tp->lock is held. */
4247static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4248{
4249 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4250 switch (kind) {
4251 case RESET_KIND_INIT:
4252 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4253 DRV_STATE_START);
4254 break;
4255
4256 case RESET_KIND_SHUTDOWN:
4257 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4258 DRV_STATE_UNLOAD);
4259 break;
4260
4261 case RESET_KIND_SUSPEND:
4262 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4263 DRV_STATE_SUSPEND);
4264 break;
4265
4266 default:
4267 break;
4268 };
4269 }
4270}
4271
4272static void tg3_stop_fw(struct tg3 *);
4273
4274/* tp->lock is held. */
4275static int tg3_chip_reset(struct tg3 *tp)
4276{
4277 u32 val;
1ee582d8 4278 void (*write_op)(struct tg3 *, u32, u32);
1da177e4
LT		 4279 int i;
4280
4281 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4282 tg3_nvram_lock(tp);
4283
4284 /*
4285 * We must avoid the readl() that normally takes place.
4286 * It locks machines, causes machine checks, and other
4287 * fun things. So, temporarily disable the 5701
4288 * hardware workaround, while we do the reset.
4289 */
1ee582d8
MC		 4290 write_op = tp->write32;
4291 if (write_op == tg3_write_flush_reg32)
4292 tp->write32 = tg3_write32;
1da177e4
LT		 4293
4294 /* do the reset */
4295 val = GRC_MISC_CFG_CORECLK_RESET;
4296
4297 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4298 if (tr32(0x7e2c) == 0x60) {
4299 tw32(0x7e2c, 0x20);
4300 }
4301 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4302 tw32(GRC_MISC_CFG, (1 << 29));
4303 val |= (1 << 29);
4304 }
4305 }
4306
4307 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4308 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4309 tw32(GRC_MISC_CFG, val);
4310
1ee582d8
MC		 4311 /* restore 5701 hardware bug workaround write method */
4312 tp->write32 = write_op;
1da177e4
LT		 4313
4314 /* Unfortunately, we have to delay before the PCI read back.
4315 * Some 575X chips even will not respond to a PCI cfg access
4316 * when the reset command is given to the chip.
4317 *
4318 * How do these hardware designers expect things to work
4319 * properly if the PCI write is posted for a long period
4320 * of time? It is always necessary to have some method by
4321 * which a register read back can occur to push the write
4322 * out which does the reset.
4323 *
4324 * For most tg3 variants the trick below was working.
4325 * Ho hum...
4326 */
4327 udelay(120);
4328
4329 /* Flush PCI posted writes. The normal MMIO registers
4330 * are inaccessible at this time so this is the only
4331 * way to make this reliably (actually, this is no longer
4332 * the case, see above). I tried to use indirect
4333 * register read/write but this upset some 5701 variants.
4334 */
4335 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4336
4337 udelay(120);
4338
4339 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4340 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4341 int i;
4342 u32 cfg_val;
4343
4344 /* Wait for link training to complete. */
4345 for (i = 0; i < 5000; i++)
4346 udelay(100);
4347
4348 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4349 pci_write_config_dword(tp->pdev, 0xc4,
4350 cfg_val | (1 << 15));
4351 }
4352 /* Set PCIE max payload size and clear error status. */
4353 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4354 }
4355
4356 /* Re-enable indirect register accesses. */
4357 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4358 tp->misc_host_ctrl);
4359
4360 /* Set MAX PCI retry to zero. */
4361 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4362 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4363 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4364 val |= PCISTATE_RETRY_SAME_DMA;
4365 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4366
4367 pci_restore_state(tp->pdev);
4368
4369 /* Make sure PCI-X relaxed ordering bit is clear. */
4370 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4371 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4372 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4373
4cf78e4f
MC		 4374 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4375 u32 val;
4376
4377 /* Chip reset on 5780 will reset MSI enable bit,
4378 * so need to restore it.
4379 */
4380 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4381 u16 ctrl;
4382
4383 pci_read_config_word(tp->pdev,
4384 tp->msi_cap + PCI_MSI_FLAGS,
4385 &ctrl);
4386 pci_write_config_word(tp->pdev,
4387 tp->msi_cap + PCI_MSI_FLAGS,
4388 ctrl | PCI_MSI_FLAGS_ENABLE);
4389 val = tr32(MSGINT_MODE);
4390 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4391 }
4392
4393 val = tr32(MEMARB_MODE);
4394 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4395
4396 } else
4397 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1da177e4
LT		 4398
4399 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4400 tg3_stop_fw(tp);
4401 tw32(0x5000, 0x400);
4402 }
4403
4404 tw32(GRC_MODE, tp->grc_mode);
4405
4406 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4407 u32 val = tr32(0xc4);
4408
4409 tw32(0xc4, val | (1 << 15));
4410 }
4411
4412 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4413 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4414 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4415 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4416 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4417 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4418 }
4419
4420 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4421 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4422 tw32_f(MAC_MODE, tp->mac_mode);
747e8f8b
MC		 4423 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4424 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4425 tw32_f(MAC_MODE, tp->mac_mode);
1da177e4
LT		 4426 } else
4427 tw32_f(MAC_MODE, 0);
4428 udelay(40);
4429
4430 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4431 /* Wait for firmware initialization to complete. */
4432 for (i = 0; i < 100000; i++) {
4433 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4434 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4435 break;
4436 udelay(10);
4437 }
4438 if (i >= 100000) {
4439 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4440 "firmware will not restart magic=%08x\n",
4441 tp->dev->name, val);
4442 return -ENODEV;
4443 }
4444 }
4445
4446 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4447 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4448 u32 val = tr32(0x7c00);
4449
4450 tw32(0x7c00, val | (1 << 25));
4451 }
4452
4453 /* Reprobe ASF enable state. */
4454 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4455 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4456 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4457 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4458 u32 nic_cfg;
4459
4460 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4461 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4462 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 4463 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 4464 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4465 }
4466 }
4467
4468 return 0;
4469}
4470
4471/* tp->lock is held. */
4472static void tg3_stop_fw(struct tg3 *tp)
4473{
4474 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4475 u32 val;
4476 int i;
4477
4478 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4479 val = tr32(GRC_RX_CPU_EVENT);
4480 val |= (1 << 14);
4481 tw32(GRC_RX_CPU_EVENT, val);
4482
4483 /* Wait for RX cpu to ACK the event. */
4484 for (i = 0; i < 100; i++) {
4485 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4486 break;
4487 udelay(1);
4488 }
4489 }
4490}
4491
4492/* tp->lock is held. */
944d980e 4493static int tg3_halt(struct tg3 *tp, int kind, int silent)
1da177e4
LT		 4494{
4495 int err;
4496
4497 tg3_stop_fw(tp);
4498
944d980e 4499 tg3_write_sig_pre_reset(tp, kind);
1da177e4 4500
b3b7d6be 4501 tg3_abort_hw(tp, silent);
1da177e4
LT		 4502 err = tg3_chip_reset(tp);
4503
944d980e
MC		 4504 tg3_write_sig_legacy(tp, kind);
4505 tg3_write_sig_post_reset(tp, kind);
1da177e4
LT		 4506
4507 if (err)
4508 return err;
4509
4510 return 0;
4511}
4512
4513#define TG3_FW_RELEASE_MAJOR 0x0
4514#define TG3_FW_RELASE_MINOR 0x0
4515#define TG3_FW_RELEASE_FIX 0x0
4516#define TG3_FW_START_ADDR 0x08000000
4517#define TG3_FW_TEXT_ADDR 0x08000000
4518#define TG3_FW_TEXT_LEN 0x9c0
4519#define TG3_FW_RODATA_ADDR 0x080009c0
4520#define TG3_FW_RODATA_LEN 0x60
4521#define TG3_FW_DATA_ADDR 0x08000a40
4522#define TG3_FW_DATA_LEN 0x20
4523#define TG3_FW_SBSS_ADDR 0x08000a60
4524#define TG3_FW_SBSS_LEN 0xc
4525#define TG3_FW_BSS_ADDR 0x08000a70
4526#define TG3_FW_BSS_LEN 0x10
4527
4528static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4529 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4530 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4531 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4532 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4533 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4534 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4535 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4536 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4537 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4538 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4539 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4540 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4541 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4542 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4543 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4544 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4545 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4546 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4547 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4548 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4549 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4550 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4551 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4554 0, 0, 0, 0, 0, 0,
4555 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4556 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4557 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4558 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4559 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4560 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4561 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4562 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4563 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4564 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4565 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4569 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4570 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4571 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4572 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4573 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4574 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4575 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4576 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4577 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4578 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4579 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4580 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4581 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4582 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4583 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4584 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4585 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4586 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4587 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4588 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4589 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4590 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4591 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4592 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4593 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4594 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4595 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4596 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4597 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4598 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4599 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4600 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4601 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4602 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4603 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4604 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4605 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4606 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4607 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4608 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4609 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4610 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4611 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4612 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4613 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4614 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4615 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4616 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4617 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4618 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4619 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4620};
4621
4622static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4623 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4624 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4625 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4626 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4627 0x00000000
4628};
4629
4630#if 0 /* All zeros, don't eat up space with it. */
4631u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4632 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4633 0x00000000, 0x00000000, 0x00000000, 0x00000000
4634};
4635#endif
4636
4637#define RX_CPU_SCRATCH_BASE 0x30000
4638#define RX_CPU_SCRATCH_SIZE 0x04000
4639#define TX_CPU_SCRATCH_BASE 0x34000
4640#define TX_CPU_SCRATCH_SIZE 0x04000
4641
4642/* tp->lock is held. */
4643static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4644{
4645 int i;
4646
4647 if (offset == TX_CPU_BASE &&
4648 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4649 BUG();
4650
4651 if (offset == RX_CPU_BASE) {
4652 for (i = 0; i < 10000; i++) {
4653 tw32(offset + CPU_STATE, 0xffffffff);
4654 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4655 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4656 break;
4657 }
4658
4659 tw32(offset + CPU_STATE, 0xffffffff);
4660 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
4661 udelay(10);
4662 } else {
4663 for (i = 0; i < 10000; i++) {
4664 tw32(offset + CPU_STATE, 0xffffffff);
4665 tw32(offset + CPU_MODE, CPU_MODE_HALT);
4666 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4667 break;
4668 }
4669 }
4670
4671 if (i >= 10000) {
4672 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4673 "and %s CPU\n",
4674 tp->dev->name,
4675 (offset == RX_CPU_BASE ? "RX" : "TX"));
4676 return -ENODEV;
4677 }
4678 return 0;
4679}
4680
4681struct fw_info {
4682 unsigned int text_base;
4683 unsigned int text_len;
4684 u32 *text_data;
4685 unsigned int rodata_base;
4686 unsigned int rodata_len;
4687 u32 *rodata_data;
4688 unsigned int data_base;
4689 unsigned int data_len;
4690 u32 *data_data;
4691};
4692
4693/* tp->lock is held. */
4694static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4695 int cpu_scratch_size, struct fw_info *info)
4696{
4697 int err, i;
1da177e4
LT		 4698 void (*write_op)(struct tg3 *, u32, u32);
4699
4700 if (cpu_base == TX_CPU_BASE &&
4701 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4702 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4703 "TX cpu firmware on %s which is 5705.\n",
4704 tp->dev->name);
4705 return -EINVAL;
4706 }
4707
4708 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4709 write_op = tg3_write_mem;
4710 else
4711 write_op = tg3_write_indirect_reg32;
4712
1b628151
MC		 4713 /* It is possible that bootcode is still loading at this point.
4714 * Get the nvram lock first before halting the cpu.
4715 */
4716 tg3_nvram_lock(tp);
1da177e4 4717 err = tg3_halt_cpu(tp, cpu_base);
1b628151 4718 tg3_nvram_unlock(tp);
1da177e4
LT		 4719 if (err)
4720 goto out;
4721
4722 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4723 write_op(tp, cpu_scratch_base + i, 0);
4724 tw32(cpu_base + CPU_STATE, 0xffffffff);
4725 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4726 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4727 write_op(tp, (cpu_scratch_base +
4728 (info->text_base & 0xffff) +
4729 (i * sizeof(u32))),
4730 (info->text_data ?
4731 info->text_data[i] : 0));
4732 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4733 write_op(tp, (cpu_scratch_base +
4734 (info->rodata_base & 0xffff) +
4735 (i * sizeof(u32))),
4736 (info->rodata_data ?
4737 info->rodata_data[i] : 0));
4738 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4739 write_op(tp, (cpu_scratch_base +
4740 (info->data_base & 0xffff) +
4741 (i * sizeof(u32))),
4742 (info->data_data ?
4743 info->data_data[i] : 0));
4744
4745 err = 0;
4746
4747out:
1da177e4
LT		 4748 return err;
4749}
4750
4751/* tp->lock is held. */
4752static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4753{
4754 struct fw_info info;
4755 int err, i;
4756
4757 info.text_base = TG3_FW_TEXT_ADDR;
4758 info.text_len = TG3_FW_TEXT_LEN;
4759 info.text_data = &tg3FwText[0];
4760 info.rodata_base = TG3_FW_RODATA_ADDR;
4761 info.rodata_len = TG3_FW_RODATA_LEN;
4762 info.rodata_data = &tg3FwRodata[0];
4763 info.data_base = TG3_FW_DATA_ADDR;
4764 info.data_len = TG3_FW_DATA_LEN;
4765 info.data_data = NULL;
4766
4767 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4768 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4769 &info);
4770 if (err)
4771 return err;
4772
4773 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4774 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4775 &info);
4776 if (err)
4777 return err;
4778
4779 /* Now startup only the RX cpu. */
4780 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4781 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4782
4783 for (i = 0; i < 5; i++) {
4784 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4785 break;
4786 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4787 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
4788 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
4789 udelay(1000);
4790 }
4791 if (i >= 5) {
4792 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4793 "to set RX CPU PC, is %08x should be %08x\n",
4794 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4795 TG3_FW_TEXT_ADDR);
4796 return -ENODEV;
4797 }
4798 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4799 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
4800
4801 return 0;
4802}
4803
4804#if TG3_TSO_SUPPORT != 0
4805
4806#define TG3_TSO_FW_RELEASE_MAJOR 0x1
4807#define TG3_TSO_FW_RELASE_MINOR 0x6
4808#define TG3_TSO_FW_RELEASE_FIX 0x0
4809#define TG3_TSO_FW_START_ADDR 0x08000000
4810#define TG3_TSO_FW_TEXT_ADDR 0x08000000
4811#define TG3_TSO_FW_TEXT_LEN 0x1aa0
4812#define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
4813#define TG3_TSO_FW_RODATA_LEN 0x60
4814#define TG3_TSO_FW_DATA_ADDR 0x08001b20
4815#define TG3_TSO_FW_DATA_LEN 0x30
4816#define TG3_TSO_FW_SBSS_ADDR 0x08001b50
4817#define TG3_TSO_FW_SBSS_LEN 0x2c
4818#define TG3_TSO_FW_BSS_ADDR 0x08001b80
4819#define TG3_TSO_FW_BSS_LEN 0x894
4820
4821static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4822 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4823 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4824 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4825 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4826 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4827 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4828 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4829 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4830 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4831 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4832 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4833 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4834 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4835 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4836 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4837 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4838 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4839 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4840 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4841 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4842 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4843 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4844 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4845 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4846 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4847 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4848 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4849 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4850 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4851 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4852 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4853 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4854 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4855 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4856 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4857 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4858 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4859 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4860 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4861 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4862 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4863 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4864 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4865 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4866 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4867 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4868 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4869 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4870 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4871 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4872 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4873 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4874 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4875 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4876 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4877 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4878 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4879 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4880 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4881 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4882 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4883 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4884 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4885 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4886 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4887 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4888 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4889 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4890 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4891 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4892 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4893 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4894 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4895 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4896 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4897 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4898 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4899 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4900 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4901 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4902 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4903 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4904 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4905 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4906 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4907 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4908 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4909 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4910 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4911 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4912 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4913 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4914 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4915 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4916 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4917 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4918 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4919 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4920 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4921 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4922 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4923 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4924 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4925 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4926 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4927 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4928 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4929 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4930 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4931 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4932 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4933 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4934 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4935 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4936 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4937 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4938 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4939 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4940 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4941 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4942 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4943 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4944 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4945 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4946 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4947 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4948 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4949 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4950 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4951 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4952 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4953 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4954 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4955 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4956 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4957 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4958 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4959 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4960 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4961 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4962 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4963 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4964 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4965 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4966 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4967 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4968 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4969 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4970 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4971 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4972 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4973 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4974 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4975 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4976 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4977 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4978 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4979 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4980 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4981 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4982 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4983 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4984 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4985 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4986 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4987 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4988 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4989 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4990 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4991 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4992 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4993 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4994 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4995 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4996 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4997 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4998 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4999 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5000 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5001 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5002 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5003 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5004 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5005 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5006 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5007 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5008 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5009 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5010 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5011 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5012 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5013 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5014 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5015 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5016 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5017 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5018 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5019 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5020 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5021 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5022 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5023 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5024 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5025 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5026 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5027 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5028 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5029 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5030 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5031 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5032 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5033 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5034 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5035 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5036 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5037 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5038 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5039 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5040 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5041 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5042 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5043 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5044 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5045 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5046 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5047 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5048 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5049 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5050 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5051 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5052 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5053 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5054 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5055 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5056 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5057 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5058 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5059 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5060 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5061 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5062 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5063 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5064 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5065 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5066 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5067 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5068 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5069 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5070 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5071 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5072 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5073 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5074 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5075 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5076 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5077 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5078 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5079 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5080 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5081 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5082 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5083 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5084 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5085 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5086 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5087 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5088 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5089 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5090 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5091 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5092 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5093 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5094 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5095 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5096 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5097 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5098 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5099 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5100 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5101 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5102 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5103 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5104 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5105 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5106};
5107
5108static u32 tg3TsoFwRodata[] = {
5109 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5110 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5111 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5112 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5113 0x00000000,
5114};
5115
5116static u32 tg3TsoFwData[] = {
5117 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5118 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5119 0x00000000,
5120};
5121
5122/* 5705 needs a special version of the TSO firmware. */
5123#define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5124#define TG3_TSO5_FW_RELASE_MINOR 0x2
5125#define TG3_TSO5_FW_RELEASE_FIX 0x0
5126#define TG3_TSO5_FW_START_ADDR 0x00010000
5127#define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5128#define TG3_TSO5_FW_TEXT_LEN 0xe90
5129#define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5130#define TG3_TSO5_FW_RODATA_LEN 0x50
5131#define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5132#define TG3_TSO5_FW_DATA_LEN 0x20
5133#define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5134#define TG3_TSO5_FW_SBSS_LEN 0x28
5135#define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5136#define TG3_TSO5_FW_BSS_LEN 0x88
5137
5138static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5139 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5140 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5141 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5142 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5143 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5144 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5145 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5146 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5147 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5148 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5149 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5150 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5151 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5152 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5153 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5154 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5155 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5156 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5157 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5158 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5159 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5160 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5161 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5162 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5163 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5164 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5165 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5166 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5167 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5168 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5169 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5170 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5171 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5172 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5173 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5174 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5175 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5176 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5177 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5178 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5179 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5180 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5181 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5182 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5183 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5184 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5185 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5186 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5187 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5188 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5189 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5190 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5191 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5192 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5193 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5194 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5195 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5196 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5197 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5198 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5199 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5200 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5201 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5202 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5203 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5204 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5205 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5206 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5207 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5208 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5209 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5210 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5211 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5212 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5213 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5214 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5215 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5216 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5217 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5218 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5219 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5220 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5221 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5222 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5223 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5224 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5225 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5226 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5227 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5228 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5229 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5230 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5231 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5232 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5233 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5234 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5235 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5236 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5237 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5238 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5239 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5240 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5241 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5242 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5243 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5244 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5245 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5246 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5247 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5248 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5249 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5250 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5251 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5252 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5253 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5254 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5255 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5256 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5257 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5258 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5259 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5260 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5261 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5262 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5263 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5264 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5265 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5266 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5267 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5268 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5269 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5270 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5271 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5272 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5273 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5274 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5275 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5276 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5277 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5278 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5279 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5280 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5281 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5282 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5283 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5284 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5285 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5286 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5287 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5288 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5289 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5290 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5291 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5292 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5293 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5294 0x00000000, 0x00000000, 0x00000000,
5295};
5296
5297static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5298 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5299 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5300 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5301 0x00000000, 0x00000000, 0x00000000,
5302};
5303
5304static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5305 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5306 0x00000000, 0x00000000, 0x00000000,
5307};
5308
5309/* tp->lock is held. */
5310static int tg3_load_tso_firmware(struct tg3 *tp)
5311{
5312 struct fw_info info;
5313 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5314 int err, i;
5315
5316 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5317 return 0;
5318
5319 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5320 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5321 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5322 info.text_data = &tg3Tso5FwText[0];
5323 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5324 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5325 info.rodata_data = &tg3Tso5FwRodata[0];
5326 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5327 info.data_len = TG3_TSO5_FW_DATA_LEN;
5328 info.data_data = &tg3Tso5FwData[0];
5329 cpu_base = RX_CPU_BASE;
5330 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5331 cpu_scratch_size = (info.text_len +
5332 info.rodata_len +
5333 info.data_len +
5334 TG3_TSO5_FW_SBSS_LEN +
5335 TG3_TSO5_FW_BSS_LEN);
5336 } else {
5337 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5338 info.text_len = TG3_TSO_FW_TEXT_LEN;
5339 info.text_data = &tg3TsoFwText[0];
5340 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5341 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5342 info.rodata_data = &tg3TsoFwRodata[0];
5343 info.data_base = TG3_TSO_FW_DATA_ADDR;
5344 info.data_len = TG3_TSO_FW_DATA_LEN;
5345 info.data_data = &tg3TsoFwData[0];
5346 cpu_base = TX_CPU_BASE;
5347 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5348 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5349 }
5350
5351 err = tg3_load_firmware_cpu(tp, cpu_base,
5352 cpu_scratch_base, cpu_scratch_size,
5353 &info);
5354 if (err)
5355 return err;
5356
5357 /* Now startup the cpu. */
5358 tw32(cpu_base + CPU_STATE, 0xffffffff);
5359 tw32_f(cpu_base + CPU_PC, info.text_base);
5360
5361 for (i = 0; i < 5; i++) {
5362 if (tr32(cpu_base + CPU_PC) == info.text_base)
5363 break;
5364 tw32(cpu_base + CPU_STATE, 0xffffffff);
5365 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5366 tw32_f(cpu_base + CPU_PC, info.text_base);
5367 udelay(1000);
5368 }
5369 if (i >= 5) {
5370 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5371 "to set CPU PC, is %08x should be %08x\n",
5372 tp->dev->name, tr32(cpu_base + CPU_PC),
5373 info.text_base);
5374 return -ENODEV;
5375 }
5376 tw32(cpu_base + CPU_STATE, 0xffffffff);
5377 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5378 return 0;
5379}
5380
5381#endif /* TG3_TSO_SUPPORT != 0 */
5382
5383/* tp->lock is held. */
5384static void __tg3_set_mac_addr(struct tg3 *tp)
5385{
5386 u32 addr_high, addr_low;
5387 int i;
5388
5389 addr_high = ((tp->dev->dev_addr[0] << 8) |
5390 tp->dev->dev_addr[1]);
5391 addr_low = ((tp->dev->dev_addr[2] << 24) |
5392 (tp->dev->dev_addr[3] << 16) |
5393 (tp->dev->dev_addr[4] << 8) |
5394 (tp->dev->dev_addr[5] << 0));
5395 for (i = 0; i < 4; i++) {
5396 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5397 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5398 }
5399
5400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5402 for (i = 0; i < 12; i++) {
5403 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5404 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5405 }
5406 }
5407
5408 addr_high = (tp->dev->dev_addr[0] +
5409 tp->dev->dev_addr[1] +
5410 tp->dev->dev_addr[2] +
5411 tp->dev->dev_addr[3] +
5412 tp->dev->dev_addr[4] +
5413 tp->dev->dev_addr[5]) &
5414 TX_BACKOFF_SEED_MASK;
5415 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5416}
5417
5418static int tg3_set_mac_addr(struct net_device *dev, void *p)
5419{
5420 struct tg3 *tp = netdev_priv(dev);
5421 struct sockaddr *addr = p;
5422
5423 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5424
f47c11ee 5425 spin_lock_bh(&tp->lock);
1da177e4 5426 __tg3_set_mac_addr(tp);
f47c11ee 5427 spin_unlock_bh(&tp->lock);
1da177e4
LT		 5428
5429 return 0;
5430}
5431
5432/* tp->lock is held. */
5433static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5434 dma_addr_t mapping, u32 maxlen_flags,
5435 u32 nic_addr)
5436{
5437 tg3_write_mem(tp,
5438 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5439 ((u64) mapping >> 32));
5440 tg3_write_mem(tp,
5441 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5442 ((u64) mapping & 0xffffffff));
5443 tg3_write_mem(tp,
5444 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5445 maxlen_flags);
5446
5447 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5448 tg3_write_mem(tp,
5449 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5450 nic_addr);
5451}
5452
5453static void __tg3_set_rx_mode(struct net_device *);
d244c892 5454static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
15f9850d
DM		 5455{
5456 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5457 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5458 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5459 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5460 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5461 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5462 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5463 }
5464 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5465 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5466 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5467 u32 val = ec->stats_block_coalesce_usecs;
5468
5469 if (!netif_carrier_ok(tp->dev))
5470 val = 0;
5471
5472 tw32(HOSTCC_STAT_COAL_TICKS, val);
5473 }
5474}
1da177e4
LT		 5475
5476/* tp->lock is held. */
5477static int tg3_reset_hw(struct tg3 *tp)
5478{
5479 u32 val, rdmac_mode;
5480 int i, err, limit;
5481
5482 tg3_disable_ints(tp);
5483
5484 tg3_stop_fw(tp);
5485
5486 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5487
5488 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
e6de8ad1 5489 tg3_abort_hw(tp, 1);
1da177e4
LT		 5490 }
5491
5492 err = tg3_chip_reset(tp);
5493 if (err)
5494 return err;
5495
5496 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5497
5498 /* This works around an issue with Athlon chipsets on
5499 * B3 tigon3 silicon. This bit has no effect on any
5500 * other revision. But do not set this on PCI Express
5501 * chips.
5502 */
5503 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5504 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5505 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5506
5507 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5508 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5509 val = tr32(TG3PCI_PCISTATE);
5510 val |= PCISTATE_RETRY_SAME_DMA;
5511 tw32(TG3PCI_PCISTATE, val);
5512 }
5513
5514 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5515 /* Enable some hw fixes. */
5516 val = tr32(TG3PCI_MSI_DATA);
5517 val |= (1 << 26) | (1 << 28) | (1 << 29);
5518 tw32(TG3PCI_MSI_DATA, val);
5519 }
5520
5521 /* Descriptor ring init may make accesses to the
5522 * NIC SRAM area to setup the TX descriptors, so we
5523 * can only do this after the hardware has been
5524 * successfully reset.
5525 */
5526 tg3_init_rings(tp);
5527
5528 /* This value is determined during the probe time DMA
5529 * engine test, tg3_test_dma.
5530 */
5531 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5532
5533 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5534 GRC_MODE_4X_NIC_SEND_RINGS |
5535 GRC_MODE_NO_TX_PHDR_CSUM |
5536 GRC_MODE_NO_RX_PHDR_CSUM);
5537 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5538 if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5539 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5540 if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5541 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5542
5543 tw32(GRC_MODE,
5544 tp->grc_mode |
5545 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5546
5547 /* Setup the timer prescalar register. Clock is always 66Mhz. */
5548 val = tr32(GRC_MISC_CFG);
5549 val &= ~0xff;
5550 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5551 tw32(GRC_MISC_CFG, val);
5552
5553 /* Initialize MBUF/DESC pool. */
cbf46853 5554 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
1da177e4
LT		 5555 /* Do nothing. */
5556 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5557 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5559 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5560 else
5561 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5562 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5563 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5564 }
5565#if TG3_TSO_SUPPORT != 0
5566 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5567 int fw_len;
5568
5569 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5570 TG3_TSO5_FW_RODATA_LEN +
5571 TG3_TSO5_FW_DATA_LEN +
5572 TG3_TSO5_FW_SBSS_LEN +
5573 TG3_TSO5_FW_BSS_LEN);
5574 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5575 tw32(BUFMGR_MB_POOL_ADDR,
5576 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5577 tw32(BUFMGR_MB_POOL_SIZE,
5578 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5579 }
5580#endif
5581
0f893dc6 5582 if (tp->dev->mtu <= ETH_DATA_LEN) {
1da177e4
LT		 5583 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5584 tp->bufmgr_config.mbuf_read_dma_low_water);
5585 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5586 tp->bufmgr_config.mbuf_mac_rx_low_water);
5587 tw32(BUFMGR_MB_HIGH_WATER,
5588 tp->bufmgr_config.mbuf_high_water);
5589 } else {
5590 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5591 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5592 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5593 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5594 tw32(BUFMGR_MB_HIGH_WATER,
5595 tp->bufmgr_config.mbuf_high_water_jumbo);
5596 }
5597 tw32(BUFMGR_DMA_LOW_WATER,
5598 tp->bufmgr_config.dma_low_water);
5599 tw32(BUFMGR_DMA_HIGH_WATER,
5600 tp->bufmgr_config.dma_high_water);
5601
5602 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5603 for (i = 0; i < 2000; i++) {
5604 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5605 break;
5606 udelay(10);
5607 }
5608 if (i >= 2000) {
5609 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5610 tp->dev->name);
5611 return -ENODEV;
5612 }
5613
5614 /* Setup replenish threshold. */
5615 tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5616
5617 /* Initialize TG3_BDINFO's at:
5618 * RCVDBDI_STD_BD: standard eth size rx ring
5619 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
5620 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
5621 *
5622 * like so:
5623 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
5624 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
5625 * ring attribute flags
5626 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
5627 *
5628 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5629 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5630 *
5631 * The size of each ring is fixed in the firmware, but the location is
5632 * configurable.
5633 */
5634 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5635 ((u64) tp->rx_std_mapping >> 32));
5636 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5637 ((u64) tp->rx_std_mapping & 0xffffffff));
5638 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5639 NIC_SRAM_RX_BUFFER_DESC);
5640
5641 /* Don't even try to program the JUMBO/MINI buffer descriptor
5642 * configs on 5705.
5643 */
5644 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5645 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5646 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5647 } else {
5648 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5649 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5650
5651 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5652 BDINFO_FLAGS_DISABLED);
5653
5654 /* Setup replenish threshold. */
5655 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5656
0f893dc6 5657 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
1da177e4
LT		 5658 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5659 ((u64) tp->rx_jumbo_mapping >> 32));
5660 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5661 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5662 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5663 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5664 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5665 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5666 } else {
5667 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5668 BDINFO_FLAGS_DISABLED);
5669 }
5670
5671 }
5672
5673 /* There is only one send ring on 5705/5750, no need to explicitly
5674 * disable the others.
5675 */
5676 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5677 /* Clear out send RCB ring in SRAM. */
5678 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5679 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5680 BDINFO_FLAGS_DISABLED);
5681 }
5682
5683 tp->tx_prod = 0;
5684 tp->tx_cons = 0;
5685 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5686 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5687
5688 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5689 tp->tx_desc_mapping,
5690 (TG3_TX_RING_SIZE <<
5691 BDINFO_FLAGS_MAXLEN_SHIFT),
5692 NIC_SRAM_TX_BUFFER_DESC);
5693
5694 /* There is only one receive return ring on 5705/5750, no need
5695 * to explicitly disable the others.
5696 */
5697 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5698 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5699 i += TG3_BDINFO_SIZE) {
5700 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5701 BDINFO_FLAGS_DISABLED);
5702 }
5703 }
5704
5705 tp->rx_rcb_ptr = 0;
5706 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5707
5708 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5709 tp->rx_rcb_mapping,
5710 (TG3_RX_RCB_RING_SIZE(tp) <<
5711 BDINFO_FLAGS_MAXLEN_SHIFT),
5712 0);
5713
5714 tp->rx_std_ptr = tp->rx_pending;
5715 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5716 tp->rx_std_ptr);
5717
0f893dc6 5718 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
1da177e4
LT		 5719 tp->rx_jumbo_pending : 0;
5720 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5721 tp->rx_jumbo_ptr);
5722
5723 /* Initialize MAC address and backoff seed. */
5724 __tg3_set_mac_addr(tp);
5725
5726 /* MTU + ethernet header + FCS + optional VLAN tag */
5727 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5728
5729 /* The slot time is changed by tg3_setup_phy if we
5730 * run at gigabit with half duplex.
5731 */
5732 tw32(MAC_TX_LENGTHS,
5733 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5734 (6 << TX_LENGTHS_IPG_SHIFT) |
5735 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5736
5737 /* Receive rules. */
5738 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5739 tw32(RCVLPC_CONFIG, 0x0181);
5740
5741 /* Calculate RDMAC_MODE setting early, we need it to determine
5742 * the RCVLPC_STATE_ENABLE mask.
5743 */
5744 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5745 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5746 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5747 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5748 RDMAC_MODE_LNGREAD_ENAB);
5749 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5750 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
85e94ced
MC		 5751
5752 /* If statement applies to 5705 and 5750 PCI devices only */
5753 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5754 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5755 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1da177e4
LT		 5756 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5757 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5758 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5759 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5760 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5761 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5762 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5763 }
5764 }
5765
85e94ced
MC		 5766 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5767 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5768
1da177e4
LT		 5769#if TG3_TSO_SUPPORT != 0
5770 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5771 rdmac_mode |= (1 << 27);
5772#endif
5773
5774 /* Receive/send statistics. */
5775 if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5776 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5777 val = tr32(RCVLPC_STATS_ENABLE);
5778 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5779 tw32(RCVLPC_STATS_ENABLE, val);
5780 } else {
5781 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5782 }
5783 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5784 tw32(SNDDATAI_STATSENAB, 0xffffff);
5785 tw32(SNDDATAI_STATSCTRL,
5786 (SNDDATAI_SCTRL_ENABLE |
5787 SNDDATAI_SCTRL_FASTUPD));
5788
5789 /* Setup host coalescing engine. */
5790 tw32(HOSTCC_MODE, 0);
5791 for (i = 0; i < 2000; i++) {
5792 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5793 break;
5794 udelay(10);
5795 }
5796
d244c892 5797 __tg3_set_coalesce(tp, &tp->coal);
1da177e4
LT		 5798
5799 /* set status block DMA address */
5800 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5801 ((u64) tp->status_mapping >> 32));
5802 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5803 ((u64) tp->status_mapping & 0xffffffff));
5804
5805 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5806 /* Status/statistics block address. See tg3_timer,
5807 * the tg3_periodic_fetch_stats call there, and
5808 * tg3_get_stats to see how this works for 5705/5750 chips.
5809 */
1da177e4
LT		 5810 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5811 ((u64) tp->stats_mapping >> 32));
5812 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5813 ((u64) tp->stats_mapping & 0xffffffff));
5814 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5815 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5816 }
5817
5818 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5819
5820 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5821 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5822 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5823 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5824
5825 /* Clear statistics/status block in chip, and status block in ram. */
5826 for (i = NIC_SRAM_STATS_BLK;
5827 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5828 i += sizeof(u32)) {
5829 tg3_write_mem(tp, i, 0);
5830 udelay(40);
5831 }
5832 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5833
5834 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5835 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5836 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5837 udelay(40);
5838
314fba34
MC		 5839 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5840 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5841 * register to preserve the GPIO settings for LOMs. The GPIOs,
5842 * whether used as inputs or outputs, are set by boot code after
5843 * reset.
5844 */
5845 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5846 u32 gpio_mask;
5847
5848 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5849 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
3e7d83bc
MC		 5850
5851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5852 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5853 GRC_LCLCTRL_GPIO_OUTPUT3;
5854
314fba34
MC		 5855 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5856
5857 /* GPIO1 must be driven high for eeprom write protect */
1da177e4
LT		 5858 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5859 GRC_LCLCTRL_GPIO_OUTPUT1);
314fba34 5860 }
1da177e4
LT		 5861 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5862 udelay(100);
5863
09ee929c 5864 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
fac9b83e 5865 tp->last_tag = 0;
1da177e4
LT		 5866
5867 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5868 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5869 udelay(40);
5870 }
5871
5872 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5873 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5874 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5875 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5876 WDMAC_MODE_LNGREAD_ENAB);
5877
85e94ced
MC		 5878 /* If statement applies to 5705 and 5750 PCI devices only */
5879 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5880 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 5882 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5883 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5884 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5885 /* nothing */
5886 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5887 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5888 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5889 val |= WDMAC_MODE_RX_ACCEL;
5890 }
5891 }
5892
5893 tw32_f(WDMAC_MODE, val);
5894 udelay(40);
5895
5896 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5897 val = tr32(TG3PCI_X_CAPS);
5898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5899 val &= ~PCIX_CAPS_BURST_MASK;
5900 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5901 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5902 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5903 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5904 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5905 val |= (tp->split_mode_max_reqs <<
5906 PCIX_CAPS_SPLIT_SHIFT);
5907 }
5908 tw32(TG3PCI_X_CAPS, val);
5909 }
5910
5911 tw32_f(RDMAC_MODE, rdmac_mode);
5912 udelay(40);
5913
5914 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5915 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5916 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5917 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5918 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5919 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5920 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5921 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5922#if TG3_TSO_SUPPORT != 0
5923 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5924 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5925#endif
5926 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5927 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5928
5929 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5930 err = tg3_load_5701_a0_firmware_fix(tp);
5931 if (err)
5932 return err;
5933 }
5934
5935#if TG3_TSO_SUPPORT != 0
5936 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5937 err = tg3_load_tso_firmware(tp);
5938 if (err)
5939 return err;
5940 }
5941#endif
5942
5943 tp->tx_mode = TX_MODE_ENABLE;
5944 tw32_f(MAC_TX_MODE, tp->tx_mode);
5945 udelay(100);
5946
5947 tp->rx_mode = RX_MODE_ENABLE;
5948 tw32_f(MAC_RX_MODE, tp->rx_mode);
5949 udelay(10);
5950
5951 if (tp->link_config.phy_is_low_power) {
5952 tp->link_config.phy_is_low_power = 0;
5953 tp->link_config.speed = tp->link_config.orig_speed;
5954 tp->link_config.duplex = tp->link_config.orig_duplex;
5955 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5956 }
5957
5958 tp->mi_mode = MAC_MI_MODE_BASE;
5959 tw32_f(MAC_MI_MODE, tp->mi_mode);
5960 udelay(80);
5961
5962 tw32(MAC_LED_CTRL, tp->led_ctrl);
5963
5964 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5965 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5966 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5967 udelay(10);
5968 }
5969 tw32_f(MAC_RX_MODE, tp->rx_mode);
5970 udelay(10);
5971
5972 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5973 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5974 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5975 /* Set drive transmission level to 1.2V */
5976 /* only if the signal pre-emphasis bit is not set */
5977 val = tr32(MAC_SERDES_CFG);
5978 val &= 0xfffff000;
5979 val |= 0x880;
5980 tw32(MAC_SERDES_CFG, val);
5981 }
5982 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5983 tw32(MAC_SERDES_CFG, 0x616000);
5984 }
5985
5986 /* Prevent chip from dropping frames when flow control
5987 * is enabled.
5988 */
5989 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5990
5991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5992 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5993 /* Use hardware link auto-negotiation */
5994 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5995 }
5996
5997 err = tg3_setup_phy(tp, 1);
5998 if (err)
5999 return err;
6000
6001 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6002 u32 tmp;
6003
6004 /* Clear CRC stats. */
6005 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6006 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6007 tg3_readphy(tp, 0x14, &tmp);
6008 }
6009 }
6010
6011 __tg3_set_rx_mode(tp->dev);
6012
6013 /* Initialize receive rules. */
6014 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6015 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6016 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6017 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6018
4cf78e4f
MC		 6019 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6020 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
1da177e4
LT		 6021 limit = 8;
6022 else
6023 limit = 16;
6024 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6025 limit -= 4;
6026 switch (limit) {
6027 case 16:
6028 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6029 case 15:
6030 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6031 case 14:
6032 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6033 case 13:
6034 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6035 case 12:
6036 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6037 case 11:
6038 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6039 case 10:
6040 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6041 case 9:
6042 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6043 case 8:
6044 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6045 case 7:
6046 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6047 case 6:
6048 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6049 case 5:
6050 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6051 case 4:
6052 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6053 case 3:
6054 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6055 case 2:
6056 case 1:
6057
6058 default:
6059 break;
6060 };
6061
6062 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6063
1da177e4
LT		 6064 return 0;
6065}
6066
6067/* Called at device open time to get the chip ready for
6068 * packet processing. Invoked with tp->lock held.
6069 */
6070static int tg3_init_hw(struct tg3 *tp)
6071{
6072 int err;
6073
6074 /* Force the chip into D0. */
6075 err = tg3_set_power_state(tp, 0);
6076 if (err)
6077 goto out;
6078
6079 tg3_switch_clocks(tp);
6080
6081 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6082
6083 err = tg3_reset_hw(tp);
6084
6085out:
6086 return err;
6087}
6088
6089#define TG3_STAT_ADD32(PSTAT, REG) \
6090do { u32 __val = tr32(REG); \
6091 (PSTAT)->low += __val; \
6092 if ((PSTAT)->low < __val) \
6093 (PSTAT)->high += 1; \
6094} while (0)
6095
6096static void tg3_periodic_fetch_stats(struct tg3 *tp)
6097{
6098 struct tg3_hw_stats *sp = tp->hw_stats;
6099
6100 if (!netif_carrier_ok(tp->dev))
6101 return;
6102
6103 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6104 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6105 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6106 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6107 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6108 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6109 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6110 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6111 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6112 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6113 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6114 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6115 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6116
6117 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6118 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6119 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6120 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6121 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6122 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6123 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6124 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6125 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6126 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6127 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6128 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6129 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6130 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6131}
6132
6133static void tg3_timer(unsigned long __opaque)
6134{
6135 struct tg3 *tp = (struct tg3 *) __opaque;
1da177e4 6136
f47c11ee 6137 spin_lock(&tp->lock);
1da177e4 6138
fac9b83e
DM		 6139 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6140 /* All of this garbage is because when using non-tagged
6141 * IRQ status the mailbox/status_block protocol the chip
6142 * uses with the cpu is race prone.
6143 */
6144 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6145 tw32(GRC_LOCAL_CTRL,
6146 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6147 } else {
6148 tw32(HOSTCC_MODE, tp->coalesce_mode |
6149 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6150 }
1da177e4 6151
fac9b83e
DM		 6152 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6153 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
f47c11ee 6154 spin_unlock(&tp->lock);
fac9b83e
DM		 6155 schedule_work(&tp->reset_task);
6156 return;
6157 }
1da177e4
LT		 6158 }
6159
1da177e4
LT		 6160 /* This part only runs once per second. */
6161 if (!--tp->timer_counter) {
fac9b83e
DM		 6162 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6163 tg3_periodic_fetch_stats(tp);
6164
1da177e4
LT		 6165 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6166 u32 mac_stat;
6167 int phy_event;
6168
6169 mac_stat = tr32(MAC_STATUS);
6170
6171 phy_event = 0;
6172 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6173 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6174 phy_event = 1;
6175 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6176 phy_event = 1;
6177
6178 if (phy_event)
6179 tg3_setup_phy(tp, 0);
6180 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6181 u32 mac_stat = tr32(MAC_STATUS);
6182 int need_setup = 0;
6183
6184 if (netif_carrier_ok(tp->dev) &&
6185 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6186 need_setup = 1;
6187 }
6188 if (! netif_carrier_ok(tp->dev) &&
6189 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6190 MAC_STATUS_SIGNAL_DET))) {
6191 need_setup = 1;
6192 }
6193 if (need_setup) {
6194 tw32_f(MAC_MODE,
6195 (tp->mac_mode &
6196 ~MAC_MODE_PORT_MODE_MASK));
6197 udelay(40);
6198 tw32_f(MAC_MODE, tp->mac_mode);
6199 udelay(40);
6200 tg3_setup_phy(tp, 0);
6201 }
747e8f8b
MC		 6202 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6203 tg3_serdes_parallel_detect(tp);
1da177e4
LT		 6204
6205 tp->timer_counter = tp->timer_multiplier;
6206 }
6207
6208 /* Heartbeat is only sent once every 120 seconds. */
6209 if (!--tp->asf_counter) {
6210 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6211 u32 val;
6212
6213 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
6214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6215 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
6216 val = tr32(GRC_RX_CPU_EVENT);
6217 val |= (1 << 14);
6218 tw32(GRC_RX_CPU_EVENT, val);
6219 }
6220 tp->asf_counter = tp->asf_multiplier;
6221 }
6222
f47c11ee 6223 spin_unlock(&tp->lock);
1da177e4
LT		 6224
6225 tp->timer.expires = jiffies + tp->timer_offset;
6226 add_timer(&tp->timer);
6227}
6228
7938109f
MC		 6229static int tg3_test_interrupt(struct tg3 *tp)
6230{
6231 struct net_device *dev = tp->dev;
6232 int err, i;
6233 u32 int_mbox = 0;
6234
d4bc3927
MC		 6235 if (!netif_running(dev))
6236 return -ENODEV;
6237
7938109f
MC		 6238 tg3_disable_ints(tp);
6239
6240 free_irq(tp->pdev->irq, dev);
6241
6242 err = request_irq(tp->pdev->irq, tg3_test_isr,
f4d0ee98 6243 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
7938109f
MC		 6244 if (err)
6245 return err;
6246
6247 tg3_enable_ints(tp);
6248
6249 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6250 HOSTCC_MODE_NOW);
6251
6252 for (i = 0; i < 5; i++) {
09ee929c
MC		 6253 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6254 TG3_64BIT_REG_LOW);
7938109f
MC		 6255 if (int_mbox != 0)
6256 break;
6257 msleep(10);
6258 }
6259
6260 tg3_disable_ints(tp);
6261
6262 free_irq(tp->pdev->irq, dev);
6263
6264 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6265 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6266 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6267 else {
6268 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6269 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6270 fn = tg3_interrupt_tagged;
6271 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6272 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6273 }
7938109f
MC		 6274
6275 if (err)
6276 return err;
6277
6278 if (int_mbox != 0)
6279 return 0;
6280
6281 return -EIO;
6282}
6283
6284/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6285 * successfully restored
6286 */
6287static int tg3_test_msi(struct tg3 *tp)
6288{
6289 struct net_device *dev = tp->dev;
6290 int err;
6291 u16 pci_cmd;
6292
6293 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6294 return 0;
6295
6296 /* Turn off SERR reporting in case MSI terminates with Master
6297 * Abort.
6298 */
6299 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6300 pci_write_config_word(tp->pdev, PCI_COMMAND,
6301 pci_cmd & ~PCI_COMMAND_SERR);
6302
6303 err = tg3_test_interrupt(tp);
6304
6305 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6306
6307 if (!err)
6308 return 0;
6309
6310 /* other failures */
6311 if (err != -EIO)
6312 return err;
6313
6314 /* MSI test failed, go back to INTx mode */
6315 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6316 "switching to INTx mode. Please report this failure to "
6317 "the PCI maintainer and include system chipset information.\n",
6318 tp->dev->name);
6319
6320 free_irq(tp->pdev->irq, dev);
6321 pci_disable_msi(tp->pdev);
6322
6323 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6324
fac9b83e
DM		 6325 {
6326 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6327 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6328 fn = tg3_interrupt_tagged;
7938109f 6329
fac9b83e
DM		 6330 err = request_irq(tp->pdev->irq, fn,
6331 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6332 }
7938109f
MC		 6333 if (err)
6334 return err;
6335
6336 /* Need to reset the chip because the MSI cycle may have terminated
6337 * with Master Abort.
6338 */
f47c11ee 6339 tg3_full_lock(tp, 1);
7938109f 6340
944d980e 6341 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6342 err = tg3_init_hw(tp);
6343
f47c11ee 6344 tg3_full_unlock(tp);
7938109f
MC		 6345
6346 if (err)
6347 free_irq(tp->pdev->irq, dev);
6348
6349 return err;
6350}
6351
1da177e4
LT		 6352static int tg3_open(struct net_device *dev)
6353{
6354 struct tg3 *tp = netdev_priv(dev);
6355 int err;
6356
f47c11ee 6357 tg3_full_lock(tp, 0);
1da177e4
LT		 6358
6359 tg3_disable_ints(tp);
6360 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6361
f47c11ee 6362 tg3_full_unlock(tp);
1da177e4
LT		 6363
6364 /* The placement of this call is tied
6365 * to the setup and use of Host TX descriptors.
6366 */
6367 err = tg3_alloc_consistent(tp);
6368 if (err)
6369 return err;
6370
88b06bc2
MC		 6371 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6372 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6373 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
fac9b83e
DM		 6374 /* All MSI supporting chips should support tagged
6375 * status. Assert that this is the case.
6376 */
6377 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6378 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6379 "Not using MSI.\n", tp->dev->name);
6380 } else if (pci_enable_msi(tp->pdev) == 0) {
88b06bc2
MC		 6381 u32 msi_mode;
6382
6383 msi_mode = tr32(MSGINT_MODE);
6384 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6385 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6386 }
6387 }
6388 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6389 err = request_irq(tp->pdev->irq, tg3_msi,
f4d0ee98 6390 SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e
DM		 6391 else {
6392 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6393 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6394 fn = tg3_interrupt_tagged;
6395
6396 err = request_irq(tp->pdev->irq, fn,
f4d0ee98 6397 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
fac9b83e 6398 }
1da177e4
LT		 6399
6400 if (err) {
88b06bc2
MC		 6401 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6402 pci_disable_msi(tp->pdev);
6403 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6404 }
1da177e4
LT		 6405 tg3_free_consistent(tp);
6406 return err;
6407 }
6408
f47c11ee 6409 tg3_full_lock(tp, 0);
1da177e4
LT		 6410
6411 err = tg3_init_hw(tp);
6412 if (err) {
944d980e 6413 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6414 tg3_free_rings(tp);
6415 } else {
fac9b83e
DM		 6416 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6417 tp->timer_offset = HZ;
6418 else
6419 tp->timer_offset = HZ / 10;
6420
6421 BUG_ON(tp->timer_offset > HZ);
6422 tp->timer_counter = tp->timer_multiplier =
6423 (HZ / tp->timer_offset);
6424 tp->asf_counter = tp->asf_multiplier =
6425 ((HZ / tp->timer_offset) * 120);
1da177e4
LT		 6426
6427 init_timer(&tp->timer);
6428 tp->timer.expires = jiffies + tp->timer_offset;
6429 tp->timer.data = (unsigned long) tp;
6430 tp->timer.function = tg3_timer;
1da177e4
LT		 6431 }
6432
f47c11ee 6433 tg3_full_unlock(tp);
1da177e4
LT		 6434
6435 if (err) {
88b06bc2
MC		 6436 free_irq(tp->pdev->irq, dev);
6437 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6438 pci_disable_msi(tp->pdev);
6439 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6440 }
1da177e4
LT		 6441 tg3_free_consistent(tp);
6442 return err;
6443 }
6444
7938109f
MC		 6445 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6446 err = tg3_test_msi(tp);
fac9b83e 6447
7938109f 6448 if (err) {
f47c11ee 6449 tg3_full_lock(tp, 0);
7938109f
MC		 6450
6451 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6452 pci_disable_msi(tp->pdev);
6453 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6454 }
944d980e 6455 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7938109f
MC		 6456 tg3_free_rings(tp);
6457 tg3_free_consistent(tp);
6458
f47c11ee 6459 tg3_full_unlock(tp);
7938109f
MC		 6460
6461 return err;
6462 }
6463 }
6464
f47c11ee 6465 tg3_full_lock(tp, 0);
1da177e4 6466
7938109f
MC		 6467 add_timer(&tp->timer);
6468 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
1da177e4
LT		 6469 tg3_enable_ints(tp);
6470
f47c11ee 6471 tg3_full_unlock(tp);
1da177e4
LT		 6472
6473 netif_start_queue(dev);
6474
6475 return 0;
6476}
6477
6478#if 0
6479/*static*/ void tg3_dump_state(struct tg3 *tp)
6480{
6481 u32 val32, val32_2, val32_3, val32_4, val32_5;
6482 u16 val16;
6483 int i;
6484
6485 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6486 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6487 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6488 val16, val32);
6489
6490 /* MAC block */
6491 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6492 tr32(MAC_MODE), tr32(MAC_STATUS));
6493 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6494 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6495 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6496 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6497 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6498 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6499
6500 /* Send data initiator control block */
6501 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6502 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6503 printk(" SNDDATAI_STATSCTRL[%08x]\n",
6504 tr32(SNDDATAI_STATSCTRL));
6505
6506 /* Send data completion control block */
6507 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6508
6509 /* Send BD ring selector block */
6510 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6511 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6512
6513 /* Send BD initiator control block */
6514 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6515 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6516
6517 /* Send BD completion control block */
6518 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6519
6520 /* Receive list placement control block */
6521 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6522 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6523 printk(" RCVLPC_STATSCTRL[%08x]\n",
6524 tr32(RCVLPC_STATSCTRL));
6525
6526 /* Receive data and receive BD initiator control block */
6527 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6528 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6529
6530 /* Receive data completion control block */
6531 printk("DEBUG: RCVDCC_MODE[%08x]\n",
6532 tr32(RCVDCC_MODE));
6533
6534 /* Receive BD initiator control block */
6535 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6536 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6537
6538 /* Receive BD completion control block */
6539 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6540 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6541
6542 /* Receive list selector control block */
6543 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6544 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6545
6546 /* Mbuf cluster free block */
6547 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6548 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6549
6550 /* Host coalescing control block */
6551 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6552 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6553 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6554 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6555 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6556 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6557 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6558 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6559 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6560 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6561 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6562 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6563
6564 /* Memory arbiter control block */
6565 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6566 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6567
6568 /* Buffer manager control block */
6569 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6570 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6571 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6572 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6573 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6574 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6575 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6576 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6577
6578 /* Read DMA control block */
6579 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6580 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6581
6582 /* Write DMA control block */
6583 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6584 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6585
6586 /* DMA completion block */
6587 printk("DEBUG: DMAC_MODE[%08x]\n",
6588 tr32(DMAC_MODE));
6589
6590 /* GRC block */
6591 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6592 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6593 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6594 tr32(GRC_LOCAL_CTRL));
6595
6596 /* TG3_BDINFOs */
6597 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6598 tr32(RCVDBDI_JUMBO_BD + 0x0),
6599 tr32(RCVDBDI_JUMBO_BD + 0x4),
6600 tr32(RCVDBDI_JUMBO_BD + 0x8),
6601 tr32(RCVDBDI_JUMBO_BD + 0xc));
6602 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6603 tr32(RCVDBDI_STD_BD + 0x0),
6604 tr32(RCVDBDI_STD_BD + 0x4),
6605 tr32(RCVDBDI_STD_BD + 0x8),
6606 tr32(RCVDBDI_STD_BD + 0xc));
6607 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6608 tr32(RCVDBDI_MINI_BD + 0x0),
6609 tr32(RCVDBDI_MINI_BD + 0x4),
6610 tr32(RCVDBDI_MINI_BD + 0x8),
6611 tr32(RCVDBDI_MINI_BD + 0xc));
6612
6613 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6614 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6615 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6616 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6617 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6618 val32, val32_2, val32_3, val32_4);
6619
6620 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6621 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6622 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6623 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6624 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6625 val32, val32_2, val32_3, val32_4);
6626
6627 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6628 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6629 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6630 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6631 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6632 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6633 val32, val32_2, val32_3, val32_4, val32_5);
6634
6635 /* SW status block */
6636 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6637 tp->hw_status->status,
6638 tp->hw_status->status_tag,
6639 tp->hw_status->rx_jumbo_consumer,
6640 tp->hw_status->rx_consumer,
6641 tp->hw_status->rx_mini_consumer,
6642 tp->hw_status->idx[0].rx_producer,
6643 tp->hw_status->idx[0].tx_consumer);
6644
6645 /* SW statistics block */
6646 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6647 ((u32 *)tp->hw_stats)[0],
6648 ((u32 *)tp->hw_stats)[1],
6649 ((u32 *)tp->hw_stats)[2],
6650 ((u32 *)tp->hw_stats)[3]);
6651
6652 /* Mailboxes */
6653 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
09ee929c
MC		 6654 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6655 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6656 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6657 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
1da177e4
LT		 6658
6659 /* NIC side send descriptors. */
6660 for (i = 0; i < 6; i++) {
6661 unsigned long txd;
6662
6663 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6664 + (i * sizeof(struct tg3_tx_buffer_desc));
6665 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6666 i,
6667 readl(txd + 0x0), readl(txd + 0x4),
6668 readl(txd + 0x8), readl(txd + 0xc));
6669 }
6670
6671 /* NIC side RX descriptors. */
6672 for (i = 0; i < 6; i++) {
6673 unsigned long rxd;
6674
6675 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6676 + (i * sizeof(struct tg3_rx_buffer_desc));
6677 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6678 i,
6679 readl(rxd + 0x0), readl(rxd + 0x4),
6680 readl(rxd + 0x8), readl(rxd + 0xc));
6681 rxd += (4 * sizeof(u32));
6682 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6683 i,
6684 readl(rxd + 0x0), readl(rxd + 0x4),
6685 readl(rxd + 0x8), readl(rxd + 0xc));
6686 }
6687
6688 for (i = 0; i < 6; i++) {
6689 unsigned long rxd;
6690
6691 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6692 + (i * sizeof(struct tg3_rx_buffer_desc));
6693 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6694 i,
6695 readl(rxd + 0x0), readl(rxd + 0x4),
6696 readl(rxd + 0x8), readl(rxd + 0xc));
6697 rxd += (4 * sizeof(u32));
6698 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6699 i,
6700 readl(rxd + 0x0), readl(rxd + 0x4),
6701 readl(rxd + 0x8), readl(rxd + 0xc));
6702 }
6703}
6704#endif
6705
6706static struct net_device_stats *tg3_get_stats(struct net_device *);
6707static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6708
6709static int tg3_close(struct net_device *dev)
6710{
6711 struct tg3 *tp = netdev_priv(dev);
6712
6713 netif_stop_queue(dev);
6714
6715 del_timer_sync(&tp->timer);
6716
f47c11ee 6717 tg3_full_lock(tp, 1);
1da177e4
LT		 6718#if 0
6719 tg3_dump_state(tp);
6720#endif
6721
6722 tg3_disable_ints(tp);
6723
944d980e 6724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 6725 tg3_free_rings(tp);
6726 tp->tg3_flags &=
6727 ~(TG3_FLAG_INIT_COMPLETE |
6728 TG3_FLAG_GOT_SERDES_FLOWCTL);
6729 netif_carrier_off(tp->dev);
6730
f47c11ee 6731 tg3_full_unlock(tp);
1da177e4 6732
88b06bc2
MC		 6733 free_irq(tp->pdev->irq, dev);
6734 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6735 pci_disable_msi(tp->pdev);
6736 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6737 }
1da177e4
LT		 6738
6739 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6740 sizeof(tp->net_stats_prev));
6741 memcpy(&tp->estats_prev, tg3_get_estats(tp),
6742 sizeof(tp->estats_prev));
6743
6744 tg3_free_consistent(tp);
6745
6746 return 0;
6747}
6748
6749static inline unsigned long get_stat64(tg3_stat64_t *val)
6750{
6751 unsigned long ret;
6752
6753#if (BITS_PER_LONG == 32)
6754 ret = val->low;
6755#else
6756 ret = ((u64)val->high << 32) | ((u64)val->low);
6757#endif
6758 return ret;
6759}
6760
6761static unsigned long calc_crc_errors(struct tg3 *tp)
6762{
6763 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6764
6765 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6766 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6767 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1da177e4
LT		 6768 u32 val;
6769
f47c11ee 6770 spin_lock_bh(&tp->lock);
1da177e4
LT		 6771 if (!tg3_readphy(tp, 0x1e, &val)) {
6772 tg3_writephy(tp, 0x1e, val | 0x8000);
6773 tg3_readphy(tp, 0x14, &val);
6774 } else
6775 val = 0;
f47c11ee 6776 spin_unlock_bh(&tp->lock);
1da177e4
LT		 6777
6778 tp->phy_crc_errors += val;
6779
6780 return tp->phy_crc_errors;
6781 }
6782
6783 return get_stat64(&hw_stats->rx_fcs_errors);
6784}
6785
6786#define ESTAT_ADD(member) \
6787 estats->member = old_estats->member + \
6788 get_stat64(&hw_stats->member)
6789
6790static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6791{
6792 struct tg3_ethtool_stats *estats = &tp->estats;
6793 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6794 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6795
6796 if (!hw_stats)
6797 return old_estats;
6798
6799 ESTAT_ADD(rx_octets);
6800 ESTAT_ADD(rx_fragments);
6801 ESTAT_ADD(rx_ucast_packets);
6802 ESTAT_ADD(rx_mcast_packets);
6803 ESTAT_ADD(rx_bcast_packets);
6804 ESTAT_ADD(rx_fcs_errors);
6805 ESTAT_ADD(rx_align_errors);
6806 ESTAT_ADD(rx_xon_pause_rcvd);
6807 ESTAT_ADD(rx_xoff_pause_rcvd);
6808 ESTAT_ADD(rx_mac_ctrl_rcvd);
6809 ESTAT_ADD(rx_xoff_entered);
6810 ESTAT_ADD(rx_frame_too_long_errors);
6811 ESTAT_ADD(rx_jabbers);
6812 ESTAT_ADD(rx_undersize_packets);
6813 ESTAT_ADD(rx_in_length_errors);
6814 ESTAT_ADD(rx_out_length_errors);
6815 ESTAT_ADD(rx_64_or_less_octet_packets);
6816 ESTAT_ADD(rx_65_to_127_octet_packets);
6817 ESTAT_ADD(rx_128_to_255_octet_packets);
6818 ESTAT_ADD(rx_256_to_511_octet_packets);
6819 ESTAT_ADD(rx_512_to_1023_octet_packets);
6820 ESTAT_ADD(rx_1024_to_1522_octet_packets);
6821 ESTAT_ADD(rx_1523_to_2047_octet_packets);
6822 ESTAT_ADD(rx_2048_to_4095_octet_packets);
6823 ESTAT_ADD(rx_4096_to_8191_octet_packets);
6824 ESTAT_ADD(rx_8192_to_9022_octet_packets);
6825
6826 ESTAT_ADD(tx_octets);
6827 ESTAT_ADD(tx_collisions);
6828 ESTAT_ADD(tx_xon_sent);
6829 ESTAT_ADD(tx_xoff_sent);
6830 ESTAT_ADD(tx_flow_control);
6831 ESTAT_ADD(tx_mac_errors);
6832 ESTAT_ADD(tx_single_collisions);
6833 ESTAT_ADD(tx_mult_collisions);
6834 ESTAT_ADD(tx_deferred);
6835 ESTAT_ADD(tx_excessive_collisions);
6836 ESTAT_ADD(tx_late_collisions);
6837 ESTAT_ADD(tx_collide_2times);
6838 ESTAT_ADD(tx_collide_3times);
6839 ESTAT_ADD(tx_collide_4times);
6840 ESTAT_ADD(tx_collide_5times);
6841 ESTAT_ADD(tx_collide_6times);
6842 ESTAT_ADD(tx_collide_7times);
6843 ESTAT_ADD(tx_collide_8times);
6844 ESTAT_ADD(tx_collide_9times);
6845 ESTAT_ADD(tx_collide_10times);
6846 ESTAT_ADD(tx_collide_11times);
6847 ESTAT_ADD(tx_collide_12times);
6848 ESTAT_ADD(tx_collide_13times);
6849 ESTAT_ADD(tx_collide_14times);
6850 ESTAT_ADD(tx_collide_15times);
6851 ESTAT_ADD(tx_ucast_packets);
6852 ESTAT_ADD(tx_mcast_packets);
6853 ESTAT_ADD(tx_bcast_packets);
6854 ESTAT_ADD(tx_carrier_sense_errors);
6855 ESTAT_ADD(tx_discards);
6856 ESTAT_ADD(tx_errors);
6857
6858 ESTAT_ADD(dma_writeq_full);
6859 ESTAT_ADD(dma_write_prioq_full);
6860 ESTAT_ADD(rxbds_empty);
6861 ESTAT_ADD(rx_discards);
6862 ESTAT_ADD(rx_errors);
6863 ESTAT_ADD(rx_threshold_hit);
6864
6865 ESTAT_ADD(dma_readq_full);
6866 ESTAT_ADD(dma_read_prioq_full);
6867 ESTAT_ADD(tx_comp_queue_full);
6868
6869 ESTAT_ADD(ring_set_send_prod_index);
6870 ESTAT_ADD(ring_status_update);
6871 ESTAT_ADD(nic_irqs);
6872 ESTAT_ADD(nic_avoided_irqs);
6873 ESTAT_ADD(nic_tx_threshold_hit);
6874
6875 return estats;
6876}
6877
6878static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6879{
6880 struct tg3 *tp = netdev_priv(dev);
6881 struct net_device_stats *stats = &tp->net_stats;
6882 struct net_device_stats *old_stats = &tp->net_stats_prev;
6883 struct tg3_hw_stats *hw_stats = tp->hw_stats;
6884
6885 if (!hw_stats)
6886 return old_stats;
6887
6888 stats->rx_packets = old_stats->rx_packets +
6889 get_stat64(&hw_stats->rx_ucast_packets) +
6890 get_stat64(&hw_stats->rx_mcast_packets) +
6891 get_stat64(&hw_stats->rx_bcast_packets);
6892
6893 stats->tx_packets = old_stats->tx_packets +
6894 get_stat64(&hw_stats->tx_ucast_packets) +
6895 get_stat64(&hw_stats->tx_mcast_packets) +
6896 get_stat64(&hw_stats->tx_bcast_packets);
6897
6898 stats->rx_bytes = old_stats->rx_bytes +
6899 get_stat64(&hw_stats->rx_octets);
6900 stats->tx_bytes = old_stats->tx_bytes +
6901 get_stat64(&hw_stats->tx_octets);
6902
6903 stats->rx_errors = old_stats->rx_errors +
6904 get_stat64(&hw_stats->rx_errors) +
6905 get_stat64(&hw_stats->rx_discards);
6906 stats->tx_errors = old_stats->tx_errors +
6907 get_stat64(&hw_stats->tx_errors) +
6908 get_stat64(&hw_stats->tx_mac_errors) +
6909 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6910 get_stat64(&hw_stats->tx_discards);
6911
6912 stats->multicast = old_stats->multicast +
6913 get_stat64(&hw_stats->rx_mcast_packets);
6914 stats->collisions = old_stats->collisions +
6915 get_stat64(&hw_stats->tx_collisions);
6916
6917 stats->rx_length_errors = old_stats->rx_length_errors +
6918 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6919 get_stat64(&hw_stats->rx_undersize_packets);
6920
6921 stats->rx_over_errors = old_stats->rx_over_errors +
6922 get_stat64(&hw_stats->rxbds_empty);
6923 stats->rx_frame_errors = old_stats->rx_frame_errors +
6924 get_stat64(&hw_stats->rx_align_errors);
6925 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6926 get_stat64(&hw_stats->tx_discards);
6927 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6928 get_stat64(&hw_stats->tx_carrier_sense_errors);
6929
6930 stats->rx_crc_errors = old_stats->rx_crc_errors +
6931 calc_crc_errors(tp);
6932
6933 return stats;
6934}
6935
6936static inline u32 calc_crc(unsigned char *buf, int len)
6937{
6938 u32 reg;
6939 u32 tmp;
6940 int j, k;
6941
6942 reg = 0xffffffff;
6943
6944 for (j = 0; j < len; j++) {
6945 reg ^= buf[j];
6946
6947 for (k = 0; k < 8; k++) {
6948 tmp = reg & 0x01;
6949
6950 reg >>= 1;
6951
6952 if (tmp) {
6953 reg ^= 0xedb88320;
6954 }
6955 }
6956 }
6957
6958 return ~reg;
6959}
6960
6961static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6962{
6963 /* accept or reject all multicast frames */
6964 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6965 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6966 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6967 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6968}
6969
6970static void __tg3_set_rx_mode(struct net_device *dev)
6971{
6972 struct tg3 *tp = netdev_priv(dev);
6973 u32 rx_mode;
6974
6975 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6976 RX_MODE_KEEP_VLAN_TAG);
6977
6978 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6979 * flag clear.
6980 */
6981#if TG3_VLAN_TAG_USED
6982 if (!tp->vlgrp &&
6983 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6984 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6985#else
6986 /* By definition, VLAN is disabled always in this
6987 * case.
6988 */
6989 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6990 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6991#endif
6992
6993 if (dev->flags & IFF_PROMISC) {
6994 /* Promiscuous mode. */
6995 rx_mode |= RX_MODE_PROMISC;
6996 } else if (dev->flags & IFF_ALLMULTI) {
6997 /* Accept all multicast. */
6998 tg3_set_multi (tp, 1);
6999 } else if (dev->mc_count < 1) {
7000 /* Reject all multicast. */
7001 tg3_set_multi (tp, 0);
7002 } else {
7003 /* Accept one or more multicast(s). */
7004 struct dev_mc_list *mclist;
7005 unsigned int i;
7006 u32 mc_filter[4] = { 0, };
7007 u32 regidx;
7008 u32 bit;
7009 u32 crc;
7010
7011 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7012 i++, mclist = mclist->next) {
7013
7014 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7015 bit = ~crc & 0x7f;
7016 regidx = (bit & 0x60) >> 5;
7017 bit &= 0x1f;
7018 mc_filter[regidx] |= (1 << bit);
7019 }
7020
7021 tw32(MAC_HASH_REG_0, mc_filter[0]);
7022 tw32(MAC_HASH_REG_1, mc_filter[1]);
7023 tw32(MAC_HASH_REG_2, mc_filter[2]);
7024 tw32(MAC_HASH_REG_3, mc_filter[3]);
7025 }
7026
7027 if (rx_mode != tp->rx_mode) {
7028 tp->rx_mode = rx_mode;
7029 tw32_f(MAC_RX_MODE, rx_mode);
7030 udelay(10);
7031 }
7032}
7033
7034static void tg3_set_rx_mode(struct net_device *dev)
7035{
7036 struct tg3 *tp = netdev_priv(dev);
7037
f47c11ee 7038 tg3_full_lock(tp, 0);
1da177e4 7039 __tg3_set_rx_mode(dev);
f47c11ee 7040 tg3_full_unlock(tp);
1da177e4
LT		 7041}
7042
7043#define TG3_REGDUMP_LEN (32 * 1024)
7044
7045static int tg3_get_regs_len(struct net_device *dev)
7046{
7047 return TG3_REGDUMP_LEN;
7048}
7049
7050static void tg3_get_regs(struct net_device *dev,
7051 struct ethtool_regs *regs, void *_p)
7052{
7053 u32 *p = _p;
7054 struct tg3 *tp = netdev_priv(dev);
7055 u8 *orig_p = _p;
7056 int i;
7057
7058 regs->version = 0;
7059
7060 memset(p, 0, TG3_REGDUMP_LEN);
7061
f47c11ee 7062 tg3_full_lock(tp, 0);
1da177e4
LT		 7063
7064#define __GET_REG32(reg) (*(p)++ = tr32(reg))
7065#define GET_REG32_LOOP(base,len) \
7066do { p = (u32 *)(orig_p + (base)); \
7067 for (i = 0; i < len; i += 4) \
7068 __GET_REG32((base) + i); \
7069} while (0)
7070#define GET_REG32_1(reg) \
7071do { p = (u32 *)(orig_p + (reg)); \
7072 __GET_REG32((reg)); \
7073} while (0)
7074
7075 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7076 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7077 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7078 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7079 GET_REG32_1(SNDDATAC_MODE);
7080 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7081 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7082 GET_REG32_1(SNDBDC_MODE);
7083 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7084 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7085 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7086 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7087 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7088 GET_REG32_1(RCVDCC_MODE);
7089 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7090 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7091 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7092 GET_REG32_1(MBFREE_MODE);
7093 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7094 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7095 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7096 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7097 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7098 GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7099 GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7100 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7101 GET_REG32_LOOP(FTQ_RESET, 0x120);
7102 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7103 GET_REG32_1(DMAC_MODE);
7104 GET_REG32_LOOP(GRC_MODE, 0x4c);
7105 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7106 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7107
7108#undef __GET_REG32
7109#undef GET_REG32_LOOP
7110#undef GET_REG32_1
7111
f47c11ee 7112 tg3_full_unlock(tp);
1da177e4
LT		 7113}
7114
7115static int tg3_get_eeprom_len(struct net_device *dev)
7116{
7117 struct tg3 *tp = netdev_priv(dev);
7118
7119 return tp->nvram_size;
7120}
7121
7122static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7123
7124static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7125{
7126 struct tg3 *tp = netdev_priv(dev);
7127 int ret;
7128 u8 *pd;
7129 u32 i, offset, len, val, b_offset, b_count;
7130
7131 offset = eeprom->offset;
7132 len = eeprom->len;
7133 eeprom->len = 0;
7134
7135 eeprom->magic = TG3_EEPROM_MAGIC;
7136
7137 if (offset & 3) {
7138 /* adjustments to start on required 4 byte boundary */
7139 b_offset = offset & 3;
7140 b_count = 4 - b_offset;
7141 if (b_count > len) {
7142 /* i.e. offset=1 len=2 */
7143 b_count = len;
7144 }
7145 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7146 if (ret)
7147 return ret;
7148 val = cpu_to_le32(val);
7149 memcpy(data, ((char*)&val) + b_offset, b_count);
7150 len -= b_count;
7151 offset += b_count;
7152 eeprom->len += b_count;
7153 }
7154
7155 /* read bytes upto the last 4 byte boundary */
7156 pd = &data[eeprom->len];
7157 for (i = 0; i < (len - (len & 3)); i += 4) {
7158 ret = tg3_nvram_read(tp, offset + i, &val);
7159 if (ret) {
7160 eeprom->len += i;
7161 return ret;
7162 }
7163 val = cpu_to_le32(val);
7164 memcpy(pd + i, &val, 4);
7165 }
7166 eeprom->len += i;
7167
7168 if (len & 3) {
7169 /* read last bytes not ending on 4 byte boundary */
7170 pd = &data[eeprom->len];
7171 b_count = len & 3;
7172 b_offset = offset + len - b_count;
7173 ret = tg3_nvram_read(tp, b_offset, &val);
7174 if (ret)
7175 return ret;
7176 val = cpu_to_le32(val);
7177 memcpy(pd, ((char*)&val), b_count);
7178 eeprom->len += b_count;
7179 }
7180 return 0;
7181}
7182
7183static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7184
7185static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7186{
7187 struct tg3 *tp = netdev_priv(dev);
7188 int ret;
7189 u32 offset, len, b_offset, odd_len, start, end;
7190 u8 *buf;
7191
7192 if (eeprom->magic != TG3_EEPROM_MAGIC)
7193 return -EINVAL;
7194
7195 offset = eeprom->offset;
7196 len = eeprom->len;
7197
7198 if ((b_offset = (offset & 3))) {
7199 /* adjustments to start on required 4 byte boundary */
7200 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7201 if (ret)
7202 return ret;
7203 start = cpu_to_le32(start);
7204 len += b_offset;
7205 offset &= ~3;
1c8594b4
MC		 7206 if (len < 4)
7207 len = 4;
1da177e4
LT		 7208 }
7209
7210 odd_len = 0;
1c8594b4 7211 if (len & 3) {
1da177e4
LT		 7212 /* adjustments to end on required 4 byte boundary */
7213 odd_len = 1;
7214 len = (len + 3) & ~3;
7215 ret = tg3_nvram_read(tp, offset+len-4, &end);
7216 if (ret)
7217 return ret;
7218 end = cpu_to_le32(end);
7219 }
7220
7221 buf = data;
7222 if (b_offset || odd_len) {
7223 buf = kmalloc(len, GFP_KERNEL);
7224 if (buf == 0)
7225 return -ENOMEM;
7226 if (b_offset)
7227 memcpy(buf, &start, 4);
7228 if (odd_len)
7229 memcpy(buf+len-4, &end, 4);
7230 memcpy(buf + b_offset, data, eeprom->len);
7231 }
7232
7233 ret = tg3_nvram_write_block(tp, offset, len, buf);
7234
7235 if (buf != data)
7236 kfree(buf);
7237
7238 return ret;
7239}
7240
7241static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7242{
7243 struct tg3 *tp = netdev_priv(dev);
7244
7245 cmd->supported = (SUPPORTED_Autoneg);
7246
7247 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7248 cmd->supported |= (SUPPORTED_1000baseT_Half |
7249 SUPPORTED_1000baseT_Full);
7250
7251 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
7252 cmd->supported |= (SUPPORTED_100baseT_Half |
7253 SUPPORTED_100baseT_Full |
7254 SUPPORTED_10baseT_Half |
7255 SUPPORTED_10baseT_Full |
7256 SUPPORTED_MII);
7257 else
7258 cmd->supported |= SUPPORTED_FIBRE;
7259
7260 cmd->advertising = tp->link_config.advertising;
7261 if (netif_running(dev)) {
7262 cmd->speed = tp->link_config.active_speed;
7263 cmd->duplex = tp->link_config.active_duplex;
7264 }
7265 cmd->port = 0;
7266 cmd->phy_address = PHY_ADDR;
7267 cmd->transceiver = 0;
7268 cmd->autoneg = tp->link_config.autoneg;
7269 cmd->maxtxpkt = 0;
7270 cmd->maxrxpkt = 0;
7271 return 0;
7272}
7273
7274static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7275{
7276 struct tg3 *tp = netdev_priv(dev);
7277
7278 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7279 /* These are the only valid advertisement bits allowed. */
7280 if (cmd->autoneg == AUTONEG_ENABLE &&
7281 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7282 ADVERTISED_1000baseT_Full |
7283 ADVERTISED_Autoneg |
7284 ADVERTISED_FIBRE)))
7285 return -EINVAL;
7286 }
7287
f47c11ee 7288 tg3_full_lock(tp, 0);
1da177e4
LT		 7289
7290 tp->link_config.autoneg = cmd->autoneg;
7291 if (cmd->autoneg == AUTONEG_ENABLE) {
7292 tp->link_config.advertising = cmd->advertising;
7293 tp->link_config.speed = SPEED_INVALID;
7294 tp->link_config.duplex = DUPLEX_INVALID;
7295 } else {
7296 tp->link_config.advertising = 0;
7297 tp->link_config.speed = cmd->speed;
7298 tp->link_config.duplex = cmd->duplex;
7299 }
7300
7301 if (netif_running(dev))
7302 tg3_setup_phy(tp, 1);
7303
f47c11ee 7304 tg3_full_unlock(tp);
1da177e4
LT		 7305
7306 return 0;
7307}
7308
7309static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7310{
7311 struct tg3 *tp = netdev_priv(dev);
7312
7313 strcpy(info->driver, DRV_MODULE_NAME);
7314 strcpy(info->version, DRV_MODULE_VERSION);
7315 strcpy(info->bus_info, pci_name(tp->pdev));
7316}
7317
7318static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7319{
7320 struct tg3 *tp = netdev_priv(dev);
7321
7322 wol->supported = WAKE_MAGIC;
7323 wol->wolopts = 0;
7324 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7325 wol->wolopts = WAKE_MAGIC;
7326 memset(&wol->sopass, 0, sizeof(wol->sopass));
7327}
7328
7329static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7330{
7331 struct tg3 *tp = netdev_priv(dev);
7332
7333 if (wol->wolopts & ~WAKE_MAGIC)
7334 return -EINVAL;
7335 if ((wol->wolopts & WAKE_MAGIC) &&
7336 tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7337 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7338 return -EINVAL;
7339
f47c11ee 7340 spin_lock_bh(&tp->lock);
1da177e4
LT		 7341 if (wol->wolopts & WAKE_MAGIC)
7342 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7343 else
7344 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
f47c11ee 7345 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7346
7347 return 0;
7348}
7349
7350static u32 tg3_get_msglevel(struct net_device *dev)
7351{
7352 struct tg3 *tp = netdev_priv(dev);
7353 return tp->msg_enable;
7354}
7355
7356static void tg3_set_msglevel(struct net_device *dev, u32 value)
7357{
7358 struct tg3 *tp = netdev_priv(dev);
7359 tp->msg_enable = value;
7360}
7361
7362#if TG3_TSO_SUPPORT != 0
7363static int tg3_set_tso(struct net_device *dev, u32 value)
7364{
7365 struct tg3 *tp = netdev_priv(dev);
7366
7367 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7368 if (value)
7369 return -EINVAL;
7370 return 0;
7371 }
7372 return ethtool_op_set_tso(dev, value);
7373}
7374#endif
7375
7376static int tg3_nway_reset(struct net_device *dev)
7377{
7378 struct tg3 *tp = netdev_priv(dev);
7379 u32 bmcr;
7380 int r;
7381
7382 if (!netif_running(dev))
7383 return -EAGAIN;
7384
f47c11ee 7385 spin_lock_bh(&tp->lock);
1da177e4
LT		 7386 r = -EINVAL;
7387 tg3_readphy(tp, MII_BMCR, &bmcr);
7388 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7389 (bmcr & BMCR_ANENABLE)) {
7390 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7391 r = 0;
7392 }
f47c11ee 7393 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7394
7395 return r;
7396}
7397
7398static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7399{
7400 struct tg3 *tp = netdev_priv(dev);
7401
7402 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7403 ering->rx_mini_max_pending = 0;
7404 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7405
7406 ering->rx_pending = tp->rx_pending;
7407 ering->rx_mini_pending = 0;
7408 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7409 ering->tx_pending = tp->tx_pending;
7410}
7411
7412static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7413{
7414 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7415 int irq_sync = 0;
1da177e4
LT		 7416
7417 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7418 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7419 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7420 return -EINVAL;
7421
bbe832c0 7422 if (netif_running(dev)) {
1da177e4 7423 tg3_netif_stop(tp);
bbe832c0
MC		 7424 irq_sync = 1;
7425 }
1da177e4 7426
bbe832c0 7427 tg3_full_lock(tp, irq_sync);
1da177e4
LT		 7428
7429 tp->rx_pending = ering->rx_pending;
7430
7431 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7432 tp->rx_pending > 63)
7433 tp->rx_pending = 63;
7434 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7435 tp->tx_pending = ering->tx_pending;
7436
7437 if (netif_running(dev)) {
944d980e 7438 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7439 tg3_init_hw(tp);
7440 tg3_netif_start(tp);
7441 }
7442
f47c11ee 7443 tg3_full_unlock(tp);
1da177e4
LT		 7444
7445 return 0;
7446}
7447
7448static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7449{
7450 struct tg3 *tp = netdev_priv(dev);
7451
7452 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7453 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7454 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7455}
7456
7457static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7458{
7459 struct tg3 *tp = netdev_priv(dev);
bbe832c0 7460 int irq_sync = 0;
1da177e4 7461
bbe832c0 7462 if (netif_running(dev)) {
1da177e4 7463 tg3_netif_stop(tp);
bbe832c0
MC		 7464 irq_sync = 1;
7465 }
1da177e4 7466
bbe832c0 7467 tg3_full_lock(tp, irq_sync);
f47c11ee 7468
1da177e4
LT		 7469 if (epause->autoneg)
7470 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7471 else
7472 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7473 if (epause->rx_pause)
7474 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7475 else
7476 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7477 if (epause->tx_pause)
7478 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7479 else
7480 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7481
7482 if (netif_running(dev)) {
944d980e 7483 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 7484 tg3_init_hw(tp);
7485 tg3_netif_start(tp);
7486 }
f47c11ee
DM		 7487
7488 tg3_full_unlock(tp);
1da177e4
LT		 7489
7490 return 0;
7491}
7492
7493static u32 tg3_get_rx_csum(struct net_device *dev)
7494{
7495 struct tg3 *tp = netdev_priv(dev);
7496 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7497}
7498
7499static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7500{
7501 struct tg3 *tp = netdev_priv(dev);
7502
7503 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7504 if (data != 0)
7505 return -EINVAL;
7506 return 0;
7507 }
7508
f47c11ee 7509 spin_lock_bh(&tp->lock);
1da177e4
LT		 7510 if (data)
7511 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7512 else
7513 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
f47c11ee 7514 spin_unlock_bh(&tp->lock);
1da177e4
LT		 7515
7516 return 0;
7517}
7518
7519static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7520{
7521 struct tg3 *tp = netdev_priv(dev);
7522
7523 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7524 if (data != 0)
7525 return -EINVAL;
7526 return 0;
7527 }
7528
7529 if (data)
7530 dev->features |= NETIF_F_IP_CSUM;
7531 else
7532 dev->features &= ~NETIF_F_IP_CSUM;
7533
7534 return 0;
7535}
7536
7537static int tg3_get_stats_count (struct net_device *dev)
7538{
7539 return TG3_NUM_STATS;
7540}
7541
4cafd3f5
MC		 7542static int tg3_get_test_count (struct net_device *dev)
7543{
7544 return TG3_NUM_TEST;
7545}
7546
1da177e4
LT		 7547static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7548{
7549 switch (stringset) {
7550 case ETH_SS_STATS:
7551 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7552 break;
4cafd3f5
MC		 7553 case ETH_SS_TEST:
7554 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7555 break;
1da177e4
LT		 7556 default:
7557 WARN_ON(1); /* we need a WARN() */
7558 break;
7559 }
7560}
7561
7562static void tg3_get_ethtool_stats (struct net_device *dev,
7563 struct ethtool_stats *estats, u64 *tmp_stats)
7564{
7565 struct tg3 *tp = netdev_priv(dev);
7566 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7567}
7568
566f86ad
MC		 7569#define NVRAM_TEST_SIZE 0x100
7570
7571static int tg3_test_nvram(struct tg3 *tp)
7572{
7573 u32 *buf, csum;
7574 int i, j, err = 0;
7575
7576 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7577 if (buf == NULL)
7578 return -ENOMEM;
7579
7580 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7581 u32 val;
7582
7583 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7584 break;
7585 buf[j] = cpu_to_le32(val);
7586 }
7587 if (i < NVRAM_TEST_SIZE)
7588 goto out;
7589
7590 err = -EIO;
7591 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7592 goto out;
7593
7594 /* Bootstrap checksum at offset 0x10 */
7595 csum = calc_crc((unsigned char *) buf, 0x10);
7596 if(csum != cpu_to_le32(buf[0x10/4]))
7597 goto out;
7598
7599 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7600 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7601 if (csum != cpu_to_le32(buf[0xfc/4]))
7602 goto out;
7603
7604 err = 0;
7605
7606out:
7607 kfree(buf);
7608 return err;
7609}
7610
ca43007a
MC		 7611#define TG3_SERDES_TIMEOUT_SEC 2
7612#define TG3_COPPER_TIMEOUT_SEC 6
7613
7614static int tg3_test_link(struct tg3 *tp)
7615{
7616 int i, max;
7617
7618 if (!netif_running(tp->dev))
7619 return -ENODEV;
7620
7621 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7622 max = TG3_SERDES_TIMEOUT_SEC;
7623 else
7624 max = TG3_COPPER_TIMEOUT_SEC;
7625
7626 for (i = 0; i < max; i++) {
7627 if (netif_carrier_ok(tp->dev))
7628 return 0;
7629
7630 if (msleep_interruptible(1000))
7631 break;
7632 }
7633
7634 return -EIO;
7635}
7636
a71116d1
MC		 7637/* Only test the commonly used registers */
7638static int tg3_test_registers(struct tg3 *tp)
7639{
7640 int i, is_5705;
7641 u32 offset, read_mask, write_mask, val, save_val, read_val;
7642 static struct {
7643 u16 offset;
7644 u16 flags;
7645#define TG3_FL_5705 0x1
7646#define TG3_FL_NOT_5705 0x2
7647#define TG3_FL_NOT_5788 0x4
7648 u32 read_mask;
7649 u32 write_mask;
7650 } reg_tbl[] = {
7651 /* MAC Control Registers */
7652 { MAC_MODE, TG3_FL_NOT_5705,
7653 0x00000000, 0x00ef6f8c },
7654 { MAC_MODE, TG3_FL_5705,
7655 0x00000000, 0x01ef6b8c },
7656 { MAC_STATUS, TG3_FL_NOT_5705,
7657 0x03800107, 0x00000000 },
7658 { MAC_STATUS, TG3_FL_5705,
7659 0x03800100, 0x00000000 },
7660 { MAC_ADDR_0_HIGH, 0x0000,
7661 0x00000000, 0x0000ffff },
7662 { MAC_ADDR_0_LOW, 0x0000,
7663 0x00000000, 0xffffffff },
7664 { MAC_RX_MTU_SIZE, 0x0000,
7665 0x00000000, 0x0000ffff },
7666 { MAC_TX_MODE, 0x0000,
7667 0x00000000, 0x00000070 },
7668 { MAC_TX_LENGTHS, 0x0000,
7669 0x00000000, 0x00003fff },
7670 { MAC_RX_MODE, TG3_FL_NOT_5705,
7671 0x00000000, 0x000007fc },
7672 { MAC_RX_MODE, TG3_FL_5705,
7673 0x00000000, 0x000007dc },
7674 { MAC_HASH_REG_0, 0x0000,
7675 0x00000000, 0xffffffff },
7676 { MAC_HASH_REG_1, 0x0000,
7677 0x00000000, 0xffffffff },
7678 { MAC_HASH_REG_2, 0x0000,
7679 0x00000000, 0xffffffff },
7680 { MAC_HASH_REG_3, 0x0000,
7681 0x00000000, 0xffffffff },
7682
7683 /* Receive Data and Receive BD Initiator Control Registers. */
7684 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7685 0x00000000, 0xffffffff },
7686 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7687 0x00000000, 0xffffffff },
7688 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7689 0x00000000, 0x00000003 },
7690 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7691 0x00000000, 0xffffffff },
7692 { RCVDBDI_STD_BD+0, 0x0000,
7693 0x00000000, 0xffffffff },
7694 { RCVDBDI_STD_BD+4, 0x0000,
7695 0x00000000, 0xffffffff },
7696 { RCVDBDI_STD_BD+8, 0x0000,
7697 0x00000000, 0xffff0002 },
7698 { RCVDBDI_STD_BD+0xc, 0x0000,
7699 0x00000000, 0xffffffff },
7700
7701 /* Receive BD Initiator Control Registers. */
7702 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7703 0x00000000, 0xffffffff },
7704 { RCVBDI_STD_THRESH, TG3_FL_5705,
7705 0x00000000, 0x000003ff },
7706 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7707 0x00000000, 0xffffffff },
7708
7709 /* Host Coalescing Control Registers. */
7710 { HOSTCC_MODE, TG3_FL_NOT_5705,
7711 0x00000000, 0x00000004 },
7712 { HOSTCC_MODE, TG3_FL_5705,
7713 0x00000000, 0x000000f6 },
7714 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7715 0x00000000, 0xffffffff },
7716 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7717 0x00000000, 0x000003ff },
7718 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7719 0x00000000, 0xffffffff },
7720 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7721 0x00000000, 0x000003ff },
7722 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7723 0x00000000, 0xffffffff },
7724 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7725 0x00000000, 0x000000ff },
7726 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7727 0x00000000, 0xffffffff },
7728 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7729 0x00000000, 0x000000ff },
7730 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7731 0x00000000, 0xffffffff },
7732 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7733 0x00000000, 0xffffffff },
7734 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7735 0x00000000, 0xffffffff },
7736 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7737 0x00000000, 0x000000ff },
7738 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7739 0x00000000, 0xffffffff },
7740 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7741 0x00000000, 0x000000ff },
7742 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7743 0x00000000, 0xffffffff },
7744 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7745 0x00000000, 0xffffffff },
7746 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7747 0x00000000, 0xffffffff },
7748 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7749 0x00000000, 0xffffffff },
7750 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7751 0x00000000, 0xffffffff },
7752 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7753 0xffffffff, 0x00000000 },
7754 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7755 0xffffffff, 0x00000000 },
7756
7757 /* Buffer Manager Control Registers. */
7758 { BUFMGR_MB_POOL_ADDR, 0x0000,
7759 0x00000000, 0x007fff80 },
7760 { BUFMGR_MB_POOL_SIZE, 0x0000,
7761 0x00000000, 0x007fffff },
7762 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7763 0x00000000, 0x0000003f },
7764 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7765 0x00000000, 0x000001ff },
7766 { BUFMGR_MB_HIGH_WATER, 0x0000,
7767 0x00000000, 0x000001ff },
7768 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7769 0xffffffff, 0x00000000 },
7770 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7771 0xffffffff, 0x00000000 },
7772
7773 /* Mailbox Registers */
7774 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7775 0x00000000, 0x000001ff },
7776 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7777 0x00000000, 0x000001ff },
7778 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7779 0x00000000, 0x000007ff },
7780 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7781 0x00000000, 0x000001ff },
7782
7783 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7784 };
7785
7786 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7787 is_5705 = 1;
7788 else
7789 is_5705 = 0;
7790
7791 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7792 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7793 continue;
7794
7795 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7796 continue;
7797
7798 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7799 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7800 continue;
7801
7802 offset = (u32) reg_tbl[i].offset;
7803 read_mask = reg_tbl[i].read_mask;
7804 write_mask = reg_tbl[i].write_mask;
7805
7806 /* Save the original register content */
7807 save_val = tr32(offset);
7808
7809 /* Determine the read-only value. */
7810 read_val = save_val & read_mask;
7811
7812 /* Write zero to the register, then make sure the read-only bits
7813 * are not changed and the read/write bits are all zeros.
7814 */
7815 tw32(offset, 0);
7816
7817 val = tr32(offset);
7818
7819 /* Test the read-only and read/write bits. */
7820 if (((val & read_mask) != read_val) || (val & write_mask))
7821 goto out;
7822
7823 /* Write ones to all the bits defined by RdMask and WrMask, then
7824 * make sure the read-only bits are not changed and the
7825 * read/write bits are all ones.
7826 */
7827 tw32(offset, read_mask | write_mask);
7828
7829 val = tr32(offset);
7830
7831 /* Test the read-only bits. */
7832 if ((val & read_mask) != read_val)
7833 goto out;
7834
7835 /* Test the read/write bits. */
7836 if ((val & write_mask) != write_mask)
7837 goto out;
7838
7839 tw32(offset, save_val);
7840 }
7841
7842 return 0;
7843
7844out:
7845 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7846 tw32(offset, save_val);
7847 return -EIO;
7848}
7849
7942e1db
MC		 7850static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7851{
7852 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7853 int i;
7854 u32 j;
7855
7856 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7857 for (j = 0; j < len; j += 4) {
7858 u32 val;
7859
7860 tg3_write_mem(tp, offset + j, test_pattern[i]);
7861 tg3_read_mem(tp, offset + j, &val);
7862 if (val != test_pattern[i])
7863 return -EIO;
7864 }
7865 }
7866 return 0;
7867}
7868
7869static int tg3_test_memory(struct tg3 *tp)
7870{
7871 static struct mem_entry {
7872 u32 offset;
7873 u32 len;
7874 } mem_tbl_570x[] = {
7875 { 0x00000000, 0x01000},
7876 { 0x00002000, 0x1c000},
7877 { 0xffffffff, 0x00000}
7878 }, mem_tbl_5705[] = {
7879 { 0x00000100, 0x0000c},
7880 { 0x00000200, 0x00008},
7881 { 0x00000b50, 0x00400},
7882 { 0x00004000, 0x00800},
7883 { 0x00006000, 0x01000},
7884 { 0x00008000, 0x02000},
7885 { 0x00010000, 0x0e000},
7886 { 0xffffffff, 0x00000}
7887 };
7888 struct mem_entry *mem_tbl;
7889 int err = 0;
7890 int i;
7891
7892 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7893 mem_tbl = mem_tbl_5705;
7894 else
7895 mem_tbl = mem_tbl_570x;
7896
7897 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7898 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7899 mem_tbl[i].len)) != 0)
7900 break;
7901 }
7902
7903 return err;
7904}
7905
c76949a6
MC		 7906static int tg3_test_loopback(struct tg3 *tp)
7907{
7908 u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7909 u32 desc_idx;
7910 struct sk_buff *skb, *rx_skb;
7911 u8 *tx_data;
7912 dma_addr_t map;
7913 int num_pkts, tx_len, rx_len, i, err;
7914 struct tg3_rx_buffer_desc *desc;
7915
7916 if (!netif_running(tp->dev))
7917 return -ENODEV;
7918
7919 err = -EIO;
7920
c76949a6
MC		 7921 tg3_reset_hw(tp);
7922
7923 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7924 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7925 MAC_MODE_PORT_MODE_GMII;
7926 tw32(MAC_MODE, mac_mode);
7927
7928 tx_len = 1514;
7929 skb = dev_alloc_skb(tx_len);
7930 tx_data = skb_put(skb, tx_len);
7931 memcpy(tx_data, tp->dev->dev_addr, 6);
7932 memset(tx_data + 6, 0x0, 8);
7933
7934 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7935
7936 for (i = 14; i < tx_len; i++)
7937 tx_data[i] = (u8) (i & 0xff);
7938
7939 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7940
7941 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7942 HOSTCC_MODE_NOW);
7943
7944 udelay(10);
7945
7946 rx_start_idx = tp->hw_status->idx[0].rx_producer;
7947
7948 send_idx = 0;
7949 num_pkts = 0;
7950
7951 tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7952
7953 send_idx++;
7954 num_pkts++;
7955
7956 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
09ee929c 7957 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
c76949a6
MC		 7958
7959 udelay(10);
7960
7961 for (i = 0; i < 10; i++) {
7962 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7963 HOSTCC_MODE_NOW);
7964
7965 udelay(10);
7966
7967 tx_idx = tp->hw_status->idx[0].tx_consumer;
7968 rx_idx = tp->hw_status->idx[0].rx_producer;
7969 if ((tx_idx == send_idx) &&
7970 (rx_idx == (rx_start_idx + num_pkts)))
7971 break;
7972 }
7973
7974 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7975 dev_kfree_skb(skb);
7976
7977 if (tx_idx != send_idx)
7978 goto out;
7979
7980 if (rx_idx != rx_start_idx + num_pkts)
7981 goto out;
7982
7983 desc = &tp->rx_rcb[rx_start_idx];
7984 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7985 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7986 if (opaque_key != RXD_OPAQUE_RING_STD)
7987 goto out;
7988
7989 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7990 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7991 goto out;
7992
7993 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7994 if (rx_len != tx_len)
7995 goto out;
7996
7997 rx_skb = tp->rx_std_buffers[desc_idx].skb;
7998
7999 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8000 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8001
8002 for (i = 14; i < tx_len; i++) {
8003 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8004 goto out;
8005 }
8006 err = 0;
8007
8008 /* tg3_free_rings will unmap and free the rx_skb */
8009out:
8010 return err;
8011}
8012
4cafd3f5
MC		 8013static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8014 u64 *data)
8015{
566f86ad
MC		 8016 struct tg3 *tp = netdev_priv(dev);
8017
8018 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8019
8020 if (tg3_test_nvram(tp) != 0) {
8021 etest->flags |= ETH_TEST_FL_FAILED;
8022 data[0] = 1;
8023 }
ca43007a
MC		 8024 if (tg3_test_link(tp) != 0) {
8025 etest->flags |= ETH_TEST_FL_FAILED;
8026 data[1] = 1;
8027 }
a71116d1 8028 if (etest->flags & ETH_TEST_FL_OFFLINE) {
bbe832c0
MC		 8029 int irq_sync = 0;
8030
8031 if (netif_running(dev)) {
a71116d1 8032 tg3_netif_stop(tp);
bbe832c0
MC		 8033 irq_sync = 1;
8034 }
a71116d1 8035
bbe832c0 8036 tg3_full_lock(tp, irq_sync);
a71116d1
MC		 8037
8038 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8039 tg3_nvram_lock(tp);
8040 tg3_halt_cpu(tp, RX_CPU_BASE);
8041 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8042 tg3_halt_cpu(tp, TX_CPU_BASE);
8043 tg3_nvram_unlock(tp);
8044
8045 if (tg3_test_registers(tp) != 0) {
8046 etest->flags |= ETH_TEST_FL_FAILED;
8047 data[2] = 1;
8048 }
7942e1db
MC		 8049 if (tg3_test_memory(tp) != 0) {
8050 etest->flags |= ETH_TEST_FL_FAILED;
8051 data[3] = 1;
8052 }
c76949a6
MC		 8053 if (tg3_test_loopback(tp) != 0) {
8054 etest->flags |= ETH_TEST_FL_FAILED;
8055 data[4] = 1;
8056 }
a71116d1 8057
f47c11ee
DM		 8058 tg3_full_unlock(tp);
8059
d4bc3927
MC		 8060 if (tg3_test_interrupt(tp) != 0) {
8061 etest->flags |= ETH_TEST_FL_FAILED;
8062 data[5] = 1;
8063 }
f47c11ee
DM		 8064
8065 tg3_full_lock(tp, 0);
d4bc3927 8066
a71116d1
MC		 8067 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8068 if (netif_running(dev)) {
8069 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8070 tg3_init_hw(tp);
8071 tg3_netif_start(tp);
8072 }
f47c11ee
DM		 8073
8074 tg3_full_unlock(tp);
a71116d1 8075 }
4cafd3f5
MC		 8076}
8077
1da177e4
LT		 8078static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8079{
8080 struct mii_ioctl_data *data = if_mii(ifr);
8081 struct tg3 *tp = netdev_priv(dev);
8082 int err;
8083
8084 switch(cmd) {
8085 case SIOCGMIIPHY:
8086 data->phy_id = PHY_ADDR;
8087
8088 /* fallthru */
8089 case SIOCGMIIREG: {
8090 u32 mii_regval;
8091
8092 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8093 break; /* We have no PHY */
8094
f47c11ee 8095 spin_lock_bh(&tp->lock);
1da177e4 8096 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
f47c11ee 8097 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8098
8099 data->val_out = mii_regval;
8100
8101 return err;
8102 }
8103
8104 case SIOCSMIIREG:
8105 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8106 break; /* We have no PHY */
8107
8108 if (!capable(CAP_NET_ADMIN))
8109 return -EPERM;
8110
f47c11ee 8111 spin_lock_bh(&tp->lock);
1da177e4 8112 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
f47c11ee 8113 spin_unlock_bh(&tp->lock);
1da177e4
LT		 8114
8115 return err;
8116
8117 default:
8118 /* do nothing */
8119 break;
8120 }
8121 return -EOPNOTSUPP;
8122}
8123
8124#if TG3_VLAN_TAG_USED
8125static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8126{
8127 struct tg3 *tp = netdev_priv(dev);
8128
f47c11ee 8129 tg3_full_lock(tp, 0);
1da177e4
LT		 8130
8131 tp->vlgrp = grp;
8132
8133 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8134 __tg3_set_rx_mode(dev);
8135
f47c11ee 8136 tg3_full_unlock(tp);
1da177e4
LT		 8137}
8138
8139static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8140{
8141 struct tg3 *tp = netdev_priv(dev);
8142
f47c11ee 8143 tg3_full_lock(tp, 0);
1da177e4
LT		 8144 if (tp->vlgrp)
8145 tp->vlgrp->vlan_devices[vid] = NULL;
f47c11ee 8146 tg3_full_unlock(tp);
1da177e4
LT		 8147}
8148#endif
8149
15f9850d
DM		 8150static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8151{
8152 struct tg3 *tp = netdev_priv(dev);
8153
8154 memcpy(ec, &tp->coal, sizeof(*ec));
8155 return 0;
8156}
8157
d244c892
MC		 8158static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8159{
8160 struct tg3 *tp = netdev_priv(dev);
8161 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8162 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8163
8164 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8165 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8166 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8167 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8168 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8169 }
8170
8171 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8172 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8173 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8174 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8175 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8176 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8177 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8178 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8179 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8180 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8181 return -EINVAL;
8182
8183 /* No rx interrupts will be generated if both are zero */
8184 if ((ec->rx_coalesce_usecs == 0) &&
8185 (ec->rx_max_coalesced_frames == 0))
8186 return -EINVAL;
8187
8188 /* No tx interrupts will be generated if both are zero */
8189 if ((ec->tx_coalesce_usecs == 0) &&
8190 (ec->tx_max_coalesced_frames == 0))
8191 return -EINVAL;
8192
8193 /* Only copy relevant parameters, ignore all others. */
8194 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8195 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8196 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8197 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8198 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8199 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8200 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8201 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8202 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8203
8204 if (netif_running(dev)) {
8205 tg3_full_lock(tp, 0);
8206 __tg3_set_coalesce(tp, &tp->coal);
8207 tg3_full_unlock(tp);
8208 }
8209 return 0;
8210}
8211
1da177e4
LT		 8212static struct ethtool_ops tg3_ethtool_ops = {
8213 .get_settings = tg3_get_settings,
8214 .set_settings = tg3_set_settings,
8215 .get_drvinfo = tg3_get_drvinfo,
8216 .get_regs_len = tg3_get_regs_len,
8217 .get_regs = tg3_get_regs,
8218 .get_wol = tg3_get_wol,
8219 .set_wol = tg3_set_wol,
8220 .get_msglevel = tg3_get_msglevel,
8221 .set_msglevel = tg3_set_msglevel,
8222 .nway_reset = tg3_nway_reset,
8223 .get_link = ethtool_op_get_link,
8224 .get_eeprom_len = tg3_get_eeprom_len,
8225 .get_eeprom = tg3_get_eeprom,
8226 .set_eeprom = tg3_set_eeprom,
8227 .get_ringparam = tg3_get_ringparam,
8228 .set_ringparam = tg3_set_ringparam,
8229 .get_pauseparam = tg3_get_pauseparam,
8230 .set_pauseparam = tg3_set_pauseparam,
8231 .get_rx_csum = tg3_get_rx_csum,
8232 .set_rx_csum = tg3_set_rx_csum,
8233 .get_tx_csum = ethtool_op_get_tx_csum,
8234 .set_tx_csum = tg3_set_tx_csum,
8235 .get_sg = ethtool_op_get_sg,
8236 .set_sg = ethtool_op_set_sg,
8237#if TG3_TSO_SUPPORT != 0
8238 .get_tso = ethtool_op_get_tso,
8239 .set_tso = tg3_set_tso,
8240#endif
4cafd3f5
MC		 8241 .self_test_count = tg3_get_test_count,
8242 .self_test = tg3_self_test,
1da177e4
LT		 8243 .get_strings = tg3_get_strings,
8244 .get_stats_count = tg3_get_stats_count,
8245 .get_ethtool_stats = tg3_get_ethtool_stats,
15f9850d 8246 .get_coalesce = tg3_get_coalesce,
d244c892 8247 .set_coalesce = tg3_set_coalesce,
1da177e4
LT		 8248};
8249
8250static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8251{
8252 u32 cursize, val;
8253
8254 tp->nvram_size = EEPROM_CHIP_SIZE;
8255
8256 if (tg3_nvram_read(tp, 0, &val) != 0)
8257 return;
8258
8259 if (swab32(val) != TG3_EEPROM_MAGIC)
8260 return;
8261
8262 /*
8263 * Size the chip by reading offsets at increasing powers of two.
8264 * When we encounter our validation signature, we know the addressing
8265 * has wrapped around, and thus have our chip size.
8266 */
8267 cursize = 0x800;
8268
8269 while (cursize < tp->nvram_size) {
8270 if (tg3_nvram_read(tp, cursize, &val) != 0)
8271 return;
8272
8273 if (swab32(val) == TG3_EEPROM_MAGIC)
8274 break;
8275
8276 cursize <<= 1;
8277 }
8278
8279 tp->nvram_size = cursize;
8280}
8281
8282static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8283{
8284 u32 val;
8285
8286 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8287 if (val != 0) {
8288 tp->nvram_size = (val >> 16) * 1024;
8289 return;
8290 }
8291 }
8292 tp->nvram_size = 0x20000;
8293}
8294
8295static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8296{
8297 u32 nvcfg1;
8298
8299 nvcfg1 = tr32(NVRAM_CFG1);
8300 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8301 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8302 }
8303 else {
8304 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8305 tw32(NVRAM_CFG1, nvcfg1);
8306 }
8307
85e94ced 8308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1da177e4
LT		 8309 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8310 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8311 tp->nvram_jedecnum = JEDEC_ATMEL;
8312 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8313 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8314 break;
8315 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8316 tp->nvram_jedecnum = JEDEC_ATMEL;
8317 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8318 break;
8319 case FLASH_VENDOR_ATMEL_EEPROM:
8320 tp->nvram_jedecnum = JEDEC_ATMEL;
8321 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8322 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8323 break;
8324 case FLASH_VENDOR_ST:
8325 tp->nvram_jedecnum = JEDEC_ST;
8326 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8327 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8328 break;
8329 case FLASH_VENDOR_SAIFUN:
8330 tp->nvram_jedecnum = JEDEC_SAIFUN;
8331 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8332 break;
8333 case FLASH_VENDOR_SST_SMALL:
8334 case FLASH_VENDOR_SST_LARGE:
8335 tp->nvram_jedecnum = JEDEC_SST;
8336 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8337 break;
8338 }
8339 }
8340 else {
8341 tp->nvram_jedecnum = JEDEC_ATMEL;
8342 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8343 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8344 }
8345}
8346
361b4ac2
MC		 8347static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8348{
8349 u32 nvcfg1;
8350
8351 nvcfg1 = tr32(NVRAM_CFG1);
8352
e6af301b
MC		 8353 /* NVRAM protection for TPM */
8354 if (nvcfg1 & (1 << 27))
8355 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8356
361b4ac2
MC		 8357 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8358 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8359 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8360 tp->nvram_jedecnum = JEDEC_ATMEL;
8361 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8362 break;
8363 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8364 tp->nvram_jedecnum = JEDEC_ATMEL;
8365 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8366 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8367 break;
8368 case FLASH_5752VENDOR_ST_M45PE10:
8369 case FLASH_5752VENDOR_ST_M45PE20:
8370 case FLASH_5752VENDOR_ST_M45PE40:
8371 tp->nvram_jedecnum = JEDEC_ST;
8372 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8373 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8374 break;
8375 }
8376
8377 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8378 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8379 case FLASH_5752PAGE_SIZE_256:
8380 tp->nvram_pagesize = 256;
8381 break;
8382 case FLASH_5752PAGE_SIZE_512:
8383 tp->nvram_pagesize = 512;
8384 break;
8385 case FLASH_5752PAGE_SIZE_1K:
8386 tp->nvram_pagesize = 1024;
8387 break;
8388 case FLASH_5752PAGE_SIZE_2K:
8389 tp->nvram_pagesize = 2048;
8390 break;
8391 case FLASH_5752PAGE_SIZE_4K:
8392 tp->nvram_pagesize = 4096;
8393 break;
8394 case FLASH_5752PAGE_SIZE_264:
8395 tp->nvram_pagesize = 264;
8396 break;
8397 }
8398 }
8399 else {
8400 /* For eeprom, set pagesize to maximum eeprom size */
8401 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8402
8403 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8404 tw32(NVRAM_CFG1, nvcfg1);
8405 }
8406}
8407
1da177e4
LT		 8408/* Chips other than 5700/5701 use the NVRAM for fetching info. */
8409static void __devinit tg3_nvram_init(struct tg3 *tp)
8410{
8411 int j;
8412
8413 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8414 return;
8415
8416 tw32_f(GRC_EEPROM_ADDR,
8417 (EEPROM_ADDR_FSM_RESET |
8418 (EEPROM_DEFAULT_CLOCK_PERIOD <<
8419 EEPROM_ADDR_CLKPERD_SHIFT)));
8420
8421 /* XXX schedule_timeout() ... */
8422 for (j = 0; j < 100; j++)
8423 udelay(10);
8424
8425 /* Enable seeprom accesses. */
8426 tw32_f(GRC_LOCAL_CTRL,
8427 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8428 udelay(100);
8429
8430 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8431 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8432 tp->tg3_flags |= TG3_FLAG_NVRAM;
8433
e6af301b 8434 tg3_enable_nvram_access(tp);
1da177e4 8435
361b4ac2
MC		 8436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8437 tg3_get_5752_nvram_info(tp);
8438 else
8439 tg3_get_nvram_info(tp);
8440
1da177e4
LT		 8441 tg3_get_nvram_size(tp);
8442
e6af301b 8443 tg3_disable_nvram_access(tp);
1da177e4
LT		 8444
8445 } else {
8446 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8447
8448 tg3_get_eeprom_size(tp);
8449 }
8450}
8451
8452static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8453 u32 offset, u32 *val)
8454{
8455 u32 tmp;
8456 int i;
8457
8458 if (offset > EEPROM_ADDR_ADDR_MASK ||
8459 (offset % 4) != 0)
8460 return -EINVAL;
8461
8462 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8463 EEPROM_ADDR_DEVID_MASK |
8464 EEPROM_ADDR_READ);
8465 tw32(GRC_EEPROM_ADDR,
8466 tmp |
8467 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8468 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8469 EEPROM_ADDR_ADDR_MASK) |
8470 EEPROM_ADDR_READ | EEPROM_ADDR_START);
8471
8472 for (i = 0; i < 10000; i++) {
8473 tmp = tr32(GRC_EEPROM_ADDR);
8474
8475 if (tmp & EEPROM_ADDR_COMPLETE)
8476 break;
8477 udelay(100);
8478 }
8479 if (!(tmp & EEPROM_ADDR_COMPLETE))
8480 return -EBUSY;
8481
8482 *val = tr32(GRC_EEPROM_DATA);
8483 return 0;
8484}
8485
8486#define NVRAM_CMD_TIMEOUT 10000
8487
8488static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8489{
8490 int i;
8491
8492 tw32(NVRAM_CMD, nvram_cmd);
8493 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8494 udelay(10);
8495 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8496 udelay(10);
8497 break;
8498 }
8499 }
8500 if (i == NVRAM_CMD_TIMEOUT) {
8501 return -EBUSY;
8502 }
8503 return 0;
8504}
8505
8506static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8507{
8508 int ret;
8509
8510 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8511 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8512 return -EINVAL;
8513 }
8514
8515 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8516 return tg3_nvram_read_using_eeprom(tp, offset, val);
8517
8518 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8519 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8520 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8521
8522 offset = ((offset / tp->nvram_pagesize) <<
8523 ATMEL_AT45DB0X1B_PAGE_POS) +
8524 (offset % tp->nvram_pagesize);
8525 }
8526
8527 if (offset > NVRAM_ADDR_MSK)
8528 return -EINVAL;
8529
8530 tg3_nvram_lock(tp);
8531
e6af301b 8532 tg3_enable_nvram_access(tp);
1da177e4
LT		 8533
8534 tw32(NVRAM_ADDR, offset);
8535 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8536 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8537
8538 if (ret == 0)
8539 *val = swab32(tr32(NVRAM_RDDATA));
8540
8541 tg3_nvram_unlock(tp);
8542
e6af301b 8543 tg3_disable_nvram_access(tp);
1da177e4
LT		 8544
8545 return ret;
8546}
8547
8548static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8549 u32 offset, u32 len, u8 *buf)
8550{
8551 int i, j, rc = 0;
8552 u32 val;
8553
8554 for (i = 0; i < len; i += 4) {
8555 u32 addr, data;
8556
8557 addr = offset + i;
8558
8559 memcpy(&data, buf + i, 4);
8560
8561 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8562
8563 val = tr32(GRC_EEPROM_ADDR);
8564 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8565
8566 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8567 EEPROM_ADDR_READ);
8568 tw32(GRC_EEPROM_ADDR, val |
8569 (0 << EEPROM_ADDR_DEVID_SHIFT) |
8570 (addr & EEPROM_ADDR_ADDR_MASK) |
8571 EEPROM_ADDR_START |
8572 EEPROM_ADDR_WRITE);
8573
8574 for (j = 0; j < 10000; j++) {
8575 val = tr32(GRC_EEPROM_ADDR);
8576
8577 if (val & EEPROM_ADDR_COMPLETE)
8578 break;
8579 udelay(100);
8580 }
8581 if (!(val & EEPROM_ADDR_COMPLETE)) {
8582 rc = -EBUSY;
8583 break;
8584 }
8585 }
8586
8587 return rc;
8588}
8589
8590/* offset and length are dword aligned */
8591static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8592 u8 *buf)
8593{
8594 int ret = 0;
8595 u32 pagesize = tp->nvram_pagesize;
8596 u32 pagemask = pagesize - 1;
8597 u32 nvram_cmd;
8598 u8 *tmp;
8599
8600 tmp = kmalloc(pagesize, GFP_KERNEL);
8601 if (tmp == NULL)
8602 return -ENOMEM;
8603
8604 while (len) {
8605 int j;
e6af301b 8606 u32 phy_addr, page_off, size;
1da177e4
LT		 8607
8608 phy_addr = offset & ~pagemask;
8609
8610 for (j = 0; j < pagesize; j += 4) {
8611 if ((ret = tg3_nvram_read(tp, phy_addr + j,
8612 (u32 *) (tmp + j))))
8613 break;
8614 }
8615 if (ret)
8616 break;
8617
8618 page_off = offset & pagemask;
8619 size = pagesize;
8620 if (len < size)
8621 size = len;
8622
8623 len -= size;
8624
8625 memcpy(tmp + page_off, buf, size);
8626
8627 offset = offset + (pagesize - page_off);
8628
e6af301b 8629 tg3_enable_nvram_access(tp);
1da177e4
LT		 8630
8631 /*
8632 * Before we can erase the flash page, we need
8633 * to issue a special "write enable" command.
8634 */
8635 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8636
8637 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8638 break;
8639
8640 /* Erase the target page */
8641 tw32(NVRAM_ADDR, phy_addr);
8642
8643 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8644 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8645
8646 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8647 break;
8648
8649 /* Issue another write enable to start the write. */
8650 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8651
8652 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8653 break;
8654
8655 for (j = 0; j < pagesize; j += 4) {
8656 u32 data;
8657
8658 data = *((u32 *) (tmp + j));
8659 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8660
8661 tw32(NVRAM_ADDR, phy_addr + j);
8662
8663 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8664 NVRAM_CMD_WR;
8665
8666 if (j == 0)
8667 nvram_cmd |= NVRAM_CMD_FIRST;
8668 else if (j == (pagesize - 4))
8669 nvram_cmd |= NVRAM_CMD_LAST;
8670
8671 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8672 break;
8673 }
8674 if (ret)
8675 break;
8676 }
8677
8678 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8679 tg3_nvram_exec_cmd(tp, nvram_cmd);
8680
8681 kfree(tmp);
8682
8683 return ret;
8684}
8685
8686/* offset and length are dword aligned */
8687static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8688 u8 *buf)
8689{
8690 int i, ret = 0;
8691
8692 for (i = 0; i < len; i += 4, offset += 4) {
8693 u32 data, page_off, phy_addr, nvram_cmd;
8694
8695 memcpy(&data, buf + i, 4);
8696 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8697
8698 page_off = offset % tp->nvram_pagesize;
8699
8700 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8701 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8702
8703 phy_addr = ((offset / tp->nvram_pagesize) <<
8704 ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8705 }
8706 else {
8707 phy_addr = offset;
8708 }
8709
8710 tw32(NVRAM_ADDR, phy_addr);
8711
8712 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8713
8714 if ((page_off == 0) || (i == 0))
8715 nvram_cmd |= NVRAM_CMD_FIRST;
8716 else if (page_off == (tp->nvram_pagesize - 4))
8717 nvram_cmd |= NVRAM_CMD_LAST;
8718
8719 if (i == (len - 4))
8720 nvram_cmd |= NVRAM_CMD_LAST;
8721
8722 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8723 (nvram_cmd & NVRAM_CMD_FIRST)) {
8724
8725 if ((ret = tg3_nvram_exec_cmd(tp,
8726 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8727 NVRAM_CMD_DONE)))
8728
8729 break;
8730 }
8731 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8732 /* We always do complete word writes to eeprom. */
8733 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8734 }
8735
8736 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8737 break;
8738 }
8739 return ret;
8740}
8741
8742/* offset and length are dword aligned */
8743static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8744{
8745 int ret;
8746
8747 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8748 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8749 return -EINVAL;
8750 }
8751
8752 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34
MC		 8753 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8754 ~GRC_LCLCTRL_GPIO_OUTPUT1);
1da177e4
LT		 8755 udelay(40);
8756 }
8757
8758 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8759 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8760 }
8761 else {
8762 u32 grc_mode;
8763
8764 tg3_nvram_lock(tp);
8765
e6af301b
MC		 8766 tg3_enable_nvram_access(tp);
8767 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8768 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
1da177e4 8769 tw32(NVRAM_WRITE1, 0x406);
1da177e4
LT		 8770
8771 grc_mode = tr32(GRC_MODE);
8772 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8773
8774 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8775 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8776
8777 ret = tg3_nvram_write_block_buffered(tp, offset, len,
8778 buf);
8779 }
8780 else {
8781 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8782 buf);
8783 }
8784
8785 grc_mode = tr32(GRC_MODE);
8786 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8787
e6af301b 8788 tg3_disable_nvram_access(tp);
1da177e4
LT		 8789 tg3_nvram_unlock(tp);
8790 }
8791
8792 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
314fba34 8793 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1da177e4
LT		 8794 udelay(40);
8795 }
8796
8797 return ret;
8798}
8799
8800struct subsys_tbl_ent {
8801 u16 subsys_vendor, subsys_devid;
8802 u32 phy_id;
8803};
8804
8805static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8806 /* Broadcom boards. */
8807 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8808 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8809 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8810 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
8811 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8812 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8813 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
8814 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8815 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8816 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8817 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8818
8819 /* 3com boards. */
8820 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8821 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8822 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
8823 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8824 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8825
8826 /* DELL boards. */
8827 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8828 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8829 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8830 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8831
8832 /* Compaq boards. */
8833 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8834 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8835 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
8836 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8837 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8838
8839 /* IBM boards. */
8840 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8841};
8842
8843static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8844{
8845 int i;
8846
8847 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8848 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8849 tp->pdev->subsystem_vendor) &&
8850 (subsys_id_to_phy_id[i].subsys_devid ==
8851 tp->pdev->subsystem_device))
8852 return &subsys_id_to_phy_id[i];
8853 }
8854 return NULL;
8855}
8856
7d0c41ef
MC		 8857/* Since this function may be called in D3-hot power state during
8858 * tg3_init_one(), only config cycles are allowed.
8859 */
8860static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
1da177e4 8861{
1da177e4 8862 u32 val;
7d0c41ef
MC		 8863
8864 /* Make sure register accesses (indirect or otherwise)
8865 * will function correctly.
8866 */
8867 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8868 tp->misc_host_ctrl);
1da177e4
LT		 8869
8870 tp->phy_id = PHY_ID_INVALID;
7d0c41ef
MC		 8871 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8872
1da177e4
LT		 8873 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8874 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8875 u32 nic_cfg, led_cfg;
7d0c41ef
MC		 8876 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8877 int eeprom_phy_serdes = 0;
1da177e4
LT		 8878
8879 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8880 tp->nic_sram_data_cfg = nic_cfg;
8881
8882 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8883 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8884 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8885 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8886 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8887 (ver > 0) && (ver < 0x100))
8888 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8889
1da177e4
LT		 8890 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8891 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8892 eeprom_phy_serdes = 1;
8893
8894 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8895 if (nic_phy_id != 0) {
8896 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8897 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8898
8899 eeprom_phy_id = (id1 >> 16) << 10;
8900 eeprom_phy_id |= (id2 & 0xfc00) << 16;
8901 eeprom_phy_id |= (id2 & 0x03ff) << 0;
8902 } else
8903 eeprom_phy_id = 0;
8904
7d0c41ef 8905 tp->phy_id = eeprom_phy_id;
747e8f8b
MC		 8906 if (eeprom_phy_serdes) {
8907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8908 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
8909 else
8910 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8911 }
7d0c41ef 8912
cbf46853 8913 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8914 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8915 SHASTA_EXT_LED_MODE_MASK);
cbf46853 8916 else
1da177e4
LT		 8917 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8918
8919 switch (led_cfg) {
8920 default:
8921 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8922 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8923 break;
8924
8925 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8926 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8927 break;
8928
8929 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8930 tp->led_ctrl = LED_CTRL_MODE_MAC;
9ba27794
MC		 8931
8932 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8933 * read on some older 5700/5701 bootcode.
8934 */
8935 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8936 ASIC_REV_5700 ||
8937 GET_ASIC_REV(tp->pci_chip_rev_id) ==
8938 ASIC_REV_5701)
8939 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8940
1da177e4
LT		 8941 break;
8942
8943 case SHASTA_EXT_LED_SHARED:
8944 tp->led_ctrl = LED_CTRL_MODE_SHARED;
8945 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8946 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8947 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8948 LED_CTRL_MODE_PHY_2);
8949 break;
8950
8951 case SHASTA_EXT_LED_MAC:
8952 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8953 break;
8954
8955 case SHASTA_EXT_LED_COMBO:
8956 tp->led_ctrl = LED_CTRL_MODE_COMBO;
8957 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8958 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8959 LED_CTRL_MODE_PHY_2);
8960 break;
8961
8962 };
8963
8964 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8966 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8967 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8968
8969 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8970 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8971 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8972 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8973
8974 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8975 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
cbf46853 8976 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 8977 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8978 }
8979 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8980 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8981
8982 if (cfg2 & (1 << 17))
8983 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8984
8985 /* serdes signal pre-emphasis in register 0x590 set by */
8986 /* bootcode if bit 18 is set */
8987 if (cfg2 & (1 << 18))
8988 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8989 }
7d0c41ef
MC		 8990}
8991
8992static int __devinit tg3_phy_probe(struct tg3 *tp)
8993{
8994 u32 hw_phy_id_1, hw_phy_id_2;
8995 u32 hw_phy_id, hw_phy_id_masked;
8996 int err;
1da177e4
LT		 8997
8998 /* Reading the PHY ID register can conflict with ASF
8999 * firwmare access to the PHY hardware.
9000 */
9001 err = 0;
9002 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9003 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9004 } else {
9005 /* Now read the physical PHY_ID from the chip and verify
9006 * that it is sane. If it doesn't look good, we fall back
9007 * to either the hard-coded table based PHY_ID and failing
9008 * that the value found in the eeprom area.
9009 */
9010 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9011 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9012
9013 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
9014 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9015 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
9016
9017 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9018 }
9019
9020 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9021 tp->phy_id = hw_phy_id;
9022 if (hw_phy_id_masked == PHY_ID_BCM8002)
9023 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
da6b2d01
MC		 9024 else
9025 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
1da177e4 9026 } else {
7d0c41ef
MC		 9027 if (tp->phy_id != PHY_ID_INVALID) {
9028 /* Do nothing, phy ID already set up in
9029 * tg3_get_eeprom_hw_cfg().
9030 */
1da177e4
LT		 9031 } else {
9032 struct subsys_tbl_ent *p;
9033
9034 /* No eeprom signature? Try the hardcoded
9035 * subsys device table.
9036 */
9037 p = lookup_by_subsys(tp);
9038 if (!p)
9039 return -ENODEV;
9040
9041 tp->phy_id = p->phy_id;
9042 if (!tp->phy_id ||
9043 tp->phy_id == PHY_ID_BCM8002)
9044 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9045 }
9046 }
9047
747e8f8b 9048 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
1da177e4
LT		 9049 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9050 u32 bmsr, adv_reg, tg3_ctrl;
9051
9052 tg3_readphy(tp, MII_BMSR, &bmsr);
9053 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9054 (bmsr & BMSR_LSTATUS))
9055 goto skip_phy_reset;
9056
9057 err = tg3_phy_reset(tp);
9058 if (err)
9059 return err;
9060
9061 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9062 ADVERTISE_100HALF | ADVERTISE_100FULL |
9063 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9064 tg3_ctrl = 0;
9065 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9066 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9067 MII_TG3_CTRL_ADV_1000_FULL);
9068 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9069 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9070 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9071 MII_TG3_CTRL_ENABLE_AS_MASTER);
9072 }
9073
9074 if (!tg3_copper_is_advertising_all(tp)) {
9075 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9076
9077 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9078 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9079
9080 tg3_writephy(tp, MII_BMCR,
9081 BMCR_ANENABLE | BMCR_ANRESTART);
9082 }
9083 tg3_phy_set_wirespeed(tp);
9084
9085 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9086 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9087 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9088 }
9089
9090skip_phy_reset:
9091 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9092 err = tg3_init_5401phy_dsp(tp);
9093 if (err)
9094 return err;
9095 }
9096
9097 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9098 err = tg3_init_5401phy_dsp(tp);
9099 }
9100
747e8f8b 9101 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1da177e4
LT		 9102 tp->link_config.advertising =
9103 (ADVERTISED_1000baseT_Half |
9104 ADVERTISED_1000baseT_Full |
9105 ADVERTISED_Autoneg |
9106 ADVERTISED_FIBRE);
9107 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9108 tp->link_config.advertising &=
9109 ~(ADVERTISED_1000baseT_Half |
9110 ADVERTISED_1000baseT_Full);
9111
9112 return err;
9113}
9114
9115static void __devinit tg3_read_partno(struct tg3 *tp)
9116{
9117 unsigned char vpd_data[256];
9118 int i;
9119
9120 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9121 /* Sun decided not to put the necessary bits in the
9122 * NVRAM of their onboard tg3 parts :(
9123 */
9124 strcpy(tp->board_part_number, "Sun 570X");
9125 return;
9126 }
9127
9128 for (i = 0; i < 256; i += 4) {
9129 u32 tmp;
9130
9131 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9132 goto out_not_found;
9133
9134 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
9135 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
9136 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9137 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9138 }
9139
9140 /* Now parse and find the part number. */
9141 for (i = 0; i < 256; ) {
9142 unsigned char val = vpd_data[i];
9143 int block_end;
9144
9145 if (val == 0x82 || val == 0x91) {
9146 i = (i + 3 +
9147 (vpd_data[i + 1] +
9148 (vpd_data[i + 2] << 8)));
9149 continue;
9150 }
9151
9152 if (val != 0x90)
9153 goto out_not_found;
9154
9155 block_end = (i + 3 +
9156 (vpd_data[i + 1] +
9157 (vpd_data[i + 2] << 8)));
9158 i += 3;
9159 while (i < block_end) {
9160 if (vpd_data[i + 0] == 'P' &&
9161 vpd_data[i + 1] == 'N') {
9162 int partno_len = vpd_data[i + 2];
9163
9164 if (partno_len > 24)
9165 goto out_not_found;
9166
9167 memcpy(tp->board_part_number,
9168 &vpd_data[i + 3],
9169 partno_len);
9170
9171 /* Success. */
9172 return;
9173 }
9174 }
9175
9176 /* Part number not found. */
9177 goto out_not_found;
9178 }
9179
9180out_not_found:
9181 strcpy(tp->board_part_number, "none");
9182}
9183
9184#ifdef CONFIG_SPARC64
9185static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9186{
9187 struct pci_dev *pdev = tp->pdev;
9188 struct pcidev_cookie *pcp = pdev->sysdata;
9189
9190 if (pcp != NULL) {
9191 int node = pcp->prom_node;
9192 u32 venid;
9193 int err;
9194
9195 err = prom_getproperty(node, "subsystem-vendor-id",
9196 (char *) &venid, sizeof(venid));
9197 if (err == 0 || err == -1)
9198 return 0;
9199 if (venid == PCI_VENDOR_ID_SUN)
9200 return 1;
9201 }
9202 return 0;
9203}
9204#endif
9205
9206static int __devinit tg3_get_invariants(struct tg3 *tp)
9207{
9208 static struct pci_device_id write_reorder_chipsets[] = {
1da177e4
LT		 9209 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9210 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9211 { },
9212 };
9213 u32 misc_ctrl_reg;
9214 u32 cacheline_sz_reg;
9215 u32 pci_state_reg, grc_misc_cfg;
9216 u32 val;
9217 u16 pci_cmd;
9218 int err;
9219
9220#ifdef CONFIG_SPARC64
9221 if (tg3_is_sun_570X(tp))
9222 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9223#endif
9224
6892914f 9225 /* If we have an AMD 762 chipset, write
1da177e4
LT		 9226 * reordering to the mailbox registers done by the host
9227 * controller can cause major troubles. We read back from
9228 * every mailbox register write to force the writes to be
9229 * posted to the chip in order.
9230 */
9231 if (pci_dev_present(write_reorder_chipsets))
9232 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9233
9234 /* Force memory write invalidate off. If we leave it on,
9235 * then on 5700_BX chips we have to enable a workaround.
9236 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9237 * to match the cacheline size. The Broadcom driver have this
9238 * workaround but turns MWI off all the times so never uses
9239 * it. This seems to suggest that the workaround is insufficient.
9240 */
9241 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9242 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9243 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9244
9245 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9246 * has the register indirect write enable bit set before
9247 * we try to access any of the MMIO registers. It is also
9248 * critical that the PCI-X hw workaround situation is decided
9249 * before that as well.
9250 */
9251 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9252 &misc_ctrl_reg);
9253
9254 tp->pci_chip_rev_id = (misc_ctrl_reg >>
9255 MISC_HOST_CTRL_CHIPREV_SHIFT);
9256
ff645bec
MC		 9257 /* Wrong chip ID in 5752 A0. This code can be removed later
9258 * as A0 is not in production.
9259 */
9260 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9261 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9262
6892914f
MC		 9263 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9264 * we need to disable memory and use config. cycles
9265 * only to access all registers. The 5702/03 chips
9266 * can mistakenly decode the special cycles from the
9267 * ICH chipsets as memory write cycles, causing corruption
9268 * of register and memory space. Only certain ICH bridges
9269 * will drive special cycles with non-zero data during the
9270 * address phase which can fall within the 5703's address
9271 * range. This is not an ICH bug as the PCI spec allows
9272 * non-zero address during special cycles. However, only
9273 * these ICH bridges are known to drive non-zero addresses
9274 * during special cycles.
9275 *
9276 * Since special cycles do not cross PCI bridges, we only
9277 * enable this workaround if the 5703 is on the secondary
9278 * bus of these ICH bridges.
9279 */
9280 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9281 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9282 static struct tg3_dev_id {
9283 u32 vendor;
9284 u32 device;
9285 u32 rev;
9286 } ich_chipsets[] = {
9287 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9288 PCI_ANY_ID },
9289 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9290 PCI_ANY_ID },
9291 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9292 0xa },
9293 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9294 PCI_ANY_ID },
9295 { },
9296 };
9297 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9298 struct pci_dev *bridge = NULL;
9299
9300 while (pci_id->vendor != 0) {
9301 bridge = pci_get_device(pci_id->vendor, pci_id->device,
9302 bridge);
9303 if (!bridge) {
9304 pci_id++;
9305 continue;
9306 }
9307 if (pci_id->rev != PCI_ANY_ID) {
9308 u8 rev;
9309
9310 pci_read_config_byte(bridge, PCI_REVISION_ID,
9311 &rev);
9312 if (rev > pci_id->rev)
9313 continue;
9314 }
9315 if (bridge->subordinate &&
9316 (bridge->subordinate->number ==
9317 tp->pdev->bus->number)) {
9318
9319 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9320 pci_dev_put(bridge);
9321 break;
9322 }
9323 }
9324 }
9325
4cf78e4f
MC		 9326 /* Find msi capability. */
9327 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9328 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9329
1da177e4
LT		 9330 /* Initialize misc host control in PCI block. */
9331 tp->misc_host_ctrl |= (misc_ctrl_reg &
9332 MISC_HOST_CTRL_CHIPREV);
9333 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9334 tp->misc_host_ctrl);
9335
9336 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9337 &cacheline_sz_reg);
9338
9339 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
9340 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
9341 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
9342 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
9343
6708e5cc 9344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
4cf78e4f
MC		 9345 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
6708e5cc
JL		 9347 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9348
1b440c56
JL		 9349 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9350 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9351 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9352
bb7064dc 9353 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
1da177e4
LT		 9354 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9355
0f893dc6
MC		 9356 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9357 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9358 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9359 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9360
1da177e4
LT		 9361 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9362 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9363
9364 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9365 tp->pci_lat_timer < 64) {
9366 tp->pci_lat_timer = 64;
9367
9368 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
9369 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
9370 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
9371 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
9372
9373 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9374 cacheline_sz_reg);
9375 }
9376
9377 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9378 &pci_state_reg);
9379
9380 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9381 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9382
9383 /* If this is a 5700 BX chipset, and we are in PCI-X
9384 * mode, enable register write workaround.
9385 *
9386 * The workaround is to use indirect register accesses
9387 * for all chip writes not to mailbox registers.
9388 */
9389 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9390 u32 pm_reg;
9391 u16 pci_cmd;
9392
9393 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9394
9395 /* The chip can have it's power management PCI config
9396 * space registers clobbered due to this bug.
9397 * So explicitly force the chip into D0 here.
9398 */
9399 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9400 &pm_reg);
9401 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9402 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9403 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9404 pm_reg);
9405
9406 /* Also, force SERR#/PERR# in PCI command. */
9407 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9408 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9409 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9410 }
9411 }
9412
9413 /* Back to back register writes can cause problems on this chip,
9414 * the workaround is to read back all reg writes except those to
9415 * mailbox regs. See tg3_write_indirect_reg32().
9416 *
9417 * PCI Express 5750_A0 rev chips need this workaround too.
9418 */
9419 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9420 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9421 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9422 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9423
9424 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9425 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9426 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9427 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9428
9429 /* Chip-specific fixup from Broadcom driver */
9430 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9431 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9432 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9433 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9434 }
9435
1ee582d8 9436 /* Default fast path register access methods */
20094930 9437 tp->read32 = tg3_read32;
1ee582d8 9438 tp->write32 = tg3_write32;
09ee929c 9439 tp->read32_mbox = tg3_read32;
20094930 9440 tp->write32_mbox = tg3_write32;
1ee582d8
MC		 9441 tp->write32_tx_mbox = tg3_write32;
9442 tp->write32_rx_mbox = tg3_write32;
9443
9444 /* Various workaround register access methods */
9445 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9446 tp->write32 = tg3_write_indirect_reg32;
9447 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9448 tp->write32 = tg3_write_flush_reg32;
9449
9450 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9451 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9452 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9453 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9454 tp->write32_rx_mbox = tg3_write_flush_reg32;
9455 }
20094930 9456
6892914f
MC		 9457 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9458 tp->read32 = tg3_read_indirect_reg32;
9459 tp->write32 = tg3_write_indirect_reg32;
9460 tp->read32_mbox = tg3_read_indirect_mbox;
9461 tp->write32_mbox = tg3_write_indirect_mbox;
9462 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9463 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9464
9465 iounmap(tp->regs);
9466 tp->regs = 0;
9467
9468 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9469 pci_cmd &= ~PCI_COMMAND_MEMORY;
9470 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9471 }
9472
7d0c41ef
MC		 9473 /* Get eeprom hw config before calling tg3_set_power_state().
9474 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9475 * determined before calling tg3_set_power_state() so that
9476 * we know whether or not to switch out of Vaux power.
9477 * When the flag is set, it means that GPIO1 is used for eeprom
9478 * write protect and also implies that it is a LOM where GPIOs
9479 * are not used to switch power.
9480 */
9481 tg3_get_eeprom_hw_cfg(tp);
9482
314fba34
MC		 9483 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9484 * GPIO1 driven high will bring 5700's external PHY out of reset.
9485 * It is also used as eeprom write protect on LOMs.
9486 */
9487 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9488 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9489 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9490 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9491 GRC_LCLCTRL_GPIO_OUTPUT1);
3e7d83bc
MC		 9492 /* Unused GPIO3 must be driven as output on 5752 because there
9493 * are no pull-up resistors on unused GPIO pins.
9494 */
9495 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9496 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
314fba34 9497
1da177e4
LT		 9498 /* Force the chip into D0. */
9499 err = tg3_set_power_state(tp, 0);
9500 if (err) {
9501 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9502 pci_name(tp->pdev));
9503 return err;
9504 }
9505
9506 /* 5700 B0 chips do not support checksumming correctly due
9507 * to hardware bugs.
9508 */
9509 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9510 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9511
9512 /* Pseudo-header checksum is done by hardware logic and not
9513 * the offload processers, so make the chip do the pseudo-
9514 * header checksums on receive. For transmit it is more
9515 * convenient to do the pseudo-header checksum in software
9516 * as Linux does that on transmit for us in all cases.
9517 */
9518 tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9519 tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9520
9521 /* Derive initial jumbo mode from MTU assigned in
9522 * ether_setup() via the alloc_etherdev() call
9523 */
0f893dc6
MC		 9524 if (tp->dev->mtu > ETH_DATA_LEN &&
9525 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780)
9526 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
1da177e4
LT		 9527
9528 /* Determine WakeOnLan speed to use. */
9529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9530 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9531 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9532 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9533 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9534 } else {
9535 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9536 }
9537
9538 /* A few boards don't want Ethernet@WireSpeed phy feature */
9539 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9540 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9541 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
747e8f8b
MC		 9542 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9543 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1da177e4
LT		 9544 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9545
9546 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9547 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9548 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9549 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9550 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9551
bb7064dc 9552 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
1da177e4
LT		 9553 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9554
1da177e4 9555 tp->coalesce_mode = 0;
1da177e4
LT		 9556 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9557 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9558 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9559
9560 /* Initialize MAC MI mode, polling disabled. */
9561 tw32_f(MAC_MI_MODE, tp->mi_mode);
9562 udelay(80);
9563
9564 /* Initialize data/descriptor byte/word swapping. */
9565 val = tr32(GRC_MODE);
9566 val &= GRC_MODE_HOST_STACKUP;
9567 tw32(GRC_MODE, val | tp->grc_mode);
9568
9569 tg3_switch_clocks(tp);
9570
9571 /* Clear this out for sanity. */
9572 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9573
9574 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9575 &pci_state_reg);
9576 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9577 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9578 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9579
9580 if (chiprevid == CHIPREV_ID_5701_A0 ||
9581 chiprevid == CHIPREV_ID_5701_B0 ||
9582 chiprevid == CHIPREV_ID_5701_B2 ||
9583 chiprevid == CHIPREV_ID_5701_B5) {
9584 void __iomem *sram_base;
9585
9586 /* Write some dummy words into the SRAM status block
9587 * area, see if it reads back correctly. If the return
9588 * value is bad, force enable the PCIX workaround.
9589 */
9590 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9591
9592 writel(0x00000000, sram_base);
9593 writel(0x00000000, sram_base + 4);
9594 writel(0xffffffff, sram_base + 4);
9595 if (readl(sram_base) != 0x00000000)
9596 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9597 }
9598 }
9599
9600 udelay(50);
9601 tg3_nvram_init(tp);
9602
9603 grc_misc_cfg = tr32(GRC_MISC_CFG);
9604 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9605
9606 /* Broadcom's driver says that CIOBE multisplit has a bug */
9607#if 0
9608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9609 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9610 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9611 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9612 }
9613#endif
9614 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9615 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9616 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9617 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9618
fac9b83e
DM		 9619 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9620 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9621 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9622 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9623 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9624 HOSTCC_MODE_CLRTICK_TXBD);
9625
9626 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9627 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9628 tp->misc_host_ctrl);
9629 }
9630
1da177e4
LT		 9631 /* these are limited to 10/100 only */
9632 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9633 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9634 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9635 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9636 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9637 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9638 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9639 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9640 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9641 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9642 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9643
9644 err = tg3_phy_probe(tp);
9645 if (err) {
9646 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9647 pci_name(tp->pdev), err);
9648 /* ... but do not return immediately ... */
9649 }
9650
9651 tg3_read_partno(tp);
9652
9653 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9654 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9655 } else {
9656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9657 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9658 else
9659 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9660 }
9661
9662 /* 5700 {AX,BX} chips have a broken status block link
9663 * change bit implementation, so we must use the
9664 * status register in those cases.
9665 */
9666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9667 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9668 else
9669 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9670
9671 /* The led_ctrl is set during tg3_phy_probe, here we might
9672 * have to force the link status polling mechanism based
9673 * upon subsystem IDs.
9674 */
9675 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9676 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9677 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9678 TG3_FLAG_USE_LINKCHG_REG);
9679 }
9680
9681 /* For all SERDES we poll the MAC status register. */
9682 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9683 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9684 else
9685 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9686
9687 /* 5700 BX chips need to have their TX producer index mailboxes
9688 * written twice to workaround a bug.
9689 */
9690 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9691 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9692 else
9693 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9694
9695 /* It seems all chips can get confused if TX buffers
9696 * straddle the 4GB address boundary in some cases.
9697 */
9698 tp->dev->hard_start_xmit = tg3_start_xmit;
9699
9700 tp->rx_offset = 2;
9701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9702 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9703 tp->rx_offset = 0;
9704
9705 /* By default, disable wake-on-lan. User can change this
9706 * using ETHTOOL_SWOL.
9707 */
9708 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9709
9710 return err;
9711}
9712
9713#ifdef CONFIG_SPARC64
9714static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9715{
9716 struct net_device *dev = tp->dev;
9717 struct pci_dev *pdev = tp->pdev;
9718 struct pcidev_cookie *pcp = pdev->sysdata;
9719
9720 if (pcp != NULL) {
9721 int node = pcp->prom_node;
9722
9723 if (prom_getproplen(node, "local-mac-address") == 6) {
9724 prom_getproperty(node, "local-mac-address",
9725 dev->dev_addr, 6);
9726 return 0;
9727 }
9728 }
9729 return -ENODEV;
9730}
9731
9732static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9733{
9734 struct net_device *dev = tp->dev;
9735
9736 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9737 return 0;
9738}
9739#endif
9740
9741static int __devinit tg3_get_device_address(struct tg3 *tp)
9742{
9743 struct net_device *dev = tp->dev;
9744 u32 hi, lo, mac_offset;
9745
9746#ifdef CONFIG_SPARC64
9747 if (!tg3_get_macaddr_sparc(tp))
9748 return 0;
9749#endif
9750
9751 mac_offset = 0x7c;
4cf78e4f
MC		 9752 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9753 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1da177e4
LT		 9755 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9756 mac_offset = 0xcc;
9757 if (tg3_nvram_lock(tp))
9758 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9759 else
9760 tg3_nvram_unlock(tp);
9761 }
9762
9763 /* First try to get it from MAC address mailbox. */
9764 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9765 if ((hi >> 16) == 0x484b) {
9766 dev->dev_addr[0] = (hi >> 8) & 0xff;
9767 dev->dev_addr[1] = (hi >> 0) & 0xff;
9768
9769 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9770 dev->dev_addr[2] = (lo >> 24) & 0xff;
9771 dev->dev_addr[3] = (lo >> 16) & 0xff;
9772 dev->dev_addr[4] = (lo >> 8) & 0xff;
9773 dev->dev_addr[5] = (lo >> 0) & 0xff;
9774 }
9775 /* Next, try NVRAM. */
9776 else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9777 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9778 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9779 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9780 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9781 dev->dev_addr[2] = ((lo >> 0) & 0xff);
9782 dev->dev_addr[3] = ((lo >> 8) & 0xff);
9783 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9784 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9785 }
9786 /* Finally just fetch it out of the MAC control regs. */
9787 else {
9788 hi = tr32(MAC_ADDR_0_HIGH);
9789 lo = tr32(MAC_ADDR_0_LOW);
9790
9791 dev->dev_addr[5] = lo & 0xff;
9792 dev->dev_addr[4] = (lo >> 8) & 0xff;
9793 dev->dev_addr[3] = (lo >> 16) & 0xff;
9794 dev->dev_addr[2] = (lo >> 24) & 0xff;
9795 dev->dev_addr[1] = hi & 0xff;
9796 dev->dev_addr[0] = (hi >> 8) & 0xff;
9797 }
9798
9799 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9800#ifdef CONFIG_SPARC64
9801 if (!tg3_get_default_macaddr_sparc(tp))
9802 return 0;
9803#endif
9804 return -EINVAL;
9805 }
9806 return 0;
9807}
9808
59e6b434
DM		 9809#define BOUNDARY_SINGLE_CACHELINE 1
9810#define BOUNDARY_MULTI_CACHELINE 2
9811
9812static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9813{
9814 int cacheline_size;
9815 u8 byte;
9816 int goal;
9817
9818 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9819 if (byte == 0)
9820 cacheline_size = 1024;
9821 else
9822 cacheline_size = (int) byte * 4;
9823
9824 /* On 5703 and later chips, the boundary bits have no
9825 * effect.
9826 */
9827 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9828 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9829 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9830 goto out;
9831
9832#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9833 goal = BOUNDARY_MULTI_CACHELINE;
9834#else
9835#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9836 goal = BOUNDARY_SINGLE_CACHELINE;
9837#else
9838 goal = 0;
9839#endif
9840#endif
9841
9842 if (!goal)
9843 goto out;
9844
9845 /* PCI controllers on most RISC systems tend to disconnect
9846 * when a device tries to burst across a cache-line boundary.
9847 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9848 *
9849 * Unfortunately, for PCI-E there are only limited
9850 * write-side controls for this, and thus for reads
9851 * we will still get the disconnects. We'll also waste
9852 * these PCI cycles for both read and write for chips
9853 * other than 5700 and 5701 which do not implement the
9854 * boundary bits.
9855 */
9856 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9857 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9858 switch (cacheline_size) {
9859 case 16:
9860 case 32:
9861 case 64:
9862 case 128:
9863 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9864 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9865 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9866 } else {
9867 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9868 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9869 }
9870 break;
9871
9872 case 256:
9873 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9874 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9875 break;
9876
9877 default:
9878 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9879 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9880 break;
9881 };
9882 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9883 switch (cacheline_size) {
9884 case 16:
9885 case 32:
9886 case 64:
9887 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9888 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9889 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9890 break;
9891 }
9892 /* fallthrough */
9893 case 128:
9894 default:
9895 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9896 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9897 break;
9898 };
9899 } else {
9900 switch (cacheline_size) {
9901 case 16:
9902 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9903 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9904 DMA_RWCTRL_WRITE_BNDRY_16);
9905 break;
9906 }
9907 /* fallthrough */
9908 case 32:
9909 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9910 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9911 DMA_RWCTRL_WRITE_BNDRY_32);
9912 break;
9913 }
9914 /* fallthrough */
9915 case 64:
9916 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9917 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9918 DMA_RWCTRL_WRITE_BNDRY_64);
9919 break;
9920 }
9921 /* fallthrough */
9922 case 128:
9923 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9924 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9925 DMA_RWCTRL_WRITE_BNDRY_128);
9926 break;
9927 }
9928 /* fallthrough */
9929 case 256:
9930 val |= (DMA_RWCTRL_READ_BNDRY_256 |
9931 DMA_RWCTRL_WRITE_BNDRY_256);
9932 break;
9933 case 512:
9934 val |= (DMA_RWCTRL_READ_BNDRY_512 |
9935 DMA_RWCTRL_WRITE_BNDRY_512);
9936 break;
9937 case 1024:
9938 default:
9939 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9940 DMA_RWCTRL_WRITE_BNDRY_1024);
9941 break;
9942 };
9943 }
9944
9945out:
9946 return val;
9947}
9948
1da177e4
LT		 9949static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9950{
9951 struct tg3_internal_buffer_desc test_desc;
9952 u32 sram_dma_descs;
9953 int i, ret;
9954
9955 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9956
9957 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9958 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9959 tw32(RDMAC_STATUS, 0);
9960 tw32(WDMAC_STATUS, 0);
9961
9962 tw32(BUFMGR_MODE, 0);
9963 tw32(FTQ_RESET, 0);
9964
9965 test_desc.addr_hi = ((u64) buf_dma) >> 32;
9966 test_desc.addr_lo = buf_dma & 0xffffffff;
9967 test_desc.nic_mbuf = 0x00002100;
9968 test_desc.len = size;
9969
9970 /*
9971 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9972 * the *second* time the tg3 driver was getting loaded after an
9973 * initial scan.
9974 *
9975 * Broadcom tells me:
9976 * ...the DMA engine is connected to the GRC block and a DMA
9977 * reset may affect the GRC block in some unpredictable way...
9978 * The behavior of resets to individual blocks has not been tested.
9979 *
9980 * Broadcom noted the GRC reset will also reset all sub-components.
9981 */
9982 if (to_device) {
9983 test_desc.cqid_sqid = (13 << 8) | 2;
9984
9985 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9986 udelay(40);
9987 } else {
9988 test_desc.cqid_sqid = (16 << 8) | 7;
9989
9990 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9991 udelay(40);
9992 }
9993 test_desc.flags = 0x00000005;
9994
9995 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9996 u32 val;
9997
9998 val = *(((u32 *)&test_desc) + i);
9999 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10000 sram_dma_descs + (i * sizeof(u32)));
10001 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10002 }
10003 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10004
10005 if (to_device) {
10006 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10007 } else {
10008 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10009 }
10010
10011 ret = -ENODEV;
10012 for (i = 0; i < 40; i++) {
10013 u32 val;
10014
10015 if (to_device)
10016 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10017 else
10018 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10019 if ((val & 0xffff) == sram_dma_descs) {
10020 ret = 0;
10021 break;
10022 }
10023
10024 udelay(100);
10025 }
10026
10027 return ret;
10028}
10029
ded7340d 10030#define TEST_BUFFER_SIZE 0x2000
1da177e4
LT		 10031
10032static int __devinit tg3_test_dma(struct tg3 *tp)
10033{
10034 dma_addr_t buf_dma;
59e6b434 10035 u32 *buf, saved_dma_rwctrl;
1da177e4
LT		 10036 int ret;
10037
10038 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10039 if (!buf) {
10040 ret = -ENOMEM;
10041 goto out_nofree;
10042 }
10043
10044 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10045 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10046
59e6b434 10047 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
1da177e4
LT		 10048
10049 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10050 /* DMA read watermark not used on PCIE */
10051 tp->dma_rwctrl |= 0x00180000;
10052 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
85e94ced
MC		 10053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
1da177e4
LT		 10055 tp->dma_rwctrl |= 0x003f0000;
10056 else
10057 tp->dma_rwctrl |= 0x003f000f;
10058 } else {
10059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10061 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10062
10063 if (ccval == 0x6 || ccval == 0x7)
10064 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10065
59e6b434 10066 /* Set bit 23 to enable PCIX hw bug fix */
1da177e4 10067 tp->dma_rwctrl |= 0x009f0000;
4cf78e4f
MC		 10068 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10069 /* 5780 always in PCIX mode */
10070 tp->dma_rwctrl |= 0x00144000;
1da177e4
LT		 10071 } else {
10072 tp->dma_rwctrl |= 0x001b000f;
10073 }
10074 }
10075
10076 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10078 tp->dma_rwctrl &= 0xfffffff0;
10079
10080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10082 /* Remove this if it causes problems for some boards. */
10083 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10084
10085 /* On 5700/5701 chips, we need to set this bit.
10086 * Otherwise the chip will issue cacheline transactions
10087 * to streamable DMA memory with not all the byte
10088 * enables turned on. This is an error on several
10089 * RISC PCI controllers, in particular sparc64.
10090 *
10091 * On 5703/5704 chips, this bit has been reassigned
10092 * a different meaning. In particular, it is used
10093 * on those chips to enable a PCI-X workaround.
10094 */
10095 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10096 }
10097
10098 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10099
10100#if 0
10101 /* Unneeded, already done by tg3_get_invariants. */
10102 tg3_switch_clocks(tp);
10103#endif
10104
10105 ret = 0;
10106 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10107 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10108 goto out;
10109
59e6b434
DM		 10110 /* It is best to perform DMA test with maximum write burst size
10111 * to expose the 5700/5701 write DMA bug.
10112 */
10113 saved_dma_rwctrl = tp->dma_rwctrl;
10114 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10115 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10116
1da177e4
LT		 10117 while (1) {
10118 u32 *p = buf, i;
10119
10120 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10121 p[i] = i;
10122
10123 /* Send the buffer to the chip. */
10124 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10125 if (ret) {
10126 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10127 break;
10128 }
10129
10130#if 0
10131 /* validate data reached card RAM correctly. */
10132 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10133 u32 val;
10134 tg3_read_mem(tp, 0x2100 + (i*4), &val);
10135 if (le32_to_cpu(val) != p[i]) {
10136 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
10137 /* ret = -ENODEV here? */
10138 }
10139 p[i] = 0;
10140 }
10141#endif
10142 /* Now read it back. */
10143 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10144 if (ret) {
10145 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10146
10147 break;
10148 }
10149
10150 /* Verify it. */
10151 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10152 if (p[i] == i)
10153 continue;
10154
59e6b434
DM		 10155 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10156 DMA_RWCTRL_WRITE_BNDRY_16) {
10157 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
1da177e4
LT		 10158 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10159 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10160 break;
10161 } else {
10162 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10163 ret = -ENODEV;
10164 goto out;
10165 }
10166 }
10167
10168 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10169 /* Success. */
10170 ret = 0;
10171 break;
10172 }
10173 }
59e6b434
DM		 10174 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10175 DMA_RWCTRL_WRITE_BNDRY_16) {
6d1cfbab
MC		 10176 static struct pci_device_id dma_wait_state_chipsets[] = {
10177 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10178 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10179 { },
10180 };
10181
59e6b434 10182 /* DMA test passed without adjusting DMA boundary,
6d1cfbab
MC		 10183 * now look for chipsets that are known to expose the
10184 * DMA bug without failing the test.
59e6b434 10185 */
6d1cfbab
MC		 10186 if (pci_dev_present(dma_wait_state_chipsets)) {
10187 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10188 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10189 }
10190 else
10191 /* Safe to use the calculated DMA boundary. */
10192 tp->dma_rwctrl = saved_dma_rwctrl;
10193
59e6b434
DM		 10194 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10195 }
1da177e4
LT		 10196
10197out:
10198 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10199out_nofree:
10200 return ret;
10201}
10202
10203static void __devinit tg3_init_link_config(struct tg3 *tp)
10204{
10205 tp->link_config.advertising =
10206 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10207 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10208 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10209 ADVERTISED_Autoneg | ADVERTISED_MII);
10210 tp->link_config.speed = SPEED_INVALID;
10211 tp->link_config.duplex = DUPLEX_INVALID;
10212 tp->link_config.autoneg = AUTONEG_ENABLE;
10213 netif_carrier_off(tp->dev);
10214 tp->link_config.active_speed = SPEED_INVALID;
10215 tp->link_config.active_duplex = DUPLEX_INVALID;
10216 tp->link_config.phy_is_low_power = 0;
10217 tp->link_config.orig_speed = SPEED_INVALID;
10218 tp->link_config.orig_duplex = DUPLEX_INVALID;
10219 tp->link_config.orig_autoneg = AUTONEG_INVALID;
10220}
10221
10222static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10223{
fdfec172
MC		 10224 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10225 tp->bufmgr_config.mbuf_read_dma_low_water =
10226 DEFAULT_MB_RDMA_LOW_WATER_5705;
10227 tp->bufmgr_config.mbuf_mac_rx_low_water =
10228 DEFAULT_MB_MACRX_LOW_WATER_5705;
10229 tp->bufmgr_config.mbuf_high_water =
10230 DEFAULT_MB_HIGH_WATER_5705;
10231
10232 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10233 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10234 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10235 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10236 tp->bufmgr_config.mbuf_high_water_jumbo =
10237 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10238 } else {
10239 tp->bufmgr_config.mbuf_read_dma_low_water =
10240 DEFAULT_MB_RDMA_LOW_WATER;
10241 tp->bufmgr_config.mbuf_mac_rx_low_water =
10242 DEFAULT_MB_MACRX_LOW_WATER;
10243 tp->bufmgr_config.mbuf_high_water =
10244 DEFAULT_MB_HIGH_WATER;
10245
10246 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10247 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10248 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10249 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10250 tp->bufmgr_config.mbuf_high_water_jumbo =
10251 DEFAULT_MB_HIGH_WATER_JUMBO;
10252 }
1da177e4
LT		 10253
10254 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10255 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10256}
10257
10258static char * __devinit tg3_phy_string(struct tg3 *tp)
10259{
10260 switch (tp->phy_id & PHY_ID_MASK) {
10261 case PHY_ID_BCM5400: return "5400";
10262 case PHY_ID_BCM5401: return "5401";
10263 case PHY_ID_BCM5411: return "5411";
10264 case PHY_ID_BCM5701: return "5701";
10265 case PHY_ID_BCM5703: return "5703";
10266 case PHY_ID_BCM5704: return "5704";
10267 case PHY_ID_BCM5705: return "5705";
10268 case PHY_ID_BCM5750: return "5750";
85e94ced 10269 case PHY_ID_BCM5752: return "5752";
4cf78e4f 10270 case PHY_ID_BCM5780: return "5780";
1da177e4
LT		 10271 case PHY_ID_BCM8002: return "8002/serdes";
10272 case 0: return "serdes";
10273 default: return "unknown";
10274 };
10275}
10276
10277static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
10278{
10279 struct pci_dev *peer;
10280 unsigned int func, devnr = tp->pdev->devfn & ~7;
10281
10282 for (func = 0; func < 8; func++) {
10283 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10284 if (peer && peer != tp->pdev)
10285 break;
10286 pci_dev_put(peer);
10287 }
10288 if (!peer || peer == tp->pdev)
10289 BUG();
10290
10291 /*
10292 * We don't need to keep the refcount elevated; there's no way
10293 * to remove one half of this device without removing the other
10294 */
10295 pci_dev_put(peer);
10296
10297 return peer;
10298}
10299
15f9850d
DM		 10300static void __devinit tg3_init_coal(struct tg3 *tp)
10301{
10302 struct ethtool_coalesce *ec = &tp->coal;
10303
10304 memset(ec, 0, sizeof(*ec));
10305 ec->cmd = ETHTOOL_GCOALESCE;
10306 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10307 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10308 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10309 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10310 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10311 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10312 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10313 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10314 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10315
10316 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10317 HOSTCC_MODE_CLRTICK_TXBD)) {
10318 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10319 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10320 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10321 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10322 }
d244c892
MC		 10323
10324 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10325 ec->rx_coalesce_usecs_irq = 0;
10326 ec->tx_coalesce_usecs_irq = 0;
10327 ec->stats_block_coalesce_usecs = 0;
10328 }
15f9850d
DM		 10329}
10330
1da177e4
LT		 10331static int __devinit tg3_init_one(struct pci_dev *pdev,
10332 const struct pci_device_id *ent)
10333{
10334 static int tg3_version_printed = 0;
10335 unsigned long tg3reg_base, tg3reg_len;
10336 struct net_device *dev;
10337 struct tg3 *tp;
10338 int i, err, pci_using_dac, pm_cap;
10339
10340 if (tg3_version_printed++ == 0)
10341 printk(KERN_INFO "%s", version);
10342
10343 err = pci_enable_device(pdev);
10344 if (err) {
10345 printk(KERN_ERR PFX "Cannot enable PCI device, "
10346 "aborting.\n");
10347 return err;
10348 }
10349
10350 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10351 printk(KERN_ERR PFX "Cannot find proper PCI device "
10352 "base address, aborting.\n");
10353 err = -ENODEV;
10354 goto err_out_disable_pdev;
10355 }
10356
10357 err = pci_request_regions(pdev, DRV_MODULE_NAME);
10358 if (err) {
10359 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10360 "aborting.\n");
10361 goto err_out_disable_pdev;
10362 }
10363
10364 pci_set_master(pdev);
10365
10366 /* Find power-management capability. */
10367 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10368 if (pm_cap == 0) {
10369 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10370 "aborting.\n");
10371 err = -EIO;
10372 goto err_out_free_res;
10373 }
10374
10375 /* Configure DMA attributes. */
10376 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
10377 if (!err) {
10378 pci_using_dac = 1;
10379 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
10380 if (err < 0) {
10381 printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10382 "for consistent allocations\n");
10383 goto err_out_free_res;
10384 }
10385 } else {
10386 err = pci_set_dma_mask(pdev, 0xffffffffULL);
10387 if (err) {
10388 printk(KERN_ERR PFX "No usable DMA configuration, "
10389 "aborting.\n");
10390 goto err_out_free_res;
10391 }
10392 pci_using_dac = 0;
10393 }
10394
10395 tg3reg_base = pci_resource_start(pdev, 0);
10396 tg3reg_len = pci_resource_len(pdev, 0);
10397
10398 dev = alloc_etherdev(sizeof(*tp));
10399 if (!dev) {
10400 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10401 err = -ENOMEM;
10402 goto err_out_free_res;
10403 }
10404
10405 SET_MODULE_OWNER(dev);
10406 SET_NETDEV_DEV(dev, &pdev->dev);
10407
10408 if (pci_using_dac)
10409 dev->features |= NETIF_F_HIGHDMA;
10410 dev->features |= NETIF_F_LLTX;
10411#if TG3_VLAN_TAG_USED
10412 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10413 dev->vlan_rx_register = tg3_vlan_rx_register;
10414 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10415#endif
10416
10417 tp = netdev_priv(dev);
10418 tp->pdev = pdev;
10419 tp->dev = dev;
10420 tp->pm_cap = pm_cap;
10421 tp->mac_mode = TG3_DEF_MAC_MODE;
10422 tp->rx_mode = TG3_DEF_RX_MODE;
10423 tp->tx_mode = TG3_DEF_TX_MODE;
10424 tp->mi_mode = MAC_MI_MODE_BASE;
10425 if (tg3_debug > 0)
10426 tp->msg_enable = tg3_debug;
10427 else
10428 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10429
10430 /* The word/byte swap controls here control register access byte
10431 * swapping. DMA data byte swapping is controlled in the GRC_MODE
10432 * setting below.
10433 */
10434 tp->misc_host_ctrl =
10435 MISC_HOST_CTRL_MASK_PCI_INT |
10436 MISC_HOST_CTRL_WORD_SWAP |
10437 MISC_HOST_CTRL_INDIR_ACCESS |
10438 MISC_HOST_CTRL_PCISTATE_RW;
10439
10440 /* The NONFRM (non-frame) byte/word swap controls take effect
10441 * on descriptor entries, anything which isn't packet data.
10442 *
10443 * The StrongARM chips on the board (one for tx, one for rx)
10444 * are running in big-endian mode.
10445 */
10446 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10447 GRC_MODE_WSWAP_NONFRM_DATA);
10448#ifdef __BIG_ENDIAN
10449 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10450#endif
10451 spin_lock_init(&tp->lock);
10452 spin_lock_init(&tp->tx_lock);
10453 spin_lock_init(&tp->indirect_lock);
10454 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10455
10456 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10457 if (tp->regs == 0UL) {
10458 printk(KERN_ERR PFX "Cannot map device registers, "
10459 "aborting.\n");
10460 err = -ENOMEM;
10461 goto err_out_free_dev;
10462 }
10463
10464 tg3_init_link_config(tp);
10465
1da177e4
LT		 10466 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10467 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10468 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10469
10470 dev->open = tg3_open;
10471 dev->stop = tg3_close;
10472 dev->get_stats = tg3_get_stats;
10473 dev->set_multicast_list = tg3_set_rx_mode;
10474 dev->set_mac_address = tg3_set_mac_addr;
10475 dev->do_ioctl = tg3_ioctl;
10476 dev->tx_timeout = tg3_tx_timeout;
10477 dev->poll = tg3_poll;
10478 dev->ethtool_ops = &tg3_ethtool_ops;
10479 dev->weight = 64;
10480 dev->watchdog_timeo = TG3_TX_TIMEOUT;
10481 dev->change_mtu = tg3_change_mtu;
10482 dev->irq = pdev->irq;
10483#ifdef CONFIG_NET_POLL_CONTROLLER
10484 dev->poll_controller = tg3_poll_controller;
10485#endif
10486
10487 err = tg3_get_invariants(tp);
10488 if (err) {
10489 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10490 "aborting.\n");
10491 goto err_out_iounmap;
10492 }
10493
fdfec172 10494 tg3_init_bufmgr_config(tp);
1da177e4
LT		 10495
10496#if TG3_TSO_SUPPORT != 0
10497 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10498 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10499 }
10500 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10502 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10503 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10504 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10505 } else {
10506 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10507 }
10508
10509 /* TSO is off by default, user can enable using ethtool. */
10510#if 0
10511 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10512 dev->features |= NETIF_F_TSO;
10513#endif
10514
10515#endif
10516
10517 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10518 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10519 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10520 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10521 tp->rx_pending = 63;
10522 }
10523
10524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10525 tp->pdev_peer = tg3_find_5704_peer(tp);
10526
10527 err = tg3_get_device_address(tp);
10528 if (err) {
10529 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10530 "aborting.\n");
10531 goto err_out_iounmap;
10532 }
10533
10534 /*
10535 * Reset chip in case UNDI or EFI driver did not shutdown
10536 * DMA self test will enable WDMAC and we'll see (spurious)
10537 * pending DMA on the PCI bus at that point.
10538 */
10539 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10540 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10541 pci_save_state(tp->pdev);
10542 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
944d980e 10543 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
1da177e4
LT		 10544 }
10545
10546 err = tg3_test_dma(tp);
10547 if (err) {
10548 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10549 goto err_out_iounmap;
10550 }
10551
10552 /* Tigon3 can do ipv4 only... and some chips have buggy
10553 * checksumming.
10554 */
10555 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10556 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10557 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10558 } else
10559 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10560
10561 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10562 dev->features &= ~NETIF_F_HIGHDMA;
10563
10564 /* flow control autonegotiation is default behavior */
10565 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10566
15f9850d
DM		 10567 tg3_init_coal(tp);
10568
7d3f4c97
DM		 10569 /* Now that we have fully setup the chip, save away a snapshot
10570 * of the PCI config space. We need to restore this after
10571 * GRC_MISC_CFG core clock resets and some resume events.
10572 */
10573 pci_save_state(tp->pdev);
10574
1da177e4
LT		 10575 err = register_netdev(dev);
10576 if (err) {
10577 printk(KERN_ERR PFX "Cannot register net device, "
10578 "aborting.\n");
10579 goto err_out_iounmap;
10580 }
10581
10582 pci_set_drvdata(pdev, dev);
10583
1da177e4
LT		 10584 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10585 dev->name,
10586 tp->board_part_number,
10587 tp->pci_chip_rev_id,
10588 tg3_phy_string(tp),
10589 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10590 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10591 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10592 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10593 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10594 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10595
10596 for (i = 0; i < 6; i++)
10597 printk("%2.2x%c", dev->dev_addr[i],
10598 i == 5 ? '\n' : ':');
10599
10600 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10601 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10602 "TSOcap[%d] \n",
10603 dev->name,
10604 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10605 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10606 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10607 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10608 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10609 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10610 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
59e6b434
DM		 10611 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10612 dev->name, tp->dma_rwctrl);
1da177e4
LT		 10613
10614 return 0;
10615
10616err_out_iounmap:
6892914f
MC		 10617 if (tp->regs) {
10618 iounmap(tp->regs);
10619 tp->regs = 0;
10620 }
1da177e4
LT		 10621
10622err_out_free_dev:
10623 free_netdev(dev);
10624
10625err_out_free_res:
10626 pci_release_regions(pdev);
10627
10628err_out_disable_pdev:
10629 pci_disable_device(pdev);
10630 pci_set_drvdata(pdev, NULL);
10631 return err;
10632}
10633
10634static void __devexit tg3_remove_one(struct pci_dev *pdev)
10635{
10636 struct net_device *dev = pci_get_drvdata(pdev);
10637
10638 if (dev) {
10639 struct tg3 *tp = netdev_priv(dev);
10640
10641 unregister_netdev(dev);
6892914f
MC		 10642 if (tp->regs) {
10643 iounmap(tp->regs);
10644 tp->regs = 0;
10645 }
1da177e4
LT		 10646 free_netdev(dev);
10647 pci_release_regions(pdev);
10648 pci_disable_device(pdev);
10649 pci_set_drvdata(pdev, NULL);
10650 }
10651}
10652
10653static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10654{
10655 struct net_device *dev = pci_get_drvdata(pdev);
10656 struct tg3 *tp = netdev_priv(dev);
10657 int err;
10658
10659 if (!netif_running(dev))
10660 return 0;
10661
10662 tg3_netif_stop(tp);
10663
10664 del_timer_sync(&tp->timer);
10665
f47c11ee 10666 tg3_full_lock(tp, 1);
1da177e4 10667 tg3_disable_ints(tp);
f47c11ee 10668 tg3_full_unlock(tp);
1da177e4
LT		 10669
10670 netif_device_detach(dev);
10671
f47c11ee 10672 tg3_full_lock(tp, 0);
944d980e 10673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
f47c11ee 10674 tg3_full_unlock(tp);
1da177e4
LT		 10675
10676 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10677 if (err) {
f47c11ee 10678 tg3_full_lock(tp, 0);
1da177e4
LT		 10679
10680 tg3_init_hw(tp);
10681
10682 tp->timer.expires = jiffies + tp->timer_offset;
10683 add_timer(&tp->timer);
10684
10685 netif_device_attach(dev);
10686 tg3_netif_start(tp);
10687
f47c11ee 10688 tg3_full_unlock(tp);
1da177e4
LT		 10689 }
10690
10691 return err;
10692}
10693
10694static int tg3_resume(struct pci_dev *pdev)
10695{
10696 struct net_device *dev = pci_get_drvdata(pdev);
10697 struct tg3 *tp = netdev_priv(dev);
10698 int err;
10699
10700 if (!netif_running(dev))
10701 return 0;
10702
10703 pci_restore_state(tp->pdev);
10704
10705 err = tg3_set_power_state(tp, 0);
10706 if (err)
10707 return err;
10708
10709 netif_device_attach(dev);
10710
f47c11ee 10711 tg3_full_lock(tp, 0);
1da177e4
LT		 10712
10713 tg3_init_hw(tp);
10714
10715 tp->timer.expires = jiffies + tp->timer_offset;
10716 add_timer(&tp->timer);
10717
1da177e4
LT		 10718 tg3_netif_start(tp);
10719
f47c11ee 10720 tg3_full_unlock(tp);
1da177e4
LT		 10721
10722 return 0;
10723}
10724
10725static struct pci_driver tg3_driver = {
10726 .name = DRV_MODULE_NAME,
10727 .id_table = tg3_pci_tbl,
10728 .probe = tg3_init_one,
10729 .remove = __devexit_p(tg3_remove_one),
10730 .suspend = tg3_suspend,
10731 .resume = tg3_resume
10732};
10733
10734static int __init tg3_init(void)
10735{
10736 return pci_module_init(&tg3_driver);
10737}
10738
10739static void __exit tg3_cleanup(void)
10740{
10741 pci_unregister_driver(&tg3_driver);
10742}
10743
10744module_init(tg3_init);
10745module_exit(tg3_cleanup);
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