]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/r8169.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: remove private net_device_stats structure
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
0b50f81d 62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
0b50f81d 66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 67#define rtl8169_rx_quota(count, quota) count
68#endif
69
1da177e4 70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 71static const int max_interrupt_work = 20;
1da177e4
LT		 72
73/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 75static const int multicast_filter_limit = 32;
1da177e4
LT		 76
77/* MAC address length */
78#define MAC_ADDR_LEN 6
79
80#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 83#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 84#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87
88#define R8169_REGS_SIZE 256
89#define R8169_NAPI_WEIGHT 64
90#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
105#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
106
107enum mac_version {
ba6eb6ee
FR		 108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
118 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 119};
120
121enum phy_version {
122 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
125 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
126 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
127 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
128};
129
1da177e4
LT		 130#define _R(NAME,MAC,MASK) \
131 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
132
3c6bee1d 133static const struct {
1da177e4
LT		 134 const char *name;
135 u8 mac_version;
136 u32 RxConfigMask; /* Clears the bits supported by this chip */
137} rtl_chip_info[] = {
ba6eb6ee
FR		 138 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
139 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
140 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
141 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 143 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 149};
150#undef _R
151
bcf0bf90
FR		 152enum cfg_version {
153 RTL_CFG_0 = 0x00,
154 RTL_CFG_1,
155 RTL_CFG_2
156};
157
07ce4064
FR		 158static void rtl_hw_start_8169(struct net_device *);
159static void rtl_hw_start_8168(struct net_device *);
160static void rtl_hw_start_8101(struct net_device *);
161
1da177e4 162static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 169 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032,
172 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 173 {0,},
174};
175
176MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
177
178static int rx_copybreak = 200;
179static int use_dac;
b57b7e5a
SH		 180static struct {
181 u32 msg_enable;
182} debug = { -1 };
1da177e4 183
07d3f51f
FR		 184enum rtl_registers {
185 MAC0 = 0, /* Ethernet hardware address. */
773d2021 186 MAC4 = 4,
07d3f51f
FR		 187 MAR0 = 8, /* Multicast filter. */
188 CounterAddrLow = 0x10,
189 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
194 FLASH = 0x30,
195 ERSR = 0x36,
196 ChipCmd = 0x37,
197 TxPoll = 0x38,
198 IntrMask = 0x3c,
199 IntrStatus = 0x3e,
200 TxConfig = 0x40,
201 RxConfig = 0x44,
202 RxMissed = 0x4c,
203 Cfg9346 = 0x50,
204 Config0 = 0x51,
205 Config1 = 0x52,
206 Config2 = 0x53,
207 Config3 = 0x54,
208 Config4 = 0x55,
209 Config5 = 0x56,
210 MultiIntr = 0x5c,
211 PHYAR = 0x60,
212 TBICSR = 0x64,
213 TBI_ANAR = 0x68,
214 TBI_LPAR = 0x6a,
215 PHYstatus = 0x6c,
216 RxMaxSize = 0xda,
217 CPlusCmd = 0xe0,
218 IntrMitigate = 0xe2,
219 RxDescAddrLow = 0xe4,
220 RxDescAddrHigh = 0xe8,
221 EarlyTxThres = 0xec,
222 FuncEvent = 0xf0,
223 FuncEventMask = 0xf4,
224 FuncPresetState = 0xf8,
225 FuncForceEvent = 0xfc,
1da177e4
LT		 226};
227
07d3f51f 228enum rtl_register_content {
1da177e4 229 /* InterruptStatusBits */
07d3f51f
FR		 230 SYSErr = 0x8000,
231 PCSTimeout = 0x4000,
232 SWInt = 0x0100,
233 TxDescUnavail = 0x0080,
234 RxFIFOOver = 0x0040,
235 LinkChg = 0x0020,
236 RxOverflow = 0x0010,
237 TxErr = 0x0008,
238 TxOK = 0x0004,
239 RxErr = 0x0002,
240 RxOK = 0x0001,
1da177e4
LT		 241
242 /* RxStatusDesc */
9dccf611
FR		 243 RxFOVF = (1 << 23),
244 RxRWT = (1 << 22),
245 RxRES = (1 << 21),
246 RxRUNT = (1 << 20),
247 RxCRC = (1 << 19),
1da177e4
LT		 248
249 /* ChipCmdBits */
07d3f51f
FR		 250 CmdReset = 0x10,
251 CmdRxEnb = 0x08,
252 CmdTxEnb = 0x04,
253 RxBufEmpty = 0x01,
1da177e4 254
275391a4
FR		 255 /* TXPoll register p.5 */
256 HPQ = 0x80, /* Poll cmd on the high prio queue */
257 NPQ = 0x40, /* Poll cmd on the low prio queue */
258 FSWInt = 0x01, /* Forced software interrupt */
259
1da177e4 260 /* Cfg9346Bits */
07d3f51f
FR		 261 Cfg9346_Lock = 0x00,
262 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 263
264 /* rx_mode_bits */
07d3f51f
FR		 265 AcceptErr = 0x20,
266 AcceptRunt = 0x10,
267 AcceptBroadcast = 0x08,
268 AcceptMulticast = 0x04,
269 AcceptMyPhys = 0x02,
270 AcceptAllPhys = 0x01,
1da177e4
LT		 271
272 /* RxConfigBits */
07d3f51f
FR		 273 RxCfgFIFOShift = 13,
274 RxCfgDMAShift = 8,
1da177e4
LT		 275
276 /* TxConfigBits */
277 TxInterFrameGapShift = 24,
278 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
279
5d06a99f 280 /* Config1 register p.24 */
fbac58fc 281 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 282 PMEnable = (1 << 0), /* Power Management Enable */
283
6dccd16b
FR		 284 /* Config2 register p. 25 */
285 PCI_Clock_66MHz = 0x01,
286 PCI_Clock_33MHz = 0x00,
287
61a4dcc2
FR		 288 /* Config3 register p.25 */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
5d06a99f 292 /* Config5 register p.27 */
61a4dcc2
FR		 293 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
294 MWF = (1 << 5), /* Accept Multicast wakeup frame */
295 UWF = (1 << 4), /* Accept Unicast wakeup frame */
296 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 297 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
298
1da177e4
LT		 299 /* TBICSR p.28 */
300 TBIReset = 0x80000000,
301 TBILoopback = 0x40000000,
302 TBINwEnable = 0x20000000,
303 TBINwRestart = 0x10000000,
304 TBILinkOk = 0x02000000,
305 TBINwComplete = 0x01000000,
306
307 /* CPlusCmd p.31 */
0e485150 308 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 309 RxVlan = (1 << 6),
310 RxChkSum = (1 << 5),
311 PCIDAC = (1 << 4),
312 PCIMulRW = (1 << 3),
0e485150
FR		 313 INTT_0 = 0x0000, // 8168
314 INTT_1 = 0x0001, // 8168
315 INTT_2 = 0x0002, // 8168
316 INTT_3 = 0x0003, // 8168
1da177e4
LT		 317
318 /* rtl8169_PHYstatus */
07d3f51f
FR		 319 TBI_Enable = 0x80,
320 TxFlowCtrl = 0x40,
321 RxFlowCtrl = 0x20,
322 _1000bpsF = 0x10,
323 _100bps = 0x08,
324 _10bps = 0x04,
325 LinkStatus = 0x02,
326 FullDup = 0x01,
1da177e4 327
1da177e4 328 /* _TBICSRBit */
07d3f51f 329 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 330
331 /* DumpCounterCommand */
07d3f51f 332 CounterDump = 0x8,
1da177e4
LT		 333};
334
07d3f51f 335enum desc_status_bit {
1da177e4
LT		 336 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
337 RingEnd = (1 << 30), /* End of descriptor ring */
338 FirstFrag = (1 << 29), /* First segment of a packet */
339 LastFrag = (1 << 28), /* Final segment of a packet */
340
341 /* Tx private */
342 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
343 MSSShift = 16, /* MSS value position */
344 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
345 IPCS = (1 << 18), /* Calculate IP checksum */
346 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
347 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
348 TxVlanTag = (1 << 17), /* Add VLAN tag */
349
350 /* Rx private */
351 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
352 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
353
354#define RxProtoUDP (PID1)
355#define RxProtoTCP (PID0)
356#define RxProtoIP (PID1 | PID0)
357#define RxProtoMask RxProtoIP
358
359 IPFail = (1 << 16), /* IP checksum failed */
360 UDPFail = (1 << 15), /* UDP/IP checksum failed */
361 TCPFail = (1 << 14), /* TCP/IP checksum failed */
362 RxVlanTag = (1 << 16), /* VLAN tag available */
363};
364
365#define RsvdMask 0x3fffc000
366
367struct TxDesc {
6cccd6e7
REB		 368 __le32 opts1;
369 __le32 opts2;
370 __le64 addr;
1da177e4
LT		 371};
372
373struct RxDesc {
6cccd6e7
REB		 374 __le32 opts1;
375 __le32 opts2;
376 __le64 addr;
1da177e4
LT		 377};
378
379struct ring_info {
380 struct sk_buff *skb;
381 u32 len;
382 u8 __pad[sizeof(void *) - sizeof(u32)];
383};
384
f23e7fda
FR		 385enum features {
386 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 387 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 388};
389
1da177e4
LT		 390struct rtl8169_private {
391 void __iomem *mmio_addr; /* memory map physical address */
392 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 393 struct net_device *dev;
bea3348e 394 struct napi_struct napi;
1da177e4 395 spinlock_t lock; /* spin lock flag */
b57b7e5a 396 u32 msg_enable;
1da177e4
LT		 397 int chipset;
398 int mac_version;
399 int phy_version;
400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
402 u32 dirty_rx;
403 u32 dirty_tx;
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 410 unsigned align;
1da177e4
LT		 411 unsigned rx_buf_sz;
412 struct timer_list timer;
413 u16 cp_cmd;
0e485150
FR		 414 u16 intr_event;
415 u16 napi_event;
1da177e4
LT		 416 u16 intr_mask;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419#ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
421#endif
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
07ce4064 425 void (*hw_start)(struct net_device *);
1da177e4
LT		 426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
c4028958 428 struct delayed_work task;
f23e7fda 429 unsigned features;
1da177e4
LT		 430};
431
979b6c13 432MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 433MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 434module_param(rx_copybreak, int, 0);
1b7efd58 435MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 436module_param(use_dac, int, 0);
437MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 438module_param_named(debug, debug.msg_enable, int, 0);
439MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 440MODULE_LICENSE("GPL");
441MODULE_VERSION(RTL8169_VERSION);
442
443static int rtl8169_open(struct net_device *dev);
444static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 445static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 446static int rtl8169_init_ring(struct net_device *dev);
07ce4064 447static void rtl_hw_start(struct net_device *dev);
1da177e4 448static int rtl8169_close(struct net_device *dev);
07ce4064 449static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 450static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 451static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 452static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 453 void __iomem *, u32 budget);
4dcb7d33 454static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 455static void rtl8169_down(struct net_device *dev);
99f252b0 456static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 457
458#ifdef CONFIG_R8169_NAPI
bea3348e 459static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 460#endif
461
1da177e4 462static const unsigned int rtl8169_rx_config =
5b0384f4 463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 464
07d3f51f 465static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 466{
467 int i;
468
07d3f51f 469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 470
2371408c 471 for (i = 20; i > 0; i--) {
07d3f51f
FR		 472 /*
473 * Check if the RTL8169 has completed writing to the specified
474 * MII register.
475 */
5b0384f4 476 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 477 break;
2371408c 478 udelay(25);
1da177e4
LT		 479 }
480}
481
07d3f51f 482static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 483{
484 int i, value = -1;
485
07d3f51f 486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 487
2371408c 488 for (i = 20; i > 0; i--) {
07d3f51f
FR		 489 /*
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
492 */
1da177e4
LT		 493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
495 break;
496 }
2371408c 497 udelay(25);
1da177e4
LT		 498 }
499 return value;
500}
501
502static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
503{
504 RTL_W16(IntrMask, 0x0000);
505
506 RTL_W16(IntrStatus, 0xffff);
507}
508
509static void rtl8169_asic_down(void __iomem *ioaddr)
510{
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
513 RTL_R16(CPlusCmd);
514}
515
516static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
517{
518 return RTL_R32(TBICSR) & TBIReset;
519}
520
521static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
522{
64e4bfb4 523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 524}
525
526static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
527{
528 return RTL_R32(TBICSR) & TBILinkOk;
529}
530
531static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
532{
533 return RTL_R8(PHYstatus) & LinkStatus;
534}
535
536static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
537{
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
539}
540
541static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
542{
543 unsigned int val;
544
9e0db8ef
FR		 545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 547}
548
549static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
1da177e4
LT		 552{
553 unsigned long flags;
554
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
b57b7e5a
SH		 558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
560 } else {
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 563 netif_carrier_off(dev);
b57b7e5a 564 }
1da177e4
LT		 565 spin_unlock_irqrestore(&tp->lock, flags);
566}
567
61a4dcc2
FR		 568static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
569{
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
572 u8 options;
573
574 wol->wolopts = 0;
575
576#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
578
579 spin_lock_irq(&tp->lock);
580
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
583 goto out_unlock;
584
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
590
591 options = RTL_R8(Config5);
592 if (options & UWF)
593 wol->wolopts |= WAKE_UCAST;
594 if (options & BWF)
5b0384f4 595 wol->wolopts |= WAKE_BCAST;
61a4dcc2 596 if (options & MWF)
5b0384f4 597 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 598
599out_unlock:
600 spin_unlock_irq(&tp->lock);
601}
602
603static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
604{
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 607 unsigned int i;
61a4dcc2
FR		 608 static struct {
609 u32 opt;
610 u16 reg;
611 u8 mask;
612 } cfg[] = {
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
620 };
621
622 spin_lock_irq(&tp->lock);
623
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
625
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
631 }
632
633 RTL_W8(Cfg9346, Cfg9346_Lock);
634
f23e7fda
FR		 635 if (wol->wolopts)
636 tp->features |= RTL_FEATURE_WOL;
637 else
638 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 639
640 spin_unlock_irq(&tp->lock);
641
642 return 0;
643}
644
1da177e4
LT		 645static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
647{
648 struct rtl8169_private *tp = netdev_priv(dev);
649
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
653}
654
655static int rtl8169_get_regs_len(struct net_device *dev)
656{
657 return R8169_REGS_SIZE;
658}
659
660static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
662{
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
665 int ret = 0;
666 u32 reg;
667
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
674 else {
b57b7e5a
SH		 675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
678 dev->name);
679 }
1da177e4
LT		 680 ret = -EOPNOTSUPP;
681 }
682
683 return ret;
684}
685
686static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
688{
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
692
64e4bfb4
FR		 693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 698
699 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 703 } else {
704 if (speed == SPEED_10)
64e4bfb4 705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 706 else if (speed == SPEED_100)
64e4bfb4 707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 708 else if (speed == SPEED_1000)
64e4bfb4 709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 710
711 if (duplex == DUPLEX_HALF)
64e4bfb4 712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 713
714 if (duplex == DUPLEX_FULL)
64e4bfb4 715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 716
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
719 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 720 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 721 }
722 }
723
724 /* The 8100e/8101e do Fast Ethernet only. */
725 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
726 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 728 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 729 netif_msg_link(tp)) {
730 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
731 dev->name);
732 }
64e4bfb4 733 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 734 }
735
623a1593
FR		 736 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
737
2584fbc3
RS		 738 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
739 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
740 mdio_write(ioaddr, 0x1f, 0x0000);
741 mdio_write(ioaddr, 0x0e, 0x0000);
742 }
743
1da177e4
LT		 744 tp->phy_auto_nego_reg = auto_nego;
745 tp->phy_1000_ctrl_reg = giga_ctrl;
746
64e4bfb4
FR		 747 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
748 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
749 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 750 return 0;
751}
752
753static int rtl8169_set_speed(struct net_device *dev,
754 u8 autoneg, u16 speed, u8 duplex)
755{
756 struct rtl8169_private *tp = netdev_priv(dev);
757 int ret;
758
759 ret = tp->set_speed(dev, autoneg, speed, duplex);
760
64e4bfb4 761 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 762 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
763
764 return ret;
765}
766
767static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
768{
769 struct rtl8169_private *tp = netdev_priv(dev);
770 unsigned long flags;
771 int ret;
772
773 spin_lock_irqsave(&tp->lock, flags);
774 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
775 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 776
1da177e4
LT		 777 return ret;
778}
779
780static u32 rtl8169_get_rx_csum(struct net_device *dev)
781{
782 struct rtl8169_private *tp = netdev_priv(dev);
783
784 return tp->cp_cmd & RxChkSum;
785}
786
787static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
788{
789 struct rtl8169_private *tp = netdev_priv(dev);
790 void __iomem *ioaddr = tp->mmio_addr;
791 unsigned long flags;
792
793 spin_lock_irqsave(&tp->lock, flags);
794
795 if (data)
796 tp->cp_cmd |= RxChkSum;
797 else
798 tp->cp_cmd &= ~RxChkSum;
799
800 RTL_W16(CPlusCmd, tp->cp_cmd);
801 RTL_R16(CPlusCmd);
802
803 spin_unlock_irqrestore(&tp->lock, flags);
804
805 return 0;
806}
807
808#ifdef CONFIG_R8169_VLAN
809
810static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
811 struct sk_buff *skb)
812{
813 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
814 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
815}
816
817static void rtl8169_vlan_rx_register(struct net_device *dev,
818 struct vlan_group *grp)
819{
820 struct rtl8169_private *tp = netdev_priv(dev);
821 void __iomem *ioaddr = tp->mmio_addr;
822 unsigned long flags;
823
824 spin_lock_irqsave(&tp->lock, flags);
825 tp->vlgrp = grp;
826 if (tp->vlgrp)
827 tp->cp_cmd |= RxVlan;
828 else
829 tp->cp_cmd &= ~RxVlan;
830 RTL_W16(CPlusCmd, tp->cp_cmd);
831 RTL_R16(CPlusCmd);
832 spin_unlock_irqrestore(&tp->lock, flags);
833}
834
1da177e4
LT		 835static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
836 struct sk_buff *skb)
837{
838 u32 opts2 = le32_to_cpu(desc->opts2);
839 int ret;
840
841 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 842 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 843 ret = 0;
844 } else
845 ret = -1;
846 desc->opts2 = 0;
847 return ret;
848}
849
850#else /* !CONFIG_R8169_VLAN */
851
852static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
853 struct sk_buff *skb)
854{
855 return 0;
856}
857
858static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
859 struct sk_buff *skb)
860{
861 return -1;
862}
863
864#endif
865
866static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
867{
868 struct rtl8169_private *tp = netdev_priv(dev);
869 void __iomem *ioaddr = tp->mmio_addr;
870 u32 status;
871
872 cmd->supported =
873 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
874 cmd->port = PORT_FIBRE;
875 cmd->transceiver = XCVR_INTERNAL;
876
877 status = RTL_R32(TBICSR);
878 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
879 cmd->autoneg = !!(status & TBINwEnable);
880
881 cmd->speed = SPEED_1000;
882 cmd->duplex = DUPLEX_FULL; /* Always set */
883}
884
885static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
886{
887 struct rtl8169_private *tp = netdev_priv(dev);
888 void __iomem *ioaddr = tp->mmio_addr;
889 u8 status;
890
891 cmd->supported = SUPPORTED_10baseT_Half |
892 SUPPORTED_10baseT_Full |
893 SUPPORTED_100baseT_Half |
894 SUPPORTED_100baseT_Full |
895 SUPPORTED_1000baseT_Full |
896 SUPPORTED_Autoneg |
5b0384f4 897 SUPPORTED_TP;
1da177e4
LT		 898
899 cmd->autoneg = 1;
900 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
901
64e4bfb4 902 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 903 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 904 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 905 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 906 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 907 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 908 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 909 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 910 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 911 cmd->advertising |= ADVERTISED_1000baseT_Full;
912
913 status = RTL_R8(PHYstatus);
914
915 if (status & _1000bpsF)
916 cmd->speed = SPEED_1000;
917 else if (status & _100bps)
918 cmd->speed = SPEED_100;
919 else if (status & _10bps)
920 cmd->speed = SPEED_10;
921
623a1593
FR		 922 if (status & TxFlowCtrl)
923 cmd->advertising |= ADVERTISED_Asym_Pause;
924 if (status & RxFlowCtrl)
925 cmd->advertising |= ADVERTISED_Pause;
926
1da177e4
LT		 927 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
928 DUPLEX_FULL : DUPLEX_HALF;
929}
930
931static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
932{
933 struct rtl8169_private *tp = netdev_priv(dev);
934 unsigned long flags;
935
936 spin_lock_irqsave(&tp->lock, flags);
937
938 tp->get_settings(dev, cmd);
939
940 spin_unlock_irqrestore(&tp->lock, flags);
941 return 0;
942}
943
944static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
945 void *p)
946{
5b0384f4
FR		 947 struct rtl8169_private *tp = netdev_priv(dev);
948 unsigned long flags;
1da177e4 949
5b0384f4
FR		 950 if (regs->len > R8169_REGS_SIZE)
951 regs->len = R8169_REGS_SIZE;
1da177e4 952
5b0384f4
FR		 953 spin_lock_irqsave(&tp->lock, flags);
954 memcpy_fromio(p, tp->mmio_addr, regs->len);
955 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 956}
957
b57b7e5a
SH		 958static u32 rtl8169_get_msglevel(struct net_device *dev)
959{
960 struct rtl8169_private *tp = netdev_priv(dev);
961
962 return tp->msg_enable;
963}
964
965static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
966{
967 struct rtl8169_private *tp = netdev_priv(dev);
968
969 tp->msg_enable = value;
970}
971
d4a3a0fc
SH		 972static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
973 "tx_packets",
974 "rx_packets",
975 "tx_errors",
976 "rx_errors",
977 "rx_missed",
978 "align_errors",
979 "tx_single_collisions",
980 "tx_multi_collisions",
981 "unicast",
982 "broadcast",
983 "multicast",
984 "tx_aborted",
985 "tx_underrun",
986};
987
988struct rtl8169_counters {
b1eab701
AV		 989 __le64 tx_packets;
990 __le64 rx_packets;
991 __le64 tx_errors;
992 __le32 rx_errors;
993 __le16 rx_missed;
994 __le16 align_errors;
995 __le32 tx_one_collision;
996 __le32 tx_multi_collision;
997 __le64 rx_unicast;
998 __le64 rx_broadcast;
999 __le32 rx_multicast;
1000 __le16 tx_aborted;
1001 __le16 tx_underun;
d4a3a0fc
SH		 1002};
1003
b9f2c044 1004static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1005{
b9f2c044
JG		 1006 switch (sset) {
1007 case ETH_SS_STATS:
1008 return ARRAY_SIZE(rtl8169_gstrings);
1009 default:
1010 return -EOPNOTSUPP;
1011 }
d4a3a0fc
SH		 1012}
1013
1014static void rtl8169_get_ethtool_stats(struct net_device *dev,
1015 struct ethtool_stats *stats, u64 *data)
1016{
1017 struct rtl8169_private *tp = netdev_priv(dev);
1018 void __iomem *ioaddr = tp->mmio_addr;
1019 struct rtl8169_counters *counters;
1020 dma_addr_t paddr;
1021 u32 cmd;
1022
1023 ASSERT_RTNL();
1024
1025 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1026 if (!counters)
1027 return;
1028
1029 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1030 cmd = (u64)paddr & DMA_32BIT_MASK;
1031 RTL_W32(CounterAddrLow, cmd);
1032 RTL_W32(CounterAddrLow, cmd | CounterDump);
1033
1034 while (RTL_R32(CounterAddrLow) & CounterDump) {
1035 if (msleep_interruptible(1))
1036 break;
1037 }
1038
1039 RTL_W32(CounterAddrLow, 0);
1040 RTL_W32(CounterAddrHigh, 0);
1041
5b0384f4 1042 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1043 data[1] = le64_to_cpu(counters->rx_packets);
1044 data[2] = le64_to_cpu(counters->tx_errors);
1045 data[3] = le32_to_cpu(counters->rx_errors);
1046 data[4] = le16_to_cpu(counters->rx_missed);
1047 data[5] = le16_to_cpu(counters->align_errors);
1048 data[6] = le32_to_cpu(counters->tx_one_collision);
1049 data[7] = le32_to_cpu(counters->tx_multi_collision);
1050 data[8] = le64_to_cpu(counters->rx_unicast);
1051 data[9] = le64_to_cpu(counters->rx_broadcast);
1052 data[10] = le32_to_cpu(counters->rx_multicast);
1053 data[11] = le16_to_cpu(counters->tx_aborted);
1054 data[12] = le16_to_cpu(counters->tx_underun);
1055
1056 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1057}
1058
1059static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1060{
1061 switch(stringset) {
1062 case ETH_SS_STATS:
1063 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1064 break;
1065 }
1066}
1067
7282d491 1068static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1069 .get_drvinfo = rtl8169_get_drvinfo,
1070 .get_regs_len = rtl8169_get_regs_len,
1071 .get_link = ethtool_op_get_link,
1072 .get_settings = rtl8169_get_settings,
1073 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1074 .get_msglevel = rtl8169_get_msglevel,
1075 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1076 .get_rx_csum = rtl8169_get_rx_csum,
1077 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1078 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1079 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1080 .set_tso = ethtool_op_set_tso,
1081 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1082 .get_wol = rtl8169_get_wol,
1083 .set_wol = rtl8169_set_wol,
d4a3a0fc 1084 .get_strings = rtl8169_get_strings,
b9f2c044 1085 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1086 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1087};
1088
07d3f51f
FR		 1089static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1090 int bitnum, int bitval)
1da177e4
LT		 1091{
1092 int val;
1093
1094 val = mdio_read(ioaddr, reg);
1095 val = (bitval == 1) ?
1096 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1097 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1098}
1099
07d3f51f
FR		 1100static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1101 void __iomem *ioaddr)
1da177e4 1102{
0e485150
FR		 1103 /*
1104 * The driver currently handles the 8168Bf and the 8168Be identically
1105 * but they can be identified more specifically through the test below
1106 * if needed:
1107 *
1108 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1109 *
1110 * Same thing for the 8101Eb and the 8101Ec:
1111 *
1112 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1113 */
1da177e4
LT		 1114 const struct {
1115 u32 mask;
1116 int mac_version;
1117 } mac_info[] = {
bcf0bf90
FR		 1118 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1119 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1120 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1121 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1122 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1123 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1124 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1125 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1126 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1127 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1128 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1129 }, *p = mac_info;
1130 u32 reg;
1131
6dccd16b 1132 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1133 while ((reg & p->mask) != p->mask)
1134 p++;
1135 tp->mac_version = p->mac_version;
1136}
1137
1138static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1139{
bcf0bf90 1140 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1141}
1142
07d3f51f
FR		 1143static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1144 void __iomem *ioaddr)
1da177e4
LT		 1145{
1146 const struct {
1147 u16 mask;
1148 u16 set;
1149 int phy_version;
1150 } phy_info[] = {
1151 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1152 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1153 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1154 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1155 }, *p = phy_info;
1156 u16 reg;
1157
64e4bfb4 1158 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1159 while ((reg & p->mask) != p->set)
1160 p++;
1161 tp->phy_version = p->phy_version;
1162}
1163
1164static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1165{
1166 struct {
1167 int version;
1168 char *msg;
1169 u32 reg;
1170 } phy_print[] = {
1171 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1172 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1173 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1174 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1175 { 0, NULL, 0x0000 }
1176 }, *p;
1177
1178 for (p = phy_print; p->msg; p++) {
1179 if (tp->phy_version == p->version) {
1180 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1181 return;
1182 }
1183 }
1184 dprintk("phy_version == Unknown\n");
1185}
1186
1187static void rtl8169_hw_phy_config(struct net_device *dev)
1188{
1189 struct rtl8169_private *tp = netdev_priv(dev);
1190 void __iomem *ioaddr = tp->mmio_addr;
1191 struct {
1192 u16 regs[5]; /* Beware of bit-sign propagation */
1193 } phy_magic[5] = { {
1194 { 0x0000, //w 4 15 12 0
1195 0x00a1, //w 3 15 0 00a1
1196 0x0008, //w 2 15 0 0008
1197 0x1020, //w 1 15 0 1020
1198 0x1000 } },{ //w 0 15 0 1000
1199 { 0x7000, //w 4 15 12 7
1200 0xff41, //w 3 15 0 ff41
1201 0xde60, //w 2 15 0 de60
1202 0x0140, //w 1 15 0 0140
1203 0x0077 } },{ //w 0 15 0 0077
1204 { 0xa000, //w 4 15 12 a
1205 0xdf01, //w 3 15 0 df01
1206 0xdf20, //w 2 15 0 df20
1207 0xff95, //w 1 15 0 ff95
1208 0xfa00 } },{ //w 0 15 0 fa00
1209 { 0xb000, //w 4 15 12 b
1210 0xff41, //w 3 15 0 ff41
1211 0xde20, //w 2 15 0 de20
1212 0x0140, //w 1 15 0 0140
1213 0x00bb } },{ //w 0 15 0 00bb
1214 { 0xf000, //w 4 15 12 f
1215 0xdf01, //w 3 15 0 df01
1216 0xdf20, //w 2 15 0 df20
1217 0xff95, //w 1 15 0 ff95
1218 0xbf00 } //w 0 15 0 bf00
1219 }
1220 }, *p = phy_magic;
07d3f51f 1221 unsigned int i;
1da177e4
LT		 1222
1223 rtl8169_print_mac_version(tp);
1224 rtl8169_print_phy_version(tp);
1225
bcf0bf90 1226 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1227 return;
1228 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1229 return;
1230
1231 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1232 dprintk("Do final_reg2.cfg\n");
1233
1234 /* Shazam ! */
1235
bcf0bf90 1236 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1237 mdio_write(ioaddr, 31, 0x0002);
1238 mdio_write(ioaddr, 1, 0x90d0);
1239 mdio_write(ioaddr, 31, 0x0000);
1240 return;
1241 }
1242
65d916d9
EH		 1243 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1244 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1245 return;
1246
1da177e4
LT		 1247 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1248 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1249 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1250 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1251
1252 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1253 int val, pos = 4;
1254
1255 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1256 mdio_write(ioaddr, pos, val);
1257 while (--pos >= 0)
1258 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1259 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1260 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1261 }
1262 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1263}
1264
1265static void rtl8169_phy_timer(unsigned long __opaque)
1266{
1267 struct net_device *dev = (struct net_device *)__opaque;
1268 struct rtl8169_private *tp = netdev_priv(dev);
1269 struct timer_list *timer = &tp->timer;
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1272
bcf0bf90 1273 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1274 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1275
64e4bfb4 1276 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1277 return;
1278
1279 spin_lock_irq(&tp->lock);
1280
1281 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1282 /*
1da177e4
LT		 1283 * A busy loop could burn quite a few cycles on nowadays CPU.
1284 * Let's delay the execution of the timer for a few ticks.
1285 */
1286 timeout = HZ/10;
1287 goto out_mod_timer;
1288 }
1289
1290 if (tp->link_ok(ioaddr))
1291 goto out_unlock;
1292
b57b7e5a
SH		 1293 if (netif_msg_link(tp))
1294 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1295
1296 tp->phy_reset_enable(ioaddr);
1297
1298out_mod_timer:
1299 mod_timer(timer, jiffies + timeout);
1300out_unlock:
1301 spin_unlock_irq(&tp->lock);
1302}
1303
1304static inline void rtl8169_delete_timer(struct net_device *dev)
1305{
1306 struct rtl8169_private *tp = netdev_priv(dev);
1307 struct timer_list *timer = &tp->timer;
1308
bcf0bf90 1309 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1310 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1311 return;
1312
1313 del_timer_sync(timer);
1314}
1315
1316static inline void rtl8169_request_timer(struct net_device *dev)
1317{
1318 struct rtl8169_private *tp = netdev_priv(dev);
1319 struct timer_list *timer = &tp->timer;
1320
bcf0bf90 1321 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1322 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1323 return;
1324
2efa53f3 1325 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1326}
1327
1328#ifdef CONFIG_NET_POLL_CONTROLLER
1329/*
1330 * Polling 'interrupt' - used by things like netconsole to send skbs
1331 * without having to re-enable interrupts. It's not called while
1332 * the interrupt routine is executing.
1333 */
1334static void rtl8169_netpoll(struct net_device *dev)
1335{
1336 struct rtl8169_private *tp = netdev_priv(dev);
1337 struct pci_dev *pdev = tp->pci_dev;
1338
1339 disable_irq(pdev->irq);
7d12e780 1340 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1341 enable_irq(pdev->irq);
1342}
1343#endif
1344
1345static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1346 void __iomem *ioaddr)
1347{
1348 iounmap(ioaddr);
1349 pci_release_regions(pdev);
1350 pci_disable_device(pdev);
1351 free_netdev(dev);
1352}
1353
bf793295
FR		 1354static void rtl8169_phy_reset(struct net_device *dev,
1355 struct rtl8169_private *tp)
1356{
1357 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1358 unsigned int i;
bf793295
FR		 1359
1360 tp->phy_reset_enable(ioaddr);
1361 for (i = 0; i < 100; i++) {
1362 if (!tp->phy_reset_pending(ioaddr))
1363 return;
1364 msleep(1);
1365 }
1366 if (netif_msg_link(tp))
1367 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1368}
1369
4ff96fa6
FR		 1370static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1371{
1372 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1373
1374 rtl8169_hw_phy_config(dev);
1375
1376 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1377 RTL_W8(0x82, 0x01);
1378
6dccd16b
FR		 1379 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1380
1381 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1382 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1383
bcf0bf90 1384 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1385 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1386 RTL_W8(0x82, 0x01);
1387 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1388 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1389 }
1390
bf793295
FR		 1391 rtl8169_phy_reset(dev, tp);
1392
901dda2b
FR		 1393 /*
1394 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1395 * only 8101. Don't panic.
1396 */
1397 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1398
1399 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1400 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1401}
1402
773d2021
FR		 1403static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1404{
1405 void __iomem *ioaddr = tp->mmio_addr;
1406 u32 high;
1407 u32 low;
1408
1409 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1410 high = addr[4] | (addr[5] << 8);
1411
1412 spin_lock_irq(&tp->lock);
1413
1414 RTL_W8(Cfg9346, Cfg9346_Unlock);
1415 RTL_W32(MAC0, low);
1416 RTL_W32(MAC4, high);
1417 RTL_W8(Cfg9346, Cfg9346_Lock);
1418
1419 spin_unlock_irq(&tp->lock);
1420}
1421
1422static int rtl_set_mac_address(struct net_device *dev, void *p)
1423{
1424 struct rtl8169_private *tp = netdev_priv(dev);
1425 struct sockaddr *addr = p;
1426
1427 if (!is_valid_ether_addr(addr->sa_data))
1428 return -EADDRNOTAVAIL;
1429
1430 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1431
1432 rtl_rar_set(tp, dev->dev_addr);
1433
1434 return 0;
1435}
1436
5f787a1a
FR		 1437static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1438{
1439 struct rtl8169_private *tp = netdev_priv(dev);
1440 struct mii_ioctl_data *data = if_mii(ifr);
1441
1442 if (!netif_running(dev))
1443 return -ENODEV;
1444
1445 switch (cmd) {
1446 case SIOCGMIIPHY:
1447 data->phy_id = 32; /* Internal PHY */
1448 return 0;
1449
1450 case SIOCGMIIREG:
1451 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1452 return 0;
1453
1454 case SIOCSMIIREG:
1455 if (!capable(CAP_NET_ADMIN))
1456 return -EPERM;
1457 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1458 return 0;
1459 }
1460 return -EOPNOTSUPP;
1461}
1462
0e485150
FR		 1463static const struct rtl_cfg_info {
1464 void (*hw_start)(struct net_device *);
1465 unsigned int region;
1466 unsigned int align;
1467 u16 intr_event;
1468 u16 napi_event;
fbac58fc 1469 unsigned msi;
0e485150
FR		 1470} rtl_cfg_infos [] = {
1471 [RTL_CFG_0] = {
1472 .hw_start = rtl_hw_start_8169,
1473 .region = 1,
e9f63f30 1474 .align = 0,
0e485150
FR		 1475 .intr_event = SYSErr | LinkChg | RxOverflow |
1476 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1477 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1478 .msi = 0
0e485150
FR		 1479 },
1480 [RTL_CFG_1] = {
1481 .hw_start = rtl_hw_start_8168,
1482 .region = 2,
1483 .align = 8,
1484 .intr_event = SYSErr | LinkChg | RxOverflow |
1485 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1486 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1487 .msi = RTL_FEATURE_MSI
0e485150
FR		 1488 },
1489 [RTL_CFG_2] = {
1490 .hw_start = rtl_hw_start_8101,
1491 .region = 2,
1492 .align = 8,
1493 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1494 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1495 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1496 .msi = RTL_FEATURE_MSI
0e485150
FR		 1497 }
1498};
1499
fbac58fc
FR		 1500/* Cfg9346_Unlock assumed. */
1501static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1502 const struct rtl_cfg_info *cfg)
1503{
1504 unsigned msi = 0;
1505 u8 cfg2;
1506
1507 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1508 if (cfg->msi) {
1509 if (pci_enable_msi(pdev)) {
1510 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1511 } else {
1512 cfg2 |= MSIEnable;
1513 msi = RTL_FEATURE_MSI;
1514 }
1515 }
1516 RTL_W8(Config2, cfg2);
1517 return msi;
1518}
1519
1520static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1521{
1522 if (tp->features & RTL_FEATURE_MSI) {
1523 pci_disable_msi(pdev);
1524 tp->features &= ~RTL_FEATURE_MSI;
1525 }
1526}
1527
1da177e4 1528static int __devinit
4ff96fa6 1529rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1530{
0e485150
FR		 1531 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1532 const unsigned int region = cfg->region;
1da177e4 1533 struct rtl8169_private *tp;
4ff96fa6
FR		 1534 struct net_device *dev;
1535 void __iomem *ioaddr;
07d3f51f
FR		 1536 unsigned int i;
1537 int rc;
1da177e4 1538
4ff96fa6
FR		 1539 if (netif_msg_drv(&debug)) {
1540 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1541 MODULENAME, RTL8169_VERSION);
1542 }
1da177e4 1543
1da177e4 1544 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1545 if (!dev) {
b57b7e5a 1546 if (netif_msg_drv(&debug))
9b91cf9d 1547 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1548 rc = -ENOMEM;
1549 goto out;
1da177e4
LT		 1550 }
1551
1da177e4
LT		 1552 SET_NETDEV_DEV(dev, &pdev->dev);
1553 tp = netdev_priv(dev);
c4028958 1554 tp->dev = dev;
b57b7e5a 1555 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1556
1557 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1558 rc = pci_enable_device(pdev);
b57b7e5a 1559 if (rc < 0) {
2e8a538d 1560 if (netif_msg_probe(tp))
9b91cf9d 1561 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1562 goto err_out_free_dev_1;
1da177e4
LT		 1563 }
1564
1565 rc = pci_set_mwi(pdev);
1566 if (rc < 0)
4ff96fa6 1567 goto err_out_disable_2;
1da177e4 1568
1da177e4 1569 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1570 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1571 if (netif_msg_probe(tp)) {
9b91cf9d 1572 dev_err(&pdev->dev,
bcf0bf90
FR		 1573 "region #%d not an MMIO resource, aborting\n",
1574 region);
4ff96fa6 1575 }
1da177e4 1576 rc = -ENODEV;
4ff96fa6 1577 goto err_out_mwi_3;
1da177e4 1578 }
4ff96fa6 1579
1da177e4 1580 /* check for weird/broken PCI region reporting */
bcf0bf90 1581 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1582 if (netif_msg_probe(tp)) {
9b91cf9d 1583 dev_err(&pdev->dev,
4ff96fa6
FR		 1584 "Invalid PCI region size(s), aborting\n");
1585 }
1da177e4 1586 rc = -ENODEV;
4ff96fa6 1587 goto err_out_mwi_3;
1da177e4
LT		 1588 }
1589
1590 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1591 if (rc < 0) {
2e8a538d 1592 if (netif_msg_probe(tp))
9b91cf9d 1593 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1594 goto err_out_mwi_3;
1da177e4
LT		 1595 }
1596
1597 tp->cp_cmd = PCIMulRW | RxChkSum;
1598
1599 if ((sizeof(dma_addr_t) > 4) &&
1600 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1601 tp->cp_cmd |= PCIDAC;
1602 dev->features |= NETIF_F_HIGHDMA;
1603 } else {
1604 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1605 if (rc < 0) {
4ff96fa6 1606 if (netif_msg_probe(tp)) {
9b91cf9d 1607 dev_err(&pdev->dev,
4ff96fa6
FR		 1608 "DMA configuration failed.\n");
1609 }
1610 goto err_out_free_res_4;
1da177e4
LT		 1611 }
1612 }
1613
1614 pci_set_master(pdev);
1615
1616 /* ioremap MMIO region */
bcf0bf90 1617 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1618 if (!ioaddr) {
b57b7e5a 1619 if (netif_msg_probe(tp))
9b91cf9d 1620 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1621 rc = -EIO;
4ff96fa6 1622 goto err_out_free_res_4;
1da177e4
LT		 1623 }
1624
1625 /* Unneeded ? Don't mess with Mrs. Murphy. */
1626 rtl8169_irq_mask_and_ack(ioaddr);
1627
1628 /* Soft reset the chip. */
1629 RTL_W8(ChipCmd, CmdReset);
1630
1631 /* Check that the chip has finished the reset. */
07d3f51f 1632 for (i = 0; i < 100; i++) {
1da177e4
LT		 1633 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1634 break;
b518fa8e 1635 msleep_interruptible(1);
1da177e4
LT		 1636 }
1637
1638 /* Identify chip attached to board */
1639 rtl8169_get_mac_version(tp, ioaddr);
1640 rtl8169_get_phy_version(tp, ioaddr);
1641
1642 rtl8169_print_mac_version(tp);
1643 rtl8169_print_phy_version(tp);
1644
1645 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1646 if (tp->mac_version == rtl_chip_info[i].mac_version)
1647 break;
1648 }
1649 if (i < 0) {
1650 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1651 if (netif_msg_probe(tp)) {
2e8a538d 1652 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1653 "unknown chip version, assuming %s\n",
1654 rtl_chip_info[0].name);
b57b7e5a 1655 }
1da177e4
LT		 1656 i++;
1657 }
1658 tp->chipset = i;
1659
5d06a99f
FR		 1660 RTL_W8(Cfg9346, Cfg9346_Unlock);
1661 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1662 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1663 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1664 RTL_W8(Cfg9346, Cfg9346_Lock);
1665
1da177e4
LT		 1666 if (RTL_R8(PHYstatus) & TBI_Enable) {
1667 tp->set_speed = rtl8169_set_speed_tbi;
1668 tp->get_settings = rtl8169_gset_tbi;
1669 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1670 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1671 tp->link_ok = rtl8169_tbi_link_ok;
1672
64e4bfb4 1673 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1674 } else {
1675 tp->set_speed = rtl8169_set_speed_xmii;
1676 tp->get_settings = rtl8169_gset_xmii;
1677 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1678 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1679 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1680
1681 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1682 }
1683
1684 /* Get MAC address. FIXME: read EEPROM */
1685 for (i = 0; i < MAC_ADDR_LEN; i++)
1686 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1687 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1688
1689 dev->open = rtl8169_open;
1690 dev->hard_start_xmit = rtl8169_start_xmit;
1691 dev->get_stats = rtl8169_get_stats;
1692 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1693 dev->stop = rtl8169_close;
1694 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1695 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1696 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1697 dev->irq = pdev->irq;
1698 dev->base_addr = (unsigned long) ioaddr;
1699 dev->change_mtu = rtl8169_change_mtu;
773d2021 1700 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1701
1702#ifdef CONFIG_R8169_NAPI
bea3348e 1703 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1704#endif
1705
1706#ifdef CONFIG_R8169_VLAN
1707 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1708 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1709#endif
1710
1711#ifdef CONFIG_NET_POLL_CONTROLLER
1712 dev->poll_controller = rtl8169_netpoll;
1713#endif
1714
1715 tp->intr_mask = 0xffff;
1716 tp->pci_dev = pdev;
1717 tp->mmio_addr = ioaddr;
0e485150
FR		 1718 tp->align = cfg->align;
1719 tp->hw_start = cfg->hw_start;
1720 tp->intr_event = cfg->intr_event;
1721 tp->napi_event = cfg->napi_event;
1da177e4 1722
2efa53f3
FR		 1723 init_timer(&tp->timer);
1724 tp->timer.data = (unsigned long) dev;
1725 tp->timer.function = rtl8169_phy_timer;
1726
1da177e4
LT		 1727 spin_lock_init(&tp->lock);
1728
1729 rc = register_netdev(dev);
4ff96fa6 1730 if (rc < 0)
fbac58fc 1731 goto err_out_msi_5;
1da177e4
LT		 1732
1733 pci_set_drvdata(pdev, dev);
1734
b57b7e5a 1735 if (netif_msg_probe(tp)) {
96b9709c
FR		 1736 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1737
b57b7e5a
SH		 1738 printk(KERN_INFO "%s: %s at 0x%lx, "
1739 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1740 "XID %08x IRQ %d\n",
b57b7e5a 1741 dev->name,
bcf0bf90 1742 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1743 dev->base_addr,
1744 dev->dev_addr[0], dev->dev_addr[1],
1745 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1746 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1747 }
1da177e4 1748
4ff96fa6 1749 rtl8169_init_phy(dev, tp);
1da177e4 1750
4ff96fa6
FR		 1751out:
1752 return rc;
1da177e4 1753
fbac58fc
FR		 1754err_out_msi_5:
1755 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1756 iounmap(ioaddr);
1757err_out_free_res_4:
1758 pci_release_regions(pdev);
1759err_out_mwi_3:
1760 pci_clear_mwi(pdev);
1761err_out_disable_2:
1762 pci_disable_device(pdev);
1763err_out_free_dev_1:
1764 free_netdev(dev);
1765 goto out;
1da177e4
LT		 1766}
1767
07d3f51f 1768static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1769{
1770 struct net_device *dev = pci_get_drvdata(pdev);
1771 struct rtl8169_private *tp = netdev_priv(dev);
1772
eb2a021c
FR		 1773 flush_scheduled_work();
1774
1da177e4 1775 unregister_netdev(dev);
fbac58fc 1776 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1777 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1778 pci_set_drvdata(pdev, NULL);
1779}
1780
1da177e4
LT		 1781static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1782 struct net_device *dev)
1783{
1784 unsigned int mtu = dev->mtu;
1785
1786 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1787}
1788
1789static int rtl8169_open(struct net_device *dev)
1790{
1791 struct rtl8169_private *tp = netdev_priv(dev);
1792 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1793 int retval = -ENOMEM;
1da177e4 1794
1da177e4 1795
99f252b0 1796 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1797
1798 /*
1799 * Rx and Tx desscriptors needs 256 bytes alignment.
1800 * pci_alloc_consistent provides more.
1801 */
1802 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1803 &tp->TxPhyAddr);
1804 if (!tp->TxDescArray)
99f252b0 1805 goto out;
1da177e4
LT		 1806
1807 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1808 &tp->RxPhyAddr);
1809 if (!tp->RxDescArray)
99f252b0 1810 goto err_free_tx_0;
1da177e4
LT		 1811
1812 retval = rtl8169_init_ring(dev);
1813 if (retval < 0)
99f252b0 1814 goto err_free_rx_1;
1da177e4 1815
c4028958 1816 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1817
99f252b0
FR		 1818 smp_mb();
1819
fbac58fc
FR		 1820 retval = request_irq(dev->irq, rtl8169_interrupt,
1821 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1822 dev->name, dev);
1823 if (retval < 0)
1824 goto err_release_ring_2;
1825
bea3348e
SH		 1826#ifdef CONFIG_R8169_NAPI
1827 napi_enable(&tp->napi);
1828#endif
1829
07ce4064 1830 rtl_hw_start(dev);
1da177e4
LT		 1831
1832 rtl8169_request_timer(dev);
1833
1834 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1835out:
1836 return retval;
1837
99f252b0
FR		 1838err_release_ring_2:
1839 rtl8169_rx_clear(tp);
1840err_free_rx_1:
1da177e4
LT		 1841 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1842 tp->RxPhyAddr);
99f252b0 1843err_free_tx_0:
1da177e4
LT		 1844 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1845 tp->TxPhyAddr);
1da177e4
LT		 1846 goto out;
1847}
1848
1849static void rtl8169_hw_reset(void __iomem *ioaddr)
1850{
1851 /* Disable interrupts */
1852 rtl8169_irq_mask_and_ack(ioaddr);
1853
1854 /* Reset the chipset */
1855 RTL_W8(ChipCmd, CmdReset);
1856
1857 /* PCI commit */
1858 RTL_R8(ChipCmd);
1859}
1860
7f796d83 1861static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1862{
1863 void __iomem *ioaddr = tp->mmio_addr;
1864 u32 cfg = rtl8169_rx_config;
1865
1866 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1867 RTL_W32(RxConfig, cfg);
1868
1869 /* Set DMA burst size and Interframe Gap Time */
1870 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1871 (InterFrameGap << TxInterFrameGapShift));
1872}
1873
07ce4064 1874static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1875{
1876 struct rtl8169_private *tp = netdev_priv(dev);
1877 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1878 unsigned int i;
1da177e4
LT		 1879
1880 /* Soft reset the chip. */
1881 RTL_W8(ChipCmd, CmdReset);
1882
1883 /* Check that the chip has finished the reset. */
07d3f51f 1884 for (i = 0; i < 100; i++) {
1da177e4
LT		 1885 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1886 break;
b518fa8e 1887 msleep_interruptible(1);
1da177e4
LT		 1888 }
1889
07ce4064
FR		 1890 tp->hw_start(dev);
1891
07ce4064
FR		 1892 netif_start_queue(dev);
1893}
1894
1895
7f796d83
FR		 1896static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1897 void __iomem *ioaddr)
1898{
1899 /*
1900 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1901 * register to be written before TxDescAddrLow to work.
1902 * Switching from MMIO to I/O access fixes the issue as well.
1903 */
1904 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1905 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1906 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1907 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1908}
1909
1910static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1911{
1912 u16 cmd;
1913
1914 cmd = RTL_R16(CPlusCmd);
1915 RTL_W16(CPlusCmd, cmd);
1916 return cmd;
1917}
1918
1919static void rtl_set_rx_max_size(void __iomem *ioaddr)
1920{
1921 /* Low hurts. Let's disable the filtering. */
1922 RTL_W16(RxMaxSize, 16383);
1923}
1924
6dccd16b
FR		 1925static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1926{
1927 struct {
1928 u32 mac_version;
1929 u32 clk;
1930 u32 val;
1931 } cfg2_info [] = {
1932 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1933 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1934 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1935 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1936 }, *p = cfg2_info;
1937 unsigned int i;
1938 u32 clk;
1939
1940 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1941 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1942 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1943 RTL_W32(0x7c, p->val);
1944 break;
1945 }
1946 }
1947}
1948
07ce4064
FR		 1949static void rtl_hw_start_8169(struct net_device *dev)
1950{
1951 struct rtl8169_private *tp = netdev_priv(dev);
1952 void __iomem *ioaddr = tp->mmio_addr;
1953 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1954
9cb427b6
FR		 1955 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1956 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1957 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1958 }
1959
1da177e4 1960 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1961 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1962 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1963 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1964 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1965 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1966
1da177e4
LT		 1967 RTL_W8(EarlyTxThres, EarlyTxThld);
1968
7f796d83 1969 rtl_set_rx_max_size(ioaddr);
1da177e4 1970
c946b304
FR		 1971 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1972 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1973 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1974 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1975 rtl_set_rx_tx_config_registers(tp);
1da177e4 1976
7f796d83 1977 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1978
bcf0bf90
FR		 1979 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1980 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 1981 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 1982 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1983 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1984 }
1985
bcf0bf90
FR		 1986 RTL_W16(CPlusCmd, tp->cp_cmd);
1987
6dccd16b
FR		 1988 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1989
1da177e4
LT		 1990 /*
1991 * Undocumented corner. Supposedly:
1992 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1993 */
1994 RTL_W16(IntrMitigate, 0x0000);
1995
7f796d83 1996 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1997
c946b304
FR		 1998 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1999 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2000 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2001 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2002 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2003 rtl_set_rx_tx_config_registers(tp);
2004 }
2005
1da177e4 2006 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2007
2008 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2009 RTL_R8(IntrMask);
1da177e4
LT		 2010
2011 RTL_W32(RxMissed, 0);
2012
07ce4064 2013 rtl_set_rx_mode(dev);
1da177e4
LT		 2014
2015 /* no early-rx interrupts */
2016 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2017
2018 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2019 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2020}
1da177e4 2021
07ce4064
FR		 2022static void rtl_hw_start_8168(struct net_device *dev)
2023{
2dd99530
FR		 2024 struct rtl8169_private *tp = netdev_priv(dev);
2025 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2026 struct pci_dev *pdev = tp->pci_dev;
2027 u8 ctl;
2dd99530
FR		 2028
2029 RTL_W8(Cfg9346, Cfg9346_Unlock);
2030
2031 RTL_W8(EarlyTxThres, EarlyTxThld);
2032
2033 rtl_set_rx_max_size(ioaddr);
2034
0e485150
FR		 2035 rtl_set_rx_tx_config_registers(tp);
2036
2037 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2038
2039 RTL_W16(CPlusCmd, tp->cp_cmd);
2040
0e485150
FR		 2041 /* Tx performance tweak. */
2042 pci_read_config_byte(pdev, 0x69, &ctl);
2043 ctl = (ctl & ~0x70) | 0x50;
2044 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2045
0e485150 2046 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2047
0e485150
FR		 2048 /* Work around for RxFIFO overflow. */
2049 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2050 tp->intr_event |= RxFIFOOver | PCSTimeout;
2051 tp->intr_event &= ~RxOverflow;
2052 }
2053
2054 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2055
2056 RTL_W8(Cfg9346, Cfg9346_Lock);
2057
2058 RTL_R8(IntrMask);
2059
2060 RTL_W32(RxMissed, 0);
2061
2062 rtl_set_rx_mode(dev);
2063
0e485150
FR		 2064 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2065
2dd99530 2066 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2067
0e485150 2068 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2069}
1da177e4 2070
07ce4064
FR		 2071static void rtl_hw_start_8101(struct net_device *dev)
2072{
cdf1a608
FR		 2073 struct rtl8169_private *tp = netdev_priv(dev);
2074 void __iomem *ioaddr = tp->mmio_addr;
2075 struct pci_dev *pdev = tp->pci_dev;
2076
2077 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2078 pci_write_config_word(pdev, 0x68, 0x00);
2079 pci_write_config_word(pdev, 0x69, 0x08);
2080 }
2081
2082 RTL_W8(Cfg9346, Cfg9346_Unlock);
2083
2084 RTL_W8(EarlyTxThres, EarlyTxThld);
2085
2086 rtl_set_rx_max_size(ioaddr);
2087
2088 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2089
2090 RTL_W16(CPlusCmd, tp->cp_cmd);
2091
2092 RTL_W16(IntrMitigate, 0x0000);
2093
2094 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2095
2096 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2097 rtl_set_rx_tx_config_registers(tp);
2098
2099 RTL_W8(Cfg9346, Cfg9346_Lock);
2100
2101 RTL_R8(IntrMask);
2102
2103 RTL_W32(RxMissed, 0);
2104
2105 rtl_set_rx_mode(dev);
2106
0e485150
FR		 2107 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2108
cdf1a608 2109 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2110
0e485150 2111 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2112}
2113
2114static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2115{
2116 struct rtl8169_private *tp = netdev_priv(dev);
2117 int ret = 0;
2118
2119 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2120 return -EINVAL;
2121
2122 dev->mtu = new_mtu;
2123
2124 if (!netif_running(dev))
2125 goto out;
2126
2127 rtl8169_down(dev);
2128
2129 rtl8169_set_rxbufsize(tp, dev);
2130
2131 ret = rtl8169_init_ring(dev);
2132 if (ret < 0)
2133 goto out;
2134
bea3348e
SH		 2135#ifdef CONFIG_R8169_NAPI
2136 napi_enable(&tp->napi);
2137#endif
1da177e4 2138
07ce4064 2139 rtl_hw_start(dev);
1da177e4
LT		 2140
2141 rtl8169_request_timer(dev);
2142
2143out:
2144 return ret;
2145}
2146
2147static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2148{
2149 desc->addr = 0x0badbadbadbadbadull;
2150 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2151}
2152
2153static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2154 struct sk_buff **sk_buff, struct RxDesc *desc)
2155{
2156 struct pci_dev *pdev = tp->pci_dev;
2157
2158 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2159 PCI_DMA_FROMDEVICE);
2160 dev_kfree_skb(*sk_buff);
2161 *sk_buff = NULL;
2162 rtl8169_make_unusable_by_asic(desc);
2163}
2164
2165static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2166{
2167 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2168
2169 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2170}
2171
2172static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2173 u32 rx_buf_sz)
2174{
2175 desc->addr = cpu_to_le64(mapping);
2176 wmb();
2177 rtl8169_mark_to_asic(desc, rx_buf_sz);
2178}
2179
15d31758
SH		 2180static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2181 struct net_device *dev,
2182 struct RxDesc *desc, int rx_buf_sz,
2183 unsigned int align)
1da177e4
LT		 2184{
2185 struct sk_buff *skb;
2186 dma_addr_t mapping;
e9f63f30 2187 unsigned int pad;
1da177e4 2188
e9f63f30
FR		 2189 pad = align ? align : NET_IP_ALIGN;
2190
2191 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2192 if (!skb)
2193 goto err_out;
2194
e9f63f30 2195 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2196
689be439 2197 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2198 PCI_DMA_FROMDEVICE);
2199
2200 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2201out:
15d31758 2202 return skb;
1da177e4
LT		 2203
2204err_out:
1da177e4
LT		 2205 rtl8169_make_unusable_by_asic(desc);
2206 goto out;
2207}
2208
2209static void rtl8169_rx_clear(struct rtl8169_private *tp)
2210{
07d3f51f 2211 unsigned int i;
1da177e4
LT		 2212
2213 for (i = 0; i < NUM_RX_DESC; i++) {
2214 if (tp->Rx_skbuff[i]) {
2215 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2216 tp->RxDescArray + i);
2217 }
2218 }
2219}
2220
2221static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2222 u32 start, u32 end)
2223{
2224 u32 cur;
5b0384f4 2225
4ae47c2d 2226 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2227 struct sk_buff *skb;
2228 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2229
4ae47c2d
FR		 2230 WARN_ON((s32)(end - cur) < 0);
2231
1da177e4
LT		 2232 if (tp->Rx_skbuff[i])
2233 continue;
bcf0bf90 2234
15d31758
SH		 2235 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2236 tp->RxDescArray + i,
2237 tp->rx_buf_sz, tp->align);
2238 if (!skb)
1da177e4 2239 break;
15d31758
SH		 2240
2241 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2242 }
2243 return cur - start;
2244}
2245
2246static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2247{
2248 desc->opts1 |= cpu_to_le32(RingEnd);
2249}
2250
2251static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2252{
2253 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2254}
2255
2256static int rtl8169_init_ring(struct net_device *dev)
2257{
2258 struct rtl8169_private *tp = netdev_priv(dev);
2259
2260 rtl8169_init_ring_indexes(tp);
2261
2262 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2263 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2264
2265 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2266 goto err_out;
2267
2268 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2269
2270 return 0;
2271
2272err_out:
2273 rtl8169_rx_clear(tp);
2274 return -ENOMEM;
2275}
2276
2277static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2278 struct TxDesc *desc)
2279{
2280 unsigned int len = tx_skb->len;
2281
2282 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2283 desc->opts1 = 0x00;
2284 desc->opts2 = 0x00;
2285 desc->addr = 0x00;
2286 tx_skb->len = 0;
2287}
2288
2289static void rtl8169_tx_clear(struct rtl8169_private *tp)
2290{
2291 unsigned int i;
2292
2293 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2294 unsigned int entry = i % NUM_TX_DESC;
2295 struct ring_info *tx_skb = tp->tx_skb + entry;
2296 unsigned int len = tx_skb->len;
2297
2298 if (len) {
2299 struct sk_buff *skb = tx_skb->skb;
2300
2301 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2302 tp->TxDescArray + entry);
2303 if (skb) {
2304 dev_kfree_skb(skb);
2305 tx_skb->skb = NULL;
2306 }
cebf8cc7 2307 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2308 }
2309 }
2310 tp->cur_tx = tp->dirty_tx = 0;
2311}
2312
c4028958 2313static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2314{
2315 struct rtl8169_private *tp = netdev_priv(dev);
2316
c4028958 2317 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2318 schedule_delayed_work(&tp->task, 4);
2319}
2320
2321static void rtl8169_wait_for_quiescence(struct net_device *dev)
2322{
2323 struct rtl8169_private *tp = netdev_priv(dev);
2324 void __iomem *ioaddr = tp->mmio_addr;
2325
2326 synchronize_irq(dev->irq);
2327
2328 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2329#ifdef CONFIG_R8169_NAPI
2330 napi_disable(&tp->napi);
2331#endif
1da177e4
LT		 2332
2333 rtl8169_irq_mask_and_ack(ioaddr);
2334
bea3348e
SH		 2335#ifdef CONFIG_R8169_NAPI
2336 napi_enable(&tp->napi);
2337#endif
1da177e4
LT		 2338}
2339
c4028958 2340static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2341{
c4028958
DH		 2342 struct rtl8169_private *tp =
2343 container_of(work, struct rtl8169_private, task.work);
2344 struct net_device *dev = tp->dev;
1da177e4
LT		 2345 int ret;
2346
eb2a021c
FR		 2347 rtnl_lock();
2348
2349 if (!netif_running(dev))
2350 goto out_unlock;
2351
2352 rtl8169_wait_for_quiescence(dev);
2353 rtl8169_close(dev);
1da177e4
LT		 2354
2355 ret = rtl8169_open(dev);
2356 if (unlikely(ret < 0)) {
07d3f51f 2357 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2358 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2359 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2360 }
2361 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2362 }
eb2a021c
FR		 2363
2364out_unlock:
2365 rtnl_unlock();
1da177e4
LT		 2366}
2367
c4028958 2368static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2369{
c4028958
DH		 2370 struct rtl8169_private *tp =
2371 container_of(work, struct rtl8169_private, task.work);
2372 struct net_device *dev = tp->dev;
1da177e4 2373
eb2a021c
FR		 2374 rtnl_lock();
2375
1da177e4 2376 if (!netif_running(dev))
eb2a021c 2377 goto out_unlock;
1da177e4
LT		 2378
2379 rtl8169_wait_for_quiescence(dev);
2380
bea3348e 2381 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2382 rtl8169_tx_clear(tp);
2383
2384 if (tp->dirty_rx == tp->cur_rx) {
2385 rtl8169_init_ring_indexes(tp);
07ce4064 2386 rtl_hw_start(dev);
1da177e4 2387 netif_wake_queue(dev);
cebf8cc7 2388 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2389 } else {
07d3f51f 2390 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2391 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2392 dev->name);
1da177e4
LT		 2393 }
2394 rtl8169_schedule_work(dev, rtl8169_reset_task);
2395 }
eb2a021c
FR		 2396
2397out_unlock:
2398 rtnl_unlock();
1da177e4
LT		 2399}
2400
2401static void rtl8169_tx_timeout(struct net_device *dev)
2402{
2403 struct rtl8169_private *tp = netdev_priv(dev);
2404
2405 rtl8169_hw_reset(tp->mmio_addr);
2406
2407 /* Let's wait a bit while any (async) irq lands on */
2408 rtl8169_schedule_work(dev, rtl8169_reset_task);
2409}
2410
2411static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2412 u32 opts1)
2413{
2414 struct skb_shared_info *info = skb_shinfo(skb);
2415 unsigned int cur_frag, entry;
a6343afb 2416 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2417
2418 entry = tp->cur_tx;
2419 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2420 skb_frag_t *frag = info->frags + cur_frag;
2421 dma_addr_t mapping;
2422 u32 status, len;
2423 void *addr;
2424
2425 entry = (entry + 1) % NUM_TX_DESC;
2426
2427 txd = tp->TxDescArray + entry;
2428 len = frag->size;
2429 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2430 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2431
2432 /* anti gcc 2.95.3 bugware (sic) */
2433 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2434
2435 txd->opts1 = cpu_to_le32(status);
2436 txd->addr = cpu_to_le64(mapping);
2437
2438 tp->tx_skb[entry].len = len;
2439 }
2440
2441 if (cur_frag) {
2442 tp->tx_skb[entry].skb = skb;
2443 txd->opts1 |= cpu_to_le32(LastFrag);
2444 }
2445
2446 return cur_frag;
2447}
2448
2449static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2450{
2451 if (dev->features & NETIF_F_TSO) {
7967168c 2452 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2453
2454 if (mss)
2455 return LargeSend | ((mss & MSSMask) << MSSShift);
2456 }
84fa7933 2457 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2458 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2459
2460 if (ip->protocol == IPPROTO_TCP)
2461 return IPCS | TCPCS;
2462 else if (ip->protocol == IPPROTO_UDP)
2463 return IPCS | UDPCS;
2464 WARN_ON(1); /* we need a WARN() */
2465 }
2466 return 0;
2467}
2468
2469static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2470{
2471 struct rtl8169_private *tp = netdev_priv(dev);
2472 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2473 struct TxDesc *txd = tp->TxDescArray + entry;
2474 void __iomem *ioaddr = tp->mmio_addr;
2475 dma_addr_t mapping;
2476 u32 status, len;
2477 u32 opts1;
188f4af0 2478 int ret = NETDEV_TX_OK;
5b0384f4 2479
1da177e4 2480 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2481 if (netif_msg_drv(tp)) {
2482 printk(KERN_ERR
2483 "%s: BUG! Tx Ring full when queue awake!\n",
2484 dev->name);
2485 }
1da177e4
LT		 2486 goto err_stop;
2487 }
2488
2489 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2490 goto err_stop;
2491
2492 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2493
2494 frags = rtl8169_xmit_frags(tp, skb, opts1);
2495 if (frags) {
2496 len = skb_headlen(skb);
2497 opts1 |= FirstFrag;
2498 } else {
2499 len = skb->len;
2500
2501 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2502 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2503 goto err_update_stats;
2504 len = ETH_ZLEN;
2505 }
2506
2507 opts1 |= FirstFrag | LastFrag;
2508 tp->tx_skb[entry].skb = skb;
2509 }
2510
2511 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2512
2513 tp->tx_skb[entry].len = len;
2514 txd->addr = cpu_to_le64(mapping);
2515 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2516
2517 wmb();
2518
2519 /* anti gcc 2.95.3 bugware (sic) */
2520 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2521 txd->opts1 = cpu_to_le32(status);
2522
2523 dev->trans_start = jiffies;
2524
2525 tp->cur_tx += frags + 1;
2526
2527 smp_wmb();
2528
275391a4 2529 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2530
2531 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2532 netif_stop_queue(dev);
2533 smp_rmb();
2534 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2535 netif_wake_queue(dev);
2536 }
2537
2538out:
2539 return ret;
2540
2541err_stop:
2542 netif_stop_queue(dev);
188f4af0 2543 ret = NETDEV_TX_BUSY;
1da177e4 2544err_update_stats:
cebf8cc7 2545 dev->stats.tx_dropped++;
1da177e4
LT		 2546 goto out;
2547}
2548
2549static void rtl8169_pcierr_interrupt(struct net_device *dev)
2550{
2551 struct rtl8169_private *tp = netdev_priv(dev);
2552 struct pci_dev *pdev = tp->pci_dev;
2553 void __iomem *ioaddr = tp->mmio_addr;
2554 u16 pci_status, pci_cmd;
2555
2556 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2557 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2558
b57b7e5a
SH		 2559 if (netif_msg_intr(tp)) {
2560 printk(KERN_ERR
2561 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2562 dev->name, pci_cmd, pci_status);
2563 }
1da177e4
LT		 2564
2565 /*
2566 * The recovery sequence below admits a very elaborated explanation:
2567 * - it seems to work;
d03902b8
FR		 2568 * - I did not see what else could be done;
2569 * - it makes iop3xx happy.
1da177e4
LT		 2570 *
2571 * Feel free to adjust to your needs.
2572 */
a27993f3 2573 if (pdev->broken_parity_status)
d03902b8
FR		 2574 pci_cmd &= ~PCI_COMMAND_PARITY;
2575 else
2576 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2577
2578 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2579
2580 pci_write_config_word(pdev, PCI_STATUS,
2581 pci_status & (PCI_STATUS_DETECTED_PARITY |
2582 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2583 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2584
2585 /* The infamous DAC f*ckup only happens at boot time */
2586 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2587 if (netif_msg_intr(tp))
2588 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2589 tp->cp_cmd &= ~PCIDAC;
2590 RTL_W16(CPlusCmd, tp->cp_cmd);
2591 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2592 }
2593
2594 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2595
2596 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2597}
2598
07d3f51f
FR		 2599static void rtl8169_tx_interrupt(struct net_device *dev,
2600 struct rtl8169_private *tp,
2601 void __iomem *ioaddr)
1da177e4
LT		 2602{
2603 unsigned int dirty_tx, tx_left;
2604
1da177e4
LT		 2605 dirty_tx = tp->dirty_tx;
2606 smp_rmb();
2607 tx_left = tp->cur_tx - dirty_tx;
2608
2609 while (tx_left > 0) {
2610 unsigned int entry = dirty_tx % NUM_TX_DESC;
2611 struct ring_info *tx_skb = tp->tx_skb + entry;
2612 u32 len = tx_skb->len;
2613 u32 status;
2614
2615 rmb();
2616 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2617 if (status & DescOwn)
2618 break;
2619
cebf8cc7
FR		 2620 dev->stats.tx_bytes += len;
2621 dev->stats.tx_packets++;
1da177e4
LT		 2622
2623 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2624
2625 if (status & LastFrag) {
2626 dev_kfree_skb_irq(tx_skb->skb);
2627 tx_skb->skb = NULL;
2628 }
2629 dirty_tx++;
2630 tx_left--;
2631 }
2632
2633 if (tp->dirty_tx != dirty_tx) {
2634 tp->dirty_tx = dirty_tx;
2635 smp_wmb();
2636 if (netif_queue_stopped(dev) &&
2637 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2638 netif_wake_queue(dev);
2639 }
d78ae2dc
FR		 2640 /*
2641 * 8168 hack: TxPoll requests are lost when the Tx packets are
2642 * too close. Let's kick an extra TxPoll request when a burst
2643 * of start_xmit activity is detected (if it is not detected,
2644 * it is slow enough). -- FR
2645 */
2646 smp_rmb();
2647 if (tp->cur_tx != dirty_tx)
2648 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2649 }
2650}
2651
126fa4b9
FR		 2652static inline int rtl8169_fragmented_frame(u32 status)
2653{
2654 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2655}
2656
1da177e4
LT		 2657static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2658{
2659 u32 opts1 = le32_to_cpu(desc->opts1);
2660 u32 status = opts1 & RxProtoMask;
2661
2662 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2663 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2664 ((status == RxProtoIP) && !(opts1 & IPFail)))
2665 skb->ip_summed = CHECKSUM_UNNECESSARY;
2666 else
2667 skb->ip_summed = CHECKSUM_NONE;
2668}
2669
07d3f51f
FR		 2670static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2671 struct rtl8169_private *tp, int pkt_size,
2672 dma_addr_t addr)
1da177e4 2673{
b449655f
SH		 2674 struct sk_buff *skb;
2675 bool done = false;
1da177e4 2676
b449655f
SH		 2677 if (pkt_size >= rx_copybreak)
2678 goto out;
1da177e4 2679
07d3f51f 2680 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2681 if (!skb)
2682 goto out;
2683
07d3f51f
FR		 2684 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2685 PCI_DMA_FROMDEVICE);
86402234 2686 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2687 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2688 *sk_buff = skb;
2689 done = true;
2690out:
2691 return done;
1da177e4
LT		 2692}
2693
07d3f51f
FR		 2694static int rtl8169_rx_interrupt(struct net_device *dev,
2695 struct rtl8169_private *tp,
bea3348e 2696 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2697{
2698 unsigned int cur_rx, rx_left;
2699 unsigned int delta, count;
2700
1da177e4
LT		 2701 cur_rx = tp->cur_rx;
2702 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2703 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2704
4dcb7d33 2705 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2706 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2707 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2708 u32 status;
2709
2710 rmb();
126fa4b9 2711 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2712
2713 if (status & DescOwn)
2714 break;
4dcb7d33 2715 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2716 if (netif_msg_rx_err(tp)) {
2717 printk(KERN_INFO
2718 "%s: Rx ERROR. status = %08x\n",
2719 dev->name, status);
2720 }
cebf8cc7 2721 dev->stats.rx_errors++;
1da177e4 2722 if (status & (RxRWT | RxRUNT))
cebf8cc7 2723 dev->stats.rx_length_errors++;
1da177e4 2724 if (status & RxCRC)
cebf8cc7 2725 dev->stats.rx_crc_errors++;
9dccf611
FR		 2726 if (status & RxFOVF) {
2727 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2728 dev->stats.rx_fifo_errors++;
9dccf611 2729 }
126fa4b9 2730 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2731 } else {
1da177e4 2732 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2733 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2734 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2735 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2736
126fa4b9
FR		 2737 /*
2738 * The driver does not support incoming fragmented
2739 * frames. They are seen as a symptom of over-mtu
2740 * sized frames.
2741 */
2742 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2743 dev->stats.rx_dropped++;
2744 dev->stats.rx_length_errors++;
126fa4b9 2745 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2746 continue;
126fa4b9
FR		 2747 }
2748
1da177e4 2749 rtl8169_rx_csum(skb, desc);
bcf0bf90 2750
07d3f51f 2751 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2752 pci_dma_sync_single_for_device(pdev, addr,
2753 pkt_size, PCI_DMA_FROMDEVICE);
2754 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2755 } else {
2756 pci_unmap_single(pdev, addr, pkt_size,
2757 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2758 tp->Rx_skbuff[entry] = NULL;
2759 }
2760
1da177e4
LT		 2761 skb_put(skb, pkt_size);
2762 skb->protocol = eth_type_trans(skb, dev);
2763
2764 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2765 rtl8169_rx_skb(skb);
2766
2767 dev->last_rx = jiffies;
cebf8cc7
FR		 2768 dev->stats.rx_bytes += pkt_size;
2769 dev->stats.rx_packets++;
1da177e4 2770 }
6dccd16b
FR		 2771
2772 /* Work around for AMD plateform. */
2773 if ((desc->opts2 & 0xfffe000) &&
2774 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2775 desc->opts2 = 0;
2776 cur_rx++;
2777 }
1da177e4
LT		 2778 }
2779
2780 count = cur_rx - tp->cur_rx;
2781 tp->cur_rx = cur_rx;
2782
2783 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2784 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2785 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2786 tp->dirty_rx += delta;
2787
2788 /*
2789 * FIXME: until there is periodic timer to try and refill the ring,
2790 * a temporary shortage may definitely kill the Rx process.
2791 * - disable the asic to try and avoid an overflow and kick it again
2792 * after refill ?
2793 * - how do others driver handle this condition (Uh oh...).
2794 */
b57b7e5a 2795 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2796 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2797
2798 return count;
2799}
2800
07d3f51f 2801static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2802{
07d3f51f 2803 struct net_device *dev = dev_instance;
1da177e4
LT		 2804 struct rtl8169_private *tp = netdev_priv(dev);
2805 int boguscnt = max_interrupt_work;
2806 void __iomem *ioaddr = tp->mmio_addr;
2807 int status;
2808 int handled = 0;
2809
2810 do {
2811 status = RTL_R16(IntrStatus);
2812
2813 /* hotplug/major error/no more work/shared irq */
2814 if ((status == 0xFFFF) || !status)
2815 break;
2816
2817 handled = 1;
2818
2819 if (unlikely(!netif_running(dev))) {
2820 rtl8169_asic_down(ioaddr);
2821 goto out;
2822 }
2823
2824 status &= tp->intr_mask;
2825 RTL_W16(IntrStatus,
2826 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2827
0e485150
FR		 2828 if (!(status & tp->intr_event))
2829 break;
2830
2831 /* Work around for rx fifo overflow */
2832 if (unlikely(status & RxFIFOOver) &&
2833 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2834 netif_stop_queue(dev);
2835 rtl8169_tx_timeout(dev);
1da177e4 2836 break;
0e485150 2837 }
1da177e4
LT		 2838
2839 if (unlikely(status & SYSErr)) {
2840 rtl8169_pcierr_interrupt(dev);
2841 break;
2842 }
2843
2844 if (status & LinkChg)
2845 rtl8169_check_link_status(dev, tp, ioaddr);
2846
2847#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2848 if (status & tp->napi_event) {
2849 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2850 tp->intr_mask = ~tp->napi_event;
2851
bea3348e
SH		 2852 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2853 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2854 else if (netif_msg_intr(tp)) {
2855 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2856 dev->name, status);
2857 }
1da177e4
LT		 2858 }
2859 break;
2860#else
2861 /* Rx interrupt */
07d3f51f 2862 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2863 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2864
1da177e4
LT		 2865 /* Tx interrupt */
2866 if (status & (TxOK | TxErr))
2867 rtl8169_tx_interrupt(dev, tp, ioaddr);
2868#endif
2869
2870 boguscnt--;
2871 } while (boguscnt > 0);
2872
2873 if (boguscnt <= 0) {
7c8b2eb4 2874 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2875 printk(KERN_WARNING
2876 "%s: Too much work at interrupt!\n", dev->name);
2877 }
1da177e4
LT		 2878 /* Clear all interrupt sources. */
2879 RTL_W16(IntrStatus, 0xffff);
2880 }
2881out:
2882 return IRQ_RETVAL(handled);
2883}
2884
2885#ifdef CONFIG_R8169_NAPI
bea3348e 2886static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2887{
bea3348e
SH		 2888 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2889 struct net_device *dev = tp->dev;
1da177e4 2890 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2891 int work_done;
1da177e4 2892
bea3348e 2893 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2894 rtl8169_tx_interrupt(dev, tp, ioaddr);
2895
bea3348e
SH		 2896 if (work_done < budget) {
2897 netif_rx_complete(dev, napi);
1da177e4
LT		 2898 tp->intr_mask = 0xffff;
2899 /*
2900 * 20040426: the barrier is not strictly required but the
2901 * behavior of the irq handler could be less predictable
2902 * without it. Btw, the lack of flush for the posted pci
2903 * write is safe - FR
2904 */
2905 smp_wmb();
0e485150 2906 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2907 }
2908
bea3348e 2909 return work_done;
1da177e4
LT		 2910}
2911#endif
2912
2913static void rtl8169_down(struct net_device *dev)
2914{
2915 struct rtl8169_private *tp = netdev_priv(dev);
2916 void __iomem *ioaddr = tp->mmio_addr;
2917 unsigned int poll_locked = 0;
733b736c 2918 unsigned int intrmask;
1da177e4
LT		 2919
2920 rtl8169_delete_timer(dev);
2921
2922 netif_stop_queue(dev);
2923
1da177e4
LT		 2924core_down:
2925 spin_lock_irq(&tp->lock);
2926
2927 rtl8169_asic_down(ioaddr);
2928
2929 /* Update the error counts. */
cebf8cc7 2930 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2931 RTL_W32(RxMissed, 0);
2932
2933 spin_unlock_irq(&tp->lock);
2934
2935 synchronize_irq(dev->irq);
2936
2937 if (!poll_locked) {
bea3348e 2938 napi_disable(&tp->napi);
1da177e4
LT		 2939 poll_locked++;
2940 }
2941
2942 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2943 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2944
2945 /*
2946 * And now for the 50k$ question: are IRQ disabled or not ?
2947 *
2948 * Two paths lead here:
2949 * 1) dev->close
2950 * -> netif_running() is available to sync the current code and the
2951 * IRQ handler. See rtl8169_interrupt for details.
2952 * 2) dev->change_mtu
2953 * -> rtl8169_poll can not be issued again and re-enable the
2954 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2955 *
2956 * No loop if hotpluged or major error (0xffff).
1da177e4 2957 */
733b736c
AP		 2958 intrmask = RTL_R16(IntrMask);
2959 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2960 goto core_down;
2961
2962 rtl8169_tx_clear(tp);
2963
2964 rtl8169_rx_clear(tp);
2965}
2966
2967static int rtl8169_close(struct net_device *dev)
2968{
2969 struct rtl8169_private *tp = netdev_priv(dev);
2970 struct pci_dev *pdev = tp->pci_dev;
2971
2972 rtl8169_down(dev);
2973
2974 free_irq(dev->irq, dev);
2975
1da177e4
LT		 2976 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2977 tp->RxPhyAddr);
2978 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2979 tp->TxPhyAddr);
2980 tp->TxDescArray = NULL;
2981 tp->RxDescArray = NULL;
2982
2983 return 0;
2984}
2985
07ce4064 2986static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2987{
2988 struct rtl8169_private *tp = netdev_priv(dev);
2989 void __iomem *ioaddr = tp->mmio_addr;
2990 unsigned long flags;
2991 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2992 int rx_mode;
1da177e4
LT		 2993 u32 tmp = 0;
2994
2995 if (dev->flags & IFF_PROMISC) {
2996 /* Unconditionally log net taps. */
b57b7e5a
SH		 2997 if (netif_msg_link(tp)) {
2998 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2999 dev->name);
3000 }
1da177e4
LT		 3001 rx_mode =
3002 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3003 AcceptAllPhys;
3004 mc_filter[1] = mc_filter[0] = 0xffffffff;
3005 } else if ((dev->mc_count > multicast_filter_limit)
3006 || (dev->flags & IFF_ALLMULTI)) {
3007 /* Too many to filter perfectly -- accept all multicasts. */
3008 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3009 mc_filter[1] = mc_filter[0] = 0xffffffff;
3010 } else {
3011 struct dev_mc_list *mclist;
07d3f51f
FR		 3012 unsigned int i;
3013
1da177e4
LT		 3014 rx_mode = AcceptBroadcast | AcceptMyPhys;
3015 mc_filter[1] = mc_filter[0] = 0;
3016 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3017 i++, mclist = mclist->next) {
3018 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3019 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3020 rx_mode |= AcceptMulticast;
3021 }
3022 }
3023
3024 spin_lock_irqsave(&tp->lock, flags);
3025
3026 tmp = rtl8169_rx_config | rx_mode |
3027 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3028
bcf0bf90
FR		 3029 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3030 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3031 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3032 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3033 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
3034 mc_filter[0] = 0xffffffff;
3035 mc_filter[1] = 0xffffffff;
3036 }
3037
1da177e4
LT		 3038 RTL_W32(MAR0 + 0, mc_filter[0]);
3039 RTL_W32(MAR0 + 4, mc_filter[1]);
3040
57a9f236
FR		 3041 RTL_W32(RxConfig, tmp);
3042
1da177e4
LT		 3043 spin_unlock_irqrestore(&tp->lock, flags);
3044}
3045
3046/**
3047 * rtl8169_get_stats - Get rtl8169 read/write statistics
3048 * @dev: The Ethernet Device to get statistics for
3049 *
3050 * Get TX/RX statistics for rtl8169
3051 */
3052static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3053{
3054 struct rtl8169_private *tp = netdev_priv(dev);
3055 void __iomem *ioaddr = tp->mmio_addr;
3056 unsigned long flags;
3057
3058 if (netif_running(dev)) {
3059 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3060 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3061 RTL_W32(RxMissed, 0);
3062 spin_unlock_irqrestore(&tp->lock, flags);
3063 }
5b0384f4 3064
cebf8cc7 3065 return &dev->stats;
1da177e4
LT		 3066}
3067
5d06a99f
FR		 3068#ifdef CONFIG_PM
3069
3070static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3071{
3072 struct net_device *dev = pci_get_drvdata(pdev);
3073 struct rtl8169_private *tp = netdev_priv(dev);
3074 void __iomem *ioaddr = tp->mmio_addr;
3075
3076 if (!netif_running(dev))
1371fa6d 3077 goto out_pci_suspend;
5d06a99f
FR		 3078
3079 netif_device_detach(dev);
3080 netif_stop_queue(dev);
3081
3082 spin_lock_irq(&tp->lock);
3083
3084 rtl8169_asic_down(ioaddr);
3085
cebf8cc7 3086 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3087 RTL_W32(RxMissed, 0);
3088
3089 spin_unlock_irq(&tp->lock);
3090
1371fa6d 3091out_pci_suspend:
5d06a99f 3092 pci_save_state(pdev);
f23e7fda
FR		 3093 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3094 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3095 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3096
5d06a99f
FR		 3097 return 0;
3098}
3099
3100static int rtl8169_resume(struct pci_dev *pdev)
3101{
3102 struct net_device *dev = pci_get_drvdata(pdev);
3103
1371fa6d
FR		 3104 pci_set_power_state(pdev, PCI_D0);
3105 pci_restore_state(pdev);
3106 pci_enable_wake(pdev, PCI_D0, 0);
3107
5d06a99f
FR		 3108 if (!netif_running(dev))
3109 goto out;
3110
3111 netif_device_attach(dev);
3112
5d06a99f
FR		 3113 rtl8169_schedule_work(dev, rtl8169_reset_task);
3114out:
3115 return 0;
3116}
3117
3118#endif /* CONFIG_PM */
3119
1da177e4
LT		 3120static struct pci_driver rtl8169_pci_driver = {
3121 .name = MODULENAME,
3122 .id_table = rtl8169_pci_tbl,
3123 .probe = rtl8169_init_one,
3124 .remove = __devexit_p(rtl8169_remove_one),
3125#ifdef CONFIG_PM
3126 .suspend = rtl8169_suspend,
3127 .resume = rtl8169_resume,
3128#endif
3129};
3130
07d3f51f 3131static int __init rtl8169_init_module(void)
1da177e4 3132{
29917620 3133 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3134}
3135
07d3f51f 3136static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3137{
3138 pci_unregister_driver(&rtl8169_pci_driver);
3139}
3140
3141module_init(rtl8169_init_module);
3142module_exit(rtl8169_cleanup_module);
Clone of davem's net-next-2.6 tree