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r8169: get ethtool settings through the generic mii helper
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
64#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 67#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 68#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72#define R8169_REGS_SIZE 256
73#define R8169_NAPI_WEIGHT 64
74#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
76#define RX_BUF_SIZE 1536 /* Rx Buffer size */
77#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80#define RTL8169_TX_TIMEOUT (6*HZ)
81#define RTL8169_PHY_TIMEOUT (10*HZ)
82
83/* write/read MMIO register */
84#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
85#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
86#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
87#define RTL_R8(reg) readb (ioaddr + (reg))
88#define RTL_R16(reg) readw (ioaddr + (reg))
89#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
90
91enum mac_version {
ba6eb6ee
FR		 92 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
93 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
94 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
95 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
96 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 97 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 98 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 99 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
100 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
101 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
102 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
103 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
104 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
105 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
106 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
107 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 108};
109
1da177e4
LT		 110#define _R(NAME,MAC,MASK) \
111 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
112
3c6bee1d 113static const struct {
1da177e4
LT		 114 const char *name;
115 u8 mac_version;
116 u32 RxConfigMask; /* Clears the bits supported by this chip */
117} rtl_chip_info[] = {
ba6eb6ee
FR		 118 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
119 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
120 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
121 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
122 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 124 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
126 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
127 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 128 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
129 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
130 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
131 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
132 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 134};
135#undef _R
136
bcf0bf90
FR		 137enum cfg_version {
138 RTL_CFG_0 = 0x00,
139 RTL_CFG_1,
140 RTL_CFG_2
141};
142
07ce4064
FR		 143static void rtl_hw_start_8169(struct net_device *);
144static void rtl_hw_start_8168(struct net_device *);
145static void rtl_hw_start_8101(struct net_device *);
146
1da177e4 147static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 148 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
153 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 154 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 155 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
156 { PCI_VENDOR_ID_LINKSYS, 0x1032,
157 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 158 { 0x0001, 0x8168,
159 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 160 {0,},
161};
162
163MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
164
165static int rx_copybreak = 200;
166static int use_dac;
b57b7e5a
SH		 167static struct {
168 u32 msg_enable;
169} debug = { -1 };
1da177e4 170
07d3f51f
FR		 171enum rtl_registers {
172 MAC0 = 0, /* Ethernet hardware address. */
773d2021 173 MAC4 = 4,
07d3f51f
FR		 174 MAR0 = 8, /* Multicast filter. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
181 FLASH = 0x30,
182 ERSR = 0x36,
183 ChipCmd = 0x37,
184 TxPoll = 0x38,
185 IntrMask = 0x3c,
186 IntrStatus = 0x3e,
187 TxConfig = 0x40,
188 RxConfig = 0x44,
189 RxMissed = 0x4c,
190 Cfg9346 = 0x50,
191 Config0 = 0x51,
192 Config1 = 0x52,
193 Config2 = 0x53,
194 Config3 = 0x54,
195 Config4 = 0x55,
196 Config5 = 0x56,
197 MultiIntr = 0x5c,
198 PHYAR = 0x60,
199 TBICSR = 0x64,
200 TBI_ANAR = 0x68,
201 TBI_LPAR = 0x6a,
202 PHYstatus = 0x6c,
203 RxMaxSize = 0xda,
204 CPlusCmd = 0xe0,
205 IntrMitigate = 0xe2,
206 RxDescAddrLow = 0xe4,
207 RxDescAddrHigh = 0xe8,
208 EarlyTxThres = 0xec,
209 FuncEvent = 0xf0,
210 FuncEventMask = 0xf4,
211 FuncPresetState = 0xf8,
212 FuncForceEvent = 0xfc,
1da177e4
LT		 213};
214
07d3f51f 215enum rtl_register_content {
1da177e4 216 /* InterruptStatusBits */
07d3f51f
FR		 217 SYSErr = 0x8000,
218 PCSTimeout = 0x4000,
219 SWInt = 0x0100,
220 TxDescUnavail = 0x0080,
221 RxFIFOOver = 0x0040,
222 LinkChg = 0x0020,
223 RxOverflow = 0x0010,
224 TxErr = 0x0008,
225 TxOK = 0x0004,
226 RxErr = 0x0002,
227 RxOK = 0x0001,
1da177e4
LT		 228
229 /* RxStatusDesc */
9dccf611
FR		 230 RxFOVF = (1 << 23),
231 RxRWT = (1 << 22),
232 RxRES = (1 << 21),
233 RxRUNT = (1 << 20),
234 RxCRC = (1 << 19),
1da177e4
LT		 235
236 /* ChipCmdBits */
07d3f51f
FR		 237 CmdReset = 0x10,
238 CmdRxEnb = 0x08,
239 CmdTxEnb = 0x04,
240 RxBufEmpty = 0x01,
1da177e4 241
275391a4
FR		 242 /* TXPoll register p.5 */
243 HPQ = 0x80, /* Poll cmd on the high prio queue */
244 NPQ = 0x40, /* Poll cmd on the low prio queue */
245 FSWInt = 0x01, /* Forced software interrupt */
246
1da177e4 247 /* Cfg9346Bits */
07d3f51f
FR		 248 Cfg9346_Lock = 0x00,
249 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 250
251 /* rx_mode_bits */
07d3f51f
FR		 252 AcceptErr = 0x20,
253 AcceptRunt = 0x10,
254 AcceptBroadcast = 0x08,
255 AcceptMulticast = 0x04,
256 AcceptMyPhys = 0x02,
257 AcceptAllPhys = 0x01,
1da177e4
LT		 258
259 /* RxConfigBits */
07d3f51f
FR		 260 RxCfgFIFOShift = 13,
261 RxCfgDMAShift = 8,
1da177e4
LT		 262
263 /* TxConfigBits */
264 TxInterFrameGapShift = 24,
265 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
266
5d06a99f 267 /* Config1 register p.24 */
fbac58fc 268 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 269 PMEnable = (1 << 0), /* Power Management Enable */
270
6dccd16b
FR		 271 /* Config2 register p. 25 */
272 PCI_Clock_66MHz = 0x01,
273 PCI_Clock_33MHz = 0x00,
274
61a4dcc2
FR		 275 /* Config3 register p.25 */
276 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
277 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
278
5d06a99f 279 /* Config5 register p.27 */
61a4dcc2
FR		 280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
1da177e4
LT		 286 /* TBICSR p.28 */
287 TBIReset = 0x80000000,
288 TBILoopback = 0x40000000,
289 TBINwEnable = 0x20000000,
290 TBINwRestart = 0x10000000,
291 TBILinkOk = 0x02000000,
292 TBINwComplete = 0x01000000,
293
294 /* CPlusCmd p.31 */
0e485150 295 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 296 RxVlan = (1 << 6),
297 RxChkSum = (1 << 5),
298 PCIDAC = (1 << 4),
299 PCIMulRW = (1 << 3),
0e485150
FR		 300 INTT_0 = 0x0000, // 8168
301 INTT_1 = 0x0001, // 8168
302 INTT_2 = 0x0002, // 8168
303 INTT_3 = 0x0003, // 8168
1da177e4
LT		 304
305 /* rtl8169_PHYstatus */
07d3f51f
FR		 306 TBI_Enable = 0x80,
307 TxFlowCtrl = 0x40,
308 RxFlowCtrl = 0x20,
309 _1000bpsF = 0x10,
310 _100bps = 0x08,
311 _10bps = 0x04,
312 LinkStatus = 0x02,
313 FullDup = 0x01,
1da177e4 314
1da177e4 315 /* _TBICSRBit */
07d3f51f 316 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 317
318 /* DumpCounterCommand */
07d3f51f 319 CounterDump = 0x8,
1da177e4
LT		 320};
321
07d3f51f 322enum desc_status_bit {
1da177e4
LT		 323 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
324 RingEnd = (1 << 30), /* End of descriptor ring */
325 FirstFrag = (1 << 29), /* First segment of a packet */
326 LastFrag = (1 << 28), /* Final segment of a packet */
327
328 /* Tx private */
329 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
330 MSSShift = 16, /* MSS value position */
331 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
332 IPCS = (1 << 18), /* Calculate IP checksum */
333 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
334 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
335 TxVlanTag = (1 << 17), /* Add VLAN tag */
336
337 /* Rx private */
338 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
339 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
340
341#define RxProtoUDP (PID1)
342#define RxProtoTCP (PID0)
343#define RxProtoIP (PID1 | PID0)
344#define RxProtoMask RxProtoIP
345
346 IPFail = (1 << 16), /* IP checksum failed */
347 UDPFail = (1 << 15), /* UDP/IP checksum failed */
348 TCPFail = (1 << 14), /* TCP/IP checksum failed */
349 RxVlanTag = (1 << 16), /* VLAN tag available */
350};
351
352#define RsvdMask 0x3fffc000
353
354struct TxDesc {
6cccd6e7
REB		 355 __le32 opts1;
356 __le32 opts2;
357 __le64 addr;
1da177e4
LT		 358};
359
360struct RxDesc {
6cccd6e7
REB		 361 __le32 opts1;
362 __le32 opts2;
363 __le64 addr;
1da177e4
LT		 364};
365
366struct ring_info {
367 struct sk_buff *skb;
368 u32 len;
369 u8 __pad[sizeof(void *) - sizeof(u32)];
370};
371
f23e7fda 372enum features {
ccdffb9a
FR		 373 RTL_FEATURE_WOL = (1 << 0),
374 RTL_FEATURE_MSI = (1 << 1),
375 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 376};
377
1da177e4
LT		 378struct rtl8169_private {
379 void __iomem *mmio_addr; /* memory map physical address */
380 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 381 struct net_device *dev;
bea3348e 382 struct napi_struct napi;
1da177e4 383 spinlock_t lock; /* spin lock flag */
b57b7e5a 384 u32 msg_enable;
1da177e4
LT		 385 int chipset;
386 int mac_version;
1da177e4
LT		 387 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
388 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
389 u32 dirty_rx;
390 u32 dirty_tx;
391 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
392 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
393 dma_addr_t TxPhyAddr;
394 dma_addr_t RxPhyAddr;
395 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
396 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 397 unsigned align;
1da177e4
LT		 398 unsigned rx_buf_sz;
399 struct timer_list timer;
400 u16 cp_cmd;
0e485150
FR		 401 u16 intr_event;
402 u16 napi_event;
1da177e4
LT		 403 u16 intr_mask;
404 int phy_auto_nego_reg;
405 int phy_1000_ctrl_reg;
406#ifdef CONFIG_R8169_VLAN
407 struct vlan_group *vlgrp;
408#endif
409 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 410 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 411 void (*phy_reset_enable)(void __iomem *);
07ce4064 412 void (*hw_start)(struct net_device *);
1da177e4
LT		 413 unsigned int (*phy_reset_pending)(void __iomem *);
414 unsigned int (*link_ok)(void __iomem *);
c4028958 415 struct delayed_work task;
f23e7fda 416 unsigned features;
ccdffb9a
FR		 417
418 struct mii_if_info mii;
1da177e4
LT		 419};
420
979b6c13 421MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 422MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 423module_param(rx_copybreak, int, 0);
1b7efd58 424MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 425module_param(use_dac, int, 0);
426MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 427module_param_named(debug, debug.msg_enable, int, 0);
428MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 429MODULE_LICENSE("GPL");
430MODULE_VERSION(RTL8169_VERSION);
431
432static int rtl8169_open(struct net_device *dev);
433static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 434static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 435static int rtl8169_init_ring(struct net_device *dev);
07ce4064 436static void rtl_hw_start(struct net_device *dev);
1da177e4 437static int rtl8169_close(struct net_device *dev);
07ce4064 438static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 439static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 440static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 441static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 442 void __iomem *, u32 budget);
4dcb7d33 443static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 444static void rtl8169_down(struct net_device *dev);
99f252b0 445static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 446static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 447
1da177e4 448static const unsigned int rtl8169_rx_config =
5b0384f4 449 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 450
07d3f51f 451static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 452{
453 int i;
454
a6baf3af 455 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 456
2371408c 457 for (i = 20; i > 0; i--) {
07d3f51f
FR		 458 /*
459 * Check if the RTL8169 has completed writing to the specified
460 * MII register.
461 */
5b0384f4 462 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 463 break;
2371408c 464 udelay(25);
1da177e4
LT		 465 }
466}
467
07d3f51f 468static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 469{
470 int i, value = -1;
471
a6baf3af 472 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 473
2371408c 474 for (i = 20; i > 0; i--) {
07d3f51f
FR		 475 /*
476 * Check if the RTL8169 has completed retrieving data from
477 * the specified MII register.
478 */
1da177e4 479 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 480 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 481 break;
482 }
2371408c 483 udelay(25);
1da177e4
LT		 484 }
485 return value;
486}
487
ccdffb9a
FR		 488static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
489 int val)
490{
491 struct rtl8169_private *tp = netdev_priv(dev);
492 void __iomem *ioaddr = tp->mmio_addr;
493
494 mdio_write(ioaddr, location, val);
495}
496
497static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
498{
499 struct rtl8169_private *tp = netdev_priv(dev);
500 void __iomem *ioaddr = tp->mmio_addr;
501
502 return mdio_read(ioaddr, location);
503}
504
1da177e4
LT		 505static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
506{
507 RTL_W16(IntrMask, 0x0000);
508
509 RTL_W16(IntrStatus, 0xffff);
510}
511
512static void rtl8169_asic_down(void __iomem *ioaddr)
513{
514 RTL_W8(ChipCmd, 0x00);
515 rtl8169_irq_mask_and_ack(ioaddr);
516 RTL_R16(CPlusCmd);
517}
518
519static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
520{
521 return RTL_R32(TBICSR) & TBIReset;
522}
523
524static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
525{
64e4bfb4 526 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 527}
528
529static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
530{
531 return RTL_R32(TBICSR) & TBILinkOk;
532}
533
534static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
535{
536 return RTL_R8(PHYstatus) & LinkStatus;
537}
538
539static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
540{
541 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
542}
543
544static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
545{
546 unsigned int val;
547
9e0db8ef
FR		 548 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
549 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 550}
551
552static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 553 struct rtl8169_private *tp,
554 void __iomem *ioaddr)
1da177e4
LT		 555{
556 unsigned long flags;
557
558 spin_lock_irqsave(&tp->lock, flags);
559 if (tp->link_ok(ioaddr)) {
560 netif_carrier_on(dev);
b57b7e5a
SH		 561 if (netif_msg_ifup(tp))
562 printk(KERN_INFO PFX "%s: link up\n", dev->name);
563 } else {
564 if (netif_msg_ifdown(tp))
565 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 566 netif_carrier_off(dev);
b57b7e5a 567 }
1da177e4
LT		 568 spin_unlock_irqrestore(&tp->lock, flags);
569}
570
61a4dcc2
FR		 571static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
572{
573 struct rtl8169_private *tp = netdev_priv(dev);
574 void __iomem *ioaddr = tp->mmio_addr;
575 u8 options;
576
577 wol->wolopts = 0;
578
579#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
580 wol->supported = WAKE_ANY;
581
582 spin_lock_irq(&tp->lock);
583
584 options = RTL_R8(Config1);
585 if (!(options & PMEnable))
586 goto out_unlock;
587
588 options = RTL_R8(Config3);
589 if (options & LinkUp)
590 wol->wolopts |= WAKE_PHY;
591 if (options & MagicPacket)
592 wol->wolopts |= WAKE_MAGIC;
593
594 options = RTL_R8(Config5);
595 if (options & UWF)
596 wol->wolopts |= WAKE_UCAST;
597 if (options & BWF)
5b0384f4 598 wol->wolopts |= WAKE_BCAST;
61a4dcc2 599 if (options & MWF)
5b0384f4 600 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 601
602out_unlock:
603 spin_unlock_irq(&tp->lock);
604}
605
606static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
607{
608 struct rtl8169_private *tp = netdev_priv(dev);
609 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 610 unsigned int i;
61a4dcc2
FR		 611 static struct {
612 u32 opt;
613 u16 reg;
614 u8 mask;
615 } cfg[] = {
616 { WAKE_ANY, Config1, PMEnable },
617 { WAKE_PHY, Config3, LinkUp },
618 { WAKE_MAGIC, Config3, MagicPacket },
619 { WAKE_UCAST, Config5, UWF },
620 { WAKE_BCAST, Config5, BWF },
621 { WAKE_MCAST, Config5, MWF },
622 { WAKE_ANY, Config5, LanWake }
623 };
624
625 spin_lock_irq(&tp->lock);
626
627 RTL_W8(Cfg9346, Cfg9346_Unlock);
628
629 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
630 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
631 if (wol->wolopts & cfg[i].opt)
632 options |= cfg[i].mask;
633 RTL_W8(cfg[i].reg, options);
634 }
635
636 RTL_W8(Cfg9346, Cfg9346_Lock);
637
f23e7fda
FR		 638 if (wol->wolopts)
639 tp->features |= RTL_FEATURE_WOL;
640 else
641 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 642
643 spin_unlock_irq(&tp->lock);
644
645 return 0;
646}
647
1da177e4
LT		 648static void rtl8169_get_drvinfo(struct net_device *dev,
649 struct ethtool_drvinfo *info)
650{
651 struct rtl8169_private *tp = netdev_priv(dev);
652
653 strcpy(info->driver, MODULENAME);
654 strcpy(info->version, RTL8169_VERSION);
655 strcpy(info->bus_info, pci_name(tp->pci_dev));
656}
657
658static int rtl8169_get_regs_len(struct net_device *dev)
659{
660 return R8169_REGS_SIZE;
661}
662
663static int rtl8169_set_speed_tbi(struct net_device *dev,
664 u8 autoneg, u16 speed, u8 duplex)
665{
666 struct rtl8169_private *tp = netdev_priv(dev);
667 void __iomem *ioaddr = tp->mmio_addr;
668 int ret = 0;
669 u32 reg;
670
671 reg = RTL_R32(TBICSR);
672 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
673 (duplex == DUPLEX_FULL)) {
674 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
675 } else if (autoneg == AUTONEG_ENABLE)
676 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
677 else {
b57b7e5a
SH		 678 if (netif_msg_link(tp)) {
679 printk(KERN_WARNING "%s: "
680 "incorrect speed setting refused in TBI mode\n",
681 dev->name);
682 }
1da177e4
LT		 683 ret = -EOPNOTSUPP;
684 }
685
686 return ret;
687}
688
689static int rtl8169_set_speed_xmii(struct net_device *dev,
690 u8 autoneg, u16 speed, u8 duplex)
691{
692 struct rtl8169_private *tp = netdev_priv(dev);
693 void __iomem *ioaddr = tp->mmio_addr;
694 int auto_nego, giga_ctrl;
695
64e4bfb4
FR		 696 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
697 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
698 ADVERTISE_100HALF | ADVERTISE_100FULL);
699 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
700 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 701
702 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 703 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
704 ADVERTISE_100HALF | ADVERTISE_100FULL);
705 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 706 } else {
707 if (speed == SPEED_10)
64e4bfb4 708 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 709 else if (speed == SPEED_100)
64e4bfb4 710 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 711 else if (speed == SPEED_1000)
64e4bfb4 712 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 713
714 if (duplex == DUPLEX_HALF)
64e4bfb4 715 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 716
717 if (duplex == DUPLEX_FULL)
64e4bfb4 718 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 719
720 /* This tweak comes straight from Realtek's driver. */
721 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 722 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
723 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 724 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 725 }
726 }
727
728 /* The 8100e/8101e do Fast Ethernet only. */
729 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
730 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 731 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
732 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 733 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 734 netif_msg_link(tp)) {
735 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
736 dev->name);
737 }
64e4bfb4 738 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 739 }
740
623a1593
FR		 741 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
742
e3cf0cc0
FR		 743 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
744 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 745 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
746 mdio_write(ioaddr, 0x1f, 0x0000);
747 mdio_write(ioaddr, 0x0e, 0x0000);
748 }
749
1da177e4
LT		 750 tp->phy_auto_nego_reg = auto_nego;
751 tp->phy_1000_ctrl_reg = giga_ctrl;
752
64e4bfb4
FR		 753 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
754 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
755 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 756 return 0;
757}
758
759static int rtl8169_set_speed(struct net_device *dev,
760 u8 autoneg, u16 speed, u8 duplex)
761{
762 struct rtl8169_private *tp = netdev_priv(dev);
763 int ret;
764
765 ret = tp->set_speed(dev, autoneg, speed, duplex);
766
64e4bfb4 767 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 768 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
769
770 return ret;
771}
772
773static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
774{
775 struct rtl8169_private *tp = netdev_priv(dev);
776 unsigned long flags;
777 int ret;
778
779 spin_lock_irqsave(&tp->lock, flags);
780 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
781 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 782
1da177e4
LT		 783 return ret;
784}
785
786static u32 rtl8169_get_rx_csum(struct net_device *dev)
787{
788 struct rtl8169_private *tp = netdev_priv(dev);
789
790 return tp->cp_cmd & RxChkSum;
791}
792
793static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
794{
795 struct rtl8169_private *tp = netdev_priv(dev);
796 void __iomem *ioaddr = tp->mmio_addr;
797 unsigned long flags;
798
799 spin_lock_irqsave(&tp->lock, flags);
800
801 if (data)
802 tp->cp_cmd |= RxChkSum;
803 else
804 tp->cp_cmd &= ~RxChkSum;
805
806 RTL_W16(CPlusCmd, tp->cp_cmd);
807 RTL_R16(CPlusCmd);
808
809 spin_unlock_irqrestore(&tp->lock, flags);
810
811 return 0;
812}
813
814#ifdef CONFIG_R8169_VLAN
815
816static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
817 struct sk_buff *skb)
818{
819 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
820 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
821}
822
823static void rtl8169_vlan_rx_register(struct net_device *dev,
824 struct vlan_group *grp)
825{
826 struct rtl8169_private *tp = netdev_priv(dev);
827 void __iomem *ioaddr = tp->mmio_addr;
828 unsigned long flags;
829
830 spin_lock_irqsave(&tp->lock, flags);
831 tp->vlgrp = grp;
832 if (tp->vlgrp)
833 tp->cp_cmd |= RxVlan;
834 else
835 tp->cp_cmd &= ~RxVlan;
836 RTL_W16(CPlusCmd, tp->cp_cmd);
837 RTL_R16(CPlusCmd);
838 spin_unlock_irqrestore(&tp->lock, flags);
839}
840
1da177e4
LT		 841static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
842 struct sk_buff *skb)
843{
844 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 845 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 846 int ret;
847
865c652d
FR		 848 if (vlgrp && (opts2 & RxVlanTag)) {
849 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 850 ret = 0;
851 } else
852 ret = -1;
853 desc->opts2 = 0;
854 return ret;
855}
856
857#else /* !CONFIG_R8169_VLAN */
858
859static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
860 struct sk_buff *skb)
861{
862 return 0;
863}
864
865static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
866 struct sk_buff *skb)
867{
868 return -1;
869}
870
871#endif
872
ccdffb9a 873static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 874{
875 struct rtl8169_private *tp = netdev_priv(dev);
876 void __iomem *ioaddr = tp->mmio_addr;
877 u32 status;
878
879 cmd->supported =
880 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
881 cmd->port = PORT_FIBRE;
882 cmd->transceiver = XCVR_INTERNAL;
883
884 status = RTL_R32(TBICSR);
885 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
886 cmd->autoneg = !!(status & TBINwEnable);
887
888 cmd->speed = SPEED_1000;
889 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 890
891 return 0;
1da177e4
LT		 892}
893
ccdffb9a 894static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 895{
896 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 897
898 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 899}
900
901static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
902{
903 struct rtl8169_private *tp = netdev_priv(dev);
904 unsigned long flags;
ccdffb9a 905 int rc;
1da177e4
LT		 906
907 spin_lock_irqsave(&tp->lock, flags);
908
ccdffb9a 909 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 910
911 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 912 return rc;
1da177e4
LT		 913}
914
915static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
916 void *p)
917{
5b0384f4
FR		 918 struct rtl8169_private *tp = netdev_priv(dev);
919 unsigned long flags;
1da177e4 920
5b0384f4
FR		 921 if (regs->len > R8169_REGS_SIZE)
922 regs->len = R8169_REGS_SIZE;
1da177e4 923
5b0384f4
FR		 924 spin_lock_irqsave(&tp->lock, flags);
925 memcpy_fromio(p, tp->mmio_addr, regs->len);
926 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 927}
928
b57b7e5a
SH		 929static u32 rtl8169_get_msglevel(struct net_device *dev)
930{
931 struct rtl8169_private *tp = netdev_priv(dev);
932
933 return tp->msg_enable;
934}
935
936static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
937{
938 struct rtl8169_private *tp = netdev_priv(dev);
939
940 tp->msg_enable = value;
941}
942
d4a3a0fc
SH		 943static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
944 "tx_packets",
945 "rx_packets",
946 "tx_errors",
947 "rx_errors",
948 "rx_missed",
949 "align_errors",
950 "tx_single_collisions",
951 "tx_multi_collisions",
952 "unicast",
953 "broadcast",
954 "multicast",
955 "tx_aborted",
956 "tx_underrun",
957};
958
959struct rtl8169_counters {
b1eab701
AV		 960 __le64 tx_packets;
961 __le64 rx_packets;
962 __le64 tx_errors;
963 __le32 rx_errors;
964 __le16 rx_missed;
965 __le16 align_errors;
966 __le32 tx_one_collision;
967 __le32 tx_multi_collision;
968 __le64 rx_unicast;
969 __le64 rx_broadcast;
970 __le32 rx_multicast;
971 __le16 tx_aborted;
972 __le16 tx_underun;
d4a3a0fc
SH		 973};
974
b9f2c044 975static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 976{
b9f2c044
JG		 977 switch (sset) {
978 case ETH_SS_STATS:
979 return ARRAY_SIZE(rtl8169_gstrings);
980 default:
981 return -EOPNOTSUPP;
982 }
d4a3a0fc
SH		 983}
984
985static void rtl8169_get_ethtool_stats(struct net_device *dev,
986 struct ethtool_stats *stats, u64 *data)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989 void __iomem *ioaddr = tp->mmio_addr;
990 struct rtl8169_counters *counters;
991 dma_addr_t paddr;
992 u32 cmd;
993
994 ASSERT_RTNL();
995
996 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
997 if (!counters)
998 return;
999
1000 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1001 cmd = (u64)paddr & DMA_32BIT_MASK;
1002 RTL_W32(CounterAddrLow, cmd);
1003 RTL_W32(CounterAddrLow, cmd | CounterDump);
1004
1005 while (RTL_R32(CounterAddrLow) & CounterDump) {
1006 if (msleep_interruptible(1))
1007 break;
1008 }
1009
1010 RTL_W32(CounterAddrLow, 0);
1011 RTL_W32(CounterAddrHigh, 0);
1012
5b0384f4 1013 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1014 data[1] = le64_to_cpu(counters->rx_packets);
1015 data[2] = le64_to_cpu(counters->tx_errors);
1016 data[3] = le32_to_cpu(counters->rx_errors);
1017 data[4] = le16_to_cpu(counters->rx_missed);
1018 data[5] = le16_to_cpu(counters->align_errors);
1019 data[6] = le32_to_cpu(counters->tx_one_collision);
1020 data[7] = le32_to_cpu(counters->tx_multi_collision);
1021 data[8] = le64_to_cpu(counters->rx_unicast);
1022 data[9] = le64_to_cpu(counters->rx_broadcast);
1023 data[10] = le32_to_cpu(counters->rx_multicast);
1024 data[11] = le16_to_cpu(counters->tx_aborted);
1025 data[12] = le16_to_cpu(counters->tx_underun);
1026
1027 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1028}
1029
1030static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1031{
1032 switch(stringset) {
1033 case ETH_SS_STATS:
1034 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1035 break;
1036 }
1037}
1038
7282d491 1039static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1040 .get_drvinfo = rtl8169_get_drvinfo,
1041 .get_regs_len = rtl8169_get_regs_len,
1042 .get_link = ethtool_op_get_link,
1043 .get_settings = rtl8169_get_settings,
1044 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1045 .get_msglevel = rtl8169_get_msglevel,
1046 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1047 .get_rx_csum = rtl8169_get_rx_csum,
1048 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1049 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1050 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1051 .set_tso = ethtool_op_set_tso,
1052 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1053 .get_wol = rtl8169_get_wol,
1054 .set_wol = rtl8169_set_wol,
d4a3a0fc 1055 .get_strings = rtl8169_get_strings,
b9f2c044 1056 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1057 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1058};
1059
07d3f51f
FR		 1060static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1061 int bitnum, int bitval)
1da177e4
LT		 1062{
1063 int val;
1064
1065 val = mdio_read(ioaddr, reg);
1066 val = (bitval == 1) ?
1067 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1068 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1069}
1070
07d3f51f
FR		 1071static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1072 void __iomem *ioaddr)
1da177e4 1073{
0e485150
FR		 1074 /*
1075 * The driver currently handles the 8168Bf and the 8168Be identically
1076 * but they can be identified more specifically through the test below
1077 * if needed:
1078 *
1079 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1080 *
1081 * Same thing for the 8101Eb and the 8101Ec:
1082 *
1083 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1084 */
1da177e4
LT		 1085 const struct {
1086 u32 mask;
e3cf0cc0 1087 u32 val;
1da177e4
LT		 1088 int mac_version;
1089 } mac_info[] = {
e3cf0cc0
FR		 1090 /* 8168B family. */
1091 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1092 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1093 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1094 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1095
1096 /* 8168B family. */
1097 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1098 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1099 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1100 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1101
1102 /* 8101 family. */
1103 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1104 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1105 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1106 /* FIXME: where did these entries come from ? -- FR */
1107 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1108 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1109
1110 /* 8110 family. */
1111 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1112 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1113 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1114 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1115 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1116 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1117
1118 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1119 }, *p = mac_info;
1120 u32 reg;
1121
e3cf0cc0
FR		 1122 reg = RTL_R32(TxConfig);
1123 while ((reg & p->mask) != p->val)
1da177e4
LT		 1124 p++;
1125 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1126
1127 if (p->mask == 0x00000000) {
1128 struct pci_dev *pdev = tp->pci_dev;
1129
1130 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1131 }
1da177e4
LT		 1132}
1133
1134static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1135{
bcf0bf90 1136 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1137}
1138
867763c1
FR		 1139struct phy_reg {
1140 u16 reg;
1141 u16 val;
1142};
1143
1144static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1145{
1146 while (len-- > 0) {
1147 mdio_write(ioaddr, regs->reg, regs->val);
1148 regs++;
1149 }
1150}
1151
5615d9f1 1152static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1153{
1da177e4
LT		 1154 struct {
1155 u16 regs[5]; /* Beware of bit-sign propagation */
1156 } phy_magic[5] = { {
1157 { 0x0000, //w 4 15 12 0
1158 0x00a1, //w 3 15 0 00a1
1159 0x0008, //w 2 15 0 0008
1160 0x1020, //w 1 15 0 1020
1161 0x1000 } },{ //w 0 15 0 1000
1162 { 0x7000, //w 4 15 12 7
1163 0xff41, //w 3 15 0 ff41
1164 0xde60, //w 2 15 0 de60
1165 0x0140, //w 1 15 0 0140
1166 0x0077 } },{ //w 0 15 0 0077
1167 { 0xa000, //w 4 15 12 a
1168 0xdf01, //w 3 15 0 df01
1169 0xdf20, //w 2 15 0 df20
1170 0xff95, //w 1 15 0 ff95
1171 0xfa00 } },{ //w 0 15 0 fa00
1172 { 0xb000, //w 4 15 12 b
1173 0xff41, //w 3 15 0 ff41
1174 0xde20, //w 2 15 0 de20
1175 0x0140, //w 1 15 0 0140
1176 0x00bb } },{ //w 0 15 0 00bb
1177 { 0xf000, //w 4 15 12 f
1178 0xdf01, //w 3 15 0 df01
1179 0xdf20, //w 2 15 0 df20
1180 0xff95, //w 1 15 0 ff95
1181 0xbf00 } //w 0 15 0 bf00
1182 }
1183 }, *p = phy_magic;
07d3f51f 1184 unsigned int i;
1da177e4 1185
a441d7b6
FR		 1186 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1187 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1188 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1189 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1190
1191 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1192 int val, pos = 4;
1193
1194 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1195 mdio_write(ioaddr, pos, val);
1196 while (--pos >= 0)
1197 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1198 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1199 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1200 }
a441d7b6 1201 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1202}
1203
5615d9f1
FR		 1204static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1205{
a441d7b6
FR		 1206 struct phy_reg phy_reg_init[] = {
1207 { 0x1f, 0x0002 },
1208 { 0x01, 0x90d0 },
1209 { 0x1f, 0x0000 }
1210 };
1211
1212 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1213}
1214
867763c1
FR		 1215static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1216{
1217 struct phy_reg phy_reg_init[] = {
1218 { 0x1f, 0x0000 },
1219 { 0x1d, 0x0f00 },
1220 { 0x1f, 0x0002 },
1221 { 0x0c, 0x1ec8 },
1222 { 0x1f, 0x0000 }
1223 };
1224
1225 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1226}
1227
1228static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1229{
1230 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1231 { 0x1f, 0x0001 },
1232 { 0x12, 0x2300 },
867763c1
FR		 1233 { 0x1f, 0x0002 },
1234 { 0x00, 0x88d4 },
1235 { 0x01, 0x82b1 },
1236 { 0x03, 0x7002 },
1237 { 0x08, 0x9e30 },
1238 { 0x09, 0x01f0 },
1239 { 0x0a, 0x5500 },
1240 { 0x0c, 0x00c8 },
1241 { 0x1f, 0x0003 },
1242 { 0x12, 0xc096 },
1243 { 0x16, 0x000a },
1244 { 0x1f, 0x0000 }
1245 };
1246
1247 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1248}
1249
7da97ec9
FR		 1250static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1251{
1252 struct phy_reg phy_reg_init[] = {
1253 { 0x1f, 0x0000 },
1254 { 0x12, 0x2300 },
1255 { 0x1f, 0x0003 },
1256 { 0x16, 0x0f0a },
1257 { 0x1f, 0x0000 },
1258 { 0x1f, 0x0002 },
1259 { 0x0c, 0x7eb8 },
1260 { 0x1f, 0x0000 }
1261 };
1262
1263 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1264}
1265
5615d9f1
FR		 1266static void rtl_hw_phy_config(struct net_device *dev)
1267{
1268 struct rtl8169_private *tp = netdev_priv(dev);
1269 void __iomem *ioaddr = tp->mmio_addr;
1270
1271 rtl8169_print_mac_version(tp);
1272
1273 switch (tp->mac_version) {
1274 case RTL_GIGA_MAC_VER_01:
1275 break;
1276 case RTL_GIGA_MAC_VER_02:
1277 case RTL_GIGA_MAC_VER_03:
1278 rtl8169s_hw_phy_config(ioaddr);
1279 break;
1280 case RTL_GIGA_MAC_VER_04:
1281 rtl8169sb_hw_phy_config(ioaddr);
1282 break;
867763c1
FR		 1283 case RTL_GIGA_MAC_VER_18:
1284 rtl8168cp_hw_phy_config(ioaddr);
1285 break;
1286 case RTL_GIGA_MAC_VER_19:
1287 rtl8168c_hw_phy_config(ioaddr);
1288 break;
7da97ec9
FR		 1289 case RTL_GIGA_MAC_VER_20:
1290 rtl8168cx_hw_phy_config(ioaddr);
1291 break;
5615d9f1
FR		 1292 default:
1293 break;
1294 }
1295}
1296
1da177e4
LT		 1297static void rtl8169_phy_timer(unsigned long __opaque)
1298{
1299 struct net_device *dev = (struct net_device *)__opaque;
1300 struct rtl8169_private *tp = netdev_priv(dev);
1301 struct timer_list *timer = &tp->timer;
1302 void __iomem *ioaddr = tp->mmio_addr;
1303 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1304
bcf0bf90 1305 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1306
64e4bfb4 1307 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1308 return;
1309
1310 spin_lock_irq(&tp->lock);
1311
1312 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1313 /*
1da177e4
LT		 1314 * A busy loop could burn quite a few cycles on nowadays CPU.
1315 * Let's delay the execution of the timer for a few ticks.
1316 */
1317 timeout = HZ/10;
1318 goto out_mod_timer;
1319 }
1320
1321 if (tp->link_ok(ioaddr))
1322 goto out_unlock;
1323
b57b7e5a
SH		 1324 if (netif_msg_link(tp))
1325 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1326
1327 tp->phy_reset_enable(ioaddr);
1328
1329out_mod_timer:
1330 mod_timer(timer, jiffies + timeout);
1331out_unlock:
1332 spin_unlock_irq(&tp->lock);
1333}
1334
1335static inline void rtl8169_delete_timer(struct net_device *dev)
1336{
1337 struct rtl8169_private *tp = netdev_priv(dev);
1338 struct timer_list *timer = &tp->timer;
1339
e179bb7b 1340 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1341 return;
1342
1343 del_timer_sync(timer);
1344}
1345
1346static inline void rtl8169_request_timer(struct net_device *dev)
1347{
1348 struct rtl8169_private *tp = netdev_priv(dev);
1349 struct timer_list *timer = &tp->timer;
1350
e179bb7b 1351 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1352 return;
1353
2efa53f3 1354 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1355}
1356
1357#ifdef CONFIG_NET_POLL_CONTROLLER
1358/*
1359 * Polling 'interrupt' - used by things like netconsole to send skbs
1360 * without having to re-enable interrupts. It's not called while
1361 * the interrupt routine is executing.
1362 */
1363static void rtl8169_netpoll(struct net_device *dev)
1364{
1365 struct rtl8169_private *tp = netdev_priv(dev);
1366 struct pci_dev *pdev = tp->pci_dev;
1367
1368 disable_irq(pdev->irq);
7d12e780 1369 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1370 enable_irq(pdev->irq);
1371}
1372#endif
1373
1374static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1375 void __iomem *ioaddr)
1376{
1377 iounmap(ioaddr);
1378 pci_release_regions(pdev);
1379 pci_disable_device(pdev);
1380 free_netdev(dev);
1381}
1382
bf793295
FR		 1383static void rtl8169_phy_reset(struct net_device *dev,
1384 struct rtl8169_private *tp)
1385{
1386 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1387 unsigned int i;
bf793295
FR		 1388
1389 tp->phy_reset_enable(ioaddr);
1390 for (i = 0; i < 100; i++) {
1391 if (!tp->phy_reset_pending(ioaddr))
1392 return;
1393 msleep(1);
1394 }
1395 if (netif_msg_link(tp))
1396 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1397}
1398
4ff96fa6
FR		 1399static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1400{
1401 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1402
5615d9f1 1403 rtl_hw_phy_config(dev);
4ff96fa6 1404
77332894
MS		 1405 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1406 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1407 RTL_W8(0x82, 0x01);
1408 }
4ff96fa6 1409
6dccd16b
FR		 1410 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1411
1412 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1413 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1414
bcf0bf90 1415 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1416 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1417 RTL_W8(0x82, 0x01);
1418 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1419 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1420 }
1421
bf793295
FR		 1422 rtl8169_phy_reset(dev, tp);
1423
901dda2b
FR		 1424 /*
1425 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1426 * only 8101. Don't panic.
1427 */
1428 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1429
1430 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1431 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1432}
1433
773d2021
FR		 1434static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1435{
1436 void __iomem *ioaddr = tp->mmio_addr;
1437 u32 high;
1438 u32 low;
1439
1440 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1441 high = addr[4] | (addr[5] << 8);
1442
1443 spin_lock_irq(&tp->lock);
1444
1445 RTL_W8(Cfg9346, Cfg9346_Unlock);
1446 RTL_W32(MAC0, low);
1447 RTL_W32(MAC4, high);
1448 RTL_W8(Cfg9346, Cfg9346_Lock);
1449
1450 spin_unlock_irq(&tp->lock);
1451}
1452
1453static int rtl_set_mac_address(struct net_device *dev, void *p)
1454{
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 struct sockaddr *addr = p;
1457
1458 if (!is_valid_ether_addr(addr->sa_data))
1459 return -EADDRNOTAVAIL;
1460
1461 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1462
1463 rtl_rar_set(tp, dev->dev_addr);
1464
1465 return 0;
1466}
1467
5f787a1a
FR		 1468static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1469{
1470 struct rtl8169_private *tp = netdev_priv(dev);
1471 struct mii_ioctl_data *data = if_mii(ifr);
1472
1473 if (!netif_running(dev))
1474 return -ENODEV;
1475
1476 switch (cmd) {
1477 case SIOCGMIIPHY:
1478 data->phy_id = 32; /* Internal PHY */
1479 return 0;
1480
1481 case SIOCGMIIREG:
1482 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1483 return 0;
1484
1485 case SIOCSMIIREG:
1486 if (!capable(CAP_NET_ADMIN))
1487 return -EPERM;
1488 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1489 return 0;
1490 }
1491 return -EOPNOTSUPP;
1492}
1493
0e485150
FR		 1494static const struct rtl_cfg_info {
1495 void (*hw_start)(struct net_device *);
1496 unsigned int region;
1497 unsigned int align;
1498 u16 intr_event;
1499 u16 napi_event;
ccdffb9a 1500 unsigned features;
0e485150
FR		 1501} rtl_cfg_infos [] = {
1502 [RTL_CFG_0] = {
1503 .hw_start = rtl_hw_start_8169,
1504 .region = 1,
e9f63f30 1505 .align = 0,
0e485150
FR		 1506 .intr_event = SYSErr | LinkChg | RxOverflow |
1507 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1508 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1509 .features = RTL_FEATURE_GMII
0e485150
FR		 1510 },
1511 [RTL_CFG_1] = {
1512 .hw_start = rtl_hw_start_8168,
1513 .region = 2,
1514 .align = 8,
1515 .intr_event = SYSErr | LinkChg | RxOverflow |
1516 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1517 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1518 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1519 },
1520 [RTL_CFG_2] = {
1521 .hw_start = rtl_hw_start_8101,
1522 .region = 2,
1523 .align = 8,
1524 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1525 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1526 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1527 .features = RTL_FEATURE_MSI
0e485150
FR		 1528 }
1529};
1530
fbac58fc
FR		 1531/* Cfg9346_Unlock assumed. */
1532static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1533 const struct rtl_cfg_info *cfg)
1534{
1535 unsigned msi = 0;
1536 u8 cfg2;
1537
1538 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1539 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1540 if (pci_enable_msi(pdev)) {
1541 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1542 } else {
1543 cfg2 |= MSIEnable;
1544 msi = RTL_FEATURE_MSI;
1545 }
1546 }
1547 RTL_W8(Config2, cfg2);
1548 return msi;
1549}
1550
1551static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1552{
1553 if (tp->features & RTL_FEATURE_MSI) {
1554 pci_disable_msi(pdev);
1555 tp->features &= ~RTL_FEATURE_MSI;
1556 }
1557}
1558
1da177e4 1559static int __devinit
4ff96fa6 1560rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1561{
0e485150
FR		 1562 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1563 const unsigned int region = cfg->region;
1da177e4 1564 struct rtl8169_private *tp;
ccdffb9a 1565 struct mii_if_info *mii;
4ff96fa6
FR		 1566 struct net_device *dev;
1567 void __iomem *ioaddr;
07d3f51f
FR		 1568 unsigned int i;
1569 int rc;
1da177e4 1570
4ff96fa6
FR		 1571 if (netif_msg_drv(&debug)) {
1572 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1573 MODULENAME, RTL8169_VERSION);
1574 }
1da177e4 1575
1da177e4 1576 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1577 if (!dev) {
b57b7e5a 1578 if (netif_msg_drv(&debug))
9b91cf9d 1579 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1580 rc = -ENOMEM;
1581 goto out;
1da177e4
LT		 1582 }
1583
1da177e4
LT		 1584 SET_NETDEV_DEV(dev, &pdev->dev);
1585 tp = netdev_priv(dev);
c4028958 1586 tp->dev = dev;
21e197f2 1587 tp->pci_dev = pdev;
b57b7e5a 1588 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1589
ccdffb9a
FR		 1590 mii = &tp->mii;
1591 mii->dev = dev;
1592 mii->mdio_read = rtl_mdio_read;
1593 mii->mdio_write = rtl_mdio_write;
1594 mii->phy_id_mask = 0x1f;
1595 mii->reg_num_mask = 0x1f;
1596 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1597
1da177e4
LT		 1598 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1599 rc = pci_enable_device(pdev);
b57b7e5a 1600 if (rc < 0) {
2e8a538d 1601 if (netif_msg_probe(tp))
9b91cf9d 1602 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1603 goto err_out_free_dev_1;
1da177e4
LT		 1604 }
1605
1606 rc = pci_set_mwi(pdev);
1607 if (rc < 0)
4ff96fa6 1608 goto err_out_disable_2;
1da177e4 1609
1da177e4 1610 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1611 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1612 if (netif_msg_probe(tp)) {
9b91cf9d 1613 dev_err(&pdev->dev,
bcf0bf90
FR		 1614 "region #%d not an MMIO resource, aborting\n",
1615 region);
4ff96fa6 1616 }
1da177e4 1617 rc = -ENODEV;
4ff96fa6 1618 goto err_out_mwi_3;
1da177e4 1619 }
4ff96fa6 1620
1da177e4 1621 /* check for weird/broken PCI region reporting */
bcf0bf90 1622 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1623 if (netif_msg_probe(tp)) {
9b91cf9d 1624 dev_err(&pdev->dev,
4ff96fa6
FR		 1625 "Invalid PCI region size(s), aborting\n");
1626 }
1da177e4 1627 rc = -ENODEV;
4ff96fa6 1628 goto err_out_mwi_3;
1da177e4
LT		 1629 }
1630
1631 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1632 if (rc < 0) {
2e8a538d 1633 if (netif_msg_probe(tp))
9b91cf9d 1634 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1635 goto err_out_mwi_3;
1da177e4
LT		 1636 }
1637
1638 tp->cp_cmd = PCIMulRW | RxChkSum;
1639
1640 if ((sizeof(dma_addr_t) > 4) &&
1641 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1642 tp->cp_cmd |= PCIDAC;
1643 dev->features |= NETIF_F_HIGHDMA;
1644 } else {
1645 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1646 if (rc < 0) {
4ff96fa6 1647 if (netif_msg_probe(tp)) {
9b91cf9d 1648 dev_err(&pdev->dev,
4ff96fa6
FR		 1649 "DMA configuration failed.\n");
1650 }
1651 goto err_out_free_res_4;
1da177e4
LT		 1652 }
1653 }
1654
1655 pci_set_master(pdev);
1656
1657 /* ioremap MMIO region */
bcf0bf90 1658 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1659 if (!ioaddr) {
b57b7e5a 1660 if (netif_msg_probe(tp))
9b91cf9d 1661 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1662 rc = -EIO;
4ff96fa6 1663 goto err_out_free_res_4;
1da177e4
LT		 1664 }
1665
1666 /* Unneeded ? Don't mess with Mrs. Murphy. */
1667 rtl8169_irq_mask_and_ack(ioaddr);
1668
1669 /* Soft reset the chip. */
1670 RTL_W8(ChipCmd, CmdReset);
1671
1672 /* Check that the chip has finished the reset. */
07d3f51f 1673 for (i = 0; i < 100; i++) {
1da177e4
LT		 1674 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1675 break;
b518fa8e 1676 msleep_interruptible(1);
1da177e4
LT		 1677 }
1678
1679 /* Identify chip attached to board */
1680 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1681
1682 rtl8169_print_mac_version(tp);
1da177e4 1683
cee60c37 1684 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1685 if (tp->mac_version == rtl_chip_info[i].mac_version)
1686 break;
1687 }
cee60c37 1688 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1689 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1690 if (netif_msg_probe(tp)) {
2e8a538d 1691 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1692 "unknown chip version, assuming %s\n",
1693 rtl_chip_info[0].name);
b57b7e5a 1694 }
cee60c37 1695 i = 0;
1da177e4
LT		 1696 }
1697 tp->chipset = i;
1698
5d06a99f
FR		 1699 RTL_W8(Cfg9346, Cfg9346_Unlock);
1700 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1701 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1702 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1703 RTL_W8(Cfg9346, Cfg9346_Lock);
1704
66ec5d4f
FR		 1705 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1706 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1707 tp->set_speed = rtl8169_set_speed_tbi;
1708 tp->get_settings = rtl8169_gset_tbi;
1709 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1710 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1711 tp->link_ok = rtl8169_tbi_link_ok;
1712
64e4bfb4 1713 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1714 } else {
1715 tp->set_speed = rtl8169_set_speed_xmii;
1716 tp->get_settings = rtl8169_gset_xmii;
1717 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1718 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1719 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1720
1721 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1722 }
1723
1724 /* Get MAC address. FIXME: read EEPROM */
1725 for (i = 0; i < MAC_ADDR_LEN; i++)
1726 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1727 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1728
1729 dev->open = rtl8169_open;
1730 dev->hard_start_xmit = rtl8169_start_xmit;
1731 dev->get_stats = rtl8169_get_stats;
1732 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1733 dev->stop = rtl8169_close;
1734 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1735 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1736 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1737 dev->irq = pdev->irq;
1738 dev->base_addr = (unsigned long) ioaddr;
1739 dev->change_mtu = rtl8169_change_mtu;
773d2021 1740 dev->set_mac_address = rtl_set_mac_address;
1da177e4 1741
bea3348e 1742 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1743
1744#ifdef CONFIG_R8169_VLAN
1745 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1746 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1747#endif
1748
1749#ifdef CONFIG_NET_POLL_CONTROLLER
1750 dev->poll_controller = rtl8169_netpoll;
1751#endif
1752
1753 tp->intr_mask = 0xffff;
1da177e4 1754 tp->mmio_addr = ioaddr;
0e485150
FR		 1755 tp->align = cfg->align;
1756 tp->hw_start = cfg->hw_start;
1757 tp->intr_event = cfg->intr_event;
1758 tp->napi_event = cfg->napi_event;
1da177e4 1759
2efa53f3
FR		 1760 init_timer(&tp->timer);
1761 tp->timer.data = (unsigned long) dev;
1762 tp->timer.function = rtl8169_phy_timer;
1763
1da177e4
LT		 1764 spin_lock_init(&tp->lock);
1765
1766 rc = register_netdev(dev);
4ff96fa6 1767 if (rc < 0)
fbac58fc 1768 goto err_out_msi_5;
1da177e4
LT		 1769
1770 pci_set_drvdata(pdev, dev);
1771
b57b7e5a 1772 if (netif_msg_probe(tp)) {
96b9709c
FR		 1773 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1774
b57b7e5a
SH		 1775 printk(KERN_INFO "%s: %s at 0x%lx, "
1776 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1777 "XID %08x IRQ %d\n",
b57b7e5a 1778 dev->name,
bcf0bf90 1779 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1780 dev->base_addr,
1781 dev->dev_addr[0], dev->dev_addr[1],
1782 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1783 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1784 }
1da177e4 1785
4ff96fa6 1786 rtl8169_init_phy(dev, tp);
1da177e4 1787
4ff96fa6
FR		 1788out:
1789 return rc;
1da177e4 1790
fbac58fc
FR		 1791err_out_msi_5:
1792 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1793 iounmap(ioaddr);
1794err_out_free_res_4:
1795 pci_release_regions(pdev);
1796err_out_mwi_3:
1797 pci_clear_mwi(pdev);
1798err_out_disable_2:
1799 pci_disable_device(pdev);
1800err_out_free_dev_1:
1801 free_netdev(dev);
1802 goto out;
1da177e4
LT		 1803}
1804
07d3f51f 1805static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1806{
1807 struct net_device *dev = pci_get_drvdata(pdev);
1808 struct rtl8169_private *tp = netdev_priv(dev);
1809
eb2a021c
FR		 1810 flush_scheduled_work();
1811
1da177e4 1812 unregister_netdev(dev);
fbac58fc 1813 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1814 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1815 pci_set_drvdata(pdev, NULL);
1816}
1817
1da177e4
LT		 1818static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1819 struct net_device *dev)
1820{
1821 unsigned int mtu = dev->mtu;
1822
1823 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1824}
1825
1826static int rtl8169_open(struct net_device *dev)
1827{
1828 struct rtl8169_private *tp = netdev_priv(dev);
1829 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1830 int retval = -ENOMEM;
1da177e4 1831
1da177e4 1832
99f252b0 1833 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1834
1835 /*
1836 * Rx and Tx desscriptors needs 256 bytes alignment.
1837 * pci_alloc_consistent provides more.
1838 */
1839 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1840 &tp->TxPhyAddr);
1841 if (!tp->TxDescArray)
99f252b0 1842 goto out;
1da177e4
LT		 1843
1844 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1845 &tp->RxPhyAddr);
1846 if (!tp->RxDescArray)
99f252b0 1847 goto err_free_tx_0;
1da177e4
LT		 1848
1849 retval = rtl8169_init_ring(dev);
1850 if (retval < 0)
99f252b0 1851 goto err_free_rx_1;
1da177e4 1852
c4028958 1853 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1854
99f252b0
FR		 1855 smp_mb();
1856
fbac58fc
FR		 1857 retval = request_irq(dev->irq, rtl8169_interrupt,
1858 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1859 dev->name, dev);
1860 if (retval < 0)
1861 goto err_release_ring_2;
1862
bea3348e 1863 napi_enable(&tp->napi);
bea3348e 1864
07ce4064 1865 rtl_hw_start(dev);
1da177e4
LT		 1866
1867 rtl8169_request_timer(dev);
1868
1869 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1870out:
1871 return retval;
1872
99f252b0
FR		 1873err_release_ring_2:
1874 rtl8169_rx_clear(tp);
1875err_free_rx_1:
1da177e4
LT		 1876 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1877 tp->RxPhyAddr);
99f252b0 1878err_free_tx_0:
1da177e4
LT		 1879 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1880 tp->TxPhyAddr);
1da177e4
LT		 1881 goto out;
1882}
1883
1884static void rtl8169_hw_reset(void __iomem *ioaddr)
1885{
1886 /* Disable interrupts */
1887 rtl8169_irq_mask_and_ack(ioaddr);
1888
1889 /* Reset the chipset */
1890 RTL_W8(ChipCmd, CmdReset);
1891
1892 /* PCI commit */
1893 RTL_R8(ChipCmd);
1894}
1895
7f796d83 1896static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1897{
1898 void __iomem *ioaddr = tp->mmio_addr;
1899 u32 cfg = rtl8169_rx_config;
1900
1901 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1902 RTL_W32(RxConfig, cfg);
1903
1904 /* Set DMA burst size and Interframe Gap Time */
1905 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1906 (InterFrameGap << TxInterFrameGapShift));
1907}
1908
07ce4064 1909static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1910{
1911 struct rtl8169_private *tp = netdev_priv(dev);
1912 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1913 unsigned int i;
1da177e4
LT		 1914
1915 /* Soft reset the chip. */
1916 RTL_W8(ChipCmd, CmdReset);
1917
1918 /* Check that the chip has finished the reset. */
07d3f51f 1919 for (i = 0; i < 100; i++) {
1da177e4
LT		 1920 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1921 break;
b518fa8e 1922 msleep_interruptible(1);
1da177e4
LT		 1923 }
1924
07ce4064
FR		 1925 tp->hw_start(dev);
1926
07ce4064
FR		 1927 netif_start_queue(dev);
1928}
1929
1930
7f796d83
FR		 1931static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1932 void __iomem *ioaddr)
1933{
1934 /*
1935 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1936 * register to be written before TxDescAddrLow to work.
1937 * Switching from MMIO to I/O access fixes the issue as well.
1938 */
1939 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1940 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1941 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1942 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1943}
1944
1945static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1946{
1947 u16 cmd;
1948
1949 cmd = RTL_R16(CPlusCmd);
1950 RTL_W16(CPlusCmd, cmd);
1951 return cmd;
1952}
1953
1954static void rtl_set_rx_max_size(void __iomem *ioaddr)
1955{
1956 /* Low hurts. Let's disable the filtering. */
1957 RTL_W16(RxMaxSize, 16383);
1958}
1959
6dccd16b
FR		 1960static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1961{
1962 struct {
1963 u32 mac_version;
1964 u32 clk;
1965 u32 val;
1966 } cfg2_info [] = {
1967 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1968 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1969 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1970 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1971 }, *p = cfg2_info;
1972 unsigned int i;
1973 u32 clk;
1974
1975 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 1976 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 1977 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1978 RTL_W32(0x7c, p->val);
1979 break;
1980 }
1981 }
1982}
1983
07ce4064
FR		 1984static void rtl_hw_start_8169(struct net_device *dev)
1985{
1986 struct rtl8169_private *tp = netdev_priv(dev);
1987 void __iomem *ioaddr = tp->mmio_addr;
1988 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1989
9cb427b6
FR		 1990 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1991 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1992 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1993 }
1994
1da177e4 1995 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1996 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1997 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1998 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1999 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2000 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2001
1da177e4
LT		 2002 RTL_W8(EarlyTxThres, EarlyTxThld);
2003
7f796d83 2004 rtl_set_rx_max_size(ioaddr);
1da177e4 2005
c946b304
FR		 2006 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2007 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2008 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2009 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2010 rtl_set_rx_tx_config_registers(tp);
1da177e4 2011
7f796d83 2012 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2013
bcf0bf90
FR		 2014 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2015 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2016 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2017 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2018 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2019 }
2020
bcf0bf90
FR		 2021 RTL_W16(CPlusCmd, tp->cp_cmd);
2022
6dccd16b
FR		 2023 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2024
1da177e4
LT		 2025 /*
2026 * Undocumented corner. Supposedly:
2027 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2028 */
2029 RTL_W16(IntrMitigate, 0x0000);
2030
7f796d83 2031 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2032
c946b304
FR		 2033 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2034 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2035 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2036 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2037 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2038 rtl_set_rx_tx_config_registers(tp);
2039 }
2040
1da177e4 2041 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2042
2043 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2044 RTL_R8(IntrMask);
1da177e4
LT		 2045
2046 RTL_W32(RxMissed, 0);
2047
07ce4064 2048 rtl_set_rx_mode(dev);
1da177e4
LT		 2049
2050 /* no early-rx interrupts */
2051 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2052
2053 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2054 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2055}
1da177e4 2056
07ce4064
FR		 2057static void rtl_hw_start_8168(struct net_device *dev)
2058{
2dd99530
FR		 2059 struct rtl8169_private *tp = netdev_priv(dev);
2060 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2061 struct pci_dev *pdev = tp->pci_dev;
2062 u8 ctl;
2dd99530
FR		 2063
2064 RTL_W8(Cfg9346, Cfg9346_Unlock);
2065
2066 RTL_W8(EarlyTxThres, EarlyTxThld);
2067
2068 rtl_set_rx_max_size(ioaddr);
2069
0e485150
FR		 2070 rtl_set_rx_tx_config_registers(tp);
2071
2072 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2073
2074 RTL_W16(CPlusCmd, tp->cp_cmd);
2075
0e485150
FR		 2076 /* Tx performance tweak. */
2077 pci_read_config_byte(pdev, 0x69, &ctl);
2078 ctl = (ctl & ~0x70) | 0x50;
2079 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2080
0e485150 2081 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2082
0e485150
FR		 2083 /* Work around for RxFIFO overflow. */
2084 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2085 tp->intr_event |= RxFIFOOver | PCSTimeout;
2086 tp->intr_event &= ~RxOverflow;
2087 }
2088
2089 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2090
2091 RTL_W8(Cfg9346, Cfg9346_Lock);
2092
2093 RTL_R8(IntrMask);
2094
2095 RTL_W32(RxMissed, 0);
2096
2097 rtl_set_rx_mode(dev);
2098
0e485150
FR		 2099 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2100
2dd99530 2101 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2102
0e485150 2103 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2104}
1da177e4 2105
07ce4064
FR		 2106static void rtl_hw_start_8101(struct net_device *dev)
2107{
cdf1a608
FR		 2108 struct rtl8169_private *tp = netdev_priv(dev);
2109 void __iomem *ioaddr = tp->mmio_addr;
2110 struct pci_dev *pdev = tp->pci_dev;
2111
e3cf0cc0
FR		 2112 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2113 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2114 pci_write_config_word(pdev, 0x68, 0x00);
2115 pci_write_config_word(pdev, 0x69, 0x08);
2116 }
2117
2118 RTL_W8(Cfg9346, Cfg9346_Unlock);
2119
2120 RTL_W8(EarlyTxThres, EarlyTxThld);
2121
2122 rtl_set_rx_max_size(ioaddr);
2123
2124 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2125
2126 RTL_W16(CPlusCmd, tp->cp_cmd);
2127
2128 RTL_W16(IntrMitigate, 0x0000);
2129
2130 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2131
2132 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2133 rtl_set_rx_tx_config_registers(tp);
2134
2135 RTL_W8(Cfg9346, Cfg9346_Lock);
2136
2137 RTL_R8(IntrMask);
2138
2139 RTL_W32(RxMissed, 0);
2140
2141 rtl_set_rx_mode(dev);
2142
0e485150
FR		 2143 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2144
cdf1a608 2145 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2146
0e485150 2147 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2148}
2149
2150static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2151{
2152 struct rtl8169_private *tp = netdev_priv(dev);
2153 int ret = 0;
2154
2155 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2156 return -EINVAL;
2157
2158 dev->mtu = new_mtu;
2159
2160 if (!netif_running(dev))
2161 goto out;
2162
2163 rtl8169_down(dev);
2164
2165 rtl8169_set_rxbufsize(tp, dev);
2166
2167 ret = rtl8169_init_ring(dev);
2168 if (ret < 0)
2169 goto out;
2170
bea3348e 2171 napi_enable(&tp->napi);
1da177e4 2172
07ce4064 2173 rtl_hw_start(dev);
1da177e4
LT		 2174
2175 rtl8169_request_timer(dev);
2176
2177out:
2178 return ret;
2179}
2180
2181static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2182{
95e0918d 2183 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2184 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2185}
2186
2187static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2188 struct sk_buff **sk_buff, struct RxDesc *desc)
2189{
2190 struct pci_dev *pdev = tp->pci_dev;
2191
2192 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2193 PCI_DMA_FROMDEVICE);
2194 dev_kfree_skb(*sk_buff);
2195 *sk_buff = NULL;
2196 rtl8169_make_unusable_by_asic(desc);
2197}
2198
2199static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2200{
2201 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2202
2203 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2204}
2205
2206static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2207 u32 rx_buf_sz)
2208{
2209 desc->addr = cpu_to_le64(mapping);
2210 wmb();
2211 rtl8169_mark_to_asic(desc, rx_buf_sz);
2212}
2213
15d31758
SH		 2214static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2215 struct net_device *dev,
2216 struct RxDesc *desc, int rx_buf_sz,
2217 unsigned int align)
1da177e4
LT		 2218{
2219 struct sk_buff *skb;
2220 dma_addr_t mapping;
e9f63f30 2221 unsigned int pad;
1da177e4 2222
e9f63f30
FR		 2223 pad = align ? align : NET_IP_ALIGN;
2224
2225 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2226 if (!skb)
2227 goto err_out;
2228
e9f63f30 2229 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2230
689be439 2231 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2232 PCI_DMA_FROMDEVICE);
2233
2234 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2235out:
15d31758 2236 return skb;
1da177e4
LT		 2237
2238err_out:
1da177e4
LT		 2239 rtl8169_make_unusable_by_asic(desc);
2240 goto out;
2241}
2242
2243static void rtl8169_rx_clear(struct rtl8169_private *tp)
2244{
07d3f51f 2245 unsigned int i;
1da177e4
LT		 2246
2247 for (i = 0; i < NUM_RX_DESC; i++) {
2248 if (tp->Rx_skbuff[i]) {
2249 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2250 tp->RxDescArray + i);
2251 }
2252 }
2253}
2254
2255static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2256 u32 start, u32 end)
2257{
2258 u32 cur;
5b0384f4 2259
4ae47c2d 2260 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2261 struct sk_buff *skb;
2262 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2263
4ae47c2d
FR		 2264 WARN_ON((s32)(end - cur) < 0);
2265
1da177e4
LT		 2266 if (tp->Rx_skbuff[i])
2267 continue;
bcf0bf90 2268
15d31758
SH		 2269 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2270 tp->RxDescArray + i,
2271 tp->rx_buf_sz, tp->align);
2272 if (!skb)
1da177e4 2273 break;
15d31758
SH		 2274
2275 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2276 }
2277 return cur - start;
2278}
2279
2280static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2281{
2282 desc->opts1 |= cpu_to_le32(RingEnd);
2283}
2284
2285static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2286{
2287 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2288}
2289
2290static int rtl8169_init_ring(struct net_device *dev)
2291{
2292 struct rtl8169_private *tp = netdev_priv(dev);
2293
2294 rtl8169_init_ring_indexes(tp);
2295
2296 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2297 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2298
2299 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2300 goto err_out;
2301
2302 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2303
2304 return 0;
2305
2306err_out:
2307 rtl8169_rx_clear(tp);
2308 return -ENOMEM;
2309}
2310
2311static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2312 struct TxDesc *desc)
2313{
2314 unsigned int len = tx_skb->len;
2315
2316 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2317 desc->opts1 = 0x00;
2318 desc->opts2 = 0x00;
2319 desc->addr = 0x00;
2320 tx_skb->len = 0;
2321}
2322
2323static void rtl8169_tx_clear(struct rtl8169_private *tp)
2324{
2325 unsigned int i;
2326
2327 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2328 unsigned int entry = i % NUM_TX_DESC;
2329 struct ring_info *tx_skb = tp->tx_skb + entry;
2330 unsigned int len = tx_skb->len;
2331
2332 if (len) {
2333 struct sk_buff *skb = tx_skb->skb;
2334
2335 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2336 tp->TxDescArray + entry);
2337 if (skb) {
2338 dev_kfree_skb(skb);
2339 tx_skb->skb = NULL;
2340 }
cebf8cc7 2341 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2342 }
2343 }
2344 tp->cur_tx = tp->dirty_tx = 0;
2345}
2346
c4028958 2347static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2348{
2349 struct rtl8169_private *tp = netdev_priv(dev);
2350
c4028958 2351 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2352 schedule_delayed_work(&tp->task, 4);
2353}
2354
2355static void rtl8169_wait_for_quiescence(struct net_device *dev)
2356{
2357 struct rtl8169_private *tp = netdev_priv(dev);
2358 void __iomem *ioaddr = tp->mmio_addr;
2359
2360 synchronize_irq(dev->irq);
2361
2362 /* Wait for any pending NAPI task to complete */
bea3348e 2363 napi_disable(&tp->napi);
1da177e4
LT		 2364
2365 rtl8169_irq_mask_and_ack(ioaddr);
2366
d1d08d12
DM		 2367 tp->intr_mask = 0xffff;
2368 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2369 napi_enable(&tp->napi);
1da177e4
LT		 2370}
2371
c4028958 2372static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2373{
c4028958
DH		 2374 struct rtl8169_private *tp =
2375 container_of(work, struct rtl8169_private, task.work);
2376 struct net_device *dev = tp->dev;
1da177e4
LT		 2377 int ret;
2378
eb2a021c
FR		 2379 rtnl_lock();
2380
2381 if (!netif_running(dev))
2382 goto out_unlock;
2383
2384 rtl8169_wait_for_quiescence(dev);
2385 rtl8169_close(dev);
1da177e4
LT		 2386
2387 ret = rtl8169_open(dev);
2388 if (unlikely(ret < 0)) {
07d3f51f 2389 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2390 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2391 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2392 }
2393 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2394 }
eb2a021c
FR		 2395
2396out_unlock:
2397 rtnl_unlock();
1da177e4
LT		 2398}
2399
c4028958 2400static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2401{
c4028958
DH		 2402 struct rtl8169_private *tp =
2403 container_of(work, struct rtl8169_private, task.work);
2404 struct net_device *dev = tp->dev;
1da177e4 2405
eb2a021c
FR		 2406 rtnl_lock();
2407
1da177e4 2408 if (!netif_running(dev))
eb2a021c 2409 goto out_unlock;
1da177e4
LT		 2410
2411 rtl8169_wait_for_quiescence(dev);
2412
bea3348e 2413 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2414 rtl8169_tx_clear(tp);
2415
2416 if (tp->dirty_rx == tp->cur_rx) {
2417 rtl8169_init_ring_indexes(tp);
07ce4064 2418 rtl_hw_start(dev);
1da177e4 2419 netif_wake_queue(dev);
cebf8cc7 2420 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2421 } else {
07d3f51f 2422 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2423 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2424 dev->name);
1da177e4
LT		 2425 }
2426 rtl8169_schedule_work(dev, rtl8169_reset_task);
2427 }
eb2a021c
FR		 2428
2429out_unlock:
2430 rtnl_unlock();
1da177e4
LT		 2431}
2432
2433static void rtl8169_tx_timeout(struct net_device *dev)
2434{
2435 struct rtl8169_private *tp = netdev_priv(dev);
2436
2437 rtl8169_hw_reset(tp->mmio_addr);
2438
2439 /* Let's wait a bit while any (async) irq lands on */
2440 rtl8169_schedule_work(dev, rtl8169_reset_task);
2441}
2442
2443static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2444 u32 opts1)
2445{
2446 struct skb_shared_info *info = skb_shinfo(skb);
2447 unsigned int cur_frag, entry;
a6343afb 2448 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2449
2450 entry = tp->cur_tx;
2451 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2452 skb_frag_t *frag = info->frags + cur_frag;
2453 dma_addr_t mapping;
2454 u32 status, len;
2455 void *addr;
2456
2457 entry = (entry + 1) % NUM_TX_DESC;
2458
2459 txd = tp->TxDescArray + entry;
2460 len = frag->size;
2461 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2462 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2463
2464 /* anti gcc 2.95.3 bugware (sic) */
2465 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2466
2467 txd->opts1 = cpu_to_le32(status);
2468 txd->addr = cpu_to_le64(mapping);
2469
2470 tp->tx_skb[entry].len = len;
2471 }
2472
2473 if (cur_frag) {
2474 tp->tx_skb[entry].skb = skb;
2475 txd->opts1 |= cpu_to_le32(LastFrag);
2476 }
2477
2478 return cur_frag;
2479}
2480
2481static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2482{
2483 if (dev->features & NETIF_F_TSO) {
7967168c 2484 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2485
2486 if (mss)
2487 return LargeSend | ((mss & MSSMask) << MSSShift);
2488 }
84fa7933 2489 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2490 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2491
2492 if (ip->protocol == IPPROTO_TCP)
2493 return IPCS | TCPCS;
2494 else if (ip->protocol == IPPROTO_UDP)
2495 return IPCS | UDPCS;
2496 WARN_ON(1); /* we need a WARN() */
2497 }
2498 return 0;
2499}
2500
2501static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2502{
2503 struct rtl8169_private *tp = netdev_priv(dev);
2504 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2505 struct TxDesc *txd = tp->TxDescArray + entry;
2506 void __iomem *ioaddr = tp->mmio_addr;
2507 dma_addr_t mapping;
2508 u32 status, len;
2509 u32 opts1;
188f4af0 2510 int ret = NETDEV_TX_OK;
5b0384f4 2511
1da177e4 2512 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2513 if (netif_msg_drv(tp)) {
2514 printk(KERN_ERR
2515 "%s: BUG! Tx Ring full when queue awake!\n",
2516 dev->name);
2517 }
1da177e4
LT		 2518 goto err_stop;
2519 }
2520
2521 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2522 goto err_stop;
2523
2524 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2525
2526 frags = rtl8169_xmit_frags(tp, skb, opts1);
2527 if (frags) {
2528 len = skb_headlen(skb);
2529 opts1 |= FirstFrag;
2530 } else {
2531 len = skb->len;
2532
2533 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2534 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2535 goto err_update_stats;
2536 len = ETH_ZLEN;
2537 }
2538
2539 opts1 |= FirstFrag | LastFrag;
2540 tp->tx_skb[entry].skb = skb;
2541 }
2542
2543 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2544
2545 tp->tx_skb[entry].len = len;
2546 txd->addr = cpu_to_le64(mapping);
2547 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2548
2549 wmb();
2550
2551 /* anti gcc 2.95.3 bugware (sic) */
2552 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2553 txd->opts1 = cpu_to_le32(status);
2554
2555 dev->trans_start = jiffies;
2556
2557 tp->cur_tx += frags + 1;
2558
2559 smp_wmb();
2560
275391a4 2561 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2562
2563 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2564 netif_stop_queue(dev);
2565 smp_rmb();
2566 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2567 netif_wake_queue(dev);
2568 }
2569
2570out:
2571 return ret;
2572
2573err_stop:
2574 netif_stop_queue(dev);
188f4af0 2575 ret = NETDEV_TX_BUSY;
1da177e4 2576err_update_stats:
cebf8cc7 2577 dev->stats.tx_dropped++;
1da177e4
LT		 2578 goto out;
2579}
2580
2581static void rtl8169_pcierr_interrupt(struct net_device *dev)
2582{
2583 struct rtl8169_private *tp = netdev_priv(dev);
2584 struct pci_dev *pdev = tp->pci_dev;
2585 void __iomem *ioaddr = tp->mmio_addr;
2586 u16 pci_status, pci_cmd;
2587
2588 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2589 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2590
b57b7e5a
SH		 2591 if (netif_msg_intr(tp)) {
2592 printk(KERN_ERR
2593 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2594 dev->name, pci_cmd, pci_status);
2595 }
1da177e4
LT		 2596
2597 /*
2598 * The recovery sequence below admits a very elaborated explanation:
2599 * - it seems to work;
d03902b8
FR		 2600 * - I did not see what else could be done;
2601 * - it makes iop3xx happy.
1da177e4
LT		 2602 *
2603 * Feel free to adjust to your needs.
2604 */
a27993f3 2605 if (pdev->broken_parity_status)
d03902b8
FR		 2606 pci_cmd &= ~PCI_COMMAND_PARITY;
2607 else
2608 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2609
2610 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2611
2612 pci_write_config_word(pdev, PCI_STATUS,
2613 pci_status & (PCI_STATUS_DETECTED_PARITY |
2614 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2615 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2616
2617 /* The infamous DAC f*ckup only happens at boot time */
2618 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2619 if (netif_msg_intr(tp))
2620 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2621 tp->cp_cmd &= ~PCIDAC;
2622 RTL_W16(CPlusCmd, tp->cp_cmd);
2623 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2624 }
2625
2626 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2627
2628 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2629}
2630
07d3f51f
FR		 2631static void rtl8169_tx_interrupt(struct net_device *dev,
2632 struct rtl8169_private *tp,
2633 void __iomem *ioaddr)
1da177e4
LT		 2634{
2635 unsigned int dirty_tx, tx_left;
2636
1da177e4
LT		 2637 dirty_tx = tp->dirty_tx;
2638 smp_rmb();
2639 tx_left = tp->cur_tx - dirty_tx;
2640
2641 while (tx_left > 0) {
2642 unsigned int entry = dirty_tx % NUM_TX_DESC;
2643 struct ring_info *tx_skb = tp->tx_skb + entry;
2644 u32 len = tx_skb->len;
2645 u32 status;
2646
2647 rmb();
2648 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2649 if (status & DescOwn)
2650 break;
2651
cebf8cc7
FR		 2652 dev->stats.tx_bytes += len;
2653 dev->stats.tx_packets++;
1da177e4
LT		 2654
2655 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2656
2657 if (status & LastFrag) {
2658 dev_kfree_skb_irq(tx_skb->skb);
2659 tx_skb->skb = NULL;
2660 }
2661 dirty_tx++;
2662 tx_left--;
2663 }
2664
2665 if (tp->dirty_tx != dirty_tx) {
2666 tp->dirty_tx = dirty_tx;
2667 smp_wmb();
2668 if (netif_queue_stopped(dev) &&
2669 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2670 netif_wake_queue(dev);
2671 }
d78ae2dc
FR		 2672 /*
2673 * 8168 hack: TxPoll requests are lost when the Tx packets are
2674 * too close. Let's kick an extra TxPoll request when a burst
2675 * of start_xmit activity is detected (if it is not detected,
2676 * it is slow enough). -- FR
2677 */
2678 smp_rmb();
2679 if (tp->cur_tx != dirty_tx)
2680 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2681 }
2682}
2683
126fa4b9
FR		 2684static inline int rtl8169_fragmented_frame(u32 status)
2685{
2686 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2687}
2688
1da177e4
LT		 2689static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2690{
2691 u32 opts1 = le32_to_cpu(desc->opts1);
2692 u32 status = opts1 & RxProtoMask;
2693
2694 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2695 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2696 ((status == RxProtoIP) && !(opts1 & IPFail)))
2697 skb->ip_summed = CHECKSUM_UNNECESSARY;
2698 else
2699 skb->ip_summed = CHECKSUM_NONE;
2700}
2701
07d3f51f
FR		 2702static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2703 struct rtl8169_private *tp, int pkt_size,
2704 dma_addr_t addr)
1da177e4 2705{
b449655f
SH		 2706 struct sk_buff *skb;
2707 bool done = false;
1da177e4 2708
b449655f
SH		 2709 if (pkt_size >= rx_copybreak)
2710 goto out;
1da177e4 2711
07d3f51f 2712 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2713 if (!skb)
2714 goto out;
2715
07d3f51f
FR		 2716 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2717 PCI_DMA_FROMDEVICE);
86402234 2718 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2719 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2720 *sk_buff = skb;
2721 done = true;
2722out:
2723 return done;
1da177e4
LT		 2724}
2725
07d3f51f
FR		 2726static int rtl8169_rx_interrupt(struct net_device *dev,
2727 struct rtl8169_private *tp,
bea3348e 2728 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2729{
2730 unsigned int cur_rx, rx_left;
2731 unsigned int delta, count;
2732
1da177e4
LT		 2733 cur_rx = tp->cur_rx;
2734 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 2735 rx_left = min(rx_left, budget);
1da177e4 2736
4dcb7d33 2737 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2738 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2739 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2740 u32 status;
2741
2742 rmb();
126fa4b9 2743 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2744
2745 if (status & DescOwn)
2746 break;
4dcb7d33 2747 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2748 if (netif_msg_rx_err(tp)) {
2749 printk(KERN_INFO
2750 "%s: Rx ERROR. status = %08x\n",
2751 dev->name, status);
2752 }
cebf8cc7 2753 dev->stats.rx_errors++;
1da177e4 2754 if (status & (RxRWT | RxRUNT))
cebf8cc7 2755 dev->stats.rx_length_errors++;
1da177e4 2756 if (status & RxCRC)
cebf8cc7 2757 dev->stats.rx_crc_errors++;
9dccf611
FR		 2758 if (status & RxFOVF) {
2759 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2760 dev->stats.rx_fifo_errors++;
9dccf611 2761 }
126fa4b9 2762 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2763 } else {
1da177e4 2764 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2765 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2766 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2767 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2768
126fa4b9
FR		 2769 /*
2770 * The driver does not support incoming fragmented
2771 * frames. They are seen as a symptom of over-mtu
2772 * sized frames.
2773 */
2774 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2775 dev->stats.rx_dropped++;
2776 dev->stats.rx_length_errors++;
126fa4b9 2777 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2778 continue;
126fa4b9
FR		 2779 }
2780
1da177e4 2781 rtl8169_rx_csum(skb, desc);
bcf0bf90 2782
07d3f51f 2783 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2784 pci_dma_sync_single_for_device(pdev, addr,
2785 pkt_size, PCI_DMA_FROMDEVICE);
2786 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2787 } else {
2788 pci_unmap_single(pdev, addr, pkt_size,
2789 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2790 tp->Rx_skbuff[entry] = NULL;
2791 }
2792
1da177e4
LT		 2793 skb_put(skb, pkt_size);
2794 skb->protocol = eth_type_trans(skb, dev);
2795
2796 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 2797 netif_receive_skb(skb);
1da177e4
LT		 2798
2799 dev->last_rx = jiffies;
cebf8cc7
FR		 2800 dev->stats.rx_bytes += pkt_size;
2801 dev->stats.rx_packets++;
1da177e4 2802 }
6dccd16b
FR		 2803
2804 /* Work around for AMD plateform. */
95e0918d 2805 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 2806 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2807 desc->opts2 = 0;
2808 cur_rx++;
2809 }
1da177e4
LT		 2810 }
2811
2812 count = cur_rx - tp->cur_rx;
2813 tp->cur_rx = cur_rx;
2814
2815 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2816 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2817 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2818 tp->dirty_rx += delta;
2819
2820 /*
2821 * FIXME: until there is periodic timer to try and refill the ring,
2822 * a temporary shortage may definitely kill the Rx process.
2823 * - disable the asic to try and avoid an overflow and kick it again
2824 * after refill ?
2825 * - how do others driver handle this condition (Uh oh...).
2826 */
b57b7e5a 2827 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2828 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2829
2830 return count;
2831}
2832
07d3f51f 2833static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2834{
07d3f51f 2835 struct net_device *dev = dev_instance;
1da177e4 2836 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 2837 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 2838 int handled = 0;
865c652d 2839 int status;
1da177e4 2840
865c652d 2841 status = RTL_R16(IntrStatus);
1da177e4 2842
865c652d
FR		 2843 /* hotplug/major error/no more work/shared irq */
2844 if ((status == 0xffff) || !status)
2845 goto out;
1da177e4 2846
865c652d 2847 handled = 1;
1da177e4 2848
865c652d
FR		 2849 if (unlikely(!netif_running(dev))) {
2850 rtl8169_asic_down(ioaddr);
2851 goto out;
2852 }
1da177e4 2853
865c652d
FR		 2854 status &= tp->intr_mask;
2855 RTL_W16(IntrStatus,
2856 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 2857
865c652d
FR		 2858 if (!(status & tp->intr_event))
2859 goto out;
0e485150 2860
865c652d
FR		 2861 /* Work around for rx fifo overflow */
2862 if (unlikely(status & RxFIFOOver) &&
2863 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2864 netif_stop_queue(dev);
2865 rtl8169_tx_timeout(dev);
2866 goto out;
2867 }
1da177e4 2868
865c652d
FR		 2869 if (unlikely(status & SYSErr)) {
2870 rtl8169_pcierr_interrupt(dev);
2871 goto out;
2872 }
1da177e4 2873
865c652d
FR		 2874 if (status & LinkChg)
2875 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 2876
865c652d
FR		 2877 if (status & tp->napi_event) {
2878 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2879 tp->intr_mask = ~tp->napi_event;
313b0305 2880
bea3348e
SH		 2881 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2882 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 2883 else if (netif_msg_intr(tp)) {
2884 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2885 dev->name, status);
b57b7e5a 2886 }
1da177e4
LT		 2887 }
2888out:
2889 return IRQ_RETVAL(handled);
2890}
2891
bea3348e 2892static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2893{
bea3348e
SH		 2894 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2895 struct net_device *dev = tp->dev;
1da177e4 2896 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2897 int work_done;
1da177e4 2898
bea3348e 2899 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2900 rtl8169_tx_interrupt(dev, tp, ioaddr);
2901
bea3348e
SH		 2902 if (work_done < budget) {
2903 netif_rx_complete(dev, napi);
1da177e4
LT		 2904 tp->intr_mask = 0xffff;
2905 /*
2906 * 20040426: the barrier is not strictly required but the
2907 * behavior of the irq handler could be less predictable
2908 * without it. Btw, the lack of flush for the posted pci
2909 * write is safe - FR
2910 */
2911 smp_wmb();
0e485150 2912 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2913 }
2914
bea3348e 2915 return work_done;
1da177e4 2916}
1da177e4
LT		 2917
2918static void rtl8169_down(struct net_device *dev)
2919{
2920 struct rtl8169_private *tp = netdev_priv(dev);
2921 void __iomem *ioaddr = tp->mmio_addr;
733b736c 2922 unsigned int intrmask;
1da177e4
LT		 2923
2924 rtl8169_delete_timer(dev);
2925
2926 netif_stop_queue(dev);
2927
93dd79e8 2928 napi_disable(&tp->napi);
93dd79e8 2929
1da177e4
LT		 2930core_down:
2931 spin_lock_irq(&tp->lock);
2932
2933 rtl8169_asic_down(ioaddr);
2934
2935 /* Update the error counts. */
cebf8cc7 2936 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2937 RTL_W32(RxMissed, 0);
2938
2939 spin_unlock_irq(&tp->lock);
2940
2941 synchronize_irq(dev->irq);
2942
1da177e4 2943 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2944 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2945
2946 /*
2947 * And now for the 50k$ question: are IRQ disabled or not ?
2948 *
2949 * Two paths lead here:
2950 * 1) dev->close
2951 * -> netif_running() is available to sync the current code and the
2952 * IRQ handler. See rtl8169_interrupt for details.
2953 * 2) dev->change_mtu
2954 * -> rtl8169_poll can not be issued again and re-enable the
2955 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2956 *
2957 * No loop if hotpluged or major error (0xffff).
1da177e4 2958 */
733b736c
AP		 2959 intrmask = RTL_R16(IntrMask);
2960 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2961 goto core_down;
2962
2963 rtl8169_tx_clear(tp);
2964
2965 rtl8169_rx_clear(tp);
2966}
2967
2968static int rtl8169_close(struct net_device *dev)
2969{
2970 struct rtl8169_private *tp = netdev_priv(dev);
2971 struct pci_dev *pdev = tp->pci_dev;
2972
2973 rtl8169_down(dev);
2974
2975 free_irq(dev->irq, dev);
2976
1da177e4
LT		 2977 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2978 tp->RxPhyAddr);
2979 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2980 tp->TxPhyAddr);
2981 tp->TxDescArray = NULL;
2982 tp->RxDescArray = NULL;
2983
2984 return 0;
2985}
2986
07ce4064 2987static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2988{
2989 struct rtl8169_private *tp = netdev_priv(dev);
2990 void __iomem *ioaddr = tp->mmio_addr;
2991 unsigned long flags;
2992 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2993 int rx_mode;
1da177e4
LT		 2994 u32 tmp = 0;
2995
2996 if (dev->flags & IFF_PROMISC) {
2997 /* Unconditionally log net taps. */
b57b7e5a
SH		 2998 if (netif_msg_link(tp)) {
2999 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3000 dev->name);
3001 }
1da177e4
LT		 3002 rx_mode =
3003 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3004 AcceptAllPhys;
3005 mc_filter[1] = mc_filter[0] = 0xffffffff;
3006 } else if ((dev->mc_count > multicast_filter_limit)
3007 || (dev->flags & IFF_ALLMULTI)) {
3008 /* Too many to filter perfectly -- accept all multicasts. */
3009 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3010 mc_filter[1] = mc_filter[0] = 0xffffffff;
3011 } else {
3012 struct dev_mc_list *mclist;
07d3f51f
FR		 3013 unsigned int i;
3014
1da177e4
LT		 3015 rx_mode = AcceptBroadcast | AcceptMyPhys;
3016 mc_filter[1] = mc_filter[0] = 0;
3017 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3018 i++, mclist = mclist->next) {
3019 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3020 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3021 rx_mode |= AcceptMulticast;
3022 }
3023 }
3024
3025 spin_lock_irqsave(&tp->lock, flags);
3026
3027 tmp = rtl8169_rx_config | rx_mode |
3028 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3029
f887cce8 3030 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3031 u32 data = mc_filter[0];
3032
3033 mc_filter[0] = swab32(mc_filter[1]);
3034 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3035 }
3036
1da177e4
LT		 3037 RTL_W32(MAR0 + 0, mc_filter[0]);
3038 RTL_W32(MAR0 + 4, mc_filter[1]);
3039
57a9f236
FR		 3040 RTL_W32(RxConfig, tmp);
3041
1da177e4
LT		 3042 spin_unlock_irqrestore(&tp->lock, flags);
3043}
3044
3045/**
3046 * rtl8169_get_stats - Get rtl8169 read/write statistics
3047 * @dev: The Ethernet Device to get statistics for
3048 *
3049 * Get TX/RX statistics for rtl8169
3050 */
3051static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3052{
3053 struct rtl8169_private *tp = netdev_priv(dev);
3054 void __iomem *ioaddr = tp->mmio_addr;
3055 unsigned long flags;
3056
3057 if (netif_running(dev)) {
3058 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3059 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3060 RTL_W32(RxMissed, 0);
3061 spin_unlock_irqrestore(&tp->lock, flags);
3062 }
5b0384f4 3063
cebf8cc7 3064 return &dev->stats;
1da177e4
LT		 3065}
3066
5d06a99f
FR		 3067#ifdef CONFIG_PM
3068
3069static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3070{
3071 struct net_device *dev = pci_get_drvdata(pdev);
3072 struct rtl8169_private *tp = netdev_priv(dev);
3073 void __iomem *ioaddr = tp->mmio_addr;
3074
3075 if (!netif_running(dev))
1371fa6d 3076 goto out_pci_suspend;
5d06a99f
FR		 3077
3078 netif_device_detach(dev);
3079 netif_stop_queue(dev);
3080
3081 spin_lock_irq(&tp->lock);
3082
3083 rtl8169_asic_down(ioaddr);
3084
cebf8cc7 3085 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3086 RTL_W32(RxMissed, 0);
3087
3088 spin_unlock_irq(&tp->lock);
3089
1371fa6d 3090out_pci_suspend:
5d06a99f 3091 pci_save_state(pdev);
f23e7fda
FR		 3092 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3093 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3094 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3095
5d06a99f
FR		 3096 return 0;
3097}
3098
3099static int rtl8169_resume(struct pci_dev *pdev)
3100{
3101 struct net_device *dev = pci_get_drvdata(pdev);
3102
1371fa6d
FR		 3103 pci_set_power_state(pdev, PCI_D0);
3104 pci_restore_state(pdev);
3105 pci_enable_wake(pdev, PCI_D0, 0);
3106
5d06a99f
FR		 3107 if (!netif_running(dev))
3108 goto out;
3109
3110 netif_device_attach(dev);
3111
5d06a99f
FR		 3112 rtl8169_schedule_work(dev, rtl8169_reset_task);
3113out:
3114 return 0;
3115}
3116
3117#endif /* CONFIG_PM */
3118
1da177e4
LT		 3119static struct pci_driver rtl8169_pci_driver = {
3120 .name = MODULENAME,
3121 .id_table = rtl8169_pci_tbl,
3122 .probe = rtl8169_init_one,
3123 .remove = __devexit_p(rtl8169_remove_one),
3124#ifdef CONFIG_PM
3125 .suspend = rtl8169_suspend,
3126 .resume = rtl8169_resume,
3127#endif
3128};
3129
07d3f51f 3130static int __init rtl8169_init_module(void)
1da177e4 3131{
29917620 3132 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3133}
3134
07d3f51f 3135static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3136{
3137 pci_unregister_driver(&rtl8169_pci_driver);
3138}
3139
3140module_init(rtl8169_init_module);
3141module_exit(rtl8169_cleanup_module);
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