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[netdrvr] forcedeth: add MCP77 device IDs
[net-next-2.6.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
0b50f81d 62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
0b50f81d 66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 67#define rtl8169_rx_quota(count, quota) count
68#endif
69
1da177e4 70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 71static const int max_interrupt_work = 20;
1da177e4
LT		 72
73/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 75static const int multicast_filter_limit = 32;
1da177e4
LT		 76
77/* MAC address length */
78#define MAC_ADDR_LEN 6
79
80#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 83#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 84#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87
88#define R8169_REGS_SIZE 256
89#define R8169_NAPI_WEIGHT 64
90#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
105#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
106
107enum mac_version {
ba6eb6ee
FR		 108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 124};
125
1da177e4
LT		 126#define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128
3c6bee1d 129static const struct {
1da177e4
LT		 130 const char *name;
131 u8 mac_version;
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133} rtl_chip_info[] = {
ba6eb6ee
FR		 134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 150};
151#undef _R
152
bcf0bf90
FR		 153enum cfg_version {
154 RTL_CFG_0 = 0x00,
155 RTL_CFG_1,
156 RTL_CFG_2
157};
158
07ce4064
FR		 159static void rtl_hw_start_8169(struct net_device *);
160static void rtl_hw_start_8168(struct net_device *);
161static void rtl_hw_start_8101(struct net_device *);
162
1da177e4 163static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 174 {0,},
175};
176
177MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179static int rx_copybreak = 200;
180static int use_dac;
b57b7e5a
SH		 181static struct {
182 u32 msg_enable;
183} debug = { -1 };
1da177e4 184
07d3f51f
FR		 185enum rtl_registers {
186 MAC0 = 0, /* Ethernet hardware address. */
773d2021 187 MAC4 = 4,
07d3f51f
FR		 188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3c,
200 IntrStatus = 0x3e,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4c,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5c,
212 PHYAR = 0x60,
213 TBICSR = 0x64,
214 TBI_ANAR = 0x68,
215 TBI_LPAR = 0x6a,
216 PHYstatus = 0x6c,
217 RxMaxSize = 0xda,
218 CPlusCmd = 0xe0,
219 IntrMitigate = 0xe2,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
222 EarlyTxThres = 0xec,
223 FuncEvent = 0xf0,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
1da177e4
LT		 227};
228
07d3f51f 229enum rtl_register_content {
1da177e4 230 /* InterruptStatusBits */
07d3f51f
FR		 231 SYSErr = 0x8000,
232 PCSTimeout = 0x4000,
233 SWInt = 0x0100,
234 TxDescUnavail = 0x0080,
235 RxFIFOOver = 0x0040,
236 LinkChg = 0x0020,
237 RxOverflow = 0x0010,
238 TxErr = 0x0008,
239 TxOK = 0x0004,
240 RxErr = 0x0002,
241 RxOK = 0x0001,
1da177e4
LT		 242
243 /* RxStatusDesc */
9dccf611
FR		 244 RxFOVF = (1 << 23),
245 RxRWT = (1 << 22),
246 RxRES = (1 << 21),
247 RxRUNT = (1 << 20),
248 RxCRC = (1 << 19),
1da177e4
LT		 249
250 /* ChipCmdBits */
07d3f51f
FR		 251 CmdReset = 0x10,
252 CmdRxEnb = 0x08,
253 CmdTxEnb = 0x04,
254 RxBufEmpty = 0x01,
1da177e4 255
275391a4
FR		 256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
260
1da177e4 261 /* Cfg9346Bits */
07d3f51f
FR		 262 Cfg9346_Lock = 0x00,
263 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 264
265 /* rx_mode_bits */
07d3f51f
FR		 266 AcceptErr = 0x20,
267 AcceptRunt = 0x10,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
270 AcceptMyPhys = 0x02,
271 AcceptAllPhys = 0x01,
1da177e4
LT		 272
273 /* RxConfigBits */
07d3f51f
FR		 274 RxCfgFIFOShift = 13,
275 RxCfgDMAShift = 8,
1da177e4
LT		 276
277 /* TxConfigBits */
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280
5d06a99f 281 /* Config1 register p.24 */
fbac58fc 282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 283 PMEnable = (1 << 0), /* Power Management Enable */
284
6dccd16b
FR		 285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
288
61a4dcc2
FR		 289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
292
5d06a99f 293 /* Config5 register p.27 */
61a4dcc2
FR		 294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299
1da177e4
LT		 300 /* TBICSR p.28 */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
307
308 /* CPlusCmd p.31 */
0e485150 309 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 310 RxVlan = (1 << 6),
311 RxChkSum = (1 << 5),
312 PCIDAC = (1 << 4),
313 PCIMulRW = (1 << 3),
0e485150
FR		 314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
1da177e4
LT		 318
319 /* rtl8169_PHYstatus */
07d3f51f
FR		 320 TBI_Enable = 0x80,
321 TxFlowCtrl = 0x40,
322 RxFlowCtrl = 0x20,
323 _1000bpsF = 0x10,
324 _100bps = 0x08,
325 _10bps = 0x04,
326 LinkStatus = 0x02,
327 FullDup = 0x01,
1da177e4 328
1da177e4 329 /* _TBICSRBit */
07d3f51f 330 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 331
332 /* DumpCounterCommand */
07d3f51f 333 CounterDump = 0x8,
1da177e4
LT		 334};
335
07d3f51f 336enum desc_status_bit {
1da177e4
LT		 337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
341
342 /* Tx private */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
350
351 /* Rx private */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
354
355#define RxProtoUDP (PID1)
356#define RxProtoTCP (PID0)
357#define RxProtoIP (PID1 | PID0)
358#define RxProtoMask RxProtoIP
359
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
364};
365
366#define RsvdMask 0x3fffc000
367
368struct TxDesc {
6cccd6e7
REB		 369 __le32 opts1;
370 __le32 opts2;
371 __le64 addr;
1da177e4
LT		 372};
373
374struct RxDesc {
6cccd6e7
REB		 375 __le32 opts1;
376 __le32 opts2;
377 __le64 addr;
1da177e4
LT		 378};
379
380struct ring_info {
381 struct sk_buff *skb;
382 u32 len;
383 u8 __pad[sizeof(void *) - sizeof(u32)];
384};
385
f23e7fda
FR		 386enum features {
387 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 388 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 389};
390
1da177e4
LT		 391struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 394 struct net_device *dev;
bea3348e 395 struct napi_struct napi;
1da177e4 396 spinlock_t lock; /* spin lock flag */
b57b7e5a 397 u32 msg_enable;
1da177e4
LT		 398 int chipset;
399 int mac_version;
1da177e4
LT		 400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
402 u32 dirty_rx;
403 u32 dirty_tx;
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 410 unsigned align;
1da177e4
LT		 411 unsigned rx_buf_sz;
412 struct timer_list timer;
413 u16 cp_cmd;
0e485150
FR		 414 u16 intr_event;
415 u16 napi_event;
1da177e4
LT		 416 u16 intr_mask;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419#ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
421#endif
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
07ce4064 425 void (*hw_start)(struct net_device *);
1da177e4
LT		 426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
c4028958 428 struct delayed_work task;
f23e7fda 429 unsigned features;
1da177e4
LT		 430};
431
979b6c13 432MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 433MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 434module_param(rx_copybreak, int, 0);
1b7efd58 435MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 436module_param(use_dac, int, 0);
437MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 438module_param_named(debug, debug.msg_enable, int, 0);
439MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 440MODULE_LICENSE("GPL");
441MODULE_VERSION(RTL8169_VERSION);
442
443static int rtl8169_open(struct net_device *dev);
444static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 445static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 446static int rtl8169_init_ring(struct net_device *dev);
07ce4064 447static void rtl_hw_start(struct net_device *dev);
1da177e4 448static int rtl8169_close(struct net_device *dev);
07ce4064 449static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 450static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 451static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 452static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 453 void __iomem *, u32 budget);
4dcb7d33 454static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 455static void rtl8169_down(struct net_device *dev);
99f252b0 456static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 457
458#ifdef CONFIG_R8169_NAPI
bea3348e 459static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 460#endif
461
1da177e4 462static const unsigned int rtl8169_rx_config =
5b0384f4 463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 464
07d3f51f 465static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 466{
467 int i;
468
07d3f51f 469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 470
2371408c 471 for (i = 20; i > 0; i--) {
07d3f51f
FR		 472 /*
473 * Check if the RTL8169 has completed writing to the specified
474 * MII register.
475 */
5b0384f4 476 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 477 break;
2371408c 478 udelay(25);
1da177e4
LT		 479 }
480}
481
07d3f51f 482static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 483{
484 int i, value = -1;
485
07d3f51f 486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 487
2371408c 488 for (i = 20; i > 0; i--) {
07d3f51f
FR		 489 /*
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
492 */
1da177e4
LT		 493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
495 break;
496 }
2371408c 497 udelay(25);
1da177e4
LT		 498 }
499 return value;
500}
501
502static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
503{
504 RTL_W16(IntrMask, 0x0000);
505
506 RTL_W16(IntrStatus, 0xffff);
507}
508
509static void rtl8169_asic_down(void __iomem *ioaddr)
510{
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
513 RTL_R16(CPlusCmd);
514}
515
516static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
517{
518 return RTL_R32(TBICSR) & TBIReset;
519}
520
521static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
522{
64e4bfb4 523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 524}
525
526static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
527{
528 return RTL_R32(TBICSR) & TBILinkOk;
529}
530
531static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
532{
533 return RTL_R8(PHYstatus) & LinkStatus;
534}
535
536static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
537{
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
539}
540
541static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
542{
543 unsigned int val;
544
9e0db8ef
FR		 545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 547}
548
549static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
1da177e4
LT		 552{
553 unsigned long flags;
554
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
b57b7e5a
SH		 558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
560 } else {
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 563 netif_carrier_off(dev);
b57b7e5a 564 }
1da177e4
LT		 565 spin_unlock_irqrestore(&tp->lock, flags);
566}
567
61a4dcc2
FR		 568static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
569{
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
572 u8 options;
573
574 wol->wolopts = 0;
575
576#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
578
579 spin_lock_irq(&tp->lock);
580
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
583 goto out_unlock;
584
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
590
591 options = RTL_R8(Config5);
592 if (options & UWF)
593 wol->wolopts |= WAKE_UCAST;
594 if (options & BWF)
5b0384f4 595 wol->wolopts |= WAKE_BCAST;
61a4dcc2 596 if (options & MWF)
5b0384f4 597 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 598
599out_unlock:
600 spin_unlock_irq(&tp->lock);
601}
602
603static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
604{
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 607 unsigned int i;
61a4dcc2
FR		 608 static struct {
609 u32 opt;
610 u16 reg;
611 u8 mask;
612 } cfg[] = {
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
620 };
621
622 spin_lock_irq(&tp->lock);
623
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
625
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
631 }
632
633 RTL_W8(Cfg9346, Cfg9346_Lock);
634
f23e7fda
FR		 635 if (wol->wolopts)
636 tp->features |= RTL_FEATURE_WOL;
637 else
638 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 639
640 spin_unlock_irq(&tp->lock);
641
642 return 0;
643}
644
1da177e4
LT		 645static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
647{
648 struct rtl8169_private *tp = netdev_priv(dev);
649
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
653}
654
655static int rtl8169_get_regs_len(struct net_device *dev)
656{
657 return R8169_REGS_SIZE;
658}
659
660static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
662{
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
665 int ret = 0;
666 u32 reg;
667
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
674 else {
b57b7e5a
SH		 675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
678 dev->name);
679 }
1da177e4
LT		 680 ret = -EOPNOTSUPP;
681 }
682
683 return ret;
684}
685
686static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
688{
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
692
64e4bfb4
FR		 693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 698
699 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 703 } else {
704 if (speed == SPEED_10)
64e4bfb4 705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 706 else if (speed == SPEED_100)
64e4bfb4 707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 708 else if (speed == SPEED_1000)
64e4bfb4 709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 710
711 if (duplex == DUPLEX_HALF)
64e4bfb4 712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 713
714 if (duplex == DUPLEX_FULL)
64e4bfb4 715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 716
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 719 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
720 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 722 }
723 }
724
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 728 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 730 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 731 netif_msg_link(tp)) {
732 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
733 dev->name);
734 }
64e4bfb4 735 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 736 }
737
623a1593
FR		 738 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
739
e3cf0cc0
FR		 740 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
741 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 742 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
743 mdio_write(ioaddr, 0x1f, 0x0000);
744 mdio_write(ioaddr, 0x0e, 0x0000);
745 }
746
1da177e4
LT		 747 tp->phy_auto_nego_reg = auto_nego;
748 tp->phy_1000_ctrl_reg = giga_ctrl;
749
64e4bfb4
FR		 750 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
751 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
752 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 753 return 0;
754}
755
756static int rtl8169_set_speed(struct net_device *dev,
757 u8 autoneg, u16 speed, u8 duplex)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 int ret;
761
762 ret = tp->set_speed(dev, autoneg, speed, duplex);
763
64e4bfb4 764 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 765 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
766
767 return ret;
768}
769
770static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773 unsigned long flags;
774 int ret;
775
776 spin_lock_irqsave(&tp->lock, flags);
777 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
778 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 779
1da177e4
LT		 780 return ret;
781}
782
783static u32 rtl8169_get_rx_csum(struct net_device *dev)
784{
785 struct rtl8169_private *tp = netdev_priv(dev);
786
787 return tp->cp_cmd & RxChkSum;
788}
789
790static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
791{
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
794 unsigned long flags;
795
796 spin_lock_irqsave(&tp->lock, flags);
797
798 if (data)
799 tp->cp_cmd |= RxChkSum;
800 else
801 tp->cp_cmd &= ~RxChkSum;
802
803 RTL_W16(CPlusCmd, tp->cp_cmd);
804 RTL_R16(CPlusCmd);
805
806 spin_unlock_irqrestore(&tp->lock, flags);
807
808 return 0;
809}
810
811#ifdef CONFIG_R8169_VLAN
812
813static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
814 struct sk_buff *skb)
815{
816 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
817 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
818}
819
820static void rtl8169_vlan_rx_register(struct net_device *dev,
821 struct vlan_group *grp)
822{
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
825 unsigned long flags;
826
827 spin_lock_irqsave(&tp->lock, flags);
828 tp->vlgrp = grp;
829 if (tp->vlgrp)
830 tp->cp_cmd |= RxVlan;
831 else
832 tp->cp_cmd &= ~RxVlan;
833 RTL_W16(CPlusCmd, tp->cp_cmd);
834 RTL_R16(CPlusCmd);
835 spin_unlock_irqrestore(&tp->lock, flags);
836}
837
1da177e4
LT		 838static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
839 struct sk_buff *skb)
840{
841 u32 opts2 = le32_to_cpu(desc->opts2);
842 int ret;
843
844 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 845 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 846 ret = 0;
847 } else
848 ret = -1;
849 desc->opts2 = 0;
850 return ret;
851}
852
853#else /* !CONFIG_R8169_VLAN */
854
855static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
856 struct sk_buff *skb)
857{
858 return 0;
859}
860
861static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
862 struct sk_buff *skb)
863{
864 return -1;
865}
866
867#endif
868
869static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
870{
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
873 u32 status;
874
875 cmd->supported =
876 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
877 cmd->port = PORT_FIBRE;
878 cmd->transceiver = XCVR_INTERNAL;
879
880 status = RTL_R32(TBICSR);
881 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
882 cmd->autoneg = !!(status & TBINwEnable);
883
884 cmd->speed = SPEED_1000;
885 cmd->duplex = DUPLEX_FULL; /* Always set */
886}
887
888static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
889{
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
892 u8 status;
893
894 cmd->supported = SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_1000baseT_Full |
899 SUPPORTED_Autoneg |
5b0384f4 900 SUPPORTED_TP;
1da177e4
LT		 901
902 cmd->autoneg = 1;
903 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
904
64e4bfb4 905 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 906 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 907 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 908 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 909 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 910 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 911 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 912 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 913 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 914 cmd->advertising |= ADVERTISED_1000baseT_Full;
915
916 status = RTL_R8(PHYstatus);
917
918 if (status & _1000bpsF)
919 cmd->speed = SPEED_1000;
920 else if (status & _100bps)
921 cmd->speed = SPEED_100;
922 else if (status & _10bps)
923 cmd->speed = SPEED_10;
924
623a1593
FR		 925 if (status & TxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Asym_Pause;
927 if (status & RxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Pause;
929
1da177e4
LT		 930 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
931 DUPLEX_FULL : DUPLEX_HALF;
932}
933
934static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
935{
936 struct rtl8169_private *tp = netdev_priv(dev);
937 unsigned long flags;
938
939 spin_lock_irqsave(&tp->lock, flags);
940
941 tp->get_settings(dev, cmd);
942
943 spin_unlock_irqrestore(&tp->lock, flags);
944 return 0;
945}
946
947static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
948 void *p)
949{
5b0384f4
FR		 950 struct rtl8169_private *tp = netdev_priv(dev);
951 unsigned long flags;
1da177e4 952
5b0384f4
FR		 953 if (regs->len > R8169_REGS_SIZE)
954 regs->len = R8169_REGS_SIZE;
1da177e4 955
5b0384f4
FR		 956 spin_lock_irqsave(&tp->lock, flags);
957 memcpy_fromio(p, tp->mmio_addr, regs->len);
958 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 959}
960
b57b7e5a
SH		 961static u32 rtl8169_get_msglevel(struct net_device *dev)
962{
963 struct rtl8169_private *tp = netdev_priv(dev);
964
965 return tp->msg_enable;
966}
967
968static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
969{
970 struct rtl8169_private *tp = netdev_priv(dev);
971
972 tp->msg_enable = value;
973}
974
d4a3a0fc
SH		 975static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
976 "tx_packets",
977 "rx_packets",
978 "tx_errors",
979 "rx_errors",
980 "rx_missed",
981 "align_errors",
982 "tx_single_collisions",
983 "tx_multi_collisions",
984 "unicast",
985 "broadcast",
986 "multicast",
987 "tx_aborted",
988 "tx_underrun",
989};
990
991struct rtl8169_counters {
b1eab701
AV		 992 __le64 tx_packets;
993 __le64 rx_packets;
994 __le64 tx_errors;
995 __le32 rx_errors;
996 __le16 rx_missed;
997 __le16 align_errors;
998 __le32 tx_one_collision;
999 __le32 tx_multi_collision;
1000 __le64 rx_unicast;
1001 __le64 rx_broadcast;
1002 __le32 rx_multicast;
1003 __le16 tx_aborted;
1004 __le16 tx_underun;
d4a3a0fc
SH		 1005};
1006
b9f2c044 1007static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1008{
b9f2c044
JG		 1009 switch (sset) {
1010 case ETH_SS_STATS:
1011 return ARRAY_SIZE(rtl8169_gstrings);
1012 default:
1013 return -EOPNOTSUPP;
1014 }
d4a3a0fc
SH		 1015}
1016
1017static void rtl8169_get_ethtool_stats(struct net_device *dev,
1018 struct ethtool_stats *stats, u64 *data)
1019{
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->mmio_addr;
1022 struct rtl8169_counters *counters;
1023 dma_addr_t paddr;
1024 u32 cmd;
1025
1026 ASSERT_RTNL();
1027
1028 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1029 if (!counters)
1030 return;
1031
1032 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1033 cmd = (u64)paddr & DMA_32BIT_MASK;
1034 RTL_W32(CounterAddrLow, cmd);
1035 RTL_W32(CounterAddrLow, cmd | CounterDump);
1036
1037 while (RTL_R32(CounterAddrLow) & CounterDump) {
1038 if (msleep_interruptible(1))
1039 break;
1040 }
1041
1042 RTL_W32(CounterAddrLow, 0);
1043 RTL_W32(CounterAddrHigh, 0);
1044
5b0384f4 1045 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1046 data[1] = le64_to_cpu(counters->rx_packets);
1047 data[2] = le64_to_cpu(counters->tx_errors);
1048 data[3] = le32_to_cpu(counters->rx_errors);
1049 data[4] = le16_to_cpu(counters->rx_missed);
1050 data[5] = le16_to_cpu(counters->align_errors);
1051 data[6] = le32_to_cpu(counters->tx_one_collision);
1052 data[7] = le32_to_cpu(counters->tx_multi_collision);
1053 data[8] = le64_to_cpu(counters->rx_unicast);
1054 data[9] = le64_to_cpu(counters->rx_broadcast);
1055 data[10] = le32_to_cpu(counters->rx_multicast);
1056 data[11] = le16_to_cpu(counters->tx_aborted);
1057 data[12] = le16_to_cpu(counters->tx_underun);
1058
1059 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1060}
1061
1062static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1063{
1064 switch(stringset) {
1065 case ETH_SS_STATS:
1066 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1067 break;
1068 }
1069}
1070
7282d491 1071static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1072 .get_drvinfo = rtl8169_get_drvinfo,
1073 .get_regs_len = rtl8169_get_regs_len,
1074 .get_link = ethtool_op_get_link,
1075 .get_settings = rtl8169_get_settings,
1076 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1077 .get_msglevel = rtl8169_get_msglevel,
1078 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1079 .get_rx_csum = rtl8169_get_rx_csum,
1080 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1081 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1082 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1083 .set_tso = ethtool_op_set_tso,
1084 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1085 .get_wol = rtl8169_get_wol,
1086 .set_wol = rtl8169_set_wol,
d4a3a0fc 1087 .get_strings = rtl8169_get_strings,
b9f2c044 1088 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1089 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1090};
1091
07d3f51f
FR		 1092static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1093 int bitnum, int bitval)
1da177e4
LT		 1094{
1095 int val;
1096
1097 val = mdio_read(ioaddr, reg);
1098 val = (bitval == 1) ?
1099 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1100 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1101}
1102
07d3f51f
FR		 1103static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1104 void __iomem *ioaddr)
1da177e4 1105{
0e485150
FR		 1106 /*
1107 * The driver currently handles the 8168Bf and the 8168Be identically
1108 * but they can be identified more specifically through the test below
1109 * if needed:
1110 *
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1112 *
1113 * Same thing for the 8101Eb and the 8101Ec:
1114 *
1115 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1116 */
1da177e4
LT		 1117 const struct {
1118 u32 mask;
e3cf0cc0 1119 u32 val;
1da177e4
LT		 1120 int mac_version;
1121 } mac_info[] = {
e3cf0cc0
FR		 1122 /* 8168B family. */
1123 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1124 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1125 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1127
1128 /* 8168B family. */
1129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1130 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1131 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1132 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1133
1134 /* 8101 family. */
1135 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1136 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1138 /* FIXME: where did these entries come from ? -- FR */
1139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1141
1142 /* 8110 family. */
1143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1149
1150 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1151 }, *p = mac_info;
1152 u32 reg;
1153
e3cf0cc0
FR		 1154 reg = RTL_R32(TxConfig);
1155 while ((reg & p->mask) != p->val)
1da177e4
LT		 1156 p++;
1157 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1158
1159 if (p->mask == 0x00000000) {
1160 struct pci_dev *pdev = tp->pci_dev;
1161
1162 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1163 }
1da177e4
LT		 1164}
1165
1166static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1167{
bcf0bf90 1168 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1169}
1170
867763c1
FR		 1171struct phy_reg {
1172 u16 reg;
1173 u16 val;
1174};
1175
1176static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1177{
1178 while (len-- > 0) {
1179 mdio_write(ioaddr, regs->reg, regs->val);
1180 regs++;
1181 }
1182}
1183
5615d9f1 1184static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1185{
1da177e4
LT		 1186 struct {
1187 u16 regs[5]; /* Beware of bit-sign propagation */
1188 } phy_magic[5] = { {
1189 { 0x0000, //w 4 15 12 0
1190 0x00a1, //w 3 15 0 00a1
1191 0x0008, //w 2 15 0 0008
1192 0x1020, //w 1 15 0 1020
1193 0x1000 } },{ //w 0 15 0 1000
1194 { 0x7000, //w 4 15 12 7
1195 0xff41, //w 3 15 0 ff41
1196 0xde60, //w 2 15 0 de60
1197 0x0140, //w 1 15 0 0140
1198 0x0077 } },{ //w 0 15 0 0077
1199 { 0xa000, //w 4 15 12 a
1200 0xdf01, //w 3 15 0 df01
1201 0xdf20, //w 2 15 0 df20
1202 0xff95, //w 1 15 0 ff95
1203 0xfa00 } },{ //w 0 15 0 fa00
1204 { 0xb000, //w 4 15 12 b
1205 0xff41, //w 3 15 0 ff41
1206 0xde20, //w 2 15 0 de20
1207 0x0140, //w 1 15 0 0140
1208 0x00bb } },{ //w 0 15 0 00bb
1209 { 0xf000, //w 4 15 12 f
1210 0xdf01, //w 3 15 0 df01
1211 0xdf20, //w 2 15 0 df20
1212 0xff95, //w 1 15 0 ff95
1213 0xbf00 } //w 0 15 0 bf00
1214 }
1215 }, *p = phy_magic;
07d3f51f 1216 unsigned int i;
1da177e4 1217
a441d7b6
FR		 1218 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1219 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1220 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1221 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1222
1223 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1224 int val, pos = 4;
1225
1226 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1227 mdio_write(ioaddr, pos, val);
1228 while (--pos >= 0)
1229 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1230 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1231 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1232 }
a441d7b6 1233 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1234}
1235
5615d9f1
FR		 1236static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1237{
a441d7b6
FR		 1238 struct phy_reg phy_reg_init[] = {
1239 { 0x1f, 0x0002 },
1240 { 0x01, 0x90d0 },
1241 { 0x1f, 0x0000 }
1242 };
1243
1244 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1 1245}
7da97ec9
FR		 1246static void rtl8168b_hw_phy_config(void __iomem *ioaddr)
1247{
1248 struct phy_reg phy_reg_init[] = {
1249 { 0x1f, 0x0000 },
1250 { 0x10, 0xf41b },
1251 { 0x1f, 0x0000 }
1252 };
1253
1254 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1255}
5615d9f1 1256
867763c1
FR		 1257static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1258{
1259 struct phy_reg phy_reg_init[] = {
1260 { 0x1f, 0x0000 },
1261 { 0x1d, 0x0f00 },
1262 { 0x1f, 0x0002 },
1263 { 0x0c, 0x1ec8 },
1264 { 0x1f, 0x0000 }
1265 };
1266
1267 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1268}
1269
1270static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1271{
1272 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1273 { 0x1f, 0x0001 },
1274 { 0x12, 0x2300 },
867763c1
FR		 1275 { 0x1f, 0x0002 },
1276 { 0x00, 0x88d4 },
1277 { 0x01, 0x82b1 },
1278 { 0x03, 0x7002 },
1279 { 0x08, 0x9e30 },
1280 { 0x09, 0x01f0 },
1281 { 0x0a, 0x5500 },
1282 { 0x0c, 0x00c8 },
1283 { 0x1f, 0x0003 },
1284 { 0x12, 0xc096 },
1285 { 0x16, 0x000a },
1286 { 0x1f, 0x0000 }
1287 };
1288
1289 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1290}
1291
7da97ec9
FR		 1292static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1293{
1294 struct phy_reg phy_reg_init[] = {
1295 { 0x1f, 0x0000 },
1296 { 0x12, 0x2300 },
1297 { 0x1f, 0x0003 },
1298 { 0x16, 0x0f0a },
1299 { 0x1f, 0x0000 },
1300 { 0x1f, 0x0002 },
1301 { 0x0c, 0x7eb8 },
1302 { 0x1f, 0x0000 }
1303 };
1304
1305 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1306}
1307
5615d9f1
FR		 1308static void rtl_hw_phy_config(struct net_device *dev)
1309{
1310 struct rtl8169_private *tp = netdev_priv(dev);
1311 void __iomem *ioaddr = tp->mmio_addr;
1312
1313 rtl8169_print_mac_version(tp);
1314
1315 switch (tp->mac_version) {
1316 case RTL_GIGA_MAC_VER_01:
1317 break;
1318 case RTL_GIGA_MAC_VER_02:
1319 case RTL_GIGA_MAC_VER_03:
1320 rtl8169s_hw_phy_config(ioaddr);
1321 break;
1322 case RTL_GIGA_MAC_VER_04:
1323 rtl8169sb_hw_phy_config(ioaddr);
1324 break;
7da97ec9
FR		 1325 case RTL_GIGA_MAC_VER_11:
1326 case RTL_GIGA_MAC_VER_12:
1327 case RTL_GIGA_MAC_VER_17:
1328 rtl8168b_hw_phy_config(ioaddr);
1329 break;
867763c1
FR		 1330 case RTL_GIGA_MAC_VER_18:
1331 rtl8168cp_hw_phy_config(ioaddr);
1332 break;
1333 case RTL_GIGA_MAC_VER_19:
1334 rtl8168c_hw_phy_config(ioaddr);
1335 break;
7da97ec9
FR		 1336 case RTL_GIGA_MAC_VER_20:
1337 rtl8168cx_hw_phy_config(ioaddr);
1338 break;
5615d9f1
FR		 1339 default:
1340 break;
1341 }
1342}
1343
1da177e4
LT		 1344static void rtl8169_phy_timer(unsigned long __opaque)
1345{
1346 struct net_device *dev = (struct net_device *)__opaque;
1347 struct rtl8169_private *tp = netdev_priv(dev);
1348 struct timer_list *timer = &tp->timer;
1349 void __iomem *ioaddr = tp->mmio_addr;
1350 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1351
bcf0bf90 1352 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1353
64e4bfb4 1354 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1355 return;
1356
1357 spin_lock_irq(&tp->lock);
1358
1359 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1360 /*
1da177e4
LT		 1361 * A busy loop could burn quite a few cycles on nowadays CPU.
1362 * Let's delay the execution of the timer for a few ticks.
1363 */
1364 timeout = HZ/10;
1365 goto out_mod_timer;
1366 }
1367
1368 if (tp->link_ok(ioaddr))
1369 goto out_unlock;
1370
b57b7e5a
SH		 1371 if (netif_msg_link(tp))
1372 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1373
1374 tp->phy_reset_enable(ioaddr);
1375
1376out_mod_timer:
1377 mod_timer(timer, jiffies + timeout);
1378out_unlock:
1379 spin_unlock_irq(&tp->lock);
1380}
1381
1382static inline void rtl8169_delete_timer(struct net_device *dev)
1383{
1384 struct rtl8169_private *tp = netdev_priv(dev);
1385 struct timer_list *timer = &tp->timer;
1386
e179bb7b 1387 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1388 return;
1389
1390 del_timer_sync(timer);
1391}
1392
1393static inline void rtl8169_request_timer(struct net_device *dev)
1394{
1395 struct rtl8169_private *tp = netdev_priv(dev);
1396 struct timer_list *timer = &tp->timer;
1397
e179bb7b 1398 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1399 return;
1400
2efa53f3 1401 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1402}
1403
1404#ifdef CONFIG_NET_POLL_CONTROLLER
1405/*
1406 * Polling 'interrupt' - used by things like netconsole to send skbs
1407 * without having to re-enable interrupts. It's not called while
1408 * the interrupt routine is executing.
1409 */
1410static void rtl8169_netpoll(struct net_device *dev)
1411{
1412 struct rtl8169_private *tp = netdev_priv(dev);
1413 struct pci_dev *pdev = tp->pci_dev;
1414
1415 disable_irq(pdev->irq);
7d12e780 1416 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1417 enable_irq(pdev->irq);
1418}
1419#endif
1420
1421static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1422 void __iomem *ioaddr)
1423{
1424 iounmap(ioaddr);
1425 pci_release_regions(pdev);
1426 pci_disable_device(pdev);
1427 free_netdev(dev);
1428}
1429
bf793295
FR		 1430static void rtl8169_phy_reset(struct net_device *dev,
1431 struct rtl8169_private *tp)
1432{
1433 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1434 unsigned int i;
bf793295
FR		 1435
1436 tp->phy_reset_enable(ioaddr);
1437 for (i = 0; i < 100; i++) {
1438 if (!tp->phy_reset_pending(ioaddr))
1439 return;
1440 msleep(1);
1441 }
1442 if (netif_msg_link(tp))
1443 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1444}
1445
4ff96fa6
FR		 1446static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1447{
1448 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1449
5615d9f1 1450 rtl_hw_phy_config(dev);
4ff96fa6
FR		 1451
1452 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1453 RTL_W8(0x82, 0x01);
1454
6dccd16b
FR		 1455 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1456
1457 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1458 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1459
bcf0bf90 1460 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1461 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1462 RTL_W8(0x82, 0x01);
1463 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1464 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1465 }
1466
bf793295
FR		 1467 rtl8169_phy_reset(dev, tp);
1468
901dda2b
FR		 1469 /*
1470 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1471 * only 8101. Don't panic.
1472 */
1473 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1474
1475 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1476 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1477}
1478
773d2021
FR		 1479static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1480{
1481 void __iomem *ioaddr = tp->mmio_addr;
1482 u32 high;
1483 u32 low;
1484
1485 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1486 high = addr[4] | (addr[5] << 8);
1487
1488 spin_lock_irq(&tp->lock);
1489
1490 RTL_W8(Cfg9346, Cfg9346_Unlock);
1491 RTL_W32(MAC0, low);
1492 RTL_W32(MAC4, high);
1493 RTL_W8(Cfg9346, Cfg9346_Lock);
1494
1495 spin_unlock_irq(&tp->lock);
1496}
1497
1498static int rtl_set_mac_address(struct net_device *dev, void *p)
1499{
1500 struct rtl8169_private *tp = netdev_priv(dev);
1501 struct sockaddr *addr = p;
1502
1503 if (!is_valid_ether_addr(addr->sa_data))
1504 return -EADDRNOTAVAIL;
1505
1506 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1507
1508 rtl_rar_set(tp, dev->dev_addr);
1509
1510 return 0;
1511}
1512
5f787a1a
FR		 1513static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1514{
1515 struct rtl8169_private *tp = netdev_priv(dev);
1516 struct mii_ioctl_data *data = if_mii(ifr);
1517
1518 if (!netif_running(dev))
1519 return -ENODEV;
1520
1521 switch (cmd) {
1522 case SIOCGMIIPHY:
1523 data->phy_id = 32; /* Internal PHY */
1524 return 0;
1525
1526 case SIOCGMIIREG:
1527 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1528 return 0;
1529
1530 case SIOCSMIIREG:
1531 if (!capable(CAP_NET_ADMIN))
1532 return -EPERM;
1533 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1534 return 0;
1535 }
1536 return -EOPNOTSUPP;
1537}
1538
0e485150
FR		 1539static const struct rtl_cfg_info {
1540 void (*hw_start)(struct net_device *);
1541 unsigned int region;
1542 unsigned int align;
1543 u16 intr_event;
1544 u16 napi_event;
fbac58fc 1545 unsigned msi;
0e485150
FR		 1546} rtl_cfg_infos [] = {
1547 [RTL_CFG_0] = {
1548 .hw_start = rtl_hw_start_8169,
1549 .region = 1,
e9f63f30 1550 .align = 0,
0e485150
FR		 1551 .intr_event = SYSErr | LinkChg | RxOverflow |
1552 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1553 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1554 .msi = 0
0e485150
FR		 1555 },
1556 [RTL_CFG_1] = {
1557 .hw_start = rtl_hw_start_8168,
1558 .region = 2,
1559 .align = 8,
1560 .intr_event = SYSErr | LinkChg | RxOverflow |
1561 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1562 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1563 .msi = RTL_FEATURE_MSI
0e485150
FR		 1564 },
1565 [RTL_CFG_2] = {
1566 .hw_start = rtl_hw_start_8101,
1567 .region = 2,
1568 .align = 8,
1569 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1570 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1571 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1572 .msi = RTL_FEATURE_MSI
0e485150
FR		 1573 }
1574};
1575
fbac58fc
FR		 1576/* Cfg9346_Unlock assumed. */
1577static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1578 const struct rtl_cfg_info *cfg)
1579{
1580 unsigned msi = 0;
1581 u8 cfg2;
1582
1583 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1584 if (cfg->msi) {
1585 if (pci_enable_msi(pdev)) {
1586 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1587 } else {
1588 cfg2 |= MSIEnable;
1589 msi = RTL_FEATURE_MSI;
1590 }
1591 }
1592 RTL_W8(Config2, cfg2);
1593 return msi;
1594}
1595
1596static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1597{
1598 if (tp->features & RTL_FEATURE_MSI) {
1599 pci_disable_msi(pdev);
1600 tp->features &= ~RTL_FEATURE_MSI;
1601 }
1602}
1603
1da177e4 1604static int __devinit
4ff96fa6 1605rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1606{
0e485150
FR		 1607 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1608 const unsigned int region = cfg->region;
1da177e4 1609 struct rtl8169_private *tp;
4ff96fa6
FR		 1610 struct net_device *dev;
1611 void __iomem *ioaddr;
07d3f51f
FR		 1612 unsigned int i;
1613 int rc;
1da177e4 1614
4ff96fa6
FR		 1615 if (netif_msg_drv(&debug)) {
1616 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1617 MODULENAME, RTL8169_VERSION);
1618 }
1da177e4 1619
1da177e4 1620 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1621 if (!dev) {
b57b7e5a 1622 if (netif_msg_drv(&debug))
9b91cf9d 1623 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1624 rc = -ENOMEM;
1625 goto out;
1da177e4
LT		 1626 }
1627
1da177e4
LT		 1628 SET_NETDEV_DEV(dev, &pdev->dev);
1629 tp = netdev_priv(dev);
c4028958 1630 tp->dev = dev;
b57b7e5a 1631 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1632
1633 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1634 rc = pci_enable_device(pdev);
b57b7e5a 1635 if (rc < 0) {
2e8a538d 1636 if (netif_msg_probe(tp))
9b91cf9d 1637 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1638 goto err_out_free_dev_1;
1da177e4
LT		 1639 }
1640
1641 rc = pci_set_mwi(pdev);
1642 if (rc < 0)
4ff96fa6 1643 goto err_out_disable_2;
1da177e4 1644
1da177e4 1645 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1646 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1647 if (netif_msg_probe(tp)) {
9b91cf9d 1648 dev_err(&pdev->dev,
bcf0bf90
FR		 1649 "region #%d not an MMIO resource, aborting\n",
1650 region);
4ff96fa6 1651 }
1da177e4 1652 rc = -ENODEV;
4ff96fa6 1653 goto err_out_mwi_3;
1da177e4 1654 }
4ff96fa6 1655
1da177e4 1656 /* check for weird/broken PCI region reporting */
bcf0bf90 1657 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1658 if (netif_msg_probe(tp)) {
9b91cf9d 1659 dev_err(&pdev->dev,
4ff96fa6
FR		 1660 "Invalid PCI region size(s), aborting\n");
1661 }
1da177e4 1662 rc = -ENODEV;
4ff96fa6 1663 goto err_out_mwi_3;
1da177e4
LT		 1664 }
1665
1666 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1667 if (rc < 0) {
2e8a538d 1668 if (netif_msg_probe(tp))
9b91cf9d 1669 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1670 goto err_out_mwi_3;
1da177e4
LT		 1671 }
1672
1673 tp->cp_cmd = PCIMulRW | RxChkSum;
1674
1675 if ((sizeof(dma_addr_t) > 4) &&
1676 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1677 tp->cp_cmd |= PCIDAC;
1678 dev->features |= NETIF_F_HIGHDMA;
1679 } else {
1680 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1681 if (rc < 0) {
4ff96fa6 1682 if (netif_msg_probe(tp)) {
9b91cf9d 1683 dev_err(&pdev->dev,
4ff96fa6
FR		 1684 "DMA configuration failed.\n");
1685 }
1686 goto err_out_free_res_4;
1da177e4
LT		 1687 }
1688 }
1689
1690 pci_set_master(pdev);
1691
1692 /* ioremap MMIO region */
bcf0bf90 1693 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1694 if (!ioaddr) {
b57b7e5a 1695 if (netif_msg_probe(tp))
9b91cf9d 1696 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1697 rc = -EIO;
4ff96fa6 1698 goto err_out_free_res_4;
1da177e4
LT		 1699 }
1700
1701 /* Unneeded ? Don't mess with Mrs. Murphy. */
1702 rtl8169_irq_mask_and_ack(ioaddr);
1703
1704 /* Soft reset the chip. */
1705 RTL_W8(ChipCmd, CmdReset);
1706
1707 /* Check that the chip has finished the reset. */
07d3f51f 1708 for (i = 0; i < 100; i++) {
1da177e4
LT		 1709 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1710 break;
b518fa8e 1711 msleep_interruptible(1);
1da177e4
LT		 1712 }
1713
1714 /* Identify chip attached to board */
1715 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1716
1717 rtl8169_print_mac_version(tp);
1da177e4
LT		 1718
1719 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1720 if (tp->mac_version == rtl_chip_info[i].mac_version)
1721 break;
1722 }
1723 if (i < 0) {
1724 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1725 if (netif_msg_probe(tp)) {
2e8a538d 1726 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1727 "unknown chip version, assuming %s\n",
1728 rtl_chip_info[0].name);
b57b7e5a 1729 }
1da177e4
LT		 1730 i++;
1731 }
1732 tp->chipset = i;
1733
5d06a99f
FR		 1734 RTL_W8(Cfg9346, Cfg9346_Unlock);
1735 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1736 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1737 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1738 RTL_W8(Cfg9346, Cfg9346_Lock);
1739
1da177e4
LT		 1740 if (RTL_R8(PHYstatus) & TBI_Enable) {
1741 tp->set_speed = rtl8169_set_speed_tbi;
1742 tp->get_settings = rtl8169_gset_tbi;
1743 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1744 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1745 tp->link_ok = rtl8169_tbi_link_ok;
1746
64e4bfb4 1747 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1748 } else {
1749 tp->set_speed = rtl8169_set_speed_xmii;
1750 tp->get_settings = rtl8169_gset_xmii;
1751 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1752 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1753 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1754
1755 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1756 }
1757
1758 /* Get MAC address. FIXME: read EEPROM */
1759 for (i = 0; i < MAC_ADDR_LEN; i++)
1760 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1761 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1762
1763 dev->open = rtl8169_open;
1764 dev->hard_start_xmit = rtl8169_start_xmit;
1765 dev->get_stats = rtl8169_get_stats;
1766 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1767 dev->stop = rtl8169_close;
1768 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1769 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1770 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1771 dev->irq = pdev->irq;
1772 dev->base_addr = (unsigned long) ioaddr;
1773 dev->change_mtu = rtl8169_change_mtu;
773d2021 1774 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1775
1776#ifdef CONFIG_R8169_NAPI
bea3348e 1777 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1778#endif
1779
1780#ifdef CONFIG_R8169_VLAN
1781 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1782 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1783#endif
1784
1785#ifdef CONFIG_NET_POLL_CONTROLLER
1786 dev->poll_controller = rtl8169_netpoll;
1787#endif
1788
1789 tp->intr_mask = 0xffff;
1790 tp->pci_dev = pdev;
1791 tp->mmio_addr = ioaddr;
0e485150
FR		 1792 tp->align = cfg->align;
1793 tp->hw_start = cfg->hw_start;
1794 tp->intr_event = cfg->intr_event;
1795 tp->napi_event = cfg->napi_event;
1da177e4 1796
2efa53f3
FR		 1797 init_timer(&tp->timer);
1798 tp->timer.data = (unsigned long) dev;
1799 tp->timer.function = rtl8169_phy_timer;
1800
1da177e4
LT		 1801 spin_lock_init(&tp->lock);
1802
1803 rc = register_netdev(dev);
4ff96fa6 1804 if (rc < 0)
fbac58fc 1805 goto err_out_msi_5;
1da177e4
LT		 1806
1807 pci_set_drvdata(pdev, dev);
1808
b57b7e5a 1809 if (netif_msg_probe(tp)) {
96b9709c
FR		 1810 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1811
b57b7e5a
SH		 1812 printk(KERN_INFO "%s: %s at 0x%lx, "
1813 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1814 "XID %08x IRQ %d\n",
b57b7e5a 1815 dev->name,
bcf0bf90 1816 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1817 dev->base_addr,
1818 dev->dev_addr[0], dev->dev_addr[1],
1819 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1820 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1821 }
1da177e4 1822
4ff96fa6 1823 rtl8169_init_phy(dev, tp);
1da177e4 1824
4ff96fa6
FR		 1825out:
1826 return rc;
1da177e4 1827
fbac58fc
FR		 1828err_out_msi_5:
1829 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1830 iounmap(ioaddr);
1831err_out_free_res_4:
1832 pci_release_regions(pdev);
1833err_out_mwi_3:
1834 pci_clear_mwi(pdev);
1835err_out_disable_2:
1836 pci_disable_device(pdev);
1837err_out_free_dev_1:
1838 free_netdev(dev);
1839 goto out;
1da177e4
LT		 1840}
1841
07d3f51f 1842static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1843{
1844 struct net_device *dev = pci_get_drvdata(pdev);
1845 struct rtl8169_private *tp = netdev_priv(dev);
1846
eb2a021c
FR		 1847 flush_scheduled_work();
1848
1da177e4 1849 unregister_netdev(dev);
fbac58fc 1850 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1851 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1852 pci_set_drvdata(pdev, NULL);
1853}
1854
1da177e4
LT		 1855static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1856 struct net_device *dev)
1857{
1858 unsigned int mtu = dev->mtu;
1859
1860 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1861}
1862
1863static int rtl8169_open(struct net_device *dev)
1864{
1865 struct rtl8169_private *tp = netdev_priv(dev);
1866 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1867 int retval = -ENOMEM;
1da177e4 1868
1da177e4 1869
99f252b0 1870 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1871
1872 /*
1873 * Rx and Tx desscriptors needs 256 bytes alignment.
1874 * pci_alloc_consistent provides more.
1875 */
1876 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1877 &tp->TxPhyAddr);
1878 if (!tp->TxDescArray)
99f252b0 1879 goto out;
1da177e4
LT		 1880
1881 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1882 &tp->RxPhyAddr);
1883 if (!tp->RxDescArray)
99f252b0 1884 goto err_free_tx_0;
1da177e4
LT		 1885
1886 retval = rtl8169_init_ring(dev);
1887 if (retval < 0)
99f252b0 1888 goto err_free_rx_1;
1da177e4 1889
c4028958 1890 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1891
99f252b0
FR		 1892 smp_mb();
1893
fbac58fc
FR		 1894 retval = request_irq(dev->irq, rtl8169_interrupt,
1895 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1896 dev->name, dev);
1897 if (retval < 0)
1898 goto err_release_ring_2;
1899
bea3348e
SH		 1900#ifdef CONFIG_R8169_NAPI
1901 napi_enable(&tp->napi);
1902#endif
1903
07ce4064 1904 rtl_hw_start(dev);
1da177e4
LT		 1905
1906 rtl8169_request_timer(dev);
1907
1908 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1909out:
1910 return retval;
1911
99f252b0
FR		 1912err_release_ring_2:
1913 rtl8169_rx_clear(tp);
1914err_free_rx_1:
1da177e4
LT		 1915 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1916 tp->RxPhyAddr);
99f252b0 1917err_free_tx_0:
1da177e4
LT		 1918 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1919 tp->TxPhyAddr);
1da177e4
LT		 1920 goto out;
1921}
1922
1923static void rtl8169_hw_reset(void __iomem *ioaddr)
1924{
1925 /* Disable interrupts */
1926 rtl8169_irq_mask_and_ack(ioaddr);
1927
1928 /* Reset the chipset */
1929 RTL_W8(ChipCmd, CmdReset);
1930
1931 /* PCI commit */
1932 RTL_R8(ChipCmd);
1933}
1934
7f796d83 1935static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1936{
1937 void __iomem *ioaddr = tp->mmio_addr;
1938 u32 cfg = rtl8169_rx_config;
1939
1940 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1941 RTL_W32(RxConfig, cfg);
1942
1943 /* Set DMA burst size and Interframe Gap Time */
1944 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1945 (InterFrameGap << TxInterFrameGapShift));
1946}
1947
07ce4064 1948static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1949{
1950 struct rtl8169_private *tp = netdev_priv(dev);
1951 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1952 unsigned int i;
1da177e4
LT		 1953
1954 /* Soft reset the chip. */
1955 RTL_W8(ChipCmd, CmdReset);
1956
1957 /* Check that the chip has finished the reset. */
07d3f51f 1958 for (i = 0; i < 100; i++) {
1da177e4
LT		 1959 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1960 break;
b518fa8e 1961 msleep_interruptible(1);
1da177e4
LT		 1962 }
1963
07ce4064
FR		 1964 tp->hw_start(dev);
1965
07ce4064
FR		 1966 netif_start_queue(dev);
1967}
1968
1969
7f796d83
FR		 1970static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1971 void __iomem *ioaddr)
1972{
1973 /*
1974 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1975 * register to be written before TxDescAddrLow to work.
1976 * Switching from MMIO to I/O access fixes the issue as well.
1977 */
1978 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1979 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1980 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1981 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1982}
1983
1984static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1985{
1986 u16 cmd;
1987
1988 cmd = RTL_R16(CPlusCmd);
1989 RTL_W16(CPlusCmd, cmd);
1990 return cmd;
1991}
1992
1993static void rtl_set_rx_max_size(void __iomem *ioaddr)
1994{
1995 /* Low hurts. Let's disable the filtering. */
1996 RTL_W16(RxMaxSize, 16383);
1997}
1998
6dccd16b
FR		 1999static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2000{
2001 struct {
2002 u32 mac_version;
2003 u32 clk;
2004 u32 val;
2005 } cfg2_info [] = {
2006 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2007 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2008 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2009 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2010 }, *p = cfg2_info;
2011 unsigned int i;
2012 u32 clk;
2013
2014 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2015 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
2016 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2017 RTL_W32(0x7c, p->val);
2018 break;
2019 }
2020 }
2021}
2022
07ce4064
FR		 2023static void rtl_hw_start_8169(struct net_device *dev)
2024{
2025 struct rtl8169_private *tp = netdev_priv(dev);
2026 void __iomem *ioaddr = tp->mmio_addr;
2027 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2028
9cb427b6
FR		 2029 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2030 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2031 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2032 }
2033
1da177e4 2034 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2035 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2036 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2037 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2038 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2039 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2040
1da177e4
LT		 2041 RTL_W8(EarlyTxThres, EarlyTxThld);
2042
7f796d83 2043 rtl_set_rx_max_size(ioaddr);
1da177e4 2044
c946b304
FR		 2045 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2046 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2047 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2048 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2049 rtl_set_rx_tx_config_registers(tp);
1da177e4 2050
7f796d83 2051 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2052
bcf0bf90
FR		 2053 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2054 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2055 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2056 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2057 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2058 }
2059
bcf0bf90
FR		 2060 RTL_W16(CPlusCmd, tp->cp_cmd);
2061
6dccd16b
FR		 2062 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2063
1da177e4
LT		 2064 /*
2065 * Undocumented corner. Supposedly:
2066 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2067 */
2068 RTL_W16(IntrMitigate, 0x0000);
2069
7f796d83 2070 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2071
c946b304
FR		 2072 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2073 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2074 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2075 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2076 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2077 rtl_set_rx_tx_config_registers(tp);
2078 }
2079
1da177e4 2080 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2081
2082 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2083 RTL_R8(IntrMask);
1da177e4
LT		 2084
2085 RTL_W32(RxMissed, 0);
2086
07ce4064 2087 rtl_set_rx_mode(dev);
1da177e4
LT		 2088
2089 /* no early-rx interrupts */
2090 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2091
2092 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2093 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2094}
1da177e4 2095
07ce4064
FR		 2096static void rtl_hw_start_8168(struct net_device *dev)
2097{
2dd99530
FR		 2098 struct rtl8169_private *tp = netdev_priv(dev);
2099 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2100 struct pci_dev *pdev = tp->pci_dev;
2101 u8 ctl;
2dd99530
FR		 2102
2103 RTL_W8(Cfg9346, Cfg9346_Unlock);
2104
2105 RTL_W8(EarlyTxThres, EarlyTxThld);
2106
2107 rtl_set_rx_max_size(ioaddr);
2108
0e485150
FR		 2109 rtl_set_rx_tx_config_registers(tp);
2110
2111 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2112
2113 RTL_W16(CPlusCmd, tp->cp_cmd);
2114
0e485150
FR		 2115 /* Tx performance tweak. */
2116 pci_read_config_byte(pdev, 0x69, &ctl);
2117 ctl = (ctl & ~0x70) | 0x50;
2118 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2119
0e485150 2120 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2121
0e485150
FR		 2122 /* Work around for RxFIFO overflow. */
2123 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2124 tp->intr_event |= RxFIFOOver | PCSTimeout;
2125 tp->intr_event &= ~RxOverflow;
2126 }
2127
2128 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2129
2130 RTL_W8(Cfg9346, Cfg9346_Lock);
2131
2132 RTL_R8(IntrMask);
2133
2134 RTL_W32(RxMissed, 0);
2135
2136 rtl_set_rx_mode(dev);
2137
0e485150
FR		 2138 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2139
2dd99530 2140 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2141
0e485150 2142 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2143}
1da177e4 2144
07ce4064
FR		 2145static void rtl_hw_start_8101(struct net_device *dev)
2146{
cdf1a608
FR		 2147 struct rtl8169_private *tp = netdev_priv(dev);
2148 void __iomem *ioaddr = tp->mmio_addr;
2149 struct pci_dev *pdev = tp->pci_dev;
2150
e3cf0cc0
FR		 2151 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2152 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2153 pci_write_config_word(pdev, 0x68, 0x00);
2154 pci_write_config_word(pdev, 0x69, 0x08);
2155 }
2156
2157 RTL_W8(Cfg9346, Cfg9346_Unlock);
2158
2159 RTL_W8(EarlyTxThres, EarlyTxThld);
2160
2161 rtl_set_rx_max_size(ioaddr);
2162
2163 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2164
2165 RTL_W16(CPlusCmd, tp->cp_cmd);
2166
2167 RTL_W16(IntrMitigate, 0x0000);
2168
2169 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2170
2171 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2172 rtl_set_rx_tx_config_registers(tp);
2173
2174 RTL_W8(Cfg9346, Cfg9346_Lock);
2175
2176 RTL_R8(IntrMask);
2177
2178 RTL_W32(RxMissed, 0);
2179
2180 rtl_set_rx_mode(dev);
2181
0e485150
FR		 2182 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2183
cdf1a608 2184 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2185
0e485150 2186 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2187}
2188
2189static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2190{
2191 struct rtl8169_private *tp = netdev_priv(dev);
2192 int ret = 0;
2193
2194 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2195 return -EINVAL;
2196
2197 dev->mtu = new_mtu;
2198
2199 if (!netif_running(dev))
2200 goto out;
2201
2202 rtl8169_down(dev);
2203
2204 rtl8169_set_rxbufsize(tp, dev);
2205
2206 ret = rtl8169_init_ring(dev);
2207 if (ret < 0)
2208 goto out;
2209
bea3348e
SH		 2210#ifdef CONFIG_R8169_NAPI
2211 napi_enable(&tp->napi);
2212#endif
1da177e4 2213
07ce4064 2214 rtl_hw_start(dev);
1da177e4
LT		 2215
2216 rtl8169_request_timer(dev);
2217
2218out:
2219 return ret;
2220}
2221
2222static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2223{
2224 desc->addr = 0x0badbadbadbadbadull;
2225 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2226}
2227
2228static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2229 struct sk_buff **sk_buff, struct RxDesc *desc)
2230{
2231 struct pci_dev *pdev = tp->pci_dev;
2232
2233 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2234 PCI_DMA_FROMDEVICE);
2235 dev_kfree_skb(*sk_buff);
2236 *sk_buff = NULL;
2237 rtl8169_make_unusable_by_asic(desc);
2238}
2239
2240static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2241{
2242 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2243
2244 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2245}
2246
2247static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2248 u32 rx_buf_sz)
2249{
2250 desc->addr = cpu_to_le64(mapping);
2251 wmb();
2252 rtl8169_mark_to_asic(desc, rx_buf_sz);
2253}
2254
15d31758
SH		 2255static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2256 struct net_device *dev,
2257 struct RxDesc *desc, int rx_buf_sz,
2258 unsigned int align)
1da177e4
LT		 2259{
2260 struct sk_buff *skb;
2261 dma_addr_t mapping;
e9f63f30 2262 unsigned int pad;
1da177e4 2263
e9f63f30
FR		 2264 pad = align ? align : NET_IP_ALIGN;
2265
2266 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2267 if (!skb)
2268 goto err_out;
2269
e9f63f30 2270 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2271
689be439 2272 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2273 PCI_DMA_FROMDEVICE);
2274
2275 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2276out:
15d31758 2277 return skb;
1da177e4
LT		 2278
2279err_out:
1da177e4
LT		 2280 rtl8169_make_unusable_by_asic(desc);
2281 goto out;
2282}
2283
2284static void rtl8169_rx_clear(struct rtl8169_private *tp)
2285{
07d3f51f 2286 unsigned int i;
1da177e4
LT		 2287
2288 for (i = 0; i < NUM_RX_DESC; i++) {
2289 if (tp->Rx_skbuff[i]) {
2290 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2291 tp->RxDescArray + i);
2292 }
2293 }
2294}
2295
2296static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2297 u32 start, u32 end)
2298{
2299 u32 cur;
5b0384f4 2300
4ae47c2d 2301 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2302 struct sk_buff *skb;
2303 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2304
4ae47c2d
FR		 2305 WARN_ON((s32)(end - cur) < 0);
2306
1da177e4
LT		 2307 if (tp->Rx_skbuff[i])
2308 continue;
bcf0bf90 2309
15d31758
SH		 2310 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2311 tp->RxDescArray + i,
2312 tp->rx_buf_sz, tp->align);
2313 if (!skb)
1da177e4 2314 break;
15d31758
SH		 2315
2316 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2317 }
2318 return cur - start;
2319}
2320
2321static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2322{
2323 desc->opts1 |= cpu_to_le32(RingEnd);
2324}
2325
2326static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2327{
2328 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2329}
2330
2331static int rtl8169_init_ring(struct net_device *dev)
2332{
2333 struct rtl8169_private *tp = netdev_priv(dev);
2334
2335 rtl8169_init_ring_indexes(tp);
2336
2337 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2338 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2339
2340 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2341 goto err_out;
2342
2343 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2344
2345 return 0;
2346
2347err_out:
2348 rtl8169_rx_clear(tp);
2349 return -ENOMEM;
2350}
2351
2352static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2353 struct TxDesc *desc)
2354{
2355 unsigned int len = tx_skb->len;
2356
2357 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2358 desc->opts1 = 0x00;
2359 desc->opts2 = 0x00;
2360 desc->addr = 0x00;
2361 tx_skb->len = 0;
2362}
2363
2364static void rtl8169_tx_clear(struct rtl8169_private *tp)
2365{
2366 unsigned int i;
2367
2368 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2369 unsigned int entry = i % NUM_TX_DESC;
2370 struct ring_info *tx_skb = tp->tx_skb + entry;
2371 unsigned int len = tx_skb->len;
2372
2373 if (len) {
2374 struct sk_buff *skb = tx_skb->skb;
2375
2376 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2377 tp->TxDescArray + entry);
2378 if (skb) {
2379 dev_kfree_skb(skb);
2380 tx_skb->skb = NULL;
2381 }
cebf8cc7 2382 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2383 }
2384 }
2385 tp->cur_tx = tp->dirty_tx = 0;
2386}
2387
c4028958 2388static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2389{
2390 struct rtl8169_private *tp = netdev_priv(dev);
2391
c4028958 2392 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2393 schedule_delayed_work(&tp->task, 4);
2394}
2395
2396static void rtl8169_wait_for_quiescence(struct net_device *dev)
2397{
2398 struct rtl8169_private *tp = netdev_priv(dev);
2399 void __iomem *ioaddr = tp->mmio_addr;
2400
2401 synchronize_irq(dev->irq);
2402
2403 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2404#ifdef CONFIG_R8169_NAPI
2405 napi_disable(&tp->napi);
2406#endif
1da177e4
LT		 2407
2408 rtl8169_irq_mask_and_ack(ioaddr);
2409
bea3348e
SH		 2410#ifdef CONFIG_R8169_NAPI
2411 napi_enable(&tp->napi);
2412#endif
1da177e4
LT		 2413}
2414
c4028958 2415static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2416{
c4028958
DH		 2417 struct rtl8169_private *tp =
2418 container_of(work, struct rtl8169_private, task.work);
2419 struct net_device *dev = tp->dev;
1da177e4
LT		 2420 int ret;
2421
eb2a021c
FR		 2422 rtnl_lock();
2423
2424 if (!netif_running(dev))
2425 goto out_unlock;
2426
2427 rtl8169_wait_for_quiescence(dev);
2428 rtl8169_close(dev);
1da177e4
LT		 2429
2430 ret = rtl8169_open(dev);
2431 if (unlikely(ret < 0)) {
07d3f51f 2432 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2433 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2434 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2435 }
2436 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2437 }
eb2a021c
FR		 2438
2439out_unlock:
2440 rtnl_unlock();
1da177e4
LT		 2441}
2442
c4028958 2443static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2444{
c4028958
DH		 2445 struct rtl8169_private *tp =
2446 container_of(work, struct rtl8169_private, task.work);
2447 struct net_device *dev = tp->dev;
1da177e4 2448
eb2a021c
FR		 2449 rtnl_lock();
2450
1da177e4 2451 if (!netif_running(dev))
eb2a021c 2452 goto out_unlock;
1da177e4
LT		 2453
2454 rtl8169_wait_for_quiescence(dev);
2455
bea3348e 2456 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2457 rtl8169_tx_clear(tp);
2458
2459 if (tp->dirty_rx == tp->cur_rx) {
2460 rtl8169_init_ring_indexes(tp);
07ce4064 2461 rtl_hw_start(dev);
1da177e4 2462 netif_wake_queue(dev);
cebf8cc7 2463 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2464 } else {
07d3f51f 2465 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2466 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2467 dev->name);
1da177e4
LT		 2468 }
2469 rtl8169_schedule_work(dev, rtl8169_reset_task);
2470 }
eb2a021c
FR		 2471
2472out_unlock:
2473 rtnl_unlock();
1da177e4
LT		 2474}
2475
2476static void rtl8169_tx_timeout(struct net_device *dev)
2477{
2478 struct rtl8169_private *tp = netdev_priv(dev);
2479
2480 rtl8169_hw_reset(tp->mmio_addr);
2481
2482 /* Let's wait a bit while any (async) irq lands on */
2483 rtl8169_schedule_work(dev, rtl8169_reset_task);
2484}
2485
2486static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2487 u32 opts1)
2488{
2489 struct skb_shared_info *info = skb_shinfo(skb);
2490 unsigned int cur_frag, entry;
a6343afb 2491 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2492
2493 entry = tp->cur_tx;
2494 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2495 skb_frag_t *frag = info->frags + cur_frag;
2496 dma_addr_t mapping;
2497 u32 status, len;
2498 void *addr;
2499
2500 entry = (entry + 1) % NUM_TX_DESC;
2501
2502 txd = tp->TxDescArray + entry;
2503 len = frag->size;
2504 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2505 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2506
2507 /* anti gcc 2.95.3 bugware (sic) */
2508 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2509
2510 txd->opts1 = cpu_to_le32(status);
2511 txd->addr = cpu_to_le64(mapping);
2512
2513 tp->tx_skb[entry].len = len;
2514 }
2515
2516 if (cur_frag) {
2517 tp->tx_skb[entry].skb = skb;
2518 txd->opts1 |= cpu_to_le32(LastFrag);
2519 }
2520
2521 return cur_frag;
2522}
2523
2524static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2525{
2526 if (dev->features & NETIF_F_TSO) {
7967168c 2527 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2528
2529 if (mss)
2530 return LargeSend | ((mss & MSSMask) << MSSShift);
2531 }
84fa7933 2532 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2533 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2534
2535 if (ip->protocol == IPPROTO_TCP)
2536 return IPCS | TCPCS;
2537 else if (ip->protocol == IPPROTO_UDP)
2538 return IPCS | UDPCS;
2539 WARN_ON(1); /* we need a WARN() */
2540 }
2541 return 0;
2542}
2543
2544static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2545{
2546 struct rtl8169_private *tp = netdev_priv(dev);
2547 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2548 struct TxDesc *txd = tp->TxDescArray + entry;
2549 void __iomem *ioaddr = tp->mmio_addr;
2550 dma_addr_t mapping;
2551 u32 status, len;
2552 u32 opts1;
188f4af0 2553 int ret = NETDEV_TX_OK;
5b0384f4 2554
1da177e4 2555 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2556 if (netif_msg_drv(tp)) {
2557 printk(KERN_ERR
2558 "%s: BUG! Tx Ring full when queue awake!\n",
2559 dev->name);
2560 }
1da177e4
LT		 2561 goto err_stop;
2562 }
2563
2564 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2565 goto err_stop;
2566
2567 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2568
2569 frags = rtl8169_xmit_frags(tp, skb, opts1);
2570 if (frags) {
2571 len = skb_headlen(skb);
2572 opts1 |= FirstFrag;
2573 } else {
2574 len = skb->len;
2575
2576 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2577 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2578 goto err_update_stats;
2579 len = ETH_ZLEN;
2580 }
2581
2582 opts1 |= FirstFrag | LastFrag;
2583 tp->tx_skb[entry].skb = skb;
2584 }
2585
2586 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2587
2588 tp->tx_skb[entry].len = len;
2589 txd->addr = cpu_to_le64(mapping);
2590 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2591
2592 wmb();
2593
2594 /* anti gcc 2.95.3 bugware (sic) */
2595 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2596 txd->opts1 = cpu_to_le32(status);
2597
2598 dev->trans_start = jiffies;
2599
2600 tp->cur_tx += frags + 1;
2601
2602 smp_wmb();
2603
275391a4 2604 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2605
2606 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2607 netif_stop_queue(dev);
2608 smp_rmb();
2609 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2610 netif_wake_queue(dev);
2611 }
2612
2613out:
2614 return ret;
2615
2616err_stop:
2617 netif_stop_queue(dev);
188f4af0 2618 ret = NETDEV_TX_BUSY;
1da177e4 2619err_update_stats:
cebf8cc7 2620 dev->stats.tx_dropped++;
1da177e4
LT		 2621 goto out;
2622}
2623
2624static void rtl8169_pcierr_interrupt(struct net_device *dev)
2625{
2626 struct rtl8169_private *tp = netdev_priv(dev);
2627 struct pci_dev *pdev = tp->pci_dev;
2628 void __iomem *ioaddr = tp->mmio_addr;
2629 u16 pci_status, pci_cmd;
2630
2631 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2632 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2633
b57b7e5a
SH		 2634 if (netif_msg_intr(tp)) {
2635 printk(KERN_ERR
2636 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2637 dev->name, pci_cmd, pci_status);
2638 }
1da177e4
LT		 2639
2640 /*
2641 * The recovery sequence below admits a very elaborated explanation:
2642 * - it seems to work;
d03902b8
FR		 2643 * - I did not see what else could be done;
2644 * - it makes iop3xx happy.
1da177e4
LT		 2645 *
2646 * Feel free to adjust to your needs.
2647 */
a27993f3 2648 if (pdev->broken_parity_status)
d03902b8
FR		 2649 pci_cmd &= ~PCI_COMMAND_PARITY;
2650 else
2651 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2652
2653 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2654
2655 pci_write_config_word(pdev, PCI_STATUS,
2656 pci_status & (PCI_STATUS_DETECTED_PARITY |
2657 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2658 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2659
2660 /* The infamous DAC f*ckup only happens at boot time */
2661 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2662 if (netif_msg_intr(tp))
2663 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2664 tp->cp_cmd &= ~PCIDAC;
2665 RTL_W16(CPlusCmd, tp->cp_cmd);
2666 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2667 }
2668
2669 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2670
2671 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2672}
2673
07d3f51f
FR		 2674static void rtl8169_tx_interrupt(struct net_device *dev,
2675 struct rtl8169_private *tp,
2676 void __iomem *ioaddr)
1da177e4
LT		 2677{
2678 unsigned int dirty_tx, tx_left;
2679
1da177e4
LT		 2680 dirty_tx = tp->dirty_tx;
2681 smp_rmb();
2682 tx_left = tp->cur_tx - dirty_tx;
2683
2684 while (tx_left > 0) {
2685 unsigned int entry = dirty_tx % NUM_TX_DESC;
2686 struct ring_info *tx_skb = tp->tx_skb + entry;
2687 u32 len = tx_skb->len;
2688 u32 status;
2689
2690 rmb();
2691 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2692 if (status & DescOwn)
2693 break;
2694
cebf8cc7
FR		 2695 dev->stats.tx_bytes += len;
2696 dev->stats.tx_packets++;
1da177e4
LT		 2697
2698 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2699
2700 if (status & LastFrag) {
2701 dev_kfree_skb_irq(tx_skb->skb);
2702 tx_skb->skb = NULL;
2703 }
2704 dirty_tx++;
2705 tx_left--;
2706 }
2707
2708 if (tp->dirty_tx != dirty_tx) {
2709 tp->dirty_tx = dirty_tx;
2710 smp_wmb();
2711 if (netif_queue_stopped(dev) &&
2712 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2713 netif_wake_queue(dev);
2714 }
d78ae2dc
FR		 2715 /*
2716 * 8168 hack: TxPoll requests are lost when the Tx packets are
2717 * too close. Let's kick an extra TxPoll request when a burst
2718 * of start_xmit activity is detected (if it is not detected,
2719 * it is slow enough). -- FR
2720 */
2721 smp_rmb();
2722 if (tp->cur_tx != dirty_tx)
2723 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2724 }
2725}
2726
126fa4b9
FR		 2727static inline int rtl8169_fragmented_frame(u32 status)
2728{
2729 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2730}
2731
1da177e4
LT		 2732static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2733{
2734 u32 opts1 = le32_to_cpu(desc->opts1);
2735 u32 status = opts1 & RxProtoMask;
2736
2737 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2738 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2739 ((status == RxProtoIP) && !(opts1 & IPFail)))
2740 skb->ip_summed = CHECKSUM_UNNECESSARY;
2741 else
2742 skb->ip_summed = CHECKSUM_NONE;
2743}
2744
07d3f51f
FR		 2745static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2746 struct rtl8169_private *tp, int pkt_size,
2747 dma_addr_t addr)
1da177e4 2748{
b449655f
SH		 2749 struct sk_buff *skb;
2750 bool done = false;
1da177e4 2751
b449655f
SH		 2752 if (pkt_size >= rx_copybreak)
2753 goto out;
1da177e4 2754
07d3f51f 2755 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2756 if (!skb)
2757 goto out;
2758
07d3f51f
FR		 2759 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2760 PCI_DMA_FROMDEVICE);
86402234 2761 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2762 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2763 *sk_buff = skb;
2764 done = true;
2765out:
2766 return done;
1da177e4
LT		 2767}
2768
07d3f51f
FR		 2769static int rtl8169_rx_interrupt(struct net_device *dev,
2770 struct rtl8169_private *tp,
bea3348e 2771 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2772{
2773 unsigned int cur_rx, rx_left;
2774 unsigned int delta, count;
2775
1da177e4
LT		 2776 cur_rx = tp->cur_rx;
2777 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2778 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2779
4dcb7d33 2780 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2781 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2782 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2783 u32 status;
2784
2785 rmb();
126fa4b9 2786 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2787
2788 if (status & DescOwn)
2789 break;
4dcb7d33 2790 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2791 if (netif_msg_rx_err(tp)) {
2792 printk(KERN_INFO
2793 "%s: Rx ERROR. status = %08x\n",
2794 dev->name, status);
2795 }
cebf8cc7 2796 dev->stats.rx_errors++;
1da177e4 2797 if (status & (RxRWT | RxRUNT))
cebf8cc7 2798 dev->stats.rx_length_errors++;
1da177e4 2799 if (status & RxCRC)
cebf8cc7 2800 dev->stats.rx_crc_errors++;
9dccf611
FR		 2801 if (status & RxFOVF) {
2802 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2803 dev->stats.rx_fifo_errors++;
9dccf611 2804 }
126fa4b9 2805 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2806 } else {
1da177e4 2807 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2808 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2809 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2810 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2811
126fa4b9
FR		 2812 /*
2813 * The driver does not support incoming fragmented
2814 * frames. They are seen as a symptom of over-mtu
2815 * sized frames.
2816 */
2817 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2818 dev->stats.rx_dropped++;
2819 dev->stats.rx_length_errors++;
126fa4b9 2820 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2821 continue;
126fa4b9
FR		 2822 }
2823
1da177e4 2824 rtl8169_rx_csum(skb, desc);
bcf0bf90 2825
07d3f51f 2826 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2827 pci_dma_sync_single_for_device(pdev, addr,
2828 pkt_size, PCI_DMA_FROMDEVICE);
2829 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2830 } else {
2831 pci_unmap_single(pdev, addr, pkt_size,
2832 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2833 tp->Rx_skbuff[entry] = NULL;
2834 }
2835
1da177e4
LT		 2836 skb_put(skb, pkt_size);
2837 skb->protocol = eth_type_trans(skb, dev);
2838
2839 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2840 rtl8169_rx_skb(skb);
2841
2842 dev->last_rx = jiffies;
cebf8cc7
FR		 2843 dev->stats.rx_bytes += pkt_size;
2844 dev->stats.rx_packets++;
1da177e4 2845 }
6dccd16b
FR		 2846
2847 /* Work around for AMD plateform. */
2848 if ((desc->opts2 & 0xfffe000) &&
2849 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2850 desc->opts2 = 0;
2851 cur_rx++;
2852 }
1da177e4
LT		 2853 }
2854
2855 count = cur_rx - tp->cur_rx;
2856 tp->cur_rx = cur_rx;
2857
2858 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2859 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2860 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2861 tp->dirty_rx += delta;
2862
2863 /*
2864 * FIXME: until there is periodic timer to try and refill the ring,
2865 * a temporary shortage may definitely kill the Rx process.
2866 * - disable the asic to try and avoid an overflow and kick it again
2867 * after refill ?
2868 * - how do others driver handle this condition (Uh oh...).
2869 */
b57b7e5a 2870 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2871 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2872
2873 return count;
2874}
2875
07d3f51f 2876static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2877{
07d3f51f 2878 struct net_device *dev = dev_instance;
1da177e4
LT		 2879 struct rtl8169_private *tp = netdev_priv(dev);
2880 int boguscnt = max_interrupt_work;
2881 void __iomem *ioaddr = tp->mmio_addr;
2882 int status;
2883 int handled = 0;
2884
2885 do {
2886 status = RTL_R16(IntrStatus);
2887
2888 /* hotplug/major error/no more work/shared irq */
2889 if ((status == 0xFFFF) || !status)
2890 break;
2891
2892 handled = 1;
2893
2894 if (unlikely(!netif_running(dev))) {
2895 rtl8169_asic_down(ioaddr);
2896 goto out;
2897 }
2898
2899 status &= tp->intr_mask;
2900 RTL_W16(IntrStatus,
2901 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2902
0e485150
FR		 2903 if (!(status & tp->intr_event))
2904 break;
2905
2906 /* Work around for rx fifo overflow */
2907 if (unlikely(status & RxFIFOOver) &&
2908 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2909 netif_stop_queue(dev);
2910 rtl8169_tx_timeout(dev);
1da177e4 2911 break;
0e485150 2912 }
1da177e4
LT		 2913
2914 if (unlikely(status & SYSErr)) {
2915 rtl8169_pcierr_interrupt(dev);
2916 break;
2917 }
2918
2919 if (status & LinkChg)
2920 rtl8169_check_link_status(dev, tp, ioaddr);
2921
2922#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2923 if (status & tp->napi_event) {
2924 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2925 tp->intr_mask = ~tp->napi_event;
2926
bea3348e
SH		 2927 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2928 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2929 else if (netif_msg_intr(tp)) {
2930 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2931 dev->name, status);
2932 }
1da177e4
LT		 2933 }
2934 break;
2935#else
2936 /* Rx interrupt */
07d3f51f 2937 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2938 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2939
1da177e4
LT		 2940 /* Tx interrupt */
2941 if (status & (TxOK | TxErr))
2942 rtl8169_tx_interrupt(dev, tp, ioaddr);
2943#endif
2944
2945 boguscnt--;
2946 } while (boguscnt > 0);
2947
2948 if (boguscnt <= 0) {
7c8b2eb4 2949 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2950 printk(KERN_WARNING
2951 "%s: Too much work at interrupt!\n", dev->name);
2952 }
1da177e4
LT		 2953 /* Clear all interrupt sources. */
2954 RTL_W16(IntrStatus, 0xffff);
2955 }
2956out:
2957 return IRQ_RETVAL(handled);
2958}
2959
2960#ifdef CONFIG_R8169_NAPI
bea3348e 2961static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2962{
bea3348e
SH		 2963 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2964 struct net_device *dev = tp->dev;
1da177e4 2965 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2966 int work_done;
1da177e4 2967
bea3348e 2968 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2969 rtl8169_tx_interrupt(dev, tp, ioaddr);
2970
bea3348e
SH		 2971 if (work_done < budget) {
2972 netif_rx_complete(dev, napi);
1da177e4
LT		 2973 tp->intr_mask = 0xffff;
2974 /*
2975 * 20040426: the barrier is not strictly required but the
2976 * behavior of the irq handler could be less predictable
2977 * without it. Btw, the lack of flush for the posted pci
2978 * write is safe - FR
2979 */
2980 smp_wmb();
0e485150 2981 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2982 }
2983
bea3348e 2984 return work_done;
1da177e4
LT		 2985}
2986#endif
2987
2988static void rtl8169_down(struct net_device *dev)
2989{
2990 struct rtl8169_private *tp = netdev_priv(dev);
2991 void __iomem *ioaddr = tp->mmio_addr;
2992 unsigned int poll_locked = 0;
733b736c 2993 unsigned int intrmask;
1da177e4
LT		 2994
2995 rtl8169_delete_timer(dev);
2996
2997 netif_stop_queue(dev);
2998
1da177e4
LT		 2999core_down:
3000 spin_lock_irq(&tp->lock);
3001
3002 rtl8169_asic_down(ioaddr);
3003
3004 /* Update the error counts. */
cebf8cc7 3005 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3006 RTL_W32(RxMissed, 0);
3007
3008 spin_unlock_irq(&tp->lock);
3009
3010 synchronize_irq(dev->irq);
3011
3012 if (!poll_locked) {
bea3348e 3013 napi_disable(&tp->napi);
1da177e4
LT		 3014 poll_locked++;
3015 }
3016
3017 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3018 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3019
3020 /*
3021 * And now for the 50k$ question: are IRQ disabled or not ?
3022 *
3023 * Two paths lead here:
3024 * 1) dev->close
3025 * -> netif_running() is available to sync the current code and the
3026 * IRQ handler. See rtl8169_interrupt for details.
3027 * 2) dev->change_mtu
3028 * -> rtl8169_poll can not be issued again and re-enable the
3029 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3030 *
3031 * No loop if hotpluged or major error (0xffff).
1da177e4 3032 */
733b736c
AP		 3033 intrmask = RTL_R16(IntrMask);
3034 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3035 goto core_down;
3036
3037 rtl8169_tx_clear(tp);
3038
3039 rtl8169_rx_clear(tp);
3040}
3041
3042static int rtl8169_close(struct net_device *dev)
3043{
3044 struct rtl8169_private *tp = netdev_priv(dev);
3045 struct pci_dev *pdev = tp->pci_dev;
3046
3047 rtl8169_down(dev);
3048
3049 free_irq(dev->irq, dev);
3050
1da177e4
LT		 3051 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3052 tp->RxPhyAddr);
3053 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3054 tp->TxPhyAddr);
3055 tp->TxDescArray = NULL;
3056 tp->RxDescArray = NULL;
3057
3058 return 0;
3059}
3060
07ce4064 3061static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3062{
3063 struct rtl8169_private *tp = netdev_priv(dev);
3064 void __iomem *ioaddr = tp->mmio_addr;
3065 unsigned long flags;
3066 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3067 int rx_mode;
1da177e4
LT		 3068 u32 tmp = 0;
3069
3070 if (dev->flags & IFF_PROMISC) {
3071 /* Unconditionally log net taps. */
b57b7e5a
SH		 3072 if (netif_msg_link(tp)) {
3073 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3074 dev->name);
3075 }
1da177e4
LT		 3076 rx_mode =
3077 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3078 AcceptAllPhys;
3079 mc_filter[1] = mc_filter[0] = 0xffffffff;
3080 } else if ((dev->mc_count > multicast_filter_limit)
3081 || (dev->flags & IFF_ALLMULTI)) {
3082 /* Too many to filter perfectly -- accept all multicasts. */
3083 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3084 mc_filter[1] = mc_filter[0] = 0xffffffff;
3085 } else {
3086 struct dev_mc_list *mclist;
07d3f51f
FR		 3087 unsigned int i;
3088
1da177e4
LT		 3089 rx_mode = AcceptBroadcast | AcceptMyPhys;
3090 mc_filter[1] = mc_filter[0] = 0;
3091 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3092 i++, mclist = mclist->next) {
3093 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3094 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3095 rx_mode |= AcceptMulticast;
3096 }
3097 }
3098
3099 spin_lock_irqsave(&tp->lock, flags);
3100
3101 tmp = rtl8169_rx_config | rx_mode |
3102 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3103
bcf0bf90
FR		 3104 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3105 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3106 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3107 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 3108 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3109 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3110 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
bcf0bf90
FR		 3111 mc_filter[0] = 0xffffffff;
3112 mc_filter[1] = 0xffffffff;
3113 }
3114
1da177e4
LT		 3115 RTL_W32(MAR0 + 0, mc_filter[0]);
3116 RTL_W32(MAR0 + 4, mc_filter[1]);
3117
57a9f236
FR		 3118 RTL_W32(RxConfig, tmp);
3119
1da177e4
LT		 3120 spin_unlock_irqrestore(&tp->lock, flags);
3121}
3122
3123/**
3124 * rtl8169_get_stats - Get rtl8169 read/write statistics
3125 * @dev: The Ethernet Device to get statistics for
3126 *
3127 * Get TX/RX statistics for rtl8169
3128 */
3129static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3130{
3131 struct rtl8169_private *tp = netdev_priv(dev);
3132 void __iomem *ioaddr = tp->mmio_addr;
3133 unsigned long flags;
3134
3135 if (netif_running(dev)) {
3136 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3137 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3138 RTL_W32(RxMissed, 0);
3139 spin_unlock_irqrestore(&tp->lock, flags);
3140 }
5b0384f4 3141
cebf8cc7 3142 return &dev->stats;
1da177e4
LT		 3143}
3144
5d06a99f
FR		 3145#ifdef CONFIG_PM
3146
3147static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3148{
3149 struct net_device *dev = pci_get_drvdata(pdev);
3150 struct rtl8169_private *tp = netdev_priv(dev);
3151 void __iomem *ioaddr = tp->mmio_addr;
3152
3153 if (!netif_running(dev))
1371fa6d 3154 goto out_pci_suspend;
5d06a99f
FR		 3155
3156 netif_device_detach(dev);
3157 netif_stop_queue(dev);
3158
3159 spin_lock_irq(&tp->lock);
3160
3161 rtl8169_asic_down(ioaddr);
3162
cebf8cc7 3163 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3164 RTL_W32(RxMissed, 0);
3165
3166 spin_unlock_irq(&tp->lock);
3167
1371fa6d 3168out_pci_suspend:
5d06a99f 3169 pci_save_state(pdev);
f23e7fda
FR		 3170 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3171 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3172 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3173
5d06a99f
FR		 3174 return 0;
3175}
3176
3177static int rtl8169_resume(struct pci_dev *pdev)
3178{
3179 struct net_device *dev = pci_get_drvdata(pdev);
3180
1371fa6d
FR		 3181 pci_set_power_state(pdev, PCI_D0);
3182 pci_restore_state(pdev);
3183 pci_enable_wake(pdev, PCI_D0, 0);
3184
5d06a99f
FR		 3185 if (!netif_running(dev))
3186 goto out;
3187
3188 netif_device_attach(dev);
3189
5d06a99f
FR		 3190 rtl8169_schedule_work(dev, rtl8169_reset_task);
3191out:
3192 return 0;
3193}
3194
3195#endif /* CONFIG_PM */
3196
1da177e4
LT		 3197static struct pci_driver rtl8169_pci_driver = {
3198 .name = MODULENAME,
3199 .id_table = rtl8169_pci_tbl,
3200 .probe = rtl8169_init_one,
3201 .remove = __devexit_p(rtl8169_remove_one),
3202#ifdef CONFIG_PM
3203 .suspend = rtl8169_suspend,
3204 .resume = rtl8169_resume,
3205#endif
3206};
3207
07d3f51f 3208static int __init rtl8169_init_module(void)
1da177e4 3209{
29917620 3210 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3211}
3212
07d3f51f 3213static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3214{
3215 pci_unregister_driver(&rtl8169_pci_driver);
3216}
3217
3218module_init(rtl8169_init_module);
3219module_exit(rtl8169_cleanup_module);
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